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Merge tag 'tag-for-linus-3.5' of git://git.linaro.org/people/sumitsemwal/linux-dma-buf
[deliverable/linux.git] / drivers / net / ethernet / atheros / atlx / atl1.c
1 /*
2 * Copyright(c) 2005 - 2006 Attansic Corporation. All rights reserved.
3 * Copyright(c) 2006 - 2007 Chris Snook <csnook@redhat.com>
4 * Copyright(c) 2006 - 2008 Jay Cliburn <jcliburn@gmail.com>
5 *
6 * Derived from Intel e1000 driver
7 * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the Free
11 * Software Foundation; either version 2 of the License, or (at your option)
12 * any later version.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc., 59
21 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 *
23 * The full GNU General Public License is included in this distribution in the
24 * file called COPYING.
25 *
26 * Contact Information:
27 * Xiong Huang <xiong.huang@atheros.com>
28 * Jie Yang <jie.yang@atheros.com>
29 * Chris Snook <csnook@redhat.com>
30 * Jay Cliburn <jcliburn@gmail.com>
31 *
32 * This version is adapted from the Attansic reference driver.
33 *
34 * TODO:
35 * Add more ethtool functions.
36 * Fix abstruse irq enable/disable condition described here:
37 * http://marc.theaimsgroup.com/?l=linux-netdev&m=116398508500553&w=2
38 *
39 * NEEDS TESTING:
40 * VLAN
41 * multicast
42 * promiscuous mode
43 * interrupt coalescing
44 * SMP torture testing
45 */
46
47 #include <linux/atomic.h>
48 #include <asm/byteorder.h>
49
50 #include <linux/compiler.h>
51 #include <linux/crc32.h>
52 #include <linux/delay.h>
53 #include <linux/dma-mapping.h>
54 #include <linux/etherdevice.h>
55 #include <linux/hardirq.h>
56 #include <linux/if_ether.h>
57 #include <linux/if_vlan.h>
58 #include <linux/in.h>
59 #include <linux/interrupt.h>
60 #include <linux/ip.h>
61 #include <linux/irqflags.h>
62 #include <linux/irqreturn.h>
63 #include <linux/jiffies.h>
64 #include <linux/mii.h>
65 #include <linux/module.h>
66 #include <linux/moduleparam.h>
67 #include <linux/net.h>
68 #include <linux/netdevice.h>
69 #include <linux/pci.h>
70 #include <linux/pci_ids.h>
71 #include <linux/pm.h>
72 #include <linux/skbuff.h>
73 #include <linux/slab.h>
74 #include <linux/spinlock.h>
75 #include <linux/string.h>
76 #include <linux/tcp.h>
77 #include <linux/timer.h>
78 #include <linux/types.h>
79 #include <linux/workqueue.h>
80
81 #include <net/checksum.h>
82
83 #include "atl1.h"
84
85 #define ATLX_DRIVER_VERSION "2.1.3"
86 MODULE_AUTHOR("Xiong Huang <xiong.huang@atheros.com>, "
87 "Chris Snook <csnook@redhat.com>, "
88 "Jay Cliburn <jcliburn@gmail.com>");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(ATLX_DRIVER_VERSION);
91
92 /* Temporary hack for merging atl1 and atl2 */
93 #include "atlx.c"
94
95 static const struct ethtool_ops atl1_ethtool_ops;
96
97 /*
98 * This is the only thing that needs to be changed to adjust the
99 * maximum number of ports that the driver can manage.
100 */
101 #define ATL1_MAX_NIC 4
102
103 #define OPTION_UNSET -1
104 #define OPTION_DISABLED 0
105 #define OPTION_ENABLED 1
106
107 #define ATL1_PARAM_INIT { [0 ... ATL1_MAX_NIC] = OPTION_UNSET }
108
109 /*
110 * Interrupt Moderate Timer in units of 2 us
111 *
112 * Valid Range: 10-65535
113 *
114 * Default Value: 100 (200us)
115 */
116 static int __devinitdata int_mod_timer[ATL1_MAX_NIC+1] = ATL1_PARAM_INIT;
117 static unsigned int num_int_mod_timer;
118 module_param_array_named(int_mod_timer, int_mod_timer, int,
119 &num_int_mod_timer, 0);
120 MODULE_PARM_DESC(int_mod_timer, "Interrupt moderator timer");
121
122 #define DEFAULT_INT_MOD_CNT 100 /* 200us */
123 #define MAX_INT_MOD_CNT 65000
124 #define MIN_INT_MOD_CNT 50
125
126 struct atl1_option {
127 enum { enable_option, range_option, list_option } type;
128 char *name;
129 char *err;
130 int def;
131 union {
132 struct { /* range_option info */
133 int min;
134 int max;
135 } r;
136 struct { /* list_option info */
137 int nr;
138 struct atl1_opt_list {
139 int i;
140 char *str;
141 } *p;
142 } l;
143 } arg;
144 };
145
146 static int __devinit atl1_validate_option(int *value, struct atl1_option *opt,
147 struct pci_dev *pdev)
148 {
149 if (*value == OPTION_UNSET) {
150 *value = opt->def;
151 return 0;
152 }
153
154 switch (opt->type) {
155 case enable_option:
156 switch (*value) {
157 case OPTION_ENABLED:
158 dev_info(&pdev->dev, "%s enabled\n", opt->name);
159 return 0;
160 case OPTION_DISABLED:
161 dev_info(&pdev->dev, "%s disabled\n", opt->name);
162 return 0;
163 }
164 break;
165 case range_option:
166 if (*value >= opt->arg.r.min && *value <= opt->arg.r.max) {
167 dev_info(&pdev->dev, "%s set to %i\n", opt->name,
168 *value);
169 return 0;
170 }
171 break;
172 case list_option:{
173 int i;
174 struct atl1_opt_list *ent;
175
176 for (i = 0; i < opt->arg.l.nr; i++) {
177 ent = &opt->arg.l.p[i];
178 if (*value == ent->i) {
179 if (ent->str[0] != '\0')
180 dev_info(&pdev->dev, "%s\n",
181 ent->str);
182 return 0;
183 }
184 }
185 }
186 break;
187
188 default:
189 break;
190 }
191
192 dev_info(&pdev->dev, "invalid %s specified (%i) %s\n",
193 opt->name, *value, opt->err);
194 *value = opt->def;
195 return -1;
196 }
197
198 /*
199 * atl1_check_options - Range Checking for Command Line Parameters
200 * @adapter: board private structure
201 *
202 * This routine checks all command line parameters for valid user
203 * input. If an invalid value is given, or if no user specified
204 * value exists, a default value is used. The final value is stored
205 * in a variable in the adapter structure.
206 */
207 static void __devinit atl1_check_options(struct atl1_adapter *adapter)
208 {
209 struct pci_dev *pdev = adapter->pdev;
210 int bd = adapter->bd_number;
211 if (bd >= ATL1_MAX_NIC) {
212 dev_notice(&pdev->dev, "no configuration for board#%i\n", bd);
213 dev_notice(&pdev->dev, "using defaults for all values\n");
214 }
215 { /* Interrupt Moderate Timer */
216 struct atl1_option opt = {
217 .type = range_option,
218 .name = "Interrupt Moderator Timer",
219 .err = "using default of "
220 __MODULE_STRING(DEFAULT_INT_MOD_CNT),
221 .def = DEFAULT_INT_MOD_CNT,
222 .arg = {.r = {.min = MIN_INT_MOD_CNT,
223 .max = MAX_INT_MOD_CNT} }
224 };
225 int val;
226 if (num_int_mod_timer > bd) {
227 val = int_mod_timer[bd];
228 atl1_validate_option(&val, &opt, pdev);
229 adapter->imt = (u16) val;
230 } else
231 adapter->imt = (u16) (opt.def);
232 }
233 }
234
235 /*
236 * atl1_pci_tbl - PCI Device ID Table
237 */
238 static DEFINE_PCI_DEVICE_TABLE(atl1_pci_tbl) = {
239 {PCI_DEVICE(PCI_VENDOR_ID_ATTANSIC, PCI_DEVICE_ID_ATTANSIC_L1)},
240 /* required last entry */
241 {0,}
242 };
243 MODULE_DEVICE_TABLE(pci, atl1_pci_tbl);
244
245 static const u32 atl1_default_msg = NETIF_MSG_DRV | NETIF_MSG_PROBE |
246 NETIF_MSG_LINK | NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP;
247
248 static int debug = -1;
249 module_param(debug, int, 0);
250 MODULE_PARM_DESC(debug, "Message level (0=none,...,16=all)");
251
252 /*
253 * Reset the transmit and receive units; mask and clear all interrupts.
254 * hw - Struct containing variables accessed by shared code
255 * return : 0 or idle status (if error)
256 */
257 static s32 atl1_reset_hw(struct atl1_hw *hw)
258 {
259 struct pci_dev *pdev = hw->back->pdev;
260 struct atl1_adapter *adapter = hw->back;
261 u32 icr;
262 int i;
263
264 /*
265 * Clear Interrupt mask to stop board from generating
266 * interrupts & Clear any pending interrupt events
267 */
268 /*
269 * atlx_irq_disable(adapter);
270 * iowrite32(0xffffffff, hw->hw_addr + REG_ISR);
271 */
272
273 /*
274 * Issue Soft Reset to the MAC. This will reset the chip's
275 * transmit, receive, DMA. It will not effect
276 * the current PCI configuration. The global reset bit is self-
277 * clearing, and should clear within a microsecond.
278 */
279 iowrite32(MASTER_CTRL_SOFT_RST, hw->hw_addr + REG_MASTER_CTRL);
280 ioread32(hw->hw_addr + REG_MASTER_CTRL);
281
282 iowrite16(1, hw->hw_addr + REG_PHY_ENABLE);
283 ioread16(hw->hw_addr + REG_PHY_ENABLE);
284
285 /* delay about 1ms */
286 msleep(1);
287
288 /* Wait at least 10ms for All module to be Idle */
289 for (i = 0; i < 10; i++) {
290 icr = ioread32(hw->hw_addr + REG_IDLE_STATUS);
291 if (!icr)
292 break;
293 /* delay 1 ms */
294 msleep(1);
295 /* FIXME: still the right way to do this? */
296 cpu_relax();
297 }
298
299 if (icr) {
300 if (netif_msg_hw(adapter))
301 dev_dbg(&pdev->dev, "ICR = 0x%x\n", icr);
302 return icr;
303 }
304
305 return 0;
306 }
307
308 /* function about EEPROM
309 *
310 * check_eeprom_exist
311 * return 0 if eeprom exist
312 */
313 static int atl1_check_eeprom_exist(struct atl1_hw *hw)
314 {
315 u32 value;
316 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
317 if (value & SPI_FLASH_CTRL_EN_VPD) {
318 value &= ~SPI_FLASH_CTRL_EN_VPD;
319 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
320 }
321
322 value = ioread16(hw->hw_addr + REG_PCIE_CAP_LIST);
323 return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
324 }
325
326 static bool atl1_read_eeprom(struct atl1_hw *hw, u32 offset, u32 *p_value)
327 {
328 int i;
329 u32 control;
330
331 if (offset & 3)
332 /* address do not align */
333 return false;
334
335 iowrite32(0, hw->hw_addr + REG_VPD_DATA);
336 control = (offset & VPD_CAP_VPD_ADDR_MASK) << VPD_CAP_VPD_ADDR_SHIFT;
337 iowrite32(control, hw->hw_addr + REG_VPD_CAP);
338 ioread32(hw->hw_addr + REG_VPD_CAP);
339
340 for (i = 0; i < 10; i++) {
341 msleep(2);
342 control = ioread32(hw->hw_addr + REG_VPD_CAP);
343 if (control & VPD_CAP_VPD_FLAG)
344 break;
345 }
346 if (control & VPD_CAP_VPD_FLAG) {
347 *p_value = ioread32(hw->hw_addr + REG_VPD_DATA);
348 return true;
349 }
350 /* timeout */
351 return false;
352 }
353
354 /*
355 * Reads the value from a PHY register
356 * hw - Struct containing variables accessed by shared code
357 * reg_addr - address of the PHY register to read
358 */
359 static s32 atl1_read_phy_reg(struct atl1_hw *hw, u16 reg_addr, u16 *phy_data)
360 {
361 u32 val;
362 int i;
363
364 val = ((u32) (reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT |
365 MDIO_START | MDIO_SUP_PREAMBLE | MDIO_RW | MDIO_CLK_25_4 <<
366 MDIO_CLK_SEL_SHIFT;
367 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
368 ioread32(hw->hw_addr + REG_MDIO_CTRL);
369
370 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
371 udelay(2);
372 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
373 if (!(val & (MDIO_START | MDIO_BUSY)))
374 break;
375 }
376 if (!(val & (MDIO_START | MDIO_BUSY))) {
377 *phy_data = (u16) val;
378 return 0;
379 }
380 return ATLX_ERR_PHY;
381 }
382
383 #define CUSTOM_SPI_CS_SETUP 2
384 #define CUSTOM_SPI_CLK_HI 2
385 #define CUSTOM_SPI_CLK_LO 2
386 #define CUSTOM_SPI_CS_HOLD 2
387 #define CUSTOM_SPI_CS_HI 3
388
389 static bool atl1_spi_read(struct atl1_hw *hw, u32 addr, u32 *buf)
390 {
391 int i;
392 u32 value;
393
394 iowrite32(0, hw->hw_addr + REG_SPI_DATA);
395 iowrite32(addr, hw->hw_addr + REG_SPI_ADDR);
396
397 value = SPI_FLASH_CTRL_WAIT_READY |
398 (CUSTOM_SPI_CS_SETUP & SPI_FLASH_CTRL_CS_SETUP_MASK) <<
399 SPI_FLASH_CTRL_CS_SETUP_SHIFT | (CUSTOM_SPI_CLK_HI &
400 SPI_FLASH_CTRL_CLK_HI_MASK) <<
401 SPI_FLASH_CTRL_CLK_HI_SHIFT | (CUSTOM_SPI_CLK_LO &
402 SPI_FLASH_CTRL_CLK_LO_MASK) <<
403 SPI_FLASH_CTRL_CLK_LO_SHIFT | (CUSTOM_SPI_CS_HOLD &
404 SPI_FLASH_CTRL_CS_HOLD_MASK) <<
405 SPI_FLASH_CTRL_CS_HOLD_SHIFT | (CUSTOM_SPI_CS_HI &
406 SPI_FLASH_CTRL_CS_HI_MASK) <<
407 SPI_FLASH_CTRL_CS_HI_SHIFT | (1 & SPI_FLASH_CTRL_INS_MASK) <<
408 SPI_FLASH_CTRL_INS_SHIFT;
409
410 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
411
412 value |= SPI_FLASH_CTRL_START;
413 iowrite32(value, hw->hw_addr + REG_SPI_FLASH_CTRL);
414 ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
415
416 for (i = 0; i < 10; i++) {
417 msleep(1);
418 value = ioread32(hw->hw_addr + REG_SPI_FLASH_CTRL);
419 if (!(value & SPI_FLASH_CTRL_START))
420 break;
421 }
422
423 if (value & SPI_FLASH_CTRL_START)
424 return false;
425
426 *buf = ioread32(hw->hw_addr + REG_SPI_DATA);
427
428 return true;
429 }
430
431 /*
432 * get_permanent_address
433 * return 0 if get valid mac address,
434 */
435 static int atl1_get_permanent_address(struct atl1_hw *hw)
436 {
437 u32 addr[2];
438 u32 i, control;
439 u16 reg;
440 u8 eth_addr[ETH_ALEN];
441 bool key_valid;
442
443 if (is_valid_ether_addr(hw->perm_mac_addr))
444 return 0;
445
446 /* init */
447 addr[0] = addr[1] = 0;
448
449 if (!atl1_check_eeprom_exist(hw)) {
450 reg = 0;
451 key_valid = false;
452 /* Read out all EEPROM content */
453 i = 0;
454 while (1) {
455 if (atl1_read_eeprom(hw, i + 0x100, &control)) {
456 if (key_valid) {
457 if (reg == REG_MAC_STA_ADDR)
458 addr[0] = control;
459 else if (reg == (REG_MAC_STA_ADDR + 4))
460 addr[1] = control;
461 key_valid = false;
462 } else if ((control & 0xff) == 0x5A) {
463 key_valid = true;
464 reg = (u16) (control >> 16);
465 } else
466 break;
467 } else
468 /* read error */
469 break;
470 i += 4;
471 }
472
473 *(u32 *) &eth_addr[2] = swab32(addr[0]);
474 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
475 if (is_valid_ether_addr(eth_addr)) {
476 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
477 return 0;
478 }
479 }
480
481 /* see if SPI FLAGS exist ? */
482 addr[0] = addr[1] = 0;
483 reg = 0;
484 key_valid = false;
485 i = 0;
486 while (1) {
487 if (atl1_spi_read(hw, i + 0x1f000, &control)) {
488 if (key_valid) {
489 if (reg == REG_MAC_STA_ADDR)
490 addr[0] = control;
491 else if (reg == (REG_MAC_STA_ADDR + 4))
492 addr[1] = control;
493 key_valid = false;
494 } else if ((control & 0xff) == 0x5A) {
495 key_valid = true;
496 reg = (u16) (control >> 16);
497 } else
498 /* data end */
499 break;
500 } else
501 /* read error */
502 break;
503 i += 4;
504 }
505
506 *(u32 *) &eth_addr[2] = swab32(addr[0]);
507 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
508 if (is_valid_ether_addr(eth_addr)) {
509 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
510 return 0;
511 }
512
513 /*
514 * On some motherboards, the MAC address is written by the
515 * BIOS directly to the MAC register during POST, and is
516 * not stored in eeprom. If all else thus far has failed
517 * to fetch the permanent MAC address, try reading it directly.
518 */
519 addr[0] = ioread32(hw->hw_addr + REG_MAC_STA_ADDR);
520 addr[1] = ioread16(hw->hw_addr + (REG_MAC_STA_ADDR + 4));
521 *(u32 *) &eth_addr[2] = swab32(addr[0]);
522 *(u16 *) &eth_addr[0] = swab16(*(u16 *) &addr[1]);
523 if (is_valid_ether_addr(eth_addr)) {
524 memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
525 return 0;
526 }
527
528 return 1;
529 }
530
531 /*
532 * Reads the adapter's MAC address from the EEPROM
533 * hw - Struct containing variables accessed by shared code
534 */
535 static s32 atl1_read_mac_addr(struct atl1_hw *hw)
536 {
537 s32 ret = 0;
538 u16 i;
539
540 if (atl1_get_permanent_address(hw)) {
541 random_ether_addr(hw->perm_mac_addr);
542 ret = 1;
543 }
544
545 for (i = 0; i < ETH_ALEN; i++)
546 hw->mac_addr[i] = hw->perm_mac_addr[i];
547 return ret;
548 }
549
550 /*
551 * Hashes an address to determine its location in the multicast table
552 * hw - Struct containing variables accessed by shared code
553 * mc_addr - the multicast address to hash
554 *
555 * atl1_hash_mc_addr
556 * purpose
557 * set hash value for a multicast address
558 * hash calcu processing :
559 * 1. calcu 32bit CRC for multicast address
560 * 2. reverse crc with MSB to LSB
561 */
562 static u32 atl1_hash_mc_addr(struct atl1_hw *hw, u8 *mc_addr)
563 {
564 u32 crc32, value = 0;
565 int i;
566
567 crc32 = ether_crc_le(6, mc_addr);
568 for (i = 0; i < 32; i++)
569 value |= (((crc32 >> i) & 1) << (31 - i));
570
571 return value;
572 }
573
574 /*
575 * Sets the bit in the multicast table corresponding to the hash value.
576 * hw - Struct containing variables accessed by shared code
577 * hash_value - Multicast address hash value
578 */
579 static void atl1_hash_set(struct atl1_hw *hw, u32 hash_value)
580 {
581 u32 hash_bit, hash_reg;
582 u32 mta;
583
584 /*
585 * The HASH Table is a register array of 2 32-bit registers.
586 * It is treated like an array of 64 bits. We want to set
587 * bit BitArray[hash_value]. So we figure out what register
588 * the bit is in, read it, OR in the new bit, then write
589 * back the new value. The register is determined by the
590 * upper 7 bits of the hash value and the bit within that
591 * register are determined by the lower 5 bits of the value.
592 */
593 hash_reg = (hash_value >> 31) & 0x1;
594 hash_bit = (hash_value >> 26) & 0x1F;
595 mta = ioread32((hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
596 mta |= (1 << hash_bit);
597 iowrite32(mta, (hw->hw_addr + REG_RX_HASH_TABLE) + (hash_reg << 2));
598 }
599
600 /*
601 * Writes a value to a PHY register
602 * hw - Struct containing variables accessed by shared code
603 * reg_addr - address of the PHY register to write
604 * data - data to write to the PHY
605 */
606 static s32 atl1_write_phy_reg(struct atl1_hw *hw, u32 reg_addr, u16 phy_data)
607 {
608 int i;
609 u32 val;
610
611 val = ((u32) (phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT |
612 (reg_addr & MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT |
613 MDIO_SUP_PREAMBLE |
614 MDIO_START | MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
615 iowrite32(val, hw->hw_addr + REG_MDIO_CTRL);
616 ioread32(hw->hw_addr + REG_MDIO_CTRL);
617
618 for (i = 0; i < MDIO_WAIT_TIMES; i++) {
619 udelay(2);
620 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
621 if (!(val & (MDIO_START | MDIO_BUSY)))
622 break;
623 }
624
625 if (!(val & (MDIO_START | MDIO_BUSY)))
626 return 0;
627
628 return ATLX_ERR_PHY;
629 }
630
631 /*
632 * Make L001's PHY out of Power Saving State (bug)
633 * hw - Struct containing variables accessed by shared code
634 * when power on, L001's PHY always on Power saving State
635 * (Gigabit Link forbidden)
636 */
637 static s32 atl1_phy_leave_power_saving(struct atl1_hw *hw)
638 {
639 s32 ret;
640 ret = atl1_write_phy_reg(hw, 29, 0x0029);
641 if (ret)
642 return ret;
643 return atl1_write_phy_reg(hw, 30, 0);
644 }
645
646 /*
647 * Resets the PHY and make all config validate
648 * hw - Struct containing variables accessed by shared code
649 *
650 * Sets bit 15 and 12 of the MII Control regiser (for F001 bug)
651 */
652 static s32 atl1_phy_reset(struct atl1_hw *hw)
653 {
654 struct pci_dev *pdev = hw->back->pdev;
655 struct atl1_adapter *adapter = hw->back;
656 s32 ret_val;
657 u16 phy_data;
658
659 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
660 hw->media_type == MEDIA_TYPE_1000M_FULL)
661 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
662 else {
663 switch (hw->media_type) {
664 case MEDIA_TYPE_100M_FULL:
665 phy_data =
666 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
667 MII_CR_RESET;
668 break;
669 case MEDIA_TYPE_100M_HALF:
670 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
671 break;
672 case MEDIA_TYPE_10M_FULL:
673 phy_data =
674 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
675 break;
676 default:
677 /* MEDIA_TYPE_10M_HALF: */
678 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
679 break;
680 }
681 }
682
683 ret_val = atl1_write_phy_reg(hw, MII_BMCR, phy_data);
684 if (ret_val) {
685 u32 val;
686 int i;
687 /* pcie serdes link may be down! */
688 if (netif_msg_hw(adapter))
689 dev_dbg(&pdev->dev, "pcie phy link down\n");
690
691 for (i = 0; i < 25; i++) {
692 msleep(1);
693 val = ioread32(hw->hw_addr + REG_MDIO_CTRL);
694 if (!(val & (MDIO_START | MDIO_BUSY)))
695 break;
696 }
697
698 if ((val & (MDIO_START | MDIO_BUSY)) != 0) {
699 if (netif_msg_hw(adapter))
700 dev_warn(&pdev->dev,
701 "pcie link down at least 25ms\n");
702 return ret_val;
703 }
704 }
705 return 0;
706 }
707
708 /*
709 * Configures PHY autoneg and flow control advertisement settings
710 * hw - Struct containing variables accessed by shared code
711 */
712 static s32 atl1_phy_setup_autoneg_adv(struct atl1_hw *hw)
713 {
714 s32 ret_val;
715 s16 mii_autoneg_adv_reg;
716 s16 mii_1000t_ctrl_reg;
717
718 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
719 mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
720
721 /* Read the MII 1000Base-T Control Register (Address 9). */
722 mii_1000t_ctrl_reg = MII_ATLX_CR_1000T_DEFAULT_CAP_MASK;
723
724 /*
725 * First we clear all the 10/100 mb speed bits in the Auto-Neg
726 * Advertisement Register (Address 4) and the 1000 mb speed bits in
727 * the 1000Base-T Control Register (Address 9).
728 */
729 mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
730 mii_1000t_ctrl_reg &= ~MII_ATLX_CR_1000T_SPEED_MASK;
731
732 /*
733 * Need to parse media_type and set up
734 * the appropriate PHY registers.
735 */
736 switch (hw->media_type) {
737 case MEDIA_TYPE_AUTO_SENSOR:
738 mii_autoneg_adv_reg |= (MII_AR_10T_HD_CAPS |
739 MII_AR_10T_FD_CAPS |
740 MII_AR_100TX_HD_CAPS |
741 MII_AR_100TX_FD_CAPS);
742 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
743 break;
744
745 case MEDIA_TYPE_1000M_FULL:
746 mii_1000t_ctrl_reg |= MII_ATLX_CR_1000T_FD_CAPS;
747 break;
748
749 case MEDIA_TYPE_100M_FULL:
750 mii_autoneg_adv_reg |= MII_AR_100TX_FD_CAPS;
751 break;
752
753 case MEDIA_TYPE_100M_HALF:
754 mii_autoneg_adv_reg |= MII_AR_100TX_HD_CAPS;
755 break;
756
757 case MEDIA_TYPE_10M_FULL:
758 mii_autoneg_adv_reg |= MII_AR_10T_FD_CAPS;
759 break;
760
761 default:
762 mii_autoneg_adv_reg |= MII_AR_10T_HD_CAPS;
763 break;
764 }
765
766 /* flow control fixed to enable all */
767 mii_autoneg_adv_reg |= (MII_AR_ASM_DIR | MII_AR_PAUSE);
768
769 hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
770 hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
771
772 ret_val = atl1_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
773 if (ret_val)
774 return ret_val;
775
776 ret_val = atl1_write_phy_reg(hw, MII_ATLX_CR, mii_1000t_ctrl_reg);
777 if (ret_val)
778 return ret_val;
779
780 return 0;
781 }
782
783 /*
784 * Configures link settings.
785 * hw - Struct containing variables accessed by shared code
786 * Assumes the hardware has previously been reset and the
787 * transmitter and receiver are not enabled.
788 */
789 static s32 atl1_setup_link(struct atl1_hw *hw)
790 {
791 struct pci_dev *pdev = hw->back->pdev;
792 struct atl1_adapter *adapter = hw->back;
793 s32 ret_val;
794
795 /*
796 * Options:
797 * PHY will advertise value(s) parsed from
798 * autoneg_advertised and fc
799 * no matter what autoneg is , We will not wait link result.
800 */
801 ret_val = atl1_phy_setup_autoneg_adv(hw);
802 if (ret_val) {
803 if (netif_msg_link(adapter))
804 dev_dbg(&pdev->dev,
805 "error setting up autonegotiation\n");
806 return ret_val;
807 }
808 /* SW.Reset , En-Auto-Neg if needed */
809 ret_val = atl1_phy_reset(hw);
810 if (ret_val) {
811 if (netif_msg_link(adapter))
812 dev_dbg(&pdev->dev, "error resetting phy\n");
813 return ret_val;
814 }
815 hw->phy_configured = true;
816 return ret_val;
817 }
818
819 static void atl1_init_flash_opcode(struct atl1_hw *hw)
820 {
821 if (hw->flash_vendor >= ARRAY_SIZE(flash_table))
822 /* Atmel */
823 hw->flash_vendor = 0;
824
825 /* Init OP table */
826 iowrite8(flash_table[hw->flash_vendor].cmd_program,
827 hw->hw_addr + REG_SPI_FLASH_OP_PROGRAM);
828 iowrite8(flash_table[hw->flash_vendor].cmd_sector_erase,
829 hw->hw_addr + REG_SPI_FLASH_OP_SC_ERASE);
830 iowrite8(flash_table[hw->flash_vendor].cmd_chip_erase,
831 hw->hw_addr + REG_SPI_FLASH_OP_CHIP_ERASE);
832 iowrite8(flash_table[hw->flash_vendor].cmd_rdid,
833 hw->hw_addr + REG_SPI_FLASH_OP_RDID);
834 iowrite8(flash_table[hw->flash_vendor].cmd_wren,
835 hw->hw_addr + REG_SPI_FLASH_OP_WREN);
836 iowrite8(flash_table[hw->flash_vendor].cmd_rdsr,
837 hw->hw_addr + REG_SPI_FLASH_OP_RDSR);
838 iowrite8(flash_table[hw->flash_vendor].cmd_wrsr,
839 hw->hw_addr + REG_SPI_FLASH_OP_WRSR);
840 iowrite8(flash_table[hw->flash_vendor].cmd_read,
841 hw->hw_addr + REG_SPI_FLASH_OP_READ);
842 }
843
844 /*
845 * Performs basic configuration of the adapter.
846 * hw - Struct containing variables accessed by shared code
847 * Assumes that the controller has previously been reset and is in a
848 * post-reset uninitialized state. Initializes multicast table,
849 * and Calls routines to setup link
850 * Leaves the transmit and receive units disabled and uninitialized.
851 */
852 static s32 atl1_init_hw(struct atl1_hw *hw)
853 {
854 u32 ret_val = 0;
855
856 /* Zero out the Multicast HASH table */
857 iowrite32(0, hw->hw_addr + REG_RX_HASH_TABLE);
858 /* clear the old settings from the multicast hash table */
859 iowrite32(0, (hw->hw_addr + REG_RX_HASH_TABLE) + (1 << 2));
860
861 atl1_init_flash_opcode(hw);
862
863 if (!hw->phy_configured) {
864 /* enable GPHY LinkChange Interrupt */
865 ret_val = atl1_write_phy_reg(hw, 18, 0xC00);
866 if (ret_val)
867 return ret_val;
868 /* make PHY out of power-saving state */
869 ret_val = atl1_phy_leave_power_saving(hw);
870 if (ret_val)
871 return ret_val;
872 /* Call a subroutine to configure the link */
873 ret_val = atl1_setup_link(hw);
874 }
875 return ret_val;
876 }
877
878 /*
879 * Detects the current speed and duplex settings of the hardware.
880 * hw - Struct containing variables accessed by shared code
881 * speed - Speed of the connection
882 * duplex - Duplex setting of the connection
883 */
884 static s32 atl1_get_speed_and_duplex(struct atl1_hw *hw, u16 *speed, u16 *duplex)
885 {
886 struct pci_dev *pdev = hw->back->pdev;
887 struct atl1_adapter *adapter = hw->back;
888 s32 ret_val;
889 u16 phy_data;
890
891 /* ; --- Read PHY Specific Status Register (17) */
892 ret_val = atl1_read_phy_reg(hw, MII_ATLX_PSSR, &phy_data);
893 if (ret_val)
894 return ret_val;
895
896 if (!(phy_data & MII_ATLX_PSSR_SPD_DPLX_RESOLVED))
897 return ATLX_ERR_PHY_RES;
898
899 switch (phy_data & MII_ATLX_PSSR_SPEED) {
900 case MII_ATLX_PSSR_1000MBS:
901 *speed = SPEED_1000;
902 break;
903 case MII_ATLX_PSSR_100MBS:
904 *speed = SPEED_100;
905 break;
906 case MII_ATLX_PSSR_10MBS:
907 *speed = SPEED_10;
908 break;
909 default:
910 if (netif_msg_hw(adapter))
911 dev_dbg(&pdev->dev, "error getting speed\n");
912 return ATLX_ERR_PHY_SPEED;
913 break;
914 }
915 if (phy_data & MII_ATLX_PSSR_DPLX)
916 *duplex = FULL_DUPLEX;
917 else
918 *duplex = HALF_DUPLEX;
919
920 return 0;
921 }
922
923 static void atl1_set_mac_addr(struct atl1_hw *hw)
924 {
925 u32 value;
926 /*
927 * 00-0B-6A-F6-00-DC
928 * 0: 6AF600DC 1: 000B
929 * low dword
930 */
931 value = (((u32) hw->mac_addr[2]) << 24) |
932 (((u32) hw->mac_addr[3]) << 16) |
933 (((u32) hw->mac_addr[4]) << 8) | (((u32) hw->mac_addr[5]));
934 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
935 /* high dword */
936 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
937 iowrite32(value, (hw->hw_addr + REG_MAC_STA_ADDR) + (1 << 2));
938 }
939
940 /*
941 * atl1_sw_init - Initialize general software structures (struct atl1_adapter)
942 * @adapter: board private structure to initialize
943 *
944 * atl1_sw_init initializes the Adapter private data structure.
945 * Fields are initialized based on PCI device information and
946 * OS network device settings (MTU size).
947 */
948 static int __devinit atl1_sw_init(struct atl1_adapter *adapter)
949 {
950 struct atl1_hw *hw = &adapter->hw;
951 struct net_device *netdev = adapter->netdev;
952
953 hw->max_frame_size = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
954 hw->min_frame_size = ETH_ZLEN + ETH_FCS_LEN;
955
956 adapter->wol = 0;
957 device_set_wakeup_enable(&adapter->pdev->dev, false);
958 adapter->rx_buffer_len = (hw->max_frame_size + 7) & ~7;
959 adapter->ict = 50000; /* 100ms */
960 adapter->link_speed = SPEED_0; /* hardware init */
961 adapter->link_duplex = FULL_DUPLEX;
962
963 hw->phy_configured = false;
964 hw->preamble_len = 7;
965 hw->ipgt = 0x60;
966 hw->min_ifg = 0x50;
967 hw->ipgr1 = 0x40;
968 hw->ipgr2 = 0x60;
969 hw->max_retry = 0xf;
970 hw->lcol = 0x37;
971 hw->jam_ipg = 7;
972 hw->rfd_burst = 8;
973 hw->rrd_burst = 8;
974 hw->rfd_fetch_gap = 1;
975 hw->rx_jumbo_th = adapter->rx_buffer_len / 8;
976 hw->rx_jumbo_lkah = 1;
977 hw->rrd_ret_timer = 16;
978 hw->tpd_burst = 4;
979 hw->tpd_fetch_th = 16;
980 hw->txf_burst = 0x100;
981 hw->tx_jumbo_task_th = (hw->max_frame_size + 7) >> 3;
982 hw->tpd_fetch_gap = 1;
983 hw->rcb_value = atl1_rcb_64;
984 hw->dma_ord = atl1_dma_ord_enh;
985 hw->dmar_block = atl1_dma_req_256;
986 hw->dmaw_block = atl1_dma_req_256;
987 hw->cmb_rrd = 4;
988 hw->cmb_tpd = 4;
989 hw->cmb_rx_timer = 1; /* about 2us */
990 hw->cmb_tx_timer = 1; /* about 2us */
991 hw->smb_timer = 100000; /* about 200ms */
992
993 spin_lock_init(&adapter->lock);
994 spin_lock_init(&adapter->mb_lock);
995
996 return 0;
997 }
998
999 static int mdio_read(struct net_device *netdev, int phy_id, int reg_num)
1000 {
1001 struct atl1_adapter *adapter = netdev_priv(netdev);
1002 u16 result;
1003
1004 atl1_read_phy_reg(&adapter->hw, reg_num & 0x1f, &result);
1005
1006 return result;
1007 }
1008
1009 static void mdio_write(struct net_device *netdev, int phy_id, int reg_num,
1010 int val)
1011 {
1012 struct atl1_adapter *adapter = netdev_priv(netdev);
1013
1014 atl1_write_phy_reg(&adapter->hw, reg_num, val);
1015 }
1016
1017 /*
1018 * atl1_mii_ioctl -
1019 * @netdev:
1020 * @ifreq:
1021 * @cmd:
1022 */
1023 static int atl1_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
1024 {
1025 struct atl1_adapter *adapter = netdev_priv(netdev);
1026 unsigned long flags;
1027 int retval;
1028
1029 if (!netif_running(netdev))
1030 return -EINVAL;
1031
1032 spin_lock_irqsave(&adapter->lock, flags);
1033 retval = generic_mii_ioctl(&adapter->mii, if_mii(ifr), cmd, NULL);
1034 spin_unlock_irqrestore(&adapter->lock, flags);
1035
1036 return retval;
1037 }
1038
1039 /*
1040 * atl1_setup_mem_resources - allocate Tx / RX descriptor resources
1041 * @adapter: board private structure
1042 *
1043 * Return 0 on success, negative on failure
1044 */
1045 static s32 atl1_setup_ring_resources(struct atl1_adapter *adapter)
1046 {
1047 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1048 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1049 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1050 struct atl1_ring_header *ring_header = &adapter->ring_header;
1051 struct pci_dev *pdev = adapter->pdev;
1052 int size;
1053 u8 offset = 0;
1054
1055 size = sizeof(struct atl1_buffer) * (tpd_ring->count + rfd_ring->count);
1056 tpd_ring->buffer_info = kzalloc(size, GFP_KERNEL);
1057 if (unlikely(!tpd_ring->buffer_info)) {
1058 if (netif_msg_drv(adapter))
1059 dev_err(&pdev->dev, "kzalloc failed , size = D%d\n",
1060 size);
1061 goto err_nomem;
1062 }
1063 rfd_ring->buffer_info =
1064 (struct atl1_buffer *)(tpd_ring->buffer_info + tpd_ring->count);
1065
1066 /*
1067 * real ring DMA buffer
1068 * each ring/block may need up to 8 bytes for alignment, hence the
1069 * additional 40 bytes tacked onto the end.
1070 */
1071 ring_header->size = size =
1072 sizeof(struct tx_packet_desc) * tpd_ring->count
1073 + sizeof(struct rx_free_desc) * rfd_ring->count
1074 + sizeof(struct rx_return_desc) * rrd_ring->count
1075 + sizeof(struct coals_msg_block)
1076 + sizeof(struct stats_msg_block)
1077 + 40;
1078
1079 ring_header->desc = pci_alloc_consistent(pdev, ring_header->size,
1080 &ring_header->dma);
1081 if (unlikely(!ring_header->desc)) {
1082 if (netif_msg_drv(adapter))
1083 dev_err(&pdev->dev, "pci_alloc_consistent failed\n");
1084 goto err_nomem;
1085 }
1086
1087 memset(ring_header->desc, 0, ring_header->size);
1088
1089 /* init TPD ring */
1090 tpd_ring->dma = ring_header->dma;
1091 offset = (tpd_ring->dma & 0x7) ? (8 - (ring_header->dma & 0x7)) : 0;
1092 tpd_ring->dma += offset;
1093 tpd_ring->desc = (u8 *) ring_header->desc + offset;
1094 tpd_ring->size = sizeof(struct tx_packet_desc) * tpd_ring->count;
1095
1096 /* init RFD ring */
1097 rfd_ring->dma = tpd_ring->dma + tpd_ring->size;
1098 offset = (rfd_ring->dma & 0x7) ? (8 - (rfd_ring->dma & 0x7)) : 0;
1099 rfd_ring->dma += offset;
1100 rfd_ring->desc = (u8 *) tpd_ring->desc + (tpd_ring->size + offset);
1101 rfd_ring->size = sizeof(struct rx_free_desc) * rfd_ring->count;
1102
1103
1104 /* init RRD ring */
1105 rrd_ring->dma = rfd_ring->dma + rfd_ring->size;
1106 offset = (rrd_ring->dma & 0x7) ? (8 - (rrd_ring->dma & 0x7)) : 0;
1107 rrd_ring->dma += offset;
1108 rrd_ring->desc = (u8 *) rfd_ring->desc + (rfd_ring->size + offset);
1109 rrd_ring->size = sizeof(struct rx_return_desc) * rrd_ring->count;
1110
1111
1112 /* init CMB */
1113 adapter->cmb.dma = rrd_ring->dma + rrd_ring->size;
1114 offset = (adapter->cmb.dma & 0x7) ? (8 - (adapter->cmb.dma & 0x7)) : 0;
1115 adapter->cmb.dma += offset;
1116 adapter->cmb.cmb = (struct coals_msg_block *)
1117 ((u8 *) rrd_ring->desc + (rrd_ring->size + offset));
1118
1119 /* init SMB */
1120 adapter->smb.dma = adapter->cmb.dma + sizeof(struct coals_msg_block);
1121 offset = (adapter->smb.dma & 0x7) ? (8 - (adapter->smb.dma & 0x7)) : 0;
1122 adapter->smb.dma += offset;
1123 adapter->smb.smb = (struct stats_msg_block *)
1124 ((u8 *) adapter->cmb.cmb +
1125 (sizeof(struct coals_msg_block) + offset));
1126
1127 return 0;
1128
1129 err_nomem:
1130 kfree(tpd_ring->buffer_info);
1131 return -ENOMEM;
1132 }
1133
1134 static void atl1_init_ring_ptrs(struct atl1_adapter *adapter)
1135 {
1136 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1137 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1138 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1139
1140 atomic_set(&tpd_ring->next_to_use, 0);
1141 atomic_set(&tpd_ring->next_to_clean, 0);
1142
1143 rfd_ring->next_to_clean = 0;
1144 atomic_set(&rfd_ring->next_to_use, 0);
1145
1146 rrd_ring->next_to_use = 0;
1147 atomic_set(&rrd_ring->next_to_clean, 0);
1148 }
1149
1150 /*
1151 * atl1_clean_rx_ring - Free RFD Buffers
1152 * @adapter: board private structure
1153 */
1154 static void atl1_clean_rx_ring(struct atl1_adapter *adapter)
1155 {
1156 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1157 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1158 struct atl1_buffer *buffer_info;
1159 struct pci_dev *pdev = adapter->pdev;
1160 unsigned long size;
1161 unsigned int i;
1162
1163 /* Free all the Rx ring sk_buffs */
1164 for (i = 0; i < rfd_ring->count; i++) {
1165 buffer_info = &rfd_ring->buffer_info[i];
1166 if (buffer_info->dma) {
1167 pci_unmap_page(pdev, buffer_info->dma,
1168 buffer_info->length, PCI_DMA_FROMDEVICE);
1169 buffer_info->dma = 0;
1170 }
1171 if (buffer_info->skb) {
1172 dev_kfree_skb(buffer_info->skb);
1173 buffer_info->skb = NULL;
1174 }
1175 }
1176
1177 size = sizeof(struct atl1_buffer) * rfd_ring->count;
1178 memset(rfd_ring->buffer_info, 0, size);
1179
1180 /* Zero out the descriptor ring */
1181 memset(rfd_ring->desc, 0, rfd_ring->size);
1182
1183 rfd_ring->next_to_clean = 0;
1184 atomic_set(&rfd_ring->next_to_use, 0);
1185
1186 rrd_ring->next_to_use = 0;
1187 atomic_set(&rrd_ring->next_to_clean, 0);
1188 }
1189
1190 /*
1191 * atl1_clean_tx_ring - Free Tx Buffers
1192 * @adapter: board private structure
1193 */
1194 static void atl1_clean_tx_ring(struct atl1_adapter *adapter)
1195 {
1196 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1197 struct atl1_buffer *buffer_info;
1198 struct pci_dev *pdev = adapter->pdev;
1199 unsigned long size;
1200 unsigned int i;
1201
1202 /* Free all the Tx ring sk_buffs */
1203 for (i = 0; i < tpd_ring->count; i++) {
1204 buffer_info = &tpd_ring->buffer_info[i];
1205 if (buffer_info->dma) {
1206 pci_unmap_page(pdev, buffer_info->dma,
1207 buffer_info->length, PCI_DMA_TODEVICE);
1208 buffer_info->dma = 0;
1209 }
1210 }
1211
1212 for (i = 0; i < tpd_ring->count; i++) {
1213 buffer_info = &tpd_ring->buffer_info[i];
1214 if (buffer_info->skb) {
1215 dev_kfree_skb_any(buffer_info->skb);
1216 buffer_info->skb = NULL;
1217 }
1218 }
1219
1220 size = sizeof(struct atl1_buffer) * tpd_ring->count;
1221 memset(tpd_ring->buffer_info, 0, size);
1222
1223 /* Zero out the descriptor ring */
1224 memset(tpd_ring->desc, 0, tpd_ring->size);
1225
1226 atomic_set(&tpd_ring->next_to_use, 0);
1227 atomic_set(&tpd_ring->next_to_clean, 0);
1228 }
1229
1230 /*
1231 * atl1_free_ring_resources - Free Tx / RX descriptor Resources
1232 * @adapter: board private structure
1233 *
1234 * Free all transmit software resources
1235 */
1236 static void atl1_free_ring_resources(struct atl1_adapter *adapter)
1237 {
1238 struct pci_dev *pdev = adapter->pdev;
1239 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
1240 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1241 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1242 struct atl1_ring_header *ring_header = &adapter->ring_header;
1243
1244 atl1_clean_tx_ring(adapter);
1245 atl1_clean_rx_ring(adapter);
1246
1247 kfree(tpd_ring->buffer_info);
1248 pci_free_consistent(pdev, ring_header->size, ring_header->desc,
1249 ring_header->dma);
1250
1251 tpd_ring->buffer_info = NULL;
1252 tpd_ring->desc = NULL;
1253 tpd_ring->dma = 0;
1254
1255 rfd_ring->buffer_info = NULL;
1256 rfd_ring->desc = NULL;
1257 rfd_ring->dma = 0;
1258
1259 rrd_ring->desc = NULL;
1260 rrd_ring->dma = 0;
1261
1262 adapter->cmb.dma = 0;
1263 adapter->cmb.cmb = NULL;
1264
1265 adapter->smb.dma = 0;
1266 adapter->smb.smb = NULL;
1267 }
1268
1269 static void atl1_setup_mac_ctrl(struct atl1_adapter *adapter)
1270 {
1271 u32 value;
1272 struct atl1_hw *hw = &adapter->hw;
1273 struct net_device *netdev = adapter->netdev;
1274 /* Config MAC CTRL Register */
1275 value = MAC_CTRL_TX_EN | MAC_CTRL_RX_EN;
1276 /* duplex */
1277 if (FULL_DUPLEX == adapter->link_duplex)
1278 value |= MAC_CTRL_DUPLX;
1279 /* speed */
1280 value |= ((u32) ((SPEED_1000 == adapter->link_speed) ?
1281 MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
1282 MAC_CTRL_SPEED_SHIFT);
1283 /* flow control */
1284 value |= (MAC_CTRL_TX_FLOW | MAC_CTRL_RX_FLOW);
1285 /* PAD & CRC */
1286 value |= (MAC_CTRL_ADD_CRC | MAC_CTRL_PAD);
1287 /* preamble length */
1288 value |= (((u32) adapter->hw.preamble_len
1289 & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
1290 /* vlan */
1291 __atlx_vlan_mode(netdev->features, &value);
1292 /* rx checksum
1293 if (adapter->rx_csum)
1294 value |= MAC_CTRL_RX_CHKSUM_EN;
1295 */
1296 /* filter mode */
1297 value |= MAC_CTRL_BC_EN;
1298 if (netdev->flags & IFF_PROMISC)
1299 value |= MAC_CTRL_PROMIS_EN;
1300 else if (netdev->flags & IFF_ALLMULTI)
1301 value |= MAC_CTRL_MC_ALL_EN;
1302 /* value |= MAC_CTRL_LOOPBACK; */
1303 iowrite32(value, hw->hw_addr + REG_MAC_CTRL);
1304 }
1305
1306 static u32 atl1_check_link(struct atl1_adapter *adapter)
1307 {
1308 struct atl1_hw *hw = &adapter->hw;
1309 struct net_device *netdev = adapter->netdev;
1310 u32 ret_val;
1311 u16 speed, duplex, phy_data;
1312 int reconfig = 0;
1313
1314 /* MII_BMSR must read twice */
1315 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1316 atl1_read_phy_reg(hw, MII_BMSR, &phy_data);
1317 if (!(phy_data & BMSR_LSTATUS)) {
1318 /* link down */
1319 if (netif_carrier_ok(netdev)) {
1320 /* old link state: Up */
1321 if (netif_msg_link(adapter))
1322 dev_info(&adapter->pdev->dev, "link is down\n");
1323 adapter->link_speed = SPEED_0;
1324 netif_carrier_off(netdev);
1325 }
1326 return 0;
1327 }
1328
1329 /* Link Up */
1330 ret_val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
1331 if (ret_val)
1332 return ret_val;
1333
1334 switch (hw->media_type) {
1335 case MEDIA_TYPE_1000M_FULL:
1336 if (speed != SPEED_1000 || duplex != FULL_DUPLEX)
1337 reconfig = 1;
1338 break;
1339 case MEDIA_TYPE_100M_FULL:
1340 if (speed != SPEED_100 || duplex != FULL_DUPLEX)
1341 reconfig = 1;
1342 break;
1343 case MEDIA_TYPE_100M_HALF:
1344 if (speed != SPEED_100 || duplex != HALF_DUPLEX)
1345 reconfig = 1;
1346 break;
1347 case MEDIA_TYPE_10M_FULL:
1348 if (speed != SPEED_10 || duplex != FULL_DUPLEX)
1349 reconfig = 1;
1350 break;
1351 case MEDIA_TYPE_10M_HALF:
1352 if (speed != SPEED_10 || duplex != HALF_DUPLEX)
1353 reconfig = 1;
1354 break;
1355 }
1356
1357 /* link result is our setting */
1358 if (!reconfig) {
1359 if (adapter->link_speed != speed ||
1360 adapter->link_duplex != duplex) {
1361 adapter->link_speed = speed;
1362 adapter->link_duplex = duplex;
1363 atl1_setup_mac_ctrl(adapter);
1364 if (netif_msg_link(adapter))
1365 dev_info(&adapter->pdev->dev,
1366 "%s link is up %d Mbps %s\n",
1367 netdev->name, adapter->link_speed,
1368 adapter->link_duplex == FULL_DUPLEX ?
1369 "full duplex" : "half duplex");
1370 }
1371 if (!netif_carrier_ok(netdev)) {
1372 /* Link down -> Up */
1373 netif_carrier_on(netdev);
1374 }
1375 return 0;
1376 }
1377
1378 /* change original link status */
1379 if (netif_carrier_ok(netdev)) {
1380 adapter->link_speed = SPEED_0;
1381 netif_carrier_off(netdev);
1382 netif_stop_queue(netdev);
1383 }
1384
1385 if (hw->media_type != MEDIA_TYPE_AUTO_SENSOR &&
1386 hw->media_type != MEDIA_TYPE_1000M_FULL) {
1387 switch (hw->media_type) {
1388 case MEDIA_TYPE_100M_FULL:
1389 phy_data = MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
1390 MII_CR_RESET;
1391 break;
1392 case MEDIA_TYPE_100M_HALF:
1393 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
1394 break;
1395 case MEDIA_TYPE_10M_FULL:
1396 phy_data =
1397 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
1398 break;
1399 default:
1400 /* MEDIA_TYPE_10M_HALF: */
1401 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
1402 break;
1403 }
1404 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
1405 return 0;
1406 }
1407
1408 /* auto-neg, insert timer to re-config phy */
1409 if (!adapter->phy_timer_pending) {
1410 adapter->phy_timer_pending = true;
1411 mod_timer(&adapter->phy_config_timer,
1412 round_jiffies(jiffies + 3 * HZ));
1413 }
1414
1415 return 0;
1416 }
1417
1418 static void set_flow_ctrl_old(struct atl1_adapter *adapter)
1419 {
1420 u32 hi, lo, value;
1421
1422 /* RFD Flow Control */
1423 value = adapter->rfd_ring.count;
1424 hi = value / 16;
1425 if (hi < 2)
1426 hi = 2;
1427 lo = value * 7 / 8;
1428
1429 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1430 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1431 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1432
1433 /* RRD Flow Control */
1434 value = adapter->rrd_ring.count;
1435 lo = value / 16;
1436 hi = value * 7 / 8;
1437 if (lo < 2)
1438 lo = 2;
1439 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1440 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1441 iowrite32(value, adapter->hw.hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1442 }
1443
1444 static void set_flow_ctrl_new(struct atl1_hw *hw)
1445 {
1446 u32 hi, lo, value;
1447
1448 /* RXF Flow Control */
1449 value = ioread32(hw->hw_addr + REG_SRAM_RXF_LEN);
1450 lo = value / 16;
1451 if (lo < 192)
1452 lo = 192;
1453 hi = value * 7 / 8;
1454 if (hi < lo)
1455 hi = lo + 16;
1456 value = ((hi & RXQ_RXF_PAUSE_TH_HI_MASK) << RXQ_RXF_PAUSE_TH_HI_SHIFT) |
1457 ((lo & RXQ_RXF_PAUSE_TH_LO_MASK) << RXQ_RXF_PAUSE_TH_LO_SHIFT);
1458 iowrite32(value, hw->hw_addr + REG_RXQ_RXF_PAUSE_THRESH);
1459
1460 /* RRD Flow Control */
1461 value = ioread32(hw->hw_addr + REG_SRAM_RRD_LEN);
1462 lo = value / 8;
1463 hi = value * 7 / 8;
1464 if (lo < 2)
1465 lo = 2;
1466 if (hi < lo)
1467 hi = lo + 3;
1468 value = ((hi & RXQ_RRD_PAUSE_TH_HI_MASK) << RXQ_RRD_PAUSE_TH_HI_SHIFT) |
1469 ((lo & RXQ_RRD_PAUSE_TH_LO_MASK) << RXQ_RRD_PAUSE_TH_LO_SHIFT);
1470 iowrite32(value, hw->hw_addr + REG_RXQ_RRD_PAUSE_THRESH);
1471 }
1472
1473 /*
1474 * atl1_configure - Configure Transmit&Receive Unit after Reset
1475 * @adapter: board private structure
1476 *
1477 * Configure the Tx /Rx unit of the MAC after a reset.
1478 */
1479 static u32 atl1_configure(struct atl1_adapter *adapter)
1480 {
1481 struct atl1_hw *hw = &adapter->hw;
1482 u32 value;
1483
1484 /* clear interrupt status */
1485 iowrite32(0xffffffff, adapter->hw.hw_addr + REG_ISR);
1486
1487 /* set MAC Address */
1488 value = (((u32) hw->mac_addr[2]) << 24) |
1489 (((u32) hw->mac_addr[3]) << 16) |
1490 (((u32) hw->mac_addr[4]) << 8) |
1491 (((u32) hw->mac_addr[5]));
1492 iowrite32(value, hw->hw_addr + REG_MAC_STA_ADDR);
1493 value = (((u32) hw->mac_addr[0]) << 8) | (((u32) hw->mac_addr[1]));
1494 iowrite32(value, hw->hw_addr + (REG_MAC_STA_ADDR + 4));
1495
1496 /* tx / rx ring */
1497
1498 /* HI base address */
1499 iowrite32((u32) ((adapter->tpd_ring.dma & 0xffffffff00000000ULL) >> 32),
1500 hw->hw_addr + REG_DESC_BASE_ADDR_HI);
1501 /* LO base address */
1502 iowrite32((u32) (adapter->rfd_ring.dma & 0x00000000ffffffffULL),
1503 hw->hw_addr + REG_DESC_RFD_ADDR_LO);
1504 iowrite32((u32) (adapter->rrd_ring.dma & 0x00000000ffffffffULL),
1505 hw->hw_addr + REG_DESC_RRD_ADDR_LO);
1506 iowrite32((u32) (adapter->tpd_ring.dma & 0x00000000ffffffffULL),
1507 hw->hw_addr + REG_DESC_TPD_ADDR_LO);
1508 iowrite32((u32) (adapter->cmb.dma & 0x00000000ffffffffULL),
1509 hw->hw_addr + REG_DESC_CMB_ADDR_LO);
1510 iowrite32((u32) (adapter->smb.dma & 0x00000000ffffffffULL),
1511 hw->hw_addr + REG_DESC_SMB_ADDR_LO);
1512
1513 /* element count */
1514 value = adapter->rrd_ring.count;
1515 value <<= 16;
1516 value += adapter->rfd_ring.count;
1517 iowrite32(value, hw->hw_addr + REG_DESC_RFD_RRD_RING_SIZE);
1518 iowrite32(adapter->tpd_ring.count, hw->hw_addr +
1519 REG_DESC_TPD_RING_SIZE);
1520
1521 /* Load Ptr */
1522 iowrite32(1, hw->hw_addr + REG_LOAD_PTR);
1523
1524 /* config Mailbox */
1525 value = ((atomic_read(&adapter->tpd_ring.next_to_use)
1526 & MB_TPD_PROD_INDX_MASK) << MB_TPD_PROD_INDX_SHIFT) |
1527 ((atomic_read(&adapter->rrd_ring.next_to_clean)
1528 & MB_RRD_CONS_INDX_MASK) << MB_RRD_CONS_INDX_SHIFT) |
1529 ((atomic_read(&adapter->rfd_ring.next_to_use)
1530 & MB_RFD_PROD_INDX_MASK) << MB_RFD_PROD_INDX_SHIFT);
1531 iowrite32(value, hw->hw_addr + REG_MAILBOX);
1532
1533 /* config IPG/IFG */
1534 value = (((u32) hw->ipgt & MAC_IPG_IFG_IPGT_MASK)
1535 << MAC_IPG_IFG_IPGT_SHIFT) |
1536 (((u32) hw->min_ifg & MAC_IPG_IFG_MIFG_MASK)
1537 << MAC_IPG_IFG_MIFG_SHIFT) |
1538 (((u32) hw->ipgr1 & MAC_IPG_IFG_IPGR1_MASK)
1539 << MAC_IPG_IFG_IPGR1_SHIFT) |
1540 (((u32) hw->ipgr2 & MAC_IPG_IFG_IPGR2_MASK)
1541 << MAC_IPG_IFG_IPGR2_SHIFT);
1542 iowrite32(value, hw->hw_addr + REG_MAC_IPG_IFG);
1543
1544 /* config Half-Duplex Control */
1545 value = ((u32) hw->lcol & MAC_HALF_DUPLX_CTRL_LCOL_MASK) |
1546 (((u32) hw->max_retry & MAC_HALF_DUPLX_CTRL_RETRY_MASK)
1547 << MAC_HALF_DUPLX_CTRL_RETRY_SHIFT) |
1548 MAC_HALF_DUPLX_CTRL_EXC_DEF_EN |
1549 (0xa << MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT) |
1550 (((u32) hw->jam_ipg & MAC_HALF_DUPLX_CTRL_JAMIPG_MASK)
1551 << MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT);
1552 iowrite32(value, hw->hw_addr + REG_MAC_HALF_DUPLX_CTRL);
1553
1554 /* set Interrupt Moderator Timer */
1555 iowrite16(adapter->imt, hw->hw_addr + REG_IRQ_MODU_TIMER_INIT);
1556 iowrite32(MASTER_CTRL_ITIMER_EN, hw->hw_addr + REG_MASTER_CTRL);
1557
1558 /* set Interrupt Clear Timer */
1559 iowrite16(adapter->ict, hw->hw_addr + REG_CMBDISDMA_TIMER);
1560
1561 /* set max frame size hw will accept */
1562 iowrite32(hw->max_frame_size, hw->hw_addr + REG_MTU);
1563
1564 /* jumbo size & rrd retirement timer */
1565 value = (((u32) hw->rx_jumbo_th & RXQ_JMBOSZ_TH_MASK)
1566 << RXQ_JMBOSZ_TH_SHIFT) |
1567 (((u32) hw->rx_jumbo_lkah & RXQ_JMBO_LKAH_MASK)
1568 << RXQ_JMBO_LKAH_SHIFT) |
1569 (((u32) hw->rrd_ret_timer & RXQ_RRD_TIMER_MASK)
1570 << RXQ_RRD_TIMER_SHIFT);
1571 iowrite32(value, hw->hw_addr + REG_RXQ_JMBOSZ_RRDTIM);
1572
1573 /* Flow Control */
1574 switch (hw->dev_rev) {
1575 case 0x8001:
1576 case 0x9001:
1577 case 0x9002:
1578 case 0x9003:
1579 set_flow_ctrl_old(adapter);
1580 break;
1581 default:
1582 set_flow_ctrl_new(hw);
1583 break;
1584 }
1585
1586 /* config TXQ */
1587 value = (((u32) hw->tpd_burst & TXQ_CTRL_TPD_BURST_NUM_MASK)
1588 << TXQ_CTRL_TPD_BURST_NUM_SHIFT) |
1589 (((u32) hw->txf_burst & TXQ_CTRL_TXF_BURST_NUM_MASK)
1590 << TXQ_CTRL_TXF_BURST_NUM_SHIFT) |
1591 (((u32) hw->tpd_fetch_th & TXQ_CTRL_TPD_FETCH_TH_MASK)
1592 << TXQ_CTRL_TPD_FETCH_TH_SHIFT) | TXQ_CTRL_ENH_MODE |
1593 TXQ_CTRL_EN;
1594 iowrite32(value, hw->hw_addr + REG_TXQ_CTRL);
1595
1596 /* min tpd fetch gap & tx jumbo packet size threshold for taskoffload */
1597 value = (((u32) hw->tx_jumbo_task_th & TX_JUMBO_TASK_TH_MASK)
1598 << TX_JUMBO_TASK_TH_SHIFT) |
1599 (((u32) hw->tpd_fetch_gap & TX_TPD_MIN_IPG_MASK)
1600 << TX_TPD_MIN_IPG_SHIFT);
1601 iowrite32(value, hw->hw_addr + REG_TX_JUMBO_TASK_TH_TPD_IPG);
1602
1603 /* config RXQ */
1604 value = (((u32) hw->rfd_burst & RXQ_CTRL_RFD_BURST_NUM_MASK)
1605 << RXQ_CTRL_RFD_BURST_NUM_SHIFT) |
1606 (((u32) hw->rrd_burst & RXQ_CTRL_RRD_BURST_THRESH_MASK)
1607 << RXQ_CTRL_RRD_BURST_THRESH_SHIFT) |
1608 (((u32) hw->rfd_fetch_gap & RXQ_CTRL_RFD_PREF_MIN_IPG_MASK)
1609 << RXQ_CTRL_RFD_PREF_MIN_IPG_SHIFT) | RXQ_CTRL_CUT_THRU_EN |
1610 RXQ_CTRL_EN;
1611 iowrite32(value, hw->hw_addr + REG_RXQ_CTRL);
1612
1613 /* config DMA Engine */
1614 value = ((((u32) hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
1615 << DMA_CTRL_DMAR_BURST_LEN_SHIFT) |
1616 ((((u32) hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
1617 << DMA_CTRL_DMAW_BURST_LEN_SHIFT) | DMA_CTRL_DMAR_EN |
1618 DMA_CTRL_DMAW_EN;
1619 value |= (u32) hw->dma_ord;
1620 if (atl1_rcb_128 == hw->rcb_value)
1621 value |= DMA_CTRL_RCB_VALUE;
1622 iowrite32(value, hw->hw_addr + REG_DMA_CTRL);
1623
1624 /* config CMB / SMB */
1625 value = (hw->cmb_tpd > adapter->tpd_ring.count) ?
1626 hw->cmb_tpd : adapter->tpd_ring.count;
1627 value <<= 16;
1628 value |= hw->cmb_rrd;
1629 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TH);
1630 value = hw->cmb_rx_timer | ((u32) hw->cmb_tx_timer << 16);
1631 iowrite32(value, hw->hw_addr + REG_CMB_WRITE_TIMER);
1632 iowrite32(hw->smb_timer, hw->hw_addr + REG_SMB_TIMER);
1633
1634 /* --- enable CMB / SMB */
1635 value = CSMB_CTRL_CMB_EN | CSMB_CTRL_SMB_EN;
1636 iowrite32(value, hw->hw_addr + REG_CSMB_CTRL);
1637
1638 value = ioread32(adapter->hw.hw_addr + REG_ISR);
1639 if (unlikely((value & ISR_PHY_LINKDOWN) != 0))
1640 value = 1; /* config failed */
1641 else
1642 value = 0;
1643
1644 /* clear all interrupt status */
1645 iowrite32(0x3fffffff, adapter->hw.hw_addr + REG_ISR);
1646 iowrite32(0, adapter->hw.hw_addr + REG_ISR);
1647 return value;
1648 }
1649
1650 /*
1651 * atl1_pcie_patch - Patch for PCIE module
1652 */
1653 static void atl1_pcie_patch(struct atl1_adapter *adapter)
1654 {
1655 u32 value;
1656
1657 /* much vendor magic here */
1658 value = 0x6500;
1659 iowrite32(value, adapter->hw.hw_addr + 0x12FC);
1660 /* pcie flow control mode change */
1661 value = ioread32(adapter->hw.hw_addr + 0x1008);
1662 value |= 0x8000;
1663 iowrite32(value, adapter->hw.hw_addr + 0x1008);
1664 }
1665
1666 /*
1667 * When ACPI resume on some VIA MotherBoard, the Interrupt Disable bit/0x400
1668 * on PCI Command register is disable.
1669 * The function enable this bit.
1670 * Brackett, 2006/03/15
1671 */
1672 static void atl1_via_workaround(struct atl1_adapter *adapter)
1673 {
1674 unsigned long value;
1675
1676 value = ioread16(adapter->hw.hw_addr + PCI_COMMAND);
1677 if (value & PCI_COMMAND_INTX_DISABLE)
1678 value &= ~PCI_COMMAND_INTX_DISABLE;
1679 iowrite32(value, adapter->hw.hw_addr + PCI_COMMAND);
1680 }
1681
1682 static void atl1_inc_smb(struct atl1_adapter *adapter)
1683 {
1684 struct net_device *netdev = adapter->netdev;
1685 struct stats_msg_block *smb = adapter->smb.smb;
1686
1687 /* Fill out the OS statistics structure */
1688 adapter->soft_stats.rx_packets += smb->rx_ok;
1689 adapter->soft_stats.tx_packets += smb->tx_ok;
1690 adapter->soft_stats.rx_bytes += smb->rx_byte_cnt;
1691 adapter->soft_stats.tx_bytes += smb->tx_byte_cnt;
1692 adapter->soft_stats.multicast += smb->rx_mcast;
1693 adapter->soft_stats.collisions += (smb->tx_1_col + smb->tx_2_col * 2 +
1694 smb->tx_late_col + smb->tx_abort_col * adapter->hw.max_retry);
1695
1696 /* Rx Errors */
1697 adapter->soft_stats.rx_errors += (smb->rx_frag + smb->rx_fcs_err +
1698 smb->rx_len_err + smb->rx_sz_ov + smb->rx_rxf_ov +
1699 smb->rx_rrd_ov + smb->rx_align_err);
1700 adapter->soft_stats.rx_fifo_errors += smb->rx_rxf_ov;
1701 adapter->soft_stats.rx_length_errors += smb->rx_len_err;
1702 adapter->soft_stats.rx_crc_errors += smb->rx_fcs_err;
1703 adapter->soft_stats.rx_frame_errors += smb->rx_align_err;
1704 adapter->soft_stats.rx_missed_errors += (smb->rx_rrd_ov +
1705 smb->rx_rxf_ov);
1706
1707 adapter->soft_stats.rx_pause += smb->rx_pause;
1708 adapter->soft_stats.rx_rrd_ov += smb->rx_rrd_ov;
1709 adapter->soft_stats.rx_trunc += smb->rx_sz_ov;
1710
1711 /* Tx Errors */
1712 adapter->soft_stats.tx_errors += (smb->tx_late_col +
1713 smb->tx_abort_col + smb->tx_underrun + smb->tx_trunc);
1714 adapter->soft_stats.tx_fifo_errors += smb->tx_underrun;
1715 adapter->soft_stats.tx_aborted_errors += smb->tx_abort_col;
1716 adapter->soft_stats.tx_window_errors += smb->tx_late_col;
1717
1718 adapter->soft_stats.excecol += smb->tx_abort_col;
1719 adapter->soft_stats.deffer += smb->tx_defer;
1720 adapter->soft_stats.scc += smb->tx_1_col;
1721 adapter->soft_stats.mcc += smb->tx_2_col;
1722 adapter->soft_stats.latecol += smb->tx_late_col;
1723 adapter->soft_stats.tx_underun += smb->tx_underrun;
1724 adapter->soft_stats.tx_trunc += smb->tx_trunc;
1725 adapter->soft_stats.tx_pause += smb->tx_pause;
1726
1727 netdev->stats.rx_packets = adapter->soft_stats.rx_packets;
1728 netdev->stats.tx_packets = adapter->soft_stats.tx_packets;
1729 netdev->stats.rx_bytes = adapter->soft_stats.rx_bytes;
1730 netdev->stats.tx_bytes = adapter->soft_stats.tx_bytes;
1731 netdev->stats.multicast = adapter->soft_stats.multicast;
1732 netdev->stats.collisions = adapter->soft_stats.collisions;
1733 netdev->stats.rx_errors = adapter->soft_stats.rx_errors;
1734 netdev->stats.rx_over_errors =
1735 adapter->soft_stats.rx_missed_errors;
1736 netdev->stats.rx_length_errors =
1737 adapter->soft_stats.rx_length_errors;
1738 netdev->stats.rx_crc_errors = adapter->soft_stats.rx_crc_errors;
1739 netdev->stats.rx_frame_errors =
1740 adapter->soft_stats.rx_frame_errors;
1741 netdev->stats.rx_fifo_errors = adapter->soft_stats.rx_fifo_errors;
1742 netdev->stats.rx_missed_errors =
1743 adapter->soft_stats.rx_missed_errors;
1744 netdev->stats.tx_errors = adapter->soft_stats.tx_errors;
1745 netdev->stats.tx_fifo_errors = adapter->soft_stats.tx_fifo_errors;
1746 netdev->stats.tx_aborted_errors =
1747 adapter->soft_stats.tx_aborted_errors;
1748 netdev->stats.tx_window_errors =
1749 adapter->soft_stats.tx_window_errors;
1750 netdev->stats.tx_carrier_errors =
1751 adapter->soft_stats.tx_carrier_errors;
1752 }
1753
1754 static void atl1_update_mailbox(struct atl1_adapter *adapter)
1755 {
1756 unsigned long flags;
1757 u32 tpd_next_to_use;
1758 u32 rfd_next_to_use;
1759 u32 rrd_next_to_clean;
1760 u32 value;
1761
1762 spin_lock_irqsave(&adapter->mb_lock, flags);
1763
1764 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
1765 rfd_next_to_use = atomic_read(&adapter->rfd_ring.next_to_use);
1766 rrd_next_to_clean = atomic_read(&adapter->rrd_ring.next_to_clean);
1767
1768 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
1769 MB_RFD_PROD_INDX_SHIFT) |
1770 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
1771 MB_RRD_CONS_INDX_SHIFT) |
1772 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
1773 MB_TPD_PROD_INDX_SHIFT);
1774 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
1775
1776 spin_unlock_irqrestore(&adapter->mb_lock, flags);
1777 }
1778
1779 static void atl1_clean_alloc_flag(struct atl1_adapter *adapter,
1780 struct rx_return_desc *rrd, u16 offset)
1781 {
1782 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1783
1784 while (rfd_ring->next_to_clean != (rrd->buf_indx + offset)) {
1785 rfd_ring->buffer_info[rfd_ring->next_to_clean].alloced = 0;
1786 if (++rfd_ring->next_to_clean == rfd_ring->count) {
1787 rfd_ring->next_to_clean = 0;
1788 }
1789 }
1790 }
1791
1792 static void atl1_update_rfd_index(struct atl1_adapter *adapter,
1793 struct rx_return_desc *rrd)
1794 {
1795 u16 num_buf;
1796
1797 num_buf = (rrd->xsz.xsum_sz.pkt_size + adapter->rx_buffer_len - 1) /
1798 adapter->rx_buffer_len;
1799 if (rrd->num_buf == num_buf)
1800 /* clean alloc flag for bad rrd */
1801 atl1_clean_alloc_flag(adapter, rrd, num_buf);
1802 }
1803
1804 static void atl1_rx_checksum(struct atl1_adapter *adapter,
1805 struct rx_return_desc *rrd, struct sk_buff *skb)
1806 {
1807 struct pci_dev *pdev = adapter->pdev;
1808
1809 /*
1810 * The L1 hardware contains a bug that erroneously sets the
1811 * PACKET_FLAG_ERR and ERR_FLAG_L4_CHKSUM bits whenever a
1812 * fragmented IP packet is received, even though the packet
1813 * is perfectly valid and its checksum is correct. There's
1814 * no way to distinguish between one of these good packets
1815 * and a packet that actually contains a TCP/UDP checksum
1816 * error, so all we can do is allow it to be handed up to
1817 * the higher layers and let it be sorted out there.
1818 */
1819
1820 skb_checksum_none_assert(skb);
1821
1822 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
1823 if (rrd->err_flg & (ERR_FLAG_CRC | ERR_FLAG_TRUNC |
1824 ERR_FLAG_CODE | ERR_FLAG_OV)) {
1825 adapter->hw_csum_err++;
1826 if (netif_msg_rx_err(adapter))
1827 dev_printk(KERN_DEBUG, &pdev->dev,
1828 "rx checksum error\n");
1829 return;
1830 }
1831 }
1832
1833 /* not IPv4 */
1834 if (!(rrd->pkt_flg & PACKET_FLAG_IPV4))
1835 /* checksum is invalid, but it's not an IPv4 pkt, so ok */
1836 return;
1837
1838 /* IPv4 packet */
1839 if (likely(!(rrd->err_flg &
1840 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM)))) {
1841 skb->ip_summed = CHECKSUM_UNNECESSARY;
1842 adapter->hw_csum_good++;
1843 return;
1844 }
1845 }
1846
1847 /*
1848 * atl1_alloc_rx_buffers - Replace used receive buffers
1849 * @adapter: address of board private structure
1850 */
1851 static u16 atl1_alloc_rx_buffers(struct atl1_adapter *adapter)
1852 {
1853 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1854 struct pci_dev *pdev = adapter->pdev;
1855 struct page *page;
1856 unsigned long offset;
1857 struct atl1_buffer *buffer_info, *next_info;
1858 struct sk_buff *skb;
1859 u16 num_alloc = 0;
1860 u16 rfd_next_to_use, next_next;
1861 struct rx_free_desc *rfd_desc;
1862
1863 next_next = rfd_next_to_use = atomic_read(&rfd_ring->next_to_use);
1864 if (++next_next == rfd_ring->count)
1865 next_next = 0;
1866 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1867 next_info = &rfd_ring->buffer_info[next_next];
1868
1869 while (!buffer_info->alloced && !next_info->alloced) {
1870 if (buffer_info->skb) {
1871 buffer_info->alloced = 1;
1872 goto next;
1873 }
1874
1875 rfd_desc = ATL1_RFD_DESC(rfd_ring, rfd_next_to_use);
1876
1877 skb = netdev_alloc_skb_ip_align(adapter->netdev,
1878 adapter->rx_buffer_len);
1879 if (unlikely(!skb)) {
1880 /* Better luck next round */
1881 adapter->netdev->stats.rx_dropped++;
1882 break;
1883 }
1884
1885 buffer_info->alloced = 1;
1886 buffer_info->skb = skb;
1887 buffer_info->length = (u16) adapter->rx_buffer_len;
1888 page = virt_to_page(skb->data);
1889 offset = (unsigned long)skb->data & ~PAGE_MASK;
1890 buffer_info->dma = pci_map_page(pdev, page, offset,
1891 adapter->rx_buffer_len,
1892 PCI_DMA_FROMDEVICE);
1893 rfd_desc->buffer_addr = cpu_to_le64(buffer_info->dma);
1894 rfd_desc->buf_len = cpu_to_le16(adapter->rx_buffer_len);
1895 rfd_desc->coalese = 0;
1896
1897 next:
1898 rfd_next_to_use = next_next;
1899 if (unlikely(++next_next == rfd_ring->count))
1900 next_next = 0;
1901
1902 buffer_info = &rfd_ring->buffer_info[rfd_next_to_use];
1903 next_info = &rfd_ring->buffer_info[next_next];
1904 num_alloc++;
1905 }
1906
1907 if (num_alloc) {
1908 /*
1909 * Force memory writes to complete before letting h/w
1910 * know there are new descriptors to fetch. (Only
1911 * applicable for weak-ordered memory model archs,
1912 * such as IA-64).
1913 */
1914 wmb();
1915 atomic_set(&rfd_ring->next_to_use, (int)rfd_next_to_use);
1916 }
1917 return num_alloc;
1918 }
1919
1920 static int atl1_intr_rx(struct atl1_adapter *adapter, int budget)
1921 {
1922 int i, count;
1923 u16 length;
1924 u16 rrd_next_to_clean;
1925 u32 value;
1926 struct atl1_rfd_ring *rfd_ring = &adapter->rfd_ring;
1927 struct atl1_rrd_ring *rrd_ring = &adapter->rrd_ring;
1928 struct atl1_buffer *buffer_info;
1929 struct rx_return_desc *rrd;
1930 struct sk_buff *skb;
1931
1932 count = 0;
1933
1934 rrd_next_to_clean = atomic_read(&rrd_ring->next_to_clean);
1935
1936 while (count < budget) {
1937 rrd = ATL1_RRD_DESC(rrd_ring, rrd_next_to_clean);
1938 i = 1;
1939 if (likely(rrd->xsz.valid)) { /* packet valid */
1940 chk_rrd:
1941 /* check rrd status */
1942 if (likely(rrd->num_buf == 1))
1943 goto rrd_ok;
1944 else if (netif_msg_rx_err(adapter)) {
1945 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1946 "unexpected RRD buffer count\n");
1947 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1948 "rx_buf_len = %d\n",
1949 adapter->rx_buffer_len);
1950 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1951 "RRD num_buf = %d\n",
1952 rrd->num_buf);
1953 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1954 "RRD pkt_len = %d\n",
1955 rrd->xsz.xsum_sz.pkt_size);
1956 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1957 "RRD pkt_flg = 0x%08X\n",
1958 rrd->pkt_flg);
1959 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1960 "RRD err_flg = 0x%08X\n",
1961 rrd->err_flg);
1962 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1963 "RRD vlan_tag = 0x%08X\n",
1964 rrd->vlan_tag);
1965 }
1966
1967 /* rrd seems to be bad */
1968 if (unlikely(i-- > 0)) {
1969 /* rrd may not be DMAed completely */
1970 udelay(1);
1971 goto chk_rrd;
1972 }
1973 /* bad rrd */
1974 if (netif_msg_rx_err(adapter))
1975 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
1976 "bad RRD\n");
1977 /* see if update RFD index */
1978 if (rrd->num_buf > 1)
1979 atl1_update_rfd_index(adapter, rrd);
1980
1981 /* update rrd */
1982 rrd->xsz.valid = 0;
1983 if (++rrd_next_to_clean == rrd_ring->count)
1984 rrd_next_to_clean = 0;
1985 count++;
1986 continue;
1987 } else { /* current rrd still not be updated */
1988
1989 break;
1990 }
1991 rrd_ok:
1992 /* clean alloc flag for bad rrd */
1993 atl1_clean_alloc_flag(adapter, rrd, 0);
1994
1995 buffer_info = &rfd_ring->buffer_info[rrd->buf_indx];
1996 if (++rfd_ring->next_to_clean == rfd_ring->count)
1997 rfd_ring->next_to_clean = 0;
1998
1999 /* update rrd next to clean */
2000 if (++rrd_next_to_clean == rrd_ring->count)
2001 rrd_next_to_clean = 0;
2002 count++;
2003
2004 if (unlikely(rrd->pkt_flg & PACKET_FLAG_ERR)) {
2005 if (!(rrd->err_flg &
2006 (ERR_FLAG_IP_CHKSUM | ERR_FLAG_L4_CHKSUM
2007 | ERR_FLAG_LEN))) {
2008 /* packet error, don't need upstream */
2009 buffer_info->alloced = 0;
2010 rrd->xsz.valid = 0;
2011 continue;
2012 }
2013 }
2014
2015 /* Good Receive */
2016 pci_unmap_page(adapter->pdev, buffer_info->dma,
2017 buffer_info->length, PCI_DMA_FROMDEVICE);
2018 buffer_info->dma = 0;
2019 skb = buffer_info->skb;
2020 length = le16_to_cpu(rrd->xsz.xsum_sz.pkt_size);
2021
2022 skb_put(skb, length - ETH_FCS_LEN);
2023
2024 /* Receive Checksum Offload */
2025 atl1_rx_checksum(adapter, rrd, skb);
2026 skb->protocol = eth_type_trans(skb, adapter->netdev);
2027
2028 if (rrd->pkt_flg & PACKET_FLAG_VLAN_INS) {
2029 u16 vlan_tag = (rrd->vlan_tag >> 4) |
2030 ((rrd->vlan_tag & 7) << 13) |
2031 ((rrd->vlan_tag & 8) << 9);
2032
2033 __vlan_hwaccel_put_tag(skb, vlan_tag);
2034 }
2035 netif_receive_skb(skb);
2036
2037 /* let protocol layer free skb */
2038 buffer_info->skb = NULL;
2039 buffer_info->alloced = 0;
2040 rrd->xsz.valid = 0;
2041 }
2042
2043 atomic_set(&rrd_ring->next_to_clean, rrd_next_to_clean);
2044
2045 atl1_alloc_rx_buffers(adapter);
2046
2047 /* update mailbox ? */
2048 if (count) {
2049 u32 tpd_next_to_use;
2050 u32 rfd_next_to_use;
2051
2052 spin_lock(&adapter->mb_lock);
2053
2054 tpd_next_to_use = atomic_read(&adapter->tpd_ring.next_to_use);
2055 rfd_next_to_use =
2056 atomic_read(&adapter->rfd_ring.next_to_use);
2057 rrd_next_to_clean =
2058 atomic_read(&adapter->rrd_ring.next_to_clean);
2059 value = ((rfd_next_to_use & MB_RFD_PROD_INDX_MASK) <<
2060 MB_RFD_PROD_INDX_SHIFT) |
2061 ((rrd_next_to_clean & MB_RRD_CONS_INDX_MASK) <<
2062 MB_RRD_CONS_INDX_SHIFT) |
2063 ((tpd_next_to_use & MB_TPD_PROD_INDX_MASK) <<
2064 MB_TPD_PROD_INDX_SHIFT);
2065 iowrite32(value, adapter->hw.hw_addr + REG_MAILBOX);
2066 spin_unlock(&adapter->mb_lock);
2067 }
2068
2069 return count;
2070 }
2071
2072 static int atl1_intr_tx(struct atl1_adapter *adapter)
2073 {
2074 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2075 struct atl1_buffer *buffer_info;
2076 u16 sw_tpd_next_to_clean;
2077 u16 cmb_tpd_next_to_clean;
2078 int count = 0;
2079
2080 sw_tpd_next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2081 cmb_tpd_next_to_clean = le16_to_cpu(adapter->cmb.cmb->tpd_cons_idx);
2082
2083 while (cmb_tpd_next_to_clean != sw_tpd_next_to_clean) {
2084 buffer_info = &tpd_ring->buffer_info[sw_tpd_next_to_clean];
2085 if (buffer_info->dma) {
2086 pci_unmap_page(adapter->pdev, buffer_info->dma,
2087 buffer_info->length, PCI_DMA_TODEVICE);
2088 buffer_info->dma = 0;
2089 }
2090
2091 if (buffer_info->skb) {
2092 dev_kfree_skb_irq(buffer_info->skb);
2093 buffer_info->skb = NULL;
2094 }
2095
2096 if (++sw_tpd_next_to_clean == tpd_ring->count)
2097 sw_tpd_next_to_clean = 0;
2098
2099 count++;
2100 }
2101 atomic_set(&tpd_ring->next_to_clean, sw_tpd_next_to_clean);
2102
2103 if (netif_queue_stopped(adapter->netdev) &&
2104 netif_carrier_ok(adapter->netdev))
2105 netif_wake_queue(adapter->netdev);
2106
2107 return count;
2108 }
2109
2110 static u16 atl1_tpd_avail(struct atl1_tpd_ring *tpd_ring)
2111 {
2112 u16 next_to_clean = atomic_read(&tpd_ring->next_to_clean);
2113 u16 next_to_use = atomic_read(&tpd_ring->next_to_use);
2114 return (next_to_clean > next_to_use) ?
2115 next_to_clean - next_to_use - 1 :
2116 tpd_ring->count + next_to_clean - next_to_use - 1;
2117 }
2118
2119 static int atl1_tso(struct atl1_adapter *adapter, struct sk_buff *skb,
2120 struct tx_packet_desc *ptpd)
2121 {
2122 u8 hdr_len, ip_off;
2123 u32 real_len;
2124 int err;
2125
2126 if (skb_shinfo(skb)->gso_size) {
2127 if (skb_header_cloned(skb)) {
2128 err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
2129 if (unlikely(err))
2130 return -1;
2131 }
2132
2133 if (skb->protocol == htons(ETH_P_IP)) {
2134 struct iphdr *iph = ip_hdr(skb);
2135
2136 real_len = (((unsigned char *)iph - skb->data) +
2137 ntohs(iph->tot_len));
2138 if (real_len < skb->len)
2139 pskb_trim(skb, real_len);
2140 hdr_len = (skb_transport_offset(skb) + tcp_hdrlen(skb));
2141 if (skb->len == hdr_len) {
2142 iph->check = 0;
2143 tcp_hdr(skb)->check =
2144 ~csum_tcpudp_magic(iph->saddr,
2145 iph->daddr, tcp_hdrlen(skb),
2146 IPPROTO_TCP, 0);
2147 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2148 TPD_IPHL_SHIFT;
2149 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2150 TPD_TCPHDRLEN_MASK) <<
2151 TPD_TCPHDRLEN_SHIFT;
2152 ptpd->word3 |= 1 << TPD_IP_CSUM_SHIFT;
2153 ptpd->word3 |= 1 << TPD_TCP_CSUM_SHIFT;
2154 return 1;
2155 }
2156
2157 iph->check = 0;
2158 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
2159 iph->daddr, 0, IPPROTO_TCP, 0);
2160 ip_off = (unsigned char *)iph -
2161 (unsigned char *) skb_network_header(skb);
2162 if (ip_off == 8) /* 802.3-SNAP frame */
2163 ptpd->word3 |= 1 << TPD_ETHTYPE_SHIFT;
2164 else if (ip_off != 0)
2165 return -2;
2166
2167 ptpd->word3 |= (iph->ihl & TPD_IPHL_MASK) <<
2168 TPD_IPHL_SHIFT;
2169 ptpd->word3 |= ((tcp_hdrlen(skb) >> 2) &
2170 TPD_TCPHDRLEN_MASK) << TPD_TCPHDRLEN_SHIFT;
2171 ptpd->word3 |= (skb_shinfo(skb)->gso_size &
2172 TPD_MSS_MASK) << TPD_MSS_SHIFT;
2173 ptpd->word3 |= 1 << TPD_SEGMENT_EN_SHIFT;
2174 return 3;
2175 }
2176 }
2177 return false;
2178 }
2179
2180 static int atl1_tx_csum(struct atl1_adapter *adapter, struct sk_buff *skb,
2181 struct tx_packet_desc *ptpd)
2182 {
2183 u8 css, cso;
2184
2185 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2186 css = skb_checksum_start_offset(skb);
2187 cso = css + (u8) skb->csum_offset;
2188 if (unlikely(css & 0x1)) {
2189 /* L1 hardware requires an even number here */
2190 if (netif_msg_tx_err(adapter))
2191 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2192 "payload offset not an even number\n");
2193 return -1;
2194 }
2195 ptpd->word3 |= (css & TPD_PLOADOFFSET_MASK) <<
2196 TPD_PLOADOFFSET_SHIFT;
2197 ptpd->word3 |= (cso & TPD_CCSUMOFFSET_MASK) <<
2198 TPD_CCSUMOFFSET_SHIFT;
2199 ptpd->word3 |= 1 << TPD_CUST_CSUM_EN_SHIFT;
2200 return true;
2201 }
2202 return 0;
2203 }
2204
2205 static void atl1_tx_map(struct atl1_adapter *adapter, struct sk_buff *skb,
2206 struct tx_packet_desc *ptpd)
2207 {
2208 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2209 struct atl1_buffer *buffer_info;
2210 u16 buf_len = skb->len;
2211 struct page *page;
2212 unsigned long offset;
2213 unsigned int nr_frags;
2214 unsigned int f;
2215 int retval;
2216 u16 next_to_use;
2217 u16 data_len;
2218 u8 hdr_len;
2219
2220 buf_len -= skb->data_len;
2221 nr_frags = skb_shinfo(skb)->nr_frags;
2222 next_to_use = atomic_read(&tpd_ring->next_to_use);
2223 buffer_info = &tpd_ring->buffer_info[next_to_use];
2224 BUG_ON(buffer_info->skb);
2225 /* put skb in last TPD */
2226 buffer_info->skb = NULL;
2227
2228 retval = (ptpd->word3 >> TPD_SEGMENT_EN_SHIFT) & TPD_SEGMENT_EN_MASK;
2229 if (retval) {
2230 /* TSO */
2231 hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
2232 buffer_info->length = hdr_len;
2233 page = virt_to_page(skb->data);
2234 offset = (unsigned long)skb->data & ~PAGE_MASK;
2235 buffer_info->dma = pci_map_page(adapter->pdev, page,
2236 offset, hdr_len,
2237 PCI_DMA_TODEVICE);
2238
2239 if (++next_to_use == tpd_ring->count)
2240 next_to_use = 0;
2241
2242 if (buf_len > hdr_len) {
2243 int i, nseg;
2244
2245 data_len = buf_len - hdr_len;
2246 nseg = (data_len + ATL1_MAX_TX_BUF_LEN - 1) /
2247 ATL1_MAX_TX_BUF_LEN;
2248 for (i = 0; i < nseg; i++) {
2249 buffer_info =
2250 &tpd_ring->buffer_info[next_to_use];
2251 buffer_info->skb = NULL;
2252 buffer_info->length =
2253 (ATL1_MAX_TX_BUF_LEN >=
2254 data_len) ? ATL1_MAX_TX_BUF_LEN : data_len;
2255 data_len -= buffer_info->length;
2256 page = virt_to_page(skb->data +
2257 (hdr_len + i * ATL1_MAX_TX_BUF_LEN));
2258 offset = (unsigned long)(skb->data +
2259 (hdr_len + i * ATL1_MAX_TX_BUF_LEN)) &
2260 ~PAGE_MASK;
2261 buffer_info->dma = pci_map_page(adapter->pdev,
2262 page, offset, buffer_info->length,
2263 PCI_DMA_TODEVICE);
2264 if (++next_to_use == tpd_ring->count)
2265 next_to_use = 0;
2266 }
2267 }
2268 } else {
2269 /* not TSO */
2270 buffer_info->length = buf_len;
2271 page = virt_to_page(skb->data);
2272 offset = (unsigned long)skb->data & ~PAGE_MASK;
2273 buffer_info->dma = pci_map_page(adapter->pdev, page,
2274 offset, buf_len, PCI_DMA_TODEVICE);
2275 if (++next_to_use == tpd_ring->count)
2276 next_to_use = 0;
2277 }
2278
2279 for (f = 0; f < nr_frags; f++) {
2280 const struct skb_frag_struct *frag;
2281 u16 i, nseg;
2282
2283 frag = &skb_shinfo(skb)->frags[f];
2284 buf_len = skb_frag_size(frag);
2285
2286 nseg = (buf_len + ATL1_MAX_TX_BUF_LEN - 1) /
2287 ATL1_MAX_TX_BUF_LEN;
2288 for (i = 0; i < nseg; i++) {
2289 buffer_info = &tpd_ring->buffer_info[next_to_use];
2290 BUG_ON(buffer_info->skb);
2291
2292 buffer_info->skb = NULL;
2293 buffer_info->length = (buf_len > ATL1_MAX_TX_BUF_LEN) ?
2294 ATL1_MAX_TX_BUF_LEN : buf_len;
2295 buf_len -= buffer_info->length;
2296 buffer_info->dma = skb_frag_dma_map(&adapter->pdev->dev,
2297 frag, i * ATL1_MAX_TX_BUF_LEN,
2298 buffer_info->length, DMA_TO_DEVICE);
2299
2300 if (++next_to_use == tpd_ring->count)
2301 next_to_use = 0;
2302 }
2303 }
2304
2305 /* last tpd's buffer-info */
2306 buffer_info->skb = skb;
2307 }
2308
2309 static void atl1_tx_queue(struct atl1_adapter *adapter, u16 count,
2310 struct tx_packet_desc *ptpd)
2311 {
2312 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2313 struct atl1_buffer *buffer_info;
2314 struct tx_packet_desc *tpd;
2315 u16 j;
2316 u32 val;
2317 u16 next_to_use = (u16) atomic_read(&tpd_ring->next_to_use);
2318
2319 for (j = 0; j < count; j++) {
2320 buffer_info = &tpd_ring->buffer_info[next_to_use];
2321 tpd = ATL1_TPD_DESC(&adapter->tpd_ring, next_to_use);
2322 if (tpd != ptpd)
2323 memcpy(tpd, ptpd, sizeof(struct tx_packet_desc));
2324 tpd->buffer_addr = cpu_to_le64(buffer_info->dma);
2325 tpd->word2 &= ~(TPD_BUFLEN_MASK << TPD_BUFLEN_SHIFT);
2326 tpd->word2 |= (cpu_to_le16(buffer_info->length) &
2327 TPD_BUFLEN_MASK) << TPD_BUFLEN_SHIFT;
2328
2329 /*
2330 * if this is the first packet in a TSO chain, set
2331 * TPD_HDRFLAG, otherwise, clear it.
2332 */
2333 val = (tpd->word3 >> TPD_SEGMENT_EN_SHIFT) &
2334 TPD_SEGMENT_EN_MASK;
2335 if (val) {
2336 if (!j)
2337 tpd->word3 |= 1 << TPD_HDRFLAG_SHIFT;
2338 else
2339 tpd->word3 &= ~(1 << TPD_HDRFLAG_SHIFT);
2340 }
2341
2342 if (j == (count - 1))
2343 tpd->word3 |= 1 << TPD_EOP_SHIFT;
2344
2345 if (++next_to_use == tpd_ring->count)
2346 next_to_use = 0;
2347 }
2348 /*
2349 * Force memory writes to complete before letting h/w
2350 * know there are new descriptors to fetch. (Only
2351 * applicable for weak-ordered memory model archs,
2352 * such as IA-64).
2353 */
2354 wmb();
2355
2356 atomic_set(&tpd_ring->next_to_use, next_to_use);
2357 }
2358
2359 static netdev_tx_t atl1_xmit_frame(struct sk_buff *skb,
2360 struct net_device *netdev)
2361 {
2362 struct atl1_adapter *adapter = netdev_priv(netdev);
2363 struct atl1_tpd_ring *tpd_ring = &adapter->tpd_ring;
2364 int len;
2365 int tso;
2366 int count = 1;
2367 int ret_val;
2368 struct tx_packet_desc *ptpd;
2369 u16 vlan_tag;
2370 unsigned int nr_frags = 0;
2371 unsigned int mss = 0;
2372 unsigned int f;
2373 unsigned int proto_hdr_len;
2374
2375 len = skb_headlen(skb);
2376
2377 if (unlikely(skb->len <= 0)) {
2378 dev_kfree_skb_any(skb);
2379 return NETDEV_TX_OK;
2380 }
2381
2382 nr_frags = skb_shinfo(skb)->nr_frags;
2383 for (f = 0; f < nr_frags; f++) {
2384 unsigned int f_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2385 count += (f_size + ATL1_MAX_TX_BUF_LEN - 1) /
2386 ATL1_MAX_TX_BUF_LEN;
2387 }
2388
2389 mss = skb_shinfo(skb)->gso_size;
2390 if (mss) {
2391 if (skb->protocol == htons(ETH_P_IP)) {
2392 proto_hdr_len = (skb_transport_offset(skb) +
2393 tcp_hdrlen(skb));
2394 if (unlikely(proto_hdr_len > len)) {
2395 dev_kfree_skb_any(skb);
2396 return NETDEV_TX_OK;
2397 }
2398 /* need additional TPD ? */
2399 if (proto_hdr_len != len)
2400 count += (len - proto_hdr_len +
2401 ATL1_MAX_TX_BUF_LEN - 1) /
2402 ATL1_MAX_TX_BUF_LEN;
2403 }
2404 }
2405
2406 if (atl1_tpd_avail(&adapter->tpd_ring) < count) {
2407 /* not enough descriptors */
2408 netif_stop_queue(netdev);
2409 if (netif_msg_tx_queued(adapter))
2410 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2411 "tx busy\n");
2412 return NETDEV_TX_BUSY;
2413 }
2414
2415 ptpd = ATL1_TPD_DESC(tpd_ring,
2416 (u16) atomic_read(&tpd_ring->next_to_use));
2417 memset(ptpd, 0, sizeof(struct tx_packet_desc));
2418
2419 if (vlan_tx_tag_present(skb)) {
2420 vlan_tag = vlan_tx_tag_get(skb);
2421 vlan_tag = (vlan_tag << 4) | (vlan_tag >> 13) |
2422 ((vlan_tag >> 9) & 0x8);
2423 ptpd->word3 |= 1 << TPD_INS_VL_TAG_SHIFT;
2424 ptpd->word2 |= (vlan_tag & TPD_VLANTAG_MASK) <<
2425 TPD_VLANTAG_SHIFT;
2426 }
2427
2428 tso = atl1_tso(adapter, skb, ptpd);
2429 if (tso < 0) {
2430 dev_kfree_skb_any(skb);
2431 return NETDEV_TX_OK;
2432 }
2433
2434 if (!tso) {
2435 ret_val = atl1_tx_csum(adapter, skb, ptpd);
2436 if (ret_val < 0) {
2437 dev_kfree_skb_any(skb);
2438 return NETDEV_TX_OK;
2439 }
2440 }
2441
2442 atl1_tx_map(adapter, skb, ptpd);
2443 atl1_tx_queue(adapter, count, ptpd);
2444 atl1_update_mailbox(adapter);
2445 mmiowb();
2446 return NETDEV_TX_OK;
2447 }
2448
2449 static int atl1_rings_clean(struct napi_struct *napi, int budget)
2450 {
2451 struct atl1_adapter *adapter = container_of(napi, struct atl1_adapter, napi);
2452 int work_done = atl1_intr_rx(adapter, budget);
2453
2454 if (atl1_intr_tx(adapter))
2455 work_done = budget;
2456
2457 /* Let's come again to process some more packets */
2458 if (work_done >= budget)
2459 return work_done;
2460
2461 napi_complete(napi);
2462 /* re-enable Interrupt */
2463 if (likely(adapter->int_enabled))
2464 atlx_imr_set(adapter, IMR_NORMAL_MASK);
2465 return work_done;
2466 }
2467
2468 static inline int atl1_sched_rings_clean(struct atl1_adapter* adapter)
2469 {
2470 if (!napi_schedule_prep(&adapter->napi))
2471 /* It is possible in case even the RX/TX ints are disabled via IMR
2472 * register the ISR bits are set anyway (but do not produce IRQ).
2473 * To handle such situation the napi functions used to check is
2474 * something scheduled or not.
2475 */
2476 return 0;
2477
2478 __napi_schedule(&adapter->napi);
2479
2480 /*
2481 * Disable RX/TX ints via IMR register if it is
2482 * allowed. NAPI handler must reenable them in same
2483 * way.
2484 */
2485 if (!adapter->int_enabled)
2486 return 1;
2487
2488 atlx_imr_set(adapter, IMR_NORXTX_MASK);
2489 return 1;
2490 }
2491
2492 /*
2493 * atl1_intr - Interrupt Handler
2494 * @irq: interrupt number
2495 * @data: pointer to a network interface device structure
2496 * @pt_regs: CPU registers structure
2497 */
2498 static irqreturn_t atl1_intr(int irq, void *data)
2499 {
2500 struct atl1_adapter *adapter = netdev_priv(data);
2501 u32 status;
2502
2503 status = adapter->cmb.cmb->int_stats;
2504 if (!status)
2505 return IRQ_NONE;
2506
2507 /* clear CMB interrupt status at once,
2508 * but leave rx/tx interrupt status in case it should be dropped
2509 * only if rx/tx processing queued. In other case interrupt
2510 * can be lost.
2511 */
2512 adapter->cmb.cmb->int_stats = status & (ISR_CMB_TX | ISR_CMB_RX);
2513
2514 if (status & ISR_GPHY) /* clear phy status */
2515 atlx_clear_phy_int(adapter);
2516
2517 /* clear ISR status, and Enable CMB DMA/Disable Interrupt */
2518 iowrite32(status | ISR_DIS_INT, adapter->hw.hw_addr + REG_ISR);
2519
2520 /* check if SMB intr */
2521 if (status & ISR_SMB)
2522 atl1_inc_smb(adapter);
2523
2524 /* check if PCIE PHY Link down */
2525 if (status & ISR_PHY_LINKDOWN) {
2526 if (netif_msg_intr(adapter))
2527 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2528 "pcie phy link down %x\n", status);
2529 if (netif_running(adapter->netdev)) { /* reset MAC */
2530 atlx_irq_disable(adapter);
2531 schedule_work(&adapter->reset_dev_task);
2532 return IRQ_HANDLED;
2533 }
2534 }
2535
2536 /* check if DMA read/write error ? */
2537 if (status & (ISR_DMAR_TO_RST | ISR_DMAW_TO_RST)) {
2538 if (netif_msg_intr(adapter))
2539 dev_printk(KERN_DEBUG, &adapter->pdev->dev,
2540 "pcie DMA r/w error (status = 0x%x)\n",
2541 status);
2542 atlx_irq_disable(adapter);
2543 schedule_work(&adapter->reset_dev_task);
2544 return IRQ_HANDLED;
2545 }
2546
2547 /* link event */
2548 if (status & ISR_GPHY) {
2549 adapter->soft_stats.tx_carrier_errors++;
2550 atl1_check_for_link(adapter);
2551 }
2552
2553 /* transmit or receive event */
2554 if (status & (ISR_CMB_TX | ISR_CMB_RX) &&
2555 atl1_sched_rings_clean(adapter))
2556 adapter->cmb.cmb->int_stats = adapter->cmb.cmb->int_stats &
2557 ~(ISR_CMB_TX | ISR_CMB_RX);
2558
2559 /* rx exception */
2560 if (unlikely(status & (ISR_RXF_OV | ISR_RFD_UNRUN |
2561 ISR_RRD_OV | ISR_HOST_RFD_UNRUN |
2562 ISR_HOST_RRD_OV))) {
2563 if (netif_msg_intr(adapter))
2564 dev_printk(KERN_DEBUG,
2565 &adapter->pdev->dev,
2566 "rx exception, ISR = 0x%x\n",
2567 status);
2568 atl1_sched_rings_clean(adapter);
2569 }
2570
2571 /* re-enable Interrupt */
2572 iowrite32(ISR_DIS_SMB | ISR_DIS_DMA, adapter->hw.hw_addr + REG_ISR);
2573 return IRQ_HANDLED;
2574 }
2575
2576
2577 /*
2578 * atl1_phy_config - Timer Call-back
2579 * @data: pointer to netdev cast into an unsigned long
2580 */
2581 static void atl1_phy_config(unsigned long data)
2582 {
2583 struct atl1_adapter *adapter = (struct atl1_adapter *)data;
2584 struct atl1_hw *hw = &adapter->hw;
2585 unsigned long flags;
2586
2587 spin_lock_irqsave(&adapter->lock, flags);
2588 adapter->phy_timer_pending = false;
2589 atl1_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
2590 atl1_write_phy_reg(hw, MII_ATLX_CR, hw->mii_1000t_ctrl_reg);
2591 atl1_write_phy_reg(hw, MII_BMCR, MII_CR_RESET | MII_CR_AUTO_NEG_EN);
2592 spin_unlock_irqrestore(&adapter->lock, flags);
2593 }
2594
2595 /*
2596 * Orphaned vendor comment left intact here:
2597 * <vendor comment>
2598 * If TPD Buffer size equal to 0, PCIE DMAR_TO_INT
2599 * will assert. We do soft reset <0x1400=1> according
2600 * with the SPEC. BUT, it seemes that PCIE or DMA
2601 * state-machine will not be reset. DMAR_TO_INT will
2602 * assert again and again.
2603 * </vendor comment>
2604 */
2605
2606 static int atl1_reset(struct atl1_adapter *adapter)
2607 {
2608 int ret;
2609 ret = atl1_reset_hw(&adapter->hw);
2610 if (ret)
2611 return ret;
2612 return atl1_init_hw(&adapter->hw);
2613 }
2614
2615 static s32 atl1_up(struct atl1_adapter *adapter)
2616 {
2617 struct net_device *netdev = adapter->netdev;
2618 int err;
2619 int irq_flags = 0;
2620
2621 /* hardware has been reset, we need to reload some things */
2622 atlx_set_multi(netdev);
2623 atl1_init_ring_ptrs(adapter);
2624 atlx_restore_vlan(adapter);
2625 err = atl1_alloc_rx_buffers(adapter);
2626 if (unlikely(!err))
2627 /* no RX BUFFER allocated */
2628 return -ENOMEM;
2629
2630 if (unlikely(atl1_configure(adapter))) {
2631 err = -EIO;
2632 goto err_up;
2633 }
2634
2635 err = pci_enable_msi(adapter->pdev);
2636 if (err) {
2637 if (netif_msg_ifup(adapter))
2638 dev_info(&adapter->pdev->dev,
2639 "Unable to enable MSI: %d\n", err);
2640 irq_flags |= IRQF_SHARED;
2641 }
2642
2643 err = request_irq(adapter->pdev->irq, atl1_intr, irq_flags,
2644 netdev->name, netdev);
2645 if (unlikely(err))
2646 goto err_up;
2647
2648 napi_enable(&adapter->napi);
2649 atlx_irq_enable(adapter);
2650 atl1_check_link(adapter);
2651 netif_start_queue(netdev);
2652 return 0;
2653
2654 err_up:
2655 pci_disable_msi(adapter->pdev);
2656 /* free rx_buffers */
2657 atl1_clean_rx_ring(adapter);
2658 return err;
2659 }
2660
2661 static void atl1_down(struct atl1_adapter *adapter)
2662 {
2663 struct net_device *netdev = adapter->netdev;
2664
2665 napi_disable(&adapter->napi);
2666 netif_stop_queue(netdev);
2667 del_timer_sync(&adapter->phy_config_timer);
2668 adapter->phy_timer_pending = false;
2669
2670 atlx_irq_disable(adapter);
2671 free_irq(adapter->pdev->irq, netdev);
2672 pci_disable_msi(adapter->pdev);
2673 atl1_reset_hw(&adapter->hw);
2674 adapter->cmb.cmb->int_stats = 0;
2675
2676 adapter->link_speed = SPEED_0;
2677 adapter->link_duplex = -1;
2678 netif_carrier_off(netdev);
2679
2680 atl1_clean_tx_ring(adapter);
2681 atl1_clean_rx_ring(adapter);
2682 }
2683
2684 static void atl1_reset_dev_task(struct work_struct *work)
2685 {
2686 struct atl1_adapter *adapter =
2687 container_of(work, struct atl1_adapter, reset_dev_task);
2688 struct net_device *netdev = adapter->netdev;
2689
2690 netif_device_detach(netdev);
2691 atl1_down(adapter);
2692 atl1_up(adapter);
2693 netif_device_attach(netdev);
2694 }
2695
2696 /*
2697 * atl1_change_mtu - Change the Maximum Transfer Unit
2698 * @netdev: network interface device structure
2699 * @new_mtu: new value for maximum frame size
2700 *
2701 * Returns 0 on success, negative on failure
2702 */
2703 static int atl1_change_mtu(struct net_device *netdev, int new_mtu)
2704 {
2705 struct atl1_adapter *adapter = netdev_priv(netdev);
2706 int old_mtu = netdev->mtu;
2707 int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
2708
2709 if ((max_frame < ETH_ZLEN + ETH_FCS_LEN) ||
2710 (max_frame > MAX_JUMBO_FRAME_SIZE)) {
2711 if (netif_msg_link(adapter))
2712 dev_warn(&adapter->pdev->dev, "invalid MTU setting\n");
2713 return -EINVAL;
2714 }
2715
2716 adapter->hw.max_frame_size = max_frame;
2717 adapter->hw.tx_jumbo_task_th = (max_frame + 7) >> 3;
2718 adapter->rx_buffer_len = (max_frame + 7) & ~7;
2719 adapter->hw.rx_jumbo_th = adapter->rx_buffer_len / 8;
2720
2721 netdev->mtu = new_mtu;
2722 if ((old_mtu != new_mtu) && netif_running(netdev)) {
2723 atl1_down(adapter);
2724 atl1_up(adapter);
2725 }
2726
2727 return 0;
2728 }
2729
2730 /*
2731 * atl1_open - Called when a network interface is made active
2732 * @netdev: network interface device structure
2733 *
2734 * Returns 0 on success, negative value on failure
2735 *
2736 * The open entry point is called when a network interface is made
2737 * active by the system (IFF_UP). At this point all resources needed
2738 * for transmit and receive operations are allocated, the interrupt
2739 * handler is registered with the OS, the watchdog timer is started,
2740 * and the stack is notified that the interface is ready.
2741 */
2742 static int atl1_open(struct net_device *netdev)
2743 {
2744 struct atl1_adapter *adapter = netdev_priv(netdev);
2745 int err;
2746
2747 netif_carrier_off(netdev);
2748
2749 /* allocate transmit descriptors */
2750 err = atl1_setup_ring_resources(adapter);
2751 if (err)
2752 return err;
2753
2754 err = atl1_up(adapter);
2755 if (err)
2756 goto err_up;
2757
2758 return 0;
2759
2760 err_up:
2761 atl1_reset(adapter);
2762 return err;
2763 }
2764
2765 /*
2766 * atl1_close - Disables a network interface
2767 * @netdev: network interface device structure
2768 *
2769 * Returns 0, this is not allowed to fail
2770 *
2771 * The close entry point is called when an interface is de-activated
2772 * by the OS. The hardware is still under the drivers control, but
2773 * needs to be disabled. A global MAC reset is issued to stop the
2774 * hardware, and all transmit and receive resources are freed.
2775 */
2776 static int atl1_close(struct net_device *netdev)
2777 {
2778 struct atl1_adapter *adapter = netdev_priv(netdev);
2779 atl1_down(adapter);
2780 atl1_free_ring_resources(adapter);
2781 return 0;
2782 }
2783
2784 #ifdef CONFIG_PM
2785 static int atl1_suspend(struct device *dev)
2786 {
2787 struct pci_dev *pdev = to_pci_dev(dev);
2788 struct net_device *netdev = pci_get_drvdata(pdev);
2789 struct atl1_adapter *adapter = netdev_priv(netdev);
2790 struct atl1_hw *hw = &adapter->hw;
2791 u32 ctrl = 0;
2792 u32 wufc = adapter->wol;
2793 u32 val;
2794 u16 speed;
2795 u16 duplex;
2796
2797 netif_device_detach(netdev);
2798 if (netif_running(netdev))
2799 atl1_down(adapter);
2800
2801 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2802 atl1_read_phy_reg(hw, MII_BMSR, (u16 *) & ctrl);
2803 val = ctrl & BMSR_LSTATUS;
2804 if (val)
2805 wufc &= ~ATLX_WUFC_LNKC;
2806 if (!wufc)
2807 goto disable_wol;
2808
2809 if (val) {
2810 val = atl1_get_speed_and_duplex(hw, &speed, &duplex);
2811 if (val) {
2812 if (netif_msg_ifdown(adapter))
2813 dev_printk(KERN_DEBUG, &pdev->dev,
2814 "error getting speed/duplex\n");
2815 goto disable_wol;
2816 }
2817
2818 ctrl = 0;
2819
2820 /* enable magic packet WOL */
2821 if (wufc & ATLX_WUFC_MAG)
2822 ctrl |= (WOL_MAGIC_EN | WOL_MAGIC_PME_EN);
2823 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2824 ioread32(hw->hw_addr + REG_WOL_CTRL);
2825
2826 /* configure the mac */
2827 ctrl = MAC_CTRL_RX_EN;
2828 ctrl |= ((u32)((speed == SPEED_1000) ? MAC_CTRL_SPEED_1000 :
2829 MAC_CTRL_SPEED_10_100) << MAC_CTRL_SPEED_SHIFT);
2830 if (duplex == FULL_DUPLEX)
2831 ctrl |= MAC_CTRL_DUPLX;
2832 ctrl |= (((u32)adapter->hw.preamble_len &
2833 MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
2834 __atlx_vlan_mode(netdev->features, &ctrl);
2835 if (wufc & ATLX_WUFC_MAG)
2836 ctrl |= MAC_CTRL_BC_EN;
2837 iowrite32(ctrl, hw->hw_addr + REG_MAC_CTRL);
2838 ioread32(hw->hw_addr + REG_MAC_CTRL);
2839
2840 /* poke the PHY */
2841 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2842 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2843 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2844 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2845 } else {
2846 ctrl |= (WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN);
2847 iowrite32(ctrl, hw->hw_addr + REG_WOL_CTRL);
2848 ioread32(hw->hw_addr + REG_WOL_CTRL);
2849 iowrite32(0, hw->hw_addr + REG_MAC_CTRL);
2850 ioread32(hw->hw_addr + REG_MAC_CTRL);
2851 hw->phy_configured = false;
2852 }
2853
2854 return 0;
2855
2856 disable_wol:
2857 iowrite32(0, hw->hw_addr + REG_WOL_CTRL);
2858 ioread32(hw->hw_addr + REG_WOL_CTRL);
2859 ctrl = ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2860 ctrl |= PCIE_PHYMISC_FORCE_RCV_DET;
2861 iowrite32(ctrl, hw->hw_addr + REG_PCIE_PHYMISC);
2862 ioread32(hw->hw_addr + REG_PCIE_PHYMISC);
2863 hw->phy_configured = false;
2864
2865 return 0;
2866 }
2867
2868 static int atl1_resume(struct device *dev)
2869 {
2870 struct pci_dev *pdev = to_pci_dev(dev);
2871 struct net_device *netdev = pci_get_drvdata(pdev);
2872 struct atl1_adapter *adapter = netdev_priv(netdev);
2873
2874 iowrite32(0, adapter->hw.hw_addr + REG_WOL_CTRL);
2875
2876 atl1_reset_hw(&adapter->hw);
2877
2878 if (netif_running(netdev)) {
2879 adapter->cmb.cmb->int_stats = 0;
2880 atl1_up(adapter);
2881 }
2882 netif_device_attach(netdev);
2883
2884 return 0;
2885 }
2886
2887 static SIMPLE_DEV_PM_OPS(atl1_pm_ops, atl1_suspend, atl1_resume);
2888 #define ATL1_PM_OPS (&atl1_pm_ops)
2889
2890 #else
2891
2892 static int atl1_suspend(struct device *dev) { return 0; }
2893
2894 #define ATL1_PM_OPS NULL
2895 #endif
2896
2897 static void atl1_shutdown(struct pci_dev *pdev)
2898 {
2899 struct net_device *netdev = pci_get_drvdata(pdev);
2900 struct atl1_adapter *adapter = netdev_priv(netdev);
2901
2902 atl1_suspend(&pdev->dev);
2903 pci_wake_from_d3(pdev, adapter->wol);
2904 pci_set_power_state(pdev, PCI_D3hot);
2905 }
2906
2907 #ifdef CONFIG_NET_POLL_CONTROLLER
2908 static void atl1_poll_controller(struct net_device *netdev)
2909 {
2910 disable_irq(netdev->irq);
2911 atl1_intr(netdev->irq, netdev);
2912 enable_irq(netdev->irq);
2913 }
2914 #endif
2915
2916 static const struct net_device_ops atl1_netdev_ops = {
2917 .ndo_open = atl1_open,
2918 .ndo_stop = atl1_close,
2919 .ndo_start_xmit = atl1_xmit_frame,
2920 .ndo_set_rx_mode = atlx_set_multi,
2921 .ndo_validate_addr = eth_validate_addr,
2922 .ndo_set_mac_address = atl1_set_mac,
2923 .ndo_change_mtu = atl1_change_mtu,
2924 .ndo_fix_features = atlx_fix_features,
2925 .ndo_set_features = atlx_set_features,
2926 .ndo_do_ioctl = atlx_ioctl,
2927 .ndo_tx_timeout = atlx_tx_timeout,
2928 #ifdef CONFIG_NET_POLL_CONTROLLER
2929 .ndo_poll_controller = atl1_poll_controller,
2930 #endif
2931 };
2932
2933 /*
2934 * atl1_probe - Device Initialization Routine
2935 * @pdev: PCI device information struct
2936 * @ent: entry in atl1_pci_tbl
2937 *
2938 * Returns 0 on success, negative on failure
2939 *
2940 * atl1_probe initializes an adapter identified by a pci_dev structure.
2941 * The OS initialization, configuring of the adapter private structure,
2942 * and a hardware reset occur.
2943 */
2944 static int __devinit atl1_probe(struct pci_dev *pdev,
2945 const struct pci_device_id *ent)
2946 {
2947 struct net_device *netdev;
2948 struct atl1_adapter *adapter;
2949 static int cards_found = 0;
2950 int err;
2951
2952 err = pci_enable_device(pdev);
2953 if (err)
2954 return err;
2955
2956 /*
2957 * The atl1 chip can DMA to 64-bit addresses, but it uses a single
2958 * shared register for the high 32 bits, so only a single, aligned,
2959 * 4 GB physical address range can be used at a time.
2960 *
2961 * Supporting 64-bit DMA on this hardware is more trouble than it's
2962 * worth. It is far easier to limit to 32-bit DMA than update
2963 * various kernel subsystems to support the mechanics required by a
2964 * fixed-high-32-bit system.
2965 */
2966 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2967 if (err) {
2968 dev_err(&pdev->dev, "no usable DMA configuration\n");
2969 goto err_dma;
2970 }
2971 /*
2972 * Mark all PCI regions associated with PCI device
2973 * pdev as being reserved by owner atl1_driver_name
2974 */
2975 err = pci_request_regions(pdev, ATLX_DRIVER_NAME);
2976 if (err)
2977 goto err_request_regions;
2978
2979 /*
2980 * Enables bus-mastering on the device and calls
2981 * pcibios_set_master to do the needed arch specific settings
2982 */
2983 pci_set_master(pdev);
2984
2985 netdev = alloc_etherdev(sizeof(struct atl1_adapter));
2986 if (!netdev) {
2987 err = -ENOMEM;
2988 goto err_alloc_etherdev;
2989 }
2990 SET_NETDEV_DEV(netdev, &pdev->dev);
2991
2992 pci_set_drvdata(pdev, netdev);
2993 adapter = netdev_priv(netdev);
2994 adapter->netdev = netdev;
2995 adapter->pdev = pdev;
2996 adapter->hw.back = adapter;
2997 adapter->msg_enable = netif_msg_init(debug, atl1_default_msg);
2998
2999 adapter->hw.hw_addr = pci_iomap(pdev, 0, 0);
3000 if (!adapter->hw.hw_addr) {
3001 err = -EIO;
3002 goto err_pci_iomap;
3003 }
3004 /* get device revision number */
3005 adapter->hw.dev_rev = ioread16(adapter->hw.hw_addr +
3006 (REG_MASTER_CTRL + 2));
3007 if (netif_msg_probe(adapter))
3008 dev_info(&pdev->dev, "version %s\n", ATLX_DRIVER_VERSION);
3009
3010 /* set default ring resource counts */
3011 adapter->rfd_ring.count = adapter->rrd_ring.count = ATL1_DEFAULT_RFD;
3012 adapter->tpd_ring.count = ATL1_DEFAULT_TPD;
3013
3014 adapter->mii.dev = netdev;
3015 adapter->mii.mdio_read = mdio_read;
3016 adapter->mii.mdio_write = mdio_write;
3017 adapter->mii.phy_id_mask = 0x1f;
3018 adapter->mii.reg_num_mask = 0x1f;
3019
3020 netdev->netdev_ops = &atl1_netdev_ops;
3021 netdev->watchdog_timeo = 5 * HZ;
3022 netif_napi_add(netdev, &adapter->napi, atl1_rings_clean, 64);
3023
3024 netdev->ethtool_ops = &atl1_ethtool_ops;
3025 adapter->bd_number = cards_found;
3026
3027 /* setup the private structure */
3028 err = atl1_sw_init(adapter);
3029 if (err)
3030 goto err_common;
3031
3032 netdev->features = NETIF_F_HW_CSUM;
3033 netdev->features |= NETIF_F_SG;
3034 netdev->features |= (NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX);
3035
3036 netdev->hw_features = NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_TSO |
3037 NETIF_F_HW_VLAN_RX;
3038
3039 /* is this valid? see atl1_setup_mac_ctrl() */
3040 netdev->features |= NETIF_F_RXCSUM;
3041
3042 /*
3043 * patch for some L1 of old version,
3044 * the final version of L1 may not need these
3045 * patches
3046 */
3047 /* atl1_pcie_patch(adapter); */
3048
3049 /* really reset GPHY core */
3050 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3051
3052 /*
3053 * reset the controller to
3054 * put the device in a known good starting state
3055 */
3056 if (atl1_reset_hw(&adapter->hw)) {
3057 err = -EIO;
3058 goto err_common;
3059 }
3060
3061 /* copy the MAC address out of the EEPROM */
3062 if (atl1_read_mac_addr(&adapter->hw)) {
3063 /* mark random mac */
3064 netdev->addr_assign_type |= NET_ADDR_RANDOM;
3065 }
3066 memcpy(netdev->dev_addr, adapter->hw.mac_addr, netdev->addr_len);
3067
3068 if (!is_valid_ether_addr(netdev->dev_addr)) {
3069 err = -EIO;
3070 goto err_common;
3071 }
3072
3073 atl1_check_options(adapter);
3074
3075 /* pre-init the MAC, and setup link */
3076 err = atl1_init_hw(&adapter->hw);
3077 if (err) {
3078 err = -EIO;
3079 goto err_common;
3080 }
3081
3082 atl1_pcie_patch(adapter);
3083 /* assume we have no link for now */
3084 netif_carrier_off(netdev);
3085
3086 setup_timer(&adapter->phy_config_timer, atl1_phy_config,
3087 (unsigned long)adapter);
3088 adapter->phy_timer_pending = false;
3089
3090 INIT_WORK(&adapter->reset_dev_task, atl1_reset_dev_task);
3091
3092 INIT_WORK(&adapter->link_chg_task, atlx_link_chg_task);
3093
3094 err = register_netdev(netdev);
3095 if (err)
3096 goto err_common;
3097
3098 cards_found++;
3099 atl1_via_workaround(adapter);
3100 return 0;
3101
3102 err_common:
3103 pci_iounmap(pdev, adapter->hw.hw_addr);
3104 err_pci_iomap:
3105 free_netdev(netdev);
3106 err_alloc_etherdev:
3107 pci_release_regions(pdev);
3108 err_dma:
3109 err_request_regions:
3110 pci_disable_device(pdev);
3111 return err;
3112 }
3113
3114 /*
3115 * atl1_remove - Device Removal Routine
3116 * @pdev: PCI device information struct
3117 *
3118 * atl1_remove is called by the PCI subsystem to alert the driver
3119 * that it should release a PCI device. The could be caused by a
3120 * Hot-Plug event, or because the driver is going to be removed from
3121 * memory.
3122 */
3123 static void __devexit atl1_remove(struct pci_dev *pdev)
3124 {
3125 struct net_device *netdev = pci_get_drvdata(pdev);
3126 struct atl1_adapter *adapter;
3127 /* Device not available. Return. */
3128 if (!netdev)
3129 return;
3130
3131 adapter = netdev_priv(netdev);
3132
3133 /*
3134 * Some atl1 boards lack persistent storage for their MAC, and get it
3135 * from the BIOS during POST. If we've been messing with the MAC
3136 * address, we need to save the permanent one.
3137 */
3138 if (memcmp(adapter->hw.mac_addr, adapter->hw.perm_mac_addr, ETH_ALEN)) {
3139 memcpy(adapter->hw.mac_addr, adapter->hw.perm_mac_addr,
3140 ETH_ALEN);
3141 atl1_set_mac_addr(&adapter->hw);
3142 }
3143
3144 iowrite16(0, adapter->hw.hw_addr + REG_PHY_ENABLE);
3145 unregister_netdev(netdev);
3146 pci_iounmap(pdev, adapter->hw.hw_addr);
3147 pci_release_regions(pdev);
3148 free_netdev(netdev);
3149 pci_disable_device(pdev);
3150 }
3151
3152 static struct pci_driver atl1_driver = {
3153 .name = ATLX_DRIVER_NAME,
3154 .id_table = atl1_pci_tbl,
3155 .probe = atl1_probe,
3156 .remove = __devexit_p(atl1_remove),
3157 .shutdown = atl1_shutdown,
3158 .driver.pm = ATL1_PM_OPS,
3159 };
3160
3161 /*
3162 * atl1_exit_module - Driver Exit Cleanup Routine
3163 *
3164 * atl1_exit_module is called just before the driver is removed
3165 * from memory.
3166 */
3167 static void __exit atl1_exit_module(void)
3168 {
3169 pci_unregister_driver(&atl1_driver);
3170 }
3171
3172 /*
3173 * atl1_init_module - Driver Registration Routine
3174 *
3175 * atl1_init_module is the first routine called when the driver is
3176 * loaded. All it does is register with the PCI subsystem.
3177 */
3178 static int __init atl1_init_module(void)
3179 {
3180 return pci_register_driver(&atl1_driver);
3181 }
3182
3183 module_init(atl1_init_module);
3184 module_exit(atl1_exit_module);
3185
3186 struct atl1_stats {
3187 char stat_string[ETH_GSTRING_LEN];
3188 int sizeof_stat;
3189 int stat_offset;
3190 };
3191
3192 #define ATL1_STAT(m) \
3193 sizeof(((struct atl1_adapter *)0)->m), offsetof(struct atl1_adapter, m)
3194
3195 static struct atl1_stats atl1_gstrings_stats[] = {
3196 {"rx_packets", ATL1_STAT(soft_stats.rx_packets)},
3197 {"tx_packets", ATL1_STAT(soft_stats.tx_packets)},
3198 {"rx_bytes", ATL1_STAT(soft_stats.rx_bytes)},
3199 {"tx_bytes", ATL1_STAT(soft_stats.tx_bytes)},
3200 {"rx_errors", ATL1_STAT(soft_stats.rx_errors)},
3201 {"tx_errors", ATL1_STAT(soft_stats.tx_errors)},
3202 {"multicast", ATL1_STAT(soft_stats.multicast)},
3203 {"collisions", ATL1_STAT(soft_stats.collisions)},
3204 {"rx_length_errors", ATL1_STAT(soft_stats.rx_length_errors)},
3205 {"rx_over_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3206 {"rx_crc_errors", ATL1_STAT(soft_stats.rx_crc_errors)},
3207 {"rx_frame_errors", ATL1_STAT(soft_stats.rx_frame_errors)},
3208 {"rx_fifo_errors", ATL1_STAT(soft_stats.rx_fifo_errors)},
3209 {"rx_missed_errors", ATL1_STAT(soft_stats.rx_missed_errors)},
3210 {"tx_aborted_errors", ATL1_STAT(soft_stats.tx_aborted_errors)},
3211 {"tx_carrier_errors", ATL1_STAT(soft_stats.tx_carrier_errors)},
3212 {"tx_fifo_errors", ATL1_STAT(soft_stats.tx_fifo_errors)},
3213 {"tx_window_errors", ATL1_STAT(soft_stats.tx_window_errors)},
3214 {"tx_abort_exce_coll", ATL1_STAT(soft_stats.excecol)},
3215 {"tx_abort_late_coll", ATL1_STAT(soft_stats.latecol)},
3216 {"tx_deferred_ok", ATL1_STAT(soft_stats.deffer)},
3217 {"tx_single_coll_ok", ATL1_STAT(soft_stats.scc)},
3218 {"tx_multi_coll_ok", ATL1_STAT(soft_stats.mcc)},
3219 {"tx_underun", ATL1_STAT(soft_stats.tx_underun)},
3220 {"tx_trunc", ATL1_STAT(soft_stats.tx_trunc)},
3221 {"tx_pause", ATL1_STAT(soft_stats.tx_pause)},
3222 {"rx_pause", ATL1_STAT(soft_stats.rx_pause)},
3223 {"rx_rrd_ov", ATL1_STAT(soft_stats.rx_rrd_ov)},
3224 {"rx_trunc", ATL1_STAT(soft_stats.rx_trunc)}
3225 };
3226
3227 static void atl1_get_ethtool_stats(struct net_device *netdev,
3228 struct ethtool_stats *stats, u64 *data)
3229 {
3230 struct atl1_adapter *adapter = netdev_priv(netdev);
3231 int i;
3232 char *p;
3233
3234 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3235 p = (char *)adapter+atl1_gstrings_stats[i].stat_offset;
3236 data[i] = (atl1_gstrings_stats[i].sizeof_stat ==
3237 sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
3238 }
3239
3240 }
3241
3242 static int atl1_get_sset_count(struct net_device *netdev, int sset)
3243 {
3244 switch (sset) {
3245 case ETH_SS_STATS:
3246 return ARRAY_SIZE(atl1_gstrings_stats);
3247 default:
3248 return -EOPNOTSUPP;
3249 }
3250 }
3251
3252 static int atl1_get_settings(struct net_device *netdev,
3253 struct ethtool_cmd *ecmd)
3254 {
3255 struct atl1_adapter *adapter = netdev_priv(netdev);
3256 struct atl1_hw *hw = &adapter->hw;
3257
3258 ecmd->supported = (SUPPORTED_10baseT_Half |
3259 SUPPORTED_10baseT_Full |
3260 SUPPORTED_100baseT_Half |
3261 SUPPORTED_100baseT_Full |
3262 SUPPORTED_1000baseT_Full |
3263 SUPPORTED_Autoneg | SUPPORTED_TP);
3264 ecmd->advertising = ADVERTISED_TP;
3265 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3266 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3267 ecmd->advertising |= ADVERTISED_Autoneg;
3268 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR) {
3269 ecmd->advertising |= ADVERTISED_Autoneg;
3270 ecmd->advertising |=
3271 (ADVERTISED_10baseT_Half |
3272 ADVERTISED_10baseT_Full |
3273 ADVERTISED_100baseT_Half |
3274 ADVERTISED_100baseT_Full |
3275 ADVERTISED_1000baseT_Full);
3276 } else
3277 ecmd->advertising |= (ADVERTISED_1000baseT_Full);
3278 }
3279 ecmd->port = PORT_TP;
3280 ecmd->phy_address = 0;
3281 ecmd->transceiver = XCVR_INTERNAL;
3282
3283 if (netif_carrier_ok(adapter->netdev)) {
3284 u16 link_speed, link_duplex;
3285 atl1_get_speed_and_duplex(hw, &link_speed, &link_duplex);
3286 ethtool_cmd_speed_set(ecmd, link_speed);
3287 if (link_duplex == FULL_DUPLEX)
3288 ecmd->duplex = DUPLEX_FULL;
3289 else
3290 ecmd->duplex = DUPLEX_HALF;
3291 } else {
3292 ethtool_cmd_speed_set(ecmd, -1);
3293 ecmd->duplex = -1;
3294 }
3295 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3296 hw->media_type == MEDIA_TYPE_1000M_FULL)
3297 ecmd->autoneg = AUTONEG_ENABLE;
3298 else
3299 ecmd->autoneg = AUTONEG_DISABLE;
3300
3301 return 0;
3302 }
3303
3304 static int atl1_set_settings(struct net_device *netdev,
3305 struct ethtool_cmd *ecmd)
3306 {
3307 struct atl1_adapter *adapter = netdev_priv(netdev);
3308 struct atl1_hw *hw = &adapter->hw;
3309 u16 phy_data;
3310 int ret_val = 0;
3311 u16 old_media_type = hw->media_type;
3312
3313 if (netif_running(adapter->netdev)) {
3314 if (netif_msg_link(adapter))
3315 dev_dbg(&adapter->pdev->dev,
3316 "ethtool shutting down adapter\n");
3317 atl1_down(adapter);
3318 }
3319
3320 if (ecmd->autoneg == AUTONEG_ENABLE)
3321 hw->media_type = MEDIA_TYPE_AUTO_SENSOR;
3322 else {
3323 u32 speed = ethtool_cmd_speed(ecmd);
3324 if (speed == SPEED_1000) {
3325 if (ecmd->duplex != DUPLEX_FULL) {
3326 if (netif_msg_link(adapter))
3327 dev_warn(&adapter->pdev->dev,
3328 "1000M half is invalid\n");
3329 ret_val = -EINVAL;
3330 goto exit_sset;
3331 }
3332 hw->media_type = MEDIA_TYPE_1000M_FULL;
3333 } else if (speed == SPEED_100) {
3334 if (ecmd->duplex == DUPLEX_FULL)
3335 hw->media_type = MEDIA_TYPE_100M_FULL;
3336 else
3337 hw->media_type = MEDIA_TYPE_100M_HALF;
3338 } else {
3339 if (ecmd->duplex == DUPLEX_FULL)
3340 hw->media_type = MEDIA_TYPE_10M_FULL;
3341 else
3342 hw->media_type = MEDIA_TYPE_10M_HALF;
3343 }
3344 }
3345 switch (hw->media_type) {
3346 case MEDIA_TYPE_AUTO_SENSOR:
3347 ecmd->advertising =
3348 ADVERTISED_10baseT_Half |
3349 ADVERTISED_10baseT_Full |
3350 ADVERTISED_100baseT_Half |
3351 ADVERTISED_100baseT_Full |
3352 ADVERTISED_1000baseT_Full |
3353 ADVERTISED_Autoneg | ADVERTISED_TP;
3354 break;
3355 case MEDIA_TYPE_1000M_FULL:
3356 ecmd->advertising =
3357 ADVERTISED_1000baseT_Full |
3358 ADVERTISED_Autoneg | ADVERTISED_TP;
3359 break;
3360 default:
3361 ecmd->advertising = 0;
3362 break;
3363 }
3364 if (atl1_phy_setup_autoneg_adv(hw)) {
3365 ret_val = -EINVAL;
3366 if (netif_msg_link(adapter))
3367 dev_warn(&adapter->pdev->dev,
3368 "invalid ethtool speed/duplex setting\n");
3369 goto exit_sset;
3370 }
3371 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3372 hw->media_type == MEDIA_TYPE_1000M_FULL)
3373 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3374 else {
3375 switch (hw->media_type) {
3376 case MEDIA_TYPE_100M_FULL:
3377 phy_data =
3378 MII_CR_FULL_DUPLEX | MII_CR_SPEED_100 |
3379 MII_CR_RESET;
3380 break;
3381 case MEDIA_TYPE_100M_HALF:
3382 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3383 break;
3384 case MEDIA_TYPE_10M_FULL:
3385 phy_data =
3386 MII_CR_FULL_DUPLEX | MII_CR_SPEED_10 | MII_CR_RESET;
3387 break;
3388 default:
3389 /* MEDIA_TYPE_10M_HALF: */
3390 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3391 break;
3392 }
3393 }
3394 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3395 exit_sset:
3396 if (ret_val)
3397 hw->media_type = old_media_type;
3398
3399 if (netif_running(adapter->netdev)) {
3400 if (netif_msg_link(adapter))
3401 dev_dbg(&adapter->pdev->dev,
3402 "ethtool starting adapter\n");
3403 atl1_up(adapter);
3404 } else if (!ret_val) {
3405 if (netif_msg_link(adapter))
3406 dev_dbg(&adapter->pdev->dev,
3407 "ethtool resetting adapter\n");
3408 atl1_reset(adapter);
3409 }
3410 return ret_val;
3411 }
3412
3413 static void atl1_get_drvinfo(struct net_device *netdev,
3414 struct ethtool_drvinfo *drvinfo)
3415 {
3416 struct atl1_adapter *adapter = netdev_priv(netdev);
3417
3418 strlcpy(drvinfo->driver, ATLX_DRIVER_NAME, sizeof(drvinfo->driver));
3419 strlcpy(drvinfo->version, ATLX_DRIVER_VERSION,
3420 sizeof(drvinfo->version));
3421 strlcpy(drvinfo->bus_info, pci_name(adapter->pdev),
3422 sizeof(drvinfo->bus_info));
3423 drvinfo->eedump_len = ATL1_EEDUMP_LEN;
3424 }
3425
3426 static void atl1_get_wol(struct net_device *netdev,
3427 struct ethtool_wolinfo *wol)
3428 {
3429 struct atl1_adapter *adapter = netdev_priv(netdev);
3430
3431 wol->supported = WAKE_MAGIC;
3432 wol->wolopts = 0;
3433 if (adapter->wol & ATLX_WUFC_MAG)
3434 wol->wolopts |= WAKE_MAGIC;
3435 }
3436
3437 static int atl1_set_wol(struct net_device *netdev,
3438 struct ethtool_wolinfo *wol)
3439 {
3440 struct atl1_adapter *adapter = netdev_priv(netdev);
3441
3442 if (wol->wolopts & (WAKE_PHY | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST |
3443 WAKE_ARP | WAKE_MAGICSECURE))
3444 return -EOPNOTSUPP;
3445 adapter->wol = 0;
3446 if (wol->wolopts & WAKE_MAGIC)
3447 adapter->wol |= ATLX_WUFC_MAG;
3448
3449 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
3450
3451 return 0;
3452 }
3453
3454 static u32 atl1_get_msglevel(struct net_device *netdev)
3455 {
3456 struct atl1_adapter *adapter = netdev_priv(netdev);
3457 return adapter->msg_enable;
3458 }
3459
3460 static void atl1_set_msglevel(struct net_device *netdev, u32 value)
3461 {
3462 struct atl1_adapter *adapter = netdev_priv(netdev);
3463 adapter->msg_enable = value;
3464 }
3465
3466 static int atl1_get_regs_len(struct net_device *netdev)
3467 {
3468 return ATL1_REG_COUNT * sizeof(u32);
3469 }
3470
3471 static void atl1_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
3472 void *p)
3473 {
3474 struct atl1_adapter *adapter = netdev_priv(netdev);
3475 struct atl1_hw *hw = &adapter->hw;
3476 unsigned int i;
3477 u32 *regbuf = p;
3478
3479 for (i = 0; i < ATL1_REG_COUNT; i++) {
3480 /*
3481 * This switch statement avoids reserved regions
3482 * of register space.
3483 */
3484 switch (i) {
3485 case 6 ... 9:
3486 case 14:
3487 case 29 ... 31:
3488 case 34 ... 63:
3489 case 75 ... 127:
3490 case 136 ... 1023:
3491 case 1027 ... 1087:
3492 case 1091 ... 1151:
3493 case 1194 ... 1195:
3494 case 1200 ... 1201:
3495 case 1206 ... 1213:
3496 case 1216 ... 1279:
3497 case 1290 ... 1311:
3498 case 1323 ... 1343:
3499 case 1358 ... 1359:
3500 case 1368 ... 1375:
3501 case 1378 ... 1383:
3502 case 1388 ... 1391:
3503 case 1393 ... 1395:
3504 case 1402 ... 1403:
3505 case 1410 ... 1471:
3506 case 1522 ... 1535:
3507 /* reserved region; don't read it */
3508 regbuf[i] = 0;
3509 break;
3510 default:
3511 /* unreserved region */
3512 regbuf[i] = ioread32(hw->hw_addr + (i * sizeof(u32)));
3513 }
3514 }
3515 }
3516
3517 static void atl1_get_ringparam(struct net_device *netdev,
3518 struct ethtool_ringparam *ring)
3519 {
3520 struct atl1_adapter *adapter = netdev_priv(netdev);
3521 struct atl1_tpd_ring *txdr = &adapter->tpd_ring;
3522 struct atl1_rfd_ring *rxdr = &adapter->rfd_ring;
3523
3524 ring->rx_max_pending = ATL1_MAX_RFD;
3525 ring->tx_max_pending = ATL1_MAX_TPD;
3526 ring->rx_pending = rxdr->count;
3527 ring->tx_pending = txdr->count;
3528 }
3529
3530 static int atl1_set_ringparam(struct net_device *netdev,
3531 struct ethtool_ringparam *ring)
3532 {
3533 struct atl1_adapter *adapter = netdev_priv(netdev);
3534 struct atl1_tpd_ring *tpdr = &adapter->tpd_ring;
3535 struct atl1_rrd_ring *rrdr = &adapter->rrd_ring;
3536 struct atl1_rfd_ring *rfdr = &adapter->rfd_ring;
3537
3538 struct atl1_tpd_ring tpd_old, tpd_new;
3539 struct atl1_rfd_ring rfd_old, rfd_new;
3540 struct atl1_rrd_ring rrd_old, rrd_new;
3541 struct atl1_ring_header rhdr_old, rhdr_new;
3542 struct atl1_smb smb;
3543 struct atl1_cmb cmb;
3544 int err;
3545
3546 tpd_old = adapter->tpd_ring;
3547 rfd_old = adapter->rfd_ring;
3548 rrd_old = adapter->rrd_ring;
3549 rhdr_old = adapter->ring_header;
3550
3551 if (netif_running(adapter->netdev))
3552 atl1_down(adapter);
3553
3554 rfdr->count = (u16) max(ring->rx_pending, (u32) ATL1_MIN_RFD);
3555 rfdr->count = rfdr->count > ATL1_MAX_RFD ? ATL1_MAX_RFD :
3556 rfdr->count;
3557 rfdr->count = (rfdr->count + 3) & ~3;
3558 rrdr->count = rfdr->count;
3559
3560 tpdr->count = (u16) max(ring->tx_pending, (u32) ATL1_MIN_TPD);
3561 tpdr->count = tpdr->count > ATL1_MAX_TPD ? ATL1_MAX_TPD :
3562 tpdr->count;
3563 tpdr->count = (tpdr->count + 3) & ~3;
3564
3565 if (netif_running(adapter->netdev)) {
3566 /* try to get new resources before deleting old */
3567 err = atl1_setup_ring_resources(adapter);
3568 if (err)
3569 goto err_setup_ring;
3570
3571 /*
3572 * save the new, restore the old in order to free it,
3573 * then restore the new back again
3574 */
3575
3576 rfd_new = adapter->rfd_ring;
3577 rrd_new = adapter->rrd_ring;
3578 tpd_new = adapter->tpd_ring;
3579 rhdr_new = adapter->ring_header;
3580 adapter->rfd_ring = rfd_old;
3581 adapter->rrd_ring = rrd_old;
3582 adapter->tpd_ring = tpd_old;
3583 adapter->ring_header = rhdr_old;
3584 /*
3585 * Save SMB and CMB, since atl1_free_ring_resources
3586 * will clear them.
3587 */
3588 smb = adapter->smb;
3589 cmb = adapter->cmb;
3590 atl1_free_ring_resources(adapter);
3591 adapter->rfd_ring = rfd_new;
3592 adapter->rrd_ring = rrd_new;
3593 adapter->tpd_ring = tpd_new;
3594 adapter->ring_header = rhdr_new;
3595 adapter->smb = smb;
3596 adapter->cmb = cmb;
3597
3598 err = atl1_up(adapter);
3599 if (err)
3600 return err;
3601 }
3602 return 0;
3603
3604 err_setup_ring:
3605 adapter->rfd_ring = rfd_old;
3606 adapter->rrd_ring = rrd_old;
3607 adapter->tpd_ring = tpd_old;
3608 adapter->ring_header = rhdr_old;
3609 atl1_up(adapter);
3610 return err;
3611 }
3612
3613 static void atl1_get_pauseparam(struct net_device *netdev,
3614 struct ethtool_pauseparam *epause)
3615 {
3616 struct atl1_adapter *adapter = netdev_priv(netdev);
3617 struct atl1_hw *hw = &adapter->hw;
3618
3619 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3620 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3621 epause->autoneg = AUTONEG_ENABLE;
3622 } else {
3623 epause->autoneg = AUTONEG_DISABLE;
3624 }
3625 epause->rx_pause = 1;
3626 epause->tx_pause = 1;
3627 }
3628
3629 static int atl1_set_pauseparam(struct net_device *netdev,
3630 struct ethtool_pauseparam *epause)
3631 {
3632 struct atl1_adapter *adapter = netdev_priv(netdev);
3633 struct atl1_hw *hw = &adapter->hw;
3634
3635 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3636 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3637 epause->autoneg = AUTONEG_ENABLE;
3638 } else {
3639 epause->autoneg = AUTONEG_DISABLE;
3640 }
3641
3642 epause->rx_pause = 1;
3643 epause->tx_pause = 1;
3644
3645 return 0;
3646 }
3647
3648 static void atl1_get_strings(struct net_device *netdev, u32 stringset,
3649 u8 *data)
3650 {
3651 u8 *p = data;
3652 int i;
3653
3654 switch (stringset) {
3655 case ETH_SS_STATS:
3656 for (i = 0; i < ARRAY_SIZE(atl1_gstrings_stats); i++) {
3657 memcpy(p, atl1_gstrings_stats[i].stat_string,
3658 ETH_GSTRING_LEN);
3659 p += ETH_GSTRING_LEN;
3660 }
3661 break;
3662 }
3663 }
3664
3665 static int atl1_nway_reset(struct net_device *netdev)
3666 {
3667 struct atl1_adapter *adapter = netdev_priv(netdev);
3668 struct atl1_hw *hw = &adapter->hw;
3669
3670 if (netif_running(netdev)) {
3671 u16 phy_data;
3672 atl1_down(adapter);
3673
3674 if (hw->media_type == MEDIA_TYPE_AUTO_SENSOR ||
3675 hw->media_type == MEDIA_TYPE_1000M_FULL) {
3676 phy_data = MII_CR_RESET | MII_CR_AUTO_NEG_EN;
3677 } else {
3678 switch (hw->media_type) {
3679 case MEDIA_TYPE_100M_FULL:
3680 phy_data = MII_CR_FULL_DUPLEX |
3681 MII_CR_SPEED_100 | MII_CR_RESET;
3682 break;
3683 case MEDIA_TYPE_100M_HALF:
3684 phy_data = MII_CR_SPEED_100 | MII_CR_RESET;
3685 break;
3686 case MEDIA_TYPE_10M_FULL:
3687 phy_data = MII_CR_FULL_DUPLEX |
3688 MII_CR_SPEED_10 | MII_CR_RESET;
3689 break;
3690 default:
3691 /* MEDIA_TYPE_10M_HALF */
3692 phy_data = MII_CR_SPEED_10 | MII_CR_RESET;
3693 }
3694 }
3695 atl1_write_phy_reg(hw, MII_BMCR, phy_data);
3696 atl1_up(adapter);
3697 }
3698 return 0;
3699 }
3700
3701 static const struct ethtool_ops atl1_ethtool_ops = {
3702 .get_settings = atl1_get_settings,
3703 .set_settings = atl1_set_settings,
3704 .get_drvinfo = atl1_get_drvinfo,
3705 .get_wol = atl1_get_wol,
3706 .set_wol = atl1_set_wol,
3707 .get_msglevel = atl1_get_msglevel,
3708 .set_msglevel = atl1_set_msglevel,
3709 .get_regs_len = atl1_get_regs_len,
3710 .get_regs = atl1_get_regs,
3711 .get_ringparam = atl1_get_ringparam,
3712 .set_ringparam = atl1_set_ringparam,
3713 .get_pauseparam = atl1_get_pauseparam,
3714 .set_pauseparam = atl1_set_pauseparam,
3715 .get_link = ethtool_op_get_link,
3716 .get_strings = atl1_get_strings,
3717 .nway_reset = atl1_nway_reset,
3718 .get_ethtool_stats = atl1_get_ethtool_stats,
3719 .get_sset_count = atl1_get_sset_count,
3720 };
Linux kernel - Deliverables
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