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net: ethernet: bgmac: add dma_dev pointer
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bgmac.c
1 /*
2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
3 *
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
5 *
6 * Licensed under the GNU/GPL. See COPYING for details.
7 */
8
9 #include "bgmac.h"
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/bcm47xx_nvram.h>
21
22 static const struct bcma_device_id bgmac_bcma_tbl[] = {
23 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
24 BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_MAC_GBIT, BCMA_ANY_REV, BCMA_ANY_CLASS),
25 {},
26 };
27 MODULE_DEVICE_TABLE(bcma, bgmac_bcma_tbl);
28
29 static inline bool bgmac_is_bcm4707_family(struct bgmac *bgmac)
30 {
31 switch (bgmac->core->bus->chipinfo.id) {
32 case BCMA_CHIP_ID_BCM4707:
33 case BCMA_CHIP_ID_BCM47094:
34 case BCMA_CHIP_ID_BCM53018:
35 return true;
36 default:
37 return false;
38 }
39 }
40
41 static bool bgmac_wait_value(struct bcma_device *core, u16 reg, u32 mask,
42 u32 value, int timeout)
43 {
44 u32 val;
45 int i;
46
47 for (i = 0; i < timeout / 10; i++) {
48 val = bcma_read32(core, reg);
49 if ((val & mask) == value)
50 return true;
51 udelay(10);
52 }
53 dev_err(&core->dev, "Timeout waiting for reg 0x%X\n", reg);
54 return false;
55 }
56
57 /**************************************************
58 * DMA
59 **************************************************/
60
61 static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
62 {
63 u32 val;
64 int i;
65
66 if (!ring->mmio_base)
67 return;
68
69 /* Suspend DMA TX ring first.
70 * bgmac_wait_value doesn't support waiting for any of few values, so
71 * implement whole loop here.
72 */
73 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
74 BGMAC_DMA_TX_SUSPEND);
75 for (i = 0; i < 10000 / 10; i++) {
76 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
77 val &= BGMAC_DMA_TX_STAT;
78 if (val == BGMAC_DMA_TX_STAT_DISABLED ||
79 val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
80 val == BGMAC_DMA_TX_STAT_STOPPED) {
81 i = 0;
82 break;
83 }
84 udelay(10);
85 }
86 if (i)
87 dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
88 ring->mmio_base, val);
89
90 /* Remove SUSPEND bit */
91 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
92 if (!bgmac_wait_value(bgmac->core,
93 ring->mmio_base + BGMAC_DMA_TX_STATUS,
94 BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
95 10000)) {
96 dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
97 ring->mmio_base);
98 udelay(300);
99 val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
100 if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
101 dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
102 ring->mmio_base);
103 }
104 }
105
106 static void bgmac_dma_tx_enable(struct bgmac *bgmac,
107 struct bgmac_dma_ring *ring)
108 {
109 u32 ctl;
110
111 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
112 if (bgmac->core->id.rev >= 4) {
113 ctl &= ~BGMAC_DMA_TX_BL_MASK;
114 ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
115
116 ctl &= ~BGMAC_DMA_TX_MR_MASK;
117 ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
118
119 ctl &= ~BGMAC_DMA_TX_PC_MASK;
120 ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
121
122 ctl &= ~BGMAC_DMA_TX_PT_MASK;
123 ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
124 }
125 ctl |= BGMAC_DMA_TX_ENABLE;
126 ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
127 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
128 }
129
130 static void
131 bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
132 int i, int len, u32 ctl0)
133 {
134 struct bgmac_slot_info *slot;
135 struct bgmac_dma_desc *dma_desc;
136 u32 ctl1;
137
138 if (i == BGMAC_TX_RING_SLOTS - 1)
139 ctl0 |= BGMAC_DESC_CTL0_EOT;
140
141 ctl1 = len & BGMAC_DESC_CTL1_LEN;
142
143 slot = &ring->slots[i];
144 dma_desc = &ring->cpu_base[i];
145 dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
146 dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
147 dma_desc->ctl0 = cpu_to_le32(ctl0);
148 dma_desc->ctl1 = cpu_to_le32(ctl1);
149 }
150
151 static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
152 struct bgmac_dma_ring *ring,
153 struct sk_buff *skb)
154 {
155 struct device *dma_dev = bgmac->dma_dev;
156 struct net_device *net_dev = bgmac->net_dev;
157 int index = ring->end % BGMAC_TX_RING_SLOTS;
158 struct bgmac_slot_info *slot = &ring->slots[index];
159 int nr_frags;
160 u32 flags;
161 int i;
162
163 if (skb->len > BGMAC_DESC_CTL1_LEN) {
164 netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
165 goto err_drop;
166 }
167
168 if (skb->ip_summed == CHECKSUM_PARTIAL)
169 skb_checksum_help(skb);
170
171 nr_frags = skb_shinfo(skb)->nr_frags;
172
173 /* ring->end - ring->start will return the number of valid slots,
174 * even when ring->end overflows
175 */
176 if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
177 netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
178 netif_stop_queue(net_dev);
179 return NETDEV_TX_BUSY;
180 }
181
182 slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
183 DMA_TO_DEVICE);
184 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
185 goto err_dma_head;
186
187 flags = BGMAC_DESC_CTL0_SOF;
188 if (!nr_frags)
189 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
190
191 bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
192 flags = 0;
193
194 for (i = 0; i < nr_frags; i++) {
195 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
196 int len = skb_frag_size(frag);
197
198 index = (index + 1) % BGMAC_TX_RING_SLOTS;
199 slot = &ring->slots[index];
200 slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
201 len, DMA_TO_DEVICE);
202 if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
203 goto err_dma;
204
205 if (i == nr_frags - 1)
206 flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
207
208 bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
209 }
210
211 slot->skb = skb;
212 ring->end += nr_frags + 1;
213 netdev_sent_queue(net_dev, skb->len);
214
215 wmb();
216
217 /* Increase ring->end to point empty slot. We tell hardware the first
218 * slot it should *not* read.
219 */
220 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
221 ring->index_base +
222 (ring->end % BGMAC_TX_RING_SLOTS) *
223 sizeof(struct bgmac_dma_desc));
224
225 if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
226 netif_stop_queue(net_dev);
227
228 return NETDEV_TX_OK;
229
230 err_dma:
231 dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
232 DMA_TO_DEVICE);
233
234 while (i > 0) {
235 int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
236 struct bgmac_slot_info *slot = &ring->slots[index];
237 u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
238 int len = ctl1 & BGMAC_DESC_CTL1_LEN;
239
240 dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
241 }
242
243 err_dma_head:
244 netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
245 ring->mmio_base);
246
247 err_drop:
248 dev_kfree_skb(skb);
249 net_dev->stats.tx_dropped++;
250 net_dev->stats.tx_errors++;
251 return NETDEV_TX_OK;
252 }
253
254 /* Free transmitted packets */
255 static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
256 {
257 struct device *dma_dev = bgmac->dma_dev;
258 int empty_slot;
259 bool freed = false;
260 unsigned bytes_compl = 0, pkts_compl = 0;
261
262 /* The last slot that hardware didn't consume yet */
263 empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
264 empty_slot &= BGMAC_DMA_TX_STATDPTR;
265 empty_slot -= ring->index_base;
266 empty_slot &= BGMAC_DMA_TX_STATDPTR;
267 empty_slot /= sizeof(struct bgmac_dma_desc);
268
269 while (ring->start != ring->end) {
270 int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
271 struct bgmac_slot_info *slot = &ring->slots[slot_idx];
272 u32 ctl0, ctl1;
273 int len;
274
275 if (slot_idx == empty_slot)
276 break;
277
278 ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
279 ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
280 len = ctl1 & BGMAC_DESC_CTL1_LEN;
281 if (ctl0 & BGMAC_DESC_CTL0_SOF)
282 /* Unmap no longer used buffer */
283 dma_unmap_single(dma_dev, slot->dma_addr, len,
284 DMA_TO_DEVICE);
285 else
286 dma_unmap_page(dma_dev, slot->dma_addr, len,
287 DMA_TO_DEVICE);
288
289 if (slot->skb) {
290 bgmac->net_dev->stats.tx_bytes += slot->skb->len;
291 bgmac->net_dev->stats.tx_packets++;
292 bytes_compl += slot->skb->len;
293 pkts_compl++;
294
295 /* Free memory! :) */
296 dev_kfree_skb(slot->skb);
297 slot->skb = NULL;
298 }
299
300 slot->dma_addr = 0;
301 ring->start++;
302 freed = true;
303 }
304
305 if (!pkts_compl)
306 return;
307
308 netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
309
310 if (netif_queue_stopped(bgmac->net_dev))
311 netif_wake_queue(bgmac->net_dev);
312 }
313
314 static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
315 {
316 if (!ring->mmio_base)
317 return;
318
319 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
320 if (!bgmac_wait_value(bgmac->core,
321 ring->mmio_base + BGMAC_DMA_RX_STATUS,
322 BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
323 10000))
324 dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
325 ring->mmio_base);
326 }
327
328 static void bgmac_dma_rx_enable(struct bgmac *bgmac,
329 struct bgmac_dma_ring *ring)
330 {
331 u32 ctl;
332
333 ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
334 if (bgmac->core->id.rev >= 4) {
335 ctl &= ~BGMAC_DMA_RX_BL_MASK;
336 ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
337
338 ctl &= ~BGMAC_DMA_RX_PC_MASK;
339 ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
340
341 ctl &= ~BGMAC_DMA_RX_PT_MASK;
342 ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
343 }
344 ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
345 ctl |= BGMAC_DMA_RX_ENABLE;
346 ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
347 ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
348 ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
349 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
350 }
351
352 static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
353 struct bgmac_slot_info *slot)
354 {
355 struct device *dma_dev = bgmac->dma_dev;
356 dma_addr_t dma_addr;
357 struct bgmac_rx_header *rx;
358 void *buf;
359
360 /* Alloc skb */
361 buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
362 if (!buf)
363 return -ENOMEM;
364
365 /* Poison - if everything goes fine, hardware will overwrite it */
366 rx = buf + BGMAC_RX_BUF_OFFSET;
367 rx->len = cpu_to_le16(0xdead);
368 rx->flags = cpu_to_le16(0xbeef);
369
370 /* Map skb for the DMA */
371 dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
372 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
373 if (dma_mapping_error(dma_dev, dma_addr)) {
374 netdev_err(bgmac->net_dev, "DMA mapping error\n");
375 put_page(virt_to_head_page(buf));
376 return -ENOMEM;
377 }
378
379 /* Update the slot */
380 slot->buf = buf;
381 slot->dma_addr = dma_addr;
382
383 return 0;
384 }
385
386 static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
387 struct bgmac_dma_ring *ring)
388 {
389 dma_wmb();
390
391 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
392 ring->index_base +
393 ring->end * sizeof(struct bgmac_dma_desc));
394 }
395
396 static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
397 struct bgmac_dma_ring *ring, int desc_idx)
398 {
399 struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
400 u32 ctl0 = 0, ctl1 = 0;
401
402 if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
403 ctl0 |= BGMAC_DESC_CTL0_EOT;
404 ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
405 /* Is there any BGMAC device that requires extension? */
406 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
407 * B43_DMA64_DCTL1_ADDREXT_MASK;
408 */
409
410 dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
411 dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
412 dma_desc->ctl0 = cpu_to_le32(ctl0);
413 dma_desc->ctl1 = cpu_to_le32(ctl1);
414
415 ring->end = desc_idx;
416 }
417
418 static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
419 struct bgmac_slot_info *slot)
420 {
421 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
422
423 dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
424 DMA_FROM_DEVICE);
425 rx->len = cpu_to_le16(0xdead);
426 rx->flags = cpu_to_le16(0xbeef);
427 dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
428 DMA_FROM_DEVICE);
429 }
430
431 static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
432 int weight)
433 {
434 u32 end_slot;
435 int handled = 0;
436
437 end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
438 end_slot &= BGMAC_DMA_RX_STATDPTR;
439 end_slot -= ring->index_base;
440 end_slot &= BGMAC_DMA_RX_STATDPTR;
441 end_slot /= sizeof(struct bgmac_dma_desc);
442
443 while (ring->start != end_slot) {
444 struct device *dma_dev = bgmac->dma_dev;
445 struct bgmac_slot_info *slot = &ring->slots[ring->start];
446 struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
447 struct sk_buff *skb;
448 void *buf = slot->buf;
449 dma_addr_t dma_addr = slot->dma_addr;
450 u16 len, flags;
451
452 do {
453 /* Prepare new skb as replacement */
454 if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
455 bgmac_dma_rx_poison_buf(dma_dev, slot);
456 break;
457 }
458
459 /* Unmap buffer to make it accessible to the CPU */
460 dma_unmap_single(dma_dev, dma_addr,
461 BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
462
463 /* Get info from the header */
464 len = le16_to_cpu(rx->len);
465 flags = le16_to_cpu(rx->flags);
466
467 /* Check for poison and drop or pass the packet */
468 if (len == 0xdead && flags == 0xbeef) {
469 netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
470 ring->start);
471 put_page(virt_to_head_page(buf));
472 bgmac->net_dev->stats.rx_errors++;
473 break;
474 }
475
476 if (len > BGMAC_RX_ALLOC_SIZE) {
477 netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
478 ring->start);
479 put_page(virt_to_head_page(buf));
480 bgmac->net_dev->stats.rx_length_errors++;
481 bgmac->net_dev->stats.rx_errors++;
482 break;
483 }
484
485 /* Omit CRC. */
486 len -= ETH_FCS_LEN;
487
488 skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
489 if (unlikely(!skb)) {
490 netdev_err(bgmac->net_dev, "build_skb failed\n");
491 put_page(virt_to_head_page(buf));
492 bgmac->net_dev->stats.rx_errors++;
493 break;
494 }
495 skb_put(skb, BGMAC_RX_FRAME_OFFSET +
496 BGMAC_RX_BUF_OFFSET + len);
497 skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
498 BGMAC_RX_BUF_OFFSET);
499
500 skb_checksum_none_assert(skb);
501 skb->protocol = eth_type_trans(skb, bgmac->net_dev);
502 bgmac->net_dev->stats.rx_bytes += len;
503 bgmac->net_dev->stats.rx_packets++;
504 napi_gro_receive(&bgmac->napi, skb);
505 handled++;
506 } while (0);
507
508 bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
509
510 if (++ring->start >= BGMAC_RX_RING_SLOTS)
511 ring->start = 0;
512
513 if (handled >= weight) /* Should never be greater */
514 break;
515 }
516
517 bgmac_dma_rx_update_index(bgmac, ring);
518
519 return handled;
520 }
521
522 /* Does ring support unaligned addressing? */
523 static bool bgmac_dma_unaligned(struct bgmac *bgmac,
524 struct bgmac_dma_ring *ring,
525 enum bgmac_dma_ring_type ring_type)
526 {
527 switch (ring_type) {
528 case BGMAC_DMA_RING_TX:
529 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
530 0xff0);
531 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
532 return true;
533 break;
534 case BGMAC_DMA_RING_RX:
535 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
536 0xff0);
537 if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
538 return true;
539 break;
540 }
541 return false;
542 }
543
544 static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
545 struct bgmac_dma_ring *ring)
546 {
547 struct device *dma_dev = bgmac->dma_dev;
548 struct bgmac_dma_desc *dma_desc = ring->cpu_base;
549 struct bgmac_slot_info *slot;
550 int i;
551
552 for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
553 int len = dma_desc[i].ctl1 & BGMAC_DESC_CTL1_LEN;
554
555 slot = &ring->slots[i];
556 dev_kfree_skb(slot->skb);
557
558 if (!slot->dma_addr)
559 continue;
560
561 if (slot->skb)
562 dma_unmap_single(dma_dev, slot->dma_addr,
563 len, DMA_TO_DEVICE);
564 else
565 dma_unmap_page(dma_dev, slot->dma_addr,
566 len, DMA_TO_DEVICE);
567 }
568 }
569
570 static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
571 struct bgmac_dma_ring *ring)
572 {
573 struct device *dma_dev = bgmac->dma_dev;
574 struct bgmac_slot_info *slot;
575 int i;
576
577 for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
578 slot = &ring->slots[i];
579 if (!slot->dma_addr)
580 continue;
581
582 dma_unmap_single(dma_dev, slot->dma_addr,
583 BGMAC_RX_BUF_SIZE,
584 DMA_FROM_DEVICE);
585 put_page(virt_to_head_page(slot->buf));
586 slot->dma_addr = 0;
587 }
588 }
589
590 static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
591 struct bgmac_dma_ring *ring,
592 int num_slots)
593 {
594 struct device *dma_dev = bgmac->dma_dev;
595 int size;
596
597 if (!ring->cpu_base)
598 return;
599
600 /* Free ring of descriptors */
601 size = num_slots * sizeof(struct bgmac_dma_desc);
602 dma_free_coherent(dma_dev, size, ring->cpu_base,
603 ring->dma_base);
604 }
605
606 static void bgmac_dma_cleanup(struct bgmac *bgmac)
607 {
608 int i;
609
610 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
611 bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
612
613 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
614 bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
615 }
616
617 static void bgmac_dma_free(struct bgmac *bgmac)
618 {
619 int i;
620
621 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
622 bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
623 BGMAC_TX_RING_SLOTS);
624
625 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
626 bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
627 BGMAC_RX_RING_SLOTS);
628 }
629
630 static int bgmac_dma_alloc(struct bgmac *bgmac)
631 {
632 struct device *dma_dev = bgmac->dma_dev;
633 struct bgmac_dma_ring *ring;
634 static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
635 BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
636 int size; /* ring size: different for Tx and Rx */
637 int err;
638 int i;
639
640 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
641 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
642
643 if (!(bcma_aread32(bgmac->core, BCMA_IOST) & BCMA_IOST_DMA64)) {
644 dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
645 return -ENOTSUPP;
646 }
647
648 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
649 ring = &bgmac->tx_ring[i];
650 ring->mmio_base = ring_base[i];
651
652 /* Alloc ring of descriptors */
653 size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
654 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
655 &ring->dma_base,
656 GFP_KERNEL);
657 if (!ring->cpu_base) {
658 dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
659 ring->mmio_base);
660 goto err_dma_free;
661 }
662
663 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
664 BGMAC_DMA_RING_TX);
665 if (ring->unaligned)
666 ring->index_base = lower_32_bits(ring->dma_base);
667 else
668 ring->index_base = 0;
669
670 /* No need to alloc TX slots yet */
671 }
672
673 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
674 ring = &bgmac->rx_ring[i];
675 ring->mmio_base = ring_base[i];
676
677 /* Alloc ring of descriptors */
678 size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
679 ring->cpu_base = dma_zalloc_coherent(dma_dev, size,
680 &ring->dma_base,
681 GFP_KERNEL);
682 if (!ring->cpu_base) {
683 dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
684 ring->mmio_base);
685 err = -ENOMEM;
686 goto err_dma_free;
687 }
688
689 ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
690 BGMAC_DMA_RING_RX);
691 if (ring->unaligned)
692 ring->index_base = lower_32_bits(ring->dma_base);
693 else
694 ring->index_base = 0;
695 }
696
697 return 0;
698
699 err_dma_free:
700 bgmac_dma_free(bgmac);
701 return -ENOMEM;
702 }
703
704 static int bgmac_dma_init(struct bgmac *bgmac)
705 {
706 struct bgmac_dma_ring *ring;
707 int i, err;
708
709 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
710 ring = &bgmac->tx_ring[i];
711
712 if (!ring->unaligned)
713 bgmac_dma_tx_enable(bgmac, ring);
714 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
715 lower_32_bits(ring->dma_base));
716 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
717 upper_32_bits(ring->dma_base));
718 if (ring->unaligned)
719 bgmac_dma_tx_enable(bgmac, ring);
720
721 ring->start = 0;
722 ring->end = 0; /* Points the slot that should *not* be read */
723 }
724
725 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
726 int j;
727
728 ring = &bgmac->rx_ring[i];
729
730 if (!ring->unaligned)
731 bgmac_dma_rx_enable(bgmac, ring);
732 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
733 lower_32_bits(ring->dma_base));
734 bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
735 upper_32_bits(ring->dma_base));
736 if (ring->unaligned)
737 bgmac_dma_rx_enable(bgmac, ring);
738
739 ring->start = 0;
740 ring->end = 0;
741 for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
742 err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
743 if (err)
744 goto error;
745
746 bgmac_dma_rx_setup_desc(bgmac, ring, j);
747 }
748
749 bgmac_dma_rx_update_index(bgmac, ring);
750 }
751
752 return 0;
753
754 error:
755 bgmac_dma_cleanup(bgmac);
756 return err;
757 }
758
759 /**************************************************
760 * PHY ops
761 **************************************************/
762
763 static u16 bgmac_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
764 {
765 struct bcma_device *core;
766 u16 phy_access_addr;
767 u16 phy_ctl_addr;
768 u32 tmp;
769
770 BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
771 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
772 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
773 BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
774 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
775 BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
776 BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
777 BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
778 BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
779 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
780 BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
781
782 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
783 core = bgmac->core->bus->drv_gmac_cmn.core;
784 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
785 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
786 } else {
787 core = bgmac->core;
788 phy_access_addr = BGMAC_PHY_ACCESS;
789 phy_ctl_addr = BGMAC_PHY_CNTL;
790 }
791
792 tmp = bcma_read32(core, phy_ctl_addr);
793 tmp &= ~BGMAC_PC_EPA_MASK;
794 tmp |= phyaddr;
795 bcma_write32(core, phy_ctl_addr, tmp);
796
797 tmp = BGMAC_PA_START;
798 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
799 tmp |= reg << BGMAC_PA_REG_SHIFT;
800 bcma_write32(core, phy_access_addr, tmp);
801
802 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
803 dev_err(bgmac->dev, "Reading PHY %d register 0x%X failed\n",
804 phyaddr, reg);
805 return 0xffff;
806 }
807
808 return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
809 }
810
811 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
812 static int bgmac_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg, u16 value)
813 {
814 struct bcma_device *core;
815 u16 phy_access_addr;
816 u16 phy_ctl_addr;
817 u32 tmp;
818
819 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT) {
820 core = bgmac->core->bus->drv_gmac_cmn.core;
821 phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
822 phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
823 } else {
824 core = bgmac->core;
825 phy_access_addr = BGMAC_PHY_ACCESS;
826 phy_ctl_addr = BGMAC_PHY_CNTL;
827 }
828
829 tmp = bcma_read32(core, phy_ctl_addr);
830 tmp &= ~BGMAC_PC_EPA_MASK;
831 tmp |= phyaddr;
832 bcma_write32(core, phy_ctl_addr, tmp);
833
834 bgmac_write(bgmac, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
835 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
836 dev_warn(bgmac->dev, "Error setting MDIO int\n");
837
838 tmp = BGMAC_PA_START;
839 tmp |= BGMAC_PA_WRITE;
840 tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
841 tmp |= reg << BGMAC_PA_REG_SHIFT;
842 tmp |= value;
843 bcma_write32(core, phy_access_addr, tmp);
844
845 if (!bgmac_wait_value(core, phy_access_addr, BGMAC_PA_START, 0, 1000)) {
846 dev_err(bgmac->dev, "Writing to PHY %d register 0x%X failed\n",
847 phyaddr, reg);
848 return -ETIMEDOUT;
849 }
850
851 return 0;
852 }
853
854 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
855 static void bgmac_phy_init(struct bgmac *bgmac)
856 {
857 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
858 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
859 u8 i;
860
861 if (ci->id == BCMA_CHIP_ID_BCM5356) {
862 for (i = 0; i < 5; i++) {
863 bgmac_phy_write(bgmac, i, 0x1f, 0x008b);
864 bgmac_phy_write(bgmac, i, 0x15, 0x0100);
865 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
866 bgmac_phy_write(bgmac, i, 0x12, 0x2aaa);
867 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
868 }
869 }
870 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
871 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
872 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
873 bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
874 bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
875 for (i = 0; i < 5; i++) {
876 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
877 bgmac_phy_write(bgmac, i, 0x16, 0x5284);
878 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
879 bgmac_phy_write(bgmac, i, 0x17, 0x0010);
880 bgmac_phy_write(bgmac, i, 0x1f, 0x000f);
881 bgmac_phy_write(bgmac, i, 0x16, 0x5296);
882 bgmac_phy_write(bgmac, i, 0x17, 0x1073);
883 bgmac_phy_write(bgmac, i, 0x17, 0x9073);
884 bgmac_phy_write(bgmac, i, 0x16, 0x52b6);
885 bgmac_phy_write(bgmac, i, 0x17, 0x9273);
886 bgmac_phy_write(bgmac, i, 0x1f, 0x000b);
887 }
888 }
889 }
890
891 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
892 static void bgmac_phy_reset(struct bgmac *bgmac)
893 {
894 if (bgmac->phyaddr == BGMAC_PHY_NOREGS)
895 return;
896
897 bgmac_phy_write(bgmac, bgmac->phyaddr, MII_BMCR, BMCR_RESET);
898 udelay(100);
899 if (bgmac_phy_read(bgmac, bgmac->phyaddr, MII_BMCR) & BMCR_RESET)
900 dev_err(bgmac->dev, "PHY reset failed\n");
901 bgmac_phy_init(bgmac);
902 }
903
904 /**************************************************
905 * Chip ops
906 **************************************************/
907
908 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
909 * nothing to change? Try if after stabilizng driver.
910 */
911 static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
912 bool force)
913 {
914 u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
915 u32 new_val = (cmdcfg & mask) | set;
916
917 bgmac_set(bgmac, BGMAC_CMDCFG, BGMAC_CMDCFG_SR(bgmac->core->id.rev));
918 udelay(2);
919
920 if (new_val != cmdcfg || force)
921 bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
922
923 bgmac_mask(bgmac, BGMAC_CMDCFG, ~BGMAC_CMDCFG_SR(bgmac->core->id.rev));
924 udelay(2);
925 }
926
927 static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
928 {
929 u32 tmp;
930
931 tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
932 bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
933 tmp = (addr[4] << 8) | addr[5];
934 bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
935 }
936
937 static void bgmac_set_rx_mode(struct net_device *net_dev)
938 {
939 struct bgmac *bgmac = netdev_priv(net_dev);
940
941 if (net_dev->flags & IFF_PROMISC)
942 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
943 else
944 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
945 }
946
947 #if 0 /* We don't use that regs yet */
948 static void bgmac_chip_stats_update(struct bgmac *bgmac)
949 {
950 int i;
951
952 if (bgmac->core->id.id != BCMA_CORE_4706_MAC_GBIT) {
953 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
954 bgmac->mib_tx_regs[i] =
955 bgmac_read(bgmac,
956 BGMAC_TX_GOOD_OCTETS + (i * 4));
957 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
958 bgmac->mib_rx_regs[i] =
959 bgmac_read(bgmac,
960 BGMAC_RX_GOOD_OCTETS + (i * 4));
961 }
962
963 /* TODO: what else? how to handle BCM4706? Specs are needed */
964 }
965 #endif
966
967 static void bgmac_clear_mib(struct bgmac *bgmac)
968 {
969 int i;
970
971 if (bgmac->core->id.id == BCMA_CORE_4706_MAC_GBIT)
972 return;
973
974 bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
975 for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
976 bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
977 for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
978 bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
979 }
980
981 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
982 static void bgmac_mac_speed(struct bgmac *bgmac)
983 {
984 u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
985 u32 set = 0;
986
987 switch (bgmac->mac_speed) {
988 case SPEED_10:
989 set |= BGMAC_CMDCFG_ES_10;
990 break;
991 case SPEED_100:
992 set |= BGMAC_CMDCFG_ES_100;
993 break;
994 case SPEED_1000:
995 set |= BGMAC_CMDCFG_ES_1000;
996 break;
997 case SPEED_2500:
998 set |= BGMAC_CMDCFG_ES_2500;
999 break;
1000 default:
1001 dev_err(bgmac->dev, "Unsupported speed: %d\n",
1002 bgmac->mac_speed);
1003 }
1004
1005 if (bgmac->mac_duplex == DUPLEX_HALF)
1006 set |= BGMAC_CMDCFG_HD;
1007
1008 bgmac_cmdcfg_maskset(bgmac, mask, set, true);
1009 }
1010
1011 static void bgmac_miiconfig(struct bgmac *bgmac)
1012 {
1013 struct bcma_device *core = bgmac->core;
1014 u8 imode;
1015
1016 if (bgmac_is_bcm4707_family(bgmac)) {
1017 bcma_awrite32(core, BCMA_IOCTL,
1018 bcma_aread32(core, BCMA_IOCTL) | 0x40 |
1019 BGMAC_BCMA_IOCTL_SW_CLKEN);
1020 bgmac->mac_speed = SPEED_2500;
1021 bgmac->mac_duplex = DUPLEX_FULL;
1022 bgmac_mac_speed(bgmac);
1023 } else {
1024 imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
1025 BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
1026 if (imode == 0 || imode == 1) {
1027 bgmac->mac_speed = SPEED_100;
1028 bgmac->mac_duplex = DUPLEX_FULL;
1029 bgmac_mac_speed(bgmac);
1030 }
1031 }
1032 }
1033
1034 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
1035 static void bgmac_chip_reset(struct bgmac *bgmac)
1036 {
1037 struct bcma_device *core = bgmac->core;
1038 struct bcma_bus *bus = core->bus;
1039 struct bcma_chipinfo *ci = &bus->chipinfo;
1040 u32 flags;
1041 u32 iost;
1042 int i;
1043
1044 if (bcma_core_is_enabled(core)) {
1045 if (!bgmac->stats_grabbed) {
1046 /* bgmac_chip_stats_update(bgmac); */
1047 bgmac->stats_grabbed = true;
1048 }
1049
1050 for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
1051 bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
1052
1053 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1054 udelay(1);
1055
1056 for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
1057 bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
1058
1059 /* TODO: Clear software multicast filter list */
1060 }
1061
1062 iost = bcma_aread32(core, BCMA_IOST);
1063 if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1064 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1065 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188))
1066 iost &= ~BGMAC_BCMA_IOST_ATTACHED;
1067
1068 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
1069 if (ci->id != BCMA_CHIP_ID_BCM4707 &&
1070 ci->id != BCMA_CHIP_ID_BCM47094) {
1071 flags = 0;
1072 if (iost & BGMAC_BCMA_IOST_ATTACHED) {
1073 flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
1074 if (!bgmac->has_robosw)
1075 flags |= BGMAC_BCMA_IOCTL_SW_RESET;
1076 }
1077 bcma_core_enable(core, flags);
1078 }
1079
1080 /* Request Misc PLL for corerev > 2 */
1081 if (core->id.rev > 2 && !bgmac_is_bcm4707_family(bgmac)) {
1082 bgmac_set(bgmac, BCMA_CLKCTLST,
1083 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
1084 bgmac_wait_value(bgmac->core, BCMA_CLKCTLST,
1085 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1086 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
1087 1000);
1088 }
1089
1090 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1091 ci->id == BCMA_CHIP_ID_BCM4749 ||
1092 ci->id == BCMA_CHIP_ID_BCM53572) {
1093 struct bcma_drv_cc *cc = &bgmac->core->bus->drv_cc;
1094 u8 et_swtype = 0;
1095 u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
1096 BGMAC_CHIPCTL_1_IF_TYPE_MII;
1097 char buf[4];
1098
1099 if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
1100 if (kstrtou8(buf, 0, &et_swtype))
1101 dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
1102 buf);
1103 et_swtype &= 0x0f;
1104 et_swtype <<= 4;
1105 sw_type = et_swtype;
1106 } else if (ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM5358) {
1107 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
1108 } else if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg == BCMA_PKG_ID_BCM47186) ||
1109 (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg == 10) ||
1110 (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg == BCMA_PKG_ID_BCM47188)) {
1111 sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
1112 BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
1113 }
1114 bcma_chipco_chipctl_maskset(cc, 1,
1115 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
1116 BGMAC_CHIPCTL_1_SW_TYPE_MASK),
1117 sw_type);
1118 }
1119
1120 if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
1121 bcma_awrite32(core, BCMA_IOCTL,
1122 bcma_aread32(core, BCMA_IOCTL) &
1123 ~BGMAC_BCMA_IOCTL_SW_RESET);
1124
1125 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1126 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1127 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1128 * be keps until taking MAC out of the reset.
1129 */
1130 bgmac_cmdcfg_maskset(bgmac,
1131 ~(BGMAC_CMDCFG_TE |
1132 BGMAC_CMDCFG_RE |
1133 BGMAC_CMDCFG_RPI |
1134 BGMAC_CMDCFG_TAI |
1135 BGMAC_CMDCFG_HD |
1136 BGMAC_CMDCFG_ML |
1137 BGMAC_CMDCFG_CFE |
1138 BGMAC_CMDCFG_RL |
1139 BGMAC_CMDCFG_RED |
1140 BGMAC_CMDCFG_PE |
1141 BGMAC_CMDCFG_TPI |
1142 BGMAC_CMDCFG_PAD_EN |
1143 BGMAC_CMDCFG_PF),
1144 BGMAC_CMDCFG_PROM |
1145 BGMAC_CMDCFG_NLC |
1146 BGMAC_CMDCFG_CFE |
1147 BGMAC_CMDCFG_SR(core->id.rev),
1148 false);
1149 bgmac->mac_speed = SPEED_UNKNOWN;
1150 bgmac->mac_duplex = DUPLEX_UNKNOWN;
1151
1152 bgmac_clear_mib(bgmac);
1153 if (core->id.id == BCMA_CORE_4706_MAC_GBIT)
1154 bcma_maskset32(bgmac->cmn, BCMA_GMAC_CMN_PHY_CTL, ~0,
1155 BCMA_GMAC_CMN_PC_MTE);
1156 else
1157 bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
1158 bgmac_miiconfig(bgmac);
1159 bgmac_phy_init(bgmac);
1160
1161 netdev_reset_queue(bgmac->net_dev);
1162 }
1163
1164 static void bgmac_chip_intrs_on(struct bgmac *bgmac)
1165 {
1166 bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
1167 }
1168
1169 static void bgmac_chip_intrs_off(struct bgmac *bgmac)
1170 {
1171 bgmac_write(bgmac, BGMAC_INT_MASK, 0);
1172 bgmac_read(bgmac, BGMAC_INT_MASK);
1173 }
1174
1175 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1176 static void bgmac_enable(struct bgmac *bgmac)
1177 {
1178 struct bcma_chipinfo *ci = &bgmac->core->bus->chipinfo;
1179 u32 cmdcfg;
1180 u32 mode;
1181 u32 rxq_ctl;
1182 u32 fl_ctl;
1183 u16 bp_clk;
1184 u8 mdp;
1185
1186 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
1187 bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
1188 BGMAC_CMDCFG_SR(bgmac->core->id.rev), true);
1189 udelay(2);
1190 cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
1191 bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
1192
1193 mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
1194 BGMAC_DS_MM_SHIFT;
1195 if (ci->id != BCMA_CHIP_ID_BCM47162 || mode != 0)
1196 bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1197 if (ci->id == BCMA_CHIP_ID_BCM47162 && mode == 2)
1198 bcma_chipco_chipctl_maskset(&bgmac->core->bus->drv_cc, 1, ~0,
1199 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
1200
1201 switch (ci->id) {
1202 case BCMA_CHIP_ID_BCM5357:
1203 case BCMA_CHIP_ID_BCM4749:
1204 case BCMA_CHIP_ID_BCM53572:
1205 case BCMA_CHIP_ID_BCM4716:
1206 case BCMA_CHIP_ID_BCM47162:
1207 fl_ctl = 0x03cb04cb;
1208 if (ci->id == BCMA_CHIP_ID_BCM5357 ||
1209 ci->id == BCMA_CHIP_ID_BCM4749 ||
1210 ci->id == BCMA_CHIP_ID_BCM53572)
1211 fl_ctl = 0x2300e1;
1212 bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
1213 bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
1214 break;
1215 }
1216
1217 if (!bgmac_is_bcm4707_family(bgmac)) {
1218 rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
1219 rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
1220 bp_clk = bcma_pmu_get_bus_clock(&bgmac->core->bus->drv_cc) /
1221 1000000;
1222 mdp = (bp_clk * 128 / 1000) - 3;
1223 rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
1224 bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
1225 }
1226 }
1227
1228 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1229 static void bgmac_chip_init(struct bgmac *bgmac)
1230 {
1231 /* 1 interrupt per received frame */
1232 bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
1233
1234 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1235 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
1236
1237 bgmac_set_rx_mode(bgmac->net_dev);
1238
1239 bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
1240
1241 if (bgmac->loopback)
1242 bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
1243 else
1244 bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
1245
1246 bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
1247
1248 bgmac_chip_intrs_on(bgmac);
1249
1250 bgmac_enable(bgmac);
1251 }
1252
1253 static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
1254 {
1255 struct bgmac *bgmac = netdev_priv(dev_id);
1256
1257 u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
1258 int_status &= bgmac->int_mask;
1259
1260 if (!int_status)
1261 return IRQ_NONE;
1262
1263 int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
1264 if (int_status)
1265 dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
1266
1267 /* Disable new interrupts until handling existing ones */
1268 bgmac_chip_intrs_off(bgmac);
1269
1270 napi_schedule(&bgmac->napi);
1271
1272 return IRQ_HANDLED;
1273 }
1274
1275 static int bgmac_poll(struct napi_struct *napi, int weight)
1276 {
1277 struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
1278 int handled = 0;
1279
1280 /* Ack */
1281 bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
1282
1283 bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
1284 handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
1285
1286 /* Poll again if more events arrived in the meantime */
1287 if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
1288 return weight;
1289
1290 if (handled < weight) {
1291 napi_complete(napi);
1292 bgmac_chip_intrs_on(bgmac);
1293 }
1294
1295 return handled;
1296 }
1297
1298 /**************************************************
1299 * net_device_ops
1300 **************************************************/
1301
1302 static int bgmac_open(struct net_device *net_dev)
1303 {
1304 struct bgmac *bgmac = netdev_priv(net_dev);
1305 int err = 0;
1306
1307 bgmac_chip_reset(bgmac);
1308
1309 err = bgmac_dma_init(bgmac);
1310 if (err)
1311 return err;
1312
1313 /* Specs say about reclaiming rings here, but we do that in DMA init */
1314 bgmac_chip_init(bgmac);
1315
1316 err = request_irq(bgmac->core->irq, bgmac_interrupt, IRQF_SHARED,
1317 KBUILD_MODNAME, net_dev);
1318 if (err < 0) {
1319 dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
1320 bgmac_dma_cleanup(bgmac);
1321 return err;
1322 }
1323 napi_enable(&bgmac->napi);
1324
1325 phy_start(net_dev->phydev);
1326
1327 netif_start_queue(net_dev);
1328
1329 return 0;
1330 }
1331
1332 static int bgmac_stop(struct net_device *net_dev)
1333 {
1334 struct bgmac *bgmac = netdev_priv(net_dev);
1335
1336 netif_carrier_off(net_dev);
1337
1338 phy_stop(net_dev->phydev);
1339
1340 napi_disable(&bgmac->napi);
1341 bgmac_chip_intrs_off(bgmac);
1342 free_irq(bgmac->core->irq, net_dev);
1343
1344 bgmac_chip_reset(bgmac);
1345 bgmac_dma_cleanup(bgmac);
1346
1347 return 0;
1348 }
1349
1350 static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
1351 struct net_device *net_dev)
1352 {
1353 struct bgmac *bgmac = netdev_priv(net_dev);
1354 struct bgmac_dma_ring *ring;
1355
1356 /* No QOS support yet */
1357 ring = &bgmac->tx_ring[0];
1358 return bgmac_dma_tx_add(bgmac, ring, skb);
1359 }
1360
1361 static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
1362 {
1363 struct bgmac *bgmac = netdev_priv(net_dev);
1364 int ret;
1365
1366 ret = eth_prepare_mac_addr_change(net_dev, addr);
1367 if (ret < 0)
1368 return ret;
1369 bgmac_write_mac_address(bgmac, (u8 *)addr);
1370 eth_commit_mac_addr_change(net_dev, addr);
1371 return 0;
1372 }
1373
1374 static int bgmac_ioctl(struct net_device *net_dev, struct ifreq *ifr, int cmd)
1375 {
1376 if (!netif_running(net_dev))
1377 return -EINVAL;
1378
1379 return phy_mii_ioctl(net_dev->phydev, ifr, cmd);
1380 }
1381
1382 static const struct net_device_ops bgmac_netdev_ops = {
1383 .ndo_open = bgmac_open,
1384 .ndo_stop = bgmac_stop,
1385 .ndo_start_xmit = bgmac_start_xmit,
1386 .ndo_set_rx_mode = bgmac_set_rx_mode,
1387 .ndo_set_mac_address = bgmac_set_mac_address,
1388 .ndo_validate_addr = eth_validate_addr,
1389 .ndo_do_ioctl = bgmac_ioctl,
1390 };
1391
1392 /**************************************************
1393 * ethtool_ops
1394 **************************************************/
1395
1396 struct bgmac_stat {
1397 u8 size;
1398 u32 offset;
1399 const char *name;
1400 };
1401
1402 static struct bgmac_stat bgmac_get_strings_stats[] = {
1403 { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
1404 { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
1405 { 8, BGMAC_TX_OCTETS, "tx_octets" },
1406 { 4, BGMAC_TX_PKTS, "tx_pkts" },
1407 { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
1408 { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
1409 { 4, BGMAC_TX_LEN_64, "tx_64" },
1410 { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
1411 { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
1412 { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
1413 { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
1414 { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
1415 { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
1416 { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
1417 { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
1418 { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
1419 { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
1420 { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
1421 { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
1422 { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
1423 { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
1424 { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
1425 { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
1426 { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
1427 { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
1428 { 4, BGMAC_TX_DEFERED, "tx_defered" },
1429 { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
1430 { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
1431 { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
1432 { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
1433 { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
1434 { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
1435 { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
1436 { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
1437 { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
1438 { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
1439 { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
1440 { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
1441 { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
1442 { 8, BGMAC_RX_OCTETS, "rx_octets" },
1443 { 4, BGMAC_RX_PKTS, "rx_pkts" },
1444 { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
1445 { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
1446 { 4, BGMAC_RX_LEN_64, "rx_64" },
1447 { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
1448 { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
1449 { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
1450 { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
1451 { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
1452 { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
1453 { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
1454 { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
1455 { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
1456 { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
1457 { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
1458 { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
1459 { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
1460 { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
1461 { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
1462 { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
1463 { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
1464 { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
1465 { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
1466 { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
1467 { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
1468 { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
1469 };
1470
1471 #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
1472
1473 static int bgmac_get_sset_count(struct net_device *dev, int string_set)
1474 {
1475 switch (string_set) {
1476 case ETH_SS_STATS:
1477 return BGMAC_STATS_LEN;
1478 }
1479
1480 return -EOPNOTSUPP;
1481 }
1482
1483 static void bgmac_get_strings(struct net_device *dev, u32 stringset,
1484 u8 *data)
1485 {
1486 int i;
1487
1488 if (stringset != ETH_SS_STATS)
1489 return;
1490
1491 for (i = 0; i < BGMAC_STATS_LEN; i++)
1492 strlcpy(data + i * ETH_GSTRING_LEN,
1493 bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
1494 }
1495
1496 static void bgmac_get_ethtool_stats(struct net_device *dev,
1497 struct ethtool_stats *ss, uint64_t *data)
1498 {
1499 struct bgmac *bgmac = netdev_priv(dev);
1500 const struct bgmac_stat *s;
1501 unsigned int i;
1502 u64 val;
1503
1504 if (!netif_running(dev))
1505 return;
1506
1507 for (i = 0; i < BGMAC_STATS_LEN; i++) {
1508 s = &bgmac_get_strings_stats[i];
1509 val = 0;
1510 if (s->size == 8)
1511 val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
1512 val |= bgmac_read(bgmac, s->offset);
1513 data[i] = val;
1514 }
1515 }
1516
1517 static void bgmac_get_drvinfo(struct net_device *net_dev,
1518 struct ethtool_drvinfo *info)
1519 {
1520 strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
1521 strlcpy(info->bus_info, "BCMA", sizeof(info->bus_info));
1522 }
1523
1524 static const struct ethtool_ops bgmac_ethtool_ops = {
1525 .get_strings = bgmac_get_strings,
1526 .get_sset_count = bgmac_get_sset_count,
1527 .get_ethtool_stats = bgmac_get_ethtool_stats,
1528 .get_drvinfo = bgmac_get_drvinfo,
1529 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1530 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1531 };
1532
1533 /**************************************************
1534 * MII
1535 **************************************************/
1536
1537 static int bgmac_mii_read(struct mii_bus *bus, int mii_id, int regnum)
1538 {
1539 return bgmac_phy_read(bus->priv, mii_id, regnum);
1540 }
1541
1542 static int bgmac_mii_write(struct mii_bus *bus, int mii_id, int regnum,
1543 u16 value)
1544 {
1545 return bgmac_phy_write(bus->priv, mii_id, regnum, value);
1546 }
1547
1548 static void bgmac_adjust_link(struct net_device *net_dev)
1549 {
1550 struct bgmac *bgmac = netdev_priv(net_dev);
1551 struct phy_device *phy_dev = net_dev->phydev;
1552 bool update = false;
1553
1554 if (phy_dev->link) {
1555 if (phy_dev->speed != bgmac->mac_speed) {
1556 bgmac->mac_speed = phy_dev->speed;
1557 update = true;
1558 }
1559
1560 if (phy_dev->duplex != bgmac->mac_duplex) {
1561 bgmac->mac_duplex = phy_dev->duplex;
1562 update = true;
1563 }
1564 }
1565
1566 if (update) {
1567 bgmac_mac_speed(bgmac);
1568 phy_print_status(phy_dev);
1569 }
1570 }
1571
1572 static int bgmac_fixed_phy_register(struct bgmac *bgmac)
1573 {
1574 struct fixed_phy_status fphy_status = {
1575 .link = 1,
1576 .speed = SPEED_1000,
1577 .duplex = DUPLEX_FULL,
1578 };
1579 struct phy_device *phy_dev;
1580 int err;
1581
1582 phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
1583 if (!phy_dev || IS_ERR(phy_dev)) {
1584 dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
1585 return -ENODEV;
1586 }
1587
1588 err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
1589 PHY_INTERFACE_MODE_MII);
1590 if (err) {
1591 dev_err(bgmac->dev, "Connecting PHY failed\n");
1592 return err;
1593 }
1594
1595 return err;
1596 }
1597
1598 static int bgmac_mii_register(struct bgmac *bgmac)
1599 {
1600 struct mii_bus *mii_bus;
1601 struct phy_device *phy_dev;
1602 char bus_id[MII_BUS_ID_SIZE + 3];
1603 int err = 0;
1604
1605 if (bgmac_is_bcm4707_family(bgmac))
1606 return bgmac_fixed_phy_register(bgmac);
1607
1608 mii_bus = mdiobus_alloc();
1609 if (!mii_bus)
1610 return -ENOMEM;
1611
1612 mii_bus->name = "bgmac mii bus";
1613 sprintf(mii_bus->id, "%s-%d-%d", "bgmac", bgmac->core->bus->num,
1614 bgmac->core->core_unit);
1615 mii_bus->priv = bgmac;
1616 mii_bus->read = bgmac_mii_read;
1617 mii_bus->write = bgmac_mii_write;
1618 mii_bus->parent = &bgmac->core->dev;
1619 mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
1620
1621 err = mdiobus_register(mii_bus);
1622 if (err) {
1623 dev_err(bgmac->dev, "Registration of mii bus failed\n");
1624 goto err_free_bus;
1625 }
1626
1627 bgmac->mii_bus = mii_bus;
1628
1629 /* Connect to the PHY */
1630 snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
1631 bgmac->phyaddr);
1632 phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
1633 PHY_INTERFACE_MODE_MII);
1634 if (IS_ERR(phy_dev)) {
1635 dev_err(bgmac->dev, "PHY connecton failed\n");
1636 err = PTR_ERR(phy_dev);
1637 goto err_unregister_bus;
1638 }
1639
1640 return err;
1641
1642 err_unregister_bus:
1643 mdiobus_unregister(mii_bus);
1644 err_free_bus:
1645 mdiobus_free(mii_bus);
1646 return err;
1647 }
1648
1649 static void bgmac_mii_unregister(struct bgmac *bgmac)
1650 {
1651 struct mii_bus *mii_bus = bgmac->mii_bus;
1652
1653 mdiobus_unregister(mii_bus);
1654 mdiobus_free(mii_bus);
1655 }
1656
1657 /**************************************************
1658 * BCMA bus ops
1659 **************************************************/
1660
1661 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1662 static int bgmac_probe(struct bcma_device *core)
1663 {
1664 struct net_device *net_dev;
1665 struct bgmac *bgmac;
1666 struct ssb_sprom *sprom = &core->bus->sprom;
1667 u8 *mac;
1668 int err;
1669
1670 switch (core->core_unit) {
1671 case 0:
1672 mac = sprom->et0mac;
1673 break;
1674 case 1:
1675 mac = sprom->et1mac;
1676 break;
1677 case 2:
1678 mac = sprom->et2mac;
1679 break;
1680 default:
1681 dev_err(&core->dev, "Unsupported core_unit %d\n",
1682 core->core_unit);
1683 return -ENOTSUPP;
1684 }
1685
1686 if (!is_valid_ether_addr(mac)) {
1687 dev_err(&core->dev, "Invalid MAC addr: %pM\n", mac);
1688 eth_random_addr(mac);
1689 dev_warn(&core->dev, "Using random MAC: %pM\n", mac);
1690 }
1691
1692 /* This (reset &) enable is not preset in specs or reference driver but
1693 * Broadcom does it in arch PCI code when enabling fake PCI device.
1694 */
1695 bcma_core_enable(core, 0);
1696
1697 /* Allocation and references */
1698 net_dev = alloc_etherdev(sizeof(*bgmac));
1699 if (!net_dev)
1700 return -ENOMEM;
1701 net_dev->netdev_ops = &bgmac_netdev_ops;
1702 net_dev->irq = core->irq;
1703 net_dev->ethtool_ops = &bgmac_ethtool_ops;
1704 bgmac = netdev_priv(net_dev);
1705 bgmac->dev = &core->dev;
1706 bgmac->dma_dev = core->dma_dev;
1707 bgmac->net_dev = net_dev;
1708 bgmac->core = core;
1709 bcma_set_drvdata(core, bgmac);
1710 SET_NETDEV_DEV(net_dev, &core->dev);
1711
1712 /* Defaults */
1713 memcpy(bgmac->net_dev->dev_addr, mac, ETH_ALEN);
1714
1715 /* On BCM4706 we need common core to access PHY */
1716 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1717 !core->bus->drv_gmac_cmn.core) {
1718 dev_err(bgmac->dev, "GMAC CMN core not found (required for BCM4706)\n");
1719 err = -ENODEV;
1720 goto err_netdev_free;
1721 }
1722 bgmac->cmn = core->bus->drv_gmac_cmn.core;
1723
1724 switch (core->core_unit) {
1725 case 0:
1726 bgmac->phyaddr = sprom->et0phyaddr;
1727 break;
1728 case 1:
1729 bgmac->phyaddr = sprom->et1phyaddr;
1730 break;
1731 case 2:
1732 bgmac->phyaddr = sprom->et2phyaddr;
1733 break;
1734 }
1735 bgmac->phyaddr &= BGMAC_PHY_MASK;
1736 if (bgmac->phyaddr == BGMAC_PHY_MASK) {
1737 dev_err(bgmac->dev, "No PHY found\n");
1738 err = -ENODEV;
1739 goto err_netdev_free;
1740 }
1741 dev_info(bgmac->dev, "Found PHY addr: %d%s\n", bgmac->phyaddr,
1742 bgmac->phyaddr == BGMAC_PHY_NOREGS ? " (NOREGS)" : "");
1743
1744 if (core->bus->hosttype == BCMA_HOSTTYPE_PCI) {
1745 dev_err(bgmac->dev, "PCI setup not implemented\n");
1746 err = -ENOTSUPP;
1747 goto err_netdev_free;
1748 }
1749
1750 bgmac_chip_reset(bgmac);
1751
1752 /* For Northstar, we have to take all GMAC core out of reset */
1753 if (bgmac_is_bcm4707_family(bgmac)) {
1754 struct bcma_device *ns_core;
1755 int ns_gmac;
1756
1757 /* Northstar has 4 GMAC cores */
1758 for (ns_gmac = 0; ns_gmac < 4; ns_gmac++) {
1759 /* As Northstar requirement, we have to reset all GMACs
1760 * before accessing one. bgmac_chip_reset() call
1761 * bcma_core_enable() for this core. Then the other
1762 * three GMACs didn't reset. We do it here.
1763 */
1764 ns_core = bcma_find_core_unit(core->bus,
1765 BCMA_CORE_MAC_GBIT,
1766 ns_gmac);
1767 if (ns_core && !bcma_core_is_enabled(ns_core))
1768 bcma_core_enable(ns_core, 0);
1769 }
1770 }
1771
1772 err = bgmac_dma_alloc(bgmac);
1773 if (err) {
1774 dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
1775 goto err_netdev_free;
1776 }
1777
1778 bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
1779 if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
1780 bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
1781
1782 /* TODO: reset the external phy. Specs are needed */
1783 bgmac_phy_reset(bgmac);
1784
1785 bgmac->has_robosw = !!(core->bus->sprom.boardflags_lo &
1786 BGMAC_BFL_ENETROBO);
1787 if (bgmac->has_robosw)
1788 dev_warn(bgmac->dev, "Support for Roboswitch not implemented\n");
1789
1790 if (core->bus->sprom.boardflags_lo & BGMAC_BFL_ENETADM)
1791 dev_warn(bgmac->dev, "Support for ADMtek ethernet switch not implemented\n");
1792
1793 netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
1794
1795 err = bgmac_mii_register(bgmac);
1796 if (err) {
1797 dev_err(bgmac->dev, "Cannot connect to phy\n");
1798 goto err_dma_free;
1799 }
1800
1801 net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
1802 net_dev->hw_features = net_dev->features;
1803 net_dev->vlan_features = net_dev->features;
1804
1805 err = register_netdev(bgmac->net_dev);
1806 if (err) {
1807 dev_err(bgmac->dev, "Cannot register net device\n");
1808 goto err_mii_unregister;
1809 }
1810
1811 netif_carrier_off(net_dev);
1812
1813 return 0;
1814
1815 err_mii_unregister:
1816 bgmac_mii_unregister(bgmac);
1817 err_dma_free:
1818 bgmac_dma_free(bgmac);
1819
1820 err_netdev_free:
1821 bcma_set_drvdata(core, NULL);
1822 free_netdev(net_dev);
1823
1824 return err;
1825 }
1826
1827 static void bgmac_remove(struct bcma_device *core)
1828 {
1829 struct bgmac *bgmac = bcma_get_drvdata(core);
1830
1831 unregister_netdev(bgmac->net_dev);
1832 bgmac_mii_unregister(bgmac);
1833 netif_napi_del(&bgmac->napi);
1834 bgmac_dma_free(bgmac);
1835 bcma_set_drvdata(core, NULL);
1836 free_netdev(bgmac->net_dev);
1837 }
1838
1839 static struct bcma_driver bgmac_bcma_driver = {
1840 .name = KBUILD_MODNAME,
1841 .id_table = bgmac_bcma_tbl,
1842 .probe = bgmac_probe,
1843 .remove = bgmac_remove,
1844 };
1845
1846 static int __init bgmac_init(void)
1847 {
1848 int err;
1849
1850 err = bcma_driver_register(&bgmac_bcma_driver);
1851 if (err)
1852 return err;
1853 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1854
1855 return 0;
1856 }
1857
1858 static void __exit bgmac_exit(void)
1859 {
1860 bcma_driver_unregister(&bgmac_bcma_driver);
1861 }
1862
1863 module_init(bgmac_init)
1864 module_exit(bgmac_exit)
1865
1866 MODULE_AUTHOR("Rafał Miłecki");
1867 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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