2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
6 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/bcm47xx_nvram.h>
22 static const struct bcma_device_id bgmac_bcma_tbl
[] = {
23 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_4706_MAC_GBIT
, BCMA_ANY_REV
, BCMA_ANY_CLASS
),
24 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_MAC_GBIT
, BCMA_ANY_REV
, BCMA_ANY_CLASS
),
27 MODULE_DEVICE_TABLE(bcma
, bgmac_bcma_tbl
);
29 static inline bool bgmac_is_bcm4707_family(struct bgmac
*bgmac
)
31 switch (bgmac
->core
->bus
->chipinfo
.id
) {
32 case BCMA_CHIP_ID_BCM4707
:
33 case BCMA_CHIP_ID_BCM47094
:
34 case BCMA_CHIP_ID_BCM53018
:
41 static bool bgmac_wait_value(struct bcma_device
*core
, u16 reg
, u32 mask
,
42 u32 value
, int timeout
)
47 for (i
= 0; i
< timeout
/ 10; i
++) {
48 val
= bcma_read32(core
, reg
);
49 if ((val
& mask
) == value
)
53 pr_err("Timeout waiting for reg 0x%X\n", reg
);
57 /**************************************************
59 **************************************************/
61 static void bgmac_dma_tx_reset(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
69 /* Suspend DMA TX ring first.
70 * bgmac_wait_value doesn't support waiting for any of few values, so
71 * implement whole loop here.
73 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
,
74 BGMAC_DMA_TX_SUSPEND
);
75 for (i
= 0; i
< 10000 / 10; i
++) {
76 val
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
77 val
&= BGMAC_DMA_TX_STAT
;
78 if (val
== BGMAC_DMA_TX_STAT_DISABLED
||
79 val
== BGMAC_DMA_TX_STAT_IDLEWAIT
||
80 val
== BGMAC_DMA_TX_STAT_STOPPED
) {
87 bgmac_err(bgmac
, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
88 ring
->mmio_base
, val
);
90 /* Remove SUSPEND bit */
91 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
, 0);
92 if (!bgmac_wait_value(bgmac
->core
,
93 ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
,
94 BGMAC_DMA_TX_STAT
, BGMAC_DMA_TX_STAT_DISABLED
,
96 bgmac_warn(bgmac
, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
99 val
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
100 if ((val
& BGMAC_DMA_TX_STAT
) != BGMAC_DMA_TX_STAT_DISABLED
)
101 bgmac_err(bgmac
, "Reset of DMA TX ring 0x%X failed\n",
106 static void bgmac_dma_tx_enable(struct bgmac
*bgmac
,
107 struct bgmac_dma_ring
*ring
)
111 ctl
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
);
112 if (bgmac
->core
->id
.rev
>= 4) {
113 ctl
&= ~BGMAC_DMA_TX_BL_MASK
;
114 ctl
|= BGMAC_DMA_TX_BL_128
<< BGMAC_DMA_TX_BL_SHIFT
;
116 ctl
&= ~BGMAC_DMA_TX_MR_MASK
;
117 ctl
|= BGMAC_DMA_TX_MR_2
<< BGMAC_DMA_TX_MR_SHIFT
;
119 ctl
&= ~BGMAC_DMA_TX_PC_MASK
;
120 ctl
|= BGMAC_DMA_TX_PC_16
<< BGMAC_DMA_TX_PC_SHIFT
;
122 ctl
&= ~BGMAC_DMA_TX_PT_MASK
;
123 ctl
|= BGMAC_DMA_TX_PT_8
<< BGMAC_DMA_TX_PT_SHIFT
;
125 ctl
|= BGMAC_DMA_TX_ENABLE
;
126 ctl
|= BGMAC_DMA_TX_PARITY_DISABLE
;
127 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
, ctl
);
131 bgmac_dma_tx_add_buf(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
,
132 int i
, int len
, u32 ctl0
)
134 struct bgmac_slot_info
*slot
;
135 struct bgmac_dma_desc
*dma_desc
;
138 if (i
== BGMAC_TX_RING_SLOTS
- 1)
139 ctl0
|= BGMAC_DESC_CTL0_EOT
;
141 ctl1
= len
& BGMAC_DESC_CTL1_LEN
;
143 slot
= &ring
->slots
[i
];
144 dma_desc
= &ring
->cpu_base
[i
];
145 dma_desc
->addr_low
= cpu_to_le32(lower_32_bits(slot
->dma_addr
));
146 dma_desc
->addr_high
= cpu_to_le32(upper_32_bits(slot
->dma_addr
));
147 dma_desc
->ctl0
= cpu_to_le32(ctl0
);
148 dma_desc
->ctl1
= cpu_to_le32(ctl1
);
151 static netdev_tx_t
bgmac_dma_tx_add(struct bgmac
*bgmac
,
152 struct bgmac_dma_ring
*ring
,
155 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
156 struct net_device
*net_dev
= bgmac
->net_dev
;
157 int index
= ring
->end
% BGMAC_TX_RING_SLOTS
;
158 struct bgmac_slot_info
*slot
= &ring
->slots
[index
];
163 if (skb
->len
> BGMAC_DESC_CTL1_LEN
) {
164 bgmac_err(bgmac
, "Too long skb (%d)\n", skb
->len
);
168 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
169 skb_checksum_help(skb
);
171 nr_frags
= skb_shinfo(skb
)->nr_frags
;
173 /* ring->end - ring->start will return the number of valid slots,
174 * even when ring->end overflows
176 if (ring
->end
- ring
->start
+ nr_frags
+ 1 >= BGMAC_TX_RING_SLOTS
) {
177 bgmac_err(bgmac
, "TX ring is full, queue should be stopped!\n");
178 netif_stop_queue(net_dev
);
179 return NETDEV_TX_BUSY
;
182 slot
->dma_addr
= dma_map_single(dma_dev
, skb
->data
, skb_headlen(skb
),
184 if (unlikely(dma_mapping_error(dma_dev
, slot
->dma_addr
)))
187 flags
= BGMAC_DESC_CTL0_SOF
;
189 flags
|= BGMAC_DESC_CTL0_EOF
| BGMAC_DESC_CTL0_IOC
;
191 bgmac_dma_tx_add_buf(bgmac
, ring
, index
, skb_headlen(skb
), flags
);
194 for (i
= 0; i
< nr_frags
; i
++) {
195 struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[i
];
196 int len
= skb_frag_size(frag
);
198 index
= (index
+ 1) % BGMAC_TX_RING_SLOTS
;
199 slot
= &ring
->slots
[index
];
200 slot
->dma_addr
= skb_frag_dma_map(dma_dev
, frag
, 0,
202 if (unlikely(dma_mapping_error(dma_dev
, slot
->dma_addr
)))
205 if (i
== nr_frags
- 1)
206 flags
|= BGMAC_DESC_CTL0_EOF
| BGMAC_DESC_CTL0_IOC
;
208 bgmac_dma_tx_add_buf(bgmac
, ring
, index
, len
, flags
);
212 ring
->end
+= nr_frags
+ 1;
213 netdev_sent_queue(net_dev
, skb
->len
);
217 /* Increase ring->end to point empty slot. We tell hardware the first
218 * slot it should *not* read.
220 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_INDEX
,
222 (ring
->end
% BGMAC_TX_RING_SLOTS
) *
223 sizeof(struct bgmac_dma_desc
));
225 if (ring
->end
- ring
->start
>= BGMAC_TX_RING_SLOTS
- 8)
226 netif_stop_queue(net_dev
);
231 dma_unmap_single(dma_dev
, slot
->dma_addr
, skb_headlen(skb
),
235 int index
= (ring
->end
+ i
) % BGMAC_TX_RING_SLOTS
;
236 struct bgmac_slot_info
*slot
= &ring
->slots
[index
];
237 u32 ctl1
= le32_to_cpu(ring
->cpu_base
[index
].ctl1
);
238 int len
= ctl1
& BGMAC_DESC_CTL1_LEN
;
240 dma_unmap_page(dma_dev
, slot
->dma_addr
, len
, DMA_TO_DEVICE
);
244 bgmac_err(bgmac
, "Mapping error of skb on ring 0x%X\n",
252 /* Free transmitted packets */
253 static void bgmac_dma_tx_free(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
255 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
258 unsigned bytes_compl
= 0, pkts_compl
= 0;
260 /* The last slot that hardware didn't consume yet */
261 empty_slot
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
262 empty_slot
&= BGMAC_DMA_TX_STATDPTR
;
263 empty_slot
-= ring
->index_base
;
264 empty_slot
&= BGMAC_DMA_TX_STATDPTR
;
265 empty_slot
/= sizeof(struct bgmac_dma_desc
);
267 while (ring
->start
!= ring
->end
) {
268 int slot_idx
= ring
->start
% BGMAC_TX_RING_SLOTS
;
269 struct bgmac_slot_info
*slot
= &ring
->slots
[slot_idx
];
273 if (slot_idx
== empty_slot
)
276 ctl1
= le32_to_cpu(ring
->cpu_base
[slot_idx
].ctl1
);
277 len
= ctl1
& BGMAC_DESC_CTL1_LEN
;
278 if (ctl1
& BGMAC_DESC_CTL0_SOF
)
279 /* Unmap no longer used buffer */
280 dma_unmap_single(dma_dev
, slot
->dma_addr
, len
,
283 dma_unmap_page(dma_dev
, slot
->dma_addr
, len
,
287 bytes_compl
+= slot
->skb
->len
;
290 /* Free memory! :) */
291 dev_kfree_skb(slot
->skb
);
303 netdev_completed_queue(bgmac
->net_dev
, pkts_compl
, bytes_compl
);
305 if (netif_queue_stopped(bgmac
->net_dev
))
306 netif_wake_queue(bgmac
->net_dev
);
309 static void bgmac_dma_rx_reset(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
311 if (!ring
->mmio_base
)
314 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
, 0);
315 if (!bgmac_wait_value(bgmac
->core
,
316 ring
->mmio_base
+ BGMAC_DMA_RX_STATUS
,
317 BGMAC_DMA_RX_STAT
, BGMAC_DMA_RX_STAT_DISABLED
,
319 bgmac_err(bgmac
, "Reset of ring 0x%X RX failed\n",
323 static void bgmac_dma_rx_enable(struct bgmac
*bgmac
,
324 struct bgmac_dma_ring
*ring
)
328 ctl
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
);
329 if (bgmac
->core
->id
.rev
>= 4) {
330 ctl
&= ~BGMAC_DMA_RX_BL_MASK
;
331 ctl
|= BGMAC_DMA_RX_BL_128
<< BGMAC_DMA_RX_BL_SHIFT
;
333 ctl
&= ~BGMAC_DMA_RX_PC_MASK
;
334 ctl
|= BGMAC_DMA_RX_PC_8
<< BGMAC_DMA_RX_PC_SHIFT
;
336 ctl
&= ~BGMAC_DMA_RX_PT_MASK
;
337 ctl
|= BGMAC_DMA_RX_PT_1
<< BGMAC_DMA_RX_PT_SHIFT
;
339 ctl
&= BGMAC_DMA_RX_ADDREXT_MASK
;
340 ctl
|= BGMAC_DMA_RX_ENABLE
;
341 ctl
|= BGMAC_DMA_RX_PARITY_DISABLE
;
342 ctl
|= BGMAC_DMA_RX_OVERFLOW_CONT
;
343 ctl
|= BGMAC_RX_FRAME_OFFSET
<< BGMAC_DMA_RX_FRAME_OFFSET_SHIFT
;
344 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
, ctl
);
347 static int bgmac_dma_rx_skb_for_slot(struct bgmac
*bgmac
,
348 struct bgmac_slot_info
*slot
)
350 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
352 struct bgmac_rx_header
*rx
;
356 buf
= netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE
);
360 /* Poison - if everything goes fine, hardware will overwrite it */
361 rx
= buf
+ BGMAC_RX_BUF_OFFSET
;
362 rx
->len
= cpu_to_le16(0xdead);
363 rx
->flags
= cpu_to_le16(0xbeef);
365 /* Map skb for the DMA */
366 dma_addr
= dma_map_single(dma_dev
, buf
+ BGMAC_RX_BUF_OFFSET
,
367 BGMAC_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
368 if (dma_mapping_error(dma_dev
, dma_addr
)) {
369 bgmac_err(bgmac
, "DMA mapping error\n");
370 put_page(virt_to_head_page(buf
));
374 /* Update the slot */
376 slot
->dma_addr
= dma_addr
;
381 static void bgmac_dma_rx_update_index(struct bgmac
*bgmac
,
382 struct bgmac_dma_ring
*ring
)
386 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_INDEX
,
388 ring
->end
* sizeof(struct bgmac_dma_desc
));
391 static void bgmac_dma_rx_setup_desc(struct bgmac
*bgmac
,
392 struct bgmac_dma_ring
*ring
, int desc_idx
)
394 struct bgmac_dma_desc
*dma_desc
= ring
->cpu_base
+ desc_idx
;
395 u32 ctl0
= 0, ctl1
= 0;
397 if (desc_idx
== BGMAC_RX_RING_SLOTS
- 1)
398 ctl0
|= BGMAC_DESC_CTL0_EOT
;
399 ctl1
|= BGMAC_RX_BUF_SIZE
& BGMAC_DESC_CTL1_LEN
;
400 /* Is there any BGMAC device that requires extension? */
401 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
402 * B43_DMA64_DCTL1_ADDREXT_MASK;
405 dma_desc
->addr_low
= cpu_to_le32(lower_32_bits(ring
->slots
[desc_idx
].dma_addr
));
406 dma_desc
->addr_high
= cpu_to_le32(upper_32_bits(ring
->slots
[desc_idx
].dma_addr
));
407 dma_desc
->ctl0
= cpu_to_le32(ctl0
);
408 dma_desc
->ctl1
= cpu_to_le32(ctl1
);
410 ring
->end
= desc_idx
;
413 static void bgmac_dma_rx_poison_buf(struct device
*dma_dev
,
414 struct bgmac_slot_info
*slot
)
416 struct bgmac_rx_header
*rx
= slot
->buf
+ BGMAC_RX_BUF_OFFSET
;
418 dma_sync_single_for_cpu(dma_dev
, slot
->dma_addr
, BGMAC_RX_BUF_SIZE
,
420 rx
->len
= cpu_to_le16(0xdead);
421 rx
->flags
= cpu_to_le16(0xbeef);
422 dma_sync_single_for_device(dma_dev
, slot
->dma_addr
, BGMAC_RX_BUF_SIZE
,
426 static int bgmac_dma_rx_read(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
,
432 end_slot
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_STATUS
);
433 end_slot
&= BGMAC_DMA_RX_STATDPTR
;
434 end_slot
-= ring
->index_base
;
435 end_slot
&= BGMAC_DMA_RX_STATDPTR
;
436 end_slot
/= sizeof(struct bgmac_dma_desc
);
438 while (ring
->start
!= end_slot
) {
439 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
440 struct bgmac_slot_info
*slot
= &ring
->slots
[ring
->start
];
441 struct bgmac_rx_header
*rx
= slot
->buf
+ BGMAC_RX_BUF_OFFSET
;
443 void *buf
= slot
->buf
;
444 dma_addr_t dma_addr
= slot
->dma_addr
;
448 /* Prepare new skb as replacement */
449 if (bgmac_dma_rx_skb_for_slot(bgmac
, slot
)) {
450 bgmac_dma_rx_poison_buf(dma_dev
, slot
);
454 /* Unmap buffer to make it accessible to the CPU */
455 dma_unmap_single(dma_dev
, dma_addr
,
456 BGMAC_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
458 /* Get info from the header */
459 len
= le16_to_cpu(rx
->len
);
460 flags
= le16_to_cpu(rx
->flags
);
462 /* Check for poison and drop or pass the packet */
463 if (len
== 0xdead && flags
== 0xbeef) {
464 bgmac_err(bgmac
, "Found poisoned packet at slot %d, DMA issue!\n",
466 put_page(virt_to_head_page(buf
));
470 if (len
> BGMAC_RX_ALLOC_SIZE
) {
471 bgmac_err(bgmac
, "Found oversized packet at slot %d, DMA issue!\n",
473 put_page(virt_to_head_page(buf
));
480 skb
= build_skb(buf
, BGMAC_RX_ALLOC_SIZE
);
481 if (unlikely(!skb
)) {
482 bgmac_err(bgmac
, "build_skb failed\n");
483 put_page(virt_to_head_page(buf
));
486 skb_put(skb
, BGMAC_RX_FRAME_OFFSET
+
487 BGMAC_RX_BUF_OFFSET
+ len
);
488 skb_pull(skb
, BGMAC_RX_FRAME_OFFSET
+
489 BGMAC_RX_BUF_OFFSET
);
491 skb_checksum_none_assert(skb
);
492 skb
->protocol
= eth_type_trans(skb
, bgmac
->net_dev
);
493 napi_gro_receive(&bgmac
->napi
, skb
);
497 bgmac_dma_rx_setup_desc(bgmac
, ring
, ring
->start
);
499 if (++ring
->start
>= BGMAC_RX_RING_SLOTS
)
502 if (handled
>= weight
) /* Should never be greater */
506 bgmac_dma_rx_update_index(bgmac
, ring
);
511 /* Does ring support unaligned addressing? */
512 static bool bgmac_dma_unaligned(struct bgmac
*bgmac
,
513 struct bgmac_dma_ring
*ring
,
514 enum bgmac_dma_ring_type ring_type
)
517 case BGMAC_DMA_RING_TX
:
518 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
,
520 if (bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
))
523 case BGMAC_DMA_RING_RX
:
524 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
,
526 if (bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
))
533 static void bgmac_dma_tx_ring_free(struct bgmac
*bgmac
,
534 struct bgmac_dma_ring
*ring
)
536 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
537 struct bgmac_dma_desc
*dma_desc
= ring
->cpu_base
;
538 struct bgmac_slot_info
*slot
;
541 for (i
= 0; i
< BGMAC_TX_RING_SLOTS
; i
++) {
542 int len
= dma_desc
[i
].ctl1
& BGMAC_DESC_CTL1_LEN
;
544 slot
= &ring
->slots
[i
];
545 dev_kfree_skb(slot
->skb
);
551 dma_unmap_single(dma_dev
, slot
->dma_addr
,
554 dma_unmap_page(dma_dev
, slot
->dma_addr
,
559 static void bgmac_dma_rx_ring_free(struct bgmac
*bgmac
,
560 struct bgmac_dma_ring
*ring
)
562 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
563 struct bgmac_slot_info
*slot
;
566 for (i
= 0; i
< BGMAC_RX_RING_SLOTS
; i
++) {
567 slot
= &ring
->slots
[i
];
571 dma_unmap_single(dma_dev
, slot
->dma_addr
,
574 put_page(virt_to_head_page(slot
->buf
));
579 static void bgmac_dma_ring_desc_free(struct bgmac
*bgmac
,
580 struct bgmac_dma_ring
*ring
,
583 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
589 /* Free ring of descriptors */
590 size
= num_slots
* sizeof(struct bgmac_dma_desc
);
591 dma_free_coherent(dma_dev
, size
, ring
->cpu_base
,
595 static void bgmac_dma_cleanup(struct bgmac
*bgmac
)
599 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
600 bgmac_dma_tx_ring_free(bgmac
, &bgmac
->tx_ring
[i
]);
602 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
603 bgmac_dma_rx_ring_free(bgmac
, &bgmac
->rx_ring
[i
]);
606 static void bgmac_dma_free(struct bgmac
*bgmac
)
610 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
611 bgmac_dma_ring_desc_free(bgmac
, &bgmac
->tx_ring
[i
],
612 BGMAC_TX_RING_SLOTS
);
614 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
615 bgmac_dma_ring_desc_free(bgmac
, &bgmac
->rx_ring
[i
],
616 BGMAC_RX_RING_SLOTS
);
619 static int bgmac_dma_alloc(struct bgmac
*bgmac
)
621 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
622 struct bgmac_dma_ring
*ring
;
623 static const u16 ring_base
[] = { BGMAC_DMA_BASE0
, BGMAC_DMA_BASE1
,
624 BGMAC_DMA_BASE2
, BGMAC_DMA_BASE3
, };
625 int size
; /* ring size: different for Tx and Rx */
629 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS
> ARRAY_SIZE(ring_base
));
630 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS
> ARRAY_SIZE(ring_base
));
632 if (!(bcma_aread32(bgmac
->core
, BCMA_IOST
) & BCMA_IOST_DMA64
)) {
633 bgmac_err(bgmac
, "Core does not report 64-bit DMA\n");
637 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++) {
638 ring
= &bgmac
->tx_ring
[i
];
639 ring
->mmio_base
= ring_base
[i
];
641 /* Alloc ring of descriptors */
642 size
= BGMAC_TX_RING_SLOTS
* sizeof(struct bgmac_dma_desc
);
643 ring
->cpu_base
= dma_zalloc_coherent(dma_dev
, size
,
646 if (!ring
->cpu_base
) {
647 bgmac_err(bgmac
, "Allocation of TX ring 0x%X failed\n",
652 ring
->unaligned
= bgmac_dma_unaligned(bgmac
, ring
,
655 ring
->index_base
= lower_32_bits(ring
->dma_base
);
657 ring
->index_base
= 0;
659 /* No need to alloc TX slots yet */
662 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++) {
663 ring
= &bgmac
->rx_ring
[i
];
664 ring
->mmio_base
= ring_base
[i
];
666 /* Alloc ring of descriptors */
667 size
= BGMAC_RX_RING_SLOTS
* sizeof(struct bgmac_dma_desc
);
668 ring
->cpu_base
= dma_zalloc_coherent(dma_dev
, size
,
671 if (!ring
->cpu_base
) {
672 bgmac_err(bgmac
, "Allocation of RX ring 0x%X failed\n",
678 ring
->unaligned
= bgmac_dma_unaligned(bgmac
, ring
,
681 ring
->index_base
= lower_32_bits(ring
->dma_base
);
683 ring
->index_base
= 0;
689 bgmac_dma_free(bgmac
);
693 static int bgmac_dma_init(struct bgmac
*bgmac
)
695 struct bgmac_dma_ring
*ring
;
698 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++) {
699 ring
= &bgmac
->tx_ring
[i
];
701 if (!ring
->unaligned
)
702 bgmac_dma_tx_enable(bgmac
, ring
);
703 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
,
704 lower_32_bits(ring
->dma_base
));
705 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGHI
,
706 upper_32_bits(ring
->dma_base
));
708 bgmac_dma_tx_enable(bgmac
, ring
);
711 ring
->end
= 0; /* Points the slot that should *not* be read */
714 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++) {
717 ring
= &bgmac
->rx_ring
[i
];
719 if (!ring
->unaligned
)
720 bgmac_dma_rx_enable(bgmac
, ring
);
721 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
,
722 lower_32_bits(ring
->dma_base
));
723 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGHI
,
724 upper_32_bits(ring
->dma_base
));
726 bgmac_dma_rx_enable(bgmac
, ring
);
730 for (j
= 0; j
< BGMAC_RX_RING_SLOTS
; j
++) {
731 err
= bgmac_dma_rx_skb_for_slot(bgmac
, &ring
->slots
[j
]);
735 bgmac_dma_rx_setup_desc(bgmac
, ring
, j
);
738 bgmac_dma_rx_update_index(bgmac
, ring
);
744 bgmac_dma_cleanup(bgmac
);
748 /**************************************************
750 **************************************************/
752 static u16
bgmac_phy_read(struct bgmac
*bgmac
, u8 phyaddr
, u8 reg
)
754 struct bcma_device
*core
;
759 BUILD_BUG_ON(BGMAC_PA_DATA_MASK
!= BCMA_GMAC_CMN_PA_DATA_MASK
);
760 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK
!= BCMA_GMAC_CMN_PA_ADDR_MASK
);
761 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT
!= BCMA_GMAC_CMN_PA_ADDR_SHIFT
);
762 BUILD_BUG_ON(BGMAC_PA_REG_MASK
!= BCMA_GMAC_CMN_PA_REG_MASK
);
763 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT
!= BCMA_GMAC_CMN_PA_REG_SHIFT
);
764 BUILD_BUG_ON(BGMAC_PA_WRITE
!= BCMA_GMAC_CMN_PA_WRITE
);
765 BUILD_BUG_ON(BGMAC_PA_START
!= BCMA_GMAC_CMN_PA_START
);
766 BUILD_BUG_ON(BGMAC_PC_EPA_MASK
!= BCMA_GMAC_CMN_PC_EPA_MASK
);
767 BUILD_BUG_ON(BGMAC_PC_MCT_MASK
!= BCMA_GMAC_CMN_PC_MCT_MASK
);
768 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT
!= BCMA_GMAC_CMN_PC_MCT_SHIFT
);
769 BUILD_BUG_ON(BGMAC_PC_MTE
!= BCMA_GMAC_CMN_PC_MTE
);
771 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
) {
772 core
= bgmac
->core
->bus
->drv_gmac_cmn
.core
;
773 phy_access_addr
= BCMA_GMAC_CMN_PHY_ACCESS
;
774 phy_ctl_addr
= BCMA_GMAC_CMN_PHY_CTL
;
777 phy_access_addr
= BGMAC_PHY_ACCESS
;
778 phy_ctl_addr
= BGMAC_PHY_CNTL
;
781 tmp
= bcma_read32(core
, phy_ctl_addr
);
782 tmp
&= ~BGMAC_PC_EPA_MASK
;
784 bcma_write32(core
, phy_ctl_addr
, tmp
);
786 tmp
= BGMAC_PA_START
;
787 tmp
|= phyaddr
<< BGMAC_PA_ADDR_SHIFT
;
788 tmp
|= reg
<< BGMAC_PA_REG_SHIFT
;
789 bcma_write32(core
, phy_access_addr
, tmp
);
791 if (!bgmac_wait_value(core
, phy_access_addr
, BGMAC_PA_START
, 0, 1000)) {
792 bgmac_err(bgmac
, "Reading PHY %d register 0x%X failed\n",
797 return bcma_read32(core
, phy_access_addr
) & BGMAC_PA_DATA_MASK
;
800 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
801 static int bgmac_phy_write(struct bgmac
*bgmac
, u8 phyaddr
, u8 reg
, u16 value
)
803 struct bcma_device
*core
;
808 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
) {
809 core
= bgmac
->core
->bus
->drv_gmac_cmn
.core
;
810 phy_access_addr
= BCMA_GMAC_CMN_PHY_ACCESS
;
811 phy_ctl_addr
= BCMA_GMAC_CMN_PHY_CTL
;
814 phy_access_addr
= BGMAC_PHY_ACCESS
;
815 phy_ctl_addr
= BGMAC_PHY_CNTL
;
818 tmp
= bcma_read32(core
, phy_ctl_addr
);
819 tmp
&= ~BGMAC_PC_EPA_MASK
;
821 bcma_write32(core
, phy_ctl_addr
, tmp
);
823 bgmac_write(bgmac
, BGMAC_INT_STATUS
, BGMAC_IS_MDIO
);
824 if (bgmac_read(bgmac
, BGMAC_INT_STATUS
) & BGMAC_IS_MDIO
)
825 bgmac_warn(bgmac
, "Error setting MDIO int\n");
827 tmp
= BGMAC_PA_START
;
828 tmp
|= BGMAC_PA_WRITE
;
829 tmp
|= phyaddr
<< BGMAC_PA_ADDR_SHIFT
;
830 tmp
|= reg
<< BGMAC_PA_REG_SHIFT
;
832 bcma_write32(core
, phy_access_addr
, tmp
);
834 if (!bgmac_wait_value(core
, phy_access_addr
, BGMAC_PA_START
, 0, 1000)) {
835 bgmac_err(bgmac
, "Writing to PHY %d register 0x%X failed\n",
843 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
844 static void bgmac_phy_init(struct bgmac
*bgmac
)
846 struct bcma_chipinfo
*ci
= &bgmac
->core
->bus
->chipinfo
;
847 struct bcma_drv_cc
*cc
= &bgmac
->core
->bus
->drv_cc
;
850 if (ci
->id
== BCMA_CHIP_ID_BCM5356
) {
851 for (i
= 0; i
< 5; i
++) {
852 bgmac_phy_write(bgmac
, i
, 0x1f, 0x008b);
853 bgmac_phy_write(bgmac
, i
, 0x15, 0x0100);
854 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
855 bgmac_phy_write(bgmac
, i
, 0x12, 0x2aaa);
856 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
859 if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
!= 10) ||
860 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
!= 10) ||
861 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
!= 9)) {
862 bcma_chipco_chipctl_maskset(cc
, 2, ~0xc0000000, 0);
863 bcma_chipco_chipctl_maskset(cc
, 4, ~0x80000000, 0);
864 for (i
= 0; i
< 5; i
++) {
865 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
866 bgmac_phy_write(bgmac
, i
, 0x16, 0x5284);
867 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
868 bgmac_phy_write(bgmac
, i
, 0x17, 0x0010);
869 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
870 bgmac_phy_write(bgmac
, i
, 0x16, 0x5296);
871 bgmac_phy_write(bgmac
, i
, 0x17, 0x1073);
872 bgmac_phy_write(bgmac
, i
, 0x17, 0x9073);
873 bgmac_phy_write(bgmac
, i
, 0x16, 0x52b6);
874 bgmac_phy_write(bgmac
, i
, 0x17, 0x9273);
875 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
880 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
881 static void bgmac_phy_reset(struct bgmac
*bgmac
)
883 if (bgmac
->phyaddr
== BGMAC_PHY_NOREGS
)
886 bgmac_phy_write(bgmac
, bgmac
->phyaddr
, MII_BMCR
, BMCR_RESET
);
888 if (bgmac_phy_read(bgmac
, bgmac
->phyaddr
, MII_BMCR
) & BMCR_RESET
)
889 bgmac_err(bgmac
, "PHY reset failed\n");
890 bgmac_phy_init(bgmac
);
893 /**************************************************
895 **************************************************/
897 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
898 * nothing to change? Try if after stabilizng driver.
900 static void bgmac_cmdcfg_maskset(struct bgmac
*bgmac
, u32 mask
, u32 set
,
903 u32 cmdcfg
= bgmac_read(bgmac
, BGMAC_CMDCFG
);
904 u32 new_val
= (cmdcfg
& mask
) | set
;
906 bgmac_set(bgmac
, BGMAC_CMDCFG
, BGMAC_CMDCFG_SR(bgmac
->core
->id
.rev
));
909 if (new_val
!= cmdcfg
|| force
)
910 bgmac_write(bgmac
, BGMAC_CMDCFG
, new_val
);
912 bgmac_mask(bgmac
, BGMAC_CMDCFG
, ~BGMAC_CMDCFG_SR(bgmac
->core
->id
.rev
));
916 static void bgmac_write_mac_address(struct bgmac
*bgmac
, u8
*addr
)
920 tmp
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
921 bgmac_write(bgmac
, BGMAC_MACADDR_HIGH
, tmp
);
922 tmp
= (addr
[4] << 8) | addr
[5];
923 bgmac_write(bgmac
, BGMAC_MACADDR_LOW
, tmp
);
926 static void bgmac_set_rx_mode(struct net_device
*net_dev
)
928 struct bgmac
*bgmac
= netdev_priv(net_dev
);
930 if (net_dev
->flags
& IFF_PROMISC
)
931 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_PROM
, true);
933 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_PROM
, 0, true);
936 #if 0 /* We don't use that regs yet */
937 static void bgmac_chip_stats_update(struct bgmac
*bgmac
)
941 if (bgmac
->core
->id
.id
!= BCMA_CORE_4706_MAC_GBIT
) {
942 for (i
= 0; i
< BGMAC_NUM_MIB_TX_REGS
; i
++)
943 bgmac
->mib_tx_regs
[i
] =
945 BGMAC_TX_GOOD_OCTETS
+ (i
* 4));
946 for (i
= 0; i
< BGMAC_NUM_MIB_RX_REGS
; i
++)
947 bgmac
->mib_rx_regs
[i
] =
949 BGMAC_RX_GOOD_OCTETS
+ (i
* 4));
952 /* TODO: what else? how to handle BCM4706? Specs are needed */
956 static void bgmac_clear_mib(struct bgmac
*bgmac
)
960 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
)
963 bgmac_set(bgmac
, BGMAC_DEV_CTL
, BGMAC_DC_MROR
);
964 for (i
= 0; i
< BGMAC_NUM_MIB_TX_REGS
; i
++)
965 bgmac_read(bgmac
, BGMAC_TX_GOOD_OCTETS
+ (i
* 4));
966 for (i
= 0; i
< BGMAC_NUM_MIB_RX_REGS
; i
++)
967 bgmac_read(bgmac
, BGMAC_RX_GOOD_OCTETS
+ (i
* 4));
970 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
971 static void bgmac_mac_speed(struct bgmac
*bgmac
)
973 u32 mask
= ~(BGMAC_CMDCFG_ES_MASK
| BGMAC_CMDCFG_HD
);
976 switch (bgmac
->mac_speed
) {
978 set
|= BGMAC_CMDCFG_ES_10
;
981 set
|= BGMAC_CMDCFG_ES_100
;
984 set
|= BGMAC_CMDCFG_ES_1000
;
987 set
|= BGMAC_CMDCFG_ES_2500
;
990 bgmac_err(bgmac
, "Unsupported speed: %d\n", bgmac
->mac_speed
);
993 if (bgmac
->mac_duplex
== DUPLEX_HALF
)
994 set
|= BGMAC_CMDCFG_HD
;
996 bgmac_cmdcfg_maskset(bgmac
, mask
, set
, true);
999 static void bgmac_miiconfig(struct bgmac
*bgmac
)
1001 struct bcma_device
*core
= bgmac
->core
;
1004 if (bgmac_is_bcm4707_family(bgmac
)) {
1005 bcma_awrite32(core
, BCMA_IOCTL
,
1006 bcma_aread32(core
, BCMA_IOCTL
) | 0x40 |
1007 BGMAC_BCMA_IOCTL_SW_CLKEN
);
1008 bgmac
->mac_speed
= SPEED_2500
;
1009 bgmac
->mac_duplex
= DUPLEX_FULL
;
1010 bgmac_mac_speed(bgmac
);
1012 imode
= (bgmac_read(bgmac
, BGMAC_DEV_STATUS
) &
1013 BGMAC_DS_MM_MASK
) >> BGMAC_DS_MM_SHIFT
;
1014 if (imode
== 0 || imode
== 1) {
1015 bgmac
->mac_speed
= SPEED_100
;
1016 bgmac
->mac_duplex
= DUPLEX_FULL
;
1017 bgmac_mac_speed(bgmac
);
1022 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
1023 static void bgmac_chip_reset(struct bgmac
*bgmac
)
1025 struct bcma_device
*core
= bgmac
->core
;
1026 struct bcma_bus
*bus
= core
->bus
;
1027 struct bcma_chipinfo
*ci
= &bus
->chipinfo
;
1032 if (bcma_core_is_enabled(core
)) {
1033 if (!bgmac
->stats_grabbed
) {
1034 /* bgmac_chip_stats_update(bgmac); */
1035 bgmac
->stats_grabbed
= true;
1038 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
1039 bgmac_dma_tx_reset(bgmac
, &bgmac
->tx_ring
[i
]);
1041 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_ML
, false);
1044 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
1045 bgmac_dma_rx_reset(bgmac
, &bgmac
->rx_ring
[i
]);
1047 /* TODO: Clear software multicast filter list */
1050 iost
= bcma_aread32(core
, BCMA_IOST
);
1051 if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== BCMA_PKG_ID_BCM47186
) ||
1052 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
== 10) ||
1053 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
== BCMA_PKG_ID_BCM47188
))
1054 iost
&= ~BGMAC_BCMA_IOST_ATTACHED
;
1056 /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
1057 if (ci
->id
!= BCMA_CHIP_ID_BCM4707
&&
1058 ci
->id
!= BCMA_CHIP_ID_BCM47094
) {
1060 if (iost
& BGMAC_BCMA_IOST_ATTACHED
) {
1061 flags
= BGMAC_BCMA_IOCTL_SW_CLKEN
;
1062 if (!bgmac
->has_robosw
)
1063 flags
|= BGMAC_BCMA_IOCTL_SW_RESET
;
1065 bcma_core_enable(core
, flags
);
1068 /* Request Misc PLL for corerev > 2 */
1069 if (core
->id
.rev
> 2 && !bgmac_is_bcm4707_family(bgmac
)) {
1070 bgmac_set(bgmac
, BCMA_CLKCTLST
,
1071 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ
);
1072 bgmac_wait_value(bgmac
->core
, BCMA_CLKCTLST
,
1073 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST
,
1074 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST
,
1078 if (ci
->id
== BCMA_CHIP_ID_BCM5357
||
1079 ci
->id
== BCMA_CHIP_ID_BCM4749
||
1080 ci
->id
== BCMA_CHIP_ID_BCM53572
) {
1081 struct bcma_drv_cc
*cc
= &bgmac
->core
->bus
->drv_cc
;
1083 u8 sw_type
= BGMAC_CHIPCTL_1_SW_TYPE_EPHY
|
1084 BGMAC_CHIPCTL_1_IF_TYPE_MII
;
1087 if (bcm47xx_nvram_getenv("et_swtype", buf
, sizeof(buf
)) > 0) {
1088 if (kstrtou8(buf
, 0, &et_swtype
))
1089 bgmac_err(bgmac
, "Failed to parse et_swtype (%s)\n",
1093 sw_type
= et_swtype
;
1094 } else if (ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== BCMA_PKG_ID_BCM5358
) {
1095 sw_type
= BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII
;
1096 } else if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== BCMA_PKG_ID_BCM47186
) ||
1097 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
== 10) ||
1098 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
== BCMA_PKG_ID_BCM47188
)) {
1099 sw_type
= BGMAC_CHIPCTL_1_IF_TYPE_RGMII
|
1100 BGMAC_CHIPCTL_1_SW_TYPE_RGMII
;
1102 bcma_chipco_chipctl_maskset(cc
, 1,
1103 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK
|
1104 BGMAC_CHIPCTL_1_SW_TYPE_MASK
),
1108 if (iost
& BGMAC_BCMA_IOST_ATTACHED
&& !bgmac
->has_robosw
)
1109 bcma_awrite32(core
, BCMA_IOCTL
,
1110 bcma_aread32(core
, BCMA_IOCTL
) &
1111 ~BGMAC_BCMA_IOCTL_SW_RESET
);
1113 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1114 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1115 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1116 * be keps until taking MAC out of the reset.
1118 bgmac_cmdcfg_maskset(bgmac
,
1130 BGMAC_CMDCFG_PAD_EN
|
1135 BGMAC_CMDCFG_SR(core
->id
.rev
),
1137 bgmac
->mac_speed
= SPEED_UNKNOWN
;
1138 bgmac
->mac_duplex
= DUPLEX_UNKNOWN
;
1140 bgmac_clear_mib(bgmac
);
1141 if (core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
)
1142 bcma_maskset32(bgmac
->cmn
, BCMA_GMAC_CMN_PHY_CTL
, ~0,
1143 BCMA_GMAC_CMN_PC_MTE
);
1145 bgmac_set(bgmac
, BGMAC_PHY_CNTL
, BGMAC_PC_MTE
);
1146 bgmac_miiconfig(bgmac
);
1147 bgmac_phy_init(bgmac
);
1149 netdev_reset_queue(bgmac
->net_dev
);
1152 static void bgmac_chip_intrs_on(struct bgmac
*bgmac
)
1154 bgmac_write(bgmac
, BGMAC_INT_MASK
, bgmac
->int_mask
);
1157 static void bgmac_chip_intrs_off(struct bgmac
*bgmac
)
1159 bgmac_write(bgmac
, BGMAC_INT_MASK
, 0);
1160 bgmac_read(bgmac
, BGMAC_INT_MASK
);
1163 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1164 static void bgmac_enable(struct bgmac
*bgmac
)
1166 struct bcma_chipinfo
*ci
= &bgmac
->core
->bus
->chipinfo
;
1174 cmdcfg
= bgmac_read(bgmac
, BGMAC_CMDCFG
);
1175 bgmac_cmdcfg_maskset(bgmac
, ~(BGMAC_CMDCFG_TE
| BGMAC_CMDCFG_RE
),
1176 BGMAC_CMDCFG_SR(bgmac
->core
->id
.rev
), true);
1178 cmdcfg
|= BGMAC_CMDCFG_TE
| BGMAC_CMDCFG_RE
;
1179 bgmac_write(bgmac
, BGMAC_CMDCFG
, cmdcfg
);
1181 mode
= (bgmac_read(bgmac
, BGMAC_DEV_STATUS
) & BGMAC_DS_MM_MASK
) >>
1183 if (ci
->id
!= BCMA_CHIP_ID_BCM47162
|| mode
!= 0)
1184 bgmac_set(bgmac
, BCMA_CLKCTLST
, BCMA_CLKCTLST_FORCEHT
);
1185 if (ci
->id
== BCMA_CHIP_ID_BCM47162
&& mode
== 2)
1186 bcma_chipco_chipctl_maskset(&bgmac
->core
->bus
->drv_cc
, 1, ~0,
1187 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS
);
1190 case BCMA_CHIP_ID_BCM5357
:
1191 case BCMA_CHIP_ID_BCM4749
:
1192 case BCMA_CHIP_ID_BCM53572
:
1193 case BCMA_CHIP_ID_BCM4716
:
1194 case BCMA_CHIP_ID_BCM47162
:
1195 fl_ctl
= 0x03cb04cb;
1196 if (ci
->id
== BCMA_CHIP_ID_BCM5357
||
1197 ci
->id
== BCMA_CHIP_ID_BCM4749
||
1198 ci
->id
== BCMA_CHIP_ID_BCM53572
)
1200 bgmac_write(bgmac
, BGMAC_FLOW_CTL_THRESH
, fl_ctl
);
1201 bgmac_write(bgmac
, BGMAC_PAUSE_CTL
, 0x27fff);
1205 if (!bgmac_is_bcm4707_family(bgmac
)) {
1206 rxq_ctl
= bgmac_read(bgmac
, BGMAC_RXQ_CTL
);
1207 rxq_ctl
&= ~BGMAC_RXQ_CTL_MDP_MASK
;
1208 bp_clk
= bcma_pmu_get_bus_clock(&bgmac
->core
->bus
->drv_cc
) /
1210 mdp
= (bp_clk
* 128 / 1000) - 3;
1211 rxq_ctl
|= (mdp
<< BGMAC_RXQ_CTL_MDP_SHIFT
);
1212 bgmac_write(bgmac
, BGMAC_RXQ_CTL
, rxq_ctl
);
1216 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1217 static void bgmac_chip_init(struct bgmac
*bgmac
)
1219 /* 1 interrupt per received frame */
1220 bgmac_write(bgmac
, BGMAC_INT_RECV_LAZY
, 1 << BGMAC_IRL_FC_SHIFT
);
1222 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1223 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_RPI
, 0, true);
1225 bgmac_set_rx_mode(bgmac
->net_dev
);
1227 bgmac_write_mac_address(bgmac
, bgmac
->net_dev
->dev_addr
);
1229 if (bgmac
->loopback
)
1230 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_ML
, false);
1232 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_ML
, 0, false);
1234 bgmac_write(bgmac
, BGMAC_RXMAX_LENGTH
, 32 + ETHER_MAX_LEN
);
1236 bgmac_chip_intrs_on(bgmac
);
1238 bgmac_enable(bgmac
);
1241 static irqreturn_t
bgmac_interrupt(int irq
, void *dev_id
)
1243 struct bgmac
*bgmac
= netdev_priv(dev_id
);
1245 u32 int_status
= bgmac_read(bgmac
, BGMAC_INT_STATUS
);
1246 int_status
&= bgmac
->int_mask
;
1251 int_status
&= ~(BGMAC_IS_TX0
| BGMAC_IS_RX
);
1253 bgmac_err(bgmac
, "Unknown IRQs: 0x%08X\n", int_status
);
1255 /* Disable new interrupts until handling existing ones */
1256 bgmac_chip_intrs_off(bgmac
);
1258 napi_schedule(&bgmac
->napi
);
1263 static int bgmac_poll(struct napi_struct
*napi
, int weight
)
1265 struct bgmac
*bgmac
= container_of(napi
, struct bgmac
, napi
);
1269 bgmac_write(bgmac
, BGMAC_INT_STATUS
, ~0);
1271 bgmac_dma_tx_free(bgmac
, &bgmac
->tx_ring
[0]);
1272 handled
+= bgmac_dma_rx_read(bgmac
, &bgmac
->rx_ring
[0], weight
);
1274 /* Poll again if more events arrived in the meantime */
1275 if (bgmac_read(bgmac
, BGMAC_INT_STATUS
) & (BGMAC_IS_TX0
| BGMAC_IS_RX
))
1278 if (handled
< weight
) {
1279 napi_complete(napi
);
1280 bgmac_chip_intrs_on(bgmac
);
1286 /**************************************************
1288 **************************************************/
1290 static int bgmac_open(struct net_device
*net_dev
)
1292 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1295 bgmac_chip_reset(bgmac
);
1297 err
= bgmac_dma_init(bgmac
);
1301 /* Specs say about reclaiming rings here, but we do that in DMA init */
1302 bgmac_chip_init(bgmac
);
1304 err
= request_irq(bgmac
->core
->irq
, bgmac_interrupt
, IRQF_SHARED
,
1305 KBUILD_MODNAME
, net_dev
);
1307 bgmac_err(bgmac
, "IRQ request error: %d!\n", err
);
1308 bgmac_dma_cleanup(bgmac
);
1311 napi_enable(&bgmac
->napi
);
1313 phy_start(bgmac
->phy_dev
);
1315 netif_carrier_on(net_dev
);
1319 static int bgmac_stop(struct net_device
*net_dev
)
1321 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1323 netif_carrier_off(net_dev
);
1325 phy_stop(bgmac
->phy_dev
);
1327 napi_disable(&bgmac
->napi
);
1328 bgmac_chip_intrs_off(bgmac
);
1329 free_irq(bgmac
->core
->irq
, net_dev
);
1331 bgmac_chip_reset(bgmac
);
1332 bgmac_dma_cleanup(bgmac
);
1337 static netdev_tx_t
bgmac_start_xmit(struct sk_buff
*skb
,
1338 struct net_device
*net_dev
)
1340 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1341 struct bgmac_dma_ring
*ring
;
1343 /* No QOS support yet */
1344 ring
= &bgmac
->tx_ring
[0];
1345 return bgmac_dma_tx_add(bgmac
, ring
, skb
);
1348 static int bgmac_set_mac_address(struct net_device
*net_dev
, void *addr
)
1350 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1353 ret
= eth_prepare_mac_addr_change(net_dev
, addr
);
1356 bgmac_write_mac_address(bgmac
, (u8
*)addr
);
1357 eth_commit_mac_addr_change(net_dev
, addr
);
1361 static int bgmac_ioctl(struct net_device
*net_dev
, struct ifreq
*ifr
, int cmd
)
1363 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1365 if (!netif_running(net_dev
))
1368 return phy_mii_ioctl(bgmac
->phy_dev
, ifr
, cmd
);
1371 static const struct net_device_ops bgmac_netdev_ops
= {
1372 .ndo_open
= bgmac_open
,
1373 .ndo_stop
= bgmac_stop
,
1374 .ndo_start_xmit
= bgmac_start_xmit
,
1375 .ndo_set_rx_mode
= bgmac_set_rx_mode
,
1376 .ndo_set_mac_address
= bgmac_set_mac_address
,
1377 .ndo_validate_addr
= eth_validate_addr
,
1378 .ndo_do_ioctl
= bgmac_ioctl
,
1381 /**************************************************
1383 **************************************************/
1385 static int bgmac_get_settings(struct net_device
*net_dev
,
1386 struct ethtool_cmd
*cmd
)
1388 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1390 return phy_ethtool_gset(bgmac
->phy_dev
, cmd
);
1393 static int bgmac_set_settings(struct net_device
*net_dev
,
1394 struct ethtool_cmd
*cmd
)
1396 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1398 return phy_ethtool_sset(bgmac
->phy_dev
, cmd
);
1401 static void bgmac_get_drvinfo(struct net_device
*net_dev
,
1402 struct ethtool_drvinfo
*info
)
1404 strlcpy(info
->driver
, KBUILD_MODNAME
, sizeof(info
->driver
));
1405 strlcpy(info
->bus_info
, "BCMA", sizeof(info
->bus_info
));
1408 static const struct ethtool_ops bgmac_ethtool_ops
= {
1409 .get_settings
= bgmac_get_settings
,
1410 .set_settings
= bgmac_set_settings
,
1411 .get_drvinfo
= bgmac_get_drvinfo
,
1414 /**************************************************
1416 **************************************************/
1418 static int bgmac_mii_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1420 return bgmac_phy_read(bus
->priv
, mii_id
, regnum
);
1423 static int bgmac_mii_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
1426 return bgmac_phy_write(bus
->priv
, mii_id
, regnum
, value
);
1429 static void bgmac_adjust_link(struct net_device
*net_dev
)
1431 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1432 struct phy_device
*phy_dev
= bgmac
->phy_dev
;
1433 bool update
= false;
1435 if (phy_dev
->link
) {
1436 if (phy_dev
->speed
!= bgmac
->mac_speed
) {
1437 bgmac
->mac_speed
= phy_dev
->speed
;
1441 if (phy_dev
->duplex
!= bgmac
->mac_duplex
) {
1442 bgmac
->mac_duplex
= phy_dev
->duplex
;
1448 bgmac_mac_speed(bgmac
);
1449 phy_print_status(phy_dev
);
1453 static int bgmac_fixed_phy_register(struct bgmac
*bgmac
)
1455 struct fixed_phy_status fphy_status
= {
1457 .speed
= SPEED_1000
,
1458 .duplex
= DUPLEX_FULL
,
1460 struct phy_device
*phy_dev
;
1463 phy_dev
= fixed_phy_register(PHY_POLL
, &fphy_status
, -1, NULL
);
1464 if (!phy_dev
|| IS_ERR(phy_dev
)) {
1465 bgmac_err(bgmac
, "Failed to register fixed PHY device\n");
1469 err
= phy_connect_direct(bgmac
->net_dev
, phy_dev
, bgmac_adjust_link
,
1470 PHY_INTERFACE_MODE_MII
);
1472 bgmac_err(bgmac
, "Connecting PHY failed\n");
1476 bgmac
->phy_dev
= phy_dev
;
1481 static int bgmac_mii_register(struct bgmac
*bgmac
)
1483 struct mii_bus
*mii_bus
;
1484 struct phy_device
*phy_dev
;
1485 char bus_id
[MII_BUS_ID_SIZE
+ 3];
1488 if (bgmac_is_bcm4707_family(bgmac
))
1489 return bgmac_fixed_phy_register(bgmac
);
1491 mii_bus
= mdiobus_alloc();
1495 mii_bus
->name
= "bgmac mii bus";
1496 sprintf(mii_bus
->id
, "%s-%d-%d", "bgmac", bgmac
->core
->bus
->num
,
1497 bgmac
->core
->core_unit
);
1498 mii_bus
->priv
= bgmac
;
1499 mii_bus
->read
= bgmac_mii_read
;
1500 mii_bus
->write
= bgmac_mii_write
;
1501 mii_bus
->parent
= &bgmac
->core
->dev
;
1502 mii_bus
->phy_mask
= ~(1 << bgmac
->phyaddr
);
1504 err
= mdiobus_register(mii_bus
);
1506 bgmac_err(bgmac
, "Registration of mii bus failed\n");
1510 bgmac
->mii_bus
= mii_bus
;
1512 /* Connect to the PHY */
1513 snprintf(bus_id
, sizeof(bus_id
), PHY_ID_FMT
, mii_bus
->id
,
1515 phy_dev
= phy_connect(bgmac
->net_dev
, bus_id
, &bgmac_adjust_link
,
1516 PHY_INTERFACE_MODE_MII
);
1517 if (IS_ERR(phy_dev
)) {
1518 bgmac_err(bgmac
, "PHY connecton failed\n");
1519 err
= PTR_ERR(phy_dev
);
1520 goto err_unregister_bus
;
1522 bgmac
->phy_dev
= phy_dev
;
1527 mdiobus_unregister(mii_bus
);
1529 mdiobus_free(mii_bus
);
1533 static void bgmac_mii_unregister(struct bgmac
*bgmac
)
1535 struct mii_bus
*mii_bus
= bgmac
->mii_bus
;
1537 mdiobus_unregister(mii_bus
);
1538 mdiobus_free(mii_bus
);
1541 /**************************************************
1543 **************************************************/
1545 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1546 static int bgmac_probe(struct bcma_device
*core
)
1548 struct net_device
*net_dev
;
1549 struct bgmac
*bgmac
;
1550 struct ssb_sprom
*sprom
= &core
->bus
->sprom
;
1554 switch (core
->core_unit
) {
1556 mac
= sprom
->et0mac
;
1559 mac
= sprom
->et1mac
;
1562 mac
= sprom
->et2mac
;
1565 pr_err("Unsupported core_unit %d\n", core
->core_unit
);
1569 if (!is_valid_ether_addr(mac
)) {
1570 dev_err(&core
->dev
, "Invalid MAC addr: %pM\n", mac
);
1571 eth_random_addr(mac
);
1572 dev_warn(&core
->dev
, "Using random MAC: %pM\n", mac
);
1575 /* This (reset &) enable is not preset in specs or reference driver but
1576 * Broadcom does it in arch PCI code when enabling fake PCI device.
1578 bcma_core_enable(core
, 0);
1580 /* Allocation and references */
1581 net_dev
= alloc_etherdev(sizeof(*bgmac
));
1584 net_dev
->netdev_ops
= &bgmac_netdev_ops
;
1585 net_dev
->irq
= core
->irq
;
1586 net_dev
->ethtool_ops
= &bgmac_ethtool_ops
;
1587 bgmac
= netdev_priv(net_dev
);
1588 bgmac
->net_dev
= net_dev
;
1590 bcma_set_drvdata(core
, bgmac
);
1593 memcpy(bgmac
->net_dev
->dev_addr
, mac
, ETH_ALEN
);
1595 /* On BCM4706 we need common core to access PHY */
1596 if (core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
&&
1597 !core
->bus
->drv_gmac_cmn
.core
) {
1598 bgmac_err(bgmac
, "GMAC CMN core not found (required for BCM4706)\n");
1600 goto err_netdev_free
;
1602 bgmac
->cmn
= core
->bus
->drv_gmac_cmn
.core
;
1604 switch (core
->core_unit
) {
1606 bgmac
->phyaddr
= sprom
->et0phyaddr
;
1609 bgmac
->phyaddr
= sprom
->et1phyaddr
;
1612 bgmac
->phyaddr
= sprom
->et2phyaddr
;
1615 bgmac
->phyaddr
&= BGMAC_PHY_MASK
;
1616 if (bgmac
->phyaddr
== BGMAC_PHY_MASK
) {
1617 bgmac_err(bgmac
, "No PHY found\n");
1619 goto err_netdev_free
;
1621 bgmac_info(bgmac
, "Found PHY addr: %d%s\n", bgmac
->phyaddr
,
1622 bgmac
->phyaddr
== BGMAC_PHY_NOREGS
? " (NOREGS)" : "");
1624 if (core
->bus
->hosttype
== BCMA_HOSTTYPE_PCI
) {
1625 bgmac_err(bgmac
, "PCI setup not implemented\n");
1627 goto err_netdev_free
;
1630 bgmac_chip_reset(bgmac
);
1632 /* For Northstar, we have to take all GMAC core out of reset */
1633 if (bgmac_is_bcm4707_family(bgmac
)) {
1634 struct bcma_device
*ns_core
;
1637 /* Northstar has 4 GMAC cores */
1638 for (ns_gmac
= 0; ns_gmac
< 4; ns_gmac
++) {
1639 /* As Northstar requirement, we have to reset all GMACs
1640 * before accessing one. bgmac_chip_reset() call
1641 * bcma_core_enable() for this core. Then the other
1642 * three GMACs didn't reset. We do it here.
1644 ns_core
= bcma_find_core_unit(core
->bus
,
1647 if (ns_core
&& !bcma_core_is_enabled(ns_core
))
1648 bcma_core_enable(ns_core
, 0);
1652 err
= bgmac_dma_alloc(bgmac
);
1654 bgmac_err(bgmac
, "Unable to alloc memory for DMA\n");
1655 goto err_netdev_free
;
1658 bgmac
->int_mask
= BGMAC_IS_ERRMASK
| BGMAC_IS_RX
| BGMAC_IS_TX_MASK
;
1659 if (bcm47xx_nvram_getenv("et0_no_txint", NULL
, 0) == 0)
1660 bgmac
->int_mask
&= ~BGMAC_IS_TX_MASK
;
1662 /* TODO: reset the external phy. Specs are needed */
1663 bgmac_phy_reset(bgmac
);
1665 bgmac
->has_robosw
= !!(core
->bus
->sprom
.boardflags_lo
&
1666 BGMAC_BFL_ENETROBO
);
1667 if (bgmac
->has_robosw
)
1668 bgmac_warn(bgmac
, "Support for Roboswitch not implemented\n");
1670 if (core
->bus
->sprom
.boardflags_lo
& BGMAC_BFL_ENETADM
)
1671 bgmac_warn(bgmac
, "Support for ADMtek ethernet switch not implemented\n");
1673 netif_napi_add(net_dev
, &bgmac
->napi
, bgmac_poll
, BGMAC_WEIGHT
);
1675 err
= bgmac_mii_register(bgmac
);
1677 bgmac_err(bgmac
, "Cannot register MDIO\n");
1681 net_dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
;
1682 net_dev
->hw_features
= net_dev
->features
;
1683 net_dev
->vlan_features
= net_dev
->features
;
1685 err
= register_netdev(bgmac
->net_dev
);
1687 bgmac_err(bgmac
, "Cannot register net device\n");
1688 goto err_mii_unregister
;
1691 netif_carrier_off(net_dev
);
1696 bgmac_mii_unregister(bgmac
);
1698 bgmac_dma_free(bgmac
);
1701 bcma_set_drvdata(core
, NULL
);
1702 free_netdev(net_dev
);
1707 static void bgmac_remove(struct bcma_device
*core
)
1709 struct bgmac
*bgmac
= bcma_get_drvdata(core
);
1711 unregister_netdev(bgmac
->net_dev
);
1712 bgmac_mii_unregister(bgmac
);
1713 netif_napi_del(&bgmac
->napi
);
1714 bgmac_dma_free(bgmac
);
1715 bcma_set_drvdata(core
, NULL
);
1716 free_netdev(bgmac
->net_dev
);
1719 static struct bcma_driver bgmac_bcma_driver
= {
1720 .name
= KBUILD_MODNAME
,
1721 .id_table
= bgmac_bcma_tbl
,
1722 .probe
= bgmac_probe
,
1723 .remove
= bgmac_remove
,
1726 static int __init
bgmac_init(void)
1730 err
= bcma_driver_register(&bgmac_bcma_driver
);
1733 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1738 static void __exit
bgmac_exit(void)
1740 bcma_driver_unregister(&bgmac_bcma_driver
);
1743 module_init(bgmac_init
)
1744 module_exit(bgmac_exit
)
1746 MODULE_AUTHOR("Rafał Miłecki");
1747 MODULE_LICENSE("GPL");