2 * Driver for (BCM4706)? GBit MAC core on BCMA bus.
4 * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
6 * Licensed under the GNU/GPL. See COPYING for details.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/phy.h>
17 #include <linux/phy_fixed.h>
18 #include <linux/interrupt.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/bcm47xx_nvram.h>
22 static const struct bcma_device_id bgmac_bcma_tbl
[] = {
23 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_4706_MAC_GBIT
, BCMA_ANY_REV
, BCMA_ANY_CLASS
),
24 BCMA_CORE(BCMA_MANUF_BCM
, BCMA_CORE_MAC_GBIT
, BCMA_ANY_REV
, BCMA_ANY_CLASS
),
27 MODULE_DEVICE_TABLE(bcma
, bgmac_bcma_tbl
);
29 static bool bgmac_wait_value(struct bcma_device
*core
, u16 reg
, u32 mask
,
30 u32 value
, int timeout
)
35 for (i
= 0; i
< timeout
/ 10; i
++) {
36 val
= bcma_read32(core
, reg
);
37 if ((val
& mask
) == value
)
41 pr_err("Timeout waiting for reg 0x%X\n", reg
);
45 /**************************************************
47 **************************************************/
49 static void bgmac_dma_tx_reset(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
57 /* Suspend DMA TX ring first.
58 * bgmac_wait_value doesn't support waiting for any of few values, so
59 * implement whole loop here.
61 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
,
62 BGMAC_DMA_TX_SUSPEND
);
63 for (i
= 0; i
< 10000 / 10; i
++) {
64 val
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
65 val
&= BGMAC_DMA_TX_STAT
;
66 if (val
== BGMAC_DMA_TX_STAT_DISABLED
||
67 val
== BGMAC_DMA_TX_STAT_IDLEWAIT
||
68 val
== BGMAC_DMA_TX_STAT_STOPPED
) {
75 bgmac_err(bgmac
, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
76 ring
->mmio_base
, val
);
78 /* Remove SUSPEND bit */
79 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
, 0);
80 if (!bgmac_wait_value(bgmac
->core
,
81 ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
,
82 BGMAC_DMA_TX_STAT
, BGMAC_DMA_TX_STAT_DISABLED
,
84 bgmac_warn(bgmac
, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
87 val
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
88 if ((val
& BGMAC_DMA_TX_STAT
) != BGMAC_DMA_TX_STAT_DISABLED
)
89 bgmac_err(bgmac
, "Reset of DMA TX ring 0x%X failed\n",
94 static void bgmac_dma_tx_enable(struct bgmac
*bgmac
,
95 struct bgmac_dma_ring
*ring
)
99 ctl
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
);
100 if (bgmac
->core
->id
.rev
>= 4) {
101 ctl
&= ~BGMAC_DMA_TX_BL_MASK
;
102 ctl
|= BGMAC_DMA_TX_BL_128
<< BGMAC_DMA_TX_BL_SHIFT
;
104 ctl
&= ~BGMAC_DMA_TX_MR_MASK
;
105 ctl
|= BGMAC_DMA_TX_MR_2
<< BGMAC_DMA_TX_MR_SHIFT
;
107 ctl
&= ~BGMAC_DMA_TX_PC_MASK
;
108 ctl
|= BGMAC_DMA_TX_PC_16
<< BGMAC_DMA_TX_PC_SHIFT
;
110 ctl
&= ~BGMAC_DMA_TX_PT_MASK
;
111 ctl
|= BGMAC_DMA_TX_PT_8
<< BGMAC_DMA_TX_PT_SHIFT
;
113 ctl
|= BGMAC_DMA_TX_ENABLE
;
114 ctl
|= BGMAC_DMA_TX_PARITY_DISABLE
;
115 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_CTL
, ctl
);
119 bgmac_dma_tx_add_buf(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
,
120 int i
, int len
, u32 ctl0
)
122 struct bgmac_slot_info
*slot
;
123 struct bgmac_dma_desc
*dma_desc
;
126 if (i
== BGMAC_TX_RING_SLOTS
- 1)
127 ctl0
|= BGMAC_DESC_CTL0_EOT
;
129 ctl1
= len
& BGMAC_DESC_CTL1_LEN
;
131 slot
= &ring
->slots
[i
];
132 dma_desc
= &ring
->cpu_base
[i
];
133 dma_desc
->addr_low
= cpu_to_le32(lower_32_bits(slot
->dma_addr
));
134 dma_desc
->addr_high
= cpu_to_le32(upper_32_bits(slot
->dma_addr
));
135 dma_desc
->ctl0
= cpu_to_le32(ctl0
);
136 dma_desc
->ctl1
= cpu_to_le32(ctl1
);
139 static netdev_tx_t
bgmac_dma_tx_add(struct bgmac
*bgmac
,
140 struct bgmac_dma_ring
*ring
,
143 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
144 struct net_device
*net_dev
= bgmac
->net_dev
;
145 int index
= ring
->end
% BGMAC_TX_RING_SLOTS
;
146 struct bgmac_slot_info
*slot
= &ring
->slots
[index
];
151 if (skb
->len
> BGMAC_DESC_CTL1_LEN
) {
152 bgmac_err(bgmac
, "Too long skb (%d)\n", skb
->len
);
156 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
157 skb_checksum_help(skb
);
159 nr_frags
= skb_shinfo(skb
)->nr_frags
;
161 /* ring->end - ring->start will return the number of valid slots,
162 * even when ring->end overflows
164 if (ring
->end
- ring
->start
+ nr_frags
+ 1 >= BGMAC_TX_RING_SLOTS
) {
165 bgmac_err(bgmac
, "TX ring is full, queue should be stopped!\n");
166 netif_stop_queue(net_dev
);
167 return NETDEV_TX_BUSY
;
170 slot
->dma_addr
= dma_map_single(dma_dev
, skb
->data
, skb_headlen(skb
),
172 if (unlikely(dma_mapping_error(dma_dev
, slot
->dma_addr
)))
175 flags
= BGMAC_DESC_CTL0_SOF
;
177 flags
|= BGMAC_DESC_CTL0_EOF
| BGMAC_DESC_CTL0_IOC
;
179 bgmac_dma_tx_add_buf(bgmac
, ring
, index
, skb_headlen(skb
), flags
);
182 for (i
= 0; i
< nr_frags
; i
++) {
183 struct skb_frag_struct
*frag
= &skb_shinfo(skb
)->frags
[i
];
184 int len
= skb_frag_size(frag
);
186 index
= (index
+ 1) % BGMAC_TX_RING_SLOTS
;
187 slot
= &ring
->slots
[index
];
188 slot
->dma_addr
= skb_frag_dma_map(dma_dev
, frag
, 0,
190 if (unlikely(dma_mapping_error(dma_dev
, slot
->dma_addr
)))
193 if (i
== nr_frags
- 1)
194 flags
|= BGMAC_DESC_CTL0_EOF
| BGMAC_DESC_CTL0_IOC
;
196 bgmac_dma_tx_add_buf(bgmac
, ring
, index
, len
, flags
);
200 ring
->end
+= nr_frags
+ 1;
201 netdev_sent_queue(net_dev
, skb
->len
);
205 /* Increase ring->end to point empty slot. We tell hardware the first
206 * slot it should *not* read.
208 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_INDEX
,
210 (ring
->end
% BGMAC_TX_RING_SLOTS
) *
211 sizeof(struct bgmac_dma_desc
));
213 if (ring
->end
- ring
->start
>= BGMAC_TX_RING_SLOTS
- 8)
214 netif_stop_queue(net_dev
);
219 dma_unmap_single(dma_dev
, slot
->dma_addr
, skb_headlen(skb
),
223 int index
= (ring
->end
+ i
) % BGMAC_TX_RING_SLOTS
;
224 struct bgmac_slot_info
*slot
= &ring
->slots
[index
];
225 u32 ctl1
= le32_to_cpu(ring
->cpu_base
[index
].ctl1
);
226 int len
= ctl1
& BGMAC_DESC_CTL1_LEN
;
228 dma_unmap_page(dma_dev
, slot
->dma_addr
, len
, DMA_TO_DEVICE
);
232 bgmac_err(bgmac
, "Mapping error of skb on ring 0x%X\n",
240 /* Free transmitted packets */
241 static void bgmac_dma_tx_free(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
243 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
246 unsigned bytes_compl
= 0, pkts_compl
= 0;
248 /* The last slot that hardware didn't consume yet */
249 empty_slot
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_STATUS
);
250 empty_slot
&= BGMAC_DMA_TX_STATDPTR
;
251 empty_slot
-= ring
->index_base
;
252 empty_slot
&= BGMAC_DMA_TX_STATDPTR
;
253 empty_slot
/= sizeof(struct bgmac_dma_desc
);
255 while (ring
->start
!= ring
->end
) {
256 int slot_idx
= ring
->start
% BGMAC_TX_RING_SLOTS
;
257 struct bgmac_slot_info
*slot
= &ring
->slots
[slot_idx
];
261 if (slot_idx
== empty_slot
)
264 ctl1
= le32_to_cpu(ring
->cpu_base
[slot_idx
].ctl1
);
265 len
= ctl1
& BGMAC_DESC_CTL1_LEN
;
266 if (ctl1
& BGMAC_DESC_CTL0_SOF
)
267 /* Unmap no longer used buffer */
268 dma_unmap_single(dma_dev
, slot
->dma_addr
, len
,
271 dma_unmap_page(dma_dev
, slot
->dma_addr
, len
,
275 bytes_compl
+= slot
->skb
->len
;
278 /* Free memory! :) */
279 dev_kfree_skb(slot
->skb
);
291 netdev_completed_queue(bgmac
->net_dev
, pkts_compl
, bytes_compl
);
293 if (netif_queue_stopped(bgmac
->net_dev
))
294 netif_wake_queue(bgmac
->net_dev
);
297 static void bgmac_dma_rx_reset(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
)
299 if (!ring
->mmio_base
)
302 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
, 0);
303 if (!bgmac_wait_value(bgmac
->core
,
304 ring
->mmio_base
+ BGMAC_DMA_RX_STATUS
,
305 BGMAC_DMA_RX_STAT
, BGMAC_DMA_RX_STAT_DISABLED
,
307 bgmac_err(bgmac
, "Reset of ring 0x%X RX failed\n",
311 static void bgmac_dma_rx_enable(struct bgmac
*bgmac
,
312 struct bgmac_dma_ring
*ring
)
316 ctl
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
);
317 if (bgmac
->core
->id
.rev
>= 4) {
318 ctl
&= ~BGMAC_DMA_RX_BL_MASK
;
319 ctl
|= BGMAC_DMA_RX_BL_128
<< BGMAC_DMA_RX_BL_SHIFT
;
321 ctl
&= ~BGMAC_DMA_RX_PC_MASK
;
322 ctl
|= BGMAC_DMA_RX_PC_8
<< BGMAC_DMA_RX_PC_SHIFT
;
324 ctl
&= ~BGMAC_DMA_RX_PT_MASK
;
325 ctl
|= BGMAC_DMA_RX_PT_1
<< BGMAC_DMA_RX_PT_SHIFT
;
327 ctl
&= BGMAC_DMA_RX_ADDREXT_MASK
;
328 ctl
|= BGMAC_DMA_RX_ENABLE
;
329 ctl
|= BGMAC_DMA_RX_PARITY_DISABLE
;
330 ctl
|= BGMAC_DMA_RX_OVERFLOW_CONT
;
331 ctl
|= BGMAC_RX_FRAME_OFFSET
<< BGMAC_DMA_RX_FRAME_OFFSET_SHIFT
;
332 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_CTL
, ctl
);
335 static int bgmac_dma_rx_skb_for_slot(struct bgmac
*bgmac
,
336 struct bgmac_slot_info
*slot
)
338 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
340 struct bgmac_rx_header
*rx
;
344 buf
= netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE
);
348 /* Poison - if everything goes fine, hardware will overwrite it */
349 rx
= buf
+ BGMAC_RX_BUF_OFFSET
;
350 rx
->len
= cpu_to_le16(0xdead);
351 rx
->flags
= cpu_to_le16(0xbeef);
353 /* Map skb for the DMA */
354 dma_addr
= dma_map_single(dma_dev
, buf
+ BGMAC_RX_BUF_OFFSET
,
355 BGMAC_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
356 if (dma_mapping_error(dma_dev
, dma_addr
)) {
357 bgmac_err(bgmac
, "DMA mapping error\n");
358 put_page(virt_to_head_page(buf
));
362 /* Update the slot */
364 slot
->dma_addr
= dma_addr
;
369 static void bgmac_dma_rx_update_index(struct bgmac
*bgmac
,
370 struct bgmac_dma_ring
*ring
)
374 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_INDEX
,
376 ring
->end
* sizeof(struct bgmac_dma_desc
));
379 static void bgmac_dma_rx_setup_desc(struct bgmac
*bgmac
,
380 struct bgmac_dma_ring
*ring
, int desc_idx
)
382 struct bgmac_dma_desc
*dma_desc
= ring
->cpu_base
+ desc_idx
;
383 u32 ctl0
= 0, ctl1
= 0;
385 if (desc_idx
== BGMAC_RX_RING_SLOTS
- 1)
386 ctl0
|= BGMAC_DESC_CTL0_EOT
;
387 ctl1
|= BGMAC_RX_BUF_SIZE
& BGMAC_DESC_CTL1_LEN
;
388 /* Is there any BGMAC device that requires extension? */
389 /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
390 * B43_DMA64_DCTL1_ADDREXT_MASK;
393 dma_desc
->addr_low
= cpu_to_le32(lower_32_bits(ring
->slots
[desc_idx
].dma_addr
));
394 dma_desc
->addr_high
= cpu_to_le32(upper_32_bits(ring
->slots
[desc_idx
].dma_addr
));
395 dma_desc
->ctl0
= cpu_to_le32(ctl0
);
396 dma_desc
->ctl1
= cpu_to_le32(ctl1
);
398 ring
->end
= desc_idx
;
401 static void bgmac_dma_rx_poison_buf(struct device
*dma_dev
,
402 struct bgmac_slot_info
*slot
)
404 struct bgmac_rx_header
*rx
= slot
->buf
+ BGMAC_RX_BUF_OFFSET
;
406 dma_sync_single_for_cpu(dma_dev
, slot
->dma_addr
, BGMAC_RX_BUF_SIZE
,
408 rx
->len
= cpu_to_le16(0xdead);
409 rx
->flags
= cpu_to_le16(0xbeef);
410 dma_sync_single_for_device(dma_dev
, slot
->dma_addr
, BGMAC_RX_BUF_SIZE
,
414 static int bgmac_dma_rx_read(struct bgmac
*bgmac
, struct bgmac_dma_ring
*ring
,
420 end_slot
= bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_STATUS
);
421 end_slot
&= BGMAC_DMA_RX_STATDPTR
;
422 end_slot
-= ring
->index_base
;
423 end_slot
&= BGMAC_DMA_RX_STATDPTR
;
424 end_slot
/= sizeof(struct bgmac_dma_desc
);
426 while (ring
->start
!= end_slot
) {
427 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
428 struct bgmac_slot_info
*slot
= &ring
->slots
[ring
->start
];
429 struct bgmac_rx_header
*rx
= slot
->buf
+ BGMAC_RX_BUF_OFFSET
;
431 void *buf
= slot
->buf
;
432 dma_addr_t dma_addr
= slot
->dma_addr
;
436 /* Prepare new skb as replacement */
437 if (bgmac_dma_rx_skb_for_slot(bgmac
, slot
)) {
438 bgmac_dma_rx_poison_buf(dma_dev
, slot
);
442 /* Unmap buffer to make it accessible to the CPU */
443 dma_unmap_single(dma_dev
, dma_addr
,
444 BGMAC_RX_BUF_SIZE
, DMA_FROM_DEVICE
);
446 /* Get info from the header */
447 len
= le16_to_cpu(rx
->len
);
448 flags
= le16_to_cpu(rx
->flags
);
450 /* Check for poison and drop or pass the packet */
451 if (len
== 0xdead && flags
== 0xbeef) {
452 bgmac_err(bgmac
, "Found poisoned packet at slot %d, DMA issue!\n",
454 put_page(virt_to_head_page(buf
));
458 if (len
> BGMAC_RX_ALLOC_SIZE
) {
459 bgmac_err(bgmac
, "Found oversized packet at slot %d, DMA issue!\n",
461 put_page(virt_to_head_page(buf
));
468 skb
= build_skb(buf
, BGMAC_RX_ALLOC_SIZE
);
469 if (unlikely(!skb
)) {
470 bgmac_err(bgmac
, "build_skb failed\n");
471 put_page(virt_to_head_page(buf
));
474 skb_put(skb
, BGMAC_RX_FRAME_OFFSET
+
475 BGMAC_RX_BUF_OFFSET
+ len
);
476 skb_pull(skb
, BGMAC_RX_FRAME_OFFSET
+
477 BGMAC_RX_BUF_OFFSET
);
479 skb_checksum_none_assert(skb
);
480 skb
->protocol
= eth_type_trans(skb
, bgmac
->net_dev
);
481 napi_gro_receive(&bgmac
->napi
, skb
);
485 bgmac_dma_rx_setup_desc(bgmac
, ring
, ring
->start
);
487 if (++ring
->start
>= BGMAC_RX_RING_SLOTS
)
490 if (handled
>= weight
) /* Should never be greater */
494 bgmac_dma_rx_update_index(bgmac
, ring
);
499 /* Does ring support unaligned addressing? */
500 static bool bgmac_dma_unaligned(struct bgmac
*bgmac
,
501 struct bgmac_dma_ring
*ring
,
502 enum bgmac_dma_ring_type ring_type
)
505 case BGMAC_DMA_RING_TX
:
506 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
,
508 if (bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
))
511 case BGMAC_DMA_RING_RX
:
512 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
,
514 if (bgmac_read(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
))
521 static void bgmac_dma_tx_ring_free(struct bgmac
*bgmac
,
522 struct bgmac_dma_ring
*ring
)
524 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
525 struct bgmac_dma_desc
*dma_desc
= ring
->cpu_base
;
526 struct bgmac_slot_info
*slot
;
529 for (i
= 0; i
< BGMAC_TX_RING_SLOTS
; i
++) {
530 int len
= dma_desc
[i
].ctl1
& BGMAC_DESC_CTL1_LEN
;
532 slot
= &ring
->slots
[i
];
533 dev_kfree_skb(slot
->skb
);
539 dma_unmap_single(dma_dev
, slot
->dma_addr
,
542 dma_unmap_page(dma_dev
, slot
->dma_addr
,
547 static void bgmac_dma_rx_ring_free(struct bgmac
*bgmac
,
548 struct bgmac_dma_ring
*ring
)
550 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
551 struct bgmac_slot_info
*slot
;
554 for (i
= 0; i
< BGMAC_RX_RING_SLOTS
; i
++) {
555 slot
= &ring
->slots
[i
];
559 dma_unmap_single(dma_dev
, slot
->dma_addr
,
562 put_page(virt_to_head_page(slot
->buf
));
567 static void bgmac_dma_ring_desc_free(struct bgmac
*bgmac
,
568 struct bgmac_dma_ring
*ring
,
571 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
577 /* Free ring of descriptors */
578 size
= num_slots
* sizeof(struct bgmac_dma_desc
);
579 dma_free_coherent(dma_dev
, size
, ring
->cpu_base
,
583 static void bgmac_dma_cleanup(struct bgmac
*bgmac
)
587 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
588 bgmac_dma_tx_ring_free(bgmac
, &bgmac
->tx_ring
[i
]);
590 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
591 bgmac_dma_rx_ring_free(bgmac
, &bgmac
->rx_ring
[i
]);
594 static void bgmac_dma_free(struct bgmac
*bgmac
)
598 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
599 bgmac_dma_ring_desc_free(bgmac
, &bgmac
->tx_ring
[i
],
600 BGMAC_TX_RING_SLOTS
);
602 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
603 bgmac_dma_ring_desc_free(bgmac
, &bgmac
->rx_ring
[i
],
604 BGMAC_RX_RING_SLOTS
);
607 static int bgmac_dma_alloc(struct bgmac
*bgmac
)
609 struct device
*dma_dev
= bgmac
->core
->dma_dev
;
610 struct bgmac_dma_ring
*ring
;
611 static const u16 ring_base
[] = { BGMAC_DMA_BASE0
, BGMAC_DMA_BASE1
,
612 BGMAC_DMA_BASE2
, BGMAC_DMA_BASE3
, };
613 int size
; /* ring size: different for Tx and Rx */
617 BUILD_BUG_ON(BGMAC_MAX_TX_RINGS
> ARRAY_SIZE(ring_base
));
618 BUILD_BUG_ON(BGMAC_MAX_RX_RINGS
> ARRAY_SIZE(ring_base
));
620 if (!(bcma_aread32(bgmac
->core
, BCMA_IOST
) & BCMA_IOST_DMA64
)) {
621 bgmac_err(bgmac
, "Core does not report 64-bit DMA\n");
625 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++) {
626 ring
= &bgmac
->tx_ring
[i
];
627 ring
->mmio_base
= ring_base
[i
];
629 /* Alloc ring of descriptors */
630 size
= BGMAC_TX_RING_SLOTS
* sizeof(struct bgmac_dma_desc
);
631 ring
->cpu_base
= dma_zalloc_coherent(dma_dev
, size
,
634 if (!ring
->cpu_base
) {
635 bgmac_err(bgmac
, "Allocation of TX ring 0x%X failed\n",
640 ring
->unaligned
= bgmac_dma_unaligned(bgmac
, ring
,
643 ring
->index_base
= lower_32_bits(ring
->dma_base
);
645 ring
->index_base
= 0;
647 /* No need to alloc TX slots yet */
650 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++) {
651 ring
= &bgmac
->rx_ring
[i
];
652 ring
->mmio_base
= ring_base
[i
];
654 /* Alloc ring of descriptors */
655 size
= BGMAC_RX_RING_SLOTS
* sizeof(struct bgmac_dma_desc
);
656 ring
->cpu_base
= dma_zalloc_coherent(dma_dev
, size
,
659 if (!ring
->cpu_base
) {
660 bgmac_err(bgmac
, "Allocation of RX ring 0x%X failed\n",
666 ring
->unaligned
= bgmac_dma_unaligned(bgmac
, ring
,
669 ring
->index_base
= lower_32_bits(ring
->dma_base
);
671 ring
->index_base
= 0;
677 bgmac_dma_free(bgmac
);
681 static int bgmac_dma_init(struct bgmac
*bgmac
)
683 struct bgmac_dma_ring
*ring
;
686 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++) {
687 ring
= &bgmac
->tx_ring
[i
];
689 if (!ring
->unaligned
)
690 bgmac_dma_tx_enable(bgmac
, ring
);
691 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGLO
,
692 lower_32_bits(ring
->dma_base
));
693 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_TX_RINGHI
,
694 upper_32_bits(ring
->dma_base
));
696 bgmac_dma_tx_enable(bgmac
, ring
);
699 ring
->end
= 0; /* Points the slot that should *not* be read */
702 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++) {
705 ring
= &bgmac
->rx_ring
[i
];
707 if (!ring
->unaligned
)
708 bgmac_dma_rx_enable(bgmac
, ring
);
709 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGLO
,
710 lower_32_bits(ring
->dma_base
));
711 bgmac_write(bgmac
, ring
->mmio_base
+ BGMAC_DMA_RX_RINGHI
,
712 upper_32_bits(ring
->dma_base
));
714 bgmac_dma_rx_enable(bgmac
, ring
);
718 for (j
= 0; j
< BGMAC_RX_RING_SLOTS
; j
++) {
719 err
= bgmac_dma_rx_skb_for_slot(bgmac
, &ring
->slots
[j
]);
723 bgmac_dma_rx_setup_desc(bgmac
, ring
, j
);
726 bgmac_dma_rx_update_index(bgmac
, ring
);
732 bgmac_dma_cleanup(bgmac
);
736 /**************************************************
738 **************************************************/
740 static u16
bgmac_phy_read(struct bgmac
*bgmac
, u8 phyaddr
, u8 reg
)
742 struct bcma_device
*core
;
747 BUILD_BUG_ON(BGMAC_PA_DATA_MASK
!= BCMA_GMAC_CMN_PA_DATA_MASK
);
748 BUILD_BUG_ON(BGMAC_PA_ADDR_MASK
!= BCMA_GMAC_CMN_PA_ADDR_MASK
);
749 BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT
!= BCMA_GMAC_CMN_PA_ADDR_SHIFT
);
750 BUILD_BUG_ON(BGMAC_PA_REG_MASK
!= BCMA_GMAC_CMN_PA_REG_MASK
);
751 BUILD_BUG_ON(BGMAC_PA_REG_SHIFT
!= BCMA_GMAC_CMN_PA_REG_SHIFT
);
752 BUILD_BUG_ON(BGMAC_PA_WRITE
!= BCMA_GMAC_CMN_PA_WRITE
);
753 BUILD_BUG_ON(BGMAC_PA_START
!= BCMA_GMAC_CMN_PA_START
);
754 BUILD_BUG_ON(BGMAC_PC_EPA_MASK
!= BCMA_GMAC_CMN_PC_EPA_MASK
);
755 BUILD_BUG_ON(BGMAC_PC_MCT_MASK
!= BCMA_GMAC_CMN_PC_MCT_MASK
);
756 BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT
!= BCMA_GMAC_CMN_PC_MCT_SHIFT
);
757 BUILD_BUG_ON(BGMAC_PC_MTE
!= BCMA_GMAC_CMN_PC_MTE
);
759 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
) {
760 core
= bgmac
->core
->bus
->drv_gmac_cmn
.core
;
761 phy_access_addr
= BCMA_GMAC_CMN_PHY_ACCESS
;
762 phy_ctl_addr
= BCMA_GMAC_CMN_PHY_CTL
;
765 phy_access_addr
= BGMAC_PHY_ACCESS
;
766 phy_ctl_addr
= BGMAC_PHY_CNTL
;
769 tmp
= bcma_read32(core
, phy_ctl_addr
);
770 tmp
&= ~BGMAC_PC_EPA_MASK
;
772 bcma_write32(core
, phy_ctl_addr
, tmp
);
774 tmp
= BGMAC_PA_START
;
775 tmp
|= phyaddr
<< BGMAC_PA_ADDR_SHIFT
;
776 tmp
|= reg
<< BGMAC_PA_REG_SHIFT
;
777 bcma_write32(core
, phy_access_addr
, tmp
);
779 if (!bgmac_wait_value(core
, phy_access_addr
, BGMAC_PA_START
, 0, 1000)) {
780 bgmac_err(bgmac
, "Reading PHY %d register 0x%X failed\n",
785 return bcma_read32(core
, phy_access_addr
) & BGMAC_PA_DATA_MASK
;
788 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
789 static int bgmac_phy_write(struct bgmac
*bgmac
, u8 phyaddr
, u8 reg
, u16 value
)
791 struct bcma_device
*core
;
796 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
) {
797 core
= bgmac
->core
->bus
->drv_gmac_cmn
.core
;
798 phy_access_addr
= BCMA_GMAC_CMN_PHY_ACCESS
;
799 phy_ctl_addr
= BCMA_GMAC_CMN_PHY_CTL
;
802 phy_access_addr
= BGMAC_PHY_ACCESS
;
803 phy_ctl_addr
= BGMAC_PHY_CNTL
;
806 tmp
= bcma_read32(core
, phy_ctl_addr
);
807 tmp
&= ~BGMAC_PC_EPA_MASK
;
809 bcma_write32(core
, phy_ctl_addr
, tmp
);
811 bgmac_write(bgmac
, BGMAC_INT_STATUS
, BGMAC_IS_MDIO
);
812 if (bgmac_read(bgmac
, BGMAC_INT_STATUS
) & BGMAC_IS_MDIO
)
813 bgmac_warn(bgmac
, "Error setting MDIO int\n");
815 tmp
= BGMAC_PA_START
;
816 tmp
|= BGMAC_PA_WRITE
;
817 tmp
|= phyaddr
<< BGMAC_PA_ADDR_SHIFT
;
818 tmp
|= reg
<< BGMAC_PA_REG_SHIFT
;
820 bcma_write32(core
, phy_access_addr
, tmp
);
822 if (!bgmac_wait_value(core
, phy_access_addr
, BGMAC_PA_START
, 0, 1000)) {
823 bgmac_err(bgmac
, "Writing to PHY %d register 0x%X failed\n",
831 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
832 static void bgmac_phy_init(struct bgmac
*bgmac
)
834 struct bcma_chipinfo
*ci
= &bgmac
->core
->bus
->chipinfo
;
835 struct bcma_drv_cc
*cc
= &bgmac
->core
->bus
->drv_cc
;
838 if (ci
->id
== BCMA_CHIP_ID_BCM5356
) {
839 for (i
= 0; i
< 5; i
++) {
840 bgmac_phy_write(bgmac
, i
, 0x1f, 0x008b);
841 bgmac_phy_write(bgmac
, i
, 0x15, 0x0100);
842 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
843 bgmac_phy_write(bgmac
, i
, 0x12, 0x2aaa);
844 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
847 if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
!= 10) ||
848 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
!= 10) ||
849 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
!= 9)) {
850 bcma_chipco_chipctl_maskset(cc
, 2, ~0xc0000000, 0);
851 bcma_chipco_chipctl_maskset(cc
, 4, ~0x80000000, 0);
852 for (i
= 0; i
< 5; i
++) {
853 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
854 bgmac_phy_write(bgmac
, i
, 0x16, 0x5284);
855 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
856 bgmac_phy_write(bgmac
, i
, 0x17, 0x0010);
857 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000f);
858 bgmac_phy_write(bgmac
, i
, 0x16, 0x5296);
859 bgmac_phy_write(bgmac
, i
, 0x17, 0x1073);
860 bgmac_phy_write(bgmac
, i
, 0x17, 0x9073);
861 bgmac_phy_write(bgmac
, i
, 0x16, 0x52b6);
862 bgmac_phy_write(bgmac
, i
, 0x17, 0x9273);
863 bgmac_phy_write(bgmac
, i
, 0x1f, 0x000b);
868 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
869 static void bgmac_phy_reset(struct bgmac
*bgmac
)
871 if (bgmac
->phyaddr
== BGMAC_PHY_NOREGS
)
874 bgmac_phy_write(bgmac
, bgmac
->phyaddr
, MII_BMCR
, BMCR_RESET
);
876 if (bgmac_phy_read(bgmac
, bgmac
->phyaddr
, MII_BMCR
) & BMCR_RESET
)
877 bgmac_err(bgmac
, "PHY reset failed\n");
878 bgmac_phy_init(bgmac
);
881 /**************************************************
883 **************************************************/
885 /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
886 * nothing to change? Try if after stabilizng driver.
888 static void bgmac_cmdcfg_maskset(struct bgmac
*bgmac
, u32 mask
, u32 set
,
891 u32 cmdcfg
= bgmac_read(bgmac
, BGMAC_CMDCFG
);
892 u32 new_val
= (cmdcfg
& mask
) | set
;
894 bgmac_set(bgmac
, BGMAC_CMDCFG
, BGMAC_CMDCFG_SR(bgmac
->core
->id
.rev
));
897 if (new_val
!= cmdcfg
|| force
)
898 bgmac_write(bgmac
, BGMAC_CMDCFG
, new_val
);
900 bgmac_mask(bgmac
, BGMAC_CMDCFG
, ~BGMAC_CMDCFG_SR(bgmac
->core
->id
.rev
));
904 static void bgmac_write_mac_address(struct bgmac
*bgmac
, u8
*addr
)
908 tmp
= (addr
[0] << 24) | (addr
[1] << 16) | (addr
[2] << 8) | addr
[3];
909 bgmac_write(bgmac
, BGMAC_MACADDR_HIGH
, tmp
);
910 tmp
= (addr
[4] << 8) | addr
[5];
911 bgmac_write(bgmac
, BGMAC_MACADDR_LOW
, tmp
);
914 static void bgmac_set_rx_mode(struct net_device
*net_dev
)
916 struct bgmac
*bgmac
= netdev_priv(net_dev
);
918 if (net_dev
->flags
& IFF_PROMISC
)
919 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_PROM
, true);
921 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_PROM
, 0, true);
924 #if 0 /* We don't use that regs yet */
925 static void bgmac_chip_stats_update(struct bgmac
*bgmac
)
929 if (bgmac
->core
->id
.id
!= BCMA_CORE_4706_MAC_GBIT
) {
930 for (i
= 0; i
< BGMAC_NUM_MIB_TX_REGS
; i
++)
931 bgmac
->mib_tx_regs
[i
] =
933 BGMAC_TX_GOOD_OCTETS
+ (i
* 4));
934 for (i
= 0; i
< BGMAC_NUM_MIB_RX_REGS
; i
++)
935 bgmac
->mib_rx_regs
[i
] =
937 BGMAC_RX_GOOD_OCTETS
+ (i
* 4));
940 /* TODO: what else? how to handle BCM4706? Specs are needed */
944 static void bgmac_clear_mib(struct bgmac
*bgmac
)
948 if (bgmac
->core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
)
951 bgmac_set(bgmac
, BGMAC_DEV_CTL
, BGMAC_DC_MROR
);
952 for (i
= 0; i
< BGMAC_NUM_MIB_TX_REGS
; i
++)
953 bgmac_read(bgmac
, BGMAC_TX_GOOD_OCTETS
+ (i
* 4));
954 for (i
= 0; i
< BGMAC_NUM_MIB_RX_REGS
; i
++)
955 bgmac_read(bgmac
, BGMAC_RX_GOOD_OCTETS
+ (i
* 4));
958 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
959 static void bgmac_mac_speed(struct bgmac
*bgmac
)
961 u32 mask
= ~(BGMAC_CMDCFG_ES_MASK
| BGMAC_CMDCFG_HD
);
964 switch (bgmac
->mac_speed
) {
966 set
|= BGMAC_CMDCFG_ES_10
;
969 set
|= BGMAC_CMDCFG_ES_100
;
972 set
|= BGMAC_CMDCFG_ES_1000
;
975 set
|= BGMAC_CMDCFG_ES_2500
;
978 bgmac_err(bgmac
, "Unsupported speed: %d\n", bgmac
->mac_speed
);
981 if (bgmac
->mac_duplex
== DUPLEX_HALF
)
982 set
|= BGMAC_CMDCFG_HD
;
984 bgmac_cmdcfg_maskset(bgmac
, mask
, set
, true);
987 static void bgmac_miiconfig(struct bgmac
*bgmac
)
989 struct bcma_device
*core
= bgmac
->core
;
990 struct bcma_chipinfo
*ci
= &core
->bus
->chipinfo
;
993 if (ci
->id
== BCMA_CHIP_ID_BCM4707
||
994 ci
->id
== BCMA_CHIP_ID_BCM53018
) {
995 bcma_awrite32(core
, BCMA_IOCTL
,
996 bcma_aread32(core
, BCMA_IOCTL
) | 0x40 |
997 BGMAC_BCMA_IOCTL_SW_CLKEN
);
998 bgmac
->mac_speed
= SPEED_2500
;
999 bgmac
->mac_duplex
= DUPLEX_FULL
;
1000 bgmac_mac_speed(bgmac
);
1002 imode
= (bgmac_read(bgmac
, BGMAC_DEV_STATUS
) &
1003 BGMAC_DS_MM_MASK
) >> BGMAC_DS_MM_SHIFT
;
1004 if (imode
== 0 || imode
== 1) {
1005 bgmac
->mac_speed
= SPEED_100
;
1006 bgmac
->mac_duplex
= DUPLEX_FULL
;
1007 bgmac_mac_speed(bgmac
);
1012 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
1013 static void bgmac_chip_reset(struct bgmac
*bgmac
)
1015 struct bcma_device
*core
= bgmac
->core
;
1016 struct bcma_bus
*bus
= core
->bus
;
1017 struct bcma_chipinfo
*ci
= &bus
->chipinfo
;
1022 if (bcma_core_is_enabled(core
)) {
1023 if (!bgmac
->stats_grabbed
) {
1024 /* bgmac_chip_stats_update(bgmac); */
1025 bgmac
->stats_grabbed
= true;
1028 for (i
= 0; i
< BGMAC_MAX_TX_RINGS
; i
++)
1029 bgmac_dma_tx_reset(bgmac
, &bgmac
->tx_ring
[i
]);
1031 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_ML
, false);
1034 for (i
= 0; i
< BGMAC_MAX_RX_RINGS
; i
++)
1035 bgmac_dma_rx_reset(bgmac
, &bgmac
->rx_ring
[i
]);
1037 /* TODO: Clear software multicast filter list */
1040 iost
= bcma_aread32(core
, BCMA_IOST
);
1041 if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== BCMA_PKG_ID_BCM47186
) ||
1042 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
== 10) ||
1043 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
== BCMA_PKG_ID_BCM47188
))
1044 iost
&= ~BGMAC_BCMA_IOST_ATTACHED
;
1046 /* 3GMAC: for BCM4707, only do core reset at bgmac_probe() */
1047 if (ci
->id
!= BCMA_CHIP_ID_BCM4707
) {
1049 if (iost
& BGMAC_BCMA_IOST_ATTACHED
) {
1050 flags
= BGMAC_BCMA_IOCTL_SW_CLKEN
;
1051 if (!bgmac
->has_robosw
)
1052 flags
|= BGMAC_BCMA_IOCTL_SW_RESET
;
1054 bcma_core_enable(core
, flags
);
1057 /* Request Misc PLL for corerev > 2 */
1058 if (core
->id
.rev
> 2 &&
1059 ci
->id
!= BCMA_CHIP_ID_BCM4707
&&
1060 ci
->id
!= BCMA_CHIP_ID_BCM53018
) {
1061 bgmac_set(bgmac
, BCMA_CLKCTLST
,
1062 BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ
);
1063 bgmac_wait_value(bgmac
->core
, BCMA_CLKCTLST
,
1064 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST
,
1065 BGMAC_BCMA_CLKCTLST_MISC_PLL_ST
,
1069 if (ci
->id
== BCMA_CHIP_ID_BCM5357
||
1070 ci
->id
== BCMA_CHIP_ID_BCM4749
||
1071 ci
->id
== BCMA_CHIP_ID_BCM53572
) {
1072 struct bcma_drv_cc
*cc
= &bgmac
->core
->bus
->drv_cc
;
1074 u8 sw_type
= BGMAC_CHIPCTL_1_SW_TYPE_EPHY
|
1075 BGMAC_CHIPCTL_1_IF_TYPE_MII
;
1078 if (bcm47xx_nvram_getenv("et_swtype", buf
, sizeof(buf
)) > 0) {
1079 if (kstrtou8(buf
, 0, &et_swtype
))
1080 bgmac_err(bgmac
, "Failed to parse et_swtype (%s)\n",
1084 sw_type
= et_swtype
;
1085 } else if (ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== BCMA_PKG_ID_BCM5358
) {
1086 sw_type
= BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII
;
1087 } else if ((ci
->id
== BCMA_CHIP_ID_BCM5357
&& ci
->pkg
== BCMA_PKG_ID_BCM47186
) ||
1088 (ci
->id
== BCMA_CHIP_ID_BCM4749
&& ci
->pkg
== 10) ||
1089 (ci
->id
== BCMA_CHIP_ID_BCM53572
&& ci
->pkg
== BCMA_PKG_ID_BCM47188
)) {
1090 sw_type
= BGMAC_CHIPCTL_1_IF_TYPE_RGMII
|
1091 BGMAC_CHIPCTL_1_SW_TYPE_RGMII
;
1093 bcma_chipco_chipctl_maskset(cc
, 1,
1094 ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK
|
1095 BGMAC_CHIPCTL_1_SW_TYPE_MASK
),
1099 if (iost
& BGMAC_BCMA_IOST_ATTACHED
&& !bgmac
->has_robosw
)
1100 bcma_awrite32(core
, BCMA_IOCTL
,
1101 bcma_aread32(core
, BCMA_IOCTL
) &
1102 ~BGMAC_BCMA_IOCTL_SW_RESET
);
1104 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
1105 * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
1106 * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
1107 * be keps until taking MAC out of the reset.
1109 bgmac_cmdcfg_maskset(bgmac
,
1121 BGMAC_CMDCFG_PAD_EN
|
1126 BGMAC_CMDCFG_SR(core
->id
.rev
),
1128 bgmac
->mac_speed
= SPEED_UNKNOWN
;
1129 bgmac
->mac_duplex
= DUPLEX_UNKNOWN
;
1131 bgmac_clear_mib(bgmac
);
1132 if (core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
)
1133 bcma_maskset32(bgmac
->cmn
, BCMA_GMAC_CMN_PHY_CTL
, ~0,
1134 BCMA_GMAC_CMN_PC_MTE
);
1136 bgmac_set(bgmac
, BGMAC_PHY_CNTL
, BGMAC_PC_MTE
);
1137 bgmac_miiconfig(bgmac
);
1138 bgmac_phy_init(bgmac
);
1140 netdev_reset_queue(bgmac
->net_dev
);
1143 static void bgmac_chip_intrs_on(struct bgmac
*bgmac
)
1145 bgmac_write(bgmac
, BGMAC_INT_MASK
, bgmac
->int_mask
);
1148 static void bgmac_chip_intrs_off(struct bgmac
*bgmac
)
1150 bgmac_write(bgmac
, BGMAC_INT_MASK
, 0);
1151 bgmac_read(bgmac
, BGMAC_INT_MASK
);
1154 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
1155 static void bgmac_enable(struct bgmac
*bgmac
)
1157 struct bcma_chipinfo
*ci
= &bgmac
->core
->bus
->chipinfo
;
1165 cmdcfg
= bgmac_read(bgmac
, BGMAC_CMDCFG
);
1166 bgmac_cmdcfg_maskset(bgmac
, ~(BGMAC_CMDCFG_TE
| BGMAC_CMDCFG_RE
),
1167 BGMAC_CMDCFG_SR(bgmac
->core
->id
.rev
), true);
1169 cmdcfg
|= BGMAC_CMDCFG_TE
| BGMAC_CMDCFG_RE
;
1170 bgmac_write(bgmac
, BGMAC_CMDCFG
, cmdcfg
);
1172 mode
= (bgmac_read(bgmac
, BGMAC_DEV_STATUS
) & BGMAC_DS_MM_MASK
) >>
1174 if (ci
->id
!= BCMA_CHIP_ID_BCM47162
|| mode
!= 0)
1175 bgmac_set(bgmac
, BCMA_CLKCTLST
, BCMA_CLKCTLST_FORCEHT
);
1176 if (ci
->id
== BCMA_CHIP_ID_BCM47162
&& mode
== 2)
1177 bcma_chipco_chipctl_maskset(&bgmac
->core
->bus
->drv_cc
, 1, ~0,
1178 BGMAC_CHIPCTL_1_RXC_DLL_BYPASS
);
1181 case BCMA_CHIP_ID_BCM5357
:
1182 case BCMA_CHIP_ID_BCM4749
:
1183 case BCMA_CHIP_ID_BCM53572
:
1184 case BCMA_CHIP_ID_BCM4716
:
1185 case BCMA_CHIP_ID_BCM47162
:
1186 fl_ctl
= 0x03cb04cb;
1187 if (ci
->id
== BCMA_CHIP_ID_BCM5357
||
1188 ci
->id
== BCMA_CHIP_ID_BCM4749
||
1189 ci
->id
== BCMA_CHIP_ID_BCM53572
)
1191 bgmac_write(bgmac
, BGMAC_FLOW_CTL_THRESH
, fl_ctl
);
1192 bgmac_write(bgmac
, BGMAC_PAUSE_CTL
, 0x27fff);
1196 if (ci
->id
!= BCMA_CHIP_ID_BCM4707
&&
1197 ci
->id
!= BCMA_CHIP_ID_BCM53018
) {
1198 rxq_ctl
= bgmac_read(bgmac
, BGMAC_RXQ_CTL
);
1199 rxq_ctl
&= ~BGMAC_RXQ_CTL_MDP_MASK
;
1200 bp_clk
= bcma_pmu_get_bus_clock(&bgmac
->core
->bus
->drv_cc
) /
1202 mdp
= (bp_clk
* 128 / 1000) - 3;
1203 rxq_ctl
|= (mdp
<< BGMAC_RXQ_CTL_MDP_SHIFT
);
1204 bgmac_write(bgmac
, BGMAC_RXQ_CTL
, rxq_ctl
);
1208 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
1209 static void bgmac_chip_init(struct bgmac
*bgmac
)
1211 /* 1 interrupt per received frame */
1212 bgmac_write(bgmac
, BGMAC_INT_RECV_LAZY
, 1 << BGMAC_IRL_FC_SHIFT
);
1214 /* Enable 802.3x tx flow control (honor received PAUSE frames) */
1215 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_RPI
, 0, true);
1217 bgmac_set_rx_mode(bgmac
->net_dev
);
1219 bgmac_write_mac_address(bgmac
, bgmac
->net_dev
->dev_addr
);
1221 if (bgmac
->loopback
)
1222 bgmac_cmdcfg_maskset(bgmac
, ~0, BGMAC_CMDCFG_ML
, false);
1224 bgmac_cmdcfg_maskset(bgmac
, ~BGMAC_CMDCFG_ML
, 0, false);
1226 bgmac_write(bgmac
, BGMAC_RXMAX_LENGTH
, 32 + ETHER_MAX_LEN
);
1228 bgmac_chip_intrs_on(bgmac
);
1230 bgmac_enable(bgmac
);
1233 static irqreturn_t
bgmac_interrupt(int irq
, void *dev_id
)
1235 struct bgmac
*bgmac
= netdev_priv(dev_id
);
1237 u32 int_status
= bgmac_read(bgmac
, BGMAC_INT_STATUS
);
1238 int_status
&= bgmac
->int_mask
;
1243 int_status
&= ~(BGMAC_IS_TX0
| BGMAC_IS_RX
);
1245 bgmac_err(bgmac
, "Unknown IRQs: 0x%08X\n", int_status
);
1247 /* Disable new interrupts until handling existing ones */
1248 bgmac_chip_intrs_off(bgmac
);
1250 napi_schedule(&bgmac
->napi
);
1255 static int bgmac_poll(struct napi_struct
*napi
, int weight
)
1257 struct bgmac
*bgmac
= container_of(napi
, struct bgmac
, napi
);
1261 bgmac_write(bgmac
, BGMAC_INT_STATUS
, ~0);
1263 bgmac_dma_tx_free(bgmac
, &bgmac
->tx_ring
[0]);
1264 handled
+= bgmac_dma_rx_read(bgmac
, &bgmac
->rx_ring
[0], weight
);
1266 /* Poll again if more events arrived in the meantime */
1267 if (bgmac_read(bgmac
, BGMAC_INT_STATUS
) & (BGMAC_IS_TX0
| BGMAC_IS_RX
))
1270 if (handled
< weight
) {
1271 napi_complete(napi
);
1272 bgmac_chip_intrs_on(bgmac
);
1278 /**************************************************
1280 **************************************************/
1282 static int bgmac_open(struct net_device
*net_dev
)
1284 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1287 bgmac_chip_reset(bgmac
);
1289 err
= bgmac_dma_init(bgmac
);
1293 /* Specs say about reclaiming rings here, but we do that in DMA init */
1294 bgmac_chip_init(bgmac
);
1296 err
= request_irq(bgmac
->core
->irq
, bgmac_interrupt
, IRQF_SHARED
,
1297 KBUILD_MODNAME
, net_dev
);
1299 bgmac_err(bgmac
, "IRQ request error: %d!\n", err
);
1300 bgmac_dma_cleanup(bgmac
);
1303 napi_enable(&bgmac
->napi
);
1305 phy_start(bgmac
->phy_dev
);
1307 netif_carrier_on(net_dev
);
1311 static int bgmac_stop(struct net_device
*net_dev
)
1313 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1315 netif_carrier_off(net_dev
);
1317 phy_stop(bgmac
->phy_dev
);
1319 napi_disable(&bgmac
->napi
);
1320 bgmac_chip_intrs_off(bgmac
);
1321 free_irq(bgmac
->core
->irq
, net_dev
);
1323 bgmac_chip_reset(bgmac
);
1324 bgmac_dma_cleanup(bgmac
);
1329 static netdev_tx_t
bgmac_start_xmit(struct sk_buff
*skb
,
1330 struct net_device
*net_dev
)
1332 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1333 struct bgmac_dma_ring
*ring
;
1335 /* No QOS support yet */
1336 ring
= &bgmac
->tx_ring
[0];
1337 return bgmac_dma_tx_add(bgmac
, ring
, skb
);
1340 static int bgmac_set_mac_address(struct net_device
*net_dev
, void *addr
)
1342 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1345 ret
= eth_prepare_mac_addr_change(net_dev
, addr
);
1348 bgmac_write_mac_address(bgmac
, (u8
*)addr
);
1349 eth_commit_mac_addr_change(net_dev
, addr
);
1353 static int bgmac_ioctl(struct net_device
*net_dev
, struct ifreq
*ifr
, int cmd
)
1355 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1357 if (!netif_running(net_dev
))
1360 return phy_mii_ioctl(bgmac
->phy_dev
, ifr
, cmd
);
1363 static const struct net_device_ops bgmac_netdev_ops
= {
1364 .ndo_open
= bgmac_open
,
1365 .ndo_stop
= bgmac_stop
,
1366 .ndo_start_xmit
= bgmac_start_xmit
,
1367 .ndo_set_rx_mode
= bgmac_set_rx_mode
,
1368 .ndo_set_mac_address
= bgmac_set_mac_address
,
1369 .ndo_validate_addr
= eth_validate_addr
,
1370 .ndo_do_ioctl
= bgmac_ioctl
,
1373 /**************************************************
1375 **************************************************/
1377 static int bgmac_get_settings(struct net_device
*net_dev
,
1378 struct ethtool_cmd
*cmd
)
1380 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1382 return phy_ethtool_gset(bgmac
->phy_dev
, cmd
);
1385 static int bgmac_set_settings(struct net_device
*net_dev
,
1386 struct ethtool_cmd
*cmd
)
1388 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1390 return phy_ethtool_sset(bgmac
->phy_dev
, cmd
);
1393 static void bgmac_get_drvinfo(struct net_device
*net_dev
,
1394 struct ethtool_drvinfo
*info
)
1396 strlcpy(info
->driver
, KBUILD_MODNAME
, sizeof(info
->driver
));
1397 strlcpy(info
->bus_info
, "BCMA", sizeof(info
->bus_info
));
1400 static const struct ethtool_ops bgmac_ethtool_ops
= {
1401 .get_settings
= bgmac_get_settings
,
1402 .set_settings
= bgmac_set_settings
,
1403 .get_drvinfo
= bgmac_get_drvinfo
,
1406 /**************************************************
1408 **************************************************/
1410 static int bgmac_mii_read(struct mii_bus
*bus
, int mii_id
, int regnum
)
1412 return bgmac_phy_read(bus
->priv
, mii_id
, regnum
);
1415 static int bgmac_mii_write(struct mii_bus
*bus
, int mii_id
, int regnum
,
1418 return bgmac_phy_write(bus
->priv
, mii_id
, regnum
, value
);
1421 static void bgmac_adjust_link(struct net_device
*net_dev
)
1423 struct bgmac
*bgmac
= netdev_priv(net_dev
);
1424 struct phy_device
*phy_dev
= bgmac
->phy_dev
;
1425 bool update
= false;
1427 if (phy_dev
->link
) {
1428 if (phy_dev
->speed
!= bgmac
->mac_speed
) {
1429 bgmac
->mac_speed
= phy_dev
->speed
;
1433 if (phy_dev
->duplex
!= bgmac
->mac_duplex
) {
1434 bgmac
->mac_duplex
= phy_dev
->duplex
;
1440 bgmac_mac_speed(bgmac
);
1441 phy_print_status(phy_dev
);
1445 static int bgmac_fixed_phy_register(struct bgmac
*bgmac
)
1447 struct fixed_phy_status fphy_status
= {
1449 .speed
= SPEED_1000
,
1450 .duplex
= DUPLEX_FULL
,
1452 struct phy_device
*phy_dev
;
1455 phy_dev
= fixed_phy_register(PHY_POLL
, &fphy_status
, -1, NULL
);
1456 if (!phy_dev
|| IS_ERR(phy_dev
)) {
1457 bgmac_err(bgmac
, "Failed to register fixed PHY device\n");
1461 err
= phy_connect_direct(bgmac
->net_dev
, phy_dev
, bgmac_adjust_link
,
1462 PHY_INTERFACE_MODE_MII
);
1464 bgmac_err(bgmac
, "Connecting PHY failed\n");
1468 bgmac
->phy_dev
= phy_dev
;
1473 static int bgmac_mii_register(struct bgmac
*bgmac
)
1475 struct bcma_chipinfo
*ci
= &bgmac
->core
->bus
->chipinfo
;
1476 struct mii_bus
*mii_bus
;
1477 struct phy_device
*phy_dev
;
1478 char bus_id
[MII_BUS_ID_SIZE
+ 3];
1481 if (ci
->id
== BCMA_CHIP_ID_BCM4707
||
1482 ci
->id
== BCMA_CHIP_ID_BCM53018
)
1483 return bgmac_fixed_phy_register(bgmac
);
1485 mii_bus
= mdiobus_alloc();
1489 mii_bus
->name
= "bgmac mii bus";
1490 sprintf(mii_bus
->id
, "%s-%d-%d", "bgmac", bgmac
->core
->bus
->num
,
1491 bgmac
->core
->core_unit
);
1492 mii_bus
->priv
= bgmac
;
1493 mii_bus
->read
= bgmac_mii_read
;
1494 mii_bus
->write
= bgmac_mii_write
;
1495 mii_bus
->parent
= &bgmac
->core
->dev
;
1496 mii_bus
->phy_mask
= ~(1 << bgmac
->phyaddr
);
1498 err
= mdiobus_register(mii_bus
);
1500 bgmac_err(bgmac
, "Registration of mii bus failed\n");
1504 bgmac
->mii_bus
= mii_bus
;
1506 /* Connect to the PHY */
1507 snprintf(bus_id
, sizeof(bus_id
), PHY_ID_FMT
, mii_bus
->id
,
1509 phy_dev
= phy_connect(bgmac
->net_dev
, bus_id
, &bgmac_adjust_link
,
1510 PHY_INTERFACE_MODE_MII
);
1511 if (IS_ERR(phy_dev
)) {
1512 bgmac_err(bgmac
, "PHY connecton failed\n");
1513 err
= PTR_ERR(phy_dev
);
1514 goto err_unregister_bus
;
1516 bgmac
->phy_dev
= phy_dev
;
1521 mdiobus_unregister(mii_bus
);
1523 mdiobus_free(mii_bus
);
1527 static void bgmac_mii_unregister(struct bgmac
*bgmac
)
1529 struct mii_bus
*mii_bus
= bgmac
->mii_bus
;
1531 mdiobus_unregister(mii_bus
);
1532 mdiobus_free(mii_bus
);
1535 /**************************************************
1537 **************************************************/
1539 /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipattach */
1540 static int bgmac_probe(struct bcma_device
*core
)
1542 struct bcma_chipinfo
*ci
= &core
->bus
->chipinfo
;
1543 struct net_device
*net_dev
;
1544 struct bgmac
*bgmac
;
1545 struct ssb_sprom
*sprom
= &core
->bus
->sprom
;
1549 switch (core
->core_unit
) {
1551 mac
= sprom
->et0mac
;
1554 mac
= sprom
->et1mac
;
1557 mac
= sprom
->et2mac
;
1560 pr_err("Unsupported core_unit %d\n", core
->core_unit
);
1564 if (!is_valid_ether_addr(mac
)) {
1565 dev_err(&core
->dev
, "Invalid MAC addr: %pM\n", mac
);
1566 eth_random_addr(mac
);
1567 dev_warn(&core
->dev
, "Using random MAC: %pM\n", mac
);
1570 /* Allocation and references */
1571 net_dev
= alloc_etherdev(sizeof(*bgmac
));
1574 net_dev
->netdev_ops
= &bgmac_netdev_ops
;
1575 net_dev
->irq
= core
->irq
;
1576 net_dev
->ethtool_ops
= &bgmac_ethtool_ops
;
1577 bgmac
= netdev_priv(net_dev
);
1578 bgmac
->net_dev
= net_dev
;
1580 bcma_set_drvdata(core
, bgmac
);
1583 memcpy(bgmac
->net_dev
->dev_addr
, mac
, ETH_ALEN
);
1585 /* On BCM4706 we need common core to access PHY */
1586 if (core
->id
.id
== BCMA_CORE_4706_MAC_GBIT
&&
1587 !core
->bus
->drv_gmac_cmn
.core
) {
1588 bgmac_err(bgmac
, "GMAC CMN core not found (required for BCM4706)\n");
1590 goto err_netdev_free
;
1592 bgmac
->cmn
= core
->bus
->drv_gmac_cmn
.core
;
1594 switch (core
->core_unit
) {
1596 bgmac
->phyaddr
= sprom
->et0phyaddr
;
1599 bgmac
->phyaddr
= sprom
->et1phyaddr
;
1602 bgmac
->phyaddr
= sprom
->et2phyaddr
;
1605 bgmac
->phyaddr
&= BGMAC_PHY_MASK
;
1606 if (bgmac
->phyaddr
== BGMAC_PHY_MASK
) {
1607 bgmac_err(bgmac
, "No PHY found\n");
1609 goto err_netdev_free
;
1611 bgmac_info(bgmac
, "Found PHY addr: %d%s\n", bgmac
->phyaddr
,
1612 bgmac
->phyaddr
== BGMAC_PHY_NOREGS
? " (NOREGS)" : "");
1614 if (core
->bus
->hosttype
== BCMA_HOSTTYPE_PCI
) {
1615 bgmac_err(bgmac
, "PCI setup not implemented\n");
1617 goto err_netdev_free
;
1620 bgmac_chip_reset(bgmac
);
1622 /* For Northstar, we have to take all GMAC core out of reset */
1623 if (ci
->id
== BCMA_CHIP_ID_BCM4707
||
1624 ci
->id
== BCMA_CHIP_ID_BCM53018
) {
1625 struct bcma_device
*ns_core
;
1628 /* Northstar has 4 GMAC cores */
1629 for (ns_gmac
= 0; ns_gmac
< 4; ns_gmac
++) {
1630 /* As Northstar requirement, we have to reset all GMACs
1631 * before accessing one. bgmac_chip_reset() call
1632 * bcma_core_enable() for this core. Then the other
1633 * three GMACs didn't reset. We do it here.
1635 ns_core
= bcma_find_core_unit(core
->bus
,
1638 if (ns_core
&& !bcma_core_is_enabled(ns_core
))
1639 bcma_core_enable(ns_core
, 0);
1643 err
= bgmac_dma_alloc(bgmac
);
1645 bgmac_err(bgmac
, "Unable to alloc memory for DMA\n");
1646 goto err_netdev_free
;
1649 bgmac
->int_mask
= BGMAC_IS_ERRMASK
| BGMAC_IS_RX
| BGMAC_IS_TX_MASK
;
1650 if (bcm47xx_nvram_getenv("et0_no_txint", NULL
, 0) == 0)
1651 bgmac
->int_mask
&= ~BGMAC_IS_TX_MASK
;
1653 /* TODO: reset the external phy. Specs are needed */
1654 bgmac_phy_reset(bgmac
);
1656 bgmac
->has_robosw
= !!(core
->bus
->sprom
.boardflags_lo
&
1657 BGMAC_BFL_ENETROBO
);
1658 if (bgmac
->has_robosw
)
1659 bgmac_warn(bgmac
, "Support for Roboswitch not implemented\n");
1661 if (core
->bus
->sprom
.boardflags_lo
& BGMAC_BFL_ENETADM
)
1662 bgmac_warn(bgmac
, "Support for ADMtek ethernet switch not implemented\n");
1664 netif_napi_add(net_dev
, &bgmac
->napi
, bgmac_poll
, BGMAC_WEIGHT
);
1666 err
= bgmac_mii_register(bgmac
);
1668 bgmac_err(bgmac
, "Cannot register MDIO\n");
1672 net_dev
->features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
;
1673 net_dev
->hw_features
= net_dev
->features
;
1674 net_dev
->vlan_features
= net_dev
->features
;
1676 err
= register_netdev(bgmac
->net_dev
);
1678 bgmac_err(bgmac
, "Cannot register net device\n");
1679 goto err_mii_unregister
;
1682 netif_carrier_off(net_dev
);
1687 bgmac_mii_unregister(bgmac
);
1689 bgmac_dma_free(bgmac
);
1692 bcma_set_drvdata(core
, NULL
);
1693 free_netdev(net_dev
);
1698 static void bgmac_remove(struct bcma_device
*core
)
1700 struct bgmac
*bgmac
= bcma_get_drvdata(core
);
1702 unregister_netdev(bgmac
->net_dev
);
1703 bgmac_mii_unregister(bgmac
);
1704 netif_napi_del(&bgmac
->napi
);
1705 bgmac_dma_free(bgmac
);
1706 bcma_set_drvdata(core
, NULL
);
1707 free_netdev(bgmac
->net_dev
);
1710 static struct bcma_driver bgmac_bcma_driver
= {
1711 .name
= KBUILD_MODNAME
,
1712 .id_table
= bgmac_bcma_tbl
,
1713 .probe
= bgmac_probe
,
1714 .remove
= bgmac_remove
,
1717 static int __init
bgmac_init(void)
1721 err
= bcma_driver_register(&bgmac_bcma_driver
);
1724 pr_info("Broadcom 47xx GBit MAC driver loaded\n");
1729 static void __exit
bgmac_exit(void)
1731 bcma_driver_unregister(&bgmac_bcma_driver
);
1734 module_init(bgmac_init
)
1735 module_exit(bgmac_exit
)
1737 MODULE_AUTHOR("Rafał Miłecki");
1738 MODULE_LICENSE("GPL");