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regulator: da9063: Add missing initialization of da9063_reg_matches
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 #include <linux/pci.h>
18 #include <linux/netdevice.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/types.h>
21 #include <linux/pci_regs.h>
22
23 /* compilation time flags */
24
25 /* define this to make the driver freeze on error to allow getting debug info
26 * (you will need to reboot afterwards) */
27 /* #define BNX2X_STOP_ON_ERROR */
28
29 #define DRV_MODULE_VERSION "1.78.17-0"
30 #define DRV_MODULE_RELDATE "2013/04/11"
31 #define BNX2X_BC_VER 0x040200
32
33 #if defined(CONFIG_DCB)
34 #define BCM_DCBNL
35 #endif
36
37 #include "bnx2x_hsi.h"
38
39 #include "../cnic_if.h"
40
41 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
42
43 #include <linux/mdio.h>
44
45 #include "bnx2x_reg.h"
46 #include "bnx2x_fw_defs.h"
47 #include "bnx2x_mfw_req.h"
48 #include "bnx2x_link.h"
49 #include "bnx2x_sp.h"
50 #include "bnx2x_dcb.h"
51 #include "bnx2x_stats.h"
52 #include "bnx2x_vfpf.h"
53
54 enum bnx2x_int_mode {
55 BNX2X_INT_MODE_MSIX,
56 BNX2X_INT_MODE_INTX,
57 BNX2X_INT_MODE_MSI
58 };
59
60 /* error/debug prints */
61
62 #define DRV_MODULE_NAME "bnx2x"
63
64 /* for messages that are currently off */
65 #define BNX2X_MSG_OFF 0x0
66 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
67 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
68 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
70 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
71 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
72 #define BNX2X_MSG_IOV 0x0800000
73 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
74 #define BNX2X_MSG_ETHTOOL 0x4000000
75 #define BNX2X_MSG_DCB 0x8000000
76
77 /* regular debug print */
78 #define DP(__mask, fmt, ...) \
79 do { \
80 if (unlikely(bp->msg_enable & (__mask))) \
81 pr_notice("[%s:%d(%s)]" fmt, \
82 __func__, __LINE__, \
83 bp->dev ? (bp->dev->name) : "?", \
84 ##__VA_ARGS__); \
85 } while (0)
86
87 #define DP_CONT(__mask, fmt, ...) \
88 do { \
89 if (unlikely(bp->msg_enable & (__mask))) \
90 pr_cont(fmt, ##__VA_ARGS__); \
91 } while (0)
92
93 /* errors debug print */
94 #define BNX2X_DBG_ERR(fmt, ...) \
95 do { \
96 if (unlikely(netif_msg_probe(bp))) \
97 pr_err("[%s:%d(%s)]" fmt, \
98 __func__, __LINE__, \
99 bp->dev ? (bp->dev->name) : "?", \
100 ##__VA_ARGS__); \
101 } while (0)
102
103 /* for errors (never masked) */
104 #define BNX2X_ERR(fmt, ...) \
105 do { \
106 pr_err("[%s:%d(%s)]" fmt, \
107 __func__, __LINE__, \
108 bp->dev ? (bp->dev->name) : "?", \
109 ##__VA_ARGS__); \
110 } while (0)
111
112 #define BNX2X_ERROR(fmt, ...) \
113 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
114
115 /* before we have a dev->name use dev_info() */
116 #define BNX2X_DEV_INFO(fmt, ...) \
117 do { \
118 if (unlikely(netif_msg_probe(bp))) \
119 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
120 } while (0)
121
122 /* Error handling */
123 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
124 #ifdef BNX2X_STOP_ON_ERROR
125 #define bnx2x_panic() \
126 do { \
127 bp->panic = 1; \
128 BNX2X_ERR("driver assert\n"); \
129 bnx2x_panic_dump(bp, true); \
130 } while (0)
131 #else
132 #define bnx2x_panic() \
133 do { \
134 bp->panic = 1; \
135 BNX2X_ERR("driver assert\n"); \
136 bnx2x_panic_dump(bp, false); \
137 } while (0)
138 #endif
139
140 #define bnx2x_mc_addr(ha) ((ha)->addr)
141 #define bnx2x_uc_addr(ha) ((ha)->addr)
142
143 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
144 #define U64_HI(x) ((u32)(((u64)(x)) >> 32))
145 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
146
147 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
148
149 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
150 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
151 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
152
153 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
154 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
155 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
156
157 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
158 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
159
160 #define REG_RD_DMAE(bp, offset, valp, len32) \
161 do { \
162 bnx2x_read_dmae(bp, offset, len32);\
163 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
164 } while (0)
165
166 #define REG_WR_DMAE(bp, offset, valp, len32) \
167 do { \
168 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
169 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
170 offset, len32); \
171 } while (0)
172
173 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
174 REG_WR_DMAE(bp, offset, valp, len32)
175
176 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
177 do { \
178 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
179 bnx2x_write_big_buf_wb(bp, addr, len32); \
180 } while (0)
181
182 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
183 offsetof(struct shmem_region, field))
184 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
185 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
186
187 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
188 offsetof(struct shmem2_region, field))
189 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
190 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
191 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
192 offsetof(struct mf_cfg, field))
193 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
194 offsetof(struct mf2_cfg, field))
195
196 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
197 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
198 MF_CFG_ADDR(bp, field), (val))
199 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
200
201 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
202 (SHMEM2_RD((bp), size) > \
203 offsetof(struct shmem2_region, field)))
204
205 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
206 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
207
208 /* SP SB indices */
209
210 /* General SP events - stats query, cfc delete, etc */
211 #define HC_SP_INDEX_ETH_DEF_CONS 3
212
213 /* EQ completions */
214 #define HC_SP_INDEX_EQ_CONS 7
215
216 /* FCoE L2 connection completions */
217 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
218 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
219 /* iSCSI L2 */
220 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
221 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
222
223 /* Special clients parameters */
224
225 /* SB indices */
226 /* FCoE L2 */
227 #define BNX2X_FCOE_L2_RX_INDEX \
228 (&bp->def_status_blk->sp_sb.\
229 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
230
231 #define BNX2X_FCOE_L2_TX_INDEX \
232 (&bp->def_status_blk->sp_sb.\
233 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
234
235 /**
236 * CIDs and CLIDs:
237 * CLIDs below is a CLID for func 0, then the CLID for other
238 * functions will be calculated by the formula:
239 *
240 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
241 *
242 */
243 enum {
244 BNX2X_ISCSI_ETH_CL_ID_IDX,
245 BNX2X_FCOE_ETH_CL_ID_IDX,
246 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
247 };
248
249 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
250 (bp)->max_cos)
251 /* iSCSI L2 */
252 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
253 /* FCoE L2 */
254 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
255
256 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
257 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
258 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
259 #define FCOE_INIT(bp) ((bp)->fcoe_init)
260
261 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
262 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
263
264 #define SM_RX_ID 0
265 #define SM_TX_ID 1
266
267 /* defines for multiple tx priority indices */
268 #define FIRST_TX_ONLY_COS_INDEX 1
269 #define FIRST_TX_COS_INDEX 0
270
271 /* rules for calculating the cids of tx-only connections */
272 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
273 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
274 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
275
276 /* fp index inside class of service range */
277 #define FP_COS_TO_TXQ(fp, cos, bp) \
278 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
279
280 /* Indexes for transmission queues array:
281 * txdata for RSS i CoS j is at location i + (j * num of RSS)
282 * txdata for FCoE (if exist) is at location max cos * num of RSS
283 * txdata for FWD (if exist) is one location after FCoE
284 * txdata for OOO (if exist) is one location after FWD
285 */
286 enum {
287 FCOE_TXQ_IDX_OFFSET,
288 FWD_TXQ_IDX_OFFSET,
289 OOO_TXQ_IDX_OFFSET,
290 };
291 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
292 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
293
294 /* fast path */
295 /*
296 * This driver uses new build_skb() API :
297 * RX ring buffer contains pointer to kmalloc() data only,
298 * skb are built only after Hardware filled the frame.
299 */
300 struct sw_rx_bd {
301 u8 *data;
302 DEFINE_DMA_UNMAP_ADDR(mapping);
303 };
304
305 struct sw_tx_bd {
306 struct sk_buff *skb;
307 u16 first_bd;
308 u8 flags;
309 /* Set on the first BD descriptor when there is a split BD */
310 #define BNX2X_TSO_SPLIT_BD (1<<0)
311 };
312
313 struct sw_rx_page {
314 struct page *page;
315 DEFINE_DMA_UNMAP_ADDR(mapping);
316 };
317
318 union db_prod {
319 struct doorbell_set_prod data;
320 u32 raw;
321 };
322
323 /* dropless fc FW/HW related params */
324 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
325 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
326 ETH_MAX_AGGREGATION_QUEUES_E1 :\
327 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
328 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
329 #define FW_PREFETCH_CNT 16
330 #define DROPLESS_FC_HEADROOM 100
331
332 /* MC hsi */
333 #define BCM_PAGE_SHIFT 12
334 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
335 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
336 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
337
338 #define PAGES_PER_SGE_SHIFT 0
339 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
340 #define SGE_PAGE_SIZE PAGE_SIZE
341 #define SGE_PAGE_SHIFT PAGE_SHIFT
342 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
343 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
344 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
345 SGE_PAGES), 0xffff)
346
347 /* SGE ring related macros */
348 #define NUM_RX_SGE_PAGES 2
349 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
350 #define NEXT_PAGE_SGE_DESC_CNT 2
351 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
352 /* RX_SGE_CNT is promised to be a power of 2 */
353 #define RX_SGE_MASK (RX_SGE_CNT - 1)
354 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
355 #define MAX_RX_SGE (NUM_RX_SGE - 1)
356 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
357 (MAX_RX_SGE_CNT - 1)) ? \
358 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
359 (x) + 1)
360 #define RX_SGE(x) ((x) & MAX_RX_SGE)
361
362 /*
363 * Number of required SGEs is the sum of two:
364 * 1. Number of possible opened aggregations (next packet for
365 * these aggregations will probably consume SGE immediately)
366 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
367 * after placement on BD for new TPA aggregation)
368 *
369 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
370 */
371 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
372 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
373 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
374 MAX_RX_SGE_CNT)
375 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
376 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
377 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
378
379 /* Manipulate a bit vector defined as an array of u64 */
380
381 /* Number of bits in one sge_mask array element */
382 #define BIT_VEC64_ELEM_SZ 64
383 #define BIT_VEC64_ELEM_SHIFT 6
384 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
385
386 #define __BIT_VEC64_SET_BIT(el, bit) \
387 do { \
388 el = ((el) | ((u64)0x1 << (bit))); \
389 } while (0)
390
391 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
392 do { \
393 el = ((el) & (~((u64)0x1 << (bit)))); \
394 } while (0)
395
396 #define BIT_VEC64_SET_BIT(vec64, idx) \
397 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
398 (idx) & BIT_VEC64_ELEM_MASK)
399
400 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
401 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
402 (idx) & BIT_VEC64_ELEM_MASK)
403
404 #define BIT_VEC64_TEST_BIT(vec64, idx) \
405 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
406 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
407
408 /* Creates a bitmask of all ones in less significant bits.
409 idx - index of the most significant bit in the created mask */
410 #define BIT_VEC64_ONES_MASK(idx) \
411 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
412 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
413
414 /*******************************************************/
415
416 /* Number of u64 elements in SGE mask array */
417 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
418 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
419 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
420
421 union host_hc_status_block {
422 /* pointer to fp status block e1x */
423 struct host_hc_status_block_e1x *e1x_sb;
424 /* pointer to fp status block e2 */
425 struct host_hc_status_block_e2 *e2_sb;
426 };
427
428 struct bnx2x_agg_info {
429 /*
430 * First aggregation buffer is a data buffer, the following - are pages.
431 * We will preallocate the data buffer for each aggregation when
432 * we open the interface and will replace the BD at the consumer
433 * with this one when we receive the TPA_START CQE in order to
434 * keep the Rx BD ring consistent.
435 */
436 struct sw_rx_bd first_buf;
437 u8 tpa_state;
438 #define BNX2X_TPA_START 1
439 #define BNX2X_TPA_STOP 2
440 #define BNX2X_TPA_ERROR 3
441 u8 placement_offset;
442 u16 parsing_flags;
443 u16 vlan_tag;
444 u16 len_on_bd;
445 u32 rxhash;
446 bool l4_rxhash;
447 u16 gro_size;
448 u16 full_page;
449 };
450
451 #define Q_STATS_OFFSET32(stat_name) \
452 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
453
454 struct bnx2x_fp_txdata {
455
456 struct sw_tx_bd *tx_buf_ring;
457
458 union eth_tx_bd_types *tx_desc_ring;
459 dma_addr_t tx_desc_mapping;
460
461 u32 cid;
462
463 union db_prod tx_db;
464
465 u16 tx_pkt_prod;
466 u16 tx_pkt_cons;
467 u16 tx_bd_prod;
468 u16 tx_bd_cons;
469
470 unsigned long tx_pkt;
471
472 __le16 *tx_cons_sb;
473
474 int txq_index;
475 struct bnx2x_fastpath *parent_fp;
476 int tx_ring_size;
477 };
478
479 enum bnx2x_tpa_mode_t {
480 TPA_MODE_LRO,
481 TPA_MODE_GRO
482 };
483
484 struct bnx2x_fastpath {
485 struct bnx2x *bp; /* parent */
486
487 struct napi_struct napi;
488
489 #ifdef CONFIG_NET_RX_BUSY_POLL
490 unsigned int state;
491 #define BNX2X_FP_STATE_IDLE 0
492 #define BNX2X_FP_STATE_NAPI (1 << 0) /* NAPI owns this FP */
493 #define BNX2X_FP_STATE_POLL (1 << 1) /* poll owns this FP */
494 #define BNX2X_FP_STATE_NAPI_YIELD (1 << 2) /* NAPI yielded this FP */
495 #define BNX2X_FP_STATE_POLL_YIELD (1 << 3) /* poll yielded this FP */
496 #define BNX2X_FP_YIELD (BNX2X_FP_STATE_NAPI_YIELD | BNX2X_FP_STATE_POLL_YIELD)
497 #define BNX2X_FP_LOCKED (BNX2X_FP_STATE_NAPI | BNX2X_FP_STATE_POLL)
498 #define BNX2X_FP_USER_PEND (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_POLL_YIELD)
499 /* protect state */
500 spinlock_t lock;
501 #endif /* CONFIG_NET_RX_BUSY_POLL */
502
503 union host_hc_status_block status_blk;
504 /* chip independent shortcuts into sb structure */
505 __le16 *sb_index_values;
506 __le16 *sb_running_index;
507 /* chip independent shortcut into rx_prods_offset memory */
508 u32 ustorm_rx_prods_offset;
509
510 u32 rx_buf_size;
511 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
512 dma_addr_t status_blk_mapping;
513
514 enum bnx2x_tpa_mode_t mode;
515
516 u8 max_cos; /* actual number of active tx coses */
517 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
518
519 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
520 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
521
522 struct eth_rx_bd *rx_desc_ring;
523 dma_addr_t rx_desc_mapping;
524
525 union eth_rx_cqe *rx_comp_ring;
526 dma_addr_t rx_comp_mapping;
527
528 /* SGE ring */
529 struct eth_rx_sge *rx_sge_ring;
530 dma_addr_t rx_sge_mapping;
531
532 u64 sge_mask[RX_SGE_MASK_LEN];
533
534 u32 cid;
535
536 __le16 fp_hc_idx;
537
538 u8 index; /* number in fp array */
539 u8 rx_queue; /* index for skb_record */
540 u8 cl_id; /* eth client id */
541 u8 cl_qzone_id;
542 u8 fw_sb_id; /* status block number in FW */
543 u8 igu_sb_id; /* status block number in HW */
544
545 u16 rx_bd_prod;
546 u16 rx_bd_cons;
547 u16 rx_comp_prod;
548 u16 rx_comp_cons;
549 u16 rx_sge_prod;
550 /* The last maximal completed SGE */
551 u16 last_max_sge;
552 __le16 *rx_cons_sb;
553 unsigned long rx_pkt,
554 rx_calls;
555
556 /* TPA related */
557 struct bnx2x_agg_info *tpa_info;
558 u8 disable_tpa;
559 #ifdef BNX2X_STOP_ON_ERROR
560 u64 tpa_queue_used;
561 #endif
562 /* The size is calculated using the following:
563 sizeof name field from netdev structure +
564 4 ('-Xx-' string) +
565 4 (for the digits and to make it DWORD aligned) */
566 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
567 char name[FP_NAME_SIZE];
568 };
569
570 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
571 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
572 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
573 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
574
575 #ifdef CONFIG_NET_RX_BUSY_POLL
576 static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
577 {
578 spin_lock_init(&fp->lock);
579 fp->state = BNX2X_FP_STATE_IDLE;
580 }
581
582 /* called from the device poll routine to get ownership of a FP */
583 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
584 {
585 bool rc = true;
586
587 spin_lock(&fp->lock);
588 if (fp->state & BNX2X_FP_LOCKED) {
589 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI);
590 fp->state |= BNX2X_FP_STATE_NAPI_YIELD;
591 rc = false;
592 } else {
593 /* we don't care if someone yielded */
594 fp->state = BNX2X_FP_STATE_NAPI;
595 }
596 spin_unlock(&fp->lock);
597 return rc;
598 }
599
600 /* returns true is someone tried to get the FP while napi had it */
601 static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
602 {
603 bool rc = false;
604
605 spin_lock(&fp->lock);
606 WARN_ON(fp->state &
607 (BNX2X_FP_STATE_POLL | BNX2X_FP_STATE_NAPI_YIELD));
608
609 if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
610 rc = true;
611 fp->state = BNX2X_FP_STATE_IDLE;
612 spin_unlock(&fp->lock);
613 return rc;
614 }
615
616 /* called from bnx2x_low_latency_poll() */
617 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
618 {
619 bool rc = true;
620
621 spin_lock_bh(&fp->lock);
622 if ((fp->state & BNX2X_FP_LOCKED)) {
623 fp->state |= BNX2X_FP_STATE_POLL_YIELD;
624 rc = false;
625 } else {
626 /* preserve yield marks */
627 fp->state |= BNX2X_FP_STATE_POLL;
628 }
629 spin_unlock_bh(&fp->lock);
630 return rc;
631 }
632
633 /* returns true if someone tried to get the FP while it was locked */
634 static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
635 {
636 bool rc = false;
637
638 spin_lock_bh(&fp->lock);
639 WARN_ON(fp->state & BNX2X_FP_STATE_NAPI);
640
641 if (fp->state & BNX2X_FP_STATE_POLL_YIELD)
642 rc = true;
643 fp->state = BNX2X_FP_STATE_IDLE;
644 spin_unlock_bh(&fp->lock);
645 return rc;
646 }
647
648 /* true if a socket is polling, even if it did not get the lock */
649 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
650 {
651 WARN_ON(!(fp->state & BNX2X_FP_LOCKED));
652 return fp->state & BNX2X_FP_USER_PEND;
653 }
654 #else
655 static inline void bnx2x_fp_init_lock(struct bnx2x_fastpath *fp)
656 {
657 }
658
659 static inline bool bnx2x_fp_lock_napi(struct bnx2x_fastpath *fp)
660 {
661 return true;
662 }
663
664 static inline bool bnx2x_fp_unlock_napi(struct bnx2x_fastpath *fp)
665 {
666 return false;
667 }
668
669 static inline bool bnx2x_fp_lock_poll(struct bnx2x_fastpath *fp)
670 {
671 return false;
672 }
673
674 static inline bool bnx2x_fp_unlock_poll(struct bnx2x_fastpath *fp)
675 {
676 return false;
677 }
678
679 static inline bool bnx2x_fp_ll_polling(struct bnx2x_fastpath *fp)
680 {
681 return false;
682 }
683 #endif /* CONFIG_NET_RX_BUSY_POLL */
684
685 /* Use 2500 as a mini-jumbo MTU for FCoE */
686 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
687
688 #define FCOE_IDX_OFFSET 0
689
690 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
691 FCOE_IDX_OFFSET)
692 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
693 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
694 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
695 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
696 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
697 txdata_ptr[FIRST_TX_COS_INDEX] \
698 ->var)
699
700 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
701 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
702 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
703
704 /* MC hsi */
705 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
706 #define RX_COPY_THRESH 92
707
708 #define NUM_TX_RINGS 16
709 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
710 #define NEXT_PAGE_TX_DESC_CNT 1
711 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
712 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
713 #define MAX_TX_BD (NUM_TX_BD - 1)
714 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
715 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
716 (MAX_TX_DESC_CNT - 1)) ? \
717 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
718 (x) + 1)
719 #define TX_BD(x) ((x) & MAX_TX_BD)
720 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
721
722 /* number of NEXT_PAGE descriptors may be required during placement */
723 #define NEXT_CNT_PER_TX_PKT(bds) \
724 (((bds) + MAX_TX_DESC_CNT - 1) / \
725 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
726 /* max BDs per tx packet w/o next_pages:
727 * START_BD - describes packed
728 * START_BD(splitted) - includes unpaged data segment for GSO
729 * PARSING_BD - for TSO and CSUM data
730 * PARSING_BD2 - for encapsulation data
731 * Frag BDs - describes pages for frags
732 */
733 #define BDS_PER_TX_PKT 4
734 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
735 /* max BDs per tx packet including next pages */
736 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
737 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
738
739 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
740 #define NUM_RX_RINGS 8
741 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
742 #define NEXT_PAGE_RX_DESC_CNT 2
743 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
744 #define RX_DESC_MASK (RX_DESC_CNT - 1)
745 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
746 #define MAX_RX_BD (NUM_RX_BD - 1)
747 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
748
749 /* dropless fc calculations for BDs
750 *
751 * Number of BDs should as number of buffers in BRB:
752 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
753 * "next" elements on each page
754 */
755 #define NUM_BD_REQ BRB_SIZE(bp)
756 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
757 MAX_RX_DESC_CNT)
758 #define BD_TH_LO(bp) (NUM_BD_REQ + \
759 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
760 FW_DROP_LEVEL(bp))
761 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
762
763 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
764
765 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
766 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
767 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
768 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
769 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
770 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
771 MIN_RX_AVAIL))
772
773 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
774 (MAX_RX_DESC_CNT - 1)) ? \
775 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
776 (x) + 1)
777 #define RX_BD(x) ((x) & MAX_RX_BD)
778
779 /*
780 * As long as CQE is X times bigger than BD entry we have to allocate X times
781 * more pages for CQ ring in order to keep it balanced with BD ring
782 */
783 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
784 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
785 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
786 #define NEXT_PAGE_RCQ_DESC_CNT 1
787 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
788 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
789 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
790 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
791 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
792 (MAX_RCQ_DESC_CNT - 1)) ? \
793 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
794 (x) + 1)
795 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
796
797 /* dropless fc calculations for RCQs
798 *
799 * Number of RCQs should be as number of buffers in BRB:
800 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
801 * "next" elements on each page
802 */
803 #define NUM_RCQ_REQ BRB_SIZE(bp)
804 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
805 MAX_RCQ_DESC_CNT)
806 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
807 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
808 FW_DROP_LEVEL(bp))
809 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
810
811 /* This is needed for determining of last_max */
812 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
813 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
814
815 #define BNX2X_SWCID_SHIFT 17
816 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
817
818 /* used on a CID received from the HW */
819 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
820 #define CQE_CMD(x) (le32_to_cpu(x) >> \
821 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
822
823 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
824 le32_to_cpu((bd)->addr_lo))
825 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
826
827 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
828 #define BNX2X_DB_SHIFT 3 /* 8 bytes*/
829 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
830 #error "Min DB doorbell stride is 8"
831 #endif
832 #define DOORBELL(bp, cid, val) \
833 do { \
834 writel((u32)(val), bp->doorbells + (bp->db_size * (cid))); \
835 } while (0)
836
837 /* TX CSUM helpers */
838 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
839 skb->csum_offset)
840 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
841 skb->csum_offset))
842
843 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
844
845 #define XMIT_PLAIN 0
846 #define XMIT_CSUM_V4 (1 << 0)
847 #define XMIT_CSUM_V6 (1 << 1)
848 #define XMIT_CSUM_TCP (1 << 2)
849 #define XMIT_GSO_V4 (1 << 3)
850 #define XMIT_GSO_V6 (1 << 4)
851 #define XMIT_CSUM_ENC_V4 (1 << 5)
852 #define XMIT_CSUM_ENC_V6 (1 << 6)
853 #define XMIT_GSO_ENC_V4 (1 << 7)
854 #define XMIT_GSO_ENC_V6 (1 << 8)
855
856 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
857 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
858
859 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
860 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
861
862 /* stuff added to make the code fit 80Col */
863 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
864 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
865 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
866 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
867 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
868
869 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
870
871 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
872 (((le16_to_cpu(flags) & \
873 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
874 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
875 == PRS_FLAG_OVERETH_IPV4)
876 #define BNX2X_RX_SUM_FIX(cqe) \
877 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
878
879 #define FP_USB_FUNC_OFF \
880 offsetof(struct cstorm_status_block_u, func)
881 #define FP_CSB_FUNC_OFF \
882 offsetof(struct cstorm_status_block_c, func)
883
884 #define HC_INDEX_ETH_RX_CQ_CONS 1
885
886 #define HC_INDEX_OOO_TX_CQ_CONS 4
887
888 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
889
890 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
891
892 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
893
894 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
895
896 #define BNX2X_RX_SB_INDEX \
897 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
898
899 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
900
901 #define BNX2X_TX_SB_INDEX_COS0 \
902 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
903
904 /* end of fast path */
905
906 /* common */
907
908 struct bnx2x_common {
909
910 u32 chip_id;
911 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
912 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
913
914 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
915 #define CHIP_NUM_57710 0x164e
916 #define CHIP_NUM_57711 0x164f
917 #define CHIP_NUM_57711E 0x1650
918 #define CHIP_NUM_57712 0x1662
919 #define CHIP_NUM_57712_MF 0x1663
920 #define CHIP_NUM_57712_VF 0x166f
921 #define CHIP_NUM_57713 0x1651
922 #define CHIP_NUM_57713E 0x1652
923 #define CHIP_NUM_57800 0x168a
924 #define CHIP_NUM_57800_MF 0x16a5
925 #define CHIP_NUM_57800_VF 0x16a9
926 #define CHIP_NUM_57810 0x168e
927 #define CHIP_NUM_57810_MF 0x16ae
928 #define CHIP_NUM_57810_VF 0x16af
929 #define CHIP_NUM_57811 0x163d
930 #define CHIP_NUM_57811_MF 0x163e
931 #define CHIP_NUM_57811_VF 0x163f
932 #define CHIP_NUM_57840_OBSOLETE 0x168d
933 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
934 #define CHIP_NUM_57840_4_10 0x16a1
935 #define CHIP_NUM_57840_2_20 0x16a2
936 #define CHIP_NUM_57840_MF 0x16a4
937 #define CHIP_NUM_57840_VF 0x16ad
938 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
939 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
940 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
941 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
942 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
943 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
944 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
945 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
946 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
947 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
948 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
949 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
950 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
951 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
952 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
953 #define CHIP_IS_57840(bp) \
954 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
955 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
956 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
957 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
958 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
959 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
960 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
961 CHIP_IS_57711E(bp))
962 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
963 CHIP_IS_57811_MF(bp) || \
964 CHIP_IS_57811_VF(bp))
965 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
966 CHIP_IS_57712_MF(bp) || \
967 CHIP_IS_57712_VF(bp))
968 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
969 CHIP_IS_57800_MF(bp) || \
970 CHIP_IS_57800_VF(bp) || \
971 CHIP_IS_57810(bp) || \
972 CHIP_IS_57810_MF(bp) || \
973 CHIP_IS_57810_VF(bp) || \
974 CHIP_IS_57811xx(bp) || \
975 CHIP_IS_57840(bp) || \
976 CHIP_IS_57840_MF(bp) || \
977 CHIP_IS_57840_VF(bp))
978 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
979 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
980 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
981
982 #define CHIP_REV_SHIFT 12
983 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
984 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
985 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
986 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
987 /* assume maximum 5 revisions */
988 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
989 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
990 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
991 !(CHIP_REV_VAL(bp) & 0x00001000))
992 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
993 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
994 (CHIP_REV_VAL(bp) & 0x00001000))
995
996 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
997 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
998
999 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
1000 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
1001 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
1002 (CHIP_REV_SHIFT + 1)) \
1003 << CHIP_REV_SHIFT)
1004 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
1005 CHIP_REV_SIM(bp) :\
1006 CHIP_REV_VAL(bp))
1007 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
1008 (CHIP_REV(bp) == CHIP_REV_Bx))
1009 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
1010 (CHIP_REV(bp) == CHIP_REV_Ax))
1011 /* This define is used in two main places:
1012 * 1. In the early stages of nic_load, to know if to configure Parser / Searcher
1013 * to nic-only mode or to offload mode. Offload mode is configured if either the
1014 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
1015 * registered for this port (which means that the user wants storage services).
1016 * 2. During cnic-related load, to know if offload mode is already configured in
1017 * the HW or needs to be configured.
1018 * Since the transition from nic-mode to offload-mode in HW causes traffic
1019 * corruption, nic-mode is configured only in ports on which storage services
1020 * where never requested.
1021 */
1022 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
1023
1024 int flash_size;
1025 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
1026 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
1027 #define BNX2X_NVRAM_PAGE_SIZE 256
1028
1029 u32 shmem_base;
1030 u32 shmem2_base;
1031 u32 mf_cfg_base;
1032 u32 mf2_cfg_base;
1033
1034 u32 hw_config;
1035
1036 u32 bc_ver;
1037
1038 u8 int_block;
1039 #define INT_BLOCK_HC 0
1040 #define INT_BLOCK_IGU 1
1041 #define INT_BLOCK_MODE_NORMAL 0
1042 #define INT_BLOCK_MODE_BW_COMP 2
1043 #define CHIP_INT_MODE_IS_NBC(bp) \
1044 (!CHIP_IS_E1x(bp) && \
1045 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
1046 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
1047
1048 u8 chip_port_mode;
1049 #define CHIP_4_PORT_MODE 0x0
1050 #define CHIP_2_PORT_MODE 0x1
1051 #define CHIP_PORT_MODE_NONE 0x2
1052 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
1053 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
1054
1055 u32 boot_mode;
1056 };
1057
1058 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
1059 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
1060 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
1061
1062 #define MAX_IGU_ATTN_ACK_TO 100
1063 /* end of common */
1064
1065 /* port */
1066
1067 struct bnx2x_port {
1068 u32 pmf;
1069
1070 u32 link_config[LINK_CONFIG_SIZE];
1071
1072 u32 supported[LINK_CONFIG_SIZE];
1073 /* link settings - missing defines */
1074 #define SUPPORTED_2500baseX_Full (1 << 15)
1075
1076 u32 advertising[LINK_CONFIG_SIZE];
1077 /* link settings - missing defines */
1078 #define ADVERTISED_2500baseX_Full (1 << 15)
1079
1080 u32 phy_addr;
1081
1082 /* used to synchronize phy accesses */
1083 struct mutex phy_mutex;
1084
1085 u32 port_stx;
1086
1087 struct nig_stats old_nig_stats;
1088 };
1089
1090 /* end of port */
1091
1092 #define STATS_OFFSET32(stat_name) \
1093 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
1094
1095 /* slow path */
1096
1097 /* slow path work-queue */
1098 extern struct workqueue_struct *bnx2x_wq;
1099
1100 #define BNX2X_MAX_NUM_OF_VFS 64
1101 #define BNX2X_VF_CID_WND 4 /* log num of queues per VF. HW config. */
1102 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
1103
1104 /* We need to reserve doorbell addresses for all VF and queue combinations */
1105 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
1106
1107 /* The doorbell is configured to have the same number of CIDs for PFs and for
1108 * VFs. For this reason the PF CID zone is as large as the VF zone.
1109 */
1110 #define BNX2X_FIRST_VF_CID BNX2X_VF_CIDS
1111 #define BNX2X_MAX_NUM_VF_QUEUES 64
1112 #define BNX2X_VF_ID_INVALID 0xFF
1113
1114 /* the number of VF CIDS multiplied by the amount of bytes reserved for each
1115 * cid must not exceed the size of the VF doorbell
1116 */
1117 #define BNX2X_VF_BAR_SIZE 512
1118 #if (BNX2X_VF_BAR_SIZE < BNX2X_CIDS_PER_VF * (1 << BNX2X_DB_SHIFT))
1119 #error "VF doorbell bar size is 512"
1120 #endif
1121
1122 /*
1123 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1124 * control by the number of fast-path status blocks supported by the
1125 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1126 * status block represents an independent interrupts context that can
1127 * serve a regular L2 networking queue. However special L2 queues such
1128 * as the FCoE queue do not require a FP-SB and other components like
1129 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1130 *
1131 * If the maximum number of FP-SB available is X then:
1132 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1133 * regular L2 queues is Y=X-1
1134 * b. In MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1135 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1136 * is Y+1
1137 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1138 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1139 * FP interrupt context for the CNIC).
1140 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1141 * L2 queue is supported. The cid for the FCoE L2 queue is always X.
1142 */
1143
1144 /* fast-path interrupt contexts E1x */
1145 #define FP_SB_MAX_E1x 16
1146 /* fast-path interrupt contexts E2 */
1147 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1148
1149 union cdu_context {
1150 struct eth_context eth;
1151 char pad[1024];
1152 };
1153
1154 /* CDU host DB constants */
1155 #define CDU_ILT_PAGE_SZ_HW 2
1156 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1157 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1158
1159 #define CNIC_ISCSI_CID_MAX 256
1160 #define CNIC_FCOE_CID_MAX 2048
1161 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1162 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1163
1164 #define QM_ILT_PAGE_SZ_HW 0
1165 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1166 #define QM_CID_ROUND 1024
1167
1168 /* TM (timers) host DB constants */
1169 #define TM_ILT_PAGE_SZ_HW 0
1170 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1171 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1172 #define TM_CONN_NUM 1024
1173 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1174 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1175
1176 /* SRC (Searcher) host DB constants */
1177 #define SRC_ILT_PAGE_SZ_HW 0
1178 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1179 #define SRC_HASH_BITS 10
1180 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1181 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1182 #define SRC_T2_SZ SRC_ILT_SZ
1183 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1184
1185 #define MAX_DMAE_C 8
1186
1187 /* DMA memory not used in fastpath */
1188 struct bnx2x_slowpath {
1189 union {
1190 struct mac_configuration_cmd e1x;
1191 struct eth_classify_rules_ramrod_data e2;
1192 } mac_rdata;
1193
1194 union {
1195 struct tstorm_eth_mac_filter_config e1x;
1196 struct eth_filter_rules_ramrod_data e2;
1197 } rx_mode_rdata;
1198
1199 union {
1200 struct mac_configuration_cmd e1;
1201 struct eth_multicast_rules_ramrod_data e2;
1202 } mcast_rdata;
1203
1204 struct eth_rss_update_ramrod_data rss_rdata;
1205
1206 /* Queue State related ramrods are always sent under rtnl_lock */
1207 union {
1208 struct client_init_ramrod_data init_data;
1209 struct client_update_ramrod_data update_data;
1210 } q_rdata;
1211
1212 union {
1213 struct function_start_data func_start;
1214 /* pfc configuration for DCBX ramrod */
1215 struct flow_control_configuration pfc_config;
1216 } func_rdata;
1217
1218 /* afex ramrod can not be a part of func_rdata union because these
1219 * events might arrive in parallel to other events from func_rdata.
1220 * Therefore, if they would have been defined in the same union,
1221 * data can get corrupted.
1222 */
1223 struct afex_vif_list_ramrod_data func_afex_rdata;
1224
1225 /* used by dmae command executer */
1226 struct dmae_command dmae[MAX_DMAE_C];
1227
1228 u32 stats_comp;
1229 union mac_stats mac_stats;
1230 struct nig_stats nig_stats;
1231 struct host_port_stats port_stats;
1232 struct host_func_stats func_stats;
1233
1234 u32 wb_comp;
1235 u32 wb_data[4];
1236
1237 union drv_info_to_mcp drv_info_to_mcp;
1238 };
1239
1240 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1241 #define bnx2x_sp_mapping(bp, var) \
1242 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1243
1244 /* attn group wiring */
1245 #define MAX_DYNAMIC_ATTN_GRPS 8
1246
1247 struct attn_route {
1248 u32 sig[5];
1249 };
1250
1251 struct iro {
1252 u32 base;
1253 u16 m1;
1254 u16 m2;
1255 u16 m3;
1256 u16 size;
1257 };
1258
1259 struct hw_context {
1260 union cdu_context *vcxt;
1261 dma_addr_t cxt_mapping;
1262 size_t size;
1263 };
1264
1265 /* forward */
1266 struct bnx2x_ilt;
1267
1268 struct bnx2x_vfdb;
1269
1270 enum bnx2x_recovery_state {
1271 BNX2X_RECOVERY_DONE,
1272 BNX2X_RECOVERY_INIT,
1273 BNX2X_RECOVERY_WAIT,
1274 BNX2X_RECOVERY_FAILED,
1275 BNX2X_RECOVERY_NIC_LOADING
1276 };
1277
1278 /*
1279 * Event queue (EQ or event ring) MC hsi
1280 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1281 */
1282 #define NUM_EQ_PAGES 1
1283 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1284 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1285 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1286 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1287 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1288
1289 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1290 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1291 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1292
1293 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1294 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1295
1296 #define BNX2X_EQ_INDEX \
1297 (&bp->def_status_blk->sp_sb.\
1298 index_values[HC_SP_INDEX_EQ_CONS])
1299
1300 /* This is a data that will be used to create a link report message.
1301 * We will keep the data used for the last link report in order
1302 * to prevent reporting the same link parameters twice.
1303 */
1304 struct bnx2x_link_report_data {
1305 u16 line_speed; /* Effective line speed */
1306 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1307 };
1308
1309 enum {
1310 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1311 BNX2X_LINK_REPORT_LINK_DOWN,
1312 BNX2X_LINK_REPORT_RX_FC_ON,
1313 BNX2X_LINK_REPORT_TX_FC_ON,
1314 };
1315
1316 enum {
1317 BNX2X_PORT_QUERY_IDX,
1318 BNX2X_PF_QUERY_IDX,
1319 BNX2X_FCOE_QUERY_IDX,
1320 BNX2X_FIRST_QUEUE_QUERY_IDX,
1321 };
1322
1323 struct bnx2x_fw_stats_req {
1324 struct stats_query_header hdr;
1325 struct stats_query_entry query[FP_SB_MAX_E1x+
1326 BNX2X_FIRST_QUEUE_QUERY_IDX];
1327 };
1328
1329 struct bnx2x_fw_stats_data {
1330 struct stats_counter storm_counters;
1331 struct per_port_stats port;
1332 struct per_pf_stats pf;
1333 struct fcoe_statistics_params fcoe;
1334 struct per_queue_stats queue_stats[1];
1335 };
1336
1337 /* Public slow path states */
1338 enum {
1339 BNX2X_SP_RTNL_SETUP_TC,
1340 BNX2X_SP_RTNL_TX_TIMEOUT,
1341 BNX2X_SP_RTNL_FAN_FAILURE,
1342 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1343 BNX2X_SP_RTNL_ENABLE_SRIOV,
1344 BNX2X_SP_RTNL_VFPF_MCAST,
1345 BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN,
1346 BNX2X_SP_RTNL_RX_MODE,
1347 BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1348 BNX2X_SP_RTNL_TX_STOP,
1349 BNX2X_SP_RTNL_TX_RESUME,
1350 };
1351
1352 struct bnx2x_prev_path_list {
1353 struct list_head list;
1354 u8 bus;
1355 u8 slot;
1356 u8 path;
1357 u8 aer;
1358 u8 undi;
1359 };
1360
1361 struct bnx2x_sp_objs {
1362 /* MACs object */
1363 struct bnx2x_vlan_mac_obj mac_obj;
1364
1365 /* Queue State object */
1366 struct bnx2x_queue_sp_obj q_obj;
1367 };
1368
1369 struct bnx2x_fp_stats {
1370 struct tstorm_per_queue_stats old_tclient;
1371 struct ustorm_per_queue_stats old_uclient;
1372 struct xstorm_per_queue_stats old_xclient;
1373 struct bnx2x_eth_q_stats eth_q_stats;
1374 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1375 };
1376
1377 struct bnx2x {
1378 /* Fields used in the tx and intr/napi performance paths
1379 * are grouped together in the beginning of the structure
1380 */
1381 struct bnx2x_fastpath *fp;
1382 struct bnx2x_sp_objs *sp_objs;
1383 struct bnx2x_fp_stats *fp_stats;
1384 struct bnx2x_fp_txdata *bnx2x_txq;
1385 void __iomem *regview;
1386 void __iomem *doorbells;
1387 u16 db_size;
1388
1389 u8 pf_num; /* absolute PF number */
1390 u8 pfid; /* per-path PF number */
1391 int base_fw_ndsb; /**/
1392 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1393 #define BP_PORT(bp) (bp->pfid & 1)
1394 #define BP_FUNC(bp) (bp->pfid)
1395 #define BP_ABS_FUNC(bp) (bp->pf_num)
1396 #define BP_VN(bp) ((bp)->pfid >> 1)
1397 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1398 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1399 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1400 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1401 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1402
1403 #ifdef CONFIG_BNX2X_SRIOV
1404 /* protects vf2pf mailbox from simultaneous access */
1405 struct mutex vf2pf_mutex;
1406 /* vf pf channel mailbox contains request and response buffers */
1407 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1408 dma_addr_t vf2pf_mbox_mapping;
1409
1410 /* we set aside a copy of the acquire response */
1411 struct pfvf_acquire_resp_tlv acquire_resp;
1412
1413 /* bulletin board for messages from pf to vf */
1414 union pf_vf_bulletin *pf2vf_bulletin;
1415 dma_addr_t pf2vf_bulletin_mapping;
1416
1417 struct pf_vf_bulletin_content old_bulletin;
1418
1419 u16 requested_nr_virtfn;
1420 #endif /* CONFIG_BNX2X_SRIOV */
1421
1422 struct net_device *dev;
1423 struct pci_dev *pdev;
1424
1425 const struct iro *iro_arr;
1426 #define IRO (bp->iro_arr)
1427
1428 enum bnx2x_recovery_state recovery_state;
1429 int is_leader;
1430 struct msix_entry *msix_table;
1431
1432 int tx_ring_size;
1433
1434 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1435 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1436 #define ETH_MIN_PACKET_SIZE 60
1437 #define ETH_MAX_PACKET_SIZE 1500
1438 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1439 /* TCP with Timestamp Option (32) + IPv6 (40) */
1440 #define ETH_MAX_TPA_HEADER_SIZE 72
1441
1442 /* Max supported alignment is 256 (8 shift) */
1443 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1444
1445 /* FW uses 2 Cache lines Alignment for start packet and size
1446 *
1447 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1448 * at the end of skb->data, to avoid wasting a full cache line.
1449 * This reduces memory use (skb->truesize).
1450 */
1451 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1452
1453 #define BNX2X_FW_RX_ALIGN_END \
1454 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1455 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1456
1457 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1458
1459 struct host_sp_status_block *def_status_blk;
1460 #define DEF_SB_IGU_ID 16
1461 #define DEF_SB_ID HC_SP_SB_ID
1462 __le16 def_idx;
1463 __le16 def_att_idx;
1464 u32 attn_state;
1465 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1466
1467 /* slow path ring */
1468 struct eth_spe *spq;
1469 dma_addr_t spq_mapping;
1470 u16 spq_prod_idx;
1471 struct eth_spe *spq_prod_bd;
1472 struct eth_spe *spq_last_bd;
1473 __le16 *dsb_sp_prod;
1474 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1475 /* used to synchronize spq accesses */
1476 spinlock_t spq_lock;
1477
1478 /* event queue */
1479 union event_ring_elem *eq_ring;
1480 dma_addr_t eq_mapping;
1481 u16 eq_prod;
1482 u16 eq_cons;
1483 __le16 *eq_cons_sb;
1484 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1485
1486 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1487 u16 stats_pending;
1488 /* Counter for completed statistics ramrods */
1489 u16 stats_comp;
1490
1491 /* End of fields used in the performance code paths */
1492
1493 int panic;
1494 int msg_enable;
1495
1496 u32 flags;
1497 #define PCIX_FLAG (1 << 0)
1498 #define PCI_32BIT_FLAG (1 << 1)
1499 #define ONE_PORT_FLAG (1 << 2)
1500 #define NO_WOL_FLAG (1 << 3)
1501 #define USING_DAC_FLAG (1 << 4)
1502 #define USING_MSIX_FLAG (1 << 5)
1503 #define USING_MSI_FLAG (1 << 6)
1504 #define DISABLE_MSI_FLAG (1 << 7)
1505 #define TPA_ENABLE_FLAG (1 << 8)
1506 #define NO_MCP_FLAG (1 << 9)
1507 #define GRO_ENABLE_FLAG (1 << 10)
1508 #define MF_FUNC_DIS (1 << 11)
1509 #define OWN_CNIC_IRQ (1 << 12)
1510 #define NO_ISCSI_OOO_FLAG (1 << 13)
1511 #define NO_ISCSI_FLAG (1 << 14)
1512 #define NO_FCOE_FLAG (1 << 15)
1513 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1514 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1515 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1516 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1517 #define IS_VF_FLAG (1 << 22)
1518 #define INTERRUPTS_ENABLED_FLAG (1 << 23)
1519 #define BC_SUPPORTS_RMMOD_CMD (1 << 24)
1520
1521 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1522
1523 #ifdef CONFIG_BNX2X_SRIOV
1524 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1525 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1526 #else
1527 #define IS_VF(bp) false
1528 #define IS_PF(bp) true
1529 #endif
1530
1531 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1532 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1533 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1534
1535 u8 cnic_support;
1536 bool cnic_enabled;
1537 bool cnic_loaded;
1538 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1539
1540 /* Flag that indicates that we can start looking for FCoE L2 queue
1541 * completions in the default status block.
1542 */
1543 bool fcoe_init;
1544
1545 int pm_cap;
1546 int mrrs;
1547
1548 struct delayed_work sp_task;
1549 atomic_t interrupt_occurred;
1550 struct delayed_work sp_rtnl_task;
1551
1552 struct delayed_work period_task;
1553 struct timer_list timer;
1554 int current_interval;
1555
1556 u16 fw_seq;
1557 u16 fw_drv_pulse_wr_seq;
1558 u32 func_stx;
1559
1560 struct link_params link_params;
1561 struct link_vars link_vars;
1562 u32 link_cnt;
1563 struct bnx2x_link_report_data last_reported_link;
1564
1565 struct mdio_if_info mdio;
1566
1567 struct bnx2x_common common;
1568 struct bnx2x_port port;
1569
1570 struct cmng_init cmng;
1571
1572 u32 mf_config[E1HVN_MAX];
1573 u32 mf_ext_config;
1574 u32 path_has_ovlan; /* E3 */
1575 u16 mf_ov;
1576 u8 mf_mode;
1577 #define IS_MF(bp) (bp->mf_mode != 0)
1578 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1579 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1580 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1581
1582 u8 wol;
1583
1584 int rx_ring_size;
1585
1586 u16 tx_quick_cons_trip_int;
1587 u16 tx_quick_cons_trip;
1588 u16 tx_ticks_int;
1589 u16 tx_ticks;
1590
1591 u16 rx_quick_cons_trip_int;
1592 u16 rx_quick_cons_trip;
1593 u16 rx_ticks_int;
1594 u16 rx_ticks;
1595 /* Maximal coalescing timeout in us */
1596 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1597
1598 u32 lin_cnt;
1599
1600 u16 state;
1601 #define BNX2X_STATE_CLOSED 0
1602 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1603 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1604 #define BNX2X_STATE_OPEN 0x3000
1605 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1606 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1607
1608 #define BNX2X_STATE_DIAG 0xe000
1609 #define BNX2X_STATE_ERROR 0xf000
1610
1611 #define BNX2X_MAX_PRIORITY 8
1612 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1613 #define BNX2X_MAX_COS 3
1614 #define BNX2X_MAX_TX_COS 2
1615 int num_queues;
1616 uint num_ethernet_queues;
1617 uint num_cnic_queues;
1618 int num_napi_queues;
1619 int disable_tpa;
1620
1621 u32 rx_mode;
1622 #define BNX2X_RX_MODE_NONE 0
1623 #define BNX2X_RX_MODE_NORMAL 1
1624 #define BNX2X_RX_MODE_ALLMULTI 2
1625 #define BNX2X_RX_MODE_PROMISC 3
1626 #define BNX2X_MAX_MULTICAST 64
1627
1628 u8 igu_dsb_id;
1629 u8 igu_base_sb;
1630 u8 igu_sb_cnt;
1631 u8 min_msix_vec_cnt;
1632
1633 u32 igu_base_addr;
1634 dma_addr_t def_status_blk_mapping;
1635
1636 struct bnx2x_slowpath *slowpath;
1637 dma_addr_t slowpath_mapping;
1638
1639 /* Total number of FW statistics requests */
1640 u8 fw_stats_num;
1641
1642 /*
1643 * This is a memory buffer that will contain both statistics
1644 * ramrod request and data.
1645 */
1646 void *fw_stats;
1647 dma_addr_t fw_stats_mapping;
1648
1649 /*
1650 * FW statistics request shortcut (points at the
1651 * beginning of fw_stats buffer).
1652 */
1653 struct bnx2x_fw_stats_req *fw_stats_req;
1654 dma_addr_t fw_stats_req_mapping;
1655 int fw_stats_req_sz;
1656
1657 /*
1658 * FW statistics data shortcut (points at the beginning of
1659 * fw_stats buffer + fw_stats_req_sz).
1660 */
1661 struct bnx2x_fw_stats_data *fw_stats_data;
1662 dma_addr_t fw_stats_data_mapping;
1663 int fw_stats_data_sz;
1664
1665 /* For max 1024 cids (VF RSS), 32KB ILT page size and 1KB
1666 * context size we need 8 ILT entries.
1667 */
1668 #define ILT_MAX_L2_LINES 32
1669 struct hw_context context[ILT_MAX_L2_LINES];
1670
1671 struct bnx2x_ilt *ilt;
1672 #define BP_ILT(bp) ((bp)->ilt)
1673 #define ILT_MAX_LINES 256
1674 /*
1675 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1676 * to CNIC.
1677 */
1678 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1679
1680 /*
1681 * Maximum CID count that might be required by the bnx2x:
1682 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1683 */
1684 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1685 + 2 * CNIC_SUPPORT(bp))
1686 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1687 + 2 * CNIC_SUPPORT(bp))
1688 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1689 ILT_PAGE_CIDS))
1690
1691 int qm_cid_count;
1692
1693 bool dropless_fc;
1694
1695 void *t2;
1696 dma_addr_t t2_mapping;
1697 struct cnic_ops __rcu *cnic_ops;
1698 void *cnic_data;
1699 u32 cnic_tag;
1700 struct cnic_eth_dev cnic_eth_dev;
1701 union host_hc_status_block cnic_sb;
1702 dma_addr_t cnic_sb_mapping;
1703 struct eth_spe *cnic_kwq;
1704 struct eth_spe *cnic_kwq_prod;
1705 struct eth_spe *cnic_kwq_cons;
1706 struct eth_spe *cnic_kwq_last;
1707 u16 cnic_kwq_pending;
1708 u16 cnic_spq_pending;
1709 u8 fip_mac[ETH_ALEN];
1710 struct mutex cnic_mutex;
1711 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1712
1713 /* Start index of the "special" (CNIC related) L2 clients */
1714 u8 cnic_base_cl_id;
1715
1716 int dmae_ready;
1717 /* used to synchronize dmae accesses */
1718 spinlock_t dmae_lock;
1719
1720 /* used to protect the FW mail box */
1721 struct mutex fw_mb_mutex;
1722
1723 /* used to synchronize stats collecting */
1724 int stats_state;
1725
1726 /* used for synchronization of concurrent threads statistics handling */
1727 spinlock_t stats_lock;
1728
1729 /* used by dmae command loader */
1730 struct dmae_command stats_dmae;
1731 int executer_idx;
1732
1733 u16 stats_counter;
1734 struct bnx2x_eth_stats eth_stats;
1735 struct host_func_stats func_stats;
1736 struct bnx2x_eth_stats_old eth_stats_old;
1737 struct bnx2x_net_stats_old net_stats_old;
1738 struct bnx2x_fw_port_stats_old fw_stats_old;
1739 bool stats_init;
1740
1741 struct z_stream_s *strm;
1742 void *gunzip_buf;
1743 dma_addr_t gunzip_mapping;
1744 int gunzip_outlen;
1745 #define FW_BUF_SIZE 0x8000
1746 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1747 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1748 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1749
1750 struct raw_op *init_ops;
1751 /* Init blocks offsets inside init_ops */
1752 u16 *init_ops_offsets;
1753 /* Data blob - has 32 bit granularity */
1754 u32 *init_data;
1755 u32 init_mode_flags;
1756 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1757 /* Zipped PRAM blobs - raw data */
1758 const u8 *tsem_int_table_data;
1759 const u8 *tsem_pram_data;
1760 const u8 *usem_int_table_data;
1761 const u8 *usem_pram_data;
1762 const u8 *xsem_int_table_data;
1763 const u8 *xsem_pram_data;
1764 const u8 *csem_int_table_data;
1765 const u8 *csem_pram_data;
1766 #define INIT_OPS(bp) (bp->init_ops)
1767 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1768 #define INIT_DATA(bp) (bp->init_data)
1769 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1770 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1771 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1772 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1773 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1774 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1775 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1776 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1777
1778 #define PHY_FW_VER_LEN 20
1779 char fw_ver[32];
1780 const struct firmware *firmware;
1781
1782 struct bnx2x_vfdb *vfdb;
1783 #define IS_SRIOV(bp) ((bp)->vfdb)
1784
1785 /* DCB support on/off */
1786 u16 dcb_state;
1787 #define BNX2X_DCB_STATE_OFF 0
1788 #define BNX2X_DCB_STATE_ON 1
1789
1790 /* DCBX engine mode */
1791 int dcbx_enabled;
1792 #define BNX2X_DCBX_ENABLED_OFF 0
1793 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1794 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1795 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1796
1797 bool dcbx_mode_uset;
1798
1799 struct bnx2x_config_dcbx_params dcbx_config_params;
1800 struct bnx2x_dcbx_port_params dcbx_port_params;
1801 int dcb_version;
1802
1803 /* CAM credit pools */
1804
1805 /* used only in sriov */
1806 struct bnx2x_credit_pool_obj vlans_pool;
1807
1808 struct bnx2x_credit_pool_obj macs_pool;
1809
1810 /* RX_MODE object */
1811 struct bnx2x_rx_mode_obj rx_mode_obj;
1812
1813 /* MCAST object */
1814 struct bnx2x_mcast_obj mcast_obj;
1815
1816 /* RSS configuration object */
1817 struct bnx2x_rss_config_obj rss_conf_obj;
1818
1819 /* Function State controlling object */
1820 struct bnx2x_func_sp_obj func_obj;
1821
1822 unsigned long sp_state;
1823
1824 /* operation indication for the sp_rtnl task */
1825 unsigned long sp_rtnl_state;
1826
1827 /* DCBX Negotiation results */
1828 struct dcbx_features dcbx_local_feat;
1829 u32 dcbx_error;
1830
1831 #ifdef BCM_DCBNL
1832 struct dcbx_features dcbx_remote_feat;
1833 u32 dcbx_remote_flags;
1834 #endif
1835 /* AFEX: store default vlan used */
1836 int afex_def_vlan_tag;
1837 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1838 u32 pending_max;
1839
1840 /* multiple tx classes of service */
1841 u8 max_cos;
1842
1843 /* priority to cos mapping */
1844 u8 prio_to_cos[8];
1845
1846 int fp_array_size;
1847 u32 dump_preset_idx;
1848 bool stats_started;
1849 struct semaphore stats_sema;
1850 };
1851
1852 /* Tx queues may be less or equal to Rx queues */
1853 extern int num_queues;
1854 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1855 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1856 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1857 (bp)->num_cnic_queues)
1858 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1859
1860 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1861
1862 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1863 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1864
1865 #define RSS_IPV4_CAP_MASK \
1866 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1867
1868 #define RSS_IPV4_TCP_CAP_MASK \
1869 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1870
1871 #define RSS_IPV6_CAP_MASK \
1872 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1873
1874 #define RSS_IPV6_TCP_CAP_MASK \
1875 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1876
1877 /* func init flags */
1878 #define FUNC_FLG_RSS 0x0001
1879 #define FUNC_FLG_STATS 0x0002
1880 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1881 #define FUNC_FLG_TPA 0x0008
1882 #define FUNC_FLG_SPQ 0x0010
1883 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1884 #define FUNC_FLG_LEADING_STATS 0x0040
1885 struct bnx2x_func_init_params {
1886 /* dma */
1887 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1888 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1889
1890 u16 func_flgs;
1891 u16 func_id; /* abs fid */
1892 u16 pf_id;
1893 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1894 };
1895
1896 #define for_each_cnic_queue(bp, var) \
1897 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1898 (var)++) \
1899 if (skip_queue(bp, var)) \
1900 continue; \
1901 else
1902
1903 #define for_each_eth_queue(bp, var) \
1904 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1905
1906 #define for_each_nondefault_eth_queue(bp, var) \
1907 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1908
1909 #define for_each_queue(bp, var) \
1910 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1911 if (skip_queue(bp, var)) \
1912 continue; \
1913 else
1914
1915 /* Skip forwarding FP */
1916 #define for_each_valid_rx_queue(bp, var) \
1917 for ((var) = 0; \
1918 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1919 BNX2X_NUM_ETH_QUEUES(bp)); \
1920 (var)++) \
1921 if (skip_rx_queue(bp, var)) \
1922 continue; \
1923 else
1924
1925 #define for_each_rx_queue_cnic(bp, var) \
1926 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1927 (var)++) \
1928 if (skip_rx_queue(bp, var)) \
1929 continue; \
1930 else
1931
1932 #define for_each_rx_queue(bp, var) \
1933 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1934 if (skip_rx_queue(bp, var)) \
1935 continue; \
1936 else
1937
1938 /* Skip OOO FP */
1939 #define for_each_valid_tx_queue(bp, var) \
1940 for ((var) = 0; \
1941 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1942 BNX2X_NUM_ETH_QUEUES(bp)); \
1943 (var)++) \
1944 if (skip_tx_queue(bp, var)) \
1945 continue; \
1946 else
1947
1948 #define for_each_tx_queue_cnic(bp, var) \
1949 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1950 (var)++) \
1951 if (skip_tx_queue(bp, var)) \
1952 continue; \
1953 else
1954
1955 #define for_each_tx_queue(bp, var) \
1956 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1957 if (skip_tx_queue(bp, var)) \
1958 continue; \
1959 else
1960
1961 #define for_each_nondefault_queue(bp, var) \
1962 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1963 if (skip_queue(bp, var)) \
1964 continue; \
1965 else
1966
1967 #define for_each_cos_in_tx_queue(fp, var) \
1968 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1969
1970 /* skip rx queue
1971 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1972 */
1973 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1974
1975 /* skip tx queue
1976 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1977 */
1978 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1979
1980 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1981
1982 /**
1983 * bnx2x_set_mac_one - configure a single MAC address
1984 *
1985 * @bp: driver handle
1986 * @mac: MAC to configure
1987 * @obj: MAC object handle
1988 * @set: if 'true' add a new MAC, otherwise - delete
1989 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1990 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1991 *
1992 * Configures one MAC according to provided parameters or continues the
1993 * execution of previously scheduled commands if RAMROD_CONT is set in
1994 * ramrod_flags.
1995 *
1996 * Returns zero if operation has successfully completed, a positive value if the
1997 * operation has been successfully scheduled and a negative - if a requested
1998 * operations has failed.
1999 */
2000 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
2001 struct bnx2x_vlan_mac_obj *obj, bool set,
2002 int mac_type, unsigned long *ramrod_flags);
2003 /**
2004 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
2005 *
2006 * @bp: driver handle
2007 * @mac_obj: MAC object handle
2008 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
2009 * @wait_for_comp: if 'true' block until completion
2010 *
2011 * Deletes all MACs of the specific type (e.g. ETH, UC list).
2012 *
2013 * Returns zero if operation has successfully completed, a positive value if the
2014 * operation has been successfully scheduled and a negative - if a requested
2015 * operations has failed.
2016 */
2017 int bnx2x_del_all_macs(struct bnx2x *bp,
2018 struct bnx2x_vlan_mac_obj *mac_obj,
2019 int mac_type, bool wait_for_comp);
2020
2021 /* Init Function API */
2022 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
2023 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
2024 u8 vf_valid, int fw_sb_id, int igu_sb_id);
2025 u32 bnx2x_get_pretend_reg(struct bnx2x *bp);
2026 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
2027 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2028 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
2029 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
2030 void bnx2x_read_mf_cfg(struct bnx2x *bp);
2031
2032 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
2033
2034 /* dmae */
2035 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
2036 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
2037 u32 len32);
2038 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
2039 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
2040 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
2041 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
2042 bool with_comp, u8 comp_type);
2043
2044 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
2045 u8 src_type, u8 dst_type);
2046 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae);
2047
2048 /* FLR related routines */
2049 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
2050 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
2051 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
2052 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
2053 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
2054 char *msg, u32 poll_cnt);
2055
2056 void bnx2x_calc_fc_adv(struct bnx2x *bp);
2057 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
2058 u32 data_hi, u32 data_lo, int cmd_type);
2059 void bnx2x_update_coalesce(struct bnx2x *bp);
2060 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
2061
2062 bool bnx2x_port_after_undi(struct bnx2x *bp);
2063
2064 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
2065 int wait)
2066 {
2067 u32 val;
2068
2069 do {
2070 val = REG_RD(bp, reg);
2071 if (val == expected)
2072 break;
2073 ms -= wait;
2074 msleep(wait);
2075
2076 } while (ms > 0);
2077
2078 return val;
2079 }
2080
2081 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
2082 bool is_pf);
2083
2084 #define BNX2X_ILT_ZALLOC(x, y, size) \
2085 x = dma_zalloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL)
2086
2087 #define BNX2X_ILT_FREE(x, y, size) \
2088 do { \
2089 if (x) { \
2090 dma_free_coherent(&bp->pdev->dev, size, x, y); \
2091 x = NULL; \
2092 y = 0; \
2093 } \
2094 } while (0)
2095
2096 #define ILOG2(x) (ilog2((x)))
2097
2098 #define ILT_NUM_PAGE_ENTRIES (3072)
2099 /* In 57710/11 we use whole table since we have 8 func
2100 * In 57712 we have only 4 func, but use same size per func, then only half of
2101 * the table in use
2102 */
2103 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
2104
2105 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
2106 /*
2107 * the phys address is shifted right 12 bits and has an added
2108 * 1=valid bit added to the 53rd bit
2109 * then since this is a wide register(TM)
2110 * we split it into two 32 bit writes
2111 */
2112 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
2113 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
2114
2115 /* load/unload mode */
2116 #define LOAD_NORMAL 0
2117 #define LOAD_OPEN 1
2118 #define LOAD_DIAG 2
2119 #define LOAD_LOOPBACK_EXT 3
2120 #define UNLOAD_NORMAL 0
2121 #define UNLOAD_CLOSE 1
2122 #define UNLOAD_RECOVERY 2
2123
2124 /* DMAE command defines */
2125 #define DMAE_TIMEOUT -1
2126 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2127 #define DMAE_NOT_RDY -3
2128 #define DMAE_PCI_ERR_FLAG 0x80000000
2129
2130 #define DMAE_SRC_PCI 0
2131 #define DMAE_SRC_GRC 1
2132
2133 #define DMAE_DST_NONE 0
2134 #define DMAE_DST_PCI 1
2135 #define DMAE_DST_GRC 2
2136
2137 #define DMAE_COMP_PCI 0
2138 #define DMAE_COMP_GRC 1
2139
2140 /* E2 and onward - PCI error handling in the completion */
2141
2142 #define DMAE_COMP_REGULAR 0
2143 #define DMAE_COM_SET_ERR 1
2144
2145 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2146 DMAE_COMMAND_SRC_SHIFT)
2147 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2148 DMAE_COMMAND_SRC_SHIFT)
2149
2150 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2151 DMAE_COMMAND_DST_SHIFT)
2152 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2153 DMAE_COMMAND_DST_SHIFT)
2154
2155 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2156 DMAE_COMMAND_C_DST_SHIFT)
2157 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2158 DMAE_COMMAND_C_DST_SHIFT)
2159
2160 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2161
2162 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2163 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2164 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2165 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2166
2167 #define DMAE_CMD_PORT_0 0
2168 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2169
2170 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2171 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2172 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2173
2174 #define DMAE_SRC_PF 0
2175 #define DMAE_SRC_VF 1
2176
2177 #define DMAE_DST_PF 0
2178 #define DMAE_DST_VF 1
2179
2180 #define DMAE_C_SRC 0
2181 #define DMAE_C_DST 1
2182
2183 #define DMAE_LEN32_RD_MAX 0x80
2184 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2185
2186 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2187 * indicates error
2188 */
2189
2190 #define MAX_DMAE_C_PER_PORT 8
2191 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2192 BP_VN(bp))
2193 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2194 E1HVN_MAX)
2195
2196 /* PCIE link and speed */
2197 #define PCICFG_LINK_WIDTH 0x1f00000
2198 #define PCICFG_LINK_WIDTH_SHIFT 20
2199 #define PCICFG_LINK_SPEED 0xf0000
2200 #define PCICFG_LINK_SPEED_SHIFT 16
2201
2202 #define BNX2X_NUM_TESTS_SF 7
2203 #define BNX2X_NUM_TESTS_MF 3
2204 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2205 BNX2X_NUM_TESTS_SF)
2206
2207 #define BNX2X_PHY_LOOPBACK 0
2208 #define BNX2X_MAC_LOOPBACK 1
2209 #define BNX2X_EXT_LOOPBACK 2
2210 #define BNX2X_PHY_LOOPBACK_FAILED 1
2211 #define BNX2X_MAC_LOOPBACK_FAILED 2
2212 #define BNX2X_EXT_LOOPBACK_FAILED 3
2213 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2214 BNX2X_PHY_LOOPBACK_FAILED)
2215
2216 #define STROM_ASSERT_ARRAY_SIZE 50
2217
2218 /* must be used on a CID before placing it on a HW ring */
2219 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2220 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2221 (x))
2222
2223 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2224 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2225
2226 #define BNX2X_BTR 4
2227 #define MAX_SPQ_PENDING 8
2228
2229 /* CMNG constants, as derived from system spec calculations */
2230 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2231 #define DEF_MIN_RATE 100
2232 /* resolution of the rate shaping timer - 400 usec */
2233 #define RS_PERIODIC_TIMEOUT_USEC 400
2234 /* number of bytes in single QM arbitration cycle -
2235 * coefficient for calculating the fairness timer */
2236 #define QM_ARB_BYTES 160000
2237 /* resolution of Min algorithm 1:100 */
2238 #define MIN_RES 100
2239 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2240 #define MIN_ABOVE_THRESH 32768
2241 /* Fairness algorithm integration time coefficient -
2242 * for calculating the actual Tfair */
2243 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2244 /* Memory of fairness algorithm . 2 cycles */
2245 #define FAIR_MEM 2
2246
2247 #define ATTN_NIG_FOR_FUNC (1L << 8)
2248 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2249 #define GPIO_2_FUNC (1L << 10)
2250 #define GPIO_3_FUNC (1L << 11)
2251 #define GPIO_4_FUNC (1L << 12)
2252 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2253 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2254 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2255 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2256 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2257 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2258
2259 #define ATTN_HARD_WIRED_MASK 0xff00
2260 #define ATTENTION_ID 4
2261
2262 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \
2263 IS_MF_FCOE_AFEX(bp))
2264
2265 /* stuff added to make the code fit 80Col */
2266
2267 #define BNX2X_PMF_LINK_ASSERT \
2268 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2269
2270 #define BNX2X_MC_ASSERT_BITS \
2271 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2272 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2273 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2274 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2275
2276 #define BNX2X_MCP_ASSERT \
2277 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2278
2279 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2280 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2281 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2282 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2283 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2284 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2285 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2286
2287 #define HW_INTERRUT_ASSERT_SET_0 \
2288 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2289 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2290 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2291 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2292 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2293 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2294 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2295 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2296 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2297 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2298 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2299 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2300 #define HW_INTERRUT_ASSERT_SET_1 \
2301 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2302 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2303 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2304 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2305 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2306 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2307 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2308 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2309 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2310 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2311 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2312 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2313 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2314 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2315 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2316 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2317 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2318 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2319 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2320 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2321 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2322 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2323 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2324 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2325 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2326 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2327 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2328 #define HW_INTERRUT_ASSERT_SET_2 \
2329 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2330 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2331 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2332 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2333 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2334 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2335 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2336 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2337 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2338 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2339 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2340 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2341 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2342
2343 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2344 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2345 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2346 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2347
2348 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2349 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2350
2351 #define MULTI_MASK 0x7f
2352
2353 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2354 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2355 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2356 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2357
2358 #define DEF_USB_IGU_INDEX_OFF \
2359 offsetof(struct cstorm_def_status_block_u, igu_index)
2360 #define DEF_CSB_IGU_INDEX_OFF \
2361 offsetof(struct cstorm_def_status_block_c, igu_index)
2362 #define DEF_XSB_IGU_INDEX_OFF \
2363 offsetof(struct xstorm_def_status_block, igu_index)
2364 #define DEF_TSB_IGU_INDEX_OFF \
2365 offsetof(struct tstorm_def_status_block, igu_index)
2366
2367 #define DEF_USB_SEGMENT_OFF \
2368 offsetof(struct cstorm_def_status_block_u, segment)
2369 #define DEF_CSB_SEGMENT_OFF \
2370 offsetof(struct cstorm_def_status_block_c, segment)
2371 #define DEF_XSB_SEGMENT_OFF \
2372 offsetof(struct xstorm_def_status_block, segment)
2373 #define DEF_TSB_SEGMENT_OFF \
2374 offsetof(struct tstorm_def_status_block, segment)
2375
2376 #define BNX2X_SP_DSB_INDEX \
2377 (&bp->def_status_blk->sp_sb.\
2378 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2379
2380 #define CAM_IS_INVALID(x) \
2381 (GET_FLAG(x.flags, \
2382 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2383 (T_ETH_MAC_COMMAND_INVALIDATE))
2384
2385 /* Number of u32 elements in MC hash array */
2386 #define MC_HASH_SIZE 8
2387 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2388 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2389
2390 #ifndef PXP2_REG_PXP2_INT_STS
2391 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2392 #endif
2393
2394 #ifndef ETH_MAX_RX_CLIENTS_E2
2395 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2396 #endif
2397
2398 #define BNX2X_VPD_LEN 128
2399 #define VENDOR_ID_LEN 4
2400
2401 #define VF_ACQUIRE_THRESH 3
2402 #define VF_ACQUIRE_MAC_FILTERS 1
2403 #define VF_ACQUIRE_MC_FILTERS 10
2404
2405 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2406 (!((me_reg) & ME_REG_VF_ERR)))
2407 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
2408 /* Congestion management fairness mode */
2409 #define CMNG_FNS_NONE 0
2410 #define CMNG_FNS_MINMAX 1
2411
2412 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2413 #define HC_SEG_ACCESS_ATTN 4
2414 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2415
2416 static const u32 dmae_reg_go_c[] = {
2417 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2418 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2419 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2420 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2421 };
2422
2423 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2424 void bnx2x_notify_link_changed(struct bnx2x *bp);
2425
2426 #define BNX2X_MF_SD_PROTOCOL(bp) \
2427 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2428
2429 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2430 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2431
2432 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2433 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2434
2435 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2436 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2437
2438 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2439 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2440
2441 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2442 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2443 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2444 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2445
2446 #define SET_FLAG(value, mask, flag) \
2447 do {\
2448 (value) &= ~(mask);\
2449 (value) |= ((flag) << (mask##_SHIFT));\
2450 } while (0)
2451
2452 #define GET_FLAG(value, mask) \
2453 (((value) & (mask)) >> (mask##_SHIFT))
2454
2455 #define GET_FIELD(value, fname) \
2456 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2457
2458 enum {
2459 SWITCH_UPDATE,
2460 AFEX_UPDATE,
2461 };
2462
2463 #define NUM_MACS 8
2464
2465 enum bnx2x_pci_bus_speed {
2466 BNX2X_PCI_LINK_SPEED_2500 = 2500,
2467 BNX2X_PCI_LINK_SPEED_5000 = 5000,
2468 BNX2X_PCI_LINK_SPEED_8000 = 8000
2469 };
2470
2471 void bnx2x_set_local_cmng(struct bnx2x *bp);
2472 #endif /* bnx2x.h */
Linux kernel - Deliverables
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