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bnx2x: previous driver unload revised
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16 #include <linux/netdevice.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/types.h>
19
20 /* compilation time flags */
21
22 /* define this to make the driver freeze on error to allow getting debug info
23 * (you will need to reboot afterwards) */
24 /* #define BNX2X_STOP_ON_ERROR */
25
26 #define DRV_MODULE_VERSION "1.72.10-0"
27 #define DRV_MODULE_RELDATE "2012/02/20"
28 #define BNX2X_BC_VER 0x040200
29
30 #if defined(CONFIG_DCB)
31 #define BCM_DCBNL
32 #endif
33 #if defined(CONFIG_CNIC) || defined(CONFIG_CNIC_MODULE)
34 #define BCM_CNIC 1
35 #include "../cnic_if.h"
36 #endif
37
38 #ifdef BCM_CNIC
39 #define BNX2X_MIN_MSIX_VEC_CNT 3
40 #define BNX2X_MSIX_VEC_FP_START 2
41 #else
42 #define BNX2X_MIN_MSIX_VEC_CNT 2
43 #define BNX2X_MSIX_VEC_FP_START 1
44 #endif
45
46 #include <linux/mdio.h>
47
48 #include "bnx2x_reg.h"
49 #include "bnx2x_fw_defs.h"
50 #include "bnx2x_hsi.h"
51 #include "bnx2x_link.h"
52 #include "bnx2x_sp.h"
53 #include "bnx2x_dcb.h"
54 #include "bnx2x_stats.h"
55
56 /* error/debug prints */
57
58 #define DRV_MODULE_NAME "bnx2x"
59
60 /* for messages that are currently off */
61 #define BNX2X_MSG_OFF 0x0
62 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
63 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
64 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
65 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
66 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
67 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
68 #define BNX2X_MSG_IOV 0x0800000
69 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
70 #define BNX2X_MSG_ETHTOOL 0x4000000
71 #define BNX2X_MSG_DCB 0x8000000
72
73 /* regular debug print */
74 #define DP(__mask, fmt, ...) \
75 do { \
76 if (unlikely(bp->msg_enable & (__mask))) \
77 pr_notice("[%s:%d(%s)]" fmt, \
78 __func__, __LINE__, \
79 bp->dev ? (bp->dev->name) : "?", \
80 ##__VA_ARGS__); \
81 } while (0)
82
83 #define DP_CONT(__mask, fmt, ...) \
84 do { \
85 if (unlikely(bp->msg_enable & (__mask))) \
86 pr_cont(fmt, ##__VA_ARGS__); \
87 } while (0)
88
89 /* errors debug print */
90 #define BNX2X_DBG_ERR(fmt, ...) \
91 do { \
92 if (unlikely(netif_msg_probe(bp))) \
93 pr_err("[%s:%d(%s)]" fmt, \
94 __func__, __LINE__, \
95 bp->dev ? (bp->dev->name) : "?", \
96 ##__VA_ARGS__); \
97 } while (0)
98
99 /* for errors (never masked) */
100 #define BNX2X_ERR(fmt, ...) \
101 do { \
102 pr_err("[%s:%d(%s)]" fmt, \
103 __func__, __LINE__, \
104 bp->dev ? (bp->dev->name) : "?", \
105 ##__VA_ARGS__); \
106 } while (0)
107
108 #define BNX2X_ERROR(fmt, ...) \
109 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
110
111
112 /* before we have a dev->name use dev_info() */
113 #define BNX2X_DEV_INFO(fmt, ...) \
114 do { \
115 if (unlikely(netif_msg_probe(bp))) \
116 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
117 } while (0)
118
119 #ifdef BNX2X_STOP_ON_ERROR
120 void bnx2x_int_disable(struct bnx2x *bp);
121 #define bnx2x_panic() \
122 do { \
123 bp->panic = 1; \
124 BNX2X_ERR("driver assert\n"); \
125 bnx2x_int_disable(bp); \
126 bnx2x_panic_dump(bp); \
127 } while (0)
128 #else
129 #define bnx2x_panic() \
130 do { \
131 bp->panic = 1; \
132 BNX2X_ERR("driver assert\n"); \
133 bnx2x_panic_dump(bp); \
134 } while (0)
135 #endif
136
137 #define bnx2x_mc_addr(ha) ((ha)->addr)
138 #define bnx2x_uc_addr(ha) ((ha)->addr)
139
140 #define U64_LO(x) (u32)(((u64)(x)) & 0xffffffff)
141 #define U64_HI(x) (u32)(((u64)(x)) >> 32)
142 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
143
144
145 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
146
147 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
148 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
149 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
150
151 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
152 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
153 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
154
155 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
156 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
157
158 #define REG_RD_DMAE(bp, offset, valp, len32) \
159 do { \
160 bnx2x_read_dmae(bp, offset, len32);\
161 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
162 } while (0)
163
164 #define REG_WR_DMAE(bp, offset, valp, len32) \
165 do { \
166 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
167 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
168 offset, len32); \
169 } while (0)
170
171 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
172 REG_WR_DMAE(bp, offset, valp, len32)
173
174 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
175 do { \
176 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
177 bnx2x_write_big_buf_wb(bp, addr, len32); \
178 } while (0)
179
180 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
181 offsetof(struct shmem_region, field))
182 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
183 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
184
185 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
186 offsetof(struct shmem2_region, field))
187 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
188 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
189 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
190 offsetof(struct mf_cfg, field))
191 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
192 offsetof(struct mf2_cfg, field))
193
194 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
195 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
196 MF_CFG_ADDR(bp, field), (val))
197 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
198
199 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
200 (SHMEM2_RD((bp), size) > \
201 offsetof(struct shmem2_region, field)))
202
203 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
204 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
205
206 /* SP SB indices */
207
208 /* General SP events - stats query, cfc delete, etc */
209 #define HC_SP_INDEX_ETH_DEF_CONS 3
210
211 /* EQ completions */
212 #define HC_SP_INDEX_EQ_CONS 7
213
214 /* FCoE L2 connection completions */
215 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
216 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
217 /* iSCSI L2 */
218 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
219 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
220
221 /* Special clients parameters */
222
223 /* SB indices */
224 /* FCoE L2 */
225 #define BNX2X_FCOE_L2_RX_INDEX \
226 (&bp->def_status_blk->sp_sb.\
227 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
228
229 #define BNX2X_FCOE_L2_TX_INDEX \
230 (&bp->def_status_blk->sp_sb.\
231 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
232
233 /**
234 * CIDs and CLIDs:
235 * CLIDs below is a CLID for func 0, then the CLID for other
236 * functions will be calculated by the formula:
237 *
238 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
239 *
240 */
241 enum {
242 BNX2X_ISCSI_ETH_CL_ID_IDX,
243 BNX2X_FCOE_ETH_CL_ID_IDX,
244 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
245 };
246
247 #define BNX2X_CNIC_START_ETH_CID 48
248 enum {
249 /* iSCSI L2 */
250 BNX2X_ISCSI_ETH_CID = BNX2X_CNIC_START_ETH_CID,
251 /* FCoE L2 */
252 BNX2X_FCOE_ETH_CID,
253 };
254
255 /** Additional rings budgeting */
256 #ifdef BCM_CNIC
257 #define CNIC_PRESENT 1
258 #define FCOE_PRESENT 1
259 #else
260 #define CNIC_PRESENT 0
261 #define FCOE_PRESENT 0
262 #endif /* BCM_CNIC */
263 #define NON_ETH_CONTEXT_USE (FCOE_PRESENT)
264
265 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
266 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
267
268 #define SM_RX_ID 0
269 #define SM_TX_ID 1
270
271 /* defines for multiple tx priority indices */
272 #define FIRST_TX_ONLY_COS_INDEX 1
273 #define FIRST_TX_COS_INDEX 0
274
275 /* defines for decodeing the fastpath index and the cos index out of the
276 * transmission queue index
277 */
278 #define MAX_TXQS_PER_COS FP_SB_MAX_E1x
279
280 #define TXQ_TO_FP(txq_index) ((txq_index) % MAX_TXQS_PER_COS)
281 #define TXQ_TO_COS(txq_index) ((txq_index) / MAX_TXQS_PER_COS)
282
283 /* rules for calculating the cids of tx-only connections */
284 #define CID_TO_FP(cid) ((cid) % MAX_TXQS_PER_COS)
285 #define CID_COS_TO_TX_ONLY_CID(cid, cos) (cid + cos * MAX_TXQS_PER_COS)
286
287 /* fp index inside class of service range */
288 #define FP_COS_TO_TXQ(fp, cos) ((fp)->index + cos * MAX_TXQS_PER_COS)
289
290 /*
291 * 0..15 eth cos0
292 * 16..31 eth cos1 if applicable
293 * 32..47 eth cos2 If applicable
294 * fcoe queue follows eth queues (16, 32, 48 depending on cos)
295 */
296 #define MAX_ETH_TXQ_IDX(bp) (MAX_TXQS_PER_COS * (bp)->max_cos)
297 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp))
298
299 /* fast path */
300 /*
301 * This driver uses new build_skb() API :
302 * RX ring buffer contains pointer to kmalloc() data only,
303 * skb are built only after Hardware filled the frame.
304 */
305 struct sw_rx_bd {
306 u8 *data;
307 DEFINE_DMA_UNMAP_ADDR(mapping);
308 };
309
310 struct sw_tx_bd {
311 struct sk_buff *skb;
312 u16 first_bd;
313 u8 flags;
314 /* Set on the first BD descriptor when there is a split BD */
315 #define BNX2X_TSO_SPLIT_BD (1<<0)
316 };
317
318 struct sw_rx_page {
319 struct page *page;
320 DEFINE_DMA_UNMAP_ADDR(mapping);
321 };
322
323 union db_prod {
324 struct doorbell_set_prod data;
325 u32 raw;
326 };
327
328 /* dropless fc FW/HW related params */
329 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
330 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
331 ETH_MAX_AGGREGATION_QUEUES_E1 :\
332 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
333 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
334 #define FW_PREFETCH_CNT 16
335 #define DROPLESS_FC_HEADROOM 100
336
337 /* MC hsi */
338 #define BCM_PAGE_SHIFT 12
339 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
340 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
341 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
342
343 #define PAGES_PER_SGE_SHIFT 0
344 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
345 #define SGE_PAGE_SIZE PAGE_SIZE
346 #define SGE_PAGE_SHIFT PAGE_SHIFT
347 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
348 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
349
350 /* SGE ring related macros */
351 #define NUM_RX_SGE_PAGES 2
352 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
353 #define NEXT_PAGE_SGE_DESC_CNT 2
354 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
355 /* RX_SGE_CNT is promised to be a power of 2 */
356 #define RX_SGE_MASK (RX_SGE_CNT - 1)
357 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
358 #define MAX_RX_SGE (NUM_RX_SGE - 1)
359 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
360 (MAX_RX_SGE_CNT - 1)) ? \
361 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
362 (x) + 1)
363 #define RX_SGE(x) ((x) & MAX_RX_SGE)
364
365 /*
366 * Number of required SGEs is the sum of two:
367 * 1. Number of possible opened aggregations (next packet for
368 * these aggregations will probably consume SGE immidiatelly)
369 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
370 * after placement on BD for new TPA aggregation)
371 *
372 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
373 */
374 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
375 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
376 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
377 MAX_RX_SGE_CNT)
378 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
379 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
380 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
381
382 /* Manipulate a bit vector defined as an array of u64 */
383
384 /* Number of bits in one sge_mask array element */
385 #define BIT_VEC64_ELEM_SZ 64
386 #define BIT_VEC64_ELEM_SHIFT 6
387 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
388
389
390 #define __BIT_VEC64_SET_BIT(el, bit) \
391 do { \
392 el = ((el) | ((u64)0x1 << (bit))); \
393 } while (0)
394
395 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
396 do { \
397 el = ((el) & (~((u64)0x1 << (bit)))); \
398 } while (0)
399
400
401 #define BIT_VEC64_SET_BIT(vec64, idx) \
402 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
403 (idx) & BIT_VEC64_ELEM_MASK)
404
405 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
406 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
407 (idx) & BIT_VEC64_ELEM_MASK)
408
409 #define BIT_VEC64_TEST_BIT(vec64, idx) \
410 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
411 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
412
413 /* Creates a bitmask of all ones in less significant bits.
414 idx - index of the most significant bit in the created mask */
415 #define BIT_VEC64_ONES_MASK(idx) \
416 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
417 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
418
419 /*******************************************************/
420
421
422
423 /* Number of u64 elements in SGE mask array */
424 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
425 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
426 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
427
428 union host_hc_status_block {
429 /* pointer to fp status block e1x */
430 struct host_hc_status_block_e1x *e1x_sb;
431 /* pointer to fp status block e2 */
432 struct host_hc_status_block_e2 *e2_sb;
433 };
434
435 struct bnx2x_agg_info {
436 /*
437 * First aggregation buffer is a data buffer, the following - are pages.
438 * We will preallocate the data buffer for each aggregation when
439 * we open the interface and will replace the BD at the consumer
440 * with this one when we receive the TPA_START CQE in order to
441 * keep the Rx BD ring consistent.
442 */
443 struct sw_rx_bd first_buf;
444 u8 tpa_state;
445 #define BNX2X_TPA_START 1
446 #define BNX2X_TPA_STOP 2
447 #define BNX2X_TPA_ERROR 3
448 u8 placement_offset;
449 u16 parsing_flags;
450 u16 vlan_tag;
451 u16 len_on_bd;
452 u32 rxhash;
453 u16 gro_size;
454 u16 full_page;
455 };
456
457 #define Q_STATS_OFFSET32(stat_name) \
458 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
459
460 struct bnx2x_fp_txdata {
461
462 struct sw_tx_bd *tx_buf_ring;
463
464 union eth_tx_bd_types *tx_desc_ring;
465 dma_addr_t tx_desc_mapping;
466
467 u32 cid;
468
469 union db_prod tx_db;
470
471 u16 tx_pkt_prod;
472 u16 tx_pkt_cons;
473 u16 tx_bd_prod;
474 u16 tx_bd_cons;
475
476 unsigned long tx_pkt;
477
478 __le16 *tx_cons_sb;
479
480 int txq_index;
481 };
482
483 enum bnx2x_tpa_mode_t {
484 TPA_MODE_LRO,
485 TPA_MODE_GRO
486 };
487
488 struct bnx2x_fastpath {
489 struct bnx2x *bp; /* parent */
490
491 #define BNX2X_NAPI_WEIGHT 128
492 struct napi_struct napi;
493 union host_hc_status_block status_blk;
494 /* chip independed shortcuts into sb structure */
495 __le16 *sb_index_values;
496 __le16 *sb_running_index;
497 /* chip independed shortcut into rx_prods_offset memory */
498 u32 ustorm_rx_prods_offset;
499
500 u32 rx_buf_size;
501
502 dma_addr_t status_blk_mapping;
503
504 enum bnx2x_tpa_mode_t mode;
505
506 u8 max_cos; /* actual number of active tx coses */
507 struct bnx2x_fp_txdata txdata[BNX2X_MULTI_TX_COS];
508
509 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
510 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
511
512 struct eth_rx_bd *rx_desc_ring;
513 dma_addr_t rx_desc_mapping;
514
515 union eth_rx_cqe *rx_comp_ring;
516 dma_addr_t rx_comp_mapping;
517
518 /* SGE ring */
519 struct eth_rx_sge *rx_sge_ring;
520 dma_addr_t rx_sge_mapping;
521
522 u64 sge_mask[RX_SGE_MASK_LEN];
523
524 u32 cid;
525
526 __le16 fp_hc_idx;
527
528 u8 index; /* number in fp array */
529 u8 rx_queue; /* index for skb_record */
530 u8 cl_id; /* eth client id */
531 u8 cl_qzone_id;
532 u8 fw_sb_id; /* status block number in FW */
533 u8 igu_sb_id; /* status block number in HW */
534
535 u16 rx_bd_prod;
536 u16 rx_bd_cons;
537 u16 rx_comp_prod;
538 u16 rx_comp_cons;
539 u16 rx_sge_prod;
540 /* The last maximal completed SGE */
541 u16 last_max_sge;
542 __le16 *rx_cons_sb;
543 unsigned long rx_pkt,
544 rx_calls;
545
546 /* TPA related */
547 struct bnx2x_agg_info tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
548 u8 disable_tpa;
549 #ifdef BNX2X_STOP_ON_ERROR
550 u64 tpa_queue_used;
551 #endif
552
553 struct tstorm_per_queue_stats old_tclient;
554 struct ustorm_per_queue_stats old_uclient;
555 struct xstorm_per_queue_stats old_xclient;
556 struct bnx2x_eth_q_stats eth_q_stats;
557 struct bnx2x_eth_q_stats_old eth_q_stats_old;
558
559 /* The size is calculated using the following:
560 sizeof name field from netdev structure +
561 4 ('-Xx-' string) +
562 4 (for the digits and to make it DWORD aligned) */
563 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
564 char name[FP_NAME_SIZE];
565
566 /* MACs object */
567 struct bnx2x_vlan_mac_obj mac_obj;
568
569 /* Queue State object */
570 struct bnx2x_queue_sp_obj q_obj;
571
572 };
573
574 #define bnx2x_fp(bp, nr, var) (bp->fp[nr].var)
575
576 /* Use 2500 as a mini-jumbo MTU for FCoE */
577 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
578
579 /* FCoE L2 `fastpath' entry is right after the eth entries */
580 #define FCOE_IDX BNX2X_NUM_ETH_QUEUES(bp)
581 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX])
582 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
583 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
584 txdata[FIRST_TX_COS_INDEX].var)
585
586
587 #define IS_ETH_FP(fp) (fp->index < \
588 BNX2X_NUM_ETH_QUEUES(fp->bp))
589 #ifdef BCM_CNIC
590 #define IS_FCOE_FP(fp) (fp->index == FCOE_IDX)
591 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX)
592 #else
593 #define IS_FCOE_FP(fp) false
594 #define IS_FCOE_IDX(idx) false
595 #endif
596
597
598 /* MC hsi */
599 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
600 #define RX_COPY_THRESH 92
601
602 #define NUM_TX_RINGS 16
603 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
604 #define NEXT_PAGE_TX_DESC_CNT 1
605 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
606 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
607 #define MAX_TX_BD (NUM_TX_BD - 1)
608 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
609 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
610 (MAX_TX_DESC_CNT - 1)) ? \
611 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
612 (x) + 1)
613 #define TX_BD(x) ((x) & MAX_TX_BD)
614 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
615
616 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
617 #define NUM_RX_RINGS 8
618 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
619 #define NEXT_PAGE_RX_DESC_CNT 2
620 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
621 #define RX_DESC_MASK (RX_DESC_CNT - 1)
622 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
623 #define MAX_RX_BD (NUM_RX_BD - 1)
624 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
625
626 /* dropless fc calculations for BDs
627 *
628 * Number of BDs should as number of buffers in BRB:
629 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
630 * "next" elements on each page
631 */
632 #define NUM_BD_REQ BRB_SIZE(bp)
633 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
634 MAX_RX_DESC_CNT)
635 #define BD_TH_LO(bp) (NUM_BD_REQ + \
636 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
637 FW_DROP_LEVEL(bp))
638 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
639
640 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
641
642 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
643 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
644 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
645 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
646 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
647 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
648 MIN_RX_AVAIL))
649
650 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
651 (MAX_RX_DESC_CNT - 1)) ? \
652 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
653 (x) + 1)
654 #define RX_BD(x) ((x) & MAX_RX_BD)
655
656 /*
657 * As long as CQE is X times bigger than BD entry we have to allocate X times
658 * more pages for CQ ring in order to keep it balanced with BD ring
659 */
660 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
661 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
662 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
663 #define NEXT_PAGE_RCQ_DESC_CNT 1
664 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
665 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
666 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
667 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
668 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
669 (MAX_RCQ_DESC_CNT - 1)) ? \
670 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
671 (x) + 1)
672 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
673
674 /* dropless fc calculations for RCQs
675 *
676 * Number of RCQs should be as number of buffers in BRB:
677 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
678 * "next" elements on each page
679 */
680 #define NUM_RCQ_REQ BRB_SIZE(bp)
681 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
682 MAX_RCQ_DESC_CNT)
683 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
684 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
685 FW_DROP_LEVEL(bp))
686 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
687
688
689 /* This is needed for determining of last_max */
690 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
691 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
692
693
694 #define BNX2X_SWCID_SHIFT 17
695 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
696
697 /* used on a CID received from the HW */
698 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
699 #define CQE_CMD(x) (le32_to_cpu(x) >> \
700 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
701
702 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
703 le32_to_cpu((bd)->addr_lo))
704 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
705
706 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
707 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
708 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
709 #error "Min DB doorbell stride is 8"
710 #endif
711 #define DPM_TRIGER_TYPE 0x40
712 #define DOORBELL(bp, cid, val) \
713 do { \
714 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
715 DPM_TRIGER_TYPE); \
716 } while (0)
717
718
719 /* TX CSUM helpers */
720 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
721 skb->csum_offset)
722 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
723 skb->csum_offset))
724
725 #define pbd_tcp_flags(skb) (ntohl(tcp_flag_word(tcp_hdr(skb)))>>16 & 0xff)
726
727 #define XMIT_PLAIN 0
728 #define XMIT_CSUM_V4 0x1
729 #define XMIT_CSUM_V6 0x2
730 #define XMIT_CSUM_TCP 0x4
731 #define XMIT_GSO_V4 0x8
732 #define XMIT_GSO_V6 0x10
733
734 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6)
735 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6)
736
737
738 /* stuff added to make the code fit 80Col */
739 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
740 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
741 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
742 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
743 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
744
745 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
746
747 #define BNX2X_IP_CSUM_ERR(cqe) \
748 (!((cqe)->fast_path_cqe.status_flags & \
749 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG) && \
750 ((cqe)->fast_path_cqe.type_error_flags & \
751 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG))
752
753 #define BNX2X_L4_CSUM_ERR(cqe) \
754 (!((cqe)->fast_path_cqe.status_flags & \
755 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG) && \
756 ((cqe)->fast_path_cqe.type_error_flags & \
757 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
758
759 #define BNX2X_RX_CSUM_OK(cqe) \
760 (!(BNX2X_L4_CSUM_ERR(cqe) || BNX2X_IP_CSUM_ERR(cqe)))
761
762 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
763 (((le16_to_cpu(flags) & \
764 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
765 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
766 == PRS_FLAG_OVERETH_IPV4)
767 #define BNX2X_RX_SUM_FIX(cqe) \
768 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
769
770
771 #define FP_USB_FUNC_OFF \
772 offsetof(struct cstorm_status_block_u, func)
773 #define FP_CSB_FUNC_OFF \
774 offsetof(struct cstorm_status_block_c, func)
775
776 #define HC_INDEX_ETH_RX_CQ_CONS 1
777
778 #define HC_INDEX_OOO_TX_CQ_CONS 4
779
780 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
781
782 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
783
784 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
785
786 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
787
788 #define BNX2X_RX_SB_INDEX \
789 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
790
791 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
792
793 #define BNX2X_TX_SB_INDEX_COS0 \
794 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
795
796 /* end of fast path */
797
798 /* common */
799
800 struct bnx2x_common {
801
802 u32 chip_id;
803 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
804 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
805
806 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
807 #define CHIP_NUM_57710 0x164e
808 #define CHIP_NUM_57711 0x164f
809 #define CHIP_NUM_57711E 0x1650
810 #define CHIP_NUM_57712 0x1662
811 #define CHIP_NUM_57712_MF 0x1663
812 #define CHIP_NUM_57713 0x1651
813 #define CHIP_NUM_57713E 0x1652
814 #define CHIP_NUM_57800 0x168a
815 #define CHIP_NUM_57800_MF 0x16a5
816 #define CHIP_NUM_57810 0x168e
817 #define CHIP_NUM_57810_MF 0x16ae
818 #define CHIP_NUM_57840 0x168d
819 #define CHIP_NUM_57840_MF 0x16ab
820 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
821 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
822 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
823 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
824 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
825 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
826 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
827 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
828 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
829 #define CHIP_IS_57840(bp) (CHIP_NUM(bp) == CHIP_NUM_57840)
830 #define CHIP_IS_57840_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_MF)
831 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
832 CHIP_IS_57711E(bp))
833 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
834 CHIP_IS_57712_MF(bp))
835 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
836 CHIP_IS_57800_MF(bp) || \
837 CHIP_IS_57810(bp) || \
838 CHIP_IS_57810_MF(bp) || \
839 CHIP_IS_57840(bp) || \
840 CHIP_IS_57840_MF(bp))
841 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
842 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
843 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
844
845 #define CHIP_REV_SHIFT 12
846 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
847 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
848 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
849 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
850 /* assume maximum 5 revisions */
851 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
852 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
853 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
854 !(CHIP_REV_VAL(bp) & 0x00001000))
855 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
856 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
857 (CHIP_REV_VAL(bp) & 0x00001000))
858
859 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
860 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
861
862 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
863 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
864 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
865 (CHIP_REV_SHIFT + 1)) \
866 << CHIP_REV_SHIFT)
867 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
868 CHIP_REV_SIM(bp) :\
869 CHIP_REV_VAL(bp))
870 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
871 (CHIP_REV(bp) == CHIP_REV_Bx))
872 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
873 (CHIP_REV(bp) == CHIP_REV_Ax))
874
875 int flash_size;
876 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
877 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
878 #define BNX2X_NVRAM_PAGE_SIZE 256
879
880 u32 shmem_base;
881 u32 shmem2_base;
882 u32 mf_cfg_base;
883 u32 mf2_cfg_base;
884
885 u32 hw_config;
886
887 u32 bc_ver;
888
889 u8 int_block;
890 #define INT_BLOCK_HC 0
891 #define INT_BLOCK_IGU 1
892 #define INT_BLOCK_MODE_NORMAL 0
893 #define INT_BLOCK_MODE_BW_COMP 2
894 #define CHIP_INT_MODE_IS_NBC(bp) \
895 (!CHIP_IS_E1x(bp) && \
896 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
897 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
898
899 u8 chip_port_mode;
900 #define CHIP_4_PORT_MODE 0x0
901 #define CHIP_2_PORT_MODE 0x1
902 #define CHIP_PORT_MODE_NONE 0x2
903 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
904 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
905
906 u32 boot_mode;
907 };
908
909 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
910 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
911 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
912
913 /* end of common */
914
915 /* port */
916
917 struct bnx2x_port {
918 u32 pmf;
919
920 u32 link_config[LINK_CONFIG_SIZE];
921
922 u32 supported[LINK_CONFIG_SIZE];
923 /* link settings - missing defines */
924 #define SUPPORTED_2500baseX_Full (1 << 15)
925
926 u32 advertising[LINK_CONFIG_SIZE];
927 /* link settings - missing defines */
928 #define ADVERTISED_2500baseX_Full (1 << 15)
929
930 u32 phy_addr;
931
932 /* used to synchronize phy accesses */
933 struct mutex phy_mutex;
934 int need_hw_lock;
935
936 u32 port_stx;
937
938 struct nig_stats old_nig_stats;
939 };
940
941 /* end of port */
942
943 #define STATS_OFFSET32(stat_name) \
944 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
945
946 /* slow path */
947
948 /* slow path work-queue */
949 extern struct workqueue_struct *bnx2x_wq;
950
951 #define BNX2X_MAX_NUM_OF_VFS 64
952 #define BNX2X_VF_ID_INVALID 0xFF
953
954 /*
955 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
956 * control by the number of fast-path status blocks supported by the
957 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
958 * status block represents an independent interrupts context that can
959 * serve a regular L2 networking queue. However special L2 queues such
960 * as the FCoE queue do not require a FP-SB and other components like
961 * the CNIC may consume FP-SB reducing the number of possible L2 queues
962 *
963 * If the maximum number of FP-SB available is X then:
964 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
965 * regular L2 queues is Y=X-1
966 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
967 * c. If the FCoE L2 queue is supported the actual number of L2 queues
968 * is Y+1
969 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
970 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
971 * FP interrupt context for the CNIC).
972 * e. The number of HW context (CID count) is always X or X+1 if FCoE
973 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
974 */
975
976 /* fast-path interrupt contexts E1x */
977 #define FP_SB_MAX_E1x 16
978 /* fast-path interrupt contexts E2 */
979 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
980
981 union cdu_context {
982 struct eth_context eth;
983 char pad[1024];
984 };
985
986 /* CDU host DB constants */
987 #define CDU_ILT_PAGE_SZ_HW 3
988 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 64K */
989 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
990
991 #ifdef BCM_CNIC
992 #define CNIC_ISCSI_CID_MAX 256
993 #define CNIC_FCOE_CID_MAX 2048
994 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
995 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
996 #endif
997
998 #define QM_ILT_PAGE_SZ_HW 0
999 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1000 #define QM_CID_ROUND 1024
1001
1002 #ifdef BCM_CNIC
1003 /* TM (timers) host DB constants */
1004 #define TM_ILT_PAGE_SZ_HW 0
1005 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1006 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1007 #define TM_CONN_NUM 1024
1008 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1009 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1010
1011 /* SRC (Searcher) host DB constants */
1012 #define SRC_ILT_PAGE_SZ_HW 0
1013 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1014 #define SRC_HASH_BITS 10
1015 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1016 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1017 #define SRC_T2_SZ SRC_ILT_SZ
1018 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1019
1020 #endif
1021
1022 #define MAX_DMAE_C 8
1023
1024 /* DMA memory not used in fastpath */
1025 struct bnx2x_slowpath {
1026 union {
1027 struct mac_configuration_cmd e1x;
1028 struct eth_classify_rules_ramrod_data e2;
1029 } mac_rdata;
1030
1031
1032 union {
1033 struct tstorm_eth_mac_filter_config e1x;
1034 struct eth_filter_rules_ramrod_data e2;
1035 } rx_mode_rdata;
1036
1037 union {
1038 struct mac_configuration_cmd e1;
1039 struct eth_multicast_rules_ramrod_data e2;
1040 } mcast_rdata;
1041
1042 struct eth_rss_update_ramrod_data rss_rdata;
1043
1044 /* Queue State related ramrods are always sent under rtnl_lock */
1045 union {
1046 struct client_init_ramrod_data init_data;
1047 struct client_update_ramrod_data update_data;
1048 } q_rdata;
1049
1050 union {
1051 struct function_start_data func_start;
1052 /* pfc configuration for DCBX ramrod */
1053 struct flow_control_configuration pfc_config;
1054 } func_rdata;
1055
1056 /* used by dmae command executer */
1057 struct dmae_command dmae[MAX_DMAE_C];
1058
1059 u32 stats_comp;
1060 union mac_stats mac_stats;
1061 struct nig_stats nig_stats;
1062 struct host_port_stats port_stats;
1063 struct host_func_stats func_stats;
1064
1065 u32 wb_comp;
1066 u32 wb_data[4];
1067
1068 union drv_info_to_mcp drv_info_to_mcp;
1069 };
1070
1071 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1072 #define bnx2x_sp_mapping(bp, var) \
1073 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1074
1075
1076 /* attn group wiring */
1077 #define MAX_DYNAMIC_ATTN_GRPS 8
1078
1079 struct attn_route {
1080 u32 sig[5];
1081 };
1082
1083 struct iro {
1084 u32 base;
1085 u16 m1;
1086 u16 m2;
1087 u16 m3;
1088 u16 size;
1089 };
1090
1091 struct hw_context {
1092 union cdu_context *vcxt;
1093 dma_addr_t cxt_mapping;
1094 size_t size;
1095 };
1096
1097 /* forward */
1098 struct bnx2x_ilt;
1099
1100
1101 enum bnx2x_recovery_state {
1102 BNX2X_RECOVERY_DONE,
1103 BNX2X_RECOVERY_INIT,
1104 BNX2X_RECOVERY_WAIT,
1105 BNX2X_RECOVERY_FAILED,
1106 BNX2X_RECOVERY_NIC_LOADING
1107 };
1108
1109 /*
1110 * Event queue (EQ or event ring) MC hsi
1111 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1112 */
1113 #define NUM_EQ_PAGES 1
1114 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1115 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1116 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1117 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1118 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1119
1120 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1121 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1122 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1123
1124 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1125 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1126
1127 #define BNX2X_EQ_INDEX \
1128 (&bp->def_status_blk->sp_sb.\
1129 index_values[HC_SP_INDEX_EQ_CONS])
1130
1131 /* This is a data that will be used to create a link report message.
1132 * We will keep the data used for the last link report in order
1133 * to prevent reporting the same link parameters twice.
1134 */
1135 struct bnx2x_link_report_data {
1136 u16 line_speed; /* Effective line speed */
1137 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1138 };
1139
1140 enum {
1141 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1142 BNX2X_LINK_REPORT_LINK_DOWN,
1143 BNX2X_LINK_REPORT_RX_FC_ON,
1144 BNX2X_LINK_REPORT_TX_FC_ON,
1145 };
1146
1147 enum {
1148 BNX2X_PORT_QUERY_IDX,
1149 BNX2X_PF_QUERY_IDX,
1150 BNX2X_FCOE_QUERY_IDX,
1151 BNX2X_FIRST_QUEUE_QUERY_IDX,
1152 };
1153
1154 struct bnx2x_fw_stats_req {
1155 struct stats_query_header hdr;
1156 struct stats_query_entry query[FP_SB_MAX_E1x+
1157 BNX2X_FIRST_QUEUE_QUERY_IDX];
1158 };
1159
1160 struct bnx2x_fw_stats_data {
1161 struct stats_counter storm_counters;
1162 struct per_port_stats port;
1163 struct per_pf_stats pf;
1164 struct fcoe_statistics_params fcoe;
1165 struct per_queue_stats queue_stats[1];
1166 };
1167
1168 /* Public slow path states */
1169 enum {
1170 BNX2X_SP_RTNL_SETUP_TC,
1171 BNX2X_SP_RTNL_TX_TIMEOUT,
1172 BNX2X_SP_RTNL_FAN_FAILURE,
1173 };
1174
1175
1176 struct bnx2x_prev_path_list {
1177 u8 bus;
1178 u8 slot;
1179 u8 path;
1180 struct list_head list;
1181 };
1182
1183 struct bnx2x {
1184 /* Fields used in the tx and intr/napi performance paths
1185 * are grouped together in the beginning of the structure
1186 */
1187 struct bnx2x_fastpath *fp;
1188 void __iomem *regview;
1189 void __iomem *doorbells;
1190 u16 db_size;
1191
1192 u8 pf_num; /* absolute PF number */
1193 u8 pfid; /* per-path PF number */
1194 int base_fw_ndsb; /**/
1195 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1196 #define BP_PORT(bp) (bp->pfid & 1)
1197 #define BP_FUNC(bp) (bp->pfid)
1198 #define BP_ABS_FUNC(bp) (bp->pf_num)
1199 #define BP_VN(bp) ((bp)->pfid >> 1)
1200 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1201 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1202 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1203 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1204 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1205
1206 struct net_device *dev;
1207 struct pci_dev *pdev;
1208
1209 const struct iro *iro_arr;
1210 #define IRO (bp->iro_arr)
1211
1212 enum bnx2x_recovery_state recovery_state;
1213 int is_leader;
1214 struct msix_entry *msix_table;
1215
1216 int tx_ring_size;
1217
1218 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1219 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1220 #define ETH_MIN_PACKET_SIZE 60
1221 #define ETH_MAX_PACKET_SIZE 1500
1222 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1223 /* TCP with Timestamp Option (32) + IPv6 (40) */
1224 #define ETH_MAX_TPA_HEADER_SIZE 72
1225 #define ETH_MIN_TPA_HEADER_SIZE 40
1226
1227 /* Max supported alignment is 256 (8 shift) */
1228 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1229
1230 /* FW uses 2 Cache lines Alignment for start packet and size
1231 *
1232 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1233 * at the end of skb->data, to avoid wasting a full cache line.
1234 * This reduces memory use (skb->truesize).
1235 */
1236 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1237
1238 #define BNX2X_FW_RX_ALIGN_END \
1239 max(1UL << BNX2X_RX_ALIGN_SHIFT, \
1240 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1241
1242 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1243
1244 struct host_sp_status_block *def_status_blk;
1245 #define DEF_SB_IGU_ID 16
1246 #define DEF_SB_ID HC_SP_SB_ID
1247 __le16 def_idx;
1248 __le16 def_att_idx;
1249 u32 attn_state;
1250 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1251
1252 /* slow path ring */
1253 struct eth_spe *spq;
1254 dma_addr_t spq_mapping;
1255 u16 spq_prod_idx;
1256 struct eth_spe *spq_prod_bd;
1257 struct eth_spe *spq_last_bd;
1258 __le16 *dsb_sp_prod;
1259 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1260 /* used to synchronize spq accesses */
1261 spinlock_t spq_lock;
1262
1263 /* event queue */
1264 union event_ring_elem *eq_ring;
1265 dma_addr_t eq_mapping;
1266 u16 eq_prod;
1267 u16 eq_cons;
1268 __le16 *eq_cons_sb;
1269 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1270
1271
1272
1273 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1274 u16 stats_pending;
1275 /* Counter for completed statistics ramrods */
1276 u16 stats_comp;
1277
1278 /* End of fields used in the performance code paths */
1279
1280 int panic;
1281 int msg_enable;
1282
1283 u32 flags;
1284 #define PCIX_FLAG (1 << 0)
1285 #define PCI_32BIT_FLAG (1 << 1)
1286 #define ONE_PORT_FLAG (1 << 2)
1287 #define NO_WOL_FLAG (1 << 3)
1288 #define USING_DAC_FLAG (1 << 4)
1289 #define USING_MSIX_FLAG (1 << 5)
1290 #define USING_MSI_FLAG (1 << 6)
1291 #define DISABLE_MSI_FLAG (1 << 7)
1292 #define TPA_ENABLE_FLAG (1 << 8)
1293 #define NO_MCP_FLAG (1 << 9)
1294
1295 #define BP_NOMCP(bp) (bp->flags & NO_MCP_FLAG)
1296 #define GRO_ENABLE_FLAG (1 << 10)
1297 #define MF_FUNC_DIS (1 << 11)
1298 #define OWN_CNIC_IRQ (1 << 12)
1299 #define NO_ISCSI_OOO_FLAG (1 << 13)
1300 #define NO_ISCSI_FLAG (1 << 14)
1301 #define NO_FCOE_FLAG (1 << 15)
1302 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1303
1304 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1305 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1306 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1307
1308 int pm_cap;
1309 int mrrs;
1310
1311 struct delayed_work sp_task;
1312 struct delayed_work sp_rtnl_task;
1313
1314 struct delayed_work period_task;
1315 struct timer_list timer;
1316 int current_interval;
1317
1318 u16 fw_seq;
1319 u16 fw_drv_pulse_wr_seq;
1320 u32 func_stx;
1321
1322 struct link_params link_params;
1323 struct link_vars link_vars;
1324 u32 link_cnt;
1325 struct bnx2x_link_report_data last_reported_link;
1326
1327 struct mdio_if_info mdio;
1328
1329 struct bnx2x_common common;
1330 struct bnx2x_port port;
1331
1332 struct cmng_struct_per_port cmng;
1333 u32 vn_weight_sum;
1334 u32 mf_config[E1HVN_MAX];
1335 u32 mf2_config[E2_FUNC_MAX];
1336 u32 path_has_ovlan; /* E3 */
1337 u16 mf_ov;
1338 u8 mf_mode;
1339 #define IS_MF(bp) (bp->mf_mode != 0)
1340 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1341 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1342
1343 u8 wol;
1344
1345 bool gro_check;
1346
1347 int rx_ring_size;
1348
1349 u16 tx_quick_cons_trip_int;
1350 u16 tx_quick_cons_trip;
1351 u16 tx_ticks_int;
1352 u16 tx_ticks;
1353
1354 u16 rx_quick_cons_trip_int;
1355 u16 rx_quick_cons_trip;
1356 u16 rx_ticks_int;
1357 u16 rx_ticks;
1358 /* Maximal coalescing timeout in us */
1359 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1360
1361 u32 lin_cnt;
1362
1363 u16 state;
1364 #define BNX2X_STATE_CLOSED 0
1365 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1366 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1367 #define BNX2X_STATE_OPEN 0x3000
1368 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1369 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1370
1371 #define BNX2X_STATE_DIAG 0xe000
1372 #define BNX2X_STATE_ERROR 0xf000
1373
1374 int multi_mode;
1375 #define BNX2X_MAX_PRIORITY 8
1376 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1377 #define BNX2X_MAX_COS 3
1378 #define BNX2X_MAX_TX_COS 2
1379 int num_queues;
1380 int disable_tpa;
1381
1382 u32 rx_mode;
1383 #define BNX2X_RX_MODE_NONE 0
1384 #define BNX2X_RX_MODE_NORMAL 1
1385 #define BNX2X_RX_MODE_ALLMULTI 2
1386 #define BNX2X_RX_MODE_PROMISC 3
1387 #define BNX2X_MAX_MULTICAST 64
1388
1389 u8 igu_dsb_id;
1390 u8 igu_base_sb;
1391 u8 igu_sb_cnt;
1392 dma_addr_t def_status_blk_mapping;
1393
1394 struct bnx2x_slowpath *slowpath;
1395 dma_addr_t slowpath_mapping;
1396
1397 /* Total number of FW statistics requests */
1398 u8 fw_stats_num;
1399
1400 /*
1401 * This is a memory buffer that will contain both statistics
1402 * ramrod request and data.
1403 */
1404 void *fw_stats;
1405 dma_addr_t fw_stats_mapping;
1406
1407 /*
1408 * FW statistics request shortcut (points at the
1409 * beginning of fw_stats buffer).
1410 */
1411 struct bnx2x_fw_stats_req *fw_stats_req;
1412 dma_addr_t fw_stats_req_mapping;
1413 int fw_stats_req_sz;
1414
1415 /*
1416 * FW statistics data shortcut (points at the begining of
1417 * fw_stats buffer + fw_stats_req_sz).
1418 */
1419 struct bnx2x_fw_stats_data *fw_stats_data;
1420 dma_addr_t fw_stats_data_mapping;
1421 int fw_stats_data_sz;
1422
1423 struct hw_context context;
1424
1425 struct bnx2x_ilt *ilt;
1426 #define BP_ILT(bp) ((bp)->ilt)
1427 #define ILT_MAX_LINES 256
1428 /*
1429 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1430 * to CNIC.
1431 */
1432 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_PRESENT)
1433
1434 /*
1435 * Maximum CID count that might be required by the bnx2x:
1436 * Max Tss * Max_Tx_Multi_Cos + CNIC L2 Clients (FCoE and iSCSI related)
1437 */
1438 #define BNX2X_L2_CID_COUNT(bp) (MAX_TXQS_PER_COS * BNX2X_MULTI_TX_COS +\
1439 NON_ETH_CONTEXT_USE + CNIC_PRESENT)
1440 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1441 ILT_PAGE_CIDS))
1442 #define BNX2X_DB_SIZE(bp) (BNX2X_L2_CID_COUNT(bp) * (1 << BNX2X_DB_SHIFT))
1443
1444 int qm_cid_count;
1445
1446 int dropless_fc;
1447
1448 #ifdef BCM_CNIC
1449 u32 cnic_flags;
1450 #define BNX2X_CNIC_FLAG_MAC_SET 1
1451 void *t2;
1452 dma_addr_t t2_mapping;
1453 struct cnic_ops __rcu *cnic_ops;
1454 void *cnic_data;
1455 u32 cnic_tag;
1456 struct cnic_eth_dev cnic_eth_dev;
1457 union host_hc_status_block cnic_sb;
1458 dma_addr_t cnic_sb_mapping;
1459 struct eth_spe *cnic_kwq;
1460 struct eth_spe *cnic_kwq_prod;
1461 struct eth_spe *cnic_kwq_cons;
1462 struct eth_spe *cnic_kwq_last;
1463 u16 cnic_kwq_pending;
1464 u16 cnic_spq_pending;
1465 u8 fip_mac[ETH_ALEN];
1466 struct mutex cnic_mutex;
1467 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1468
1469 /* Start index of the "special" (CNIC related) L2 cleints */
1470 u8 cnic_base_cl_id;
1471 #endif
1472
1473 int dmae_ready;
1474 /* used to synchronize dmae accesses */
1475 spinlock_t dmae_lock;
1476
1477 /* used to protect the FW mail box */
1478 struct mutex fw_mb_mutex;
1479
1480 /* used to synchronize stats collecting */
1481 int stats_state;
1482
1483 /* used for synchronization of concurrent threads statistics handling */
1484 spinlock_t stats_lock;
1485
1486 /* used by dmae command loader */
1487 struct dmae_command stats_dmae;
1488 int executer_idx;
1489
1490 u16 stats_counter;
1491 struct bnx2x_eth_stats eth_stats;
1492 struct host_func_stats func_stats;
1493 struct bnx2x_eth_stats_old eth_stats_old;
1494 struct bnx2x_net_stats_old net_stats_old;
1495 struct bnx2x_fw_port_stats_old fw_stats_old;
1496 bool stats_init;
1497
1498 struct z_stream_s *strm;
1499 void *gunzip_buf;
1500 dma_addr_t gunzip_mapping;
1501 int gunzip_outlen;
1502 #define FW_BUF_SIZE 0x8000
1503 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1504 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1505 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1506
1507 struct raw_op *init_ops;
1508 /* Init blocks offsets inside init_ops */
1509 u16 *init_ops_offsets;
1510 /* Data blob - has 32 bit granularity */
1511 u32 *init_data;
1512 u32 init_mode_flags;
1513 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1514 /* Zipped PRAM blobs - raw data */
1515 const u8 *tsem_int_table_data;
1516 const u8 *tsem_pram_data;
1517 const u8 *usem_int_table_data;
1518 const u8 *usem_pram_data;
1519 const u8 *xsem_int_table_data;
1520 const u8 *xsem_pram_data;
1521 const u8 *csem_int_table_data;
1522 const u8 *csem_pram_data;
1523 #define INIT_OPS(bp) (bp->init_ops)
1524 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1525 #define INIT_DATA(bp) (bp->init_data)
1526 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1527 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1528 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1529 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1530 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1531 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1532 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1533 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1534
1535 #define PHY_FW_VER_LEN 20
1536 char fw_ver[32];
1537 const struct firmware *firmware;
1538
1539 /* DCB support on/off */
1540 u16 dcb_state;
1541 #define BNX2X_DCB_STATE_OFF 0
1542 #define BNX2X_DCB_STATE_ON 1
1543
1544 /* DCBX engine mode */
1545 int dcbx_enabled;
1546 #define BNX2X_DCBX_ENABLED_OFF 0
1547 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1548 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1549 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1550
1551 bool dcbx_mode_uset;
1552
1553 struct bnx2x_config_dcbx_params dcbx_config_params;
1554 struct bnx2x_dcbx_port_params dcbx_port_params;
1555 int dcb_version;
1556
1557 /* CAM credit pools */
1558 struct bnx2x_credit_pool_obj macs_pool;
1559
1560 /* RX_MODE object */
1561 struct bnx2x_rx_mode_obj rx_mode_obj;
1562
1563 /* MCAST object */
1564 struct bnx2x_mcast_obj mcast_obj;
1565
1566 /* RSS configuration object */
1567 struct bnx2x_rss_config_obj rss_conf_obj;
1568
1569 /* Function State controlling object */
1570 struct bnx2x_func_sp_obj func_obj;
1571
1572 unsigned long sp_state;
1573
1574 /* operation indication for the sp_rtnl task */
1575 unsigned long sp_rtnl_state;
1576
1577 /* DCBX Negotation results */
1578 struct dcbx_features dcbx_local_feat;
1579 u32 dcbx_error;
1580
1581 #ifdef BCM_DCBNL
1582 struct dcbx_features dcbx_remote_feat;
1583 u32 dcbx_remote_flags;
1584 #endif
1585 u32 pending_max;
1586
1587 /* multiple tx classes of service */
1588 u8 max_cos;
1589
1590 /* priority to cos mapping */
1591 u8 prio_to_cos[8];
1592 };
1593
1594 /* Tx queues may be less or equal to Rx queues */
1595 extern int num_queues;
1596 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1597 #define BNX2X_NUM_ETH_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - NON_ETH_CONTEXT_USE)
1598 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1599
1600 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1601
1602 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1603 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1604
1605 #define RSS_IPV4_CAP_MASK \
1606 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1607
1608 #define RSS_IPV4_TCP_CAP_MASK \
1609 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1610
1611 #define RSS_IPV6_CAP_MASK \
1612 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1613
1614 #define RSS_IPV6_TCP_CAP_MASK \
1615 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1616
1617 /* func init flags */
1618 #define FUNC_FLG_RSS 0x0001
1619 #define FUNC_FLG_STATS 0x0002
1620 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1621 #define FUNC_FLG_TPA 0x0008
1622 #define FUNC_FLG_SPQ 0x0010
1623 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1624
1625
1626 struct bnx2x_func_init_params {
1627 /* dma */
1628 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1629 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1630
1631 u16 func_flgs;
1632 u16 func_id; /* abs fid */
1633 u16 pf_id;
1634 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1635 };
1636
1637 #define for_each_eth_queue(bp, var) \
1638 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1639
1640 #define for_each_nondefault_eth_queue(bp, var) \
1641 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1642
1643 #define for_each_queue(bp, var) \
1644 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1645 if (skip_queue(bp, var)) \
1646 continue; \
1647 else
1648
1649 /* Skip forwarding FP */
1650 #define for_each_rx_queue(bp, var) \
1651 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1652 if (skip_rx_queue(bp, var)) \
1653 continue; \
1654 else
1655
1656 /* Skip OOO FP */
1657 #define for_each_tx_queue(bp, var) \
1658 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1659 if (skip_tx_queue(bp, var)) \
1660 continue; \
1661 else
1662
1663 #define for_each_nondefault_queue(bp, var) \
1664 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1665 if (skip_queue(bp, var)) \
1666 continue; \
1667 else
1668
1669 #define for_each_cos_in_tx_queue(fp, var) \
1670 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1671
1672 /* skip rx queue
1673 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1674 */
1675 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1676
1677 /* skip tx queue
1678 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1679 */
1680 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1681
1682 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1683
1684
1685
1686
1687 /**
1688 * bnx2x_set_mac_one - configure a single MAC address
1689 *
1690 * @bp: driver handle
1691 * @mac: MAC to configure
1692 * @obj: MAC object handle
1693 * @set: if 'true' add a new MAC, otherwise - delete
1694 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1695 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1696 *
1697 * Configures one MAC according to provided parameters or continues the
1698 * execution of previously scheduled commands if RAMROD_CONT is set in
1699 * ramrod_flags.
1700 *
1701 * Returns zero if operation has successfully completed, a positive value if the
1702 * operation has been successfully scheduled and a negative - if a requested
1703 * operations has failed.
1704 */
1705 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1706 struct bnx2x_vlan_mac_obj *obj, bool set,
1707 int mac_type, unsigned long *ramrod_flags);
1708 /**
1709 * Deletes all MACs configured for the specific MAC object.
1710 *
1711 * @param bp Function driver instance
1712 * @param mac_obj MAC object to cleanup
1713 *
1714 * @return zero if all MACs were cleaned
1715 */
1716
1717 /**
1718 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1719 *
1720 * @bp: driver handle
1721 * @mac_obj: MAC object handle
1722 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1723 * @wait_for_comp: if 'true' block until completion
1724 *
1725 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1726 *
1727 * Returns zero if operation has successfully completed, a positive value if the
1728 * operation has been successfully scheduled and a negative - if a requested
1729 * operations has failed.
1730 */
1731 int bnx2x_del_all_macs(struct bnx2x *bp,
1732 struct bnx2x_vlan_mac_obj *mac_obj,
1733 int mac_type, bool wait_for_comp);
1734
1735 /* Init Function API */
1736 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1737 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1738 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1739 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1740 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1741 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1742
1743
1744 /* dmae */
1745 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1746 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1747 u32 len32);
1748 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1749 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1750 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1751 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1752 bool with_comp, u8 comp_type);
1753
1754
1755 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1756 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1757 u32 data_hi, u32 data_lo, int cmd_type);
1758 void bnx2x_update_coalesce(struct bnx2x *bp);
1759 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1760
1761 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1762 int wait)
1763 {
1764 u32 val;
1765
1766 do {
1767 val = REG_RD(bp, reg);
1768 if (val == expected)
1769 break;
1770 ms -= wait;
1771 msleep(wait);
1772
1773 } while (ms > 0);
1774
1775 return val;
1776 }
1777
1778 #define BNX2X_ILT_ZALLOC(x, y, size) \
1779 do { \
1780 x = dma_alloc_coherent(&bp->pdev->dev, size, y, GFP_KERNEL); \
1781 if (x) \
1782 memset(x, 0, size); \
1783 } while (0)
1784
1785 #define BNX2X_ILT_FREE(x, y, size) \
1786 do { \
1787 if (x) { \
1788 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1789 x = NULL; \
1790 y = 0; \
1791 } \
1792 } while (0)
1793
1794 #define ILOG2(x) (ilog2((x)))
1795
1796 #define ILT_NUM_PAGE_ENTRIES (3072)
1797 /* In 57710/11 we use whole table since we have 8 func
1798 * In 57712 we have only 4 func, but use same size per func, then only half of
1799 * the table in use
1800 */
1801 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1802
1803 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1804 /*
1805 * the phys address is shifted right 12 bits and has an added
1806 * 1=valid bit added to the 53rd bit
1807 * then since this is a wide register(TM)
1808 * we split it into two 32 bit writes
1809 */
1810 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1811 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1812
1813 /* load/unload mode */
1814 #define LOAD_NORMAL 0
1815 #define LOAD_OPEN 1
1816 #define LOAD_DIAG 2
1817 #define UNLOAD_NORMAL 0
1818 #define UNLOAD_CLOSE 1
1819 #define UNLOAD_RECOVERY 2
1820
1821
1822 /* DMAE command defines */
1823 #define DMAE_TIMEOUT -1
1824 #define DMAE_PCI_ERROR -2 /* E2 and onward */
1825 #define DMAE_NOT_RDY -3
1826 #define DMAE_PCI_ERR_FLAG 0x80000000
1827
1828 #define DMAE_SRC_PCI 0
1829 #define DMAE_SRC_GRC 1
1830
1831 #define DMAE_DST_NONE 0
1832 #define DMAE_DST_PCI 1
1833 #define DMAE_DST_GRC 2
1834
1835 #define DMAE_COMP_PCI 0
1836 #define DMAE_COMP_GRC 1
1837
1838 /* E2 and onward - PCI error handling in the completion */
1839
1840 #define DMAE_COMP_REGULAR 0
1841 #define DMAE_COM_SET_ERR 1
1842
1843 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
1844 DMAE_COMMAND_SRC_SHIFT)
1845 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
1846 DMAE_COMMAND_SRC_SHIFT)
1847
1848 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
1849 DMAE_COMMAND_DST_SHIFT)
1850 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
1851 DMAE_COMMAND_DST_SHIFT)
1852
1853 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
1854 DMAE_COMMAND_C_DST_SHIFT)
1855 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
1856 DMAE_COMMAND_C_DST_SHIFT)
1857
1858 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
1859
1860 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
1861 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
1862 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
1863 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
1864
1865 #define DMAE_CMD_PORT_0 0
1866 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
1867
1868 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
1869 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
1870 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
1871
1872 #define DMAE_SRC_PF 0
1873 #define DMAE_SRC_VF 1
1874
1875 #define DMAE_DST_PF 0
1876 #define DMAE_DST_VF 1
1877
1878 #define DMAE_C_SRC 0
1879 #define DMAE_C_DST 1
1880
1881 #define DMAE_LEN32_RD_MAX 0x80
1882 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
1883
1884 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
1885 indicates eror */
1886
1887 #define MAX_DMAE_C_PER_PORT 8
1888 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1889 BP_VN(bp))
1890 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1891 E1HVN_MAX)
1892
1893 /* PCIE link and speed */
1894 #define PCICFG_LINK_WIDTH 0x1f00000
1895 #define PCICFG_LINK_WIDTH_SHIFT 20
1896 #define PCICFG_LINK_SPEED 0xf0000
1897 #define PCICFG_LINK_SPEED_SHIFT 16
1898
1899
1900 #define BNX2X_NUM_TESTS 7
1901
1902 #define BNX2X_PHY_LOOPBACK 0
1903 #define BNX2X_MAC_LOOPBACK 1
1904 #define BNX2X_PHY_LOOPBACK_FAILED 1
1905 #define BNX2X_MAC_LOOPBACK_FAILED 2
1906 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
1907 BNX2X_PHY_LOOPBACK_FAILED)
1908
1909
1910 #define STROM_ASSERT_ARRAY_SIZE 50
1911
1912
1913 /* must be used on a CID before placing it on a HW ring */
1914 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1915 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
1916 (x))
1917
1918 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1919 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1920
1921
1922 #define BNX2X_BTR 4
1923 #define MAX_SPQ_PENDING 8
1924
1925 /* CMNG constants, as derived from system spec calculations */
1926 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
1927 #define DEF_MIN_RATE 100
1928 /* resolution of the rate shaping timer - 400 usec */
1929 #define RS_PERIODIC_TIMEOUT_USEC 400
1930 /* number of bytes in single QM arbitration cycle -
1931 * coefficient for calculating the fairness timer */
1932 #define QM_ARB_BYTES 160000
1933 /* resolution of Min algorithm 1:100 */
1934 #define MIN_RES 100
1935 /* how many bytes above threshold for the minimal credit of Min algorithm*/
1936 #define MIN_ABOVE_THRESH 32768
1937 /* Fairness algorithm integration time coefficient -
1938 * for calculating the actual Tfair */
1939 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
1940 /* Memory of fairness algorithm . 2 cycles */
1941 #define FAIR_MEM 2
1942
1943
1944 #define ATTN_NIG_FOR_FUNC (1L << 8)
1945 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
1946 #define GPIO_2_FUNC (1L << 10)
1947 #define GPIO_3_FUNC (1L << 11)
1948 #define GPIO_4_FUNC (1L << 12)
1949 #define ATTN_GENERAL_ATTN_1 (1L << 13)
1950 #define ATTN_GENERAL_ATTN_2 (1L << 14)
1951 #define ATTN_GENERAL_ATTN_3 (1L << 15)
1952 #define ATTN_GENERAL_ATTN_4 (1L << 13)
1953 #define ATTN_GENERAL_ATTN_5 (1L << 14)
1954 #define ATTN_GENERAL_ATTN_6 (1L << 15)
1955
1956 #define ATTN_HARD_WIRED_MASK 0xff00
1957 #define ATTENTION_ID 4
1958
1959
1960 /* stuff added to make the code fit 80Col */
1961
1962 #define BNX2X_PMF_LINK_ASSERT \
1963 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
1964
1965 #define BNX2X_MC_ASSERT_BITS \
1966 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1967 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1968 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
1969 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
1970
1971 #define BNX2X_MCP_ASSERT \
1972 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
1973
1974 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
1975 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
1976 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
1977 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
1978 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
1979 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
1980 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
1981
1982 #define HW_INTERRUT_ASSERT_SET_0 \
1983 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
1984 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
1985 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
1986 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
1987 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
1988 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
1989 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
1990 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
1991 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
1992 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
1993 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
1994 #define HW_INTERRUT_ASSERT_SET_1 \
1995 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
1996 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
1997 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
1998 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
1999 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2000 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2001 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2002 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2003 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2004 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2005 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2006 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2007 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2008 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2009 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2010 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2011 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2012 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2013 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2014 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2015 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2016 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2017 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2018 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2019 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2020 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2021 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2022 #define HW_INTERRUT_ASSERT_SET_2 \
2023 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2024 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2025 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2026 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2027 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2028 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2029 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2030 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2031 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2032 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2033 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2034 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2035 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2036
2037 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2038 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2039 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2040 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2041
2042 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2043 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2044
2045 #define MULTI_MASK 0x7f
2046
2047
2048 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2049 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2050 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2051 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2052
2053 #define DEF_USB_IGU_INDEX_OFF \
2054 offsetof(struct cstorm_def_status_block_u, igu_index)
2055 #define DEF_CSB_IGU_INDEX_OFF \
2056 offsetof(struct cstorm_def_status_block_c, igu_index)
2057 #define DEF_XSB_IGU_INDEX_OFF \
2058 offsetof(struct xstorm_def_status_block, igu_index)
2059 #define DEF_TSB_IGU_INDEX_OFF \
2060 offsetof(struct tstorm_def_status_block, igu_index)
2061
2062 #define DEF_USB_SEGMENT_OFF \
2063 offsetof(struct cstorm_def_status_block_u, segment)
2064 #define DEF_CSB_SEGMENT_OFF \
2065 offsetof(struct cstorm_def_status_block_c, segment)
2066 #define DEF_XSB_SEGMENT_OFF \
2067 offsetof(struct xstorm_def_status_block, segment)
2068 #define DEF_TSB_SEGMENT_OFF \
2069 offsetof(struct tstorm_def_status_block, segment)
2070
2071 #define BNX2X_SP_DSB_INDEX \
2072 (&bp->def_status_blk->sp_sb.\
2073 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2074
2075 #define SET_FLAG(value, mask, flag) \
2076 do {\
2077 (value) &= ~(mask);\
2078 (value) |= ((flag) << (mask##_SHIFT));\
2079 } while (0)
2080
2081 #define GET_FLAG(value, mask) \
2082 (((value) & (mask)) >> (mask##_SHIFT))
2083
2084 #define GET_FIELD(value, fname) \
2085 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2086
2087 #define CAM_IS_INVALID(x) \
2088 (GET_FLAG(x.flags, \
2089 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2090 (T_ETH_MAC_COMMAND_INVALIDATE))
2091
2092 /* Number of u32 elements in MC hash array */
2093 #define MC_HASH_SIZE 8
2094 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2095 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2096
2097
2098 #ifndef PXP2_REG_PXP2_INT_STS
2099 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2100 #endif
2101
2102 #ifndef ETH_MAX_RX_CLIENTS_E2
2103 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2104 #endif
2105
2106 #define BNX2X_VPD_LEN 128
2107 #define VENDOR_ID_LEN 4
2108
2109 /* Congestion management fairness mode */
2110 #define CMNG_FNS_NONE 0
2111 #define CMNG_FNS_MINMAX 1
2112
2113 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2114 #define HC_SEG_ACCESS_ATTN 4
2115 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2116
2117 static const u32 dmae_reg_go_c[] = {
2118 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2119 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2120 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2121 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2122 };
2123
2124 void bnx2x_set_ethtool_ops(struct net_device *netdev);
2125 void bnx2x_notify_link_changed(struct bnx2x *bp);
2126
2127
2128 #define BNX2X_MF_SD_PROTOCOL(bp) \
2129 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2130
2131 #ifdef BCM_CNIC
2132 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2133 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2134
2135 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2136 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2137
2138 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2139 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2140
2141 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2142 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2143 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2144 #endif
2145
2146 #endif /* bnx2x.h */
Linux kernel - Deliverables
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