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bnx2x: Add Private Flags Support
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x.h
1 /* bnx2x.h: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 */
13
14 #ifndef BNX2X_H
15 #define BNX2X_H
16
17 #include <linux/pci.h>
18 #include <linux/netdevice.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/types.h>
21 #include <linux/pci_regs.h>
22
23 /* compilation time flags */
24
25 /* define this to make the driver freeze on error to allow getting debug info
26 * (you will need to reboot afterwards) */
27 /* #define BNX2X_STOP_ON_ERROR */
28
29 #define DRV_MODULE_VERSION "1.78.17-0"
30 #define DRV_MODULE_RELDATE "2013/04/11"
31 #define BNX2X_BC_VER 0x040200
32
33 #if defined(CONFIG_DCB)
34 #define BCM_DCBNL
35 #endif
36
37
38 #include "bnx2x_hsi.h"
39
40 #include "../cnic_if.h"
41
42
43 #define BNX2X_MIN_MSIX_VEC_CNT(bp) ((bp)->min_msix_vec_cnt)
44
45 #include <linux/mdio.h>
46
47 #include "bnx2x_reg.h"
48 #include "bnx2x_fw_defs.h"
49 #include "bnx2x_mfw_req.h"
50 #include "bnx2x_link.h"
51 #include "bnx2x_sp.h"
52 #include "bnx2x_dcb.h"
53 #include "bnx2x_stats.h"
54 #include "bnx2x_vfpf.h"
55
56 enum bnx2x_int_mode {
57 BNX2X_INT_MODE_MSIX,
58 BNX2X_INT_MODE_INTX,
59 BNX2X_INT_MODE_MSI
60 };
61
62 /* error/debug prints */
63
64 #define DRV_MODULE_NAME "bnx2x"
65
66 /* for messages that are currently off */
67 #define BNX2X_MSG_OFF 0x0
68 #define BNX2X_MSG_MCP 0x0010000 /* was: NETIF_MSG_HW */
69 #define BNX2X_MSG_STATS 0x0020000 /* was: NETIF_MSG_TIMER */
70 #define BNX2X_MSG_NVM 0x0040000 /* was: NETIF_MSG_HW */
71 #define BNX2X_MSG_DMAE 0x0080000 /* was: NETIF_MSG_HW */
72 #define BNX2X_MSG_SP 0x0100000 /* was: NETIF_MSG_INTR */
73 #define BNX2X_MSG_FP 0x0200000 /* was: NETIF_MSG_INTR */
74 #define BNX2X_MSG_IOV 0x0800000
75 #define BNX2X_MSG_IDLE 0x2000000 /* used for idle check*/
76 #define BNX2X_MSG_ETHTOOL 0x4000000
77 #define BNX2X_MSG_DCB 0x8000000
78
79 /* regular debug print */
80 #define DP(__mask, fmt, ...) \
81 do { \
82 if (unlikely(bp->msg_enable & (__mask))) \
83 pr_notice("[%s:%d(%s)]" fmt, \
84 __func__, __LINE__, \
85 bp->dev ? (bp->dev->name) : "?", \
86 ##__VA_ARGS__); \
87 } while (0)
88
89 #define DP_CONT(__mask, fmt, ...) \
90 do { \
91 if (unlikely(bp->msg_enable & (__mask))) \
92 pr_cont(fmt, ##__VA_ARGS__); \
93 } while (0)
94
95 /* errors debug print */
96 #define BNX2X_DBG_ERR(fmt, ...) \
97 do { \
98 if (unlikely(netif_msg_probe(bp))) \
99 pr_err("[%s:%d(%s)]" fmt, \
100 __func__, __LINE__, \
101 bp->dev ? (bp->dev->name) : "?", \
102 ##__VA_ARGS__); \
103 } while (0)
104
105 /* for errors (never masked) */
106 #define BNX2X_ERR(fmt, ...) \
107 do { \
108 pr_err("[%s:%d(%s)]" fmt, \
109 __func__, __LINE__, \
110 bp->dev ? (bp->dev->name) : "?", \
111 ##__VA_ARGS__); \
112 } while (0)
113
114 #define BNX2X_ERROR(fmt, ...) \
115 pr_err("[%s:%d]" fmt, __func__, __LINE__, ##__VA_ARGS__)
116
117
118 /* before we have a dev->name use dev_info() */
119 #define BNX2X_DEV_INFO(fmt, ...) \
120 do { \
121 if (unlikely(netif_msg_probe(bp))) \
122 dev_info(&bp->pdev->dev, fmt, ##__VA_ARGS__); \
123 } while (0)
124
125 /* Error handling */
126 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int);
127 #ifdef BNX2X_STOP_ON_ERROR
128 #define bnx2x_panic() \
129 do { \
130 bp->panic = 1; \
131 BNX2X_ERR("driver assert\n"); \
132 bnx2x_panic_dump(bp, true); \
133 } while (0)
134 #else
135 #define bnx2x_panic() \
136 do { \
137 bp->panic = 1; \
138 BNX2X_ERR("driver assert\n"); \
139 bnx2x_panic_dump(bp, false); \
140 } while (0)
141 #endif
142
143 #define bnx2x_mc_addr(ha) ((ha)->addr)
144 #define bnx2x_uc_addr(ha) ((ha)->addr)
145
146 #define U64_LO(x) ((u32)(((u64)(x)) & 0xffffffff))
147 #define U64_HI(x) ((u32)(((u64)(x)) >> 32))
148 #define HILO_U64(hi, lo) ((((u64)(hi)) << 32) + (lo))
149
150
151 #define REG_ADDR(bp, offset) ((bp->regview) + (offset))
152
153 #define REG_RD(bp, offset) readl(REG_ADDR(bp, offset))
154 #define REG_RD8(bp, offset) readb(REG_ADDR(bp, offset))
155 #define REG_RD16(bp, offset) readw(REG_ADDR(bp, offset))
156
157 #define REG_WR(bp, offset, val) writel((u32)val, REG_ADDR(bp, offset))
158 #define REG_WR8(bp, offset, val) writeb((u8)val, REG_ADDR(bp, offset))
159 #define REG_WR16(bp, offset, val) writew((u16)val, REG_ADDR(bp, offset))
160
161 #define REG_RD_IND(bp, offset) bnx2x_reg_rd_ind(bp, offset)
162 #define REG_WR_IND(bp, offset, val) bnx2x_reg_wr_ind(bp, offset, val)
163
164 #define REG_RD_DMAE(bp, offset, valp, len32) \
165 do { \
166 bnx2x_read_dmae(bp, offset, len32);\
167 memcpy(valp, bnx2x_sp(bp, wb_data[0]), (len32) * 4); \
168 } while (0)
169
170 #define REG_WR_DMAE(bp, offset, valp, len32) \
171 do { \
172 memcpy(bnx2x_sp(bp, wb_data[0]), valp, (len32) * 4); \
173 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data), \
174 offset, len32); \
175 } while (0)
176
177 #define REG_WR_DMAE_LEN(bp, offset, valp, len32) \
178 REG_WR_DMAE(bp, offset, valp, len32)
179
180 #define VIRT_WR_DMAE_LEN(bp, data, addr, len32, le32_swap) \
181 do { \
182 memcpy(GUNZIP_BUF(bp), data, (len32) * 4); \
183 bnx2x_write_big_buf_wb(bp, addr, len32); \
184 } while (0)
185
186 #define SHMEM_ADDR(bp, field) (bp->common.shmem_base + \
187 offsetof(struct shmem_region, field))
188 #define SHMEM_RD(bp, field) REG_RD(bp, SHMEM_ADDR(bp, field))
189 #define SHMEM_WR(bp, field, val) REG_WR(bp, SHMEM_ADDR(bp, field), val)
190
191 #define SHMEM2_ADDR(bp, field) (bp->common.shmem2_base + \
192 offsetof(struct shmem2_region, field))
193 #define SHMEM2_RD(bp, field) REG_RD(bp, SHMEM2_ADDR(bp, field))
194 #define SHMEM2_WR(bp, field, val) REG_WR(bp, SHMEM2_ADDR(bp, field), val)
195 #define MF_CFG_ADDR(bp, field) (bp->common.mf_cfg_base + \
196 offsetof(struct mf_cfg, field))
197 #define MF2_CFG_ADDR(bp, field) (bp->common.mf2_cfg_base + \
198 offsetof(struct mf2_cfg, field))
199
200 #define MF_CFG_RD(bp, field) REG_RD(bp, MF_CFG_ADDR(bp, field))
201 #define MF_CFG_WR(bp, field, val) REG_WR(bp,\
202 MF_CFG_ADDR(bp, field), (val))
203 #define MF2_CFG_RD(bp, field) REG_RD(bp, MF2_CFG_ADDR(bp, field))
204
205 #define SHMEM2_HAS(bp, field) ((bp)->common.shmem2_base && \
206 (SHMEM2_RD((bp), size) > \
207 offsetof(struct shmem2_region, field)))
208
209 #define EMAC_RD(bp, reg) REG_RD(bp, emac_base + reg)
210 #define EMAC_WR(bp, reg, val) REG_WR(bp, emac_base + reg, val)
211
212 /* SP SB indices */
213
214 /* General SP events - stats query, cfc delete, etc */
215 #define HC_SP_INDEX_ETH_DEF_CONS 3
216
217 /* EQ completions */
218 #define HC_SP_INDEX_EQ_CONS 7
219
220 /* FCoE L2 connection completions */
221 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
222 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
223 /* iSCSI L2 */
224 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
225 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
226
227 /* Special clients parameters */
228
229 /* SB indices */
230 /* FCoE L2 */
231 #define BNX2X_FCOE_L2_RX_INDEX \
232 (&bp->def_status_blk->sp_sb.\
233 index_values[HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS])
234
235 #define BNX2X_FCOE_L2_TX_INDEX \
236 (&bp->def_status_blk->sp_sb.\
237 index_values[HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS])
238
239 /**
240 * CIDs and CLIDs:
241 * CLIDs below is a CLID for func 0, then the CLID for other
242 * functions will be calculated by the formula:
243 *
244 * FUNC_N_CLID_X = N * NUM_SPECIAL_CLIENTS + FUNC_0_CLID_X
245 *
246 */
247 enum {
248 BNX2X_ISCSI_ETH_CL_ID_IDX,
249 BNX2X_FCOE_ETH_CL_ID_IDX,
250 BNX2X_MAX_CNIC_ETH_CL_ID_IDX,
251 };
252
253 #define BNX2X_CNIC_START_ETH_CID(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) *\
254 (bp)->max_cos)
255 /* iSCSI L2 */
256 #define BNX2X_ISCSI_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp))
257 /* FCoE L2 */
258 #define BNX2X_FCOE_ETH_CID(bp) (BNX2X_CNIC_START_ETH_CID(bp) + 1)
259
260 #define CNIC_SUPPORT(bp) ((bp)->cnic_support)
261 #define CNIC_ENABLED(bp) ((bp)->cnic_enabled)
262 #define CNIC_LOADED(bp) ((bp)->cnic_loaded)
263 #define FCOE_INIT(bp) ((bp)->fcoe_init)
264
265 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
266 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
267
268 #define SM_RX_ID 0
269 #define SM_TX_ID 1
270
271 /* defines for multiple tx priority indices */
272 #define FIRST_TX_ONLY_COS_INDEX 1
273 #define FIRST_TX_COS_INDEX 0
274
275 /* rules for calculating the cids of tx-only connections */
276 #define CID_TO_FP(cid, bp) ((cid) % BNX2X_NUM_NON_CNIC_QUEUES(bp))
277 #define CID_COS_TO_TX_ONLY_CID(cid, cos, bp) \
278 (cid + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
279
280 /* fp index inside class of service range */
281 #define FP_COS_TO_TXQ(fp, cos, bp) \
282 ((fp)->index + cos * BNX2X_NUM_NON_CNIC_QUEUES(bp))
283
284 /* Indexes for transmission queues array:
285 * txdata for RSS i CoS j is at location i + (j * num of RSS)
286 * txdata for FCoE (if exist) is at location max cos * num of RSS
287 * txdata for FWD (if exist) is one location after FCoE
288 * txdata for OOO (if exist) is one location after FWD
289 */
290 enum {
291 FCOE_TXQ_IDX_OFFSET,
292 FWD_TXQ_IDX_OFFSET,
293 OOO_TXQ_IDX_OFFSET,
294 };
295 #define MAX_ETH_TXQ_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) * (bp)->max_cos)
296 #define FCOE_TXQ_IDX(bp) (MAX_ETH_TXQ_IDX(bp) + FCOE_TXQ_IDX_OFFSET)
297
298 /* fast path */
299 /*
300 * This driver uses new build_skb() API :
301 * RX ring buffer contains pointer to kmalloc() data only,
302 * skb are built only after Hardware filled the frame.
303 */
304 struct sw_rx_bd {
305 u8 *data;
306 DEFINE_DMA_UNMAP_ADDR(mapping);
307 };
308
309 struct sw_tx_bd {
310 struct sk_buff *skb;
311 u16 first_bd;
312 u8 flags;
313 /* Set on the first BD descriptor when there is a split BD */
314 #define BNX2X_TSO_SPLIT_BD (1<<0)
315 };
316
317 struct sw_rx_page {
318 struct page *page;
319 DEFINE_DMA_UNMAP_ADDR(mapping);
320 };
321
322 union db_prod {
323 struct doorbell_set_prod data;
324 u32 raw;
325 };
326
327 /* dropless fc FW/HW related params */
328 #define BRB_SIZE(bp) (CHIP_IS_E3(bp) ? 1024 : 512)
329 #define MAX_AGG_QS(bp) (CHIP_IS_E1(bp) ? \
330 ETH_MAX_AGGREGATION_QUEUES_E1 :\
331 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
332 #define FW_DROP_LEVEL(bp) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(bp))
333 #define FW_PREFETCH_CNT 16
334 #define DROPLESS_FC_HEADROOM 100
335
336 /* MC hsi */
337 #define BCM_PAGE_SHIFT 12
338 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
339 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
340 #define BCM_PAGE_ALIGN(addr) (((addr) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
341
342 #define PAGES_PER_SGE_SHIFT 0
343 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
344 #define SGE_PAGE_SIZE PAGE_SIZE
345 #define SGE_PAGE_SHIFT PAGE_SHIFT
346 #define SGE_PAGE_ALIGN(addr) PAGE_ALIGN((typeof(PAGE_SIZE))(addr))
347 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
348 #define TPA_AGG_SIZE min_t(u32, (min_t(u32, 8, MAX_SKB_FRAGS) * \
349 SGE_PAGES), 0xffff)
350
351 /* SGE ring related macros */
352 #define NUM_RX_SGE_PAGES 2
353 #define RX_SGE_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
354 #define NEXT_PAGE_SGE_DESC_CNT 2
355 #define MAX_RX_SGE_CNT (RX_SGE_CNT - NEXT_PAGE_SGE_DESC_CNT)
356 /* RX_SGE_CNT is promised to be a power of 2 */
357 #define RX_SGE_MASK (RX_SGE_CNT - 1)
358 #define NUM_RX_SGE (RX_SGE_CNT * NUM_RX_SGE_PAGES)
359 #define MAX_RX_SGE (NUM_RX_SGE - 1)
360 #define NEXT_SGE_IDX(x) ((((x) & RX_SGE_MASK) == \
361 (MAX_RX_SGE_CNT - 1)) ? \
362 (x) + 1 + NEXT_PAGE_SGE_DESC_CNT : \
363 (x) + 1)
364 #define RX_SGE(x) ((x) & MAX_RX_SGE)
365
366 /*
367 * Number of required SGEs is the sum of two:
368 * 1. Number of possible opened aggregations (next packet for
369 * these aggregations will probably consume SGE immidiatelly)
370 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
371 * after placement on BD for new TPA aggregation)
372 *
373 * Takes into account NEXT_PAGE_SGE_DESC_CNT "next" elements on each page
374 */
375 #define NUM_SGE_REQ (MAX_AGG_QS(bp) + \
376 (BRB_SIZE(bp) - MAX_AGG_QS(bp)) / 2)
377 #define NUM_SGE_PG_REQ ((NUM_SGE_REQ + MAX_RX_SGE_CNT - 1) / \
378 MAX_RX_SGE_CNT)
379 #define SGE_TH_LO(bp) (NUM_SGE_REQ + \
380 NUM_SGE_PG_REQ * NEXT_PAGE_SGE_DESC_CNT)
381 #define SGE_TH_HI(bp) (SGE_TH_LO(bp) + DROPLESS_FC_HEADROOM)
382
383 /* Manipulate a bit vector defined as an array of u64 */
384
385 /* Number of bits in one sge_mask array element */
386 #define BIT_VEC64_ELEM_SZ 64
387 #define BIT_VEC64_ELEM_SHIFT 6
388 #define BIT_VEC64_ELEM_MASK ((u64)BIT_VEC64_ELEM_SZ - 1)
389
390
391 #define __BIT_VEC64_SET_BIT(el, bit) \
392 do { \
393 el = ((el) | ((u64)0x1 << (bit))); \
394 } while (0)
395
396 #define __BIT_VEC64_CLEAR_BIT(el, bit) \
397 do { \
398 el = ((el) & (~((u64)0x1 << (bit)))); \
399 } while (0)
400
401
402 #define BIT_VEC64_SET_BIT(vec64, idx) \
403 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
404 (idx) & BIT_VEC64_ELEM_MASK)
405
406 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \
407 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \
408 (idx) & BIT_VEC64_ELEM_MASK)
409
410 #define BIT_VEC64_TEST_BIT(vec64, idx) \
411 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \
412 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1)
413
414 /* Creates a bitmask of all ones in less significant bits.
415 idx - index of the most significant bit in the created mask */
416 #define BIT_VEC64_ONES_MASK(idx) \
417 (((u64)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1)
418 #define BIT_VEC64_ELEM_ONE_MASK ((u64)(~0))
419
420 /*******************************************************/
421
422
423
424 /* Number of u64 elements in SGE mask array */
425 #define RX_SGE_MASK_LEN (NUM_RX_SGE / BIT_VEC64_ELEM_SZ)
426 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
427 #define NEXT_SGE_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
428
429 union host_hc_status_block {
430 /* pointer to fp status block e1x */
431 struct host_hc_status_block_e1x *e1x_sb;
432 /* pointer to fp status block e2 */
433 struct host_hc_status_block_e2 *e2_sb;
434 };
435
436 struct bnx2x_agg_info {
437 /*
438 * First aggregation buffer is a data buffer, the following - are pages.
439 * We will preallocate the data buffer for each aggregation when
440 * we open the interface and will replace the BD at the consumer
441 * with this one when we receive the TPA_START CQE in order to
442 * keep the Rx BD ring consistent.
443 */
444 struct sw_rx_bd first_buf;
445 u8 tpa_state;
446 #define BNX2X_TPA_START 1
447 #define BNX2X_TPA_STOP 2
448 #define BNX2X_TPA_ERROR 3
449 u8 placement_offset;
450 u16 parsing_flags;
451 u16 vlan_tag;
452 u16 len_on_bd;
453 u32 rxhash;
454 bool l4_rxhash;
455 u16 gro_size;
456 u16 full_page;
457 };
458
459 #define Q_STATS_OFFSET32(stat_name) \
460 (offsetof(struct bnx2x_eth_q_stats, stat_name) / 4)
461
462 struct bnx2x_fp_txdata {
463
464 struct sw_tx_bd *tx_buf_ring;
465
466 union eth_tx_bd_types *tx_desc_ring;
467 dma_addr_t tx_desc_mapping;
468
469 u32 cid;
470
471 union db_prod tx_db;
472
473 u16 tx_pkt_prod;
474 u16 tx_pkt_cons;
475 u16 tx_bd_prod;
476 u16 tx_bd_cons;
477
478 unsigned long tx_pkt;
479
480 __le16 *tx_cons_sb;
481
482 int txq_index;
483 struct bnx2x_fastpath *parent_fp;
484 int tx_ring_size;
485 };
486
487 enum bnx2x_tpa_mode_t {
488 TPA_MODE_LRO,
489 TPA_MODE_GRO
490 };
491
492 struct bnx2x_fastpath {
493 struct bnx2x *bp; /* parent */
494
495 struct napi_struct napi;
496 union host_hc_status_block status_blk;
497 /* chip independed shortcuts into sb structure */
498 __le16 *sb_index_values;
499 __le16 *sb_running_index;
500 /* chip independed shortcut into rx_prods_offset memory */
501 u32 ustorm_rx_prods_offset;
502
503 u32 rx_buf_size;
504 u32 rx_frag_size; /* 0 if kmalloced(), or rx_buf_size + NET_SKB_PAD */
505 dma_addr_t status_blk_mapping;
506
507 enum bnx2x_tpa_mode_t mode;
508
509 u8 max_cos; /* actual number of active tx coses */
510 struct bnx2x_fp_txdata *txdata_ptr[BNX2X_MULTI_TX_COS];
511
512 struct sw_rx_bd *rx_buf_ring; /* BDs mappings ring */
513 struct sw_rx_page *rx_page_ring; /* SGE pages mappings ring */
514
515 struct eth_rx_bd *rx_desc_ring;
516 dma_addr_t rx_desc_mapping;
517
518 union eth_rx_cqe *rx_comp_ring;
519 dma_addr_t rx_comp_mapping;
520
521 /* SGE ring */
522 struct eth_rx_sge *rx_sge_ring;
523 dma_addr_t rx_sge_mapping;
524
525 u64 sge_mask[RX_SGE_MASK_LEN];
526
527 u32 cid;
528
529 __le16 fp_hc_idx;
530
531 u8 index; /* number in fp array */
532 u8 rx_queue; /* index for skb_record */
533 u8 cl_id; /* eth client id */
534 u8 cl_qzone_id;
535 u8 fw_sb_id; /* status block number in FW */
536 u8 igu_sb_id; /* status block number in HW */
537
538 u16 rx_bd_prod;
539 u16 rx_bd_cons;
540 u16 rx_comp_prod;
541 u16 rx_comp_cons;
542 u16 rx_sge_prod;
543 /* The last maximal completed SGE */
544 u16 last_max_sge;
545 __le16 *rx_cons_sb;
546 unsigned long rx_pkt,
547 rx_calls;
548
549 /* TPA related */
550 struct bnx2x_agg_info *tpa_info;
551 u8 disable_tpa;
552 #ifdef BNX2X_STOP_ON_ERROR
553 u64 tpa_queue_used;
554 #endif
555 /* The size is calculated using the following:
556 sizeof name field from netdev structure +
557 4 ('-Xx-' string) +
558 4 (for the digits and to make it DWORD aligned) */
559 #define FP_NAME_SIZE (sizeof(((struct net_device *)0)->name) + 8)
560 char name[FP_NAME_SIZE];
561 };
562
563 #define bnx2x_fp(bp, nr, var) ((bp)->fp[(nr)].var)
564 #define bnx2x_sp_obj(bp, fp) ((bp)->sp_objs[(fp)->index])
565 #define bnx2x_fp_stats(bp, fp) (&((bp)->fp_stats[(fp)->index]))
566 #define bnx2x_fp_qstats(bp, fp) (&((bp)->fp_stats[(fp)->index].eth_q_stats))
567
568 /* Use 2500 as a mini-jumbo MTU for FCoE */
569 #define BNX2X_FCOE_MINI_JUMBO_MTU 2500
570
571 #define FCOE_IDX_OFFSET 0
572
573 #define FCOE_IDX(bp) (BNX2X_NUM_NON_CNIC_QUEUES(bp) + \
574 FCOE_IDX_OFFSET)
575 #define bnx2x_fcoe_fp(bp) (&bp->fp[FCOE_IDX(bp)])
576 #define bnx2x_fcoe(bp, var) (bnx2x_fcoe_fp(bp)->var)
577 #define bnx2x_fcoe_inner_sp_obj(bp) (&bp->sp_objs[FCOE_IDX(bp)])
578 #define bnx2x_fcoe_sp_obj(bp, var) (bnx2x_fcoe_inner_sp_obj(bp)->var)
579 #define bnx2x_fcoe_tx(bp, var) (bnx2x_fcoe_fp(bp)-> \
580 txdata_ptr[FIRST_TX_COS_INDEX] \
581 ->var)
582
583
584 #define IS_ETH_FP(fp) ((fp)->index < BNX2X_NUM_ETH_QUEUES((fp)->bp))
585 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->bp))
586 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(bp))
587
588
589 /* MC hsi */
590 #define MAX_FETCH_BD 13 /* HW max BDs per packet */
591 #define RX_COPY_THRESH 92
592
593 #define NUM_TX_RINGS 16
594 #define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
595 #define NEXT_PAGE_TX_DESC_CNT 1
596 #define MAX_TX_DESC_CNT (TX_DESC_CNT - NEXT_PAGE_TX_DESC_CNT)
597 #define NUM_TX_BD (TX_DESC_CNT * NUM_TX_RINGS)
598 #define MAX_TX_BD (NUM_TX_BD - 1)
599 #define MAX_TX_AVAIL (MAX_TX_DESC_CNT * NUM_TX_RINGS - 2)
600 #define NEXT_TX_IDX(x) ((((x) & MAX_TX_DESC_CNT) == \
601 (MAX_TX_DESC_CNT - 1)) ? \
602 (x) + 1 + NEXT_PAGE_TX_DESC_CNT : \
603 (x) + 1)
604 #define TX_BD(x) ((x) & MAX_TX_BD)
605 #define TX_BD_POFF(x) ((x) & MAX_TX_DESC_CNT)
606
607 /* number of NEXT_PAGE descriptors may be required during placement */
608 #define NEXT_CNT_PER_TX_PKT(bds) \
609 (((bds) + MAX_TX_DESC_CNT - 1) / \
610 MAX_TX_DESC_CNT * NEXT_PAGE_TX_DESC_CNT)
611 /* max BDs per tx packet w/o next_pages:
612 * START_BD - describes packed
613 * START_BD(splitted) - includes unpaged data segment for GSO
614 * PARSING_BD - for TSO and CSUM data
615 * PARSING_BD2 - for encapsulation data
616 * Frag BDs - decribes pages for frags
617 */
618 #define BDS_PER_TX_PKT 4
619 #define MAX_BDS_PER_TX_PKT (MAX_SKB_FRAGS + BDS_PER_TX_PKT)
620 /* max BDs per tx packet including next pages */
621 #define MAX_DESC_PER_TX_PKT (MAX_BDS_PER_TX_PKT + \
622 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))
623
624 /* The RX BD ring is special, each bd is 8 bytes but the last one is 16 */
625 #define NUM_RX_RINGS 8
626 #define RX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
627 #define NEXT_PAGE_RX_DESC_CNT 2
628 #define MAX_RX_DESC_CNT (RX_DESC_CNT - NEXT_PAGE_RX_DESC_CNT)
629 #define RX_DESC_MASK (RX_DESC_CNT - 1)
630 #define NUM_RX_BD (RX_DESC_CNT * NUM_RX_RINGS)
631 #define MAX_RX_BD (NUM_RX_BD - 1)
632 #define MAX_RX_AVAIL (MAX_RX_DESC_CNT * NUM_RX_RINGS - 2)
633
634 /* dropless fc calculations for BDs
635 *
636 * Number of BDs should as number of buffers in BRB:
637 * Low threshold takes into account NEXT_PAGE_RX_DESC_CNT
638 * "next" elements on each page
639 */
640 #define NUM_BD_REQ BRB_SIZE(bp)
641 #define NUM_BD_PG_REQ ((NUM_BD_REQ + MAX_RX_DESC_CNT - 1) / \
642 MAX_RX_DESC_CNT)
643 #define BD_TH_LO(bp) (NUM_BD_REQ + \
644 NUM_BD_PG_REQ * NEXT_PAGE_RX_DESC_CNT + \
645 FW_DROP_LEVEL(bp))
646 #define BD_TH_HI(bp) (BD_TH_LO(bp) + DROPLESS_FC_HEADROOM)
647
648 #define MIN_RX_AVAIL ((bp)->dropless_fc ? BD_TH_HI(bp) + 128 : 128)
649
650 #define MIN_RX_SIZE_TPA_HW (CHIP_IS_E1(bp) ? \
651 ETH_MIN_RX_CQES_WITH_TPA_E1 : \
652 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
653 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
654 #define MIN_RX_SIZE_TPA (max_t(u32, MIN_RX_SIZE_TPA_HW, MIN_RX_AVAIL))
655 #define MIN_RX_SIZE_NONTPA (max_t(u32, MIN_RX_SIZE_NONTPA_HW,\
656 MIN_RX_AVAIL))
657
658 #define NEXT_RX_IDX(x) ((((x) & RX_DESC_MASK) == \
659 (MAX_RX_DESC_CNT - 1)) ? \
660 (x) + 1 + NEXT_PAGE_RX_DESC_CNT : \
661 (x) + 1)
662 #define RX_BD(x) ((x) & MAX_RX_BD)
663
664 /*
665 * As long as CQE is X times bigger than BD entry we have to allocate X times
666 * more pages for CQ ring in order to keep it balanced with BD ring
667 */
668 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / sizeof(struct eth_rx_bd))
669 #define NUM_RCQ_RINGS (NUM_RX_RINGS * CQE_BD_REL)
670 #define RCQ_DESC_CNT (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
671 #define NEXT_PAGE_RCQ_DESC_CNT 1
672 #define MAX_RCQ_DESC_CNT (RCQ_DESC_CNT - NEXT_PAGE_RCQ_DESC_CNT)
673 #define NUM_RCQ_BD (RCQ_DESC_CNT * NUM_RCQ_RINGS)
674 #define MAX_RCQ_BD (NUM_RCQ_BD - 1)
675 #define MAX_RCQ_AVAIL (MAX_RCQ_DESC_CNT * NUM_RCQ_RINGS - 2)
676 #define NEXT_RCQ_IDX(x) ((((x) & MAX_RCQ_DESC_CNT) == \
677 (MAX_RCQ_DESC_CNT - 1)) ? \
678 (x) + 1 + NEXT_PAGE_RCQ_DESC_CNT : \
679 (x) + 1)
680 #define RCQ_BD(x) ((x) & MAX_RCQ_BD)
681
682 /* dropless fc calculations for RCQs
683 *
684 * Number of RCQs should be as number of buffers in BRB:
685 * Low threshold takes into account NEXT_PAGE_RCQ_DESC_CNT
686 * "next" elements on each page
687 */
688 #define NUM_RCQ_REQ BRB_SIZE(bp)
689 #define NUM_RCQ_PG_REQ ((NUM_BD_REQ + MAX_RCQ_DESC_CNT - 1) / \
690 MAX_RCQ_DESC_CNT)
691 #define RCQ_TH_LO(bp) (NUM_RCQ_REQ + \
692 NUM_RCQ_PG_REQ * NEXT_PAGE_RCQ_DESC_CNT + \
693 FW_DROP_LEVEL(bp))
694 #define RCQ_TH_HI(bp) (RCQ_TH_LO(bp) + DROPLESS_FC_HEADROOM)
695
696
697 /* This is needed for determining of last_max */
698 #define SUB_S16(a, b) (s16)((s16)(a) - (s16)(b))
699 #define SUB_S32(a, b) (s32)((s32)(a) - (s32)(b))
700
701
702 #define BNX2X_SWCID_SHIFT 17
703 #define BNX2X_SWCID_MASK ((0x1 << BNX2X_SWCID_SHIFT) - 1)
704
705 /* used on a CID received from the HW */
706 #define SW_CID(x) (le32_to_cpu(x) & BNX2X_SWCID_MASK)
707 #define CQE_CMD(x) (le32_to_cpu(x) >> \
708 COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
709
710 #define BD_UNMAP_ADDR(bd) HILO_U64(le32_to_cpu((bd)->addr_hi), \
711 le32_to_cpu((bd)->addr_lo))
712 #define BD_UNMAP_LEN(bd) (le16_to_cpu((bd)->nbytes))
713
714 #define BNX2X_DB_MIN_SHIFT 3 /* 8 bytes */
715 #define BNX2X_DB_SHIFT 7 /* 128 bytes*/
716 #if (BNX2X_DB_SHIFT < BNX2X_DB_MIN_SHIFT)
717 #error "Min DB doorbell stride is 8"
718 #endif
719 #define DPM_TRIGER_TYPE 0x40
720 #define DOORBELL(bp, cid, val) \
721 do { \
722 writel((u32)(val), bp->doorbells + (bp->db_size * (cid)) + \
723 DPM_TRIGER_TYPE); \
724 } while (0)
725
726
727 /* TX CSUM helpers */
728 #define SKB_CS_OFF(skb) (offsetof(struct tcphdr, check) - \
729 skb->csum_offset)
730 #define SKB_CS(skb) (*(u16 *)(skb_transport_header(skb) + \
731 skb->csum_offset))
732
733 #define pbd_tcp_flags(tcp_hdr) (ntohl(tcp_flag_word(tcp_hdr))>>16 & 0xff)
734
735 #define XMIT_PLAIN 0
736 #define XMIT_CSUM_V4 (1 << 0)
737 #define XMIT_CSUM_V6 (1 << 1)
738 #define XMIT_CSUM_TCP (1 << 2)
739 #define XMIT_GSO_V4 (1 << 3)
740 #define XMIT_GSO_V6 (1 << 4)
741 #define XMIT_CSUM_ENC_V4 (1 << 5)
742 #define XMIT_CSUM_ENC_V6 (1 << 6)
743 #define XMIT_GSO_ENC_V4 (1 << 7)
744 #define XMIT_GSO_ENC_V6 (1 << 8)
745
746 #define XMIT_CSUM_ENC (XMIT_CSUM_ENC_V4 | XMIT_CSUM_ENC_V6)
747 #define XMIT_GSO_ENC (XMIT_GSO_ENC_V4 | XMIT_GSO_ENC_V6)
748
749 #define XMIT_CSUM (XMIT_CSUM_V4 | XMIT_CSUM_V6 | XMIT_CSUM_ENC)
750 #define XMIT_GSO (XMIT_GSO_V4 | XMIT_GSO_V6 | XMIT_GSO_ENC)
751
752 /* stuff added to make the code fit 80Col */
753 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
754 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
755 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
756 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
757 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
758
759 #define ETH_RX_ERROR_FALGS ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG
760
761 #define BNX2X_PRS_FLAG_OVERETH_IPV4(flags) \
762 (((le16_to_cpu(flags) & \
763 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) >> \
764 PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT) \
765 == PRS_FLAG_OVERETH_IPV4)
766 #define BNX2X_RX_SUM_FIX(cqe) \
767 BNX2X_PRS_FLAG_OVERETH_IPV4(cqe->fast_path_cqe.pars_flags.flags)
768
769
770 #define FP_USB_FUNC_OFF \
771 offsetof(struct cstorm_status_block_u, func)
772 #define FP_CSB_FUNC_OFF \
773 offsetof(struct cstorm_status_block_c, func)
774
775 #define HC_INDEX_ETH_RX_CQ_CONS 1
776
777 #define HC_INDEX_OOO_TX_CQ_CONS 4
778
779 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
780
781 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
782
783 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
784
785 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
786
787 #define BNX2X_RX_SB_INDEX \
788 (&fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS])
789
790 #define BNX2X_TX_SB_INDEX_BASE BNX2X_TX_SB_INDEX_COS0
791
792 #define BNX2X_TX_SB_INDEX_COS0 \
793 (&fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0])
794
795 /* end of fast path */
796
797 /* common */
798
799 struct bnx2x_common {
800
801 u32 chip_id;
802 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
803 #define CHIP_ID(bp) (bp->common.chip_id & 0xfffffff0)
804
805 #define CHIP_NUM(bp) (bp->common.chip_id >> 16)
806 #define CHIP_NUM_57710 0x164e
807 #define CHIP_NUM_57711 0x164f
808 #define CHIP_NUM_57711E 0x1650
809 #define CHIP_NUM_57712 0x1662
810 #define CHIP_NUM_57712_MF 0x1663
811 #define CHIP_NUM_57712_VF 0x166f
812 #define CHIP_NUM_57713 0x1651
813 #define CHIP_NUM_57713E 0x1652
814 #define CHIP_NUM_57800 0x168a
815 #define CHIP_NUM_57800_MF 0x16a5
816 #define CHIP_NUM_57800_VF 0x16a9
817 #define CHIP_NUM_57810 0x168e
818 #define CHIP_NUM_57810_MF 0x16ae
819 #define CHIP_NUM_57810_VF 0x16af
820 #define CHIP_NUM_57811 0x163d
821 #define CHIP_NUM_57811_MF 0x163e
822 #define CHIP_NUM_57811_VF 0x163f
823 #define CHIP_NUM_57840_OBSOLETE 0x168d
824 #define CHIP_NUM_57840_MF_OBSOLETE 0x16ab
825 #define CHIP_NUM_57840_4_10 0x16a1
826 #define CHIP_NUM_57840_2_20 0x16a2
827 #define CHIP_NUM_57840_MF 0x16a4
828 #define CHIP_NUM_57840_VF 0x16ad
829 #define CHIP_IS_E1(bp) (CHIP_NUM(bp) == CHIP_NUM_57710)
830 #define CHIP_IS_57711(bp) (CHIP_NUM(bp) == CHIP_NUM_57711)
831 #define CHIP_IS_57711E(bp) (CHIP_NUM(bp) == CHIP_NUM_57711E)
832 #define CHIP_IS_57712(bp) (CHIP_NUM(bp) == CHIP_NUM_57712)
833 #define CHIP_IS_57712_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_VF)
834 #define CHIP_IS_57712_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57712_MF)
835 #define CHIP_IS_57800(bp) (CHIP_NUM(bp) == CHIP_NUM_57800)
836 #define CHIP_IS_57800_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_MF)
837 #define CHIP_IS_57800_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57800_VF)
838 #define CHIP_IS_57810(bp) (CHIP_NUM(bp) == CHIP_NUM_57810)
839 #define CHIP_IS_57810_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_MF)
840 #define CHIP_IS_57810_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57810_VF)
841 #define CHIP_IS_57811(bp) (CHIP_NUM(bp) == CHIP_NUM_57811)
842 #define CHIP_IS_57811_MF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_MF)
843 #define CHIP_IS_57811_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57811_VF)
844 #define CHIP_IS_57840(bp) \
845 ((CHIP_NUM(bp) == CHIP_NUM_57840_4_10) || \
846 (CHIP_NUM(bp) == CHIP_NUM_57840_2_20) || \
847 (CHIP_NUM(bp) == CHIP_NUM_57840_OBSOLETE))
848 #define CHIP_IS_57840_MF(bp) ((CHIP_NUM(bp) == CHIP_NUM_57840_MF) || \
849 (CHIP_NUM(bp) == CHIP_NUM_57840_MF_OBSOLETE))
850 #define CHIP_IS_57840_VF(bp) (CHIP_NUM(bp) == CHIP_NUM_57840_VF)
851 #define CHIP_IS_E1H(bp) (CHIP_IS_57711(bp) || \
852 CHIP_IS_57711E(bp))
853 #define CHIP_IS_57811xx(bp) (CHIP_IS_57811(bp) || \
854 CHIP_IS_57811_MF(bp) || \
855 CHIP_IS_57811_VF(bp))
856 #define CHIP_IS_E2(bp) (CHIP_IS_57712(bp) || \
857 CHIP_IS_57712_MF(bp) || \
858 CHIP_IS_57712_VF(bp))
859 #define CHIP_IS_E3(bp) (CHIP_IS_57800(bp) || \
860 CHIP_IS_57800_MF(bp) || \
861 CHIP_IS_57800_VF(bp) || \
862 CHIP_IS_57810(bp) || \
863 CHIP_IS_57810_MF(bp) || \
864 CHIP_IS_57810_VF(bp) || \
865 CHIP_IS_57811xx(bp) || \
866 CHIP_IS_57840(bp) || \
867 CHIP_IS_57840_MF(bp) || \
868 CHIP_IS_57840_VF(bp))
869 #define CHIP_IS_E1x(bp) (CHIP_IS_E1((bp)) || CHIP_IS_E1H((bp)))
870 #define USES_WARPCORE(bp) (CHIP_IS_E3(bp))
871 #define IS_E1H_OFFSET (!CHIP_IS_E1(bp))
872
873 #define CHIP_REV_SHIFT 12
874 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
875 #define CHIP_REV_VAL(bp) (bp->common.chip_id & CHIP_REV_MASK)
876 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
877 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
878 /* assume maximum 5 revisions */
879 #define CHIP_REV_IS_SLOW(bp) (CHIP_REV_VAL(bp) > 0x00005000)
880 /* Emul versions are A=>0xe, B=>0xc, C=>0xa, D=>8, E=>6 */
881 #define CHIP_REV_IS_EMUL(bp) ((CHIP_REV_IS_SLOW(bp)) && \
882 !(CHIP_REV_VAL(bp) & 0x00001000))
883 /* FPGA versions are A=>0xf, B=>0xd, C=>0xb, D=>9, E=>7 */
884 #define CHIP_REV_IS_FPGA(bp) ((CHIP_REV_IS_SLOW(bp)) && \
885 (CHIP_REV_VAL(bp) & 0x00001000))
886
887 #define CHIP_TIME(bp) ((CHIP_REV_IS_EMUL(bp)) ? 2000 : \
888 ((CHIP_REV_IS_FPGA(bp)) ? 200 : 1))
889
890 #define CHIP_METAL(bp) (bp->common.chip_id & 0x00000ff0)
891 #define CHIP_BOND_ID(bp) (bp->common.chip_id & 0x0000000f)
892 #define CHIP_REV_SIM(bp) (((CHIP_REV_MASK - CHIP_REV_VAL(bp)) >>\
893 (CHIP_REV_SHIFT + 1)) \
894 << CHIP_REV_SHIFT)
895 #define CHIP_REV(bp) (CHIP_REV_IS_SLOW(bp) ? \
896 CHIP_REV_SIM(bp) :\
897 CHIP_REV_VAL(bp))
898 #define CHIP_IS_E3B0(bp) (CHIP_IS_E3(bp) && \
899 (CHIP_REV(bp) == CHIP_REV_Bx))
900 #define CHIP_IS_E3A0(bp) (CHIP_IS_E3(bp) && \
901 (CHIP_REV(bp) == CHIP_REV_Ax))
902 /* This define is used in two main places:
903 * 1. In the early stages of nic_load, to know if to configrue Parser / Searcher
904 * to nic-only mode or to offload mode. Offload mode is configured if either the
905 * chip is E1x (where MIC_MODE register is not applicable), or if cnic already
906 * registered for this port (which means that the user wants storage services).
907 * 2. During cnic-related load, to know if offload mode is already configured in
908 * the HW or needs to be configrued.
909 * Since the transition from nic-mode to offload-mode in HW causes traffic
910 * coruption, nic-mode is configured only in ports on which storage services
911 * where never requested.
912 */
913 #define CONFIGURE_NIC_MODE(bp) (!CHIP_IS_E1x(bp) && !CNIC_ENABLED(bp))
914
915 int flash_size;
916 #define BNX2X_NVRAM_1MB_SIZE 0x20000 /* 1M bit in bytes */
917 #define BNX2X_NVRAM_TIMEOUT_COUNT 30000
918 #define BNX2X_NVRAM_PAGE_SIZE 256
919
920 u32 shmem_base;
921 u32 shmem2_base;
922 u32 mf_cfg_base;
923 u32 mf2_cfg_base;
924
925 u32 hw_config;
926
927 u32 bc_ver;
928
929 u8 int_block;
930 #define INT_BLOCK_HC 0
931 #define INT_BLOCK_IGU 1
932 #define INT_BLOCK_MODE_NORMAL 0
933 #define INT_BLOCK_MODE_BW_COMP 2
934 #define CHIP_INT_MODE_IS_NBC(bp) \
935 (!CHIP_IS_E1x(bp) && \
936 !((bp)->common.int_block & INT_BLOCK_MODE_BW_COMP))
937 #define CHIP_INT_MODE_IS_BC(bp) (!CHIP_INT_MODE_IS_NBC(bp))
938
939 u8 chip_port_mode;
940 #define CHIP_4_PORT_MODE 0x0
941 #define CHIP_2_PORT_MODE 0x1
942 #define CHIP_PORT_MODE_NONE 0x2
943 #define CHIP_MODE(bp) (bp->common.chip_port_mode)
944 #define CHIP_MODE_IS_4_PORT(bp) (CHIP_MODE(bp) == CHIP_4_PORT_MODE)
945
946 u32 boot_mode;
947 };
948
949 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
950 #define BNX2X_IGU_STAS_MSG_VF_CNT 64
951 #define BNX2X_IGU_STAS_MSG_PF_CNT 4
952
953 #define MAX_IGU_ATTN_ACK_TO 100
954 /* end of common */
955
956 /* port */
957
958 struct bnx2x_port {
959 u32 pmf;
960
961 u32 link_config[LINK_CONFIG_SIZE];
962
963 u32 supported[LINK_CONFIG_SIZE];
964 /* link settings - missing defines */
965 #define SUPPORTED_2500baseX_Full (1 << 15)
966
967 u32 advertising[LINK_CONFIG_SIZE];
968 /* link settings - missing defines */
969 #define ADVERTISED_2500baseX_Full (1 << 15)
970
971 u32 phy_addr;
972
973 /* used to synchronize phy accesses */
974 struct mutex phy_mutex;
975
976 u32 port_stx;
977
978 struct nig_stats old_nig_stats;
979 };
980
981 /* end of port */
982
983 #define STATS_OFFSET32(stat_name) \
984 (offsetof(struct bnx2x_eth_stats, stat_name) / 4)
985
986 /* slow path */
987
988 /* slow path work-queue */
989 extern struct workqueue_struct *bnx2x_wq;
990
991 #define BNX2X_MAX_NUM_OF_VFS 64
992 #define BNX2X_VF_CID_WND 0
993 #define BNX2X_CIDS_PER_VF (1 << BNX2X_VF_CID_WND)
994 #define BNX2X_CLIENTS_PER_VF 1
995 #define BNX2X_FIRST_VF_CID 256
996 #define BNX2X_VF_CIDS (BNX2X_MAX_NUM_OF_VFS * BNX2X_CIDS_PER_VF)
997 #define BNX2X_VF_ID_INVALID 0xFF
998
999 /*
1000 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
1001 * control by the number of fast-path status blocks supported by the
1002 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
1003 * status block represents an independent interrupts context that can
1004 * serve a regular L2 networking queue. However special L2 queues such
1005 * as the FCoE queue do not require a FP-SB and other components like
1006 * the CNIC may consume FP-SB reducing the number of possible L2 queues
1007 *
1008 * If the maximum number of FP-SB available is X then:
1009 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
1010 * regular L2 queues is Y=X-1
1011 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
1012 * c. If the FCoE L2 queue is supported the actual number of L2 queues
1013 * is Y+1
1014 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
1015 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
1016 * FP interrupt context for the CNIC).
1017 * e. The number of HW context (CID count) is always X or X+1 if FCoE
1018 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
1019 */
1020
1021 /* fast-path interrupt contexts E1x */
1022 #define FP_SB_MAX_E1x 16
1023 /* fast-path interrupt contexts E2 */
1024 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
1025
1026 union cdu_context {
1027 struct eth_context eth;
1028 char pad[1024];
1029 };
1030
1031 /* CDU host DB constants */
1032 #define CDU_ILT_PAGE_SZ_HW 2
1033 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
1034 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
1035
1036 #define CNIC_ISCSI_CID_MAX 256
1037 #define CNIC_FCOE_CID_MAX 2048
1038 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
1039 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
1040
1041 #define QM_ILT_PAGE_SZ_HW 0
1042 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
1043 #define QM_CID_ROUND 1024
1044
1045 /* TM (timers) host DB constants */
1046 #define TM_ILT_PAGE_SZ_HW 0
1047 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
1048 /* #define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
1049 #define TM_CONN_NUM 1024
1050 #define TM_ILT_SZ (8 * TM_CONN_NUM)
1051 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
1052
1053 /* SRC (Searcher) host DB constants */
1054 #define SRC_ILT_PAGE_SZ_HW 0
1055 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
1056 #define SRC_HASH_BITS 10
1057 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
1058 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
1059 #define SRC_T2_SZ SRC_ILT_SZ
1060 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
1061
1062 #define MAX_DMAE_C 8
1063
1064 /* DMA memory not used in fastpath */
1065 struct bnx2x_slowpath {
1066 union {
1067 struct mac_configuration_cmd e1x;
1068 struct eth_classify_rules_ramrod_data e2;
1069 } mac_rdata;
1070
1071
1072 union {
1073 struct tstorm_eth_mac_filter_config e1x;
1074 struct eth_filter_rules_ramrod_data e2;
1075 } rx_mode_rdata;
1076
1077 union {
1078 struct mac_configuration_cmd e1;
1079 struct eth_multicast_rules_ramrod_data e2;
1080 } mcast_rdata;
1081
1082 struct eth_rss_update_ramrod_data rss_rdata;
1083
1084 /* Queue State related ramrods are always sent under rtnl_lock */
1085 union {
1086 struct client_init_ramrod_data init_data;
1087 struct client_update_ramrod_data update_data;
1088 } q_rdata;
1089
1090 union {
1091 struct function_start_data func_start;
1092 /* pfc configuration for DCBX ramrod */
1093 struct flow_control_configuration pfc_config;
1094 } func_rdata;
1095
1096 /* afex ramrod can not be a part of func_rdata union because these
1097 * events might arrive in parallel to other events from func_rdata.
1098 * Therefore, if they would have been defined in the same union,
1099 * data can get corrupted.
1100 */
1101 struct afex_vif_list_ramrod_data func_afex_rdata;
1102
1103 /* used by dmae command executer */
1104 struct dmae_command dmae[MAX_DMAE_C];
1105
1106 u32 stats_comp;
1107 union mac_stats mac_stats;
1108 struct nig_stats nig_stats;
1109 struct host_port_stats port_stats;
1110 struct host_func_stats func_stats;
1111
1112 u32 wb_comp;
1113 u32 wb_data[4];
1114
1115 union drv_info_to_mcp drv_info_to_mcp;
1116 };
1117
1118 #define bnx2x_sp(bp, var) (&bp->slowpath->var)
1119 #define bnx2x_sp_mapping(bp, var) \
1120 (bp->slowpath_mapping + offsetof(struct bnx2x_slowpath, var))
1121
1122
1123 /* attn group wiring */
1124 #define MAX_DYNAMIC_ATTN_GRPS 8
1125
1126 struct attn_route {
1127 u32 sig[5];
1128 };
1129
1130 struct iro {
1131 u32 base;
1132 u16 m1;
1133 u16 m2;
1134 u16 m3;
1135 u16 size;
1136 };
1137
1138 struct hw_context {
1139 union cdu_context *vcxt;
1140 dma_addr_t cxt_mapping;
1141 size_t size;
1142 };
1143
1144 /* forward */
1145 struct bnx2x_ilt;
1146
1147 struct bnx2x_vfdb;
1148
1149 enum bnx2x_recovery_state {
1150 BNX2X_RECOVERY_DONE,
1151 BNX2X_RECOVERY_INIT,
1152 BNX2X_RECOVERY_WAIT,
1153 BNX2X_RECOVERY_FAILED,
1154 BNX2X_RECOVERY_NIC_LOADING
1155 };
1156
1157 /*
1158 * Event queue (EQ or event ring) MC hsi
1159 * NUM_EQ_PAGES and EQ_DESC_CNT_PAGE must be power of 2
1160 */
1161 #define NUM_EQ_PAGES 1
1162 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1163 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1164 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1165 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1166 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1167
1168 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1169 #define NEXT_EQ_IDX(x) ((((x) & EQ_DESC_MAX_PAGE) == \
1170 (EQ_DESC_MAX_PAGE - 1)) ? (x) + 2 : (x) + 1)
1171
1172 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1173 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1174
1175 #define BNX2X_EQ_INDEX \
1176 (&bp->def_status_blk->sp_sb.\
1177 index_values[HC_SP_INDEX_EQ_CONS])
1178
1179 /* This is a data that will be used to create a link report message.
1180 * We will keep the data used for the last link report in order
1181 * to prevent reporting the same link parameters twice.
1182 */
1183 struct bnx2x_link_report_data {
1184 u16 line_speed; /* Effective line speed */
1185 unsigned long link_report_flags;/* BNX2X_LINK_REPORT_XXX flags */
1186 };
1187
1188 enum {
1189 BNX2X_LINK_REPORT_FD, /* Full DUPLEX */
1190 BNX2X_LINK_REPORT_LINK_DOWN,
1191 BNX2X_LINK_REPORT_RX_FC_ON,
1192 BNX2X_LINK_REPORT_TX_FC_ON,
1193 };
1194
1195 enum {
1196 BNX2X_PORT_QUERY_IDX,
1197 BNX2X_PF_QUERY_IDX,
1198 BNX2X_FCOE_QUERY_IDX,
1199 BNX2X_FIRST_QUEUE_QUERY_IDX,
1200 };
1201
1202 struct bnx2x_fw_stats_req {
1203 struct stats_query_header hdr;
1204 struct stats_query_entry query[FP_SB_MAX_E1x+
1205 BNX2X_FIRST_QUEUE_QUERY_IDX];
1206 };
1207
1208 struct bnx2x_fw_stats_data {
1209 struct stats_counter storm_counters;
1210 struct per_port_stats port;
1211 struct per_pf_stats pf;
1212 struct fcoe_statistics_params fcoe;
1213 struct per_queue_stats queue_stats[1];
1214 };
1215
1216 /* Public slow path states */
1217 enum {
1218 BNX2X_SP_RTNL_SETUP_TC,
1219 BNX2X_SP_RTNL_TX_TIMEOUT,
1220 BNX2X_SP_RTNL_FAN_FAILURE,
1221 BNX2X_SP_RTNL_AFEX_F_UPDATE,
1222 BNX2X_SP_RTNL_ENABLE_SRIOV,
1223 BNX2X_SP_RTNL_VFPF_MCAST,
1224 BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
1225 BNX2X_SP_RTNL_HYPERVISOR_VLAN,
1226 };
1227
1228
1229 struct bnx2x_prev_path_list {
1230 struct list_head list;
1231 u8 bus;
1232 u8 slot;
1233 u8 path;
1234 u8 aer;
1235 u8 undi;
1236 };
1237
1238 struct bnx2x_sp_objs {
1239 /* MACs object */
1240 struct bnx2x_vlan_mac_obj mac_obj;
1241
1242 /* Queue State object */
1243 struct bnx2x_queue_sp_obj q_obj;
1244 };
1245
1246 struct bnx2x_fp_stats {
1247 struct tstorm_per_queue_stats old_tclient;
1248 struct ustorm_per_queue_stats old_uclient;
1249 struct xstorm_per_queue_stats old_xclient;
1250 struct bnx2x_eth_q_stats eth_q_stats;
1251 struct bnx2x_eth_q_stats_old eth_q_stats_old;
1252 };
1253
1254 struct bnx2x {
1255 /* Fields used in the tx and intr/napi performance paths
1256 * are grouped together in the beginning of the structure
1257 */
1258 struct bnx2x_fastpath *fp;
1259 struct bnx2x_sp_objs *sp_objs;
1260 struct bnx2x_fp_stats *fp_stats;
1261 struct bnx2x_fp_txdata *bnx2x_txq;
1262 void __iomem *regview;
1263 void __iomem *doorbells;
1264 u16 db_size;
1265
1266 u8 pf_num; /* absolute PF number */
1267 u8 pfid; /* per-path PF number */
1268 int base_fw_ndsb; /**/
1269 #define BP_PATH(bp) (CHIP_IS_E1x(bp) ? 0 : (bp->pf_num & 1))
1270 #define BP_PORT(bp) (bp->pfid & 1)
1271 #define BP_FUNC(bp) (bp->pfid)
1272 #define BP_ABS_FUNC(bp) (bp->pf_num)
1273 #define BP_VN(bp) ((bp)->pfid >> 1)
1274 #define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1275 #define BP_L_ID(bp) (BP_VN(bp) << 2)
1276 #define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1277 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1278 #define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1279
1280 #ifdef CONFIG_BNX2X_SRIOV
1281 /* protects vf2pf mailbox from simultaneous access */
1282 struct mutex vf2pf_mutex;
1283 /* vf pf channel mailbox contains request and response buffers */
1284 struct bnx2x_vf_mbx_msg *vf2pf_mbox;
1285 dma_addr_t vf2pf_mbox_mapping;
1286
1287 /* we set aside a copy of the acquire response */
1288 struct pfvf_acquire_resp_tlv acquire_resp;
1289
1290 /* bulletin board for messages from pf to vf */
1291 union pf_vf_bulletin *pf2vf_bulletin;
1292 dma_addr_t pf2vf_bulletin_mapping;
1293
1294 struct pf_vf_bulletin_content old_bulletin;
1295
1296 u16 requested_nr_virtfn;
1297 #endif /* CONFIG_BNX2X_SRIOV */
1298
1299 struct net_device *dev;
1300 struct pci_dev *pdev;
1301
1302 const struct iro *iro_arr;
1303 #define IRO (bp->iro_arr)
1304
1305 enum bnx2x_recovery_state recovery_state;
1306 int is_leader;
1307 struct msix_entry *msix_table;
1308
1309 int tx_ring_size;
1310
1311 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
1312 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
1313 #define ETH_MIN_PACKET_SIZE 60
1314 #define ETH_MAX_PACKET_SIZE 1500
1315 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
1316 /* TCP with Timestamp Option (32) + IPv6 (40) */
1317 #define ETH_MAX_TPA_HEADER_SIZE 72
1318
1319 /* Max supported alignment is 256 (8 shift) */
1320 #define BNX2X_RX_ALIGN_SHIFT min(8, L1_CACHE_SHIFT)
1321
1322 /* FW uses 2 Cache lines Alignment for start packet and size
1323 *
1324 * We assume skb_build() uses sizeof(struct skb_shared_info) bytes
1325 * at the end of skb->data, to avoid wasting a full cache line.
1326 * This reduces memory use (skb->truesize).
1327 */
1328 #define BNX2X_FW_RX_ALIGN_START (1UL << BNX2X_RX_ALIGN_SHIFT)
1329
1330 #define BNX2X_FW_RX_ALIGN_END \
1331 max_t(u64, 1UL << BNX2X_RX_ALIGN_SHIFT, \
1332 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
1333
1334 #define BNX2X_PXP_DRAM_ALIGN (BNX2X_RX_ALIGN_SHIFT - 5)
1335
1336 struct host_sp_status_block *def_status_blk;
1337 #define DEF_SB_IGU_ID 16
1338 #define DEF_SB_ID HC_SP_SB_ID
1339 __le16 def_idx;
1340 __le16 def_att_idx;
1341 u32 attn_state;
1342 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1343
1344 /* slow path ring */
1345 struct eth_spe *spq;
1346 dma_addr_t spq_mapping;
1347 u16 spq_prod_idx;
1348 struct eth_spe *spq_prod_bd;
1349 struct eth_spe *spq_last_bd;
1350 __le16 *dsb_sp_prod;
1351 atomic_t cq_spq_left; /* ETH_XXX ramrods credit */
1352 /* used to synchronize spq accesses */
1353 spinlock_t spq_lock;
1354
1355 /* event queue */
1356 union event_ring_elem *eq_ring;
1357 dma_addr_t eq_mapping;
1358 u16 eq_prod;
1359 u16 eq_cons;
1360 __le16 *eq_cons_sb;
1361 atomic_t eq_spq_left; /* COMMON_XXX ramrods credit */
1362
1363 /* Counter for marking that there is a STAT_QUERY ramrod pending */
1364 u16 stats_pending;
1365 /* Counter for completed statistics ramrods */
1366 u16 stats_comp;
1367
1368 /* End of fields used in the performance code paths */
1369
1370 int panic;
1371 int msg_enable;
1372
1373 u32 flags;
1374 #define PCIX_FLAG (1 << 0)
1375 #define PCI_32BIT_FLAG (1 << 1)
1376 #define ONE_PORT_FLAG (1 << 2)
1377 #define NO_WOL_FLAG (1 << 3)
1378 #define USING_DAC_FLAG (1 << 4)
1379 #define USING_MSIX_FLAG (1 << 5)
1380 #define USING_MSI_FLAG (1 << 6)
1381 #define DISABLE_MSI_FLAG (1 << 7)
1382 #define TPA_ENABLE_FLAG (1 << 8)
1383 #define NO_MCP_FLAG (1 << 9)
1384 #define GRO_ENABLE_FLAG (1 << 10)
1385 #define MF_FUNC_DIS (1 << 11)
1386 #define OWN_CNIC_IRQ (1 << 12)
1387 #define NO_ISCSI_OOO_FLAG (1 << 13)
1388 #define NO_ISCSI_FLAG (1 << 14)
1389 #define NO_FCOE_FLAG (1 << 15)
1390 #define BC_SUPPORTS_PFC_STATS (1 << 17)
1391 #define BC_SUPPORTS_FCOE_FEATURES (1 << 19)
1392 #define USING_SINGLE_MSIX_FLAG (1 << 20)
1393 #define BC_SUPPORTS_DCBX_MSG_NON_PMF (1 << 21)
1394 #define IS_VF_FLAG (1 << 22)
1395
1396 #define BP_NOMCP(bp) ((bp)->flags & NO_MCP_FLAG)
1397
1398 #ifdef CONFIG_BNX2X_SRIOV
1399 #define IS_VF(bp) ((bp)->flags & IS_VF_FLAG)
1400 #define IS_PF(bp) (!((bp)->flags & IS_VF_FLAG))
1401 #else
1402 #define IS_VF(bp) false
1403 #define IS_PF(bp) true
1404 #endif
1405
1406 #define NO_ISCSI(bp) ((bp)->flags & NO_ISCSI_FLAG)
1407 #define NO_ISCSI_OOO(bp) ((bp)->flags & NO_ISCSI_OOO_FLAG)
1408 #define NO_FCOE(bp) ((bp)->flags & NO_FCOE_FLAG)
1409
1410 u8 cnic_support;
1411 bool cnic_enabled;
1412 bool cnic_loaded;
1413 struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
1414
1415 /* Flag that indicates that we can start looking for FCoE L2 queue
1416 * completions in the default status block.
1417 */
1418 bool fcoe_init;
1419
1420 int pm_cap;
1421 int mrrs;
1422
1423 struct delayed_work sp_task;
1424 atomic_t interrupt_occurred;
1425 struct delayed_work sp_rtnl_task;
1426
1427 struct delayed_work period_task;
1428 struct timer_list timer;
1429 int current_interval;
1430
1431 u16 fw_seq;
1432 u16 fw_drv_pulse_wr_seq;
1433 u32 func_stx;
1434
1435 struct link_params link_params;
1436 struct link_vars link_vars;
1437 u32 link_cnt;
1438 struct bnx2x_link_report_data last_reported_link;
1439
1440 struct mdio_if_info mdio;
1441
1442 struct bnx2x_common common;
1443 struct bnx2x_port port;
1444
1445 struct cmng_init cmng;
1446
1447 u32 mf_config[E1HVN_MAX];
1448 u32 mf_ext_config;
1449 u32 path_has_ovlan; /* E3 */
1450 u16 mf_ov;
1451 u8 mf_mode;
1452 #define IS_MF(bp) (bp->mf_mode != 0)
1453 #define IS_MF_SI(bp) (bp->mf_mode == MULTI_FUNCTION_SI)
1454 #define IS_MF_SD(bp) (bp->mf_mode == MULTI_FUNCTION_SD)
1455 #define IS_MF_AFEX(bp) (bp->mf_mode == MULTI_FUNCTION_AFEX)
1456
1457 u8 wol;
1458
1459 int rx_ring_size;
1460
1461 u16 tx_quick_cons_trip_int;
1462 u16 tx_quick_cons_trip;
1463 u16 tx_ticks_int;
1464 u16 tx_ticks;
1465
1466 u16 rx_quick_cons_trip_int;
1467 u16 rx_quick_cons_trip;
1468 u16 rx_ticks_int;
1469 u16 rx_ticks;
1470 /* Maximal coalescing timeout in us */
1471 #define BNX2X_MAX_COALESCE_TOUT (0xf0*12)
1472
1473 u32 lin_cnt;
1474
1475 u16 state;
1476 #define BNX2X_STATE_CLOSED 0
1477 #define BNX2X_STATE_OPENING_WAIT4_LOAD 0x1000
1478 #define BNX2X_STATE_OPENING_WAIT4_PORT 0x2000
1479 #define BNX2X_STATE_OPEN 0x3000
1480 #define BNX2X_STATE_CLOSING_WAIT4_HALT 0x4000
1481 #define BNX2X_STATE_CLOSING_WAIT4_DELETE 0x5000
1482
1483 #define BNX2X_STATE_DIAG 0xe000
1484 #define BNX2X_STATE_ERROR 0xf000
1485
1486 #define BNX2X_MAX_PRIORITY 8
1487 #define BNX2X_MAX_ENTRIES_PER_PRI 16
1488 #define BNX2X_MAX_COS 3
1489 #define BNX2X_MAX_TX_COS 2
1490 int num_queues;
1491 uint num_ethernet_queues;
1492 uint num_cnic_queues;
1493 int num_napi_queues;
1494 int disable_tpa;
1495
1496 u32 rx_mode;
1497 #define BNX2X_RX_MODE_NONE 0
1498 #define BNX2X_RX_MODE_NORMAL 1
1499 #define BNX2X_RX_MODE_ALLMULTI 2
1500 #define BNX2X_RX_MODE_PROMISC 3
1501 #define BNX2X_MAX_MULTICAST 64
1502
1503 u8 igu_dsb_id;
1504 u8 igu_base_sb;
1505 u8 igu_sb_cnt;
1506 u8 min_msix_vec_cnt;
1507
1508 u32 igu_base_addr;
1509 dma_addr_t def_status_blk_mapping;
1510
1511 struct bnx2x_slowpath *slowpath;
1512 dma_addr_t slowpath_mapping;
1513
1514 /* Total number of FW statistics requests */
1515 u8 fw_stats_num;
1516
1517 /*
1518 * This is a memory buffer that will contain both statistics
1519 * ramrod request and data.
1520 */
1521 void *fw_stats;
1522 dma_addr_t fw_stats_mapping;
1523
1524 /*
1525 * FW statistics request shortcut (points at the
1526 * beginning of fw_stats buffer).
1527 */
1528 struct bnx2x_fw_stats_req *fw_stats_req;
1529 dma_addr_t fw_stats_req_mapping;
1530 int fw_stats_req_sz;
1531
1532 /*
1533 * FW statistics data shortcut (points at the beginning of
1534 * fw_stats buffer + fw_stats_req_sz).
1535 */
1536 struct bnx2x_fw_stats_data *fw_stats_data;
1537 dma_addr_t fw_stats_data_mapping;
1538 int fw_stats_data_sz;
1539
1540 /* For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1541 * context size we need 8 ILT entries.
1542 */
1543 #define ILT_MAX_L2_LINES 8
1544 struct hw_context context[ILT_MAX_L2_LINES];
1545
1546 struct bnx2x_ilt *ilt;
1547 #define BP_ILT(bp) ((bp)->ilt)
1548 #define ILT_MAX_LINES 256
1549 /*
1550 * Maximum supported number of RSS queues: number of IGU SBs minus one that goes
1551 * to CNIC.
1552 */
1553 #define BNX2X_MAX_RSS_COUNT(bp) ((bp)->igu_sb_cnt - CNIC_SUPPORT(bp))
1554
1555 /*
1556 * Maximum CID count that might be required by the bnx2x:
1557 * Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI
1558 */
1559 #define BNX2X_L2_CID_COUNT(bp) (BNX2X_NUM_ETH_QUEUES(bp) * BNX2X_MULTI_TX_COS \
1560 + 2 * CNIC_SUPPORT(bp))
1561 #define BNX2X_L2_MAX_CID(bp) (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS \
1562 + 2 * CNIC_SUPPORT(bp))
1563 #define L2_ILT_LINES(bp) (DIV_ROUND_UP(BNX2X_L2_CID_COUNT(bp),\
1564 ILT_PAGE_CIDS))
1565
1566 int qm_cid_count;
1567
1568 bool dropless_fc;
1569
1570 void *t2;
1571 dma_addr_t t2_mapping;
1572 struct cnic_ops __rcu *cnic_ops;
1573 void *cnic_data;
1574 u32 cnic_tag;
1575 struct cnic_eth_dev cnic_eth_dev;
1576 union host_hc_status_block cnic_sb;
1577 dma_addr_t cnic_sb_mapping;
1578 struct eth_spe *cnic_kwq;
1579 struct eth_spe *cnic_kwq_prod;
1580 struct eth_spe *cnic_kwq_cons;
1581 struct eth_spe *cnic_kwq_last;
1582 u16 cnic_kwq_pending;
1583 u16 cnic_spq_pending;
1584 u8 fip_mac[ETH_ALEN];
1585 struct mutex cnic_mutex;
1586 struct bnx2x_vlan_mac_obj iscsi_l2_mac_obj;
1587
1588 /* Start index of the "special" (CNIC related) L2 cleints */
1589 u8 cnic_base_cl_id;
1590
1591 int dmae_ready;
1592 /* used to synchronize dmae accesses */
1593 spinlock_t dmae_lock;
1594
1595 /* used to protect the FW mail box */
1596 struct mutex fw_mb_mutex;
1597
1598 /* used to synchronize stats collecting */
1599 int stats_state;
1600
1601 /* used for synchronization of concurrent threads statistics handling */
1602 spinlock_t stats_lock;
1603
1604 /* used by dmae command loader */
1605 struct dmae_command stats_dmae;
1606 int executer_idx;
1607
1608 u16 stats_counter;
1609 struct bnx2x_eth_stats eth_stats;
1610 struct host_func_stats func_stats;
1611 struct bnx2x_eth_stats_old eth_stats_old;
1612 struct bnx2x_net_stats_old net_stats_old;
1613 struct bnx2x_fw_port_stats_old fw_stats_old;
1614 bool stats_init;
1615
1616 struct z_stream_s *strm;
1617 void *gunzip_buf;
1618 dma_addr_t gunzip_mapping;
1619 int gunzip_outlen;
1620 #define FW_BUF_SIZE 0x8000
1621 #define GUNZIP_BUF(bp) (bp->gunzip_buf)
1622 #define GUNZIP_PHYS(bp) (bp->gunzip_mapping)
1623 #define GUNZIP_OUTLEN(bp) (bp->gunzip_outlen)
1624
1625 struct raw_op *init_ops;
1626 /* Init blocks offsets inside init_ops */
1627 u16 *init_ops_offsets;
1628 /* Data blob - has 32 bit granularity */
1629 u32 *init_data;
1630 u32 init_mode_flags;
1631 #define INIT_MODE_FLAGS(bp) (bp->init_mode_flags)
1632 /* Zipped PRAM blobs - raw data */
1633 const u8 *tsem_int_table_data;
1634 const u8 *tsem_pram_data;
1635 const u8 *usem_int_table_data;
1636 const u8 *usem_pram_data;
1637 const u8 *xsem_int_table_data;
1638 const u8 *xsem_pram_data;
1639 const u8 *csem_int_table_data;
1640 const u8 *csem_pram_data;
1641 #define INIT_OPS(bp) (bp->init_ops)
1642 #define INIT_OPS_OFFSETS(bp) (bp->init_ops_offsets)
1643 #define INIT_DATA(bp) (bp->init_data)
1644 #define INIT_TSEM_INT_TABLE_DATA(bp) (bp->tsem_int_table_data)
1645 #define INIT_TSEM_PRAM_DATA(bp) (bp->tsem_pram_data)
1646 #define INIT_USEM_INT_TABLE_DATA(bp) (bp->usem_int_table_data)
1647 #define INIT_USEM_PRAM_DATA(bp) (bp->usem_pram_data)
1648 #define INIT_XSEM_INT_TABLE_DATA(bp) (bp->xsem_int_table_data)
1649 #define INIT_XSEM_PRAM_DATA(bp) (bp->xsem_pram_data)
1650 #define INIT_CSEM_INT_TABLE_DATA(bp) (bp->csem_int_table_data)
1651 #define INIT_CSEM_PRAM_DATA(bp) (bp->csem_pram_data)
1652
1653 #define PHY_FW_VER_LEN 20
1654 char fw_ver[32];
1655 const struct firmware *firmware;
1656
1657 struct bnx2x_vfdb *vfdb;
1658 #define IS_SRIOV(bp) ((bp)->vfdb)
1659
1660 /* DCB support on/off */
1661 u16 dcb_state;
1662 #define BNX2X_DCB_STATE_OFF 0
1663 #define BNX2X_DCB_STATE_ON 1
1664
1665 /* DCBX engine mode */
1666 int dcbx_enabled;
1667 #define BNX2X_DCBX_ENABLED_OFF 0
1668 #define BNX2X_DCBX_ENABLED_ON_NEG_OFF 1
1669 #define BNX2X_DCBX_ENABLED_ON_NEG_ON 2
1670 #define BNX2X_DCBX_ENABLED_INVALID (-1)
1671
1672 bool dcbx_mode_uset;
1673
1674 struct bnx2x_config_dcbx_params dcbx_config_params;
1675 struct bnx2x_dcbx_port_params dcbx_port_params;
1676 int dcb_version;
1677
1678 /* CAM credit pools */
1679
1680 /* used only in sriov */
1681 struct bnx2x_credit_pool_obj vlans_pool;
1682
1683 struct bnx2x_credit_pool_obj macs_pool;
1684
1685 /* RX_MODE object */
1686 struct bnx2x_rx_mode_obj rx_mode_obj;
1687
1688 /* MCAST object */
1689 struct bnx2x_mcast_obj mcast_obj;
1690
1691 /* RSS configuration object */
1692 struct bnx2x_rss_config_obj rss_conf_obj;
1693
1694 /* Function State controlling object */
1695 struct bnx2x_func_sp_obj func_obj;
1696
1697 unsigned long sp_state;
1698
1699 /* operation indication for the sp_rtnl task */
1700 unsigned long sp_rtnl_state;
1701
1702 /* DCBX Negotation results */
1703 struct dcbx_features dcbx_local_feat;
1704 u32 dcbx_error;
1705
1706 #ifdef BCM_DCBNL
1707 struct dcbx_features dcbx_remote_feat;
1708 u32 dcbx_remote_flags;
1709 #endif
1710 /* AFEX: store default vlan used */
1711 int afex_def_vlan_tag;
1712 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1713 u32 pending_max;
1714
1715 /* multiple tx classes of service */
1716 u8 max_cos;
1717
1718 /* priority to cos mapping */
1719 u8 prio_to_cos[8];
1720
1721 int fp_array_size;
1722 u32 dump_preset_idx;
1723 };
1724
1725 /* Tx queues may be less or equal to Rx queues */
1726 extern int num_queues;
1727 #define BNX2X_NUM_QUEUES(bp) (bp->num_queues)
1728 #define BNX2X_NUM_ETH_QUEUES(bp) ((bp)->num_ethernet_queues)
1729 #define BNX2X_NUM_NON_CNIC_QUEUES(bp) (BNX2X_NUM_QUEUES(bp) - \
1730 (bp)->num_cnic_queues)
1731 #define BNX2X_NUM_RX_QUEUES(bp) BNX2X_NUM_QUEUES(bp)
1732
1733 #define is_multi(bp) (BNX2X_NUM_QUEUES(bp) > 1)
1734
1735 #define BNX2X_MAX_QUEUES(bp) BNX2X_MAX_RSS_COUNT(bp)
1736 /* #define is_eth_multi(bp) (BNX2X_NUM_ETH_QUEUES(bp) > 1) */
1737
1738 #define RSS_IPV4_CAP_MASK \
1739 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY
1740
1741 #define RSS_IPV4_TCP_CAP_MASK \
1742 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY
1743
1744 #define RSS_IPV6_CAP_MASK \
1745 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY
1746
1747 #define RSS_IPV6_TCP_CAP_MASK \
1748 TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY
1749
1750 /* func init flags */
1751 #define FUNC_FLG_RSS 0x0001
1752 #define FUNC_FLG_STATS 0x0002
1753 /* removed FUNC_FLG_UNMATCHED 0x0004 */
1754 #define FUNC_FLG_TPA 0x0008
1755 #define FUNC_FLG_SPQ 0x0010
1756 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1757
1758
1759 struct bnx2x_func_init_params {
1760 /* dma */
1761 dma_addr_t fw_stat_map; /* valid iff FUNC_FLG_STATS */
1762 dma_addr_t spq_map; /* valid iff FUNC_FLG_SPQ */
1763
1764 u16 func_flgs;
1765 u16 func_id; /* abs fid */
1766 u16 pf_id;
1767 u16 spq_prod; /* valid iff FUNC_FLG_SPQ */
1768 };
1769
1770 #define for_each_cnic_queue(bp, var) \
1771 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1772 (var)++) \
1773 if (skip_queue(bp, var)) \
1774 continue; \
1775 else
1776
1777 #define for_each_eth_queue(bp, var) \
1778 for ((var) = 0; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1779
1780 #define for_each_nondefault_eth_queue(bp, var) \
1781 for ((var) = 1; (var) < BNX2X_NUM_ETH_QUEUES(bp); (var)++)
1782
1783 #define for_each_queue(bp, var) \
1784 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1785 if (skip_queue(bp, var)) \
1786 continue; \
1787 else
1788
1789 /* Skip forwarding FP */
1790 #define for_each_valid_rx_queue(bp, var) \
1791 for ((var) = 0; \
1792 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1793 BNX2X_NUM_ETH_QUEUES(bp)); \
1794 (var)++) \
1795 if (skip_rx_queue(bp, var)) \
1796 continue; \
1797 else
1798
1799 #define for_each_rx_queue_cnic(bp, var) \
1800 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1801 (var)++) \
1802 if (skip_rx_queue(bp, var)) \
1803 continue; \
1804 else
1805
1806 #define for_each_rx_queue(bp, var) \
1807 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1808 if (skip_rx_queue(bp, var)) \
1809 continue; \
1810 else
1811
1812 /* Skip OOO FP */
1813 #define for_each_valid_tx_queue(bp, var) \
1814 for ((var) = 0; \
1815 (var) < (CNIC_LOADED(bp) ? BNX2X_NUM_QUEUES(bp) : \
1816 BNX2X_NUM_ETH_QUEUES(bp)); \
1817 (var)++) \
1818 if (skip_tx_queue(bp, var)) \
1819 continue; \
1820 else
1821
1822 #define for_each_tx_queue_cnic(bp, var) \
1823 for ((var) = BNX2X_NUM_ETH_QUEUES(bp); (var) < BNX2X_NUM_QUEUES(bp); \
1824 (var)++) \
1825 if (skip_tx_queue(bp, var)) \
1826 continue; \
1827 else
1828
1829 #define for_each_tx_queue(bp, var) \
1830 for ((var) = 0; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1831 if (skip_tx_queue(bp, var)) \
1832 continue; \
1833 else
1834
1835 #define for_each_nondefault_queue(bp, var) \
1836 for ((var) = 1; (var) < BNX2X_NUM_QUEUES(bp); (var)++) \
1837 if (skip_queue(bp, var)) \
1838 continue; \
1839 else
1840
1841 #define for_each_cos_in_tx_queue(fp, var) \
1842 for ((var) = 0; (var) < (fp)->max_cos; (var)++)
1843
1844 /* skip rx queue
1845 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1846 */
1847 #define skip_rx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1848
1849 /* skip tx queue
1850 * if FCOE l2 support is disabled and this is the fcoe L2 queue
1851 */
1852 #define skip_tx_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1853
1854 #define skip_queue(bp, idx) (NO_FCOE(bp) && IS_FCOE_IDX(idx))
1855
1856
1857
1858
1859 /**
1860 * bnx2x_set_mac_one - configure a single MAC address
1861 *
1862 * @bp: driver handle
1863 * @mac: MAC to configure
1864 * @obj: MAC object handle
1865 * @set: if 'true' add a new MAC, otherwise - delete
1866 * @mac_type: the type of the MAC to configure (e.g. ETH, UC list)
1867 * @ramrod_flags: RAMROD_XXX flags (e.g. RAMROD_CONT, RAMROD_COMP_WAIT)
1868 *
1869 * Configures one MAC according to provided parameters or continues the
1870 * execution of previously scheduled commands if RAMROD_CONT is set in
1871 * ramrod_flags.
1872 *
1873 * Returns zero if operation has successfully completed, a positive value if the
1874 * operation has been successfully scheduled and a negative - if a requested
1875 * operations has failed.
1876 */
1877 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
1878 struct bnx2x_vlan_mac_obj *obj, bool set,
1879 int mac_type, unsigned long *ramrod_flags);
1880 /**
1881 * bnx2x_del_all_macs - delete all MACs configured for the specific MAC object
1882 *
1883 * @bp: driver handle
1884 * @mac_obj: MAC object handle
1885 * @mac_type: type of the MACs to clear (BNX2X_XXX_MAC)
1886 * @wait_for_comp: if 'true' block until completion
1887 *
1888 * Deletes all MACs of the specific type (e.g. ETH, UC list).
1889 *
1890 * Returns zero if operation has successfully completed, a positive value if the
1891 * operation has been successfully scheduled and a negative - if a requested
1892 * operations has failed.
1893 */
1894 int bnx2x_del_all_macs(struct bnx2x *bp,
1895 struct bnx2x_vlan_mac_obj *mac_obj,
1896 int mac_type, bool wait_for_comp);
1897
1898 /* Init Function API */
1899 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p);
1900 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
1901 u8 vf_valid, int fw_sb_id, int igu_sb_id);
1902 u32 bnx2x_get_pretend_reg(struct bnx2x *bp);
1903 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port);
1904 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1905 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode);
1906 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port);
1907 void bnx2x_read_mf_cfg(struct bnx2x *bp);
1908
1909 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val);
1910
1911 /* dmae */
1912 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32);
1913 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
1914 u32 len32);
1915 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx);
1916 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type);
1917 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode);
1918 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
1919 bool with_comp, u8 comp_type);
1920
1921 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
1922 u8 src_type, u8 dst_type);
1923 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae);
1924 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl);
1925
1926 /* FLR related routines */
1927 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp);
1928 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count);
1929 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt);
1930 u8 bnx2x_is_pcie_pending(struct pci_dev *dev);
1931 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1932 char *msg, u32 poll_cnt);
1933
1934 void bnx2x_calc_fc_adv(struct bnx2x *bp);
1935 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
1936 u32 data_hi, u32 data_lo, int cmd_type);
1937 void bnx2x_update_coalesce(struct bnx2x *bp);
1938 int bnx2x_get_cur_phy_idx(struct bnx2x *bp);
1939
1940 static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1941 int wait)
1942 {
1943 u32 val;
1944
1945 do {
1946 val = REG_RD(bp, reg);
1947 if (val == expected)
1948 break;
1949 ms -= wait;
1950 msleep(wait);
1951
1952 } while (ms > 0);
1953
1954 return val;
1955 }
1956
1957 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id,
1958 bool is_pf);
1959
1960 #define BNX2X_ILT_ZALLOC(x, y, size) \
1961 x = dma_alloc_coherent(&bp->pdev->dev, size, y, \
1962 GFP_KERNEL | __GFP_ZERO)
1963
1964 #define BNX2X_ILT_FREE(x, y, size) \
1965 do { \
1966 if (x) { \
1967 dma_free_coherent(&bp->pdev->dev, size, x, y); \
1968 x = NULL; \
1969 y = 0; \
1970 } \
1971 } while (0)
1972
1973 #define ILOG2(x) (ilog2((x)))
1974
1975 #define ILT_NUM_PAGE_ENTRIES (3072)
1976 /* In 57710/11 we use whole table since we have 8 func
1977 * In 57712 we have only 4 func, but use same size per func, then only half of
1978 * the table in use
1979 */
1980 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES/8)
1981
1982 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
1983 /*
1984 * the phys address is shifted right 12 bits and has an added
1985 * 1=valid bit added to the 53rd bit
1986 * then since this is a wide register(TM)
1987 * we split it into two 32 bit writes
1988 */
1989 #define ONCHIP_ADDR1(x) ((u32)(((u64)x >> 12) & 0xFFFFFFFF))
1990 #define ONCHIP_ADDR2(x) ((u32)((1 << 20) | ((u64)x >> 44)))
1991
1992 /* load/unload mode */
1993 #define LOAD_NORMAL 0
1994 #define LOAD_OPEN 1
1995 #define LOAD_DIAG 2
1996 #define LOAD_LOOPBACK_EXT 3
1997 #define UNLOAD_NORMAL 0
1998 #define UNLOAD_CLOSE 1
1999 #define UNLOAD_RECOVERY 2
2000
2001
2002 /* DMAE command defines */
2003 #define DMAE_TIMEOUT -1
2004 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2005 #define DMAE_NOT_RDY -3
2006 #define DMAE_PCI_ERR_FLAG 0x80000000
2007
2008 #define DMAE_SRC_PCI 0
2009 #define DMAE_SRC_GRC 1
2010
2011 #define DMAE_DST_NONE 0
2012 #define DMAE_DST_PCI 1
2013 #define DMAE_DST_GRC 2
2014
2015 #define DMAE_COMP_PCI 0
2016 #define DMAE_COMP_GRC 1
2017
2018 /* E2 and onward - PCI error handling in the completion */
2019
2020 #define DMAE_COMP_REGULAR 0
2021 #define DMAE_COM_SET_ERR 1
2022
2023 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << \
2024 DMAE_COMMAND_SRC_SHIFT)
2025 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << \
2026 DMAE_COMMAND_SRC_SHIFT)
2027
2028 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << \
2029 DMAE_COMMAND_DST_SHIFT)
2030 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << \
2031 DMAE_COMMAND_DST_SHIFT)
2032
2033 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << \
2034 DMAE_COMMAND_C_DST_SHIFT)
2035 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << \
2036 DMAE_COMMAND_C_DST_SHIFT)
2037
2038 #define DMAE_CMD_C_ENABLE DMAE_COMMAND_C_TYPE_ENABLE
2039
2040 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2041 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2042 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2043 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2044
2045 #define DMAE_CMD_PORT_0 0
2046 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2047
2048 #define DMAE_CMD_SRC_RESET DMAE_COMMAND_SRC_RESET
2049 #define DMAE_CMD_DST_RESET DMAE_COMMAND_DST_RESET
2050 #define DMAE_CMD_E1HVN_SHIFT DMAE_COMMAND_E1HVN_SHIFT
2051
2052 #define DMAE_SRC_PF 0
2053 #define DMAE_SRC_VF 1
2054
2055 #define DMAE_DST_PF 0
2056 #define DMAE_DST_VF 1
2057
2058 #define DMAE_C_SRC 0
2059 #define DMAE_C_DST 1
2060
2061 #define DMAE_LEN32_RD_MAX 0x80
2062 #define DMAE_LEN32_WR_MAX(bp) (CHIP_IS_E1(bp) ? 0x400 : 0x2000)
2063
2064 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and on - upper bit
2065 indicates eror */
2066
2067 #define MAX_DMAE_C_PER_PORT 8
2068 #define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2069 BP_VN(bp))
2070 #define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
2071 E1HVN_MAX)
2072
2073 /* PCIE link and speed */
2074 #define PCICFG_LINK_WIDTH 0x1f00000
2075 #define PCICFG_LINK_WIDTH_SHIFT 20
2076 #define PCICFG_LINK_SPEED 0xf0000
2077 #define PCICFG_LINK_SPEED_SHIFT 16
2078
2079 #define BNX2X_NUM_TESTS_SF 7
2080 #define BNX2X_NUM_TESTS_MF 3
2081 #define BNX2X_NUM_TESTS(bp) (IS_MF(bp) ? BNX2X_NUM_TESTS_MF : \
2082 BNX2X_NUM_TESTS_SF)
2083
2084 #define BNX2X_PHY_LOOPBACK 0
2085 #define BNX2X_MAC_LOOPBACK 1
2086 #define BNX2X_EXT_LOOPBACK 2
2087 #define BNX2X_PHY_LOOPBACK_FAILED 1
2088 #define BNX2X_MAC_LOOPBACK_FAILED 2
2089 #define BNX2X_EXT_LOOPBACK_FAILED 3
2090 #define BNX2X_LOOPBACK_FAILED (BNX2X_MAC_LOOPBACK_FAILED | \
2091 BNX2X_PHY_LOOPBACK_FAILED)
2092
2093 #define STROM_ASSERT_ARRAY_SIZE 50
2094
2095 /* must be used on a CID before placing it on a HW ring */
2096 #define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
2097 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
2098 (x))
2099
2100 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
2101 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
2102
2103
2104 #define BNX2X_BTR 4
2105 #define MAX_SPQ_PENDING 8
2106
2107 /* CMNG constants, as derived from system spec calculations */
2108 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
2109 #define DEF_MIN_RATE 100
2110 /* resolution of the rate shaping timer - 400 usec */
2111 #define RS_PERIODIC_TIMEOUT_USEC 400
2112 /* number of bytes in single QM arbitration cycle -
2113 * coefficient for calculating the fairness timer */
2114 #define QM_ARB_BYTES 160000
2115 /* resolution of Min algorithm 1:100 */
2116 #define MIN_RES 100
2117 /* how many bytes above threshold for the minimal credit of Min algorithm*/
2118 #define MIN_ABOVE_THRESH 32768
2119 /* Fairness algorithm integration time coefficient -
2120 * for calculating the actual Tfair */
2121 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
2122 /* Memory of fairness algorithm . 2 cycles */
2123 #define FAIR_MEM 2
2124
2125 #define ATTN_NIG_FOR_FUNC (1L << 8)
2126 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2127 #define GPIO_2_FUNC (1L << 10)
2128 #define GPIO_3_FUNC (1L << 11)
2129 #define GPIO_4_FUNC (1L << 12)
2130 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2131 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2132 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2133 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2134 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2135 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2136
2137 #define ATTN_HARD_WIRED_MASK 0xff00
2138 #define ATTENTION_ID 4
2139
2140 #define IS_MF_STORAGE_ONLY(bp) (IS_MF_STORAGE_SD(bp) || \
2141 IS_MF_FCOE_AFEX(bp))
2142
2143 /* stuff added to make the code fit 80Col */
2144
2145 #define BNX2X_PMF_LINK_ASSERT \
2146 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + BP_FUNC(bp))
2147
2148 #define BNX2X_MC_ASSERT_BITS \
2149 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2150 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2151 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2152 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2153
2154 #define BNX2X_MCP_ASSERT \
2155 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2156
2157 #define BNX2X_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2158 #define BNX2X_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2159 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2160 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2161 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2162 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2163 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2164
2165 #define HW_INTERRUT_ASSERT_SET_0 \
2166 (AEU_INPUTS_ATTN_BITS_TSDM_HW_INTERRUPT | \
2167 AEU_INPUTS_ATTN_BITS_TCM_HW_INTERRUPT | \
2168 AEU_INPUTS_ATTN_BITS_TSEMI_HW_INTERRUPT | \
2169 AEU_INPUTS_ATTN_BITS_BRB_HW_INTERRUPT | \
2170 AEU_INPUTS_ATTN_BITS_PBCLIENT_HW_INTERRUPT)
2171 #define HW_PRTY_ASSERT_SET_0 (AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR | \
2172 AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR | \
2173 AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR | \
2174 AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR |\
2175 AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR |\
2176 AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR |\
2177 AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR)
2178 #define HW_INTERRUT_ASSERT_SET_1 \
2179 (AEU_INPUTS_ATTN_BITS_QM_HW_INTERRUPT | \
2180 AEU_INPUTS_ATTN_BITS_TIMERS_HW_INTERRUPT | \
2181 AEU_INPUTS_ATTN_BITS_XSDM_HW_INTERRUPT | \
2182 AEU_INPUTS_ATTN_BITS_XCM_HW_INTERRUPT | \
2183 AEU_INPUTS_ATTN_BITS_XSEMI_HW_INTERRUPT | \
2184 AEU_INPUTS_ATTN_BITS_USDM_HW_INTERRUPT | \
2185 AEU_INPUTS_ATTN_BITS_UCM_HW_INTERRUPT | \
2186 AEU_INPUTS_ATTN_BITS_USEMI_HW_INTERRUPT | \
2187 AEU_INPUTS_ATTN_BITS_UPB_HW_INTERRUPT | \
2188 AEU_INPUTS_ATTN_BITS_CSDM_HW_INTERRUPT | \
2189 AEU_INPUTS_ATTN_BITS_CCM_HW_INTERRUPT)
2190 #define HW_PRTY_ASSERT_SET_1 (AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR |\
2191 AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR | \
2192 AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR |\
2193 AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR | \
2194 AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR |\
2195 AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR | \
2196 AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR |\
2197 AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR |\
2198 AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR |\
2199 AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR | \
2200 AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR | \
2201 AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR |\
2202 AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR | \
2203 AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR | \
2204 AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR |\
2205 AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR)
2206 #define HW_INTERRUT_ASSERT_SET_2 \
2207 (AEU_INPUTS_ATTN_BITS_CSEMI_HW_INTERRUPT | \
2208 AEU_INPUTS_ATTN_BITS_CDU_HW_INTERRUPT | \
2209 AEU_INPUTS_ATTN_BITS_DMAE_HW_INTERRUPT | \
2210 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT |\
2211 AEU_INPUTS_ATTN_BITS_MISC_HW_INTERRUPT)
2212 #define HW_PRTY_ASSERT_SET_2 (AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR | \
2213 AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR | \
2214 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR |\
2215 AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR | \
2216 AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR | \
2217 AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR |\
2218 AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR | \
2219 AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR)
2220
2221 #define HW_PRTY_ASSERT_SET_3 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \
2222 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \
2223 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY | \
2224 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY)
2225
2226 #define HW_PRTY_ASSERT_SET_4 (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | \
2227 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)
2228
2229 #define MULTI_MASK 0x7f
2230
2231 #define DEF_USB_FUNC_OFF offsetof(struct cstorm_def_status_block_u, func)
2232 #define DEF_CSB_FUNC_OFF offsetof(struct cstorm_def_status_block_c, func)
2233 #define DEF_XSB_FUNC_OFF offsetof(struct xstorm_def_status_block, func)
2234 #define DEF_TSB_FUNC_OFF offsetof(struct tstorm_def_status_block, func)
2235
2236 #define DEF_USB_IGU_INDEX_OFF \
2237 offsetof(struct cstorm_def_status_block_u, igu_index)
2238 #define DEF_CSB_IGU_INDEX_OFF \
2239 offsetof(struct cstorm_def_status_block_c, igu_index)
2240 #define DEF_XSB_IGU_INDEX_OFF \
2241 offsetof(struct xstorm_def_status_block, igu_index)
2242 #define DEF_TSB_IGU_INDEX_OFF \
2243 offsetof(struct tstorm_def_status_block, igu_index)
2244
2245 #define DEF_USB_SEGMENT_OFF \
2246 offsetof(struct cstorm_def_status_block_u, segment)
2247 #define DEF_CSB_SEGMENT_OFF \
2248 offsetof(struct cstorm_def_status_block_c, segment)
2249 #define DEF_XSB_SEGMENT_OFF \
2250 offsetof(struct xstorm_def_status_block, segment)
2251 #define DEF_TSB_SEGMENT_OFF \
2252 offsetof(struct tstorm_def_status_block, segment)
2253
2254 #define BNX2X_SP_DSB_INDEX \
2255 (&bp->def_status_blk->sp_sb.\
2256 index_values[HC_SP_INDEX_ETH_DEF_CONS])
2257
2258 #define CAM_IS_INVALID(x) \
2259 (GET_FLAG(x.flags, \
2260 MAC_CONFIGURATION_ENTRY_ACTION_TYPE) == \
2261 (T_ETH_MAC_COMMAND_INVALIDATE))
2262
2263 /* Number of u32 elements in MC hash array */
2264 #define MC_HASH_SIZE 8
2265 #define MC_HASH_OFFSET(bp, i) (BAR_TSTRORM_INTMEM + \
2266 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(BP_FUNC(bp)) + i*4)
2267
2268 #ifndef PXP2_REG_PXP2_INT_STS
2269 #define PXP2_REG_PXP2_INT_STS PXP2_REG_PXP2_INT_STS_0
2270 #endif
2271
2272 #ifndef ETH_MAX_RX_CLIENTS_E2
2273 #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
2274 #endif
2275
2276 #define BNX2X_VPD_LEN 128
2277 #define VENDOR_ID_LEN 4
2278
2279 #define VF_ACQUIRE_THRESH 3
2280 #define VF_ACQUIRE_MAC_FILTERS 1
2281 #define VF_ACQUIRE_MC_FILTERS 10
2282
2283 #define GOOD_ME_REG(me_reg) (((me_reg) & ME_REG_VF_VALID) && \
2284 (!((me_reg) & ME_REG_VF_ERR)))
2285 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code);
2286 /* Congestion management fairness mode */
2287 #define CMNG_FNS_NONE 0
2288 #define CMNG_FNS_MINMAX 1
2289
2290 #define HC_SEG_ACCESS_DEF 0 /*Driver decision 0-3*/
2291 #define HC_SEG_ACCESS_ATTN 4
2292 #define HC_SEG_ACCESS_NORM 0 /*Driver decision 0-1*/
2293
2294 static const u32 dmae_reg_go_c[] = {
2295 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2296 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2297 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2298 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2299 };
2300
2301 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev);
2302 void bnx2x_notify_link_changed(struct bnx2x *bp);
2303
2304 #define BNX2X_MF_SD_PROTOCOL(bp) \
2305 ((bp)->mf_config[BP_VN(bp)] & FUNC_MF_CFG_PROTOCOL_MASK)
2306
2307 #define BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) \
2308 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_ISCSI)
2309
2310 #define BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp) \
2311 (BNX2X_MF_SD_PROTOCOL(bp) == FUNC_MF_CFG_PROTOCOL_FCOE)
2312
2313 #define IS_MF_ISCSI_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp))
2314 #define IS_MF_FCOE_SD(bp) (IS_MF_SD(bp) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp))
2315
2316 #define BNX2X_MF_EXT_PROTOCOL_FCOE(bp) ((bp)->mf_ext_config & \
2317 MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD)
2318
2319 #define IS_MF_FCOE_AFEX(bp) (IS_MF_AFEX(bp) && BNX2X_MF_EXT_PROTOCOL_FCOE(bp))
2320 #define IS_MF_STORAGE_SD(bp) (IS_MF_SD(bp) && \
2321 (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp) || \
2322 BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)))
2323
2324 #define SET_FLAG(value, mask, flag) \
2325 do {\
2326 (value) &= ~(mask);\
2327 (value) |= ((flag) << (mask##_SHIFT));\
2328 } while (0)
2329
2330 #define GET_FLAG(value, mask) \
2331 (((value) & (mask)) >> (mask##_SHIFT))
2332
2333 #define GET_FIELD(value, fname) \
2334 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
2335
2336 enum {
2337 SWITCH_UPDATE,
2338 AFEX_UPDATE,
2339 };
2340
2341 #define NUM_MACS 8
2342
2343 #endif /* bnx2x.h */
Linux kernel - Deliverables
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