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[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_cmn.c
1 /* bnx2x_cmn.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/etherdevice.h>
21 #include <linux/if_vlan.h>
22 #include <linux/interrupt.h>
23 #include <linux/ip.h>
24 #include <net/tcp.h>
25 #include <net/ipv6.h>
26 #include <net/ip6_checksum.h>
27 #include <linux/prefetch.h>
28 #include "bnx2x_cmn.h"
29 #include "bnx2x_init.h"
30 #include "bnx2x_sp.h"
31
32 /**
33 * bnx2x_move_fp - move content of the fastpath structure.
34 *
35 * @bp: driver handle
36 * @from: source FP index
37 * @to: destination FP index
38 *
39 * Makes sure the contents of the bp->fp[to].napi is kept
40 * intact. This is done by first copying the napi struct from
41 * the target to the source, and then mem copying the entire
42 * source onto the target. Update txdata pointers and related
43 * content.
44 */
45 static inline void bnx2x_move_fp(struct bnx2x *bp, int from, int to)
46 {
47 struct bnx2x_fastpath *from_fp = &bp->fp[from];
48 struct bnx2x_fastpath *to_fp = &bp->fp[to];
49 struct bnx2x_sp_objs *from_sp_objs = &bp->sp_objs[from];
50 struct bnx2x_sp_objs *to_sp_objs = &bp->sp_objs[to];
51 struct bnx2x_fp_stats *from_fp_stats = &bp->fp_stats[from];
52 struct bnx2x_fp_stats *to_fp_stats = &bp->fp_stats[to];
53 int old_max_eth_txqs, new_max_eth_txqs;
54 int old_txdata_index = 0, new_txdata_index = 0;
55
56 /* Copy the NAPI object as it has been already initialized */
57 from_fp->napi = to_fp->napi;
58
59 /* Move bnx2x_fastpath contents */
60 memcpy(to_fp, from_fp, sizeof(*to_fp));
61 to_fp->index = to;
62
63 /* move sp_objs contents as well, as their indices match fp ones */
64 memcpy(to_sp_objs, from_sp_objs, sizeof(*to_sp_objs));
65
66 /* move fp_stats contents as well, as their indices match fp ones */
67 memcpy(to_fp_stats, from_fp_stats, sizeof(*to_fp_stats));
68
69 /* Update txdata pointers in fp and move txdata content accordingly:
70 * Each fp consumes 'max_cos' txdata structures, so the index should be
71 * decremented by max_cos x delta.
72 */
73
74 old_max_eth_txqs = BNX2X_NUM_ETH_QUEUES(bp) * (bp)->max_cos;
75 new_max_eth_txqs = (BNX2X_NUM_ETH_QUEUES(bp) - from + to) *
76 (bp)->max_cos;
77 if (from == FCOE_IDX(bp)) {
78 old_txdata_index = old_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
79 new_txdata_index = new_max_eth_txqs + FCOE_TXQ_IDX_OFFSET;
80 }
81
82 memcpy(&bp->bnx2x_txq[new_txdata_index],
83 &bp->bnx2x_txq[old_txdata_index],
84 sizeof(struct bnx2x_fp_txdata));
85 to_fp->txdata_ptr[0] = &bp->bnx2x_txq[new_txdata_index];
86 }
87
88 /**
89 * bnx2x_fill_fw_str - Fill buffer with FW version string.
90 *
91 * @bp: driver handle
92 * @buf: character buffer to fill with the fw name
93 * @buf_len: length of the above buffer
94 *
95 */
96 void bnx2x_fill_fw_str(struct bnx2x *bp, char *buf, size_t buf_len)
97 {
98 if (IS_PF(bp)) {
99 u8 phy_fw_ver[PHY_FW_VER_LEN];
100
101 phy_fw_ver[0] = '\0';
102 bnx2x_get_ext_phy_fw_version(&bp->link_params,
103 phy_fw_ver, PHY_FW_VER_LEN);
104 strlcpy(buf, bp->fw_ver, buf_len);
105 snprintf(buf + strlen(bp->fw_ver), 32 - strlen(bp->fw_ver),
106 "bc %d.%d.%d%s%s",
107 (bp->common.bc_ver & 0xff0000) >> 16,
108 (bp->common.bc_ver & 0xff00) >> 8,
109 (bp->common.bc_ver & 0xff),
110 ((phy_fw_ver[0] != '\0') ? " phy " : ""), phy_fw_ver);
111 } else {
112 bnx2x_vf_fill_fw_str(bp, buf, buf_len);
113 }
114 }
115
116 /**
117 * bnx2x_shrink_eth_fp - guarantees fastpath structures stay intact
118 *
119 * @bp: driver handle
120 * @delta: number of eth queues which were not allocated
121 */
122 static void bnx2x_shrink_eth_fp(struct bnx2x *bp, int delta)
123 {
124 int i, cos, old_eth_num = BNX2X_NUM_ETH_QUEUES(bp);
125
126 /* Queue pointer cannot be re-set on an fp-basis, as moving pointer
127 * backward along the array could cause memory to be overriden
128 */
129 for (cos = 1; cos < bp->max_cos; cos++) {
130 for (i = 0; i < old_eth_num - delta; i++) {
131 struct bnx2x_fastpath *fp = &bp->fp[i];
132 int new_idx = cos * (old_eth_num - delta) + i;
133
134 memcpy(&bp->bnx2x_txq[new_idx], fp->txdata_ptr[cos],
135 sizeof(struct bnx2x_fp_txdata));
136 fp->txdata_ptr[cos] = &bp->bnx2x_txq[new_idx];
137 }
138 }
139 }
140
141 int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */
142
143 /* free skb in the packet ring at pos idx
144 * return idx of last bd freed
145 */
146 static u16 bnx2x_free_tx_pkt(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata,
147 u16 idx, unsigned int *pkts_compl,
148 unsigned int *bytes_compl)
149 {
150 struct sw_tx_bd *tx_buf = &txdata->tx_buf_ring[idx];
151 struct eth_tx_start_bd *tx_start_bd;
152 struct eth_tx_bd *tx_data_bd;
153 struct sk_buff *skb = tx_buf->skb;
154 u16 bd_idx = TX_BD(tx_buf->first_bd), new_cons;
155 int nbd;
156
157 /* prefetch skb end pointer to speedup dev_kfree_skb() */
158 prefetch(&skb->end);
159
160 DP(NETIF_MSG_TX_DONE, "fp[%d]: pkt_idx %d buff @(%p)->skb %p\n",
161 txdata->txq_index, idx, tx_buf, skb);
162
163 /* unmap first bd */
164 tx_start_bd = &txdata->tx_desc_ring[bd_idx].start_bd;
165 dma_unmap_single(&bp->pdev->dev, BD_UNMAP_ADDR(tx_start_bd),
166 BD_UNMAP_LEN(tx_start_bd), DMA_TO_DEVICE);
167
168
169 nbd = le16_to_cpu(tx_start_bd->nbd) - 1;
170 #ifdef BNX2X_STOP_ON_ERROR
171 if ((nbd - 1) > (MAX_SKB_FRAGS + 2)) {
172 BNX2X_ERR("BAD nbd!\n");
173 bnx2x_panic();
174 }
175 #endif
176 new_cons = nbd + tx_buf->first_bd;
177
178 /* Get the next bd */
179 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
180
181 /* Skip a parse bd... */
182 --nbd;
183 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
184
185 /* ...and the TSO split header bd since they have no mapping */
186 if (tx_buf->flags & BNX2X_TSO_SPLIT_BD) {
187 --nbd;
188 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
189 }
190
191 /* now free frags */
192 while (nbd > 0) {
193
194 tx_data_bd = &txdata->tx_desc_ring[bd_idx].reg_bd;
195 dma_unmap_page(&bp->pdev->dev, BD_UNMAP_ADDR(tx_data_bd),
196 BD_UNMAP_LEN(tx_data_bd), DMA_TO_DEVICE);
197 if (--nbd)
198 bd_idx = TX_BD(NEXT_TX_IDX(bd_idx));
199 }
200
201 /* release skb */
202 WARN_ON(!skb);
203 if (likely(skb)) {
204 (*pkts_compl)++;
205 (*bytes_compl) += skb->len;
206 }
207
208 dev_kfree_skb_any(skb);
209 tx_buf->first_bd = 0;
210 tx_buf->skb = NULL;
211
212 return new_cons;
213 }
214
215 int bnx2x_tx_int(struct bnx2x *bp, struct bnx2x_fp_txdata *txdata)
216 {
217 struct netdev_queue *txq;
218 u16 hw_cons, sw_cons, bd_cons = txdata->tx_bd_cons;
219 unsigned int pkts_compl = 0, bytes_compl = 0;
220
221 #ifdef BNX2X_STOP_ON_ERROR
222 if (unlikely(bp->panic))
223 return -1;
224 #endif
225
226 txq = netdev_get_tx_queue(bp->dev, txdata->txq_index);
227 hw_cons = le16_to_cpu(*txdata->tx_cons_sb);
228 sw_cons = txdata->tx_pkt_cons;
229
230 while (sw_cons != hw_cons) {
231 u16 pkt_cons;
232
233 pkt_cons = TX_BD(sw_cons);
234
235 DP(NETIF_MSG_TX_DONE,
236 "queue[%d]: hw_cons %u sw_cons %u pkt_cons %u\n",
237 txdata->txq_index, hw_cons, sw_cons, pkt_cons);
238
239 bd_cons = bnx2x_free_tx_pkt(bp, txdata, pkt_cons,
240 &pkts_compl, &bytes_compl);
241
242 sw_cons++;
243 }
244
245 netdev_tx_completed_queue(txq, pkts_compl, bytes_compl);
246
247 txdata->tx_pkt_cons = sw_cons;
248 txdata->tx_bd_cons = bd_cons;
249
250 /* Need to make the tx_bd_cons update visible to start_xmit()
251 * before checking for netif_tx_queue_stopped(). Without the
252 * memory barrier, there is a small possibility that
253 * start_xmit() will miss it and cause the queue to be stopped
254 * forever.
255 * On the other hand we need an rmb() here to ensure the proper
256 * ordering of bit testing in the following
257 * netif_tx_queue_stopped(txq) call.
258 */
259 smp_mb();
260
261 if (unlikely(netif_tx_queue_stopped(txq))) {
262 /* Taking tx_lock() is needed to prevent reenabling the queue
263 * while it's empty. This could have happen if rx_action() gets
264 * suspended in bnx2x_tx_int() after the condition before
265 * netif_tx_wake_queue(), while tx_action (bnx2x_start_xmit()):
266 *
267 * stops the queue->sees fresh tx_bd_cons->releases the queue->
268 * sends some packets consuming the whole queue again->
269 * stops the queue
270 */
271
272 __netif_tx_lock(txq, smp_processor_id());
273
274 if ((netif_tx_queue_stopped(txq)) &&
275 (bp->state == BNX2X_STATE_OPEN) &&
276 (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT))
277 netif_tx_wake_queue(txq);
278
279 __netif_tx_unlock(txq);
280 }
281 return 0;
282 }
283
284 static inline void bnx2x_update_last_max_sge(struct bnx2x_fastpath *fp,
285 u16 idx)
286 {
287 u16 last_max = fp->last_max_sge;
288
289 if (SUB_S16(idx, last_max) > 0)
290 fp->last_max_sge = idx;
291 }
292
293 static inline void bnx2x_update_sge_prod(struct bnx2x_fastpath *fp,
294 u16 sge_len,
295 struct eth_end_agg_rx_cqe *cqe)
296 {
297 struct bnx2x *bp = fp->bp;
298 u16 last_max, last_elem, first_elem;
299 u16 delta = 0;
300 u16 i;
301
302 if (!sge_len)
303 return;
304
305 /* First mark all used pages */
306 for (i = 0; i < sge_len; i++)
307 BIT_VEC64_CLEAR_BIT(fp->sge_mask,
308 RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[i])));
309
310 DP(NETIF_MSG_RX_STATUS, "fp_cqe->sgl[%d] = %d\n",
311 sge_len - 1, le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
312
313 /* Here we assume that the last SGE index is the biggest */
314 prefetch((void *)(fp->sge_mask));
315 bnx2x_update_last_max_sge(fp,
316 le16_to_cpu(cqe->sgl_or_raw_data.sgl[sge_len - 1]));
317
318 last_max = RX_SGE(fp->last_max_sge);
319 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT;
320 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT;
321
322 /* If ring is not full */
323 if (last_elem + 1 != first_elem)
324 last_elem++;
325
326 /* Now update the prod */
327 for (i = first_elem; i != last_elem; i = NEXT_SGE_MASK_ELEM(i)) {
328 if (likely(fp->sge_mask[i]))
329 break;
330
331 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK;
332 delta += BIT_VEC64_ELEM_SZ;
333 }
334
335 if (delta > 0) {
336 fp->rx_sge_prod += delta;
337 /* clear page-end entries */
338 bnx2x_clear_sge_mask_next_elems(fp);
339 }
340
341 DP(NETIF_MSG_RX_STATUS,
342 "fp->last_max_sge = %d fp->rx_sge_prod = %d\n",
343 fp->last_max_sge, fp->rx_sge_prod);
344 }
345
346 /* Get Toeplitz hash value in the skb using the value from the
347 * CQE (calculated by HW).
348 */
349 static u32 bnx2x_get_rxhash(const struct bnx2x *bp,
350 const struct eth_fast_path_rx_cqe *cqe,
351 bool *l4_rxhash)
352 {
353 /* Get Toeplitz hash from CQE */
354 if ((bp->dev->features & NETIF_F_RXHASH) &&
355 (cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG)) {
356 enum eth_rss_hash_type htype;
357
358 htype = cqe->status_flags & ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE;
359 *l4_rxhash = (htype == TCP_IPV4_HASH_TYPE) ||
360 (htype == TCP_IPV6_HASH_TYPE);
361 return le32_to_cpu(cqe->rss_hash_result);
362 }
363 *l4_rxhash = false;
364 return 0;
365 }
366
367 static void bnx2x_tpa_start(struct bnx2x_fastpath *fp, u16 queue,
368 u16 cons, u16 prod,
369 struct eth_fast_path_rx_cqe *cqe)
370 {
371 struct bnx2x *bp = fp->bp;
372 struct sw_rx_bd *cons_rx_buf = &fp->rx_buf_ring[cons];
373 struct sw_rx_bd *prod_rx_buf = &fp->rx_buf_ring[prod];
374 struct eth_rx_bd *prod_bd = &fp->rx_desc_ring[prod];
375 dma_addr_t mapping;
376 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[queue];
377 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
378
379 /* print error if current state != stop */
380 if (tpa_info->tpa_state != BNX2X_TPA_STOP)
381 BNX2X_ERR("start of bin not in stop [%d]\n", queue);
382
383 /* Try to map an empty data buffer from the aggregation info */
384 mapping = dma_map_single(&bp->pdev->dev,
385 first_buf->data + NET_SKB_PAD,
386 fp->rx_buf_size, DMA_FROM_DEVICE);
387 /*
388 * ...if it fails - move the skb from the consumer to the producer
389 * and set the current aggregation state as ERROR to drop it
390 * when TPA_STOP arrives.
391 */
392
393 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
394 /* Move the BD from the consumer to the producer */
395 bnx2x_reuse_rx_data(fp, cons, prod);
396 tpa_info->tpa_state = BNX2X_TPA_ERROR;
397 return;
398 }
399
400 /* move empty data from pool to prod */
401 prod_rx_buf->data = first_buf->data;
402 dma_unmap_addr_set(prod_rx_buf, mapping, mapping);
403 /* point prod_bd to new data */
404 prod_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
405 prod_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
406
407 /* move partial skb from cons to pool (don't unmap yet) */
408 *first_buf = *cons_rx_buf;
409
410 /* mark bin state as START */
411 tpa_info->parsing_flags =
412 le16_to_cpu(cqe->pars_flags.flags);
413 tpa_info->vlan_tag = le16_to_cpu(cqe->vlan_tag);
414 tpa_info->tpa_state = BNX2X_TPA_START;
415 tpa_info->len_on_bd = le16_to_cpu(cqe->len_on_bd);
416 tpa_info->placement_offset = cqe->placement_offset;
417 tpa_info->rxhash = bnx2x_get_rxhash(bp, cqe, &tpa_info->l4_rxhash);
418 if (fp->mode == TPA_MODE_GRO) {
419 u16 gro_size = le16_to_cpu(cqe->pkt_len_or_gro_seg_len);
420 tpa_info->full_page = SGE_PAGES / gro_size * gro_size;
421 tpa_info->gro_size = gro_size;
422 }
423
424 #ifdef BNX2X_STOP_ON_ERROR
425 fp->tpa_queue_used |= (1 << queue);
426 #ifdef _ASM_GENERIC_INT_L64_H
427 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%lx\n",
428 #else
429 DP(NETIF_MSG_RX_STATUS, "fp->tpa_queue_used = 0x%llx\n",
430 #endif
431 fp->tpa_queue_used);
432 #endif
433 }
434
435 /* Timestamp option length allowed for TPA aggregation:
436 *
437 * nop nop kind length echo val
438 */
439 #define TPA_TSTAMP_OPT_LEN 12
440 /**
441 * bnx2x_set_gro_params - compute GRO values
442 *
443 * @skb: packet skb
444 * @parsing_flags: parsing flags from the START CQE
445 * @len_on_bd: total length of the first packet for the
446 * aggregation.
447 * @pkt_len: length of all segments
448 *
449 * Approximate value of the MSS for this aggregation calculated using
450 * the first packet of it.
451 * Compute number of aggregated segments, and gso_type.
452 */
453 static void bnx2x_set_gro_params(struct sk_buff *skb, u16 parsing_flags,
454 u16 len_on_bd, unsigned int pkt_len)
455 {
456 /* TPA aggregation won't have either IP options or TCP options
457 * other than timestamp or IPv6 extension headers.
458 */
459 u16 hdrs_len = ETH_HLEN + sizeof(struct tcphdr);
460
461 if (GET_FLAG(parsing_flags, PARSING_FLAGS_OVER_ETHERNET_PROTOCOL) ==
462 PRS_FLAG_OVERETH_IPV6) {
463 hdrs_len += sizeof(struct ipv6hdr);
464 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV6;
465 } else {
466 hdrs_len += sizeof(struct iphdr);
467 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
468 }
469
470 /* Check if there was a TCP timestamp, if there is it's will
471 * always be 12 bytes length: nop nop kind length echo val.
472 *
473 * Otherwise FW would close the aggregation.
474 */
475 if (parsing_flags & PARSING_FLAGS_TIME_STAMP_EXIST_FLAG)
476 hdrs_len += TPA_TSTAMP_OPT_LEN;
477
478 skb_shinfo(skb)->gso_size = len_on_bd - hdrs_len;
479
480 /* tcp_gro_complete() will copy NAPI_GRO_CB(skb)->count
481 * to skb_shinfo(skb)->gso_segs
482 */
483 NAPI_GRO_CB(skb)->count = DIV_ROUND_UP(pkt_len - hdrs_len,
484 skb_shinfo(skb)->gso_size);
485 }
486
487 static int bnx2x_alloc_rx_sge(struct bnx2x *bp,
488 struct bnx2x_fastpath *fp, u16 index)
489 {
490 struct page *page = alloc_pages(GFP_ATOMIC, PAGES_PER_SGE_SHIFT);
491 struct sw_rx_page *sw_buf = &fp->rx_page_ring[index];
492 struct eth_rx_sge *sge = &fp->rx_sge_ring[index];
493 dma_addr_t mapping;
494
495 if (unlikely(page == NULL)) {
496 BNX2X_ERR("Can't alloc sge\n");
497 return -ENOMEM;
498 }
499
500 mapping = dma_map_page(&bp->pdev->dev, page, 0,
501 SGE_PAGES, DMA_FROM_DEVICE);
502 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
503 __free_pages(page, PAGES_PER_SGE_SHIFT);
504 BNX2X_ERR("Can't map sge\n");
505 return -ENOMEM;
506 }
507
508 sw_buf->page = page;
509 dma_unmap_addr_set(sw_buf, mapping, mapping);
510
511 sge->addr_hi = cpu_to_le32(U64_HI(mapping));
512 sge->addr_lo = cpu_to_le32(U64_LO(mapping));
513
514 return 0;
515 }
516
517 static int bnx2x_fill_frag_skb(struct bnx2x *bp, struct bnx2x_fastpath *fp,
518 struct bnx2x_agg_info *tpa_info,
519 u16 pages,
520 struct sk_buff *skb,
521 struct eth_end_agg_rx_cqe *cqe,
522 u16 cqe_idx)
523 {
524 struct sw_rx_page *rx_pg, old_rx_pg;
525 u32 i, frag_len, frag_size;
526 int err, j, frag_id = 0;
527 u16 len_on_bd = tpa_info->len_on_bd;
528 u16 full_page = 0, gro_size = 0;
529
530 frag_size = le16_to_cpu(cqe->pkt_len) - len_on_bd;
531
532 if (fp->mode == TPA_MODE_GRO) {
533 gro_size = tpa_info->gro_size;
534 full_page = tpa_info->full_page;
535 }
536
537 /* This is needed in order to enable forwarding support */
538 if (frag_size)
539 bnx2x_set_gro_params(skb, tpa_info->parsing_flags, len_on_bd,
540 le16_to_cpu(cqe->pkt_len));
541
542 #ifdef BNX2X_STOP_ON_ERROR
543 if (pages > min_t(u32, 8, MAX_SKB_FRAGS) * SGE_PAGES) {
544 BNX2X_ERR("SGL length is too long: %d. CQE index is %d\n",
545 pages, cqe_idx);
546 BNX2X_ERR("cqe->pkt_len = %d\n", cqe->pkt_len);
547 bnx2x_panic();
548 return -EINVAL;
549 }
550 #endif
551
552 /* Run through the SGL and compose the fragmented skb */
553 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) {
554 u16 sge_idx = RX_SGE(le16_to_cpu(cqe->sgl_or_raw_data.sgl[j]));
555
556 /* FW gives the indices of the SGE as if the ring is an array
557 (meaning that "next" element will consume 2 indices) */
558 if (fp->mode == TPA_MODE_GRO)
559 frag_len = min_t(u32, frag_size, (u32)full_page);
560 else /* LRO */
561 frag_len = min_t(u32, frag_size, (u32)SGE_PAGES);
562
563 rx_pg = &fp->rx_page_ring[sge_idx];
564 old_rx_pg = *rx_pg;
565
566 /* If we fail to allocate a substitute page, we simply stop
567 where we are and drop the whole packet */
568 err = bnx2x_alloc_rx_sge(bp, fp, sge_idx);
569 if (unlikely(err)) {
570 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
571 return err;
572 }
573
574 /* Unmap the page as we r going to pass it to the stack */
575 dma_unmap_page(&bp->pdev->dev,
576 dma_unmap_addr(&old_rx_pg, mapping),
577 SGE_PAGES, DMA_FROM_DEVICE);
578 /* Add one frag and update the appropriate fields in the skb */
579 if (fp->mode == TPA_MODE_LRO)
580 skb_fill_page_desc(skb, j, old_rx_pg.page, 0, frag_len);
581 else { /* GRO */
582 int rem;
583 int offset = 0;
584 for (rem = frag_len; rem > 0; rem -= gro_size) {
585 int len = rem > gro_size ? gro_size : rem;
586 skb_fill_page_desc(skb, frag_id++,
587 old_rx_pg.page, offset, len);
588 if (offset)
589 get_page(old_rx_pg.page);
590 offset += len;
591 }
592 }
593
594 skb->data_len += frag_len;
595 skb->truesize += SGE_PAGES;
596 skb->len += frag_len;
597
598 frag_size -= frag_len;
599 }
600
601 return 0;
602 }
603
604 static void bnx2x_frag_free(const struct bnx2x_fastpath *fp, void *data)
605 {
606 if (fp->rx_frag_size)
607 put_page(virt_to_head_page(data));
608 else
609 kfree(data);
610 }
611
612 static void *bnx2x_frag_alloc(const struct bnx2x_fastpath *fp)
613 {
614 if (fp->rx_frag_size)
615 return netdev_alloc_frag(fp->rx_frag_size);
616
617 return kmalloc(fp->rx_buf_size + NET_SKB_PAD, GFP_ATOMIC);
618 }
619
620 #ifdef CONFIG_INET
621 static void bnx2x_gro_ip_csum(struct bnx2x *bp, struct sk_buff *skb)
622 {
623 const struct iphdr *iph = ip_hdr(skb);
624 struct tcphdr *th;
625
626 skb_set_transport_header(skb, sizeof(struct iphdr));
627 th = tcp_hdr(skb);
628
629 th->check = ~tcp_v4_check(skb->len - skb_transport_offset(skb),
630 iph->saddr, iph->daddr, 0);
631 }
632
633 static void bnx2x_gro_ipv6_csum(struct bnx2x *bp, struct sk_buff *skb)
634 {
635 struct ipv6hdr *iph = ipv6_hdr(skb);
636 struct tcphdr *th;
637
638 skb_set_transport_header(skb, sizeof(struct ipv6hdr));
639 th = tcp_hdr(skb);
640
641 th->check = ~tcp_v6_check(skb->len - skb_transport_offset(skb),
642 &iph->saddr, &iph->daddr, 0);
643 }
644 #endif
645
646 static void bnx2x_gro_receive(struct bnx2x *bp, struct bnx2x_fastpath *fp,
647 struct sk_buff *skb)
648 {
649 #ifdef CONFIG_INET
650 if (skb_shinfo(skb)->gso_size) {
651 skb_set_network_header(skb, 0);
652 switch (be16_to_cpu(skb->protocol)) {
653 case ETH_P_IP:
654 bnx2x_gro_ip_csum(bp, skb);
655 break;
656 case ETH_P_IPV6:
657 bnx2x_gro_ipv6_csum(bp, skb);
658 break;
659 default:
660 BNX2X_ERR("FW GRO supports only IPv4/IPv6, not 0x%04x\n",
661 be16_to_cpu(skb->protocol));
662 }
663 tcp_gro_complete(skb);
664 }
665 #endif
666 napi_gro_receive(&fp->napi, skb);
667 }
668
669 static void bnx2x_tpa_stop(struct bnx2x *bp, struct bnx2x_fastpath *fp,
670 struct bnx2x_agg_info *tpa_info,
671 u16 pages,
672 struct eth_end_agg_rx_cqe *cqe,
673 u16 cqe_idx)
674 {
675 struct sw_rx_bd *rx_buf = &tpa_info->first_buf;
676 u8 pad = tpa_info->placement_offset;
677 u16 len = tpa_info->len_on_bd;
678 struct sk_buff *skb = NULL;
679 u8 *new_data, *data = rx_buf->data;
680 u8 old_tpa_state = tpa_info->tpa_state;
681
682 tpa_info->tpa_state = BNX2X_TPA_STOP;
683
684 /* If we there was an error during the handling of the TPA_START -
685 * drop this aggregation.
686 */
687 if (old_tpa_state == BNX2X_TPA_ERROR)
688 goto drop;
689
690 /* Try to allocate the new data */
691 new_data = bnx2x_frag_alloc(fp);
692 /* Unmap skb in the pool anyway, as we are going to change
693 pool entry status to BNX2X_TPA_STOP even if new skb allocation
694 fails. */
695 dma_unmap_single(&bp->pdev->dev, dma_unmap_addr(rx_buf, mapping),
696 fp->rx_buf_size, DMA_FROM_DEVICE);
697 if (likely(new_data))
698 skb = build_skb(data, fp->rx_frag_size);
699
700 if (likely(skb)) {
701 #ifdef BNX2X_STOP_ON_ERROR
702 if (pad + len > fp->rx_buf_size) {
703 BNX2X_ERR("skb_put is about to fail... pad %d len %d rx_buf_size %d\n",
704 pad, len, fp->rx_buf_size);
705 bnx2x_panic();
706 return;
707 }
708 #endif
709
710 skb_reserve(skb, pad + NET_SKB_PAD);
711 skb_put(skb, len);
712 skb->rxhash = tpa_info->rxhash;
713 skb->l4_rxhash = tpa_info->l4_rxhash;
714
715 skb->protocol = eth_type_trans(skb, bp->dev);
716 skb->ip_summed = CHECKSUM_UNNECESSARY;
717
718 if (!bnx2x_fill_frag_skb(bp, fp, tpa_info, pages,
719 skb, cqe, cqe_idx)) {
720 if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN)
721 __vlan_hwaccel_put_tag(skb, tpa_info->vlan_tag);
722 bnx2x_gro_receive(bp, fp, skb);
723 } else {
724 DP(NETIF_MSG_RX_STATUS,
725 "Failed to allocate new pages - dropping packet!\n");
726 dev_kfree_skb_any(skb);
727 }
728
729
730 /* put new data in bin */
731 rx_buf->data = new_data;
732
733 return;
734 }
735 bnx2x_frag_free(fp, new_data);
736 drop:
737 /* drop the packet and keep the buffer in the bin */
738 DP(NETIF_MSG_RX_STATUS,
739 "Failed to allocate or map a new skb - dropping packet!\n");
740 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed++;
741 }
742
743 static int bnx2x_alloc_rx_data(struct bnx2x *bp,
744 struct bnx2x_fastpath *fp, u16 index)
745 {
746 u8 *data;
747 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[index];
748 struct eth_rx_bd *rx_bd = &fp->rx_desc_ring[index];
749 dma_addr_t mapping;
750
751 data = bnx2x_frag_alloc(fp);
752 if (unlikely(data == NULL))
753 return -ENOMEM;
754
755 mapping = dma_map_single(&bp->pdev->dev, data + NET_SKB_PAD,
756 fp->rx_buf_size,
757 DMA_FROM_DEVICE);
758 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
759 bnx2x_frag_free(fp, data);
760 BNX2X_ERR("Can't map rx data\n");
761 return -ENOMEM;
762 }
763
764 rx_buf->data = data;
765 dma_unmap_addr_set(rx_buf, mapping, mapping);
766
767 rx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
768 rx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
769
770 return 0;
771 }
772
773 static
774 void bnx2x_csum_validate(struct sk_buff *skb, union eth_rx_cqe *cqe,
775 struct bnx2x_fastpath *fp,
776 struct bnx2x_eth_q_stats *qstats)
777 {
778 /* Do nothing if no L4 csum validation was done.
779 * We do not check whether IP csum was validated. For IPv4 we assume
780 * that if the card got as far as validating the L4 csum, it also
781 * validated the IP csum. IPv6 has no IP csum.
782 */
783 if (cqe->fast_path_cqe.status_flags &
784 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)
785 return;
786
787 /* If L4 validation was done, check if an error was found. */
788
789 if (cqe->fast_path_cqe.type_error_flags &
790 (ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG |
791 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG))
792 qstats->hw_csum_err++;
793 else
794 skb->ip_summed = CHECKSUM_UNNECESSARY;
795 }
796
797 int bnx2x_rx_int(struct bnx2x_fastpath *fp, int budget)
798 {
799 struct bnx2x *bp = fp->bp;
800 u16 bd_cons, bd_prod, bd_prod_fw, comp_ring_cons;
801 u16 hw_comp_cons, sw_comp_cons, sw_comp_prod;
802 int rx_pkt = 0;
803
804 #ifdef BNX2X_STOP_ON_ERROR
805 if (unlikely(bp->panic))
806 return 0;
807 #endif
808
809 /* CQ "next element" is of the size of the regular element,
810 that's why it's ok here */
811 hw_comp_cons = le16_to_cpu(*fp->rx_cons_sb);
812 if ((hw_comp_cons & MAX_RCQ_DESC_CNT) == MAX_RCQ_DESC_CNT)
813 hw_comp_cons++;
814
815 bd_cons = fp->rx_bd_cons;
816 bd_prod = fp->rx_bd_prod;
817 bd_prod_fw = bd_prod;
818 sw_comp_cons = fp->rx_comp_cons;
819 sw_comp_prod = fp->rx_comp_prod;
820
821 /* Memory barrier necessary as speculative reads of the rx
822 * buffer can be ahead of the index in the status block
823 */
824 rmb();
825
826 DP(NETIF_MSG_RX_STATUS,
827 "queue[%d]: hw_comp_cons %u sw_comp_cons %u\n",
828 fp->index, hw_comp_cons, sw_comp_cons);
829
830 while (sw_comp_cons != hw_comp_cons) {
831 struct sw_rx_bd *rx_buf = NULL;
832 struct sk_buff *skb;
833 union eth_rx_cqe *cqe;
834 struct eth_fast_path_rx_cqe *cqe_fp;
835 u8 cqe_fp_flags;
836 enum eth_rx_cqe_type cqe_fp_type;
837 u16 len, pad, queue;
838 u8 *data;
839 bool l4_rxhash;
840
841 #ifdef BNX2X_STOP_ON_ERROR
842 if (unlikely(bp->panic))
843 return 0;
844 #endif
845
846 comp_ring_cons = RCQ_BD(sw_comp_cons);
847 bd_prod = RX_BD(bd_prod);
848 bd_cons = RX_BD(bd_cons);
849
850 cqe = &fp->rx_comp_ring[comp_ring_cons];
851 cqe_fp = &cqe->fast_path_cqe;
852 cqe_fp_flags = cqe_fp->type_error_flags;
853 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
854
855 DP(NETIF_MSG_RX_STATUS,
856 "CQE type %x err %x status %x queue %x vlan %x len %u\n",
857 CQE_TYPE(cqe_fp_flags),
858 cqe_fp_flags, cqe_fp->status_flags,
859 le32_to_cpu(cqe_fp->rss_hash_result),
860 le16_to_cpu(cqe_fp->vlan_tag),
861 le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len));
862
863 /* is this a slowpath msg? */
864 if (unlikely(CQE_TYPE_SLOW(cqe_fp_type))) {
865 bnx2x_sp_event(fp, cqe);
866 goto next_cqe;
867 }
868
869 rx_buf = &fp->rx_buf_ring[bd_cons];
870 data = rx_buf->data;
871
872 if (!CQE_TYPE_FAST(cqe_fp_type)) {
873 struct bnx2x_agg_info *tpa_info;
874 u16 frag_size, pages;
875 #ifdef BNX2X_STOP_ON_ERROR
876 /* sanity check */
877 if (fp->disable_tpa &&
878 (CQE_TYPE_START(cqe_fp_type) ||
879 CQE_TYPE_STOP(cqe_fp_type)))
880 BNX2X_ERR("START/STOP packet while disable_tpa type %x\n",
881 CQE_TYPE(cqe_fp_type));
882 #endif
883
884 if (CQE_TYPE_START(cqe_fp_type)) {
885 u16 queue = cqe_fp->queue_index;
886 DP(NETIF_MSG_RX_STATUS,
887 "calling tpa_start on queue %d\n",
888 queue);
889
890 bnx2x_tpa_start(fp, queue,
891 bd_cons, bd_prod,
892 cqe_fp);
893
894 goto next_rx;
895
896 }
897 queue = cqe->end_agg_cqe.queue_index;
898 tpa_info = &fp->tpa_info[queue];
899 DP(NETIF_MSG_RX_STATUS,
900 "calling tpa_stop on queue %d\n",
901 queue);
902
903 frag_size = le16_to_cpu(cqe->end_agg_cqe.pkt_len) -
904 tpa_info->len_on_bd;
905
906 if (fp->mode == TPA_MODE_GRO)
907 pages = (frag_size + tpa_info->full_page - 1) /
908 tpa_info->full_page;
909 else
910 pages = SGE_PAGE_ALIGN(frag_size) >>
911 SGE_PAGE_SHIFT;
912
913 bnx2x_tpa_stop(bp, fp, tpa_info, pages,
914 &cqe->end_agg_cqe, comp_ring_cons);
915 #ifdef BNX2X_STOP_ON_ERROR
916 if (bp->panic)
917 return 0;
918 #endif
919
920 bnx2x_update_sge_prod(fp, pages, &cqe->end_agg_cqe);
921 goto next_cqe;
922 }
923 /* non TPA */
924 len = le16_to_cpu(cqe_fp->pkt_len_or_gro_seg_len);
925 pad = cqe_fp->placement_offset;
926 dma_sync_single_for_cpu(&bp->pdev->dev,
927 dma_unmap_addr(rx_buf, mapping),
928 pad + RX_COPY_THRESH,
929 DMA_FROM_DEVICE);
930 pad += NET_SKB_PAD;
931 prefetch(data + pad); /* speedup eth_type_trans() */
932 /* is this an error packet? */
933 if (unlikely(cqe_fp_flags & ETH_RX_ERROR_FALGS)) {
934 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
935 "ERROR flags %x rx packet %u\n",
936 cqe_fp_flags, sw_comp_cons);
937 bnx2x_fp_qstats(bp, fp)->rx_err_discard_pkt++;
938 goto reuse_rx;
939 }
940
941 /* Since we don't have a jumbo ring
942 * copy small packets if mtu > 1500
943 */
944 if ((bp->dev->mtu > ETH_MAX_PACKET_SIZE) &&
945 (len <= RX_COPY_THRESH)) {
946 skb = netdev_alloc_skb_ip_align(bp->dev, len);
947 if (skb == NULL) {
948 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
949 "ERROR packet dropped because of alloc failure\n");
950 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
951 goto reuse_rx;
952 }
953 memcpy(skb->data, data + pad, len);
954 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
955 } else {
956 if (likely(bnx2x_alloc_rx_data(bp, fp, bd_prod) == 0)) {
957 dma_unmap_single(&bp->pdev->dev,
958 dma_unmap_addr(rx_buf, mapping),
959 fp->rx_buf_size,
960 DMA_FROM_DEVICE);
961 skb = build_skb(data, fp->rx_frag_size);
962 if (unlikely(!skb)) {
963 bnx2x_frag_free(fp, data);
964 bnx2x_fp_qstats(bp, fp)->
965 rx_skb_alloc_failed++;
966 goto next_rx;
967 }
968 skb_reserve(skb, pad);
969 } else {
970 DP(NETIF_MSG_RX_ERR | NETIF_MSG_RX_STATUS,
971 "ERROR packet dropped because of alloc failure\n");
972 bnx2x_fp_qstats(bp, fp)->rx_skb_alloc_failed++;
973 reuse_rx:
974 bnx2x_reuse_rx_data(fp, bd_cons, bd_prod);
975 goto next_rx;
976 }
977 }
978
979 skb_put(skb, len);
980 skb->protocol = eth_type_trans(skb, bp->dev);
981
982 /* Set Toeplitz hash for a none-LRO skb */
983 skb->rxhash = bnx2x_get_rxhash(bp, cqe_fp, &l4_rxhash);
984 skb->l4_rxhash = l4_rxhash;
985
986 skb_checksum_none_assert(skb);
987
988 if (bp->dev->features & NETIF_F_RXCSUM)
989 bnx2x_csum_validate(skb, cqe, fp,
990 bnx2x_fp_qstats(bp, fp));
991
992 skb_record_rx_queue(skb, fp->rx_queue);
993
994 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
995 PARSING_FLAGS_VLAN)
996 __vlan_hwaccel_put_tag(skb,
997 le16_to_cpu(cqe_fp->vlan_tag));
998 napi_gro_receive(&fp->napi, skb);
999
1000
1001 next_rx:
1002 rx_buf->data = NULL;
1003
1004 bd_cons = NEXT_RX_IDX(bd_cons);
1005 bd_prod = NEXT_RX_IDX(bd_prod);
1006 bd_prod_fw = NEXT_RX_IDX(bd_prod_fw);
1007 rx_pkt++;
1008 next_cqe:
1009 sw_comp_prod = NEXT_RCQ_IDX(sw_comp_prod);
1010 sw_comp_cons = NEXT_RCQ_IDX(sw_comp_cons);
1011
1012 if (rx_pkt == budget)
1013 break;
1014 } /* while */
1015
1016 fp->rx_bd_cons = bd_cons;
1017 fp->rx_bd_prod = bd_prod_fw;
1018 fp->rx_comp_cons = sw_comp_cons;
1019 fp->rx_comp_prod = sw_comp_prod;
1020
1021 /* Update producers */
1022 bnx2x_update_rx_prod(bp, fp, bd_prod_fw, sw_comp_prod,
1023 fp->rx_sge_prod);
1024
1025 fp->rx_pkt += rx_pkt;
1026 fp->rx_calls++;
1027
1028 return rx_pkt;
1029 }
1030
1031 static irqreturn_t bnx2x_msix_fp_int(int irq, void *fp_cookie)
1032 {
1033 struct bnx2x_fastpath *fp = fp_cookie;
1034 struct bnx2x *bp = fp->bp;
1035 u8 cos;
1036
1037 DP(NETIF_MSG_INTR,
1038 "got an MSI-X interrupt on IDX:SB [fp %d fw_sd %d igusb %d]\n",
1039 fp->index, fp->fw_sb_id, fp->igu_sb_id);
1040 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0);
1041
1042 #ifdef BNX2X_STOP_ON_ERROR
1043 if (unlikely(bp->panic))
1044 return IRQ_HANDLED;
1045 #endif
1046
1047 /* Handle Rx and Tx according to MSI-X vector */
1048 prefetch(fp->rx_cons_sb);
1049
1050 for_each_cos_in_tx_queue(fp, cos)
1051 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1052
1053 prefetch(&fp->sb_running_index[SM_RX_ID]);
1054 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1055
1056 return IRQ_HANDLED;
1057 }
1058
1059 /* HW Lock for shared dual port PHYs */
1060 void bnx2x_acquire_phy_lock(struct bnx2x *bp)
1061 {
1062 mutex_lock(&bp->port.phy_mutex);
1063
1064 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1065 }
1066
1067 void bnx2x_release_phy_lock(struct bnx2x *bp)
1068 {
1069 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_MDIO);
1070
1071 mutex_unlock(&bp->port.phy_mutex);
1072 }
1073
1074 /* calculates MF speed according to current linespeed and MF configuration */
1075 u16 bnx2x_get_mf_speed(struct bnx2x *bp)
1076 {
1077 u16 line_speed = bp->link_vars.line_speed;
1078 if (IS_MF(bp)) {
1079 u16 maxCfg = bnx2x_extract_max_cfg(bp,
1080 bp->mf_config[BP_VN(bp)]);
1081
1082 /* Calculate the current MAX line speed limit for the MF
1083 * devices
1084 */
1085 if (IS_MF_SI(bp))
1086 line_speed = (line_speed * maxCfg) / 100;
1087 else { /* SD mode */
1088 u16 vn_max_rate = maxCfg * 100;
1089
1090 if (vn_max_rate < line_speed)
1091 line_speed = vn_max_rate;
1092 }
1093 }
1094
1095 return line_speed;
1096 }
1097
1098 /**
1099 * bnx2x_fill_report_data - fill link report data to report
1100 *
1101 * @bp: driver handle
1102 * @data: link state to update
1103 *
1104 * It uses a none-atomic bit operations because is called under the mutex.
1105 */
1106 static void bnx2x_fill_report_data(struct bnx2x *bp,
1107 struct bnx2x_link_report_data *data)
1108 {
1109 u16 line_speed = bnx2x_get_mf_speed(bp);
1110
1111 memset(data, 0, sizeof(*data));
1112
1113 /* Fill the report data: efective line speed */
1114 data->line_speed = line_speed;
1115
1116 /* Link is down */
1117 if (!bp->link_vars.link_up || (bp->flags & MF_FUNC_DIS))
1118 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1119 &data->link_report_flags);
1120
1121 /* Full DUPLEX */
1122 if (bp->link_vars.duplex == DUPLEX_FULL)
1123 __set_bit(BNX2X_LINK_REPORT_FD, &data->link_report_flags);
1124
1125 /* Rx Flow Control is ON */
1126 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_RX)
1127 __set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);
1128
1129 /* Tx Flow Control is ON */
1130 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
1131 __set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);
1132 }
1133
1134 /**
1135 * bnx2x_link_report - report link status to OS.
1136 *
1137 * @bp: driver handle
1138 *
1139 * Calls the __bnx2x_link_report() under the same locking scheme
1140 * as a link/PHY state managing code to ensure a consistent link
1141 * reporting.
1142 */
1143
1144 void bnx2x_link_report(struct bnx2x *bp)
1145 {
1146 bnx2x_acquire_phy_lock(bp);
1147 __bnx2x_link_report(bp);
1148 bnx2x_release_phy_lock(bp);
1149 }
1150
1151 /**
1152 * __bnx2x_link_report - report link status to OS.
1153 *
1154 * @bp: driver handle
1155 *
1156 * None atomic inmlementation.
1157 * Should be called under the phy_lock.
1158 */
1159 void __bnx2x_link_report(struct bnx2x *bp)
1160 {
1161 struct bnx2x_link_report_data cur_data;
1162
1163 /* reread mf_cfg */
1164 if (IS_PF(bp) && !CHIP_IS_E1(bp))
1165 bnx2x_read_mf_cfg(bp);
1166
1167 /* Read the current link report info */
1168 bnx2x_fill_report_data(bp, &cur_data);
1169
1170 /* Don't report link down or exactly the same link status twice */
1171 if (!memcmp(&cur_data, &bp->last_reported_link, sizeof(cur_data)) ||
1172 (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1173 &bp->last_reported_link.link_report_flags) &&
1174 test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1175 &cur_data.link_report_flags)))
1176 return;
1177
1178 bp->link_cnt++;
1179
1180 /* We are going to report a new link parameters now -
1181 * remember the current data for the next time.
1182 */
1183 memcpy(&bp->last_reported_link, &cur_data, sizeof(cur_data));
1184
1185 if (test_bit(BNX2X_LINK_REPORT_LINK_DOWN,
1186 &cur_data.link_report_flags)) {
1187 netif_carrier_off(bp->dev);
1188 netdev_err(bp->dev, "NIC Link is Down\n");
1189 return;
1190 } else {
1191 const char *duplex;
1192 const char *flow;
1193
1194 netif_carrier_on(bp->dev);
1195
1196 if (test_and_clear_bit(BNX2X_LINK_REPORT_FD,
1197 &cur_data.link_report_flags))
1198 duplex = "full";
1199 else
1200 duplex = "half";
1201
1202 /* Handle the FC at the end so that only these flags would be
1203 * possibly set. This way we may easily check if there is no FC
1204 * enabled.
1205 */
1206 if (cur_data.link_report_flags) {
1207 if (test_bit(BNX2X_LINK_REPORT_RX_FC_ON,
1208 &cur_data.link_report_flags)) {
1209 if (test_bit(BNX2X_LINK_REPORT_TX_FC_ON,
1210 &cur_data.link_report_flags))
1211 flow = "ON - receive & transmit";
1212 else
1213 flow = "ON - receive";
1214 } else {
1215 flow = "ON - transmit";
1216 }
1217 } else {
1218 flow = "none";
1219 }
1220 netdev_info(bp->dev, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
1221 cur_data.line_speed, duplex, flow);
1222 }
1223 }
1224
1225 static void bnx2x_set_next_page_sgl(struct bnx2x_fastpath *fp)
1226 {
1227 int i;
1228
1229 for (i = 1; i <= NUM_RX_SGE_PAGES; i++) {
1230 struct eth_rx_sge *sge;
1231
1232 sge = &fp->rx_sge_ring[RX_SGE_CNT * i - 2];
1233 sge->addr_hi =
1234 cpu_to_le32(U64_HI(fp->rx_sge_mapping +
1235 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1236
1237 sge->addr_lo =
1238 cpu_to_le32(U64_LO(fp->rx_sge_mapping +
1239 BCM_PAGE_SIZE*(i % NUM_RX_SGE_PAGES)));
1240 }
1241 }
1242
1243 static void bnx2x_free_tpa_pool(struct bnx2x *bp,
1244 struct bnx2x_fastpath *fp, int last)
1245 {
1246 int i;
1247
1248 for (i = 0; i < last; i++) {
1249 struct bnx2x_agg_info *tpa_info = &fp->tpa_info[i];
1250 struct sw_rx_bd *first_buf = &tpa_info->first_buf;
1251 u8 *data = first_buf->data;
1252
1253 if (data == NULL) {
1254 DP(NETIF_MSG_IFDOWN, "tpa bin %d empty on free\n", i);
1255 continue;
1256 }
1257 if (tpa_info->tpa_state == BNX2X_TPA_START)
1258 dma_unmap_single(&bp->pdev->dev,
1259 dma_unmap_addr(first_buf, mapping),
1260 fp->rx_buf_size, DMA_FROM_DEVICE);
1261 bnx2x_frag_free(fp, data);
1262 first_buf->data = NULL;
1263 }
1264 }
1265
1266 void bnx2x_init_rx_rings_cnic(struct bnx2x *bp)
1267 {
1268 int j;
1269
1270 for_each_rx_queue_cnic(bp, j) {
1271 struct bnx2x_fastpath *fp = &bp->fp[j];
1272
1273 fp->rx_bd_cons = 0;
1274
1275 /* Activate BD ring */
1276 /* Warning!
1277 * this will generate an interrupt (to the TSTORM)
1278 * must only be done after chip is initialized
1279 */
1280 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1281 fp->rx_sge_prod);
1282 }
1283 }
1284
1285 void bnx2x_init_rx_rings(struct bnx2x *bp)
1286 {
1287 int func = BP_FUNC(bp);
1288 u16 ring_prod;
1289 int i, j;
1290
1291 /* Allocate TPA resources */
1292 for_each_eth_queue(bp, j) {
1293 struct bnx2x_fastpath *fp = &bp->fp[j];
1294
1295 DP(NETIF_MSG_IFUP,
1296 "mtu %d rx_buf_size %d\n", bp->dev->mtu, fp->rx_buf_size);
1297
1298 if (!fp->disable_tpa) {
1299 /* Fill the per-aggregtion pool */
1300 for (i = 0; i < MAX_AGG_QS(bp); i++) {
1301 struct bnx2x_agg_info *tpa_info =
1302 &fp->tpa_info[i];
1303 struct sw_rx_bd *first_buf =
1304 &tpa_info->first_buf;
1305
1306 first_buf->data = bnx2x_frag_alloc(fp);
1307 if (!first_buf->data) {
1308 BNX2X_ERR("Failed to allocate TPA skb pool for queue[%d] - disabling TPA on this queue!\n",
1309 j);
1310 bnx2x_free_tpa_pool(bp, fp, i);
1311 fp->disable_tpa = 1;
1312 break;
1313 }
1314 dma_unmap_addr_set(first_buf, mapping, 0);
1315 tpa_info->tpa_state = BNX2X_TPA_STOP;
1316 }
1317
1318 /* "next page" elements initialization */
1319 bnx2x_set_next_page_sgl(fp);
1320
1321 /* set SGEs bit mask */
1322 bnx2x_init_sge_ring_bit_mask(fp);
1323
1324 /* Allocate SGEs and initialize the ring elements */
1325 for (i = 0, ring_prod = 0;
1326 i < MAX_RX_SGE_CNT*NUM_RX_SGE_PAGES; i++) {
1327
1328 if (bnx2x_alloc_rx_sge(bp, fp, ring_prod) < 0) {
1329 BNX2X_ERR("was only able to allocate %d rx sges\n",
1330 i);
1331 BNX2X_ERR("disabling TPA for queue[%d]\n",
1332 j);
1333 /* Cleanup already allocated elements */
1334 bnx2x_free_rx_sge_range(bp, fp,
1335 ring_prod);
1336 bnx2x_free_tpa_pool(bp, fp,
1337 MAX_AGG_QS(bp));
1338 fp->disable_tpa = 1;
1339 ring_prod = 0;
1340 break;
1341 }
1342 ring_prod = NEXT_SGE_IDX(ring_prod);
1343 }
1344
1345 fp->rx_sge_prod = ring_prod;
1346 }
1347 }
1348
1349 for_each_eth_queue(bp, j) {
1350 struct bnx2x_fastpath *fp = &bp->fp[j];
1351
1352 fp->rx_bd_cons = 0;
1353
1354 /* Activate BD ring */
1355 /* Warning!
1356 * this will generate an interrupt (to the TSTORM)
1357 * must only be done after chip is initialized
1358 */
1359 bnx2x_update_rx_prod(bp, fp, fp->rx_bd_prod, fp->rx_comp_prod,
1360 fp->rx_sge_prod);
1361
1362 if (j != 0)
1363 continue;
1364
1365 if (CHIP_IS_E1(bp)) {
1366 REG_WR(bp, BAR_USTRORM_INTMEM +
1367 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func),
1368 U64_LO(fp->rx_comp_mapping));
1369 REG_WR(bp, BAR_USTRORM_INTMEM +
1370 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(func) + 4,
1371 U64_HI(fp->rx_comp_mapping));
1372 }
1373 }
1374 }
1375
1376 static void bnx2x_free_tx_skbs_queue(struct bnx2x_fastpath *fp)
1377 {
1378 u8 cos;
1379 struct bnx2x *bp = fp->bp;
1380
1381 for_each_cos_in_tx_queue(fp, cos) {
1382 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1383 unsigned pkts_compl = 0, bytes_compl = 0;
1384
1385 u16 sw_prod = txdata->tx_pkt_prod;
1386 u16 sw_cons = txdata->tx_pkt_cons;
1387
1388 while (sw_cons != sw_prod) {
1389 bnx2x_free_tx_pkt(bp, txdata, TX_BD(sw_cons),
1390 &pkts_compl, &bytes_compl);
1391 sw_cons++;
1392 }
1393
1394 netdev_tx_reset_queue(
1395 netdev_get_tx_queue(bp->dev,
1396 txdata->txq_index));
1397 }
1398 }
1399
1400 static void bnx2x_free_tx_skbs_cnic(struct bnx2x *bp)
1401 {
1402 int i;
1403
1404 for_each_tx_queue_cnic(bp, i) {
1405 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1406 }
1407 }
1408
1409 static void bnx2x_free_tx_skbs(struct bnx2x *bp)
1410 {
1411 int i;
1412
1413 for_each_eth_queue(bp, i) {
1414 bnx2x_free_tx_skbs_queue(&bp->fp[i]);
1415 }
1416 }
1417
1418 static void bnx2x_free_rx_bds(struct bnx2x_fastpath *fp)
1419 {
1420 struct bnx2x *bp = fp->bp;
1421 int i;
1422
1423 /* ring wasn't allocated */
1424 if (fp->rx_buf_ring == NULL)
1425 return;
1426
1427 for (i = 0; i < NUM_RX_BD; i++) {
1428 struct sw_rx_bd *rx_buf = &fp->rx_buf_ring[i];
1429 u8 *data = rx_buf->data;
1430
1431 if (data == NULL)
1432 continue;
1433 dma_unmap_single(&bp->pdev->dev,
1434 dma_unmap_addr(rx_buf, mapping),
1435 fp->rx_buf_size, DMA_FROM_DEVICE);
1436
1437 rx_buf->data = NULL;
1438 bnx2x_frag_free(fp, data);
1439 }
1440 }
1441
1442 static void bnx2x_free_rx_skbs_cnic(struct bnx2x *bp)
1443 {
1444 int j;
1445
1446 for_each_rx_queue_cnic(bp, j) {
1447 bnx2x_free_rx_bds(&bp->fp[j]);
1448 }
1449 }
1450
1451 static void bnx2x_free_rx_skbs(struct bnx2x *bp)
1452 {
1453 int j;
1454
1455 for_each_eth_queue(bp, j) {
1456 struct bnx2x_fastpath *fp = &bp->fp[j];
1457
1458 bnx2x_free_rx_bds(fp);
1459
1460 if (!fp->disable_tpa)
1461 bnx2x_free_tpa_pool(bp, fp, MAX_AGG_QS(bp));
1462 }
1463 }
1464
1465 void bnx2x_free_skbs_cnic(struct bnx2x *bp)
1466 {
1467 bnx2x_free_tx_skbs_cnic(bp);
1468 bnx2x_free_rx_skbs_cnic(bp);
1469 }
1470
1471 void bnx2x_free_skbs(struct bnx2x *bp)
1472 {
1473 bnx2x_free_tx_skbs(bp);
1474 bnx2x_free_rx_skbs(bp);
1475 }
1476
1477 void bnx2x_update_max_mf_config(struct bnx2x *bp, u32 value)
1478 {
1479 /* load old values */
1480 u32 mf_cfg = bp->mf_config[BP_VN(bp)];
1481
1482 if (value != bnx2x_extract_max_cfg(bp, mf_cfg)) {
1483 /* leave all but MAX value */
1484 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK;
1485
1486 /* set new MAX value */
1487 mf_cfg |= (value << FUNC_MF_CFG_MAX_BW_SHIFT)
1488 & FUNC_MF_CFG_MAX_BW_MASK;
1489
1490 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW, mf_cfg);
1491 }
1492 }
1493
1494 /**
1495 * bnx2x_free_msix_irqs - free previously requested MSI-X IRQ vectors
1496 *
1497 * @bp: driver handle
1498 * @nvecs: number of vectors to be released
1499 */
1500 static void bnx2x_free_msix_irqs(struct bnx2x *bp, int nvecs)
1501 {
1502 int i, offset = 0;
1503
1504 if (nvecs == offset)
1505 return;
1506
1507 /* VFs don't have a default SB */
1508 if (IS_PF(bp)) {
1509 free_irq(bp->msix_table[offset].vector, bp->dev);
1510 DP(NETIF_MSG_IFDOWN, "released sp irq (%d)\n",
1511 bp->msix_table[offset].vector);
1512 offset++;
1513 }
1514
1515 if (CNIC_SUPPORT(bp)) {
1516 if (nvecs == offset)
1517 return;
1518 offset++;
1519 }
1520
1521 for_each_eth_queue(bp, i) {
1522 if (nvecs == offset)
1523 return;
1524 DP(NETIF_MSG_IFDOWN, "about to release fp #%d->%d irq\n",
1525 i, bp->msix_table[offset].vector);
1526
1527 free_irq(bp->msix_table[offset++].vector, &bp->fp[i]);
1528 }
1529 }
1530
1531 void bnx2x_free_irq(struct bnx2x *bp)
1532 {
1533 if (bp->flags & USING_MSIX_FLAG &&
1534 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1535 int nvecs = BNX2X_NUM_ETH_QUEUES(bp) + CNIC_SUPPORT(bp);
1536
1537 /* vfs don't have a default status block */
1538 if (IS_PF(bp))
1539 nvecs++;
1540
1541 bnx2x_free_msix_irqs(bp, nvecs);
1542 } else {
1543 free_irq(bp->dev->irq, bp->dev);
1544 }
1545 }
1546
1547 int bnx2x_enable_msix(struct bnx2x *bp)
1548 {
1549 int msix_vec = 0, i, rc;
1550
1551 /* VFs don't have a default status block */
1552 if (IS_PF(bp)) {
1553 bp->msix_table[msix_vec].entry = msix_vec;
1554 BNX2X_DEV_INFO("msix_table[0].entry = %d (slowpath)\n",
1555 bp->msix_table[0].entry);
1556 msix_vec++;
1557 }
1558
1559 /* Cnic requires an msix vector for itself */
1560 if (CNIC_SUPPORT(bp)) {
1561 bp->msix_table[msix_vec].entry = msix_vec;
1562 BNX2X_DEV_INFO("msix_table[%d].entry = %d (CNIC)\n",
1563 msix_vec, bp->msix_table[msix_vec].entry);
1564 msix_vec++;
1565 }
1566
1567 /* We need separate vectors for ETH queues only (not FCoE) */
1568 for_each_eth_queue(bp, i) {
1569 bp->msix_table[msix_vec].entry = msix_vec;
1570 BNX2X_DEV_INFO("msix_table[%d].entry = %d (fastpath #%u)\n",
1571 msix_vec, msix_vec, i);
1572 msix_vec++;
1573 }
1574
1575 DP(BNX2X_MSG_SP, "about to request enable msix with %d vectors\n",
1576 msix_vec);
1577
1578 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], msix_vec);
1579
1580 /*
1581 * reconfigure number of tx/rx queues according to available
1582 * MSI-X vectors
1583 */
1584 if (rc >= BNX2X_MIN_MSIX_VEC_CNT(bp)) {
1585 /* how less vectors we will have? */
1586 int diff = msix_vec - rc;
1587
1588 BNX2X_DEV_INFO("Trying to use less MSI-X vectors: %d\n", rc);
1589
1590 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], rc);
1591
1592 if (rc) {
1593 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1594 goto no_msix;
1595 }
1596 /*
1597 * decrease number of queues by number of unallocated entries
1598 */
1599 bp->num_ethernet_queues -= diff;
1600 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1601
1602 BNX2X_DEV_INFO("New queue configuration set: %d\n",
1603 bp->num_queues);
1604 } else if (rc > 0) {
1605 /* Get by with single vector */
1606 rc = pci_enable_msix(bp->pdev, &bp->msix_table[0], 1);
1607 if (rc) {
1608 BNX2X_DEV_INFO("Single MSI-X is not attainable rc %d\n",
1609 rc);
1610 goto no_msix;
1611 }
1612
1613 BNX2X_DEV_INFO("Using single MSI-X vector\n");
1614 bp->flags |= USING_SINGLE_MSIX_FLAG;
1615
1616 BNX2X_DEV_INFO("set number of queues to 1\n");
1617 bp->num_ethernet_queues = 1;
1618 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1619 } else if (rc < 0) {
1620 BNX2X_DEV_INFO("MSI-X is not attainable rc %d\n", rc);
1621 goto no_msix;
1622 }
1623
1624 bp->flags |= USING_MSIX_FLAG;
1625
1626 return 0;
1627
1628 no_msix:
1629 /* fall to INTx if not enough memory */
1630 if (rc == -ENOMEM)
1631 bp->flags |= DISABLE_MSI_FLAG;
1632
1633 return rc;
1634 }
1635
1636 static int bnx2x_req_msix_irqs(struct bnx2x *bp)
1637 {
1638 int i, rc, offset = 0;
1639
1640 /* no default status block for vf */
1641 if (IS_PF(bp)) {
1642 rc = request_irq(bp->msix_table[offset++].vector,
1643 bnx2x_msix_sp_int, 0,
1644 bp->dev->name, bp->dev);
1645 if (rc) {
1646 BNX2X_ERR("request sp irq failed\n");
1647 return -EBUSY;
1648 }
1649 }
1650
1651 if (CNIC_SUPPORT(bp))
1652 offset++;
1653
1654 for_each_eth_queue(bp, i) {
1655 struct bnx2x_fastpath *fp = &bp->fp[i];
1656 snprintf(fp->name, sizeof(fp->name), "%s-fp-%d",
1657 bp->dev->name, i);
1658
1659 rc = request_irq(bp->msix_table[offset].vector,
1660 bnx2x_msix_fp_int, 0, fp->name, fp);
1661 if (rc) {
1662 BNX2X_ERR("request fp #%d irq (%d) failed rc %d\n", i,
1663 bp->msix_table[offset].vector, rc);
1664 bnx2x_free_msix_irqs(bp, offset);
1665 return -EBUSY;
1666 }
1667
1668 offset++;
1669 }
1670
1671 i = BNX2X_NUM_ETH_QUEUES(bp);
1672 if (IS_PF(bp)) {
1673 offset = 1 + CNIC_SUPPORT(bp);
1674 netdev_info(bp->dev,
1675 "using MSI-X IRQs: sp %d fp[%d] %d ... fp[%d] %d\n",
1676 bp->msix_table[0].vector,
1677 0, bp->msix_table[offset].vector,
1678 i - 1, bp->msix_table[offset + i - 1].vector);
1679 } else {
1680 offset = CNIC_SUPPORT(bp);
1681 netdev_info(bp->dev,
1682 "using MSI-X IRQs: fp[%d] %d ... fp[%d] %d\n",
1683 0, bp->msix_table[offset].vector,
1684 i - 1, bp->msix_table[offset + i - 1].vector);
1685 }
1686 return 0;
1687 }
1688
1689 int bnx2x_enable_msi(struct bnx2x *bp)
1690 {
1691 int rc;
1692
1693 rc = pci_enable_msi(bp->pdev);
1694 if (rc) {
1695 BNX2X_DEV_INFO("MSI is not attainable\n");
1696 return -1;
1697 }
1698 bp->flags |= USING_MSI_FLAG;
1699
1700 return 0;
1701 }
1702
1703 static int bnx2x_req_irq(struct bnx2x *bp)
1704 {
1705 unsigned long flags;
1706 unsigned int irq;
1707
1708 if (bp->flags & (USING_MSI_FLAG | USING_MSIX_FLAG))
1709 flags = 0;
1710 else
1711 flags = IRQF_SHARED;
1712
1713 if (bp->flags & USING_MSIX_FLAG)
1714 irq = bp->msix_table[0].vector;
1715 else
1716 irq = bp->pdev->irq;
1717
1718 return request_irq(irq, bnx2x_interrupt, flags, bp->dev->name, bp->dev);
1719 }
1720
1721 static int bnx2x_setup_irqs(struct bnx2x *bp)
1722 {
1723 int rc = 0;
1724 if (bp->flags & USING_MSIX_FLAG &&
1725 !(bp->flags & USING_SINGLE_MSIX_FLAG)) {
1726 rc = bnx2x_req_msix_irqs(bp);
1727 if (rc)
1728 return rc;
1729 } else {
1730 rc = bnx2x_req_irq(bp);
1731 if (rc) {
1732 BNX2X_ERR("IRQ request failed rc %d, aborting\n", rc);
1733 return rc;
1734 }
1735 if (bp->flags & USING_MSI_FLAG) {
1736 bp->dev->irq = bp->pdev->irq;
1737 netdev_info(bp->dev, "using MSI IRQ %d\n",
1738 bp->dev->irq);
1739 }
1740 if (bp->flags & USING_MSIX_FLAG) {
1741 bp->dev->irq = bp->msix_table[0].vector;
1742 netdev_info(bp->dev, "using MSIX IRQ %d\n",
1743 bp->dev->irq);
1744 }
1745 }
1746
1747 return 0;
1748 }
1749
1750 static void bnx2x_napi_enable_cnic(struct bnx2x *bp)
1751 {
1752 int i;
1753
1754 for_each_rx_queue_cnic(bp, i)
1755 napi_enable(&bnx2x_fp(bp, i, napi));
1756 }
1757
1758 static void bnx2x_napi_enable(struct bnx2x *bp)
1759 {
1760 int i;
1761
1762 for_each_eth_queue(bp, i)
1763 napi_enable(&bnx2x_fp(bp, i, napi));
1764 }
1765
1766 static void bnx2x_napi_disable_cnic(struct bnx2x *bp)
1767 {
1768 int i;
1769
1770 for_each_rx_queue_cnic(bp, i)
1771 napi_disable(&bnx2x_fp(bp, i, napi));
1772 }
1773
1774 static void bnx2x_napi_disable(struct bnx2x *bp)
1775 {
1776 int i;
1777
1778 for_each_eth_queue(bp, i)
1779 napi_disable(&bnx2x_fp(bp, i, napi));
1780 }
1781
1782 void bnx2x_netif_start(struct bnx2x *bp)
1783 {
1784 if (netif_running(bp->dev)) {
1785 bnx2x_napi_enable(bp);
1786 if (CNIC_LOADED(bp))
1787 bnx2x_napi_enable_cnic(bp);
1788 bnx2x_int_enable(bp);
1789 if (bp->state == BNX2X_STATE_OPEN)
1790 netif_tx_wake_all_queues(bp->dev);
1791 }
1792 }
1793
1794 void bnx2x_netif_stop(struct bnx2x *bp, int disable_hw)
1795 {
1796 bnx2x_int_disable_sync(bp, disable_hw);
1797 bnx2x_napi_disable(bp);
1798 if (CNIC_LOADED(bp))
1799 bnx2x_napi_disable_cnic(bp);
1800 }
1801
1802 u16 bnx2x_select_queue(struct net_device *dev, struct sk_buff *skb)
1803 {
1804 struct bnx2x *bp = netdev_priv(dev);
1805
1806 if (CNIC_LOADED(bp) && !NO_FCOE(bp)) {
1807 struct ethhdr *hdr = (struct ethhdr *)skb->data;
1808 u16 ether_type = ntohs(hdr->h_proto);
1809
1810 /* Skip VLAN tag if present */
1811 if (ether_type == ETH_P_8021Q) {
1812 struct vlan_ethhdr *vhdr =
1813 (struct vlan_ethhdr *)skb->data;
1814
1815 ether_type = ntohs(vhdr->h_vlan_encapsulated_proto);
1816 }
1817
1818 /* If ethertype is FCoE or FIP - use FCoE ring */
1819 if ((ether_type == ETH_P_FCOE) || (ether_type == ETH_P_FIP))
1820 return bnx2x_fcoe_tx(bp, txq_index);
1821 }
1822
1823 /* select a non-FCoE queue */
1824 return __skb_tx_hash(dev, skb, BNX2X_NUM_ETH_QUEUES(bp));
1825 }
1826
1827 void bnx2x_set_num_queues(struct bnx2x *bp)
1828 {
1829 /* RSS queues */
1830 bp->num_ethernet_queues = bnx2x_calc_num_queues(bp);
1831
1832 /* override in STORAGE SD modes */
1833 if (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))
1834 bp->num_ethernet_queues = 1;
1835
1836 /* Add special queues */
1837 bp->num_cnic_queues = CNIC_SUPPORT(bp); /* For FCOE */
1838 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
1839
1840 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
1841 }
1842
1843 /**
1844 * bnx2x_set_real_num_queues - configure netdev->real_num_[tx,rx]_queues
1845 *
1846 * @bp: Driver handle
1847 *
1848 * We currently support for at most 16 Tx queues for each CoS thus we will
1849 * allocate a multiple of 16 for ETH L2 rings according to the value of the
1850 * bp->max_cos.
1851 *
1852 * If there is an FCoE L2 queue the appropriate Tx queue will have the next
1853 * index after all ETH L2 indices.
1854 *
1855 * If the actual number of Tx queues (for each CoS) is less than 16 then there
1856 * will be the holes at the end of each group of 16 ETh L2 indices (0..15,
1857 * 16..31,...) with indicies that are not coupled with any real Tx queue.
1858 *
1859 * The proper configuration of skb->queue_mapping is handled by
1860 * bnx2x_select_queue() and __skb_tx_hash().
1861 *
1862 * bnx2x_setup_tc() takes care of the proper TC mappings so that __skb_tx_hash()
1863 * will return a proper Tx index if TC is enabled (netdev->num_tc > 0).
1864 */
1865 static int bnx2x_set_real_num_queues(struct bnx2x *bp, int include_cnic)
1866 {
1867 int rc, tx, rx;
1868
1869 tx = BNX2X_NUM_ETH_QUEUES(bp) * bp->max_cos;
1870 rx = BNX2X_NUM_ETH_QUEUES(bp);
1871
1872 /* account for fcoe queue */
1873 if (include_cnic && !NO_FCOE(bp)) {
1874 rx++;
1875 tx++;
1876 }
1877
1878 rc = netif_set_real_num_tx_queues(bp->dev, tx);
1879 if (rc) {
1880 BNX2X_ERR("Failed to set real number of Tx queues: %d\n", rc);
1881 return rc;
1882 }
1883 rc = netif_set_real_num_rx_queues(bp->dev, rx);
1884 if (rc) {
1885 BNX2X_ERR("Failed to set real number of Rx queues: %d\n", rc);
1886 return rc;
1887 }
1888
1889 DP(NETIF_MSG_IFUP, "Setting real num queues to (tx, rx) (%d, %d)\n",
1890 tx, rx);
1891
1892 return rc;
1893 }
1894
1895 static void bnx2x_set_rx_buf_size(struct bnx2x *bp)
1896 {
1897 int i;
1898
1899 for_each_queue(bp, i) {
1900 struct bnx2x_fastpath *fp = &bp->fp[i];
1901 u32 mtu;
1902
1903 /* Always use a mini-jumbo MTU for the FCoE L2 ring */
1904 if (IS_FCOE_IDX(i))
1905 /*
1906 * Although there are no IP frames expected to arrive to
1907 * this ring we still want to add an
1908 * IP_HEADER_ALIGNMENT_PADDING to prevent a buffer
1909 * overrun attack.
1910 */
1911 mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
1912 else
1913 mtu = bp->dev->mtu;
1914 fp->rx_buf_size = BNX2X_FW_RX_ALIGN_START +
1915 IP_HEADER_ALIGNMENT_PADDING +
1916 ETH_OVREHEAD +
1917 mtu +
1918 BNX2X_FW_RX_ALIGN_END;
1919 /* Note : rx_buf_size doesnt take into account NET_SKB_PAD */
1920 if (fp->rx_buf_size + NET_SKB_PAD <= PAGE_SIZE)
1921 fp->rx_frag_size = fp->rx_buf_size + NET_SKB_PAD;
1922 else
1923 fp->rx_frag_size = 0;
1924 }
1925 }
1926
1927 static int bnx2x_init_rss_pf(struct bnx2x *bp)
1928 {
1929 int i;
1930 u8 num_eth_queues = BNX2X_NUM_ETH_QUEUES(bp);
1931
1932 /* Prepare the initial contents fo the indirection table if RSS is
1933 * enabled
1934 */
1935 for (i = 0; i < sizeof(bp->rss_conf_obj.ind_table); i++)
1936 bp->rss_conf_obj.ind_table[i] =
1937 bp->fp->cl_id +
1938 ethtool_rxfh_indir_default(i, num_eth_queues);
1939
1940 /*
1941 * For 57710 and 57711 SEARCHER configuration (rss_keys) is
1942 * per-port, so if explicit configuration is needed , do it only
1943 * for a PMF.
1944 *
1945 * For 57712 and newer on the other hand it's a per-function
1946 * configuration.
1947 */
1948 return bnx2x_config_rss_eth(bp, bp->port.pmf || !CHIP_IS_E1x(bp));
1949 }
1950
1951 int bnx2x_config_rss_pf(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
1952 bool config_hash)
1953 {
1954 struct bnx2x_config_rss_params params = {NULL};
1955
1956 /* Although RSS is meaningless when there is a single HW queue we
1957 * still need it enabled in order to have HW Rx hash generated.
1958 *
1959 * if (!is_eth_multi(bp))
1960 * bp->multi_mode = ETH_RSS_MODE_DISABLED;
1961 */
1962
1963 params.rss_obj = rss_obj;
1964
1965 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
1966
1967 __set_bit(BNX2X_RSS_MODE_REGULAR, &params.rss_flags);
1968
1969 /* RSS configuration */
1970 __set_bit(BNX2X_RSS_IPV4, &params.rss_flags);
1971 __set_bit(BNX2X_RSS_IPV4_TCP, &params.rss_flags);
1972 __set_bit(BNX2X_RSS_IPV6, &params.rss_flags);
1973 __set_bit(BNX2X_RSS_IPV6_TCP, &params.rss_flags);
1974 if (rss_obj->udp_rss_v4)
1975 __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
1976 if (rss_obj->udp_rss_v6)
1977 __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
1978
1979 /* Hash bits */
1980 params.rss_result_mask = MULTI_MASK;
1981
1982 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table));
1983
1984 if (config_hash) {
1985 /* RSS keys */
1986 prandom_bytes(params.rss_key, sizeof(params.rss_key));
1987 __set_bit(BNX2X_RSS_SET_SRCH, &params.rss_flags);
1988 }
1989
1990 return bnx2x_config_rss(bp, &params);
1991 }
1992
1993 static int bnx2x_init_hw(struct bnx2x *bp, u32 load_code)
1994 {
1995 struct bnx2x_func_state_params func_params = {NULL};
1996
1997 /* Prepare parameters for function state transitions */
1998 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
1999
2000 func_params.f_obj = &bp->func_obj;
2001 func_params.cmd = BNX2X_F_CMD_HW_INIT;
2002
2003 func_params.params.hw_init.load_phase = load_code;
2004
2005 return bnx2x_func_state_change(bp, &func_params);
2006 }
2007
2008 /*
2009 * Cleans the object that have internal lists without sending
2010 * ramrods. Should be run when interrutps are disabled.
2011 */
2012 static void bnx2x_squeeze_objects(struct bnx2x *bp)
2013 {
2014 int rc;
2015 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
2016 struct bnx2x_mcast_ramrod_params rparam = {NULL};
2017 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
2018
2019 /***************** Cleanup MACs' object first *************************/
2020
2021 /* Wait for completion of requested */
2022 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
2023 /* Perform a dry cleanup */
2024 __set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);
2025
2026 /* Clean ETH primary MAC */
2027 __set_bit(BNX2X_ETH_MAC, &vlan_mac_flags);
2028 rc = mac_obj->delete_all(bp, &bp->sp_objs->mac_obj, &vlan_mac_flags,
2029 &ramrod_flags);
2030 if (rc != 0)
2031 BNX2X_ERR("Failed to clean ETH MACs: %d\n", rc);
2032
2033 /* Cleanup UC list */
2034 vlan_mac_flags = 0;
2035 __set_bit(BNX2X_UC_LIST_MAC, &vlan_mac_flags);
2036 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags,
2037 &ramrod_flags);
2038 if (rc != 0)
2039 BNX2X_ERR("Failed to clean UC list MACs: %d\n", rc);
2040
2041 /***************** Now clean mcast object *****************************/
2042 rparam.mcast_obj = &bp->mcast_obj;
2043 __set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);
2044
2045 /* Add a DEL command... */
2046 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
2047 if (rc < 0)
2048 BNX2X_ERR("Failed to add a new DEL command to a multi-cast object: %d\n",
2049 rc);
2050
2051 /* ...and wait until all pending commands are cleared */
2052 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2053 while (rc != 0) {
2054 if (rc < 0) {
2055 BNX2X_ERR("Failed to clean multi-cast object: %d\n",
2056 rc);
2057 return;
2058 }
2059
2060 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
2061 }
2062 }
2063
2064 #ifndef BNX2X_STOP_ON_ERROR
2065 #define LOAD_ERROR_EXIT(bp, label) \
2066 do { \
2067 (bp)->state = BNX2X_STATE_ERROR; \
2068 goto label; \
2069 } while (0)
2070
2071 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2072 do { \
2073 bp->cnic_loaded = false; \
2074 goto label; \
2075 } while (0)
2076 #else /*BNX2X_STOP_ON_ERROR*/
2077 #define LOAD_ERROR_EXIT(bp, label) \
2078 do { \
2079 (bp)->state = BNX2X_STATE_ERROR; \
2080 (bp)->panic = 1; \
2081 return -EBUSY; \
2082 } while (0)
2083 #define LOAD_ERROR_EXIT_CNIC(bp, label) \
2084 do { \
2085 bp->cnic_loaded = false; \
2086 (bp)->panic = 1; \
2087 return -EBUSY; \
2088 } while (0)
2089 #endif /*BNX2X_STOP_ON_ERROR*/
2090
2091 static void bnx2x_free_fw_stats_mem(struct bnx2x *bp)
2092 {
2093 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
2094 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2095 return;
2096 }
2097
2098 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
2099 {
2100 int num_groups, vf_headroom = 0;
2101 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
2102
2103 /* number of queues for statistics is number of eth queues + FCoE */
2104 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
2105
2106 /* Total number of FW statistics requests =
2107 * 1 for port stats + 1 for PF stats + potential 2 for FCoE (fcoe proper
2108 * and fcoe l2 queue) stats + num of queues (which includes another 1
2109 * for fcoe l2 queue if applicable)
2110 */
2111 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
2112
2113 /* vf stats appear in the request list, but their data is allocated by
2114 * the VFs themselves. We don't include them in the bp->fw_stats_num as
2115 * it is used to determine where to place the vf stats queries in the
2116 * request struct
2117 */
2118 if (IS_SRIOV(bp))
2119 vf_headroom = bnx2x_vf_headroom(bp);
2120
2121 /* Request is built from stats_query_header and an array of
2122 * stats_query_cmd_group each of which contains
2123 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
2124 * configured in the stats_query_header.
2125 */
2126 num_groups =
2127 (((bp->fw_stats_num + vf_headroom) / STATS_QUERY_CMD_COUNT) +
2128 (((bp->fw_stats_num + vf_headroom) % STATS_QUERY_CMD_COUNT) ?
2129 1 : 0));
2130
2131 DP(BNX2X_MSG_SP, "stats fw_stats_num %d, vf headroom %d, num_groups %d\n",
2132 bp->fw_stats_num, vf_headroom, num_groups);
2133 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
2134 num_groups * sizeof(struct stats_query_cmd_group);
2135
2136 /* Data for statistics requests + stats_counter
2137 * stats_counter holds per-STORM counters that are incremented
2138 * when STORM has finished with the current request.
2139 * memory for FCoE offloaded statistics are counted anyway,
2140 * even if they will not be sent.
2141 * VF stats are not accounted for here as the data of VF stats is stored
2142 * in memory allocated by the VF, not here.
2143 */
2144 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
2145 sizeof(struct per_pf_stats) +
2146 sizeof(struct fcoe_statistics_params) +
2147 sizeof(struct per_queue_stats) * num_queue_stats +
2148 sizeof(struct stats_counter);
2149
2150 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
2151 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
2152
2153 /* Set shortcuts */
2154 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
2155 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
2156 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
2157 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
2158 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
2159 bp->fw_stats_req_sz;
2160
2161 DP(BNX2X_MSG_SP, "statistics request base address set to %x %x",
2162 U64_HI(bp->fw_stats_req_mapping),
2163 U64_LO(bp->fw_stats_req_mapping));
2164 DP(BNX2X_MSG_SP, "statistics data base address set to %x %x",
2165 U64_HI(bp->fw_stats_data_mapping),
2166 U64_LO(bp->fw_stats_data_mapping));
2167 return 0;
2168
2169 alloc_mem_err:
2170 bnx2x_free_fw_stats_mem(bp);
2171 BNX2X_ERR("Can't allocate FW stats memory\n");
2172 return -ENOMEM;
2173 }
2174
2175 /* send load request to mcp and analyze response */
2176 static int bnx2x_nic_load_request(struct bnx2x *bp, u32 *load_code)
2177 {
2178 /* init fw_seq */
2179 bp->fw_seq =
2180 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
2181 DRV_MSG_SEQ_NUMBER_MASK);
2182 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
2183
2184 /* Get current FW pulse sequence */
2185 bp->fw_drv_pulse_wr_seq =
2186 (SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb) &
2187 DRV_PULSE_SEQ_MASK);
2188 BNX2X_DEV_INFO("drv_pulse 0x%x\n", bp->fw_drv_pulse_wr_seq);
2189
2190 /* load request */
2191 (*load_code) = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
2192 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
2193
2194 /* if mcp fails to respond we must abort */
2195 if (!(*load_code)) {
2196 BNX2X_ERR("MCP response failure, aborting\n");
2197 return -EBUSY;
2198 }
2199
2200 /* If mcp refused (e.g. other port is in diagnostic mode) we
2201 * must abort
2202 */
2203 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) {
2204 BNX2X_ERR("MCP refused load request, aborting\n");
2205 return -EBUSY;
2206 }
2207 return 0;
2208 }
2209
2210 /* check whether another PF has already loaded FW to chip. In
2211 * virtualized environments a pf from another VM may have already
2212 * initialized the device including loading FW
2213 */
2214 int bnx2x_nic_load_analyze_req(struct bnx2x *bp, u32 load_code)
2215 {
2216 /* is another pf loaded on this engine? */
2217 if (load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP &&
2218 load_code != FW_MSG_CODE_DRV_LOAD_COMMON) {
2219 /* build my FW version dword */
2220 u32 my_fw = (BCM_5710_FW_MAJOR_VERSION) +
2221 (BCM_5710_FW_MINOR_VERSION << 8) +
2222 (BCM_5710_FW_REVISION_VERSION << 16) +
2223 (BCM_5710_FW_ENGINEERING_VERSION << 24);
2224
2225 /* read loaded FW from chip */
2226 u32 loaded_fw = REG_RD(bp, XSEM_REG_PRAM);
2227
2228 DP(BNX2X_MSG_SP, "loaded fw %x, my fw %x\n",
2229 loaded_fw, my_fw);
2230
2231 /* abort nic load if version mismatch */
2232 if (my_fw != loaded_fw) {
2233 BNX2X_ERR("bnx2x with FW %x was already loaded which mismatches my %x FW. aborting\n",
2234 loaded_fw, my_fw);
2235 return -EBUSY;
2236 }
2237 }
2238 return 0;
2239 }
2240
2241 /* returns the "mcp load_code" according to global load_count array */
2242 static int bnx2x_nic_load_no_mcp(struct bnx2x *bp, int port)
2243 {
2244 int path = BP_PATH(bp);
2245
2246 DP(NETIF_MSG_IFUP, "NO MCP - load counts[%d] %d, %d, %d\n",
2247 path, load_count[path][0], load_count[path][1],
2248 load_count[path][2]);
2249 load_count[path][0]++;
2250 load_count[path][1 + port]++;
2251 DP(NETIF_MSG_IFUP, "NO MCP - new load counts[%d] %d, %d, %d\n",
2252 path, load_count[path][0], load_count[path][1],
2253 load_count[path][2]);
2254 if (load_count[path][0] == 1)
2255 return FW_MSG_CODE_DRV_LOAD_COMMON;
2256 else if (load_count[path][1 + port] == 1)
2257 return FW_MSG_CODE_DRV_LOAD_PORT;
2258 else
2259 return FW_MSG_CODE_DRV_LOAD_FUNCTION;
2260 }
2261
2262 /* mark PMF if applicable */
2263 static void bnx2x_nic_load_pmf(struct bnx2x *bp, u32 load_code)
2264 {
2265 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2266 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) ||
2267 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) {
2268 bp->port.pmf = 1;
2269 /* We need the barrier to ensure the ordering between the
2270 * writing to bp->port.pmf here and reading it from the
2271 * bnx2x_periodic_task().
2272 */
2273 smp_mb();
2274 } else {
2275 bp->port.pmf = 0;
2276 }
2277
2278 DP(NETIF_MSG_LINK, "pmf %d\n", bp->port.pmf);
2279 }
2280
2281 static void bnx2x_nic_load_afex_dcc(struct bnx2x *bp, int load_code)
2282 {
2283 if (((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) ||
2284 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP)) &&
2285 (bp->common.shmem2_base)) {
2286 if (SHMEM2_HAS(bp, dcc_support))
2287 SHMEM2_WR(bp, dcc_support,
2288 (SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV |
2289 SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV));
2290 if (SHMEM2_HAS(bp, afex_driver_support))
2291 SHMEM2_WR(bp, afex_driver_support,
2292 SHMEM_AFEX_SUPPORTED_VERSION_ONE);
2293 }
2294
2295 /* Set AFEX default VLAN tag to an invalid value */
2296 bp->afex_def_vlan_tag = -1;
2297 }
2298
2299 /**
2300 * bnx2x_bz_fp - zero content of the fastpath structure.
2301 *
2302 * @bp: driver handle
2303 * @index: fastpath index to be zeroed
2304 *
2305 * Makes sure the contents of the bp->fp[index].napi is kept
2306 * intact.
2307 */
2308 static void bnx2x_bz_fp(struct bnx2x *bp, int index)
2309 {
2310 struct bnx2x_fastpath *fp = &bp->fp[index];
2311
2312 int cos;
2313 struct napi_struct orig_napi = fp->napi;
2314 struct bnx2x_agg_info *orig_tpa_info = fp->tpa_info;
2315 /* bzero bnx2x_fastpath contents */
2316 if (fp->tpa_info)
2317 memset(fp->tpa_info, 0, ETH_MAX_AGGREGATION_QUEUES_E1H_E2 *
2318 sizeof(struct bnx2x_agg_info));
2319 memset(fp, 0, sizeof(*fp));
2320
2321 /* Restore the NAPI object as it has been already initialized */
2322 fp->napi = orig_napi;
2323 fp->tpa_info = orig_tpa_info;
2324 fp->bp = bp;
2325 fp->index = index;
2326 if (IS_ETH_FP(fp))
2327 fp->max_cos = bp->max_cos;
2328 else
2329 /* Special queues support only one CoS */
2330 fp->max_cos = 1;
2331
2332 /* Init txdata pointers */
2333 if (IS_FCOE_FP(fp))
2334 fp->txdata_ptr[0] = &bp->bnx2x_txq[FCOE_TXQ_IDX(bp)];
2335 if (IS_ETH_FP(fp))
2336 for_each_cos_in_tx_queue(fp, cos)
2337 fp->txdata_ptr[cos] = &bp->bnx2x_txq[cos *
2338 BNX2X_NUM_ETH_QUEUES(bp) + index];
2339
2340 /*
2341 * set the tpa flag for each queue. The tpa flag determines the queue
2342 * minimal size so it must be set prior to queue memory allocation
2343 */
2344 fp->disable_tpa = !(bp->flags & TPA_ENABLE_FLAG ||
2345 (bp->flags & GRO_ENABLE_FLAG &&
2346 bnx2x_mtu_allows_gro(bp->dev->mtu)));
2347 if (bp->flags & TPA_ENABLE_FLAG)
2348 fp->mode = TPA_MODE_LRO;
2349 else if (bp->flags & GRO_ENABLE_FLAG)
2350 fp->mode = TPA_MODE_GRO;
2351
2352 /* We don't want TPA on an FCoE L2 ring */
2353 if (IS_FCOE_FP(fp))
2354 fp->disable_tpa = 1;
2355 }
2356
2357 int bnx2x_load_cnic(struct bnx2x *bp)
2358 {
2359 int i, rc, port = BP_PORT(bp);
2360
2361 DP(NETIF_MSG_IFUP, "Starting CNIC-related load\n");
2362
2363 mutex_init(&bp->cnic_mutex);
2364
2365 if (IS_PF(bp)) {
2366 rc = bnx2x_alloc_mem_cnic(bp);
2367 if (rc) {
2368 BNX2X_ERR("Unable to allocate bp memory for cnic\n");
2369 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2370 }
2371 }
2372
2373 rc = bnx2x_alloc_fp_mem_cnic(bp);
2374 if (rc) {
2375 BNX2X_ERR("Unable to allocate memory for cnic fps\n");
2376 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2377 }
2378
2379 /* Update the number of queues with the cnic queues */
2380 rc = bnx2x_set_real_num_queues(bp, 1);
2381 if (rc) {
2382 BNX2X_ERR("Unable to set real_num_queues including cnic\n");
2383 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic0);
2384 }
2385
2386 /* Add all CNIC NAPI objects */
2387 bnx2x_add_all_napi_cnic(bp);
2388 DP(NETIF_MSG_IFUP, "cnic napi added\n");
2389 bnx2x_napi_enable_cnic(bp);
2390
2391 rc = bnx2x_init_hw_func_cnic(bp);
2392 if (rc)
2393 LOAD_ERROR_EXIT_CNIC(bp, load_error_cnic1);
2394
2395 bnx2x_nic_init_cnic(bp);
2396
2397 if (IS_PF(bp)) {
2398 /* Enable Timer scan */
2399 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 1);
2400
2401 /* setup cnic queues */
2402 for_each_cnic_queue(bp, i) {
2403 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2404 if (rc) {
2405 BNX2X_ERR("Queue setup failed\n");
2406 LOAD_ERROR_EXIT(bp, load_error_cnic2);
2407 }
2408 }
2409 }
2410
2411 /* Initialize Rx filter. */
2412 netif_addr_lock_bh(bp->dev);
2413 bnx2x_set_rx_mode(bp->dev);
2414 netif_addr_unlock_bh(bp->dev);
2415
2416 /* re-read iscsi info */
2417 bnx2x_get_iscsi_info(bp);
2418 bnx2x_setup_cnic_irq_info(bp);
2419 bnx2x_setup_cnic_info(bp);
2420 bp->cnic_loaded = true;
2421 if (bp->state == BNX2X_STATE_OPEN)
2422 bnx2x_cnic_notify(bp, CNIC_CTL_START_CMD);
2423
2424
2425 DP(NETIF_MSG_IFUP, "Ending successfully CNIC-related load\n");
2426
2427 return 0;
2428
2429 #ifndef BNX2X_STOP_ON_ERROR
2430 load_error_cnic2:
2431 /* Disable Timer scan */
2432 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
2433
2434 load_error_cnic1:
2435 bnx2x_napi_disable_cnic(bp);
2436 /* Update the number of queues without the cnic queues */
2437 rc = bnx2x_set_real_num_queues(bp, 0);
2438 if (rc)
2439 BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
2440 load_error_cnic0:
2441 BNX2X_ERR("CNIC-related load failed\n");
2442 bnx2x_free_fp_mem_cnic(bp);
2443 bnx2x_free_mem_cnic(bp);
2444 return rc;
2445 #endif /* ! BNX2X_STOP_ON_ERROR */
2446 }
2447
2448 /* must be called with rtnl_lock */
2449 int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
2450 {
2451 int port = BP_PORT(bp);
2452 int i, rc = 0, load_code = 0;
2453
2454 DP(NETIF_MSG_IFUP, "Starting NIC load\n");
2455 DP(NETIF_MSG_IFUP,
2456 "CNIC is %s\n", CNIC_ENABLED(bp) ? "enabled" : "disabled");
2457
2458 #ifdef BNX2X_STOP_ON_ERROR
2459 if (unlikely(bp->panic)) {
2460 BNX2X_ERR("Can't load NIC when there is panic\n");
2461 return -EPERM;
2462 }
2463 #endif
2464
2465 bp->state = BNX2X_STATE_OPENING_WAIT4_LOAD;
2466
2467 memset(&bp->last_reported_link, 0, sizeof(bp->last_reported_link));
2468 __set_bit(BNX2X_LINK_REPORT_LINK_DOWN,
2469 &bp->last_reported_link.link_report_flags);
2470
2471 if (IS_PF(bp))
2472 /* must be called before memory allocation and HW init */
2473 bnx2x_ilt_set_info(bp);
2474
2475 /*
2476 * Zero fastpath structures preserving invariants like napi, which are
2477 * allocated only once, fp index, max_cos, bp pointer.
2478 * Also set fp->disable_tpa and txdata_ptr.
2479 */
2480 DP(NETIF_MSG_IFUP, "num queues: %d", bp->num_queues);
2481 for_each_queue(bp, i)
2482 bnx2x_bz_fp(bp, i);
2483 memset(bp->bnx2x_txq, 0, (BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS +
2484 bp->num_cnic_queues) *
2485 sizeof(struct bnx2x_fp_txdata));
2486
2487 bp->fcoe_init = false;
2488
2489 /* Set the receive queues buffer size */
2490 bnx2x_set_rx_buf_size(bp);
2491
2492 if (IS_PF(bp)) {
2493 rc = bnx2x_alloc_mem(bp);
2494 if (rc) {
2495 BNX2X_ERR("Unable to allocate bp memory\n");
2496 return rc;
2497 }
2498 }
2499
2500 /* Allocated memory for FW statistics */
2501 if (bnx2x_alloc_fw_stats_mem(bp))
2502 LOAD_ERROR_EXIT(bp, load_error0);
2503
2504 /* need to be done after alloc mem, since it's self adjusting to amount
2505 * of memory available for RSS queues
2506 */
2507 rc = bnx2x_alloc_fp_mem(bp);
2508 if (rc) {
2509 BNX2X_ERR("Unable to allocate memory for fps\n");
2510 LOAD_ERROR_EXIT(bp, load_error0);
2511 }
2512
2513 /* request pf to initialize status blocks */
2514 if (IS_VF(bp)) {
2515 rc = bnx2x_vfpf_init(bp);
2516 if (rc)
2517 LOAD_ERROR_EXIT(bp, load_error0);
2518 }
2519
2520 /* As long as bnx2x_alloc_mem() may possibly update
2521 * bp->num_queues, bnx2x_set_real_num_queues() should always
2522 * come after it. At this stage cnic queues are not counted.
2523 */
2524 rc = bnx2x_set_real_num_queues(bp, 0);
2525 if (rc) {
2526 BNX2X_ERR("Unable to set real_num_queues\n");
2527 LOAD_ERROR_EXIT(bp, load_error0);
2528 }
2529
2530 /* configure multi cos mappings in kernel.
2531 * this configuration may be overriden by a multi class queue discipline
2532 * or by a dcbx negotiation result.
2533 */
2534 bnx2x_setup_tc(bp->dev, bp->max_cos);
2535
2536 /* Add all NAPI objects */
2537 bnx2x_add_all_napi(bp);
2538 DP(NETIF_MSG_IFUP, "napi added\n");
2539 bnx2x_napi_enable(bp);
2540
2541 if (IS_PF(bp)) {
2542 /* set pf load just before approaching the MCP */
2543 bnx2x_set_pf_load(bp);
2544
2545 /* if mcp exists send load request and analyze response */
2546 if (!BP_NOMCP(bp)) {
2547 /* attempt to load pf */
2548 rc = bnx2x_nic_load_request(bp, &load_code);
2549 if (rc)
2550 LOAD_ERROR_EXIT(bp, load_error1);
2551
2552 /* what did mcp say? */
2553 rc = bnx2x_nic_load_analyze_req(bp, load_code);
2554 if (rc) {
2555 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2556 LOAD_ERROR_EXIT(bp, load_error2);
2557 }
2558 } else {
2559 load_code = bnx2x_nic_load_no_mcp(bp, port);
2560 }
2561
2562 /* mark pmf if applicable */
2563 bnx2x_nic_load_pmf(bp, load_code);
2564
2565 /* Init Function state controlling object */
2566 bnx2x__init_func_obj(bp);
2567
2568 /* Initialize HW */
2569 rc = bnx2x_init_hw(bp, load_code);
2570 if (rc) {
2571 BNX2X_ERR("HW init failed, aborting\n");
2572 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2573 LOAD_ERROR_EXIT(bp, load_error2);
2574 }
2575 }
2576
2577 /* Connect to IRQs */
2578 rc = bnx2x_setup_irqs(bp);
2579 if (rc) {
2580 BNX2X_ERR("setup irqs failed\n");
2581 if (IS_PF(bp))
2582 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2583 LOAD_ERROR_EXIT(bp, load_error2);
2584 }
2585
2586 /* Setup NIC internals and enable interrupts */
2587 bnx2x_nic_init(bp, load_code);
2588
2589 /* Init per-function objects */
2590 if (IS_PF(bp)) {
2591 bnx2x_init_bp_objs(bp);
2592 bnx2x_iov_nic_init(bp);
2593
2594 /* Set AFEX default VLAN tag to an invalid value */
2595 bp->afex_def_vlan_tag = -1;
2596 bnx2x_nic_load_afex_dcc(bp, load_code);
2597 bp->state = BNX2X_STATE_OPENING_WAIT4_PORT;
2598 rc = bnx2x_func_start(bp);
2599 if (rc) {
2600 BNX2X_ERR("Function start failed!\n");
2601 bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
2602
2603 LOAD_ERROR_EXIT(bp, load_error3);
2604 }
2605
2606 /* Send LOAD_DONE command to MCP */
2607 if (!BP_NOMCP(bp)) {
2608 load_code = bnx2x_fw_command(bp,
2609 DRV_MSG_CODE_LOAD_DONE, 0);
2610 if (!load_code) {
2611 BNX2X_ERR("MCP response failure, aborting\n");
2612 rc = -EBUSY;
2613 LOAD_ERROR_EXIT(bp, load_error3);
2614 }
2615 }
2616
2617 /* setup the leading queue */
2618 rc = bnx2x_setup_leading(bp);
2619 if (rc) {
2620 BNX2X_ERR("Setup leading failed!\n");
2621 LOAD_ERROR_EXIT(bp, load_error3);
2622 }
2623
2624 /* set up the rest of the queues */
2625 for_each_nondefault_eth_queue(bp, i) {
2626 rc = bnx2x_setup_queue(bp, &bp->fp[i], 0);
2627 if (rc) {
2628 BNX2X_ERR("Queue setup failed\n");
2629 LOAD_ERROR_EXIT(bp, load_error3);
2630 }
2631 }
2632
2633 /* setup rss */
2634 rc = bnx2x_init_rss_pf(bp);
2635 if (rc) {
2636 BNX2X_ERR("PF RSS init failed\n");
2637 LOAD_ERROR_EXIT(bp, load_error3);
2638 }
2639
2640 } else { /* vf */
2641 for_each_eth_queue(bp, i) {
2642 rc = bnx2x_vfpf_setup_q(bp, i);
2643 if (rc) {
2644 BNX2X_ERR("Queue setup failed\n");
2645 LOAD_ERROR_EXIT(bp, load_error3);
2646 }
2647 }
2648 }
2649
2650 /* Now when Clients are configured we are ready to work */
2651 bp->state = BNX2X_STATE_OPEN;
2652
2653 /* Configure a ucast MAC */
2654 if (IS_PF(bp))
2655 rc = bnx2x_set_eth_mac(bp, true);
2656 else /* vf */
2657 rc = bnx2x_vfpf_set_mac(bp);
2658 if (rc) {
2659 BNX2X_ERR("Setting Ethernet MAC failed\n");
2660 LOAD_ERROR_EXIT(bp, load_error3);
2661 }
2662
2663 if (IS_PF(bp) && bp->pending_max) {
2664 bnx2x_update_max_mf_config(bp, bp->pending_max);
2665 bp->pending_max = 0;
2666 }
2667
2668 if (bp->port.pmf) {
2669 rc = bnx2x_initial_phy_init(bp, load_mode);
2670 if (rc)
2671 LOAD_ERROR_EXIT(bp, load_error3);
2672 }
2673 bp->link_params.feature_config_flags &= ~FEATURE_CONFIG_BOOT_FROM_SAN;
2674
2675 /* Start fast path */
2676
2677 /* Initialize Rx filter. */
2678 netif_addr_lock_bh(bp->dev);
2679 bnx2x_set_rx_mode(bp->dev);
2680 netif_addr_unlock_bh(bp->dev);
2681
2682 /* Start the Tx */
2683 switch (load_mode) {
2684 case LOAD_NORMAL:
2685 /* Tx queue should be only reenabled */
2686 netif_tx_wake_all_queues(bp->dev);
2687 break;
2688
2689 case LOAD_OPEN:
2690 netif_tx_start_all_queues(bp->dev);
2691 smp_mb__after_clear_bit();
2692 break;
2693
2694 case LOAD_DIAG:
2695 case LOAD_LOOPBACK_EXT:
2696 bp->state = BNX2X_STATE_DIAG;
2697 break;
2698
2699 default:
2700 break;
2701 }
2702
2703 if (bp->port.pmf)
2704 bnx2x_update_drv_flags(bp, 1 << DRV_FLAGS_PORT_MASK, 0);
2705 else
2706 bnx2x__link_status_update(bp);
2707
2708 /* start the timer */
2709 mod_timer(&bp->timer, jiffies + bp->current_interval);
2710
2711 if (CNIC_ENABLED(bp))
2712 bnx2x_load_cnic(bp);
2713
2714 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2715 /* mark driver is loaded in shmem2 */
2716 u32 val;
2717 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2718 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2719 val | DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED |
2720 DRV_FLAGS_CAPABILITIES_LOADED_L2);
2721 }
2722
2723 /* Wait for all pending SP commands to complete */
2724 if (IS_PF(bp) && !bnx2x_wait_sp_comp(bp, ~0x0UL)) {
2725 BNX2X_ERR("Timeout waiting for SP elements to complete\n");
2726 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
2727 return -EBUSY;
2728 }
2729
2730 /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */
2731 if (bp->port.pmf && (bp->state != BNX2X_STATE_DIAG))
2732 bnx2x_dcbx_init(bp, false);
2733
2734 DP(NETIF_MSG_IFUP, "Ending successfully NIC load\n");
2735
2736 return 0;
2737
2738 #ifndef BNX2X_STOP_ON_ERROR
2739 load_error3:
2740 if (IS_PF(bp)) {
2741 bnx2x_int_disable_sync(bp, 1);
2742
2743 /* Clean queueable objects */
2744 bnx2x_squeeze_objects(bp);
2745 }
2746
2747 /* Free SKBs, SGEs, TPA pool and driver internals */
2748 bnx2x_free_skbs(bp);
2749 for_each_rx_queue(bp, i)
2750 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2751
2752 /* Release IRQs */
2753 bnx2x_free_irq(bp);
2754 load_error2:
2755 if (IS_PF(bp) && !BP_NOMCP(bp)) {
2756 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
2757 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
2758 }
2759
2760 bp->port.pmf = 0;
2761 load_error1:
2762 bnx2x_napi_disable(bp);
2763 bnx2x_del_all_napi(bp);
2764
2765 /* clear pf_load status, as it was already set */
2766 if (IS_PF(bp))
2767 bnx2x_clear_pf_load(bp);
2768 load_error0:
2769 bnx2x_free_fp_mem(bp);
2770 bnx2x_free_fw_stats_mem(bp);
2771 bnx2x_free_mem(bp);
2772
2773 return rc;
2774 #endif /* ! BNX2X_STOP_ON_ERROR */
2775 }
2776
2777 static int bnx2x_drain_tx_queues(struct bnx2x *bp)
2778 {
2779 u8 rc = 0, cos, i;
2780
2781 /* Wait until tx fastpath tasks complete */
2782 for_each_tx_queue(bp, i) {
2783 struct bnx2x_fastpath *fp = &bp->fp[i];
2784
2785 for_each_cos_in_tx_queue(fp, cos)
2786 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
2787 if (rc)
2788 return rc;
2789 }
2790 return 0;
2791 }
2792
2793 /* must be called with rtnl_lock */
2794 int bnx2x_nic_unload(struct bnx2x *bp, int unload_mode, bool keep_link)
2795 {
2796 int i;
2797 bool global = false;
2798
2799 DP(NETIF_MSG_IFUP, "Starting NIC unload\n");
2800
2801 /* mark driver is unloaded in shmem2 */
2802 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
2803 u32 val;
2804 val = SHMEM2_RD(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
2805 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
2806 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
2807 }
2808
2809 if (IS_PF(bp) && bp->recovery_state != BNX2X_RECOVERY_DONE &&
2810 (bp->state == BNX2X_STATE_CLOSED ||
2811 bp->state == BNX2X_STATE_ERROR)) {
2812 /* We can get here if the driver has been unloaded
2813 * during parity error recovery and is either waiting for a
2814 * leader to complete or for other functions to unload and
2815 * then ifdown has been issued. In this case we want to
2816 * unload and let other functions to complete a recovery
2817 * process.
2818 */
2819 bp->recovery_state = BNX2X_RECOVERY_DONE;
2820 bp->is_leader = 0;
2821 bnx2x_release_leader_lock(bp);
2822 smp_mb();
2823
2824 DP(NETIF_MSG_IFDOWN, "Releasing a leadership...\n");
2825 BNX2X_ERR("Can't unload in closed or error state\n");
2826 return -EINVAL;
2827 }
2828
2829 /* Nothing to do during unload if previous bnx2x_nic_load()
2830 * have not completed succesfully - all resourses are released.
2831 *
2832 * we can get here only after unsuccessful ndo_* callback, during which
2833 * dev->IFF_UP flag is still on.
2834 */
2835 if (bp->state == BNX2X_STATE_CLOSED || bp->state == BNX2X_STATE_ERROR)
2836 return 0;
2837
2838 /* It's important to set the bp->state to the value different from
2839 * BNX2X_STATE_OPEN and only then stop the Tx. Otherwise bnx2x_tx_int()
2840 * may restart the Tx from the NAPI context (see bnx2x_tx_int()).
2841 */
2842 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
2843 smp_mb();
2844
2845 if (CNIC_LOADED(bp))
2846 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
2847
2848 /* Stop Tx */
2849 bnx2x_tx_disable(bp);
2850 netdev_reset_tc(bp->dev);
2851
2852 bp->rx_mode = BNX2X_RX_MODE_NONE;
2853
2854 del_timer_sync(&bp->timer);
2855
2856 if (IS_PF(bp)) {
2857 /* Set ALWAYS_ALIVE bit in shmem */
2858 bp->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE;
2859 bnx2x_drv_pulse(bp);
2860 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2861 bnx2x_save_statistics(bp);
2862 }
2863
2864 /* wait till consumers catch up with producers in all queues */
2865 bnx2x_drain_tx_queues(bp);
2866
2867 /* if VF indicate to PF this function is going down (PF will delete sp
2868 * elements and clear initializations
2869 */
2870 if (IS_VF(bp))
2871 bnx2x_vfpf_close_vf(bp);
2872 else if (unload_mode != UNLOAD_RECOVERY)
2873 /* if this is a normal/close unload need to clean up chip*/
2874 bnx2x_chip_cleanup(bp, unload_mode, keep_link);
2875 else {
2876 /* Send the UNLOAD_REQUEST to the MCP */
2877 bnx2x_send_unload_req(bp, unload_mode);
2878
2879 /*
2880 * Prevent transactions to host from the functions on the
2881 * engine that doesn't reset global blocks in case of global
2882 * attention once gloabl blocks are reset and gates are opened
2883 * (the engine which leader will perform the recovery
2884 * last).
2885 */
2886 if (!CHIP_IS_E1x(bp))
2887 bnx2x_pf_disable(bp);
2888
2889 /* Disable HW interrupts, NAPI */
2890 bnx2x_netif_stop(bp, 1);
2891 /* Delete all NAPI objects */
2892 bnx2x_del_all_napi(bp);
2893 if (CNIC_LOADED(bp))
2894 bnx2x_del_all_napi_cnic(bp);
2895 /* Release IRQs */
2896 bnx2x_free_irq(bp);
2897
2898 /* Report UNLOAD_DONE to MCP */
2899 bnx2x_send_unload_done(bp, false);
2900 }
2901
2902 /*
2903 * At this stage no more interrupts will arrive so we may safly clean
2904 * the queueable objects here in case they failed to get cleaned so far.
2905 */
2906 if (IS_PF(bp))
2907 bnx2x_squeeze_objects(bp);
2908
2909 /* There should be no more pending SP commands at this stage */
2910 bp->sp_state = 0;
2911
2912 bp->port.pmf = 0;
2913
2914 /* Free SKBs, SGEs, TPA pool and driver internals */
2915 bnx2x_free_skbs(bp);
2916 if (CNIC_LOADED(bp))
2917 bnx2x_free_skbs_cnic(bp);
2918 for_each_rx_queue(bp, i)
2919 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
2920
2921 bnx2x_free_fp_mem(bp);
2922 if (CNIC_LOADED(bp))
2923 bnx2x_free_fp_mem_cnic(bp);
2924
2925 if (IS_PF(bp)) {
2926 bnx2x_free_mem(bp);
2927 if (CNIC_LOADED(bp))
2928 bnx2x_free_mem_cnic(bp);
2929 }
2930 bp->state = BNX2X_STATE_CLOSED;
2931 bp->cnic_loaded = false;
2932
2933 /* Check if there are pending parity attentions. If there are - set
2934 * RECOVERY_IN_PROGRESS.
2935 */
2936 if (IS_PF(bp) && bnx2x_chk_parity_attn(bp, &global, false)) {
2937 bnx2x_set_reset_in_progress(bp);
2938
2939 /* Set RESET_IS_GLOBAL if needed */
2940 if (global)
2941 bnx2x_set_reset_global(bp);
2942 }
2943
2944
2945 /* The last driver must disable a "close the gate" if there is no
2946 * parity attention or "process kill" pending.
2947 */
2948 if (IS_PF(bp) &&
2949 !bnx2x_clear_pf_load(bp) &&
2950 bnx2x_reset_is_done(bp, BP_PATH(bp)))
2951 bnx2x_disable_close_the_gate(bp);
2952
2953 DP(NETIF_MSG_IFUP, "Ending NIC unload\n");
2954
2955 return 0;
2956 }
2957
2958 int bnx2x_set_power_state(struct bnx2x *bp, pci_power_t state)
2959 {
2960 u16 pmcsr;
2961
2962 /* If there is no power capability, silently succeed */
2963 if (!bp->pm_cap) {
2964 BNX2X_DEV_INFO("No power capability. Breaking.\n");
2965 return 0;
2966 }
2967
2968 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmcsr);
2969
2970 switch (state) {
2971 case PCI_D0:
2972 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2973 ((pmcsr & ~PCI_PM_CTRL_STATE_MASK) |
2974 PCI_PM_CTRL_PME_STATUS));
2975
2976 if (pmcsr & PCI_PM_CTRL_STATE_MASK)
2977 /* delay required during transition out of D3hot */
2978 msleep(20);
2979 break;
2980
2981 case PCI_D3hot:
2982 /* If there are other clients above don't
2983 shut down the power */
2984 if (atomic_read(&bp->pdev->enable_cnt) != 1)
2985 return 0;
2986 /* Don't shut down the power for emulation and FPGA */
2987 if (CHIP_REV_IS_SLOW(bp))
2988 return 0;
2989
2990 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
2991 pmcsr |= 3;
2992
2993 if (bp->wol)
2994 pmcsr |= PCI_PM_CTRL_PME_ENABLE;
2995
2996 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL,
2997 pmcsr);
2998
2999 /* No more memory access after this point until
3000 * device is brought back to D0.
3001 */
3002 break;
3003
3004 default:
3005 dev_err(&bp->pdev->dev, "Can't support state = %d\n", state);
3006 return -EINVAL;
3007 }
3008 return 0;
3009 }
3010
3011 /*
3012 * net_device service functions
3013 */
3014 int bnx2x_poll(struct napi_struct *napi, int budget)
3015 {
3016 int work_done = 0;
3017 u8 cos;
3018 struct bnx2x_fastpath *fp = container_of(napi, struct bnx2x_fastpath,
3019 napi);
3020 struct bnx2x *bp = fp->bp;
3021
3022 while (1) {
3023 #ifdef BNX2X_STOP_ON_ERROR
3024 if (unlikely(bp->panic)) {
3025 napi_complete(napi);
3026 return 0;
3027 }
3028 #endif
3029
3030 for_each_cos_in_tx_queue(fp, cos)
3031 if (bnx2x_tx_queue_has_work(fp->txdata_ptr[cos]))
3032 bnx2x_tx_int(bp, fp->txdata_ptr[cos]);
3033
3034 if (bnx2x_has_rx_work(fp)) {
3035 work_done += bnx2x_rx_int(fp, budget - work_done);
3036
3037 /* must not complete if we consumed full budget */
3038 if (work_done >= budget)
3039 break;
3040 }
3041
3042 /* Fall out from the NAPI loop if needed */
3043 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
3044
3045 /* No need to update SB for FCoE L2 ring as long as
3046 * it's connected to the default SB and the SB
3047 * has been updated when NAPI was scheduled.
3048 */
3049 if (IS_FCOE_FP(fp)) {
3050 napi_complete(napi);
3051 break;
3052 }
3053 bnx2x_update_fpsb_idx(fp);
3054 /* bnx2x_has_rx_work() reads the status block,
3055 * thus we need to ensure that status block indices
3056 * have been actually read (bnx2x_update_fpsb_idx)
3057 * prior to this check (bnx2x_has_rx_work) so that
3058 * we won't write the "newer" value of the status block
3059 * to IGU (if there was a DMA right after
3060 * bnx2x_has_rx_work and if there is no rmb, the memory
3061 * reading (bnx2x_update_fpsb_idx) may be postponed
3062 * to right before bnx2x_ack_sb). In this case there
3063 * will never be another interrupt until there is
3064 * another update of the status block, while there
3065 * is still unhandled work.
3066 */
3067 rmb();
3068
3069 if (!(bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
3070 napi_complete(napi);
3071 /* Re-enable interrupts */
3072 DP(NETIF_MSG_RX_STATUS,
3073 "Update index to %d\n", fp->fp_hc_idx);
3074 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID,
3075 le16_to_cpu(fp->fp_hc_idx),
3076 IGU_INT_ENABLE, 1);
3077 break;
3078 }
3079 }
3080 }
3081
3082 return work_done;
3083 }
3084
3085 /* we split the first BD into headers and data BDs
3086 * to ease the pain of our fellow microcode engineers
3087 * we use one mapping for both BDs
3088 */
3089 static noinline u16 bnx2x_tx_split(struct bnx2x *bp,
3090 struct bnx2x_fp_txdata *txdata,
3091 struct sw_tx_bd *tx_buf,
3092 struct eth_tx_start_bd **tx_bd, u16 hlen,
3093 u16 bd_prod, int nbd)
3094 {
3095 struct eth_tx_start_bd *h_tx_bd = *tx_bd;
3096 struct eth_tx_bd *d_tx_bd;
3097 dma_addr_t mapping;
3098 int old_len = le16_to_cpu(h_tx_bd->nbytes);
3099
3100 /* first fix first BD */
3101 h_tx_bd->nbd = cpu_to_le16(nbd);
3102 h_tx_bd->nbytes = cpu_to_le16(hlen);
3103
3104 DP(NETIF_MSG_TX_QUEUED, "TSO split header size is %d (%x:%x) nbd %d\n",
3105 h_tx_bd->nbytes, h_tx_bd->addr_hi, h_tx_bd->addr_lo, h_tx_bd->nbd);
3106
3107 /* now get a new data BD
3108 * (after the pbd) and fill it */
3109 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3110 d_tx_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3111
3112 mapping = HILO_U64(le32_to_cpu(h_tx_bd->addr_hi),
3113 le32_to_cpu(h_tx_bd->addr_lo)) + hlen;
3114
3115 d_tx_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3116 d_tx_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3117 d_tx_bd->nbytes = cpu_to_le16(old_len - hlen);
3118
3119 /* this marks the BD as one that has no individual mapping */
3120 tx_buf->flags |= BNX2X_TSO_SPLIT_BD;
3121
3122 DP(NETIF_MSG_TX_QUEUED,
3123 "TSO split data size is %d (%x:%x)\n",
3124 d_tx_bd->nbytes, d_tx_bd->addr_hi, d_tx_bd->addr_lo);
3125
3126 /* update tx_bd */
3127 *tx_bd = (struct eth_tx_start_bd *)d_tx_bd;
3128
3129 return bd_prod;
3130 }
3131
3132 #define bswab32(b32) ((__force __le32) swab32((__force __u32) (b32)))
3133 #define bswab16(b16) ((__force __le16) swab16((__force __u16) (b16)))
3134 static inline __le16 bnx2x_csum_fix(unsigned char *t_header, u16 csum, s8 fix)
3135 {
3136 __sum16 tsum = (__force __sum16) csum;
3137
3138 if (fix > 0)
3139 tsum = ~csum_fold(csum_sub((__force __wsum) csum,
3140 csum_partial(t_header - fix, fix, 0)));
3141
3142 else if (fix < 0)
3143 tsum = ~csum_fold(csum_add((__force __wsum) csum,
3144 csum_partial(t_header, -fix, 0)));
3145
3146 return bswab16(tsum);
3147 }
3148
3149 static inline u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
3150 {
3151 u32 rc;
3152
3153 if (skb->ip_summed != CHECKSUM_PARTIAL)
3154 rc = XMIT_PLAIN;
3155
3156 else {
3157 if (vlan_get_protocol(skb) == htons(ETH_P_IPV6)) {
3158 rc = XMIT_CSUM_V6;
3159 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
3160 rc |= XMIT_CSUM_TCP;
3161
3162 } else {
3163 rc = XMIT_CSUM_V4;
3164 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
3165 rc |= XMIT_CSUM_TCP;
3166 }
3167 }
3168
3169 if (skb_is_gso_v6(skb))
3170 rc |= XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6;
3171 else if (skb_is_gso(skb))
3172 rc |= XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP;
3173
3174 return rc;
3175 }
3176
3177 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
3178 /* check if packet requires linearization (packet is too fragmented)
3179 no need to check fragmentation if page size > 8K (there will be no
3180 violation to FW restrictions) */
3181 static int bnx2x_pkt_req_lin(struct bnx2x *bp, struct sk_buff *skb,
3182 u32 xmit_type)
3183 {
3184 int to_copy = 0;
3185 int hlen = 0;
3186 int first_bd_sz = 0;
3187
3188 /* 3 = 1 (for linear data BD) + 2 (for PBD and last BD) */
3189 if (skb_shinfo(skb)->nr_frags >= (MAX_FETCH_BD - 3)) {
3190
3191 if (xmit_type & XMIT_GSO) {
3192 unsigned short lso_mss = skb_shinfo(skb)->gso_size;
3193 /* Check if LSO packet needs to be copied:
3194 3 = 1 (for headers BD) + 2 (for PBD and last BD) */
3195 int wnd_size = MAX_FETCH_BD - 3;
3196 /* Number of windows to check */
3197 int num_wnds = skb_shinfo(skb)->nr_frags - wnd_size;
3198 int wnd_idx = 0;
3199 int frag_idx = 0;
3200 u32 wnd_sum = 0;
3201
3202 /* Headers length */
3203 hlen = (int)(skb_transport_header(skb) - skb->data) +
3204 tcp_hdrlen(skb);
3205
3206 /* Amount of data (w/o headers) on linear part of SKB*/
3207 first_bd_sz = skb_headlen(skb) - hlen;
3208
3209 wnd_sum = first_bd_sz;
3210
3211 /* Calculate the first sum - it's special */
3212 for (frag_idx = 0; frag_idx < wnd_size - 1; frag_idx++)
3213 wnd_sum +=
3214 skb_frag_size(&skb_shinfo(skb)->frags[frag_idx]);
3215
3216 /* If there was data on linear skb data - check it */
3217 if (first_bd_sz > 0) {
3218 if (unlikely(wnd_sum < lso_mss)) {
3219 to_copy = 1;
3220 goto exit_lbl;
3221 }
3222
3223 wnd_sum -= first_bd_sz;
3224 }
3225
3226 /* Others are easier: run through the frag list and
3227 check all windows */
3228 for (wnd_idx = 0; wnd_idx <= num_wnds; wnd_idx++) {
3229 wnd_sum +=
3230 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx + wnd_size - 1]);
3231
3232 if (unlikely(wnd_sum < lso_mss)) {
3233 to_copy = 1;
3234 break;
3235 }
3236 wnd_sum -=
3237 skb_frag_size(&skb_shinfo(skb)->frags[wnd_idx]);
3238 }
3239 } else {
3240 /* in non-LSO too fragmented packet should always
3241 be linearized */
3242 to_copy = 1;
3243 }
3244 }
3245
3246 exit_lbl:
3247 if (unlikely(to_copy))
3248 DP(NETIF_MSG_TX_QUEUED,
3249 "Linearization IS REQUIRED for %s packet. num_frags %d hlen %d first_bd_sz %d\n",
3250 (xmit_type & XMIT_GSO) ? "LSO" : "non-LSO",
3251 skb_shinfo(skb)->nr_frags, hlen, first_bd_sz);
3252
3253 return to_copy;
3254 }
3255 #endif
3256
3257 static inline void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data,
3258 u32 xmit_type)
3259 {
3260 *parsing_data |= (skb_shinfo(skb)->gso_size <<
3261 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
3262 ETH_TX_PARSE_BD_E2_LSO_MSS;
3263 if ((xmit_type & XMIT_GSO_V6) &&
3264 (ipv6_hdr(skb)->nexthdr == NEXTHDR_IPV6))
3265 *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
3266 }
3267
3268 /**
3269 * bnx2x_set_pbd_gso - update PBD in GSO case.
3270 *
3271 * @skb: packet skb
3272 * @pbd: parse BD
3273 * @xmit_type: xmit flags
3274 */
3275 static inline void bnx2x_set_pbd_gso(struct sk_buff *skb,
3276 struct eth_tx_parse_bd_e1x *pbd,
3277 u32 xmit_type)
3278 {
3279 pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
3280 pbd->tcp_send_seq = bswab32(tcp_hdr(skb)->seq);
3281 pbd->tcp_flags = pbd_tcp_flags(skb);
3282
3283 if (xmit_type & XMIT_GSO_V4) {
3284 pbd->ip_id = bswab16(ip_hdr(skb)->id);
3285 pbd->tcp_pseudo_csum =
3286 bswab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
3287 ip_hdr(skb)->daddr,
3288 0, IPPROTO_TCP, 0));
3289
3290 } else
3291 pbd->tcp_pseudo_csum =
3292 bswab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
3293 &ipv6_hdr(skb)->daddr,
3294 0, IPPROTO_TCP, 0));
3295
3296 pbd->global_data |=
3297 cpu_to_le16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN);
3298 }
3299
3300 /**
3301 * bnx2x_set_pbd_csum_e2 - update PBD with checksum and return header length
3302 *
3303 * @bp: driver handle
3304 * @skb: packet skb
3305 * @parsing_data: data to be updated
3306 * @xmit_type: xmit flags
3307 *
3308 * 57712 related
3309 */
3310 static inline u8 bnx2x_set_pbd_csum_e2(struct bnx2x *bp, struct sk_buff *skb,
3311 u32 *parsing_data, u32 xmit_type)
3312 {
3313 *parsing_data |=
3314 ((((u8 *)skb_transport_header(skb) - skb->data) >> 1) <<
3315 ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT) &
3316 ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W;
3317
3318 if (xmit_type & XMIT_CSUM_TCP) {
3319 *parsing_data |= ((tcp_hdrlen(skb) / 4) <<
3320 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) &
3321 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW;
3322
3323 return skb_transport_header(skb) + tcp_hdrlen(skb) - skb->data;
3324 }
3325 /* We support checksum offload for TCP and UDP only.
3326 * No need to pass the UDP header length - it's a constant.
3327 */
3328 return skb_transport_header(skb) + sizeof(struct udphdr) - skb->data;
3329 }
3330
3331 static inline void bnx2x_set_sbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3332 struct eth_tx_start_bd *tx_start_bd, u32 xmit_type)
3333 {
3334 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM;
3335
3336 if (xmit_type & XMIT_CSUM_V4)
3337 tx_start_bd->bd_flags.as_bitfield |=
3338 ETH_TX_BD_FLAGS_IP_CSUM;
3339 else
3340 tx_start_bd->bd_flags.as_bitfield |=
3341 ETH_TX_BD_FLAGS_IPV6;
3342
3343 if (!(xmit_type & XMIT_CSUM_TCP))
3344 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IS_UDP;
3345 }
3346
3347 /**
3348 * bnx2x_set_pbd_csum - update PBD with checksum and return header length
3349 *
3350 * @bp: driver handle
3351 * @skb: packet skb
3352 * @pbd: parse BD to be updated
3353 * @xmit_type: xmit flags
3354 */
3355 static inline u8 bnx2x_set_pbd_csum(struct bnx2x *bp, struct sk_buff *skb,
3356 struct eth_tx_parse_bd_e1x *pbd,
3357 u32 xmit_type)
3358 {
3359 u8 hlen = (skb_network_header(skb) - skb->data) >> 1;
3360
3361 /* for now NS flag is not used in Linux */
3362 pbd->global_data =
3363 cpu_to_le16(hlen |
3364 ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
3365 ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT));
3366
3367 pbd->ip_hlen_w = (skb_transport_header(skb) -
3368 skb_network_header(skb)) >> 1;
3369
3370 hlen += pbd->ip_hlen_w;
3371
3372 /* We support checksum offload for TCP and UDP only */
3373 if (xmit_type & XMIT_CSUM_TCP)
3374 hlen += tcp_hdrlen(skb) / 2;
3375 else
3376 hlen += sizeof(struct udphdr) / 2;
3377
3378 pbd->total_hlen_w = cpu_to_le16(hlen);
3379 hlen = hlen*2;
3380
3381 if (xmit_type & XMIT_CSUM_TCP) {
3382 pbd->tcp_pseudo_csum = bswab16(tcp_hdr(skb)->check);
3383
3384 } else {
3385 s8 fix = SKB_CS_OFF(skb); /* signed! */
3386
3387 DP(NETIF_MSG_TX_QUEUED,
3388 "hlen %d fix %d csum before fix %x\n",
3389 le16_to_cpu(pbd->total_hlen_w), fix, SKB_CS(skb));
3390
3391 /* HW bug: fixup the CSUM */
3392 pbd->tcp_pseudo_csum =
3393 bnx2x_csum_fix(skb_transport_header(skb),
3394 SKB_CS(skb), fix);
3395
3396 DP(NETIF_MSG_TX_QUEUED, "csum after fix %x\n",
3397 pbd->tcp_pseudo_csum);
3398 }
3399
3400 return hlen;
3401 }
3402
3403 /* called with netif_tx_lock
3404 * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
3405 * netif_wake_queue()
3406 */
3407 netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
3408 {
3409 struct bnx2x *bp = netdev_priv(dev);
3410
3411 struct netdev_queue *txq;
3412 struct bnx2x_fp_txdata *txdata;
3413 struct sw_tx_bd *tx_buf;
3414 struct eth_tx_start_bd *tx_start_bd, *first_bd;
3415 struct eth_tx_bd *tx_data_bd, *total_pkt_bd = NULL;
3416 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL;
3417 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL;
3418 u32 pbd_e2_parsing_data = 0;
3419 u16 pkt_prod, bd_prod;
3420 int nbd, txq_index;
3421 dma_addr_t mapping;
3422 u32 xmit_type = bnx2x_xmit_type(bp, skb);
3423 int i;
3424 u8 hlen = 0;
3425 __le16 pkt_size = 0;
3426 struct ethhdr *eth;
3427 u8 mac_type = UNICAST_ADDRESS;
3428
3429 #ifdef BNX2X_STOP_ON_ERROR
3430 if (unlikely(bp->panic))
3431 return NETDEV_TX_BUSY;
3432 #endif
3433
3434 txq_index = skb_get_queue_mapping(skb);
3435 txq = netdev_get_tx_queue(dev, txq_index);
3436
3437 BUG_ON(txq_index >= MAX_ETH_TXQ_IDX(bp) + (CNIC_LOADED(bp) ? 1 : 0));
3438
3439 txdata = &bp->bnx2x_txq[txq_index];
3440
3441 /* enable this debug print to view the transmission queue being used
3442 DP(NETIF_MSG_TX_QUEUED, "indices: txq %d, fp %d, txdata %d\n",
3443 txq_index, fp_index, txdata_index); */
3444
3445 /* enable this debug print to view the tranmission details
3446 DP(NETIF_MSG_TX_QUEUED,
3447 "transmitting packet cid %d fp index %d txdata_index %d tx_data ptr %p fp pointer %p\n",
3448 txdata->cid, fp_index, txdata_index, txdata, fp); */
3449
3450 if (unlikely(bnx2x_tx_avail(bp, txdata) <
3451 skb_shinfo(skb)->nr_frags +
3452 BDS_PER_TX_PKT +
3453 NEXT_CNT_PER_TX_PKT(MAX_BDS_PER_TX_PKT))) {
3454 /* Handle special storage cases separately */
3455 if (txdata->tx_ring_size == 0) {
3456 struct bnx2x_eth_q_stats *q_stats =
3457 bnx2x_fp_qstats(bp, txdata->parent_fp);
3458 q_stats->driver_filtered_tx_pkt++;
3459 dev_kfree_skb(skb);
3460 return NETDEV_TX_OK;
3461 }
3462 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
3463 netif_tx_stop_queue(txq);
3464 BNX2X_ERR("BUG! Tx ring full when queue awake!\n");
3465
3466 return NETDEV_TX_BUSY;
3467 }
3468
3469 DP(NETIF_MSG_TX_QUEUED,
3470 "queue[%d]: SKB: summed %x protocol %x protocol(%x,%x) gso type %x xmit_type %x len %d\n",
3471 txq_index, skb->ip_summed, skb->protocol, ipv6_hdr(skb)->nexthdr,
3472 ip_hdr(skb)->protocol, skb_shinfo(skb)->gso_type, xmit_type,
3473 skb->len);
3474
3475 eth = (struct ethhdr *)skb->data;
3476
3477 /* set flag according to packet type (UNICAST_ADDRESS is default)*/
3478 if (unlikely(is_multicast_ether_addr(eth->h_dest))) {
3479 if (is_broadcast_ether_addr(eth->h_dest))
3480 mac_type = BROADCAST_ADDRESS;
3481 else
3482 mac_type = MULTICAST_ADDRESS;
3483 }
3484
3485 #if (MAX_SKB_FRAGS >= MAX_FETCH_BD - 3)
3486 /* First, check if we need to linearize the skb (due to FW
3487 restrictions). No need to check fragmentation if page size > 8K
3488 (there will be no violation to FW restrictions) */
3489 if (bnx2x_pkt_req_lin(bp, skb, xmit_type)) {
3490 /* Statistics of linearization */
3491 bp->lin_cnt++;
3492 if (skb_linearize(skb) != 0) {
3493 DP(NETIF_MSG_TX_QUEUED,
3494 "SKB linearization failed - silently dropping this SKB\n");
3495 dev_kfree_skb_any(skb);
3496 return NETDEV_TX_OK;
3497 }
3498 }
3499 #endif
3500 /* Map skb linear data for DMA */
3501 mapping = dma_map_single(&bp->pdev->dev, skb->data,
3502 skb_headlen(skb), DMA_TO_DEVICE);
3503 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
3504 DP(NETIF_MSG_TX_QUEUED,
3505 "SKB mapping failed - silently dropping this SKB\n");
3506 dev_kfree_skb_any(skb);
3507 return NETDEV_TX_OK;
3508 }
3509 /*
3510 Please read carefully. First we use one BD which we mark as start,
3511 then we have a parsing info BD (used for TSO or xsum),
3512 and only then we have the rest of the TSO BDs.
3513 (don't forget to mark the last one as last,
3514 and to unmap only AFTER you write to the BD ...)
3515 And above all, all pdb sizes are in words - NOT DWORDS!
3516 */
3517
3518 /* get current pkt produced now - advance it just before sending packet
3519 * since mapping of pages may fail and cause packet to be dropped
3520 */
3521 pkt_prod = txdata->tx_pkt_prod;
3522 bd_prod = TX_BD(txdata->tx_bd_prod);
3523
3524 /* get a tx_buf and first BD
3525 * tx_start_bd may be changed during SPLIT,
3526 * but first_bd will always stay first
3527 */
3528 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
3529 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
3530 first_bd = tx_start_bd;
3531
3532 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
3533 SET_FLAG(tx_start_bd->general_data,
3534 ETH_TX_START_BD_PARSE_NBDS,
3535 0);
3536
3537 /* header nbd */
3538 SET_FLAG(tx_start_bd->general_data, ETH_TX_START_BD_HDR_NBDS, 1);
3539
3540 /* remember the first BD of the packet */
3541 tx_buf->first_bd = txdata->tx_bd_prod;
3542 tx_buf->skb = skb;
3543 tx_buf->flags = 0;
3544
3545 DP(NETIF_MSG_TX_QUEUED,
3546 "sending pkt %u @%p next_idx %u bd %u @%p\n",
3547 pkt_prod, tx_buf, txdata->tx_pkt_prod, bd_prod, tx_start_bd);
3548
3549 if (vlan_tx_tag_present(skb)) {
3550 tx_start_bd->vlan_or_ethertype =
3551 cpu_to_le16(vlan_tx_tag_get(skb));
3552 tx_start_bd->bd_flags.as_bitfield |=
3553 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT);
3554 } else {
3555 /* when transmitting in a vf, start bd must hold the ethertype
3556 * for fw to enforce it
3557 */
3558 #ifndef BNX2X_STOP_ON_ERROR
3559 if (IS_VF(bp)) {
3560 #endif
3561 tx_start_bd->vlan_or_ethertype =
3562 cpu_to_le16(ntohs(eth->h_proto));
3563 #ifndef BNX2X_STOP_ON_ERROR
3564 } else {
3565 /* used by FW for packet accounting */
3566 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
3567 }
3568 #endif
3569 }
3570
3571 /* turn on parsing and get a BD */
3572 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3573
3574 if (xmit_type & XMIT_CSUM)
3575 bnx2x_set_sbd_csum(bp, skb, tx_start_bd, xmit_type);
3576
3577 if (!CHIP_IS_E1x(bp)) {
3578 pbd_e2 = &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
3579 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
3580 /* Set PBD in checksum offload case */
3581 if (xmit_type & XMIT_CSUM)
3582 hlen = bnx2x_set_pbd_csum_e2(bp, skb,
3583 &pbd_e2_parsing_data,
3584 xmit_type);
3585
3586 if (IS_MF_SI(bp) || IS_VF(bp)) {
3587 /* fill in the MAC addresses in the PBD - for local
3588 * switching
3589 */
3590 bnx2x_set_fw_mac_addr(&pbd_e2->src_mac_addr_hi,
3591 &pbd_e2->src_mac_addr_mid,
3592 &pbd_e2->src_mac_addr_lo,
3593 eth->h_source);
3594 bnx2x_set_fw_mac_addr(&pbd_e2->dst_mac_addr_hi,
3595 &pbd_e2->dst_mac_addr_mid,
3596 &pbd_e2->dst_mac_addr_lo,
3597 eth->h_dest);
3598 }
3599
3600 SET_FLAG(pbd_e2_parsing_data,
3601 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, mac_type);
3602 } else {
3603 u16 global_data = 0;
3604 pbd_e1x = &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
3605 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
3606 /* Set PBD in checksum offload case */
3607 if (xmit_type & XMIT_CSUM)
3608 hlen = bnx2x_set_pbd_csum(bp, skb, pbd_e1x, xmit_type);
3609
3610 SET_FLAG(global_data,
3611 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type);
3612 pbd_e1x->global_data |= cpu_to_le16(global_data);
3613 }
3614
3615 /* Setup the data pointer of the first BD of the packet */
3616 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3617 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3618 nbd = 2; /* start_bd + pbd + frags (updated when pages are mapped) */
3619 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
3620 pkt_size = tx_start_bd->nbytes;
3621
3622 DP(NETIF_MSG_TX_QUEUED,
3623 "first bd @%p addr (%x:%x) nbd %d nbytes %d flags %x vlan %x\n",
3624 tx_start_bd, tx_start_bd->addr_hi, tx_start_bd->addr_lo,
3625 le16_to_cpu(tx_start_bd->nbd), le16_to_cpu(tx_start_bd->nbytes),
3626 tx_start_bd->bd_flags.as_bitfield,
3627 le16_to_cpu(tx_start_bd->vlan_or_ethertype));
3628
3629 if (xmit_type & XMIT_GSO) {
3630
3631 DP(NETIF_MSG_TX_QUEUED,
3632 "TSO packet len %d hlen %d total len %d tso size %d\n",
3633 skb->len, hlen, skb_headlen(skb),
3634 skb_shinfo(skb)->gso_size);
3635
3636 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO;
3637
3638 if (unlikely(skb_headlen(skb) > hlen))
3639 bd_prod = bnx2x_tx_split(bp, txdata, tx_buf,
3640 &tx_start_bd, hlen,
3641 bd_prod, ++nbd);
3642 if (!CHIP_IS_E1x(bp))
3643 bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data,
3644 xmit_type);
3645 else
3646 bnx2x_set_pbd_gso(skb, pbd_e1x, xmit_type);
3647 }
3648
3649 /* Set the PBD's parsing_data field if not zero
3650 * (for the chips newer than 57711).
3651 */
3652 if (pbd_e2_parsing_data)
3653 pbd_e2->parsing_data = cpu_to_le32(pbd_e2_parsing_data);
3654
3655 tx_data_bd = (struct eth_tx_bd *)tx_start_bd;
3656
3657 /* Handle fragmented skb */
3658 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3659 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3660
3661 mapping = skb_frag_dma_map(&bp->pdev->dev, frag, 0,
3662 skb_frag_size(frag), DMA_TO_DEVICE);
3663 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
3664 unsigned int pkts_compl = 0, bytes_compl = 0;
3665
3666 DP(NETIF_MSG_TX_QUEUED,
3667 "Unable to map page - dropping packet...\n");
3668
3669 /* we need unmap all buffers already mapped
3670 * for this SKB;
3671 * first_bd->nbd need to be properly updated
3672 * before call to bnx2x_free_tx_pkt
3673 */
3674 first_bd->nbd = cpu_to_le16(nbd);
3675 bnx2x_free_tx_pkt(bp, txdata,
3676 TX_BD(txdata->tx_pkt_prod),
3677 &pkts_compl, &bytes_compl);
3678 return NETDEV_TX_OK;
3679 }
3680
3681 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3682 tx_data_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3683 if (total_pkt_bd == NULL)
3684 total_pkt_bd = &txdata->tx_desc_ring[bd_prod].reg_bd;
3685
3686 tx_data_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
3687 tx_data_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
3688 tx_data_bd->nbytes = cpu_to_le16(skb_frag_size(frag));
3689 le16_add_cpu(&pkt_size, skb_frag_size(frag));
3690 nbd++;
3691
3692 DP(NETIF_MSG_TX_QUEUED,
3693 "frag %d bd @%p addr (%x:%x) nbytes %d\n",
3694 i, tx_data_bd, tx_data_bd->addr_hi, tx_data_bd->addr_lo,
3695 le16_to_cpu(tx_data_bd->nbytes));
3696 }
3697
3698 DP(NETIF_MSG_TX_QUEUED, "last bd @%p\n", tx_data_bd);
3699
3700 /* update with actual num BDs */
3701 first_bd->nbd = cpu_to_le16(nbd);
3702
3703 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
3704
3705 /* now send a tx doorbell, counting the next BD
3706 * if the packet contains or ends with it
3707 */
3708 if (TX_BD_POFF(bd_prod) < nbd)
3709 nbd++;
3710
3711 /* total_pkt_bytes should be set on the first data BD if
3712 * it's not an LSO packet and there is more than one
3713 * data BD. In this case pkt_size is limited by an MTU value.
3714 * However we prefer to set it for an LSO packet (while we don't
3715 * have to) in order to save some CPU cycles in a none-LSO
3716 * case, when we much more care about them.
3717 */
3718 if (total_pkt_bd != NULL)
3719 total_pkt_bd->total_pkt_bytes = pkt_size;
3720
3721 if (pbd_e1x)
3722 DP(NETIF_MSG_TX_QUEUED,
3723 "PBD (E1X) @%p ip_data %x ip_hlen %u ip_id %u lso_mss %u tcp_flags %x xsum %x seq %u hlen %u\n",
3724 pbd_e1x, pbd_e1x->global_data, pbd_e1x->ip_hlen_w,
3725 pbd_e1x->ip_id, pbd_e1x->lso_mss, pbd_e1x->tcp_flags,
3726 pbd_e1x->tcp_pseudo_csum, pbd_e1x->tcp_send_seq,
3727 le16_to_cpu(pbd_e1x->total_hlen_w));
3728 if (pbd_e2)
3729 DP(NETIF_MSG_TX_QUEUED,
3730 "PBD (E2) @%p dst %x %x %x src %x %x %x parsing_data %x\n",
3731 pbd_e2, pbd_e2->dst_mac_addr_hi, pbd_e2->dst_mac_addr_mid,
3732 pbd_e2->dst_mac_addr_lo, pbd_e2->src_mac_addr_hi,
3733 pbd_e2->src_mac_addr_mid, pbd_e2->src_mac_addr_lo,
3734 pbd_e2->parsing_data);
3735 DP(NETIF_MSG_TX_QUEUED, "doorbell: nbd %d bd %u\n", nbd, bd_prod);
3736
3737 netdev_tx_sent_queue(txq, skb->len);
3738
3739 skb_tx_timestamp(skb);
3740
3741 txdata->tx_pkt_prod++;
3742 /*
3743 * Make sure that the BD data is updated before updating the producer
3744 * since FW might read the BD right after the producer is updated.
3745 * This is only applicable for weak-ordered memory model archs such
3746 * as IA-64. The following barrier is also mandatory since FW will
3747 * assumes packets must have BDs.
3748 */
3749 wmb();
3750
3751 txdata->tx_db.data.prod += nbd;
3752 barrier();
3753
3754 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
3755
3756 mmiowb();
3757
3758 txdata->tx_bd_prod += nbd;
3759
3760 if (unlikely(bnx2x_tx_avail(bp, txdata) < MAX_DESC_PER_TX_PKT)) {
3761 netif_tx_stop_queue(txq);
3762
3763 /* paired memory barrier is in bnx2x_tx_int(), we have to keep
3764 * ordering of set_bit() in netif_tx_stop_queue() and read of
3765 * fp->bd_tx_cons */
3766 smp_mb();
3767
3768 bnx2x_fp_qstats(bp, txdata->parent_fp)->driver_xoff++;
3769 if (bnx2x_tx_avail(bp, txdata) >= MAX_DESC_PER_TX_PKT)
3770 netif_tx_wake_queue(txq);
3771 }
3772 txdata->tx_pkt++;
3773
3774 return NETDEV_TX_OK;
3775 }
3776
3777 /**
3778 * bnx2x_setup_tc - routine to configure net_device for multi tc
3779 *
3780 * @netdev: net device to configure
3781 * @tc: number of traffic classes to enable
3782 *
3783 * callback connected to the ndo_setup_tc function pointer
3784 */
3785 int bnx2x_setup_tc(struct net_device *dev, u8 num_tc)
3786 {
3787 int cos, prio, count, offset;
3788 struct bnx2x *bp = netdev_priv(dev);
3789
3790 /* setup tc must be called under rtnl lock */
3791 ASSERT_RTNL();
3792
3793 /* no traffic classes requested. aborting */
3794 if (!num_tc) {
3795 netdev_reset_tc(dev);
3796 return 0;
3797 }
3798
3799 /* requested to support too many traffic classes */
3800 if (num_tc > bp->max_cos) {
3801 BNX2X_ERR("support for too many traffic classes requested: %d. max supported is %d\n",
3802 num_tc, bp->max_cos);
3803 return -EINVAL;
3804 }
3805
3806 /* declare amount of supported traffic classes */
3807 if (netdev_set_num_tc(dev, num_tc)) {
3808 BNX2X_ERR("failed to declare %d traffic classes\n", num_tc);
3809 return -EINVAL;
3810 }
3811
3812 /* configure priority to traffic class mapping */
3813 for (prio = 0; prio < BNX2X_MAX_PRIORITY; prio++) {
3814 netdev_set_prio_tc_map(dev, prio, bp->prio_to_cos[prio]);
3815 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
3816 "mapping priority %d to tc %d\n",
3817 prio, bp->prio_to_cos[prio]);
3818 }
3819
3820
3821 /* Use this configuration to diffrentiate tc0 from other COSes
3822 This can be used for ets or pfc, and save the effort of setting
3823 up a multio class queue disc or negotiating DCBX with a switch
3824 netdev_set_prio_tc_map(dev, 0, 0);
3825 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", 0, 0);
3826 for (prio = 1; prio < 16; prio++) {
3827 netdev_set_prio_tc_map(dev, prio, 1);
3828 DP(BNX2X_MSG_SP, "mapping priority %d to tc %d\n", prio, 1);
3829 } */
3830
3831 /* configure traffic class to transmission queue mapping */
3832 for (cos = 0; cos < bp->max_cos; cos++) {
3833 count = BNX2X_NUM_ETH_QUEUES(bp);
3834 offset = cos * BNX2X_NUM_NON_CNIC_QUEUES(bp);
3835 netdev_set_tc_queue(dev, cos, count, offset);
3836 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
3837 "mapping tc %d to offset %d count %d\n",
3838 cos, offset, count);
3839 }
3840
3841 return 0;
3842 }
3843
3844 /* called with rtnl_lock */
3845 int bnx2x_change_mac_addr(struct net_device *dev, void *p)
3846 {
3847 struct sockaddr *addr = p;
3848 struct bnx2x *bp = netdev_priv(dev);
3849 int rc = 0;
3850
3851 if (!bnx2x_is_valid_ether_addr(bp, addr->sa_data)) {
3852 BNX2X_ERR("Requested MAC address is not valid\n");
3853 return -EINVAL;
3854 }
3855
3856 if ((IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp)) &&
3857 !is_zero_ether_addr(addr->sa_data)) {
3858 BNX2X_ERR("Can't configure non-zero address on iSCSI or FCoE functions in MF-SD mode\n");
3859 return -EINVAL;
3860 }
3861
3862 if (netif_running(dev)) {
3863 rc = bnx2x_set_eth_mac(bp, false);
3864 if (rc)
3865 return rc;
3866 }
3867
3868 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
3869
3870 if (netif_running(dev))
3871 rc = bnx2x_set_eth_mac(bp, true);
3872
3873 return rc;
3874 }
3875
3876 static void bnx2x_free_fp_mem_at(struct bnx2x *bp, int fp_index)
3877 {
3878 union host_hc_status_block *sb = &bnx2x_fp(bp, fp_index, status_blk);
3879 struct bnx2x_fastpath *fp = &bp->fp[fp_index];
3880 u8 cos;
3881
3882 /* Common */
3883
3884 if (IS_FCOE_IDX(fp_index)) {
3885 memset(sb, 0, sizeof(union host_hc_status_block));
3886 fp->status_blk_mapping = 0;
3887 } else {
3888 /* status blocks */
3889 if (!CHIP_IS_E1x(bp))
3890 BNX2X_PCI_FREE(sb->e2_sb,
3891 bnx2x_fp(bp, fp_index,
3892 status_blk_mapping),
3893 sizeof(struct host_hc_status_block_e2));
3894 else
3895 BNX2X_PCI_FREE(sb->e1x_sb,
3896 bnx2x_fp(bp, fp_index,
3897 status_blk_mapping),
3898 sizeof(struct host_hc_status_block_e1x));
3899 }
3900
3901 /* Rx */
3902 if (!skip_rx_queue(bp, fp_index)) {
3903 bnx2x_free_rx_bds(fp);
3904
3905 /* fastpath rx rings: rx_buf rx_desc rx_comp */
3906 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_buf_ring));
3907 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_desc_ring),
3908 bnx2x_fp(bp, fp_index, rx_desc_mapping),
3909 sizeof(struct eth_rx_bd) * NUM_RX_BD);
3910
3911 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_comp_ring),
3912 bnx2x_fp(bp, fp_index, rx_comp_mapping),
3913 sizeof(struct eth_fast_path_rx_cqe) *
3914 NUM_RCQ_BD);
3915
3916 /* SGE ring */
3917 BNX2X_FREE(bnx2x_fp(bp, fp_index, rx_page_ring));
3918 BNX2X_PCI_FREE(bnx2x_fp(bp, fp_index, rx_sge_ring),
3919 bnx2x_fp(bp, fp_index, rx_sge_mapping),
3920 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
3921 }
3922
3923 /* Tx */
3924 if (!skip_tx_queue(bp, fp_index)) {
3925 /* fastpath tx rings: tx_buf tx_desc */
3926 for_each_cos_in_tx_queue(fp, cos) {
3927 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
3928
3929 DP(NETIF_MSG_IFDOWN,
3930 "freeing tx memory of fp %d cos %d cid %d\n",
3931 fp_index, cos, txdata->cid);
3932
3933 BNX2X_FREE(txdata->tx_buf_ring);
3934 BNX2X_PCI_FREE(txdata->tx_desc_ring,
3935 txdata->tx_desc_mapping,
3936 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
3937 }
3938 }
3939 /* end of fastpath */
3940 }
3941
3942 void bnx2x_free_fp_mem_cnic(struct bnx2x *bp)
3943 {
3944 int i;
3945 for_each_cnic_queue(bp, i)
3946 bnx2x_free_fp_mem_at(bp, i);
3947 }
3948
3949 void bnx2x_free_fp_mem(struct bnx2x *bp)
3950 {
3951 int i;
3952 for_each_eth_queue(bp, i)
3953 bnx2x_free_fp_mem_at(bp, i);
3954 }
3955
3956 static void set_sb_shortcuts(struct bnx2x *bp, int index)
3957 {
3958 union host_hc_status_block status_blk = bnx2x_fp(bp, index, status_blk);
3959 if (!CHIP_IS_E1x(bp)) {
3960 bnx2x_fp(bp, index, sb_index_values) =
3961 (__le16 *)status_blk.e2_sb->sb.index_values;
3962 bnx2x_fp(bp, index, sb_running_index) =
3963 (__le16 *)status_blk.e2_sb->sb.running_index;
3964 } else {
3965 bnx2x_fp(bp, index, sb_index_values) =
3966 (__le16 *)status_blk.e1x_sb->sb.index_values;
3967 bnx2x_fp(bp, index, sb_running_index) =
3968 (__le16 *)status_blk.e1x_sb->sb.running_index;
3969 }
3970 }
3971
3972 /* Returns the number of actually allocated BDs */
3973 static int bnx2x_alloc_rx_bds(struct bnx2x_fastpath *fp,
3974 int rx_ring_size)
3975 {
3976 struct bnx2x *bp = fp->bp;
3977 u16 ring_prod, cqe_ring_prod;
3978 int i, failure_cnt = 0;
3979
3980 fp->rx_comp_cons = 0;
3981 cqe_ring_prod = ring_prod = 0;
3982
3983 /* This routine is called only during fo init so
3984 * fp->eth_q_stats.rx_skb_alloc_failed = 0
3985 */
3986 for (i = 0; i < rx_ring_size; i++) {
3987 if (bnx2x_alloc_rx_data(bp, fp, ring_prod) < 0) {
3988 failure_cnt++;
3989 continue;
3990 }
3991 ring_prod = NEXT_RX_IDX(ring_prod);
3992 cqe_ring_prod = NEXT_RCQ_IDX(cqe_ring_prod);
3993 WARN_ON(ring_prod <= (i - failure_cnt));
3994 }
3995
3996 if (failure_cnt)
3997 BNX2X_ERR("was only able to allocate %d rx skbs on queue[%d]\n",
3998 i - failure_cnt, fp->index);
3999
4000 fp->rx_bd_prod = ring_prod;
4001 /* Limit the CQE producer by the CQE ring size */
4002 fp->rx_comp_prod = min_t(u16, NUM_RCQ_RINGS*RCQ_DESC_CNT,
4003 cqe_ring_prod);
4004 fp->rx_pkt = fp->rx_calls = 0;
4005
4006 bnx2x_fp_stats(bp, fp)->eth_q_stats.rx_skb_alloc_failed += failure_cnt;
4007
4008 return i - failure_cnt;
4009 }
4010
4011 static void bnx2x_set_next_page_rx_cq(struct bnx2x_fastpath *fp)
4012 {
4013 int i;
4014
4015 for (i = 1; i <= NUM_RCQ_RINGS; i++) {
4016 struct eth_rx_cqe_next_page *nextpg;
4017
4018 nextpg = (struct eth_rx_cqe_next_page *)
4019 &fp->rx_comp_ring[RCQ_DESC_CNT * i - 1];
4020 nextpg->addr_hi =
4021 cpu_to_le32(U64_HI(fp->rx_comp_mapping +
4022 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4023 nextpg->addr_lo =
4024 cpu_to_le32(U64_LO(fp->rx_comp_mapping +
4025 BCM_PAGE_SIZE*(i % NUM_RCQ_RINGS)));
4026 }
4027 }
4028
4029 static int bnx2x_alloc_fp_mem_at(struct bnx2x *bp, int index)
4030 {
4031 union host_hc_status_block *sb;
4032 struct bnx2x_fastpath *fp = &bp->fp[index];
4033 int ring_size = 0;
4034 u8 cos;
4035 int rx_ring_size = 0;
4036
4037 if (!bp->rx_ring_size &&
4038 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
4039 rx_ring_size = MIN_RX_SIZE_NONTPA;
4040 bp->rx_ring_size = rx_ring_size;
4041 } else if (!bp->rx_ring_size) {
4042 rx_ring_size = MAX_RX_AVAIL/BNX2X_NUM_RX_QUEUES(bp);
4043
4044 if (CHIP_IS_E3(bp)) {
4045 u32 cfg = SHMEM_RD(bp,
4046 dev_info.port_hw_config[BP_PORT(bp)].
4047 default_cfg);
4048
4049 /* Decrease ring size for 1G functions */
4050 if ((cfg & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
4051 PORT_HW_CFG_NET_SERDES_IF_SGMII)
4052 rx_ring_size /= 10;
4053 }
4054
4055 /* allocate at least number of buffers required by FW */
4056 rx_ring_size = max_t(int, bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
4057 MIN_RX_SIZE_TPA, rx_ring_size);
4058
4059 bp->rx_ring_size = rx_ring_size;
4060 } else /* if rx_ring_size specified - use it */
4061 rx_ring_size = bp->rx_ring_size;
4062
4063 DP(BNX2X_MSG_SP, "calculated rx_ring_size %d\n", rx_ring_size);
4064
4065 /* Common */
4066 sb = &bnx2x_fp(bp, index, status_blk);
4067
4068 if (!IS_FCOE_IDX(index)) {
4069 /* status blocks */
4070 if (!CHIP_IS_E1x(bp))
4071 BNX2X_PCI_ALLOC(sb->e2_sb,
4072 &bnx2x_fp(bp, index, status_blk_mapping),
4073 sizeof(struct host_hc_status_block_e2));
4074 else
4075 BNX2X_PCI_ALLOC(sb->e1x_sb,
4076 &bnx2x_fp(bp, index, status_blk_mapping),
4077 sizeof(struct host_hc_status_block_e1x));
4078 }
4079
4080 /* FCoE Queue uses Default SB and doesn't ACK the SB, thus no need to
4081 * set shortcuts for it.
4082 */
4083 if (!IS_FCOE_IDX(index))
4084 set_sb_shortcuts(bp, index);
4085
4086 /* Tx */
4087 if (!skip_tx_queue(bp, index)) {
4088 /* fastpath tx rings: tx_buf tx_desc */
4089 for_each_cos_in_tx_queue(fp, cos) {
4090 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
4091
4092 DP(NETIF_MSG_IFUP,
4093 "allocating tx memory of fp %d cos %d\n",
4094 index, cos);
4095
4096 BNX2X_ALLOC(txdata->tx_buf_ring,
4097 sizeof(struct sw_tx_bd) * NUM_TX_BD);
4098 BNX2X_PCI_ALLOC(txdata->tx_desc_ring,
4099 &txdata->tx_desc_mapping,
4100 sizeof(union eth_tx_bd_types) * NUM_TX_BD);
4101 }
4102 }
4103
4104 /* Rx */
4105 if (!skip_rx_queue(bp, index)) {
4106 /* fastpath rx rings: rx_buf rx_desc rx_comp */
4107 BNX2X_ALLOC(bnx2x_fp(bp, index, rx_buf_ring),
4108 sizeof(struct sw_rx_bd) * NUM_RX_BD);
4109 BNX2X_PCI_ALLOC(bnx2x_fp(bp, index, rx_desc_ring),
4110 &bnx2x_fp(bp, index, rx_desc_mapping),
4111 sizeof(struct eth_rx_bd) * NUM_RX_BD);
4112
4113 BNX2X_PCI_ALLOC(bnx2x_fp(bp, index, rx_comp_ring),
4114 &bnx2x_fp(bp, index, rx_comp_mapping),
4115 sizeof(struct eth_fast_path_rx_cqe) *
4116 NUM_RCQ_BD);
4117
4118 /* SGE ring */
4119 BNX2X_ALLOC(bnx2x_fp(bp, index, rx_page_ring),
4120 sizeof(struct sw_rx_page) * NUM_RX_SGE);
4121 BNX2X_PCI_ALLOC(bnx2x_fp(bp, index, rx_sge_ring),
4122 &bnx2x_fp(bp, index, rx_sge_mapping),
4123 BCM_PAGE_SIZE * NUM_RX_SGE_PAGES);
4124 /* RX BD ring */
4125 bnx2x_set_next_page_rx_bd(fp);
4126
4127 /* CQ ring */
4128 bnx2x_set_next_page_rx_cq(fp);
4129
4130 /* BDs */
4131 ring_size = bnx2x_alloc_rx_bds(fp, rx_ring_size);
4132 if (ring_size < rx_ring_size)
4133 goto alloc_mem_err;
4134 }
4135
4136 return 0;
4137
4138 /* handles low memory cases */
4139 alloc_mem_err:
4140 BNX2X_ERR("Unable to allocate full memory for queue %d (size %d)\n",
4141 index, ring_size);
4142 /* FW will drop all packets if queue is not big enough,
4143 * In these cases we disable the queue
4144 * Min size is different for OOO, TPA and non-TPA queues
4145 */
4146 if (ring_size < (fp->disable_tpa ?
4147 MIN_RX_SIZE_NONTPA : MIN_RX_SIZE_TPA)) {
4148 /* release memory allocated for this queue */
4149 bnx2x_free_fp_mem_at(bp, index);
4150 return -ENOMEM;
4151 }
4152 return 0;
4153 }
4154
4155 int bnx2x_alloc_fp_mem_cnic(struct bnx2x *bp)
4156 {
4157 if (!NO_FCOE(bp))
4158 /* FCoE */
4159 if (bnx2x_alloc_fp_mem_at(bp, FCOE_IDX(bp)))
4160 /* we will fail load process instead of mark
4161 * NO_FCOE_FLAG
4162 */
4163 return -ENOMEM;
4164
4165 return 0;
4166 }
4167
4168 int bnx2x_alloc_fp_mem(struct bnx2x *bp)
4169 {
4170 int i;
4171
4172 /* 1. Allocate FP for leading - fatal if error
4173 * 2. Allocate RSS - fix number of queues if error
4174 */
4175
4176 /* leading */
4177 if (bnx2x_alloc_fp_mem_at(bp, 0))
4178 return -ENOMEM;
4179
4180 /* RSS */
4181 for_each_nondefault_eth_queue(bp, i)
4182 if (bnx2x_alloc_fp_mem_at(bp, i))
4183 break;
4184
4185 /* handle memory failures */
4186 if (i != BNX2X_NUM_ETH_QUEUES(bp)) {
4187 int delta = BNX2X_NUM_ETH_QUEUES(bp) - i;
4188
4189 WARN_ON(delta < 0);
4190 bnx2x_shrink_eth_fp(bp, delta);
4191 if (CNIC_SUPPORT(bp))
4192 /* move non eth FPs next to last eth FP
4193 * must be done in that order
4194 * FCOE_IDX < FWD_IDX < OOO_IDX
4195 */
4196
4197 /* move FCoE fp even NO_FCOE_FLAG is on */
4198 bnx2x_move_fp(bp, FCOE_IDX(bp), FCOE_IDX(bp) - delta);
4199 bp->num_ethernet_queues -= delta;
4200 bp->num_queues = bp->num_ethernet_queues +
4201 bp->num_cnic_queues;
4202 BNX2X_ERR("Adjusted num of queues from %d to %d\n",
4203 bp->num_queues + delta, bp->num_queues);
4204 }
4205
4206 return 0;
4207 }
4208
4209 void bnx2x_free_mem_bp(struct bnx2x *bp)
4210 {
4211 int i;
4212
4213 for (i = 0; i < bp->fp_array_size; i++)
4214 kfree(bp->fp[i].tpa_info);
4215 kfree(bp->fp);
4216 kfree(bp->sp_objs);
4217 kfree(bp->fp_stats);
4218 kfree(bp->bnx2x_txq);
4219 kfree(bp->msix_table);
4220 kfree(bp->ilt);
4221 }
4222
4223 int bnx2x_alloc_mem_bp(struct bnx2x *bp)
4224 {
4225 struct bnx2x_fastpath *fp;
4226 struct msix_entry *tbl;
4227 struct bnx2x_ilt *ilt;
4228 int msix_table_size = 0;
4229 int fp_array_size, txq_array_size;
4230 int i;
4231
4232 /*
4233 * The biggest MSI-X table we might need is as a maximum number of fast
4234 * path IGU SBs plus default SB (for PF only).
4235 */
4236 msix_table_size = bp->igu_sb_cnt;
4237 if (IS_PF(bp))
4238 msix_table_size++;
4239 BNX2X_DEV_INFO("msix_table_size %d\n", msix_table_size);
4240
4241 /* fp array: RSS plus CNIC related L2 queues */
4242 fp_array_size = BNX2X_MAX_RSS_COUNT(bp) + CNIC_SUPPORT(bp);
4243 bp->fp_array_size = fp_array_size;
4244 BNX2X_DEV_INFO("fp_array_size %d\n", bp->fp_array_size);
4245
4246 fp = kcalloc(bp->fp_array_size, sizeof(*fp), GFP_KERNEL);
4247 if (!fp)
4248 goto alloc_err;
4249 for (i = 0; i < bp->fp_array_size; i++) {
4250 fp[i].tpa_info =
4251 kcalloc(ETH_MAX_AGGREGATION_QUEUES_E1H_E2,
4252 sizeof(struct bnx2x_agg_info), GFP_KERNEL);
4253 if (!(fp[i].tpa_info))
4254 goto alloc_err;
4255 }
4256
4257 bp->fp = fp;
4258
4259 /* allocate sp objs */
4260 bp->sp_objs = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_sp_objs),
4261 GFP_KERNEL);
4262 if (!bp->sp_objs)
4263 goto alloc_err;
4264
4265 /* allocate fp_stats */
4266 bp->fp_stats = kcalloc(bp->fp_array_size, sizeof(struct bnx2x_fp_stats),
4267 GFP_KERNEL);
4268 if (!bp->fp_stats)
4269 goto alloc_err;
4270
4271 /* Allocate memory for the transmission queues array */
4272 txq_array_size =
4273 BNX2X_MAX_RSS_COUNT(bp) * BNX2X_MULTI_TX_COS + CNIC_SUPPORT(bp);
4274 BNX2X_DEV_INFO("txq_array_size %d", txq_array_size);
4275
4276 bp->bnx2x_txq = kcalloc(txq_array_size, sizeof(struct bnx2x_fp_txdata),
4277 GFP_KERNEL);
4278 if (!bp->bnx2x_txq)
4279 goto alloc_err;
4280
4281 /* msix table */
4282 tbl = kcalloc(msix_table_size, sizeof(*tbl), GFP_KERNEL);
4283 if (!tbl)
4284 goto alloc_err;
4285 bp->msix_table = tbl;
4286
4287 /* ilt */
4288 ilt = kzalloc(sizeof(*ilt), GFP_KERNEL);
4289 if (!ilt)
4290 goto alloc_err;
4291 bp->ilt = ilt;
4292
4293 return 0;
4294 alloc_err:
4295 bnx2x_free_mem_bp(bp);
4296 return -ENOMEM;
4297
4298 }
4299
4300 int bnx2x_reload_if_running(struct net_device *dev)
4301 {
4302 struct bnx2x *bp = netdev_priv(dev);
4303
4304 if (unlikely(!netif_running(dev)))
4305 return 0;
4306
4307 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
4308 return bnx2x_nic_load(bp, LOAD_NORMAL);
4309 }
4310
4311 int bnx2x_get_cur_phy_idx(struct bnx2x *bp)
4312 {
4313 u32 sel_phy_idx = 0;
4314 if (bp->link_params.num_phys <= 1)
4315 return INT_PHY;
4316
4317 if (bp->link_vars.link_up) {
4318 sel_phy_idx = EXT_PHY1;
4319 /* In case link is SERDES, check if the EXT_PHY2 is the one */
4320 if ((bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) &&
4321 (bp->link_params.phy[EXT_PHY2].supported & SUPPORTED_FIBRE))
4322 sel_phy_idx = EXT_PHY2;
4323 } else {
4324
4325 switch (bnx2x_phy_selection(&bp->link_params)) {
4326 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
4327 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
4328 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
4329 sel_phy_idx = EXT_PHY1;
4330 break;
4331 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
4332 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
4333 sel_phy_idx = EXT_PHY2;
4334 break;
4335 }
4336 }
4337
4338 return sel_phy_idx;
4339
4340 }
4341 int bnx2x_get_link_cfg_idx(struct bnx2x *bp)
4342 {
4343 u32 sel_phy_idx = bnx2x_get_cur_phy_idx(bp);
4344 /*
4345 * The selected activated PHY is always after swapping (in case PHY
4346 * swapping is enabled). So when swapping is enabled, we need to reverse
4347 * the configuration
4348 */
4349
4350 if (bp->link_params.multi_phy_config &
4351 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
4352 if (sel_phy_idx == EXT_PHY1)
4353 sel_phy_idx = EXT_PHY2;
4354 else if (sel_phy_idx == EXT_PHY2)
4355 sel_phy_idx = EXT_PHY1;
4356 }
4357 return LINK_CONFIG_IDX(sel_phy_idx);
4358 }
4359
4360 #ifdef NETDEV_FCOE_WWNN
4361 int bnx2x_fcoe_get_wwn(struct net_device *dev, u64 *wwn, int type)
4362 {
4363 struct bnx2x *bp = netdev_priv(dev);
4364 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
4365
4366 switch (type) {
4367 case NETDEV_FCOE_WWNN:
4368 *wwn = HILO_U64(cp->fcoe_wwn_node_name_hi,
4369 cp->fcoe_wwn_node_name_lo);
4370 break;
4371 case NETDEV_FCOE_WWPN:
4372 *wwn = HILO_U64(cp->fcoe_wwn_port_name_hi,
4373 cp->fcoe_wwn_port_name_lo);
4374 break;
4375 default:
4376 BNX2X_ERR("Wrong WWN type requested - %d\n", type);
4377 return -EINVAL;
4378 }
4379
4380 return 0;
4381 }
4382 #endif
4383
4384 /* called with rtnl_lock */
4385 int bnx2x_change_mtu(struct net_device *dev, int new_mtu)
4386 {
4387 struct bnx2x *bp = netdev_priv(dev);
4388
4389 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
4390 BNX2X_ERR("Can't perform change MTU during parity recovery\n");
4391 return -EAGAIN;
4392 }
4393
4394 if ((new_mtu > ETH_MAX_JUMBO_PACKET_SIZE) ||
4395 ((new_mtu + ETH_HLEN) < ETH_MIN_PACKET_SIZE)) {
4396 BNX2X_ERR("Can't support requested MTU size\n");
4397 return -EINVAL;
4398 }
4399
4400 /* This does not race with packet allocation
4401 * because the actual alloc size is
4402 * only updated as part of load
4403 */
4404 dev->mtu = new_mtu;
4405
4406 return bnx2x_reload_if_running(dev);
4407 }
4408
4409 netdev_features_t bnx2x_fix_features(struct net_device *dev,
4410 netdev_features_t features)
4411 {
4412 struct bnx2x *bp = netdev_priv(dev);
4413
4414 /* TPA requires Rx CSUM offloading */
4415 if (!(features & NETIF_F_RXCSUM) || bp->disable_tpa) {
4416 features &= ~NETIF_F_LRO;
4417 features &= ~NETIF_F_GRO;
4418 }
4419
4420 return features;
4421 }
4422
4423 int bnx2x_set_features(struct net_device *dev, netdev_features_t features)
4424 {
4425 struct bnx2x *bp = netdev_priv(dev);
4426 u32 flags = bp->flags;
4427 bool bnx2x_reload = false;
4428
4429 if (features & NETIF_F_LRO)
4430 flags |= TPA_ENABLE_FLAG;
4431 else
4432 flags &= ~TPA_ENABLE_FLAG;
4433
4434 if (features & NETIF_F_GRO)
4435 flags |= GRO_ENABLE_FLAG;
4436 else
4437 flags &= ~GRO_ENABLE_FLAG;
4438
4439 if (features & NETIF_F_LOOPBACK) {
4440 if (bp->link_params.loopback_mode != LOOPBACK_BMAC) {
4441 bp->link_params.loopback_mode = LOOPBACK_BMAC;
4442 bnx2x_reload = true;
4443 }
4444 } else {
4445 if (bp->link_params.loopback_mode != LOOPBACK_NONE) {
4446 bp->link_params.loopback_mode = LOOPBACK_NONE;
4447 bnx2x_reload = true;
4448 }
4449 }
4450
4451 if (flags ^ bp->flags) {
4452 bp->flags = flags;
4453 bnx2x_reload = true;
4454 }
4455
4456 if (bnx2x_reload) {
4457 if (bp->recovery_state == BNX2X_RECOVERY_DONE)
4458 return bnx2x_reload_if_running(dev);
4459 /* else: bnx2x_nic_load() will be called at end of recovery */
4460 }
4461
4462 return 0;
4463 }
4464
4465 void bnx2x_tx_timeout(struct net_device *dev)
4466 {
4467 struct bnx2x *bp = netdev_priv(dev);
4468
4469 #ifdef BNX2X_STOP_ON_ERROR
4470 if (!bp->panic)
4471 bnx2x_panic();
4472 #endif
4473
4474 smp_mb__before_clear_bit();
4475 set_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state);
4476 smp_mb__after_clear_bit();
4477
4478 /* This allows the netif to be shutdown gracefully before resetting */
4479 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4480 }
4481
4482 int bnx2x_suspend(struct pci_dev *pdev, pm_message_t state)
4483 {
4484 struct net_device *dev = pci_get_drvdata(pdev);
4485 struct bnx2x *bp;
4486
4487 if (!dev) {
4488 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
4489 return -ENODEV;
4490 }
4491 bp = netdev_priv(dev);
4492
4493 rtnl_lock();
4494
4495 pci_save_state(pdev);
4496
4497 if (!netif_running(dev)) {
4498 rtnl_unlock();
4499 return 0;
4500 }
4501
4502 netif_device_detach(dev);
4503
4504 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
4505
4506 bnx2x_set_power_state(bp, pci_choose_state(pdev, state));
4507
4508 rtnl_unlock();
4509
4510 return 0;
4511 }
4512
4513 int bnx2x_resume(struct pci_dev *pdev)
4514 {
4515 struct net_device *dev = pci_get_drvdata(pdev);
4516 struct bnx2x *bp;
4517 int rc;
4518
4519 if (!dev) {
4520 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
4521 return -ENODEV;
4522 }
4523 bp = netdev_priv(dev);
4524
4525 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
4526 BNX2X_ERR("Handling parity error recovery. Try again later\n");
4527 return -EAGAIN;
4528 }
4529
4530 rtnl_lock();
4531
4532 pci_restore_state(pdev);
4533
4534 if (!netif_running(dev)) {
4535 rtnl_unlock();
4536 return 0;
4537 }
4538
4539 bnx2x_set_power_state(bp, PCI_D0);
4540 netif_device_attach(dev);
4541
4542 rc = bnx2x_nic_load(bp, LOAD_OPEN);
4543
4544 rtnl_unlock();
4545
4546 return rc;
4547 }
4548
4549
4550 void bnx2x_set_ctx_validation(struct bnx2x *bp, struct eth_context *cxt,
4551 u32 cid)
4552 {
4553 /* ustorm cxt validation */
4554 cxt->ustorm_ag_context.cdu_usage =
4555 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
4556 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE);
4557 /* xcontext validation */
4558 cxt->xstorm_ag_context.cdu_reserved =
4559 CDU_RSRVD_VALUE_TYPE_A(HW_CID(bp, cid),
4560 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE);
4561 }
4562
4563 static void storm_memset_hc_timeout(struct bnx2x *bp, u8 port,
4564 u8 fw_sb_id, u8 sb_index,
4565 u8 ticks)
4566 {
4567
4568 u32 addr = BAR_CSTRORM_INTMEM +
4569 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index);
4570 REG_WR8(bp, addr, ticks);
4571 DP(NETIF_MSG_IFUP,
4572 "port %x fw_sb_id %d sb_index %d ticks %d\n",
4573 port, fw_sb_id, sb_index, ticks);
4574 }
4575
4576 static void storm_memset_hc_disable(struct bnx2x *bp, u8 port,
4577 u16 fw_sb_id, u8 sb_index,
4578 u8 disable)
4579 {
4580 u32 enable_flag = disable ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT);
4581 u32 addr = BAR_CSTRORM_INTMEM +
4582 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index);
4583 u16 flags = REG_RD16(bp, addr);
4584 /* clear and set */
4585 flags &= ~HC_INDEX_DATA_HC_ENABLED;
4586 flags |= enable_flag;
4587 REG_WR16(bp, addr, flags);
4588 DP(NETIF_MSG_IFUP,
4589 "port %x fw_sb_id %d sb_index %d disable %d\n",
4590 port, fw_sb_id, sb_index, disable);
4591 }
4592
4593 void bnx2x_update_coalesce_sb_index(struct bnx2x *bp, u8 fw_sb_id,
4594 u8 sb_index, u8 disable, u16 usec)
4595 {
4596 int port = BP_PORT(bp);
4597 u8 ticks = usec / BNX2X_BTR;
4598
4599 storm_memset_hc_timeout(bp, port, fw_sb_id, sb_index, ticks);
4600
4601 disable = disable ? 1 : (usec ? 0 : 1);
4602 storm_memset_hc_disable(bp, port, fw_sb_id, sb_index, disable);
4603 }
Linux kernel - Deliverables
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