projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
bnx2x: Change to D3hot only on removal
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_ethtool.c
1 /* bnx2x_ethtool.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/ethtool.h>
21 #include <linux/netdevice.h>
22 #include <linux/types.h>
23 #include <linux/sched.h>
24 #include <linux/crc32.h>
25 #include "bnx2x.h"
26 #include "bnx2x_cmn.h"
27 #include "bnx2x_dump.h"
28 #include "bnx2x_init.h"
29
30 /* Note: in the format strings below %s is replaced by the queue-name which is
31 * either its index or 'fcoe' for the fcoe queue. Make sure the format string
32 * length does not exceed ETH_GSTRING_LEN - MAX_QUEUE_NAME_LEN + 2
33 */
34 #define MAX_QUEUE_NAME_LEN 4
35 static const struct {
36 long offset;
37 int size;
38 char string[ETH_GSTRING_LEN];
39 } bnx2x_q_stats_arr[] = {
40 /* 1 */ { Q_STATS_OFFSET32(total_bytes_received_hi), 8, "[%s]: rx_bytes" },
41 { Q_STATS_OFFSET32(total_unicast_packets_received_hi),
42 8, "[%s]: rx_ucast_packets" },
43 { Q_STATS_OFFSET32(total_multicast_packets_received_hi),
44 8, "[%s]: rx_mcast_packets" },
45 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi),
46 8, "[%s]: rx_bcast_packets" },
47 { Q_STATS_OFFSET32(no_buff_discard_hi), 8, "[%s]: rx_discards" },
48 { Q_STATS_OFFSET32(rx_err_discard_pkt),
49 4, "[%s]: rx_phy_ip_err_discards"},
50 { Q_STATS_OFFSET32(rx_skb_alloc_failed),
51 4, "[%s]: rx_skb_alloc_discard" },
52 { Q_STATS_OFFSET32(hw_csum_err), 4, "[%s]: rx_csum_offload_errors" },
53
54 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 8, "[%s]: tx_bytes" },
55 /* 10 */{ Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi),
56 8, "[%s]: tx_ucast_packets" },
57 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi),
58 8, "[%s]: tx_mcast_packets" },
59 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
60 8, "[%s]: tx_bcast_packets" },
61 { Q_STATS_OFFSET32(total_tpa_aggregations_hi),
62 8, "[%s]: tpa_aggregations" },
63 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi),
64 8, "[%s]: tpa_aggregated_frames"},
65 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 8, "[%s]: tpa_bytes"},
66 { Q_STATS_OFFSET32(driver_filtered_tx_pkt),
67 4, "[%s]: driver_filtered_tx_pkt" }
68 };
69
70 #define BNX2X_NUM_Q_STATS ARRAY_SIZE(bnx2x_q_stats_arr)
71
72 static const struct {
73 long offset;
74 int size;
75 u32 flags;
76 #define STATS_FLAGS_PORT 1
77 #define STATS_FLAGS_FUNC 2
78 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT)
79 char string[ETH_GSTRING_LEN];
80 } bnx2x_stats_arr[] = {
81 /* 1 */ { STATS_OFFSET32(total_bytes_received_hi),
82 8, STATS_FLAGS_BOTH, "rx_bytes" },
83 { STATS_OFFSET32(error_bytes_received_hi),
84 8, STATS_FLAGS_BOTH, "rx_error_bytes" },
85 { STATS_OFFSET32(total_unicast_packets_received_hi),
86 8, STATS_FLAGS_BOTH, "rx_ucast_packets" },
87 { STATS_OFFSET32(total_multicast_packets_received_hi),
88 8, STATS_FLAGS_BOTH, "rx_mcast_packets" },
89 { STATS_OFFSET32(total_broadcast_packets_received_hi),
90 8, STATS_FLAGS_BOTH, "rx_bcast_packets" },
91 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi),
92 8, STATS_FLAGS_PORT, "rx_crc_errors" },
93 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi),
94 8, STATS_FLAGS_PORT, "rx_align_errors" },
95 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi),
96 8, STATS_FLAGS_PORT, "rx_undersize_packets" },
97 { STATS_OFFSET32(etherstatsoverrsizepkts_hi),
98 8, STATS_FLAGS_PORT, "rx_oversize_packets" },
99 /* 10 */{ STATS_OFFSET32(rx_stat_etherstatsfragments_hi),
100 8, STATS_FLAGS_PORT, "rx_fragments" },
101 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi),
102 8, STATS_FLAGS_PORT, "rx_jabbers" },
103 { STATS_OFFSET32(no_buff_discard_hi),
104 8, STATS_FLAGS_BOTH, "rx_discards" },
105 { STATS_OFFSET32(mac_filter_discard),
106 4, STATS_FLAGS_PORT, "rx_filtered_packets" },
107 { STATS_OFFSET32(mf_tag_discard),
108 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" },
109 { STATS_OFFSET32(pfc_frames_received_hi),
110 8, STATS_FLAGS_PORT, "pfc_frames_received" },
111 { STATS_OFFSET32(pfc_frames_sent_hi),
112 8, STATS_FLAGS_PORT, "pfc_frames_sent" },
113 { STATS_OFFSET32(brb_drop_hi),
114 8, STATS_FLAGS_PORT, "rx_brb_discard" },
115 { STATS_OFFSET32(brb_truncate_hi),
116 8, STATS_FLAGS_PORT, "rx_brb_truncate" },
117 { STATS_OFFSET32(pause_frames_received_hi),
118 8, STATS_FLAGS_PORT, "rx_pause_frames" },
119 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi),
120 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" },
121 { STATS_OFFSET32(nig_timer_max),
122 4, STATS_FLAGS_PORT, "rx_constant_pause_events" },
123 /* 20 */{ STATS_OFFSET32(rx_err_discard_pkt),
124 4, STATS_FLAGS_BOTH, "rx_phy_ip_err_discards"},
125 { STATS_OFFSET32(rx_skb_alloc_failed),
126 4, STATS_FLAGS_BOTH, "rx_skb_alloc_discard" },
127 { STATS_OFFSET32(hw_csum_err),
128 4, STATS_FLAGS_BOTH, "rx_csum_offload_errors" },
129
130 { STATS_OFFSET32(total_bytes_transmitted_hi),
131 8, STATS_FLAGS_BOTH, "tx_bytes" },
132 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi),
133 8, STATS_FLAGS_PORT, "tx_error_bytes" },
134 { STATS_OFFSET32(total_unicast_packets_transmitted_hi),
135 8, STATS_FLAGS_BOTH, "tx_ucast_packets" },
136 { STATS_OFFSET32(total_multicast_packets_transmitted_hi),
137 8, STATS_FLAGS_BOTH, "tx_mcast_packets" },
138 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi),
139 8, STATS_FLAGS_BOTH, "tx_bcast_packets" },
140 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi),
141 8, STATS_FLAGS_PORT, "tx_mac_errors" },
142 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi),
143 8, STATS_FLAGS_PORT, "tx_carrier_errors" },
144 /* 30 */{ STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi),
145 8, STATS_FLAGS_PORT, "tx_single_collisions" },
146 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi),
147 8, STATS_FLAGS_PORT, "tx_multi_collisions" },
148 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi),
149 8, STATS_FLAGS_PORT, "tx_deferred" },
150 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi),
151 8, STATS_FLAGS_PORT, "tx_excess_collisions" },
152 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi),
153 8, STATS_FLAGS_PORT, "tx_late_collisions" },
154 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi),
155 8, STATS_FLAGS_PORT, "tx_total_collisions" },
156 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi),
157 8, STATS_FLAGS_PORT, "tx_64_byte_packets" },
158 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi),
159 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" },
160 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi),
161 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" },
162 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi),
163 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" },
164 /* 40 */{ STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi),
165 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" },
166 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi),
167 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" },
168 { STATS_OFFSET32(etherstatspktsover1522octets_hi),
169 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" },
170 { STATS_OFFSET32(pause_frames_sent_hi),
171 8, STATS_FLAGS_PORT, "tx_pause_frames" },
172 { STATS_OFFSET32(total_tpa_aggregations_hi),
173 8, STATS_FLAGS_FUNC, "tpa_aggregations" },
174 { STATS_OFFSET32(total_tpa_aggregated_frames_hi),
175 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"},
176 { STATS_OFFSET32(total_tpa_bytes_hi),
177 8, STATS_FLAGS_FUNC, "tpa_bytes"},
178 { STATS_OFFSET32(recoverable_error),
179 4, STATS_FLAGS_FUNC, "recoverable_errors" },
180 { STATS_OFFSET32(unrecoverable_error),
181 4, STATS_FLAGS_FUNC, "unrecoverable_errors" },
182 { STATS_OFFSET32(driver_filtered_tx_pkt),
183 4, STATS_FLAGS_FUNC, "driver_filtered_tx_pkt" },
184 { STATS_OFFSET32(eee_tx_lpi),
185 4, STATS_FLAGS_PORT, "Tx LPI entry count"}
186 };
187
188 #define BNX2X_NUM_STATS ARRAY_SIZE(bnx2x_stats_arr)
189
190 static int bnx2x_get_port_type(struct bnx2x *bp)
191 {
192 int port_type;
193 u32 phy_idx = bnx2x_get_cur_phy_idx(bp);
194 switch (bp->link_params.phy[phy_idx].media_type) {
195 case ETH_PHY_SFPP_10G_FIBER:
196 case ETH_PHY_SFP_1G_FIBER:
197 case ETH_PHY_XFP_FIBER:
198 case ETH_PHY_KR:
199 case ETH_PHY_CX4:
200 port_type = PORT_FIBRE;
201 break;
202 case ETH_PHY_DA_TWINAX:
203 port_type = PORT_DA;
204 break;
205 case ETH_PHY_BASE_T:
206 port_type = PORT_TP;
207 break;
208 case ETH_PHY_NOT_PRESENT:
209 port_type = PORT_NONE;
210 break;
211 case ETH_PHY_UNSPECIFIED:
212 default:
213 port_type = PORT_OTHER;
214 break;
215 }
216 return port_type;
217 }
218
219 static int bnx2x_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
220 {
221 struct bnx2x *bp = netdev_priv(dev);
222 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
223
224 /* Dual Media boards present all available port types */
225 cmd->supported = bp->port.supported[cfg_idx] |
226 (bp->port.supported[cfg_idx ^ 1] &
227 (SUPPORTED_TP | SUPPORTED_FIBRE));
228 cmd->advertising = bp->port.advertising[cfg_idx];
229 if (bp->link_params.phy[bnx2x_get_cur_phy_idx(bp)].media_type ==
230 ETH_PHY_SFP_1G_FIBER) {
231 cmd->supported &= ~(SUPPORTED_10000baseT_Full);
232 cmd->advertising &= ~(ADVERTISED_10000baseT_Full);
233 }
234
235 if ((bp->state == BNX2X_STATE_OPEN) && bp->link_vars.link_up &&
236 !(bp->flags & MF_FUNC_DIS)) {
237 cmd->duplex = bp->link_vars.duplex;
238
239 if (IS_MF(bp) && !BP_NOMCP(bp))
240 ethtool_cmd_speed_set(cmd, bnx2x_get_mf_speed(bp));
241 else
242 ethtool_cmd_speed_set(cmd, bp->link_vars.line_speed);
243 } else {
244 cmd->duplex = DUPLEX_UNKNOWN;
245 ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
246 }
247
248 cmd->port = bnx2x_get_port_type(bp);
249
250 cmd->phy_address = bp->mdio.prtad;
251 cmd->transceiver = XCVR_INTERNAL;
252
253 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG)
254 cmd->autoneg = AUTONEG_ENABLE;
255 else
256 cmd->autoneg = AUTONEG_DISABLE;
257
258 /* Publish LP advertised speeds and FC */
259 if (bp->link_vars.link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
260 u32 status = bp->link_vars.link_status;
261
262 cmd->lp_advertising |= ADVERTISED_Autoneg;
263 if (status & LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE)
264 cmd->lp_advertising |= ADVERTISED_Pause;
265 if (status & LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
266 cmd->lp_advertising |= ADVERTISED_Asym_Pause;
267
268 if (status & LINK_STATUS_LINK_PARTNER_10THD_CAPABLE)
269 cmd->lp_advertising |= ADVERTISED_10baseT_Half;
270 if (status & LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE)
271 cmd->lp_advertising |= ADVERTISED_10baseT_Full;
272 if (status & LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE)
273 cmd->lp_advertising |= ADVERTISED_100baseT_Half;
274 if (status & LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE)
275 cmd->lp_advertising |= ADVERTISED_100baseT_Full;
276 if (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE)
277 cmd->lp_advertising |= ADVERTISED_1000baseT_Half;
278 if (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE)
279 cmd->lp_advertising |= ADVERTISED_1000baseT_Full;
280 if (status & LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE)
281 cmd->lp_advertising |= ADVERTISED_2500baseX_Full;
282 if (status & LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE)
283 cmd->lp_advertising |= ADVERTISED_10000baseT_Full;
284 if (status & LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE)
285 cmd->lp_advertising |= ADVERTISED_20000baseKR2_Full;
286 }
287
288 cmd->maxtxpkt = 0;
289 cmd->maxrxpkt = 0;
290
291 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
292 " supported 0x%x advertising 0x%x speed %u\n"
293 " duplex %d port %d phy_address %d transceiver %d\n"
294 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
295 cmd->cmd, cmd->supported, cmd->advertising,
296 ethtool_cmd_speed(cmd),
297 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
298 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
299
300 return 0;
301 }
302
303 static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
304 {
305 struct bnx2x *bp = netdev_priv(dev);
306 u32 advertising, cfg_idx, old_multi_phy_config, new_multi_phy_config;
307 u32 speed, phy_idx;
308
309 if (IS_MF_SD(bp))
310 return 0;
311
312 DP(BNX2X_MSG_ETHTOOL, "ethtool_cmd: cmd %d\n"
313 " supported 0x%x advertising 0x%x speed %u\n"
314 " duplex %d port %d phy_address %d transceiver %d\n"
315 " autoneg %d maxtxpkt %d maxrxpkt %d\n",
316 cmd->cmd, cmd->supported, cmd->advertising,
317 ethtool_cmd_speed(cmd),
318 cmd->duplex, cmd->port, cmd->phy_address, cmd->transceiver,
319 cmd->autoneg, cmd->maxtxpkt, cmd->maxrxpkt);
320
321 speed = ethtool_cmd_speed(cmd);
322
323 /* If recieved a request for an unknown duplex, assume full*/
324 if (cmd->duplex == DUPLEX_UNKNOWN)
325 cmd->duplex = DUPLEX_FULL;
326
327 if (IS_MF_SI(bp)) {
328 u32 part;
329 u32 line_speed = bp->link_vars.line_speed;
330
331 /* use 10G if no link detected */
332 if (!line_speed)
333 line_speed = 10000;
334
335 if (bp->common.bc_ver < REQ_BC_VER_4_SET_MF_BW) {
336 DP(BNX2X_MSG_ETHTOOL,
337 "To set speed BC %X or higher is required, please upgrade BC\n",
338 REQ_BC_VER_4_SET_MF_BW);
339 return -EINVAL;
340 }
341
342 part = (speed * 100) / line_speed;
343
344 if (line_speed < speed || !part) {
345 DP(BNX2X_MSG_ETHTOOL,
346 "Speed setting should be in a range from 1%% to 100%% of actual line speed\n");
347 return -EINVAL;
348 }
349
350 if (bp->state != BNX2X_STATE_OPEN)
351 /* store value for following "load" */
352 bp->pending_max = part;
353 else
354 bnx2x_update_max_mf_config(bp, part);
355
356 return 0;
357 }
358
359 cfg_idx = bnx2x_get_link_cfg_idx(bp);
360 old_multi_phy_config = bp->link_params.multi_phy_config;
361 switch (cmd->port) {
362 case PORT_TP:
363 if (bp->port.supported[cfg_idx] & SUPPORTED_TP)
364 break; /* no port change */
365
366 if (!(bp->port.supported[0] & SUPPORTED_TP ||
367 bp->port.supported[1] & SUPPORTED_TP)) {
368 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
369 return -EINVAL;
370 }
371 bp->link_params.multi_phy_config &=
372 ~PORT_HW_CFG_PHY_SELECTION_MASK;
373 if (bp->link_params.multi_phy_config &
374 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
375 bp->link_params.multi_phy_config |=
376 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
377 else
378 bp->link_params.multi_phy_config |=
379 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
380 break;
381 case PORT_FIBRE:
382 case PORT_DA:
383 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
384 break; /* no port change */
385
386 if (!(bp->port.supported[0] & SUPPORTED_FIBRE ||
387 bp->port.supported[1] & SUPPORTED_FIBRE)) {
388 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
389 return -EINVAL;
390 }
391 bp->link_params.multi_phy_config &=
392 ~PORT_HW_CFG_PHY_SELECTION_MASK;
393 if (bp->link_params.multi_phy_config &
394 PORT_HW_CFG_PHY_SWAPPED_ENABLED)
395 bp->link_params.multi_phy_config |=
396 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
397 else
398 bp->link_params.multi_phy_config |=
399 PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
400 break;
401 default:
402 DP(BNX2X_MSG_ETHTOOL, "Unsupported port type\n");
403 return -EINVAL;
404 }
405 /* Save new config in case command complete successfully */
406 new_multi_phy_config = bp->link_params.multi_phy_config;
407 /* Get the new cfg_idx */
408 cfg_idx = bnx2x_get_link_cfg_idx(bp);
409 /* Restore old config in case command failed */
410 bp->link_params.multi_phy_config = old_multi_phy_config;
411 DP(BNX2X_MSG_ETHTOOL, "cfg_idx = %x\n", cfg_idx);
412
413 if (cmd->autoneg == AUTONEG_ENABLE) {
414 u32 an_supported_speed = bp->port.supported[cfg_idx];
415 if (bp->link_params.phy[EXT_PHY1].type ==
416 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
417 an_supported_speed |= (SUPPORTED_100baseT_Half |
418 SUPPORTED_100baseT_Full);
419 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
420 DP(BNX2X_MSG_ETHTOOL, "Autoneg not supported\n");
421 return -EINVAL;
422 }
423
424 /* advertise the requested speed and duplex if supported */
425 if (cmd->advertising & ~an_supported_speed) {
426 DP(BNX2X_MSG_ETHTOOL,
427 "Advertisement parameters are not supported\n");
428 return -EINVAL;
429 }
430
431 bp->link_params.req_line_speed[cfg_idx] = SPEED_AUTO_NEG;
432 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
433 bp->port.advertising[cfg_idx] = (ADVERTISED_Autoneg |
434 cmd->advertising);
435 if (cmd->advertising) {
436
437 bp->link_params.speed_cap_mask[cfg_idx] = 0;
438 if (cmd->advertising & ADVERTISED_10baseT_Half) {
439 bp->link_params.speed_cap_mask[cfg_idx] |=
440 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF;
441 }
442 if (cmd->advertising & ADVERTISED_10baseT_Full)
443 bp->link_params.speed_cap_mask[cfg_idx] |=
444 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL;
445
446 if (cmd->advertising & ADVERTISED_100baseT_Full)
447 bp->link_params.speed_cap_mask[cfg_idx] |=
448 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL;
449
450 if (cmd->advertising & ADVERTISED_100baseT_Half) {
451 bp->link_params.speed_cap_mask[cfg_idx] |=
452 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF;
453 }
454 if (cmd->advertising & ADVERTISED_1000baseT_Half) {
455 bp->link_params.speed_cap_mask[cfg_idx] |=
456 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
457 }
458 if (cmd->advertising & (ADVERTISED_1000baseT_Full |
459 ADVERTISED_1000baseKX_Full))
460 bp->link_params.speed_cap_mask[cfg_idx] |=
461 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G;
462
463 if (cmd->advertising & (ADVERTISED_10000baseT_Full |
464 ADVERTISED_10000baseKX4_Full |
465 ADVERTISED_10000baseKR_Full))
466 bp->link_params.speed_cap_mask[cfg_idx] |=
467 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G;
468
469 if (cmd->advertising & ADVERTISED_20000baseKR2_Full)
470 bp->link_params.speed_cap_mask[cfg_idx] |=
471 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G;
472 }
473 } else { /* forced speed */
474 /* advertise the requested speed and duplex if supported */
475 switch (speed) {
476 case SPEED_10:
477 if (cmd->duplex == DUPLEX_FULL) {
478 if (!(bp->port.supported[cfg_idx] &
479 SUPPORTED_10baseT_Full)) {
480 DP(BNX2X_MSG_ETHTOOL,
481 "10M full not supported\n");
482 return -EINVAL;
483 }
484
485 advertising = (ADVERTISED_10baseT_Full |
486 ADVERTISED_TP);
487 } else {
488 if (!(bp->port.supported[cfg_idx] &
489 SUPPORTED_10baseT_Half)) {
490 DP(BNX2X_MSG_ETHTOOL,
491 "10M half not supported\n");
492 return -EINVAL;
493 }
494
495 advertising = (ADVERTISED_10baseT_Half |
496 ADVERTISED_TP);
497 }
498 break;
499
500 case SPEED_100:
501 if (cmd->duplex == DUPLEX_FULL) {
502 if (!(bp->port.supported[cfg_idx] &
503 SUPPORTED_100baseT_Full)) {
504 DP(BNX2X_MSG_ETHTOOL,
505 "100M full not supported\n");
506 return -EINVAL;
507 }
508
509 advertising = (ADVERTISED_100baseT_Full |
510 ADVERTISED_TP);
511 } else {
512 if (!(bp->port.supported[cfg_idx] &
513 SUPPORTED_100baseT_Half)) {
514 DP(BNX2X_MSG_ETHTOOL,
515 "100M half not supported\n");
516 return -EINVAL;
517 }
518
519 advertising = (ADVERTISED_100baseT_Half |
520 ADVERTISED_TP);
521 }
522 break;
523
524 case SPEED_1000:
525 if (cmd->duplex != DUPLEX_FULL) {
526 DP(BNX2X_MSG_ETHTOOL,
527 "1G half not supported\n");
528 return -EINVAL;
529 }
530
531 if (!(bp->port.supported[cfg_idx] &
532 SUPPORTED_1000baseT_Full)) {
533 DP(BNX2X_MSG_ETHTOOL,
534 "1G full not supported\n");
535 return -EINVAL;
536 }
537
538 advertising = (ADVERTISED_1000baseT_Full |
539 ADVERTISED_TP);
540 break;
541
542 case SPEED_2500:
543 if (cmd->duplex != DUPLEX_FULL) {
544 DP(BNX2X_MSG_ETHTOOL,
545 "2.5G half not supported\n");
546 return -EINVAL;
547 }
548
549 if (!(bp->port.supported[cfg_idx]
550 & SUPPORTED_2500baseX_Full)) {
551 DP(BNX2X_MSG_ETHTOOL,
552 "2.5G full not supported\n");
553 return -EINVAL;
554 }
555
556 advertising = (ADVERTISED_2500baseX_Full |
557 ADVERTISED_TP);
558 break;
559
560 case SPEED_10000:
561 if (cmd->duplex != DUPLEX_FULL) {
562 DP(BNX2X_MSG_ETHTOOL,
563 "10G half not supported\n");
564 return -EINVAL;
565 }
566 phy_idx = bnx2x_get_cur_phy_idx(bp);
567 if (!(bp->port.supported[cfg_idx]
568 & SUPPORTED_10000baseT_Full) ||
569 (bp->link_params.phy[phy_idx].media_type ==
570 ETH_PHY_SFP_1G_FIBER)) {
571 DP(BNX2X_MSG_ETHTOOL,
572 "10G full not supported\n");
573 return -EINVAL;
574 }
575
576 advertising = (ADVERTISED_10000baseT_Full |
577 ADVERTISED_FIBRE);
578 break;
579
580 default:
581 DP(BNX2X_MSG_ETHTOOL, "Unsupported speed %u\n", speed);
582 return -EINVAL;
583 }
584
585 bp->link_params.req_line_speed[cfg_idx] = speed;
586 bp->link_params.req_duplex[cfg_idx] = cmd->duplex;
587 bp->port.advertising[cfg_idx] = advertising;
588 }
589
590 DP(BNX2X_MSG_ETHTOOL, "req_line_speed %d\n"
591 " req_duplex %d advertising 0x%x\n",
592 bp->link_params.req_line_speed[cfg_idx],
593 bp->link_params.req_duplex[cfg_idx],
594 bp->port.advertising[cfg_idx]);
595
596 /* Set new config */
597 bp->link_params.multi_phy_config = new_multi_phy_config;
598 if (netif_running(dev)) {
599 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
600 bnx2x_link_set(bp);
601 }
602
603 return 0;
604 }
605
606 #define DUMP_ALL_PRESETS 0x1FFF
607 #define DUMP_MAX_PRESETS 13
608
609 static int __bnx2x_get_preset_regs_len(struct bnx2x *bp, u32 preset)
610 {
611 if (CHIP_IS_E1(bp))
612 return dump_num_registers[0][preset-1];
613 else if (CHIP_IS_E1H(bp))
614 return dump_num_registers[1][preset-1];
615 else if (CHIP_IS_E2(bp))
616 return dump_num_registers[2][preset-1];
617 else if (CHIP_IS_E3A0(bp))
618 return dump_num_registers[3][preset-1];
619 else if (CHIP_IS_E3B0(bp))
620 return dump_num_registers[4][preset-1];
621 else
622 return 0;
623 }
624
625 static int __bnx2x_get_regs_len(struct bnx2x *bp)
626 {
627 u32 preset_idx;
628 int regdump_len = 0;
629
630 /* Calculate the total preset regs length */
631 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++)
632 regdump_len += __bnx2x_get_preset_regs_len(bp, preset_idx);
633
634 return regdump_len;
635 }
636
637 static int bnx2x_get_regs_len(struct net_device *dev)
638 {
639 struct bnx2x *bp = netdev_priv(dev);
640 int regdump_len = 0;
641
642 regdump_len = __bnx2x_get_regs_len(bp);
643 regdump_len *= 4;
644 regdump_len += sizeof(struct dump_header);
645
646 return regdump_len;
647 }
648
649 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1)
650 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H)
651 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2)
652 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0)
653 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0)
654
655 #define IS_REG_IN_PRESET(presets, idx) \
656 ((presets & (1 << (idx-1))) == (1 << (idx-1)))
657
658 /******* Paged registers info selectors ********/
659 static const u32 *__bnx2x_get_page_addr_ar(struct bnx2x *bp)
660 {
661 if (CHIP_IS_E2(bp))
662 return page_vals_e2;
663 else if (CHIP_IS_E3(bp))
664 return page_vals_e3;
665 else
666 return NULL;
667 }
668
669 static u32 __bnx2x_get_page_reg_num(struct bnx2x *bp)
670 {
671 if (CHIP_IS_E2(bp))
672 return PAGE_MODE_VALUES_E2;
673 else if (CHIP_IS_E3(bp))
674 return PAGE_MODE_VALUES_E3;
675 else
676 return 0;
677 }
678
679 static const u32 *__bnx2x_get_page_write_ar(struct bnx2x *bp)
680 {
681 if (CHIP_IS_E2(bp))
682 return page_write_regs_e2;
683 else if (CHIP_IS_E3(bp))
684 return page_write_regs_e3;
685 else
686 return NULL;
687 }
688
689 static u32 __bnx2x_get_page_write_num(struct bnx2x *bp)
690 {
691 if (CHIP_IS_E2(bp))
692 return PAGE_WRITE_REGS_E2;
693 else if (CHIP_IS_E3(bp))
694 return PAGE_WRITE_REGS_E3;
695 else
696 return 0;
697 }
698
699 static const struct reg_addr *__bnx2x_get_page_read_ar(struct bnx2x *bp)
700 {
701 if (CHIP_IS_E2(bp))
702 return page_read_regs_e2;
703 else if (CHIP_IS_E3(bp))
704 return page_read_regs_e3;
705 else
706 return NULL;
707 }
708
709 static u32 __bnx2x_get_page_read_num(struct bnx2x *bp)
710 {
711 if (CHIP_IS_E2(bp))
712 return PAGE_READ_REGS_E2;
713 else if (CHIP_IS_E3(bp))
714 return PAGE_READ_REGS_E3;
715 else
716 return 0;
717 }
718
719 static bool bnx2x_is_reg_in_chip(struct bnx2x *bp,
720 const struct reg_addr *reg_info)
721 {
722 if (CHIP_IS_E1(bp))
723 return IS_E1_REG(reg_info->chips);
724 else if (CHIP_IS_E1H(bp))
725 return IS_E1H_REG(reg_info->chips);
726 else if (CHIP_IS_E2(bp))
727 return IS_E2_REG(reg_info->chips);
728 else if (CHIP_IS_E3A0(bp))
729 return IS_E3A0_REG(reg_info->chips);
730 else if (CHIP_IS_E3B0(bp))
731 return IS_E3B0_REG(reg_info->chips);
732 else
733 return false;
734 }
735
736
737 static bool bnx2x_is_wreg_in_chip(struct bnx2x *bp,
738 const struct wreg_addr *wreg_info)
739 {
740 if (CHIP_IS_E1(bp))
741 return IS_E1_REG(wreg_info->chips);
742 else if (CHIP_IS_E1H(bp))
743 return IS_E1H_REG(wreg_info->chips);
744 else if (CHIP_IS_E2(bp))
745 return IS_E2_REG(wreg_info->chips);
746 else if (CHIP_IS_E3A0(bp))
747 return IS_E3A0_REG(wreg_info->chips);
748 else if (CHIP_IS_E3B0(bp))
749 return IS_E3B0_REG(wreg_info->chips);
750 else
751 return false;
752 }
753
754 /**
755 * bnx2x_read_pages_regs - read "paged" registers
756 *
757 * @bp device handle
758 * @p output buffer
759 *
760 * Reads "paged" memories: memories that may only be read by first writing to a
761 * specific address ("write address") and then reading from a specific address
762 * ("read address"). There may be more than one write address per "page" and
763 * more than one read address per write address.
764 */
765 static void bnx2x_read_pages_regs(struct bnx2x *bp, u32 *p, u32 preset)
766 {
767 u32 i, j, k, n;
768
769 /* addresses of the paged registers */
770 const u32 *page_addr = __bnx2x_get_page_addr_ar(bp);
771 /* number of paged registers */
772 int num_pages = __bnx2x_get_page_reg_num(bp);
773 /* write addresses */
774 const u32 *write_addr = __bnx2x_get_page_write_ar(bp);
775 /* number of write addresses */
776 int write_num = __bnx2x_get_page_write_num(bp);
777 /* read addresses info */
778 const struct reg_addr *read_addr = __bnx2x_get_page_read_ar(bp);
779 /* number of read addresses */
780 int read_num = __bnx2x_get_page_read_num(bp);
781 u32 addr, size;
782
783 for (i = 0; i < num_pages; i++) {
784 for (j = 0; j < write_num; j++) {
785 REG_WR(bp, write_addr[j], page_addr[i]);
786
787 for (k = 0; k < read_num; k++) {
788 if (IS_REG_IN_PRESET(read_addr[k].presets,
789 preset)) {
790 size = read_addr[k].size;
791 for (n = 0; n < size; n++) {
792 addr = read_addr[k].addr + n*4;
793 *p++ = REG_RD(bp, addr);
794 }
795 }
796 }
797 }
798 }
799 }
800
801 static int __bnx2x_get_preset_regs(struct bnx2x *bp, u32 *p, u32 preset)
802 {
803 u32 i, j, addr;
804 const struct wreg_addr *wreg_addr_p = NULL;
805
806 if (CHIP_IS_E1(bp))
807 wreg_addr_p = &wreg_addr_e1;
808 else if (CHIP_IS_E1H(bp))
809 wreg_addr_p = &wreg_addr_e1h;
810 else if (CHIP_IS_E2(bp))
811 wreg_addr_p = &wreg_addr_e2;
812 else if (CHIP_IS_E3A0(bp))
813 wreg_addr_p = &wreg_addr_e3;
814 else if (CHIP_IS_E3B0(bp))
815 wreg_addr_p = &wreg_addr_e3b0;
816
817 /* Read the idle_chk registers */
818 for (i = 0; i < IDLE_REGS_COUNT; i++) {
819 if (bnx2x_is_reg_in_chip(bp, &idle_reg_addrs[i]) &&
820 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) {
821 for (j = 0; j < idle_reg_addrs[i].size; j++)
822 *p++ = REG_RD(bp, idle_reg_addrs[i].addr + j*4);
823 }
824 }
825
826 /* Read the regular registers */
827 for (i = 0; i < REGS_COUNT; i++) {
828 if (bnx2x_is_reg_in_chip(bp, &reg_addrs[i]) &&
829 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) {
830 for (j = 0; j < reg_addrs[i].size; j++)
831 *p++ = REG_RD(bp, reg_addrs[i].addr + j*4);
832 }
833 }
834
835 /* Read the CAM registers */
836 if (bnx2x_is_wreg_in_chip(bp, wreg_addr_p) &&
837 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) {
838 for (i = 0; i < wreg_addr_p->size; i++) {
839 *p++ = REG_RD(bp, wreg_addr_p->addr + i*4);
840
841 /* In case of wreg_addr register, read additional
842 registers from read_regs array
843 */
844 for (j = 0; j < wreg_addr_p->read_regs_count; j++) {
845 addr = *(wreg_addr_p->read_regs);
846 *p++ = REG_RD(bp, addr + j*4);
847 }
848 }
849 }
850
851 /* Paged registers are supported in E2 & E3 only */
852 if (CHIP_IS_E2(bp) || CHIP_IS_E3(bp)) {
853 /* Read "paged" registes */
854 bnx2x_read_pages_regs(bp, p, preset);
855 }
856
857 return 0;
858 }
859
860 static void __bnx2x_get_regs(struct bnx2x *bp, u32 *p)
861 {
862 u32 preset_idx;
863
864 /* Read all registers, by reading all preset registers */
865 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) {
866 /* Skip presets with IOR */
867 if ((preset_idx == 2) ||
868 (preset_idx == 5) ||
869 (preset_idx == 8) ||
870 (preset_idx == 11))
871 continue;
872 __bnx2x_get_preset_regs(bp, p, preset_idx);
873 p += __bnx2x_get_preset_regs_len(bp, preset_idx);
874 }
875 }
876
877 static void bnx2x_get_regs(struct net_device *dev,
878 struct ethtool_regs *regs, void *_p)
879 {
880 u32 *p = _p;
881 struct bnx2x *bp = netdev_priv(dev);
882 struct dump_header dump_hdr = {0};
883
884 regs->version = 2;
885 memset(p, 0, regs->len);
886
887 if (!netif_running(bp->dev))
888 return;
889
890 /* Disable parity attentions as long as following dump may
891 * cause false alarms by reading never written registers. We
892 * will re-enable parity attentions right after the dump.
893 */
894
895 /* Disable parity on path 0 */
896 bnx2x_pretend_func(bp, 0);
897 bnx2x_disable_blocks_parity(bp);
898
899 /* Disable parity on path 1 */
900 bnx2x_pretend_func(bp, 1);
901 bnx2x_disable_blocks_parity(bp);
902
903 /* Return to current function */
904 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
905
906 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
907 dump_hdr.preset = DUMP_ALL_PRESETS;
908 dump_hdr.version = BNX2X_DUMP_VERSION;
909
910 /* dump_meta_data presents OR of CHIP and PATH. */
911 if (CHIP_IS_E1(bp)) {
912 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
913 } else if (CHIP_IS_E1H(bp)) {
914 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
915 } else if (CHIP_IS_E2(bp)) {
916 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
917 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
918 } else if (CHIP_IS_E3A0(bp)) {
919 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
920 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
921 } else if (CHIP_IS_E3B0(bp)) {
922 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
923 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
924 }
925
926 memcpy(p, &dump_hdr, sizeof(struct dump_header));
927 p += dump_hdr.header_size + 1;
928
929 /* Actually read the registers */
930 __bnx2x_get_regs(bp, p);
931
932 /* Re-enable parity attentions on path 0 */
933 bnx2x_pretend_func(bp, 0);
934 bnx2x_clear_blocks_parity(bp);
935 bnx2x_enable_blocks_parity(bp);
936
937 /* Re-enable parity attentions on path 1 */
938 bnx2x_pretend_func(bp, 1);
939 bnx2x_clear_blocks_parity(bp);
940 bnx2x_enable_blocks_parity(bp);
941
942 /* Return to current function */
943 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
944 }
945
946 static int bnx2x_get_preset_regs_len(struct net_device *dev, u32 preset)
947 {
948 struct bnx2x *bp = netdev_priv(dev);
949 int regdump_len = 0;
950
951 regdump_len = __bnx2x_get_preset_regs_len(bp, preset);
952 regdump_len *= 4;
953 regdump_len += sizeof(struct dump_header);
954
955 return regdump_len;
956 }
957
958 static int bnx2x_set_dump(struct net_device *dev, struct ethtool_dump *val)
959 {
960 struct bnx2x *bp = netdev_priv(dev);
961
962 /* Use the ethtool_dump "flag" field as the dump preset index */
963 bp->dump_preset_idx = val->flag;
964 return 0;
965 }
966
967 static int bnx2x_get_dump_flag(struct net_device *dev,
968 struct ethtool_dump *dump)
969 {
970 struct bnx2x *bp = netdev_priv(dev);
971
972 /* Calculate the requested preset idx length */
973 dump->len = bnx2x_get_preset_regs_len(dev, bp->dump_preset_idx);
974 DP(BNX2X_MSG_ETHTOOL, "Get dump preset %d length=%d\n",
975 bp->dump_preset_idx, dump->len);
976
977 dump->flag = ETHTOOL_GET_DUMP_DATA;
978 return 0;
979 }
980
981 static int bnx2x_get_dump_data(struct net_device *dev,
982 struct ethtool_dump *dump,
983 void *buffer)
984 {
985 u32 *p = buffer;
986 struct bnx2x *bp = netdev_priv(dev);
987 struct dump_header dump_hdr = {0};
988
989 memset(p, 0, dump->len);
990
991 /* Disable parity attentions as long as following dump may
992 * cause false alarms by reading never written registers. We
993 * will re-enable parity attentions right after the dump.
994 */
995
996 /* Disable parity on path 0 */
997 bnx2x_pretend_func(bp, 0);
998 bnx2x_disable_blocks_parity(bp);
999
1000 /* Disable parity on path 1 */
1001 bnx2x_pretend_func(bp, 1);
1002 bnx2x_disable_blocks_parity(bp);
1003
1004 /* Return to current function */
1005 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1006
1007 dump_hdr.header_size = (sizeof(struct dump_header) / 4) - 1;
1008 dump_hdr.preset = bp->dump_preset_idx;
1009 dump_hdr.version = BNX2X_DUMP_VERSION;
1010
1011 DP(BNX2X_MSG_ETHTOOL, "Get dump data of preset %d\n", dump_hdr.preset);
1012
1013 /* dump_meta_data presents OR of CHIP and PATH. */
1014 if (CHIP_IS_E1(bp)) {
1015 dump_hdr.dump_meta_data = DUMP_CHIP_E1;
1016 } else if (CHIP_IS_E1H(bp)) {
1017 dump_hdr.dump_meta_data = DUMP_CHIP_E1H;
1018 } else if (CHIP_IS_E2(bp)) {
1019 dump_hdr.dump_meta_data = DUMP_CHIP_E2 |
1020 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1021 } else if (CHIP_IS_E3A0(bp)) {
1022 dump_hdr.dump_meta_data = DUMP_CHIP_E3A0 |
1023 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1024 } else if (CHIP_IS_E3B0(bp)) {
1025 dump_hdr.dump_meta_data = DUMP_CHIP_E3B0 |
1026 (BP_PATH(bp) ? DUMP_PATH_1 : DUMP_PATH_0);
1027 }
1028
1029 memcpy(p, &dump_hdr, sizeof(struct dump_header));
1030 p += dump_hdr.header_size + 1;
1031
1032 /* Actually read the registers */
1033 __bnx2x_get_preset_regs(bp, p, dump_hdr.preset);
1034
1035 /* Re-enable parity attentions on path 0 */
1036 bnx2x_pretend_func(bp, 0);
1037 bnx2x_clear_blocks_parity(bp);
1038 bnx2x_enable_blocks_parity(bp);
1039
1040 /* Re-enable parity attentions on path 1 */
1041 bnx2x_pretend_func(bp, 1);
1042 bnx2x_clear_blocks_parity(bp);
1043 bnx2x_enable_blocks_parity(bp);
1044
1045 /* Return to current function */
1046 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
1047
1048 return 0;
1049 }
1050
1051 static void bnx2x_get_drvinfo(struct net_device *dev,
1052 struct ethtool_drvinfo *info)
1053 {
1054 struct bnx2x *bp = netdev_priv(dev);
1055
1056 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
1057 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version));
1058
1059 bnx2x_fill_fw_str(bp, info->fw_version, sizeof(info->fw_version));
1060
1061 strlcpy(info->bus_info, pci_name(bp->pdev), sizeof(info->bus_info));
1062 info->n_stats = BNX2X_NUM_STATS;
1063 info->testinfo_len = BNX2X_NUM_TESTS(bp);
1064 info->eedump_len = bp->common.flash_size;
1065 info->regdump_len = bnx2x_get_regs_len(dev);
1066 }
1067
1068 static void bnx2x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1069 {
1070 struct bnx2x *bp = netdev_priv(dev);
1071
1072 if (bp->flags & NO_WOL_FLAG) {
1073 wol->supported = 0;
1074 wol->wolopts = 0;
1075 } else {
1076 wol->supported = WAKE_MAGIC;
1077 if (bp->wol)
1078 wol->wolopts = WAKE_MAGIC;
1079 else
1080 wol->wolopts = 0;
1081 }
1082 memset(&wol->sopass, 0, sizeof(wol->sopass));
1083 }
1084
1085 static int bnx2x_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1086 {
1087 struct bnx2x *bp = netdev_priv(dev);
1088
1089 if (wol->wolopts & ~WAKE_MAGIC) {
1090 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1091 return -EINVAL;
1092 }
1093
1094 if (wol->wolopts & WAKE_MAGIC) {
1095 if (bp->flags & NO_WOL_FLAG) {
1096 DP(BNX2X_MSG_ETHTOOL, "WOL not supported\n");
1097 return -EINVAL;
1098 }
1099 bp->wol = 1;
1100 } else
1101 bp->wol = 0;
1102
1103 return 0;
1104 }
1105
1106 static u32 bnx2x_get_msglevel(struct net_device *dev)
1107 {
1108 struct bnx2x *bp = netdev_priv(dev);
1109
1110 return bp->msg_enable;
1111 }
1112
1113 static void bnx2x_set_msglevel(struct net_device *dev, u32 level)
1114 {
1115 struct bnx2x *bp = netdev_priv(dev);
1116
1117 if (capable(CAP_NET_ADMIN)) {
1118 /* dump MCP trace */
1119 if (IS_PF(bp) && (level & BNX2X_MSG_MCP))
1120 bnx2x_fw_dump_lvl(bp, KERN_INFO);
1121 bp->msg_enable = level;
1122 }
1123 }
1124
1125 static int bnx2x_nway_reset(struct net_device *dev)
1126 {
1127 struct bnx2x *bp = netdev_priv(dev);
1128
1129 if (!bp->port.pmf)
1130 return 0;
1131
1132 if (netif_running(dev)) {
1133 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1134 bnx2x_force_link_reset(bp);
1135 bnx2x_link_set(bp);
1136 }
1137
1138 return 0;
1139 }
1140
1141 static u32 bnx2x_get_link(struct net_device *dev)
1142 {
1143 struct bnx2x *bp = netdev_priv(dev);
1144
1145 if (bp->flags & MF_FUNC_DIS || (bp->state != BNX2X_STATE_OPEN))
1146 return 0;
1147
1148 return bp->link_vars.link_up;
1149 }
1150
1151 static int bnx2x_get_eeprom_len(struct net_device *dev)
1152 {
1153 struct bnx2x *bp = netdev_priv(dev);
1154
1155 return bp->common.flash_size;
1156 }
1157
1158 /* Per pf misc lock must be aquired before the per port mcp lock. Otherwise, had
1159 * we done things the other way around, if two pfs from the same port would
1160 * attempt to access nvram at the same time, we could run into a scenario such
1161 * as:
1162 * pf A takes the port lock.
1163 * pf B succeeds in taking the same lock since they are from the same port.
1164 * pf A takes the per pf misc lock. Performs eeprom access.
1165 * pf A finishes. Unlocks the per pf misc lock.
1166 * Pf B takes the lock and proceeds to perform it's own access.
1167 * pf A unlocks the per port lock, while pf B is still working (!).
1168 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own
1169 * access corrupted by pf B)
1170 */
1171 static int bnx2x_acquire_nvram_lock(struct bnx2x *bp)
1172 {
1173 int port = BP_PORT(bp);
1174 int count, i;
1175 u32 val;
1176
1177 /* acquire HW lock: protect against other PFs in PF Direct Assignment */
1178 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1179
1180 /* adjust timeout for emulation/FPGA */
1181 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1182 if (CHIP_REV_IS_SLOW(bp))
1183 count *= 100;
1184
1185 /* request access to nvram interface */
1186 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1187 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port));
1188
1189 for (i = 0; i < count*10; i++) {
1190 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1191 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))
1192 break;
1193
1194 udelay(5);
1195 }
1196
1197 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) {
1198 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1199 "cannot get access to nvram interface\n");
1200 return -EBUSY;
1201 }
1202
1203 return 0;
1204 }
1205
1206 static int bnx2x_release_nvram_lock(struct bnx2x *bp)
1207 {
1208 int port = BP_PORT(bp);
1209 int count, i;
1210 u32 val;
1211
1212 /* adjust timeout for emulation/FPGA */
1213 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1214 if (CHIP_REV_IS_SLOW(bp))
1215 count *= 100;
1216
1217 /* relinquish nvram interface */
1218 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
1219 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port));
1220
1221 for (i = 0; i < count*10; i++) {
1222 val = REG_RD(bp, MCP_REG_MCPR_NVM_SW_ARB);
1223 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)))
1224 break;
1225
1226 udelay(5);
1227 }
1228
1229 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) {
1230 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1231 "cannot free access to nvram interface\n");
1232 return -EBUSY;
1233 }
1234
1235 /* release HW lock: protect against other PFs in PF Direct Assignment */
1236 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_NVRAM);
1237 return 0;
1238 }
1239
1240 static void bnx2x_enable_nvram_access(struct bnx2x *bp)
1241 {
1242 u32 val;
1243
1244 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1245
1246 /* enable both bits, even on read */
1247 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1248 (val | MCPR_NVM_ACCESS_ENABLE_EN |
1249 MCPR_NVM_ACCESS_ENABLE_WR_EN));
1250 }
1251
1252 static void bnx2x_disable_nvram_access(struct bnx2x *bp)
1253 {
1254 u32 val;
1255
1256 val = REG_RD(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE);
1257
1258 /* disable both bits, even after read */
1259 REG_WR(bp, MCP_REG_MCPR_NVM_ACCESS_ENABLE,
1260 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN |
1261 MCPR_NVM_ACCESS_ENABLE_WR_EN)));
1262 }
1263
1264 static int bnx2x_nvram_read_dword(struct bnx2x *bp, u32 offset, __be32 *ret_val,
1265 u32 cmd_flags)
1266 {
1267 int count, i, rc;
1268 u32 val;
1269
1270 /* build the command word */
1271 cmd_flags |= MCPR_NVM_COMMAND_DOIT;
1272
1273 /* need to clear DONE bit separately */
1274 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1275
1276 /* address of the NVRAM to read from */
1277 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1278 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1279
1280 /* issue a read command */
1281 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1282
1283 /* adjust timeout for emulation/FPGA */
1284 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1285 if (CHIP_REV_IS_SLOW(bp))
1286 count *= 100;
1287
1288 /* wait for completion */
1289 *ret_val = 0;
1290 rc = -EBUSY;
1291 for (i = 0; i < count; i++) {
1292 udelay(5);
1293 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1294
1295 if (val & MCPR_NVM_COMMAND_DONE) {
1296 val = REG_RD(bp, MCP_REG_MCPR_NVM_READ);
1297 /* we read nvram data in cpu order
1298 * but ethtool sees it as an array of bytes
1299 * converting to big-endian will do the work
1300 */
1301 *ret_val = cpu_to_be32(val);
1302 rc = 0;
1303 break;
1304 }
1305 }
1306 if (rc == -EBUSY)
1307 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1308 "nvram read timeout expired\n");
1309 return rc;
1310 }
1311
1312 static int bnx2x_nvram_read(struct bnx2x *bp, u32 offset, u8 *ret_buf,
1313 int buf_size)
1314 {
1315 int rc;
1316 u32 cmd_flags;
1317 __be32 val;
1318
1319 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1320 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1321 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1322 offset, buf_size);
1323 return -EINVAL;
1324 }
1325
1326 if (offset + buf_size > bp->common.flash_size) {
1327 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1328 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1329 offset, buf_size, bp->common.flash_size);
1330 return -EINVAL;
1331 }
1332
1333 /* request access to nvram interface */
1334 rc = bnx2x_acquire_nvram_lock(bp);
1335 if (rc)
1336 return rc;
1337
1338 /* enable access to nvram interface */
1339 bnx2x_enable_nvram_access(bp);
1340
1341 /* read the first word(s) */
1342 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1343 while ((buf_size > sizeof(u32)) && (rc == 0)) {
1344 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1345 memcpy(ret_buf, &val, 4);
1346
1347 /* advance to the next dword */
1348 offset += sizeof(u32);
1349 ret_buf += sizeof(u32);
1350 buf_size -= sizeof(u32);
1351 cmd_flags = 0;
1352 }
1353
1354 if (rc == 0) {
1355 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1356 rc = bnx2x_nvram_read_dword(bp, offset, &val, cmd_flags);
1357 memcpy(ret_buf, &val, 4);
1358 }
1359
1360 /* disable access to nvram interface */
1361 bnx2x_disable_nvram_access(bp);
1362 bnx2x_release_nvram_lock(bp);
1363
1364 return rc;
1365 }
1366
1367 static int bnx2x_nvram_read32(struct bnx2x *bp, u32 offset, u32 *buf,
1368 int buf_size)
1369 {
1370 int rc;
1371
1372 rc = bnx2x_nvram_read(bp, offset, (u8 *)buf, buf_size);
1373
1374 if (!rc) {
1375 __be32 *be = (__be32 *)buf;
1376
1377 while ((buf_size -= 4) >= 0)
1378 *buf++ = be32_to_cpu(*be++);
1379 }
1380
1381 return rc;
1382 }
1383
1384 static bool bnx2x_is_nvm_accessible(struct bnx2x *bp)
1385 {
1386 int rc = 1;
1387 u16 pm = 0;
1388 struct net_device *dev = pci_get_drvdata(bp->pdev);
1389
1390 if (bp->pm_cap)
1391 rc = pci_read_config_word(bp->pdev,
1392 bp->pm_cap + PCI_PM_CTRL, &pm);
1393
1394 if ((rc && !netif_running(dev)) || (!rc && ((pm & PCI_D0) != PCI_D0)))
1395 return false;
1396
1397 return true;
1398 }
1399
1400 static int bnx2x_get_eeprom(struct net_device *dev,
1401 struct ethtool_eeprom *eeprom, u8 *eebuf)
1402 {
1403 struct bnx2x *bp = netdev_priv(dev);
1404
1405 if (!bnx2x_is_nvm_accessible(bp)) {
1406 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1407 "cannot access eeprom when the interface is down\n");
1408 return -EAGAIN;
1409 }
1410
1411 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1412 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1413 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1414 eeprom->len, eeprom->len);
1415
1416 /* parameters already validated in ethtool_get_eeprom */
1417
1418 return bnx2x_nvram_read(bp, eeprom->offset, eebuf, eeprom->len);
1419 }
1420
1421 static int bnx2x_get_module_eeprom(struct net_device *dev,
1422 struct ethtool_eeprom *ee,
1423 u8 *data)
1424 {
1425 struct bnx2x *bp = netdev_priv(dev);
1426 int rc = -EINVAL, phy_idx;
1427 u8 *user_data = data;
1428 unsigned int start_addr = ee->offset, xfer_size = 0;
1429
1430 if (!bnx2x_is_nvm_accessible(bp)) {
1431 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1432 "cannot access eeprom when the interface is down\n");
1433 return -EAGAIN;
1434 }
1435
1436 phy_idx = bnx2x_get_cur_phy_idx(bp);
1437
1438 /* Read A0 section */
1439 if (start_addr < ETH_MODULE_SFF_8079_LEN) {
1440 /* Limit transfer size to the A0 section boundary */
1441 if (start_addr + ee->len > ETH_MODULE_SFF_8079_LEN)
1442 xfer_size = ETH_MODULE_SFF_8079_LEN - start_addr;
1443 else
1444 xfer_size = ee->len;
1445 bnx2x_acquire_phy_lock(bp);
1446 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1447 &bp->link_params,
1448 I2C_DEV_ADDR_A0,
1449 start_addr,
1450 xfer_size,
1451 user_data);
1452 bnx2x_release_phy_lock(bp);
1453 if (rc) {
1454 DP(BNX2X_MSG_ETHTOOL, "Failed reading A0 section\n");
1455
1456 return -EINVAL;
1457 }
1458 user_data += xfer_size;
1459 start_addr += xfer_size;
1460 }
1461
1462 /* Read A2 section */
1463 if ((start_addr >= ETH_MODULE_SFF_8079_LEN) &&
1464 (start_addr < ETH_MODULE_SFF_8472_LEN)) {
1465 xfer_size = ee->len - xfer_size;
1466 /* Limit transfer size to the A2 section boundary */
1467 if (start_addr + xfer_size > ETH_MODULE_SFF_8472_LEN)
1468 xfer_size = ETH_MODULE_SFF_8472_LEN - start_addr;
1469 start_addr -= ETH_MODULE_SFF_8079_LEN;
1470 bnx2x_acquire_phy_lock(bp);
1471 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1472 &bp->link_params,
1473 I2C_DEV_ADDR_A2,
1474 start_addr,
1475 xfer_size,
1476 user_data);
1477 bnx2x_release_phy_lock(bp);
1478 if (rc) {
1479 DP(BNX2X_MSG_ETHTOOL, "Failed reading A2 section\n");
1480 return -EINVAL;
1481 }
1482 }
1483 return rc;
1484 }
1485
1486 static int bnx2x_get_module_info(struct net_device *dev,
1487 struct ethtool_modinfo *modinfo)
1488 {
1489 struct bnx2x *bp = netdev_priv(dev);
1490 int phy_idx, rc;
1491 u8 sff8472_comp, diag_type;
1492
1493 if (!bnx2x_is_nvm_accessible(bp)) {
1494 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1495 "cannot access eeprom when the interface is down\n");
1496 return -EAGAIN;
1497 }
1498 phy_idx = bnx2x_get_cur_phy_idx(bp);
1499 bnx2x_acquire_phy_lock(bp);
1500 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1501 &bp->link_params,
1502 I2C_DEV_ADDR_A0,
1503 SFP_EEPROM_SFF_8472_COMP_ADDR,
1504 SFP_EEPROM_SFF_8472_COMP_SIZE,
1505 &sff8472_comp);
1506 bnx2x_release_phy_lock(bp);
1507 if (rc) {
1508 DP(BNX2X_MSG_ETHTOOL, "Failed reading SFF-8472 comp field\n");
1509 return -EINVAL;
1510 }
1511
1512 bnx2x_acquire_phy_lock(bp);
1513 rc = bnx2x_read_sfp_module_eeprom(&bp->link_params.phy[phy_idx],
1514 &bp->link_params,
1515 I2C_DEV_ADDR_A0,
1516 SFP_EEPROM_DIAG_TYPE_ADDR,
1517 SFP_EEPROM_DIAG_TYPE_SIZE,
1518 &diag_type);
1519 bnx2x_release_phy_lock(bp);
1520 if (rc) {
1521 DP(BNX2X_MSG_ETHTOOL, "Failed reading Diag Type field\n");
1522 return -EINVAL;
1523 }
1524
1525 if (!sff8472_comp ||
1526 (diag_type & SFP_EEPROM_DIAG_ADDR_CHANGE_REQ)) {
1527 modinfo->type = ETH_MODULE_SFF_8079;
1528 modinfo->eeprom_len = ETH_MODULE_SFF_8079_LEN;
1529 } else {
1530 modinfo->type = ETH_MODULE_SFF_8472;
1531 modinfo->eeprom_len = ETH_MODULE_SFF_8472_LEN;
1532 }
1533 return 0;
1534 }
1535
1536 static int bnx2x_nvram_write_dword(struct bnx2x *bp, u32 offset, u32 val,
1537 u32 cmd_flags)
1538 {
1539 int count, i, rc;
1540
1541 /* build the command word */
1542 cmd_flags |= MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR;
1543
1544 /* need to clear DONE bit separately */
1545 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
1546
1547 /* write the data */
1548 REG_WR(bp, MCP_REG_MCPR_NVM_WRITE, val);
1549
1550 /* address of the NVRAM to write to */
1551 REG_WR(bp, MCP_REG_MCPR_NVM_ADDR,
1552 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE));
1553
1554 /* issue the write command */
1555 REG_WR(bp, MCP_REG_MCPR_NVM_COMMAND, cmd_flags);
1556
1557 /* adjust timeout for emulation/FPGA */
1558 count = BNX2X_NVRAM_TIMEOUT_COUNT;
1559 if (CHIP_REV_IS_SLOW(bp))
1560 count *= 100;
1561
1562 /* wait for completion */
1563 rc = -EBUSY;
1564 for (i = 0; i < count; i++) {
1565 udelay(5);
1566 val = REG_RD(bp, MCP_REG_MCPR_NVM_COMMAND);
1567 if (val & MCPR_NVM_COMMAND_DONE) {
1568 rc = 0;
1569 break;
1570 }
1571 }
1572
1573 if (rc == -EBUSY)
1574 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1575 "nvram write timeout expired\n");
1576 return rc;
1577 }
1578
1579 #define BYTE_OFFSET(offset) (8 * (offset & 0x03))
1580
1581 static int bnx2x_nvram_write1(struct bnx2x *bp, u32 offset, u8 *data_buf,
1582 int buf_size)
1583 {
1584 int rc;
1585 u32 cmd_flags, align_offset, val;
1586 __be32 val_be;
1587
1588 if (offset + buf_size > bp->common.flash_size) {
1589 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1590 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1591 offset, buf_size, bp->common.flash_size);
1592 return -EINVAL;
1593 }
1594
1595 /* request access to nvram interface */
1596 rc = bnx2x_acquire_nvram_lock(bp);
1597 if (rc)
1598 return rc;
1599
1600 /* enable access to nvram interface */
1601 bnx2x_enable_nvram_access(bp);
1602
1603 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST);
1604 align_offset = (offset & ~0x03);
1605 rc = bnx2x_nvram_read_dword(bp, align_offset, &val_be, cmd_flags);
1606
1607 if (rc == 0) {
1608 /* nvram data is returned as an array of bytes
1609 * convert it back to cpu order
1610 */
1611 val = be32_to_cpu(val_be);
1612
1613 val &= ~le32_to_cpu(0xff << BYTE_OFFSET(offset));
1614 val |= le32_to_cpu(*data_buf << BYTE_OFFSET(offset));
1615
1616 rc = bnx2x_nvram_write_dword(bp, align_offset, val,
1617 cmd_flags);
1618 }
1619
1620 /* disable access to nvram interface */
1621 bnx2x_disable_nvram_access(bp);
1622 bnx2x_release_nvram_lock(bp);
1623
1624 return rc;
1625 }
1626
1627 static int bnx2x_nvram_write(struct bnx2x *bp, u32 offset, u8 *data_buf,
1628 int buf_size)
1629 {
1630 int rc;
1631 u32 cmd_flags;
1632 u32 val;
1633 u32 written_so_far;
1634
1635 if (buf_size == 1) /* ethtool */
1636 return bnx2x_nvram_write1(bp, offset, data_buf, buf_size);
1637
1638 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) {
1639 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1640 "Invalid parameter: offset 0x%x buf_size 0x%x\n",
1641 offset, buf_size);
1642 return -EINVAL;
1643 }
1644
1645 if (offset + buf_size > bp->common.flash_size) {
1646 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1647 "Invalid parameter: offset (0x%x) + buf_size (0x%x) > flash_size (0x%x)\n",
1648 offset, buf_size, bp->common.flash_size);
1649 return -EINVAL;
1650 }
1651
1652 /* request access to nvram interface */
1653 rc = bnx2x_acquire_nvram_lock(bp);
1654 if (rc)
1655 return rc;
1656
1657 /* enable access to nvram interface */
1658 bnx2x_enable_nvram_access(bp);
1659
1660 written_so_far = 0;
1661 cmd_flags = MCPR_NVM_COMMAND_FIRST;
1662 while ((written_so_far < buf_size) && (rc == 0)) {
1663 if (written_so_far == (buf_size - sizeof(u32)))
1664 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1665 else if (((offset + 4) % BNX2X_NVRAM_PAGE_SIZE) == 0)
1666 cmd_flags |= MCPR_NVM_COMMAND_LAST;
1667 else if ((offset % BNX2X_NVRAM_PAGE_SIZE) == 0)
1668 cmd_flags |= MCPR_NVM_COMMAND_FIRST;
1669
1670 memcpy(&val, data_buf, 4);
1671
1672 rc = bnx2x_nvram_write_dword(bp, offset, val, cmd_flags);
1673
1674 /* advance to the next dword */
1675 offset += sizeof(u32);
1676 data_buf += sizeof(u32);
1677 written_so_far += sizeof(u32);
1678 cmd_flags = 0;
1679 }
1680
1681 /* disable access to nvram interface */
1682 bnx2x_disable_nvram_access(bp);
1683 bnx2x_release_nvram_lock(bp);
1684
1685 return rc;
1686 }
1687
1688 static int bnx2x_set_eeprom(struct net_device *dev,
1689 struct ethtool_eeprom *eeprom, u8 *eebuf)
1690 {
1691 struct bnx2x *bp = netdev_priv(dev);
1692 int port = BP_PORT(bp);
1693 int rc = 0;
1694 u32 ext_phy_config;
1695
1696 if (!bnx2x_is_nvm_accessible(bp)) {
1697 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1698 "cannot access eeprom when the interface is down\n");
1699 return -EAGAIN;
1700 }
1701
1702 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "ethtool_eeprom: cmd %d\n"
1703 " magic 0x%x offset 0x%x (%d) len 0x%x (%d)\n",
1704 eeprom->cmd, eeprom->magic, eeprom->offset, eeprom->offset,
1705 eeprom->len, eeprom->len);
1706
1707 /* parameters already validated in ethtool_set_eeprom */
1708
1709 /* PHY eeprom can be accessed only by the PMF */
1710 if ((eeprom->magic >= 0x50485900) && (eeprom->magic <= 0x504859FF) &&
1711 !bp->port.pmf) {
1712 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
1713 "wrong magic or interface is not pmf\n");
1714 return -EINVAL;
1715 }
1716
1717 ext_phy_config =
1718 SHMEM_RD(bp,
1719 dev_info.port_hw_config[port].external_phy_config);
1720
1721 if (eeprom->magic == 0x50485950) {
1722 /* 'PHYP' (0x50485950): prepare phy for FW upgrade */
1723 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1724
1725 bnx2x_acquire_phy_lock(bp);
1726 rc |= bnx2x_link_reset(&bp->link_params,
1727 &bp->link_vars, 0);
1728 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1729 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101)
1730 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1731 MISC_REGISTERS_GPIO_HIGH, port);
1732 bnx2x_release_phy_lock(bp);
1733 bnx2x_link_report(bp);
1734
1735 } else if (eeprom->magic == 0x50485952) {
1736 /* 'PHYR' (0x50485952): re-init link after FW upgrade */
1737 if (bp->state == BNX2X_STATE_OPEN) {
1738 bnx2x_acquire_phy_lock(bp);
1739 rc |= bnx2x_link_reset(&bp->link_params,
1740 &bp->link_vars, 1);
1741
1742 rc |= bnx2x_phy_init(&bp->link_params,
1743 &bp->link_vars);
1744 bnx2x_release_phy_lock(bp);
1745 bnx2x_calc_fc_adv(bp);
1746 }
1747 } else if (eeprom->magic == 0x53985943) {
1748 /* 'PHYC' (0x53985943): PHY FW upgrade completed */
1749 if (XGXS_EXT_PHY_TYPE(ext_phy_config) ==
1750 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101) {
1751
1752 /* DSP Remove Download Mode */
1753 bnx2x_set_gpio(bp, MISC_REGISTERS_GPIO_0,
1754 MISC_REGISTERS_GPIO_LOW, port);
1755
1756 bnx2x_acquire_phy_lock(bp);
1757
1758 bnx2x_sfx7101_sp_sw_reset(bp,
1759 &bp->link_params.phy[EXT_PHY1]);
1760
1761 /* wait 0.5 sec to allow it to run */
1762 msleep(500);
1763 bnx2x_ext_phy_hw_reset(bp, port);
1764 msleep(500);
1765 bnx2x_release_phy_lock(bp);
1766 }
1767 } else
1768 rc = bnx2x_nvram_write(bp, eeprom->offset, eebuf, eeprom->len);
1769
1770 return rc;
1771 }
1772
1773 static int bnx2x_get_coalesce(struct net_device *dev,
1774 struct ethtool_coalesce *coal)
1775 {
1776 struct bnx2x *bp = netdev_priv(dev);
1777
1778 memset(coal, 0, sizeof(struct ethtool_coalesce));
1779
1780 coal->rx_coalesce_usecs = bp->rx_ticks;
1781 coal->tx_coalesce_usecs = bp->tx_ticks;
1782
1783 return 0;
1784 }
1785
1786 static int bnx2x_set_coalesce(struct net_device *dev,
1787 struct ethtool_coalesce *coal)
1788 {
1789 struct bnx2x *bp = netdev_priv(dev);
1790
1791 bp->rx_ticks = (u16)coal->rx_coalesce_usecs;
1792 if (bp->rx_ticks > BNX2X_MAX_COALESCE_TOUT)
1793 bp->rx_ticks = BNX2X_MAX_COALESCE_TOUT;
1794
1795 bp->tx_ticks = (u16)coal->tx_coalesce_usecs;
1796 if (bp->tx_ticks > BNX2X_MAX_COALESCE_TOUT)
1797 bp->tx_ticks = BNX2X_MAX_COALESCE_TOUT;
1798
1799 if (netif_running(dev))
1800 bnx2x_update_coalesce(bp);
1801
1802 return 0;
1803 }
1804
1805 static void bnx2x_get_ringparam(struct net_device *dev,
1806 struct ethtool_ringparam *ering)
1807 {
1808 struct bnx2x *bp = netdev_priv(dev);
1809
1810 ering->rx_max_pending = MAX_RX_AVAIL;
1811
1812 if (bp->rx_ring_size)
1813 ering->rx_pending = bp->rx_ring_size;
1814 else
1815 ering->rx_pending = MAX_RX_AVAIL;
1816
1817 ering->tx_max_pending = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
1818 ering->tx_pending = bp->tx_ring_size;
1819 }
1820
1821 static int bnx2x_set_ringparam(struct net_device *dev,
1822 struct ethtool_ringparam *ering)
1823 {
1824 struct bnx2x *bp = netdev_priv(dev);
1825
1826 DP(BNX2X_MSG_ETHTOOL,
1827 "set ring params command parameters: rx_pending = %d, tx_pending = %d\n",
1828 ering->rx_pending, ering->tx_pending);
1829
1830 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
1831 DP(BNX2X_MSG_ETHTOOL,
1832 "Handling parity error recovery. Try again later\n");
1833 return -EAGAIN;
1834 }
1835
1836 if ((ering->rx_pending > MAX_RX_AVAIL) ||
1837 (ering->rx_pending < (bp->disable_tpa ? MIN_RX_SIZE_NONTPA :
1838 MIN_RX_SIZE_TPA)) ||
1839 (ering->tx_pending > (IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL)) ||
1840 (ering->tx_pending <= MAX_SKB_FRAGS + 4)) {
1841 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
1842 return -EINVAL;
1843 }
1844
1845 bp->rx_ring_size = ering->rx_pending;
1846 bp->tx_ring_size = ering->tx_pending;
1847
1848 return bnx2x_reload_if_running(dev);
1849 }
1850
1851 static void bnx2x_get_pauseparam(struct net_device *dev,
1852 struct ethtool_pauseparam *epause)
1853 {
1854 struct bnx2x *bp = netdev_priv(dev);
1855 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
1856 int cfg_reg;
1857
1858 epause->autoneg = (bp->link_params.req_flow_ctrl[cfg_idx] ==
1859 BNX2X_FLOW_CTRL_AUTO);
1860
1861 if (!epause->autoneg)
1862 cfg_reg = bp->link_params.req_flow_ctrl[cfg_idx];
1863 else
1864 cfg_reg = bp->link_params.req_fc_auto_adv;
1865
1866 epause->rx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_RX) ==
1867 BNX2X_FLOW_CTRL_RX);
1868 epause->tx_pause = ((cfg_reg & BNX2X_FLOW_CTRL_TX) ==
1869 BNX2X_FLOW_CTRL_TX);
1870
1871 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1872 " autoneg %d rx_pause %d tx_pause %d\n",
1873 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1874 }
1875
1876 static int bnx2x_set_pauseparam(struct net_device *dev,
1877 struct ethtool_pauseparam *epause)
1878 {
1879 struct bnx2x *bp = netdev_priv(dev);
1880 u32 cfg_idx = bnx2x_get_link_cfg_idx(bp);
1881 if (IS_MF(bp))
1882 return 0;
1883
1884 DP(BNX2X_MSG_ETHTOOL, "ethtool_pauseparam: cmd %d\n"
1885 " autoneg %d rx_pause %d tx_pause %d\n",
1886 epause->cmd, epause->autoneg, epause->rx_pause, epause->tx_pause);
1887
1888 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_AUTO;
1889
1890 if (epause->rx_pause)
1891 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_RX;
1892
1893 if (epause->tx_pause)
1894 bp->link_params.req_flow_ctrl[cfg_idx] |= BNX2X_FLOW_CTRL_TX;
1895
1896 if (bp->link_params.req_flow_ctrl[cfg_idx] == BNX2X_FLOW_CTRL_AUTO)
1897 bp->link_params.req_flow_ctrl[cfg_idx] = BNX2X_FLOW_CTRL_NONE;
1898
1899 if (epause->autoneg) {
1900 if (!(bp->port.supported[cfg_idx] & SUPPORTED_Autoneg)) {
1901 DP(BNX2X_MSG_ETHTOOL, "autoneg not supported\n");
1902 return -EINVAL;
1903 }
1904
1905 if (bp->link_params.req_line_speed[cfg_idx] == SPEED_AUTO_NEG) {
1906 bp->link_params.req_flow_ctrl[cfg_idx] =
1907 BNX2X_FLOW_CTRL_AUTO;
1908 }
1909 bp->link_params.req_fc_auto_adv = 0;
1910 if (epause->rx_pause)
1911 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_RX;
1912
1913 if (epause->tx_pause)
1914 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_TX;
1915
1916 if (!bp->link_params.req_fc_auto_adv)
1917 bp->link_params.req_fc_auto_adv |= BNX2X_FLOW_CTRL_NONE;
1918 }
1919
1920 DP(BNX2X_MSG_ETHTOOL,
1921 "req_flow_ctrl 0x%x\n", bp->link_params.req_flow_ctrl[cfg_idx]);
1922
1923 if (netif_running(dev)) {
1924 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
1925 bnx2x_link_set(bp);
1926 }
1927
1928 return 0;
1929 }
1930
1931 static const char bnx2x_tests_str_arr[BNX2X_NUM_TESTS_SF][ETH_GSTRING_LEN] = {
1932 "register_test (offline) ",
1933 "memory_test (offline) ",
1934 "int_loopback_test (offline)",
1935 "ext_loopback_test (offline)",
1936 "nvram_test (online) ",
1937 "interrupt_test (online) ",
1938 "link_test (online) "
1939 };
1940
1941 enum {
1942 BNX2X_PRI_FLAG_ISCSI,
1943 BNX2X_PRI_FLAG_FCOE,
1944 BNX2X_PRI_FLAG_STORAGE,
1945 BNX2X_PRI_FLAG_LEN,
1946 };
1947
1948 static const char bnx2x_private_arr[BNX2X_PRI_FLAG_LEN][ETH_GSTRING_LEN] = {
1949 "iSCSI offload support",
1950 "FCoE offload support",
1951 "Storage only interface"
1952 };
1953
1954 static u32 bnx2x_eee_to_adv(u32 eee_adv)
1955 {
1956 u32 modes = 0;
1957
1958 if (eee_adv & SHMEM_EEE_100M_ADV)
1959 modes |= ADVERTISED_100baseT_Full;
1960 if (eee_adv & SHMEM_EEE_1G_ADV)
1961 modes |= ADVERTISED_1000baseT_Full;
1962 if (eee_adv & SHMEM_EEE_10G_ADV)
1963 modes |= ADVERTISED_10000baseT_Full;
1964
1965 return modes;
1966 }
1967
1968 static u32 bnx2x_adv_to_eee(u32 modes, u32 shift)
1969 {
1970 u32 eee_adv = 0;
1971 if (modes & ADVERTISED_100baseT_Full)
1972 eee_adv |= SHMEM_EEE_100M_ADV;
1973 if (modes & ADVERTISED_1000baseT_Full)
1974 eee_adv |= SHMEM_EEE_1G_ADV;
1975 if (modes & ADVERTISED_10000baseT_Full)
1976 eee_adv |= SHMEM_EEE_10G_ADV;
1977
1978 return eee_adv << shift;
1979 }
1980
1981 static int bnx2x_get_eee(struct net_device *dev, struct ethtool_eee *edata)
1982 {
1983 struct bnx2x *bp = netdev_priv(dev);
1984 u32 eee_cfg;
1985
1986 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
1987 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
1988 return -EOPNOTSUPP;
1989 }
1990
1991 eee_cfg = bp->link_vars.eee_status;
1992
1993 edata->supported =
1994 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_SUPPORTED_MASK) >>
1995 SHMEM_EEE_SUPPORTED_SHIFT);
1996
1997 edata->advertised =
1998 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_ADV_STATUS_MASK) >>
1999 SHMEM_EEE_ADV_STATUS_SHIFT);
2000 edata->lp_advertised =
2001 bnx2x_eee_to_adv((eee_cfg & SHMEM_EEE_LP_ADV_STATUS_MASK) >>
2002 SHMEM_EEE_LP_ADV_STATUS_SHIFT);
2003
2004 /* SHMEM value is in 16u units --> Convert to 1u units. */
2005 edata->tx_lpi_timer = (eee_cfg & SHMEM_EEE_TIMER_MASK) << 4;
2006
2007 edata->eee_enabled = (eee_cfg & SHMEM_EEE_REQUESTED_BIT) ? 1 : 0;
2008 edata->eee_active = (eee_cfg & SHMEM_EEE_ACTIVE_BIT) ? 1 : 0;
2009 edata->tx_lpi_enabled = (eee_cfg & SHMEM_EEE_LPI_REQUESTED_BIT) ? 1 : 0;
2010
2011 return 0;
2012 }
2013
2014 static int bnx2x_set_eee(struct net_device *dev, struct ethtool_eee *edata)
2015 {
2016 struct bnx2x *bp = netdev_priv(dev);
2017 u32 eee_cfg;
2018 u32 advertised;
2019
2020 if (IS_MF(bp))
2021 return 0;
2022
2023 if (!SHMEM2_HAS(bp, eee_status[BP_PORT(bp)])) {
2024 DP(BNX2X_MSG_ETHTOOL, "BC Version does not support EEE\n");
2025 return -EOPNOTSUPP;
2026 }
2027
2028 eee_cfg = bp->link_vars.eee_status;
2029
2030 if (!(eee_cfg & SHMEM_EEE_SUPPORTED_MASK)) {
2031 DP(BNX2X_MSG_ETHTOOL, "Board does not support EEE!\n");
2032 return -EOPNOTSUPP;
2033 }
2034
2035 advertised = bnx2x_adv_to_eee(edata->advertised,
2036 SHMEM_EEE_ADV_STATUS_SHIFT);
2037 if ((advertised != (eee_cfg & SHMEM_EEE_ADV_STATUS_MASK))) {
2038 DP(BNX2X_MSG_ETHTOOL,
2039 "Direct manipulation of EEE advertisement is not supported\n");
2040 return -EINVAL;
2041 }
2042
2043 if (edata->tx_lpi_timer > EEE_MODE_TIMER_MASK) {
2044 DP(BNX2X_MSG_ETHTOOL,
2045 "Maximal Tx Lpi timer supported is %x(u)\n",
2046 EEE_MODE_TIMER_MASK);
2047 return -EINVAL;
2048 }
2049 if (edata->tx_lpi_enabled &&
2050 (edata->tx_lpi_timer < EEE_MODE_NVRAM_AGGRESSIVE_TIME)) {
2051 DP(BNX2X_MSG_ETHTOOL,
2052 "Minimal Tx Lpi timer supported is %d(u)\n",
2053 EEE_MODE_NVRAM_AGGRESSIVE_TIME);
2054 return -EINVAL;
2055 }
2056
2057 /* All is well; Apply changes*/
2058 if (edata->eee_enabled)
2059 bp->link_params.eee_mode |= EEE_MODE_ADV_LPI;
2060 else
2061 bp->link_params.eee_mode &= ~EEE_MODE_ADV_LPI;
2062
2063 if (edata->tx_lpi_enabled)
2064 bp->link_params.eee_mode |= EEE_MODE_ENABLE_LPI;
2065 else
2066 bp->link_params.eee_mode &= ~EEE_MODE_ENABLE_LPI;
2067
2068 bp->link_params.eee_mode &= ~EEE_MODE_TIMER_MASK;
2069 bp->link_params.eee_mode |= (edata->tx_lpi_timer &
2070 EEE_MODE_TIMER_MASK) |
2071 EEE_MODE_OVERRIDE_NVRAM |
2072 EEE_MODE_OUTPUT_TIME;
2073
2074 /* Restart link to propogate changes */
2075 if (netif_running(dev)) {
2076 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2077 bnx2x_force_link_reset(bp);
2078 bnx2x_link_set(bp);
2079 }
2080
2081 return 0;
2082 }
2083
2084 enum {
2085 BNX2X_CHIP_E1_OFST = 0,
2086 BNX2X_CHIP_E1H_OFST,
2087 BNX2X_CHIP_E2_OFST,
2088 BNX2X_CHIP_E3_OFST,
2089 BNX2X_CHIP_E3B0_OFST,
2090 BNX2X_CHIP_MAX_OFST
2091 };
2092
2093 #define BNX2X_CHIP_MASK_E1 (1 << BNX2X_CHIP_E1_OFST)
2094 #define BNX2X_CHIP_MASK_E1H (1 << BNX2X_CHIP_E1H_OFST)
2095 #define BNX2X_CHIP_MASK_E2 (1 << BNX2X_CHIP_E2_OFST)
2096 #define BNX2X_CHIP_MASK_E3 (1 << BNX2X_CHIP_E3_OFST)
2097 #define BNX2X_CHIP_MASK_E3B0 (1 << BNX2X_CHIP_E3B0_OFST)
2098
2099 #define BNX2X_CHIP_MASK_ALL ((1 << BNX2X_CHIP_MAX_OFST) - 1)
2100 #define BNX2X_CHIP_MASK_E1X (BNX2X_CHIP_MASK_E1 | BNX2X_CHIP_MASK_E1H)
2101
2102 static int bnx2x_test_registers(struct bnx2x *bp)
2103 {
2104 int idx, i, rc = -ENODEV;
2105 u32 wr_val = 0, hw;
2106 int port = BP_PORT(bp);
2107 static const struct {
2108 u32 hw;
2109 u32 offset0;
2110 u32 offset1;
2111 u32 mask;
2112 } reg_tbl[] = {
2113 /* 0 */ { BNX2X_CHIP_MASK_ALL,
2114 BRB1_REG_PAUSE_LOW_THRESHOLD_0, 4, 0x000003ff },
2115 { BNX2X_CHIP_MASK_ALL,
2116 DORQ_REG_DB_ADDR0, 4, 0xffffffff },
2117 { BNX2X_CHIP_MASK_E1X,
2118 HC_REG_AGG_INT_0, 4, 0x000003ff },
2119 { BNX2X_CHIP_MASK_ALL,
2120 PBF_REG_MAC_IF0_ENABLE, 4, 0x00000001 },
2121 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2 | BNX2X_CHIP_MASK_E3,
2122 PBF_REG_P0_INIT_CRD, 4, 0x000007ff },
2123 { BNX2X_CHIP_MASK_E3B0,
2124 PBF_REG_INIT_CRD_Q0, 4, 0x000007ff },
2125 { BNX2X_CHIP_MASK_ALL,
2126 PRS_REG_CID_PORT_0, 4, 0x00ffffff },
2127 { BNX2X_CHIP_MASK_ALL,
2128 PXP2_REG_PSWRQ_CDU0_L2P, 4, 0x000fffff },
2129 { BNX2X_CHIP_MASK_ALL,
2130 PXP2_REG_RQ_CDU0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2131 { BNX2X_CHIP_MASK_ALL,
2132 PXP2_REG_PSWRQ_TM0_L2P, 4, 0x000fffff },
2133 /* 10 */ { BNX2X_CHIP_MASK_ALL,
2134 PXP2_REG_RQ_USDM0_EFIRST_MEM_ADDR, 8, 0x0003ffff },
2135 { BNX2X_CHIP_MASK_ALL,
2136 PXP2_REG_PSWRQ_TSDM0_L2P, 4, 0x000fffff },
2137 { BNX2X_CHIP_MASK_ALL,
2138 QM_REG_CONNNUM_0, 4, 0x000fffff },
2139 { BNX2X_CHIP_MASK_ALL,
2140 TM_REG_LIN0_MAX_ACTIVE_CID, 4, 0x0003ffff },
2141 { BNX2X_CHIP_MASK_ALL,
2142 SRC_REG_KEYRSS0_0, 40, 0xffffffff },
2143 { BNX2X_CHIP_MASK_ALL,
2144 SRC_REG_KEYRSS0_7, 40, 0xffffffff },
2145 { BNX2X_CHIP_MASK_ALL,
2146 XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 4, 0x00000001 },
2147 { BNX2X_CHIP_MASK_ALL,
2148 XCM_REG_WU_DA_CNT_CMD00, 4, 0x00000003 },
2149 { BNX2X_CHIP_MASK_ALL,
2150 XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 4, 0x000000ff },
2151 { BNX2X_CHIP_MASK_ALL,
2152 NIG_REG_LLH0_T_BIT, 4, 0x00000001 },
2153 /* 20 */ { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2154 NIG_REG_EMAC0_IN_EN, 4, 0x00000001 },
2155 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2156 NIG_REG_BMAC0_IN_EN, 4, 0x00000001 },
2157 { BNX2X_CHIP_MASK_ALL,
2158 NIG_REG_XCM0_OUT_EN, 4, 0x00000001 },
2159 { BNX2X_CHIP_MASK_ALL,
2160 NIG_REG_BRB0_OUT_EN, 4, 0x00000001 },
2161 { BNX2X_CHIP_MASK_ALL,
2162 NIG_REG_LLH0_XCM_MASK, 4, 0x00000007 },
2163 { BNX2X_CHIP_MASK_ALL,
2164 NIG_REG_LLH0_ACPI_PAT_6_LEN, 68, 0x000000ff },
2165 { BNX2X_CHIP_MASK_ALL,
2166 NIG_REG_LLH0_ACPI_PAT_0_CRC, 68, 0xffffffff },
2167 { BNX2X_CHIP_MASK_ALL,
2168 NIG_REG_LLH0_DEST_MAC_0_0, 160, 0xffffffff },
2169 { BNX2X_CHIP_MASK_ALL,
2170 NIG_REG_LLH0_DEST_IP_0_1, 160, 0xffffffff },
2171 { BNX2X_CHIP_MASK_ALL,
2172 NIG_REG_LLH0_IPV4_IPV6_0, 160, 0x00000001 },
2173 /* 30 */ { BNX2X_CHIP_MASK_ALL,
2174 NIG_REG_LLH0_DEST_UDP_0, 160, 0x0000ffff },
2175 { BNX2X_CHIP_MASK_ALL,
2176 NIG_REG_LLH0_DEST_TCP_0, 160, 0x0000ffff },
2177 { BNX2X_CHIP_MASK_ALL,
2178 NIG_REG_LLH0_VLAN_ID_0, 160, 0x00000fff },
2179 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2180 NIG_REG_XGXS_SERDES0_MODE_SEL, 4, 0x00000001 },
2181 { BNX2X_CHIP_MASK_ALL,
2182 NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0, 4, 0x00000001},
2183 { BNX2X_CHIP_MASK_ALL,
2184 NIG_REG_STATUS_INTERRUPT_PORT0, 4, 0x07ffffff },
2185 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2186 NIG_REG_XGXS0_CTRL_EXTREMOTEMDIOST, 24, 0x00000001 },
2187 { BNX2X_CHIP_MASK_E1X | BNX2X_CHIP_MASK_E2,
2188 NIG_REG_SERDES0_CTRL_PHY_ADDR, 16, 0x0000001f },
2189
2190 { BNX2X_CHIP_MASK_ALL, 0xffffffff, 0, 0x00000000 }
2191 };
2192
2193 if (!bnx2x_is_nvm_accessible(bp)) {
2194 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2195 "cannot access eeprom when the interface is down\n");
2196 return rc;
2197 }
2198
2199 if (CHIP_IS_E1(bp))
2200 hw = BNX2X_CHIP_MASK_E1;
2201 else if (CHIP_IS_E1H(bp))
2202 hw = BNX2X_CHIP_MASK_E1H;
2203 else if (CHIP_IS_E2(bp))
2204 hw = BNX2X_CHIP_MASK_E2;
2205 else if (CHIP_IS_E3B0(bp))
2206 hw = BNX2X_CHIP_MASK_E3B0;
2207 else /* e3 A0 */
2208 hw = BNX2X_CHIP_MASK_E3;
2209
2210 /* Repeat the test twice:
2211 * First by writing 0x00000000, second by writing 0xffffffff
2212 */
2213 for (idx = 0; idx < 2; idx++) {
2214
2215 switch (idx) {
2216 case 0:
2217 wr_val = 0;
2218 break;
2219 case 1:
2220 wr_val = 0xffffffff;
2221 break;
2222 }
2223
2224 for (i = 0; reg_tbl[i].offset0 != 0xffffffff; i++) {
2225 u32 offset, mask, save_val, val;
2226 if (!(hw & reg_tbl[i].hw))
2227 continue;
2228
2229 offset = reg_tbl[i].offset0 + port*reg_tbl[i].offset1;
2230 mask = reg_tbl[i].mask;
2231
2232 save_val = REG_RD(bp, offset);
2233
2234 REG_WR(bp, offset, wr_val & mask);
2235
2236 val = REG_RD(bp, offset);
2237
2238 /* Restore the original register's value */
2239 REG_WR(bp, offset, save_val);
2240
2241 /* verify value is as expected */
2242 if ((val & mask) != (wr_val & mask)) {
2243 DP(BNX2X_MSG_ETHTOOL,
2244 "offset 0x%x: val 0x%x != 0x%x mask 0x%x\n",
2245 offset, val, wr_val, mask);
2246 goto test_reg_exit;
2247 }
2248 }
2249 }
2250
2251 rc = 0;
2252
2253 test_reg_exit:
2254 return rc;
2255 }
2256
2257 static int bnx2x_test_memory(struct bnx2x *bp)
2258 {
2259 int i, j, rc = -ENODEV;
2260 u32 val, index;
2261 static const struct {
2262 u32 offset;
2263 int size;
2264 } mem_tbl[] = {
2265 { CCM_REG_XX_DESCR_TABLE, CCM_REG_XX_DESCR_TABLE_SIZE },
2266 { CFC_REG_ACTIVITY_COUNTER, CFC_REG_ACTIVITY_COUNTER_SIZE },
2267 { CFC_REG_LINK_LIST, CFC_REG_LINK_LIST_SIZE },
2268 { DMAE_REG_CMD_MEM, DMAE_REG_CMD_MEM_SIZE },
2269 { TCM_REG_XX_DESCR_TABLE, TCM_REG_XX_DESCR_TABLE_SIZE },
2270 { UCM_REG_XX_DESCR_TABLE, UCM_REG_XX_DESCR_TABLE_SIZE },
2271 { XCM_REG_XX_DESCR_TABLE, XCM_REG_XX_DESCR_TABLE_SIZE },
2272
2273 { 0xffffffff, 0 }
2274 };
2275
2276 static const struct {
2277 char *name;
2278 u32 offset;
2279 u32 hw_mask[BNX2X_CHIP_MAX_OFST];
2280 } prty_tbl[] = {
2281 { "CCM_PRTY_STS", CCM_REG_CCM_PRTY_STS,
2282 {0x3ffc0, 0, 0, 0} },
2283 { "CFC_PRTY_STS", CFC_REG_CFC_PRTY_STS,
2284 {0x2, 0x2, 0, 0} },
2285 { "DMAE_PRTY_STS", DMAE_REG_DMAE_PRTY_STS,
2286 {0, 0, 0, 0} },
2287 { "TCM_PRTY_STS", TCM_REG_TCM_PRTY_STS,
2288 {0x3ffc0, 0, 0, 0} },
2289 { "UCM_PRTY_STS", UCM_REG_UCM_PRTY_STS,
2290 {0x3ffc0, 0, 0, 0} },
2291 { "XCM_PRTY_STS", XCM_REG_XCM_PRTY_STS,
2292 {0x3ffc1, 0, 0, 0} },
2293
2294 { NULL, 0xffffffff, {0, 0, 0, 0} }
2295 };
2296
2297 if (!bnx2x_is_nvm_accessible(bp)) {
2298 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2299 "cannot access eeprom when the interface is down\n");
2300 return rc;
2301 }
2302
2303 if (CHIP_IS_E1(bp))
2304 index = BNX2X_CHIP_E1_OFST;
2305 else if (CHIP_IS_E1H(bp))
2306 index = BNX2X_CHIP_E1H_OFST;
2307 else if (CHIP_IS_E2(bp))
2308 index = BNX2X_CHIP_E2_OFST;
2309 else /* e3 */
2310 index = BNX2X_CHIP_E3_OFST;
2311
2312 /* pre-Check the parity status */
2313 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2314 val = REG_RD(bp, prty_tbl[i].offset);
2315 if (val & ~(prty_tbl[i].hw_mask[index])) {
2316 DP(BNX2X_MSG_ETHTOOL,
2317 "%s is 0x%x\n", prty_tbl[i].name, val);
2318 goto test_mem_exit;
2319 }
2320 }
2321
2322 /* Go through all the memories */
2323 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++)
2324 for (j = 0; j < mem_tbl[i].size; j++)
2325 REG_RD(bp, mem_tbl[i].offset + j*4);
2326
2327 /* Check the parity status */
2328 for (i = 0; prty_tbl[i].offset != 0xffffffff; i++) {
2329 val = REG_RD(bp, prty_tbl[i].offset);
2330 if (val & ~(prty_tbl[i].hw_mask[index])) {
2331 DP(BNX2X_MSG_ETHTOOL,
2332 "%s is 0x%x\n", prty_tbl[i].name, val);
2333 goto test_mem_exit;
2334 }
2335 }
2336
2337 rc = 0;
2338
2339 test_mem_exit:
2340 return rc;
2341 }
2342
2343 static void bnx2x_wait_for_link(struct bnx2x *bp, u8 link_up, u8 is_serdes)
2344 {
2345 int cnt = 1400;
2346
2347 if (link_up) {
2348 while (bnx2x_link_test(bp, is_serdes) && cnt--)
2349 msleep(20);
2350
2351 if (cnt <= 0 && bnx2x_link_test(bp, is_serdes))
2352 DP(BNX2X_MSG_ETHTOOL, "Timeout waiting for link up\n");
2353
2354 cnt = 1400;
2355 while (!bp->link_vars.link_up && cnt--)
2356 msleep(20);
2357
2358 if (cnt <= 0 && !bp->link_vars.link_up)
2359 DP(BNX2X_MSG_ETHTOOL,
2360 "Timeout waiting for link init\n");
2361 }
2362 }
2363
2364 static int bnx2x_run_loopback(struct bnx2x *bp, int loopback_mode)
2365 {
2366 unsigned int pkt_size, num_pkts, i;
2367 struct sk_buff *skb;
2368 unsigned char *packet;
2369 struct bnx2x_fastpath *fp_rx = &bp->fp[0];
2370 struct bnx2x_fastpath *fp_tx = &bp->fp[0];
2371 struct bnx2x_fp_txdata *txdata = fp_tx->txdata_ptr[0];
2372 u16 tx_start_idx, tx_idx;
2373 u16 rx_start_idx, rx_idx;
2374 u16 pkt_prod, bd_prod;
2375 struct sw_tx_bd *tx_buf;
2376 struct eth_tx_start_bd *tx_start_bd;
2377 dma_addr_t mapping;
2378 union eth_rx_cqe *cqe;
2379 u8 cqe_fp_flags, cqe_fp_type;
2380 struct sw_rx_bd *rx_buf;
2381 u16 len;
2382 int rc = -ENODEV;
2383 u8 *data;
2384 struct netdev_queue *txq = netdev_get_tx_queue(bp->dev,
2385 txdata->txq_index);
2386
2387 /* check the loopback mode */
2388 switch (loopback_mode) {
2389 case BNX2X_PHY_LOOPBACK:
2390 if (bp->link_params.loopback_mode != LOOPBACK_XGXS) {
2391 DP(BNX2X_MSG_ETHTOOL, "PHY loopback not supported\n");
2392 return -EINVAL;
2393 }
2394 break;
2395 case BNX2X_MAC_LOOPBACK:
2396 if (CHIP_IS_E3(bp)) {
2397 int cfg_idx = bnx2x_get_link_cfg_idx(bp);
2398 if (bp->port.supported[cfg_idx] &
2399 (SUPPORTED_10000baseT_Full |
2400 SUPPORTED_20000baseMLD2_Full |
2401 SUPPORTED_20000baseKR2_Full))
2402 bp->link_params.loopback_mode = LOOPBACK_XMAC;
2403 else
2404 bp->link_params.loopback_mode = LOOPBACK_UMAC;
2405 } else
2406 bp->link_params.loopback_mode = LOOPBACK_BMAC;
2407
2408 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2409 break;
2410 case BNX2X_EXT_LOOPBACK:
2411 if (bp->link_params.loopback_mode != LOOPBACK_EXT) {
2412 DP(BNX2X_MSG_ETHTOOL,
2413 "Can't configure external loopback\n");
2414 return -EINVAL;
2415 }
2416 break;
2417 default:
2418 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
2419 return -EINVAL;
2420 }
2421
2422 /* prepare the loopback packet */
2423 pkt_size = (((bp->dev->mtu < ETH_MAX_PACKET_SIZE) ?
2424 bp->dev->mtu : ETH_MAX_PACKET_SIZE) + ETH_HLEN);
2425 skb = netdev_alloc_skb(bp->dev, fp_rx->rx_buf_size);
2426 if (!skb) {
2427 DP(BNX2X_MSG_ETHTOOL, "Can't allocate skb\n");
2428 rc = -ENOMEM;
2429 goto test_loopback_exit;
2430 }
2431 packet = skb_put(skb, pkt_size);
2432 memcpy(packet, bp->dev->dev_addr, ETH_ALEN);
2433 memset(packet + ETH_ALEN, 0, ETH_ALEN);
2434 memset(packet + 2*ETH_ALEN, 0x77, (ETH_HLEN - 2*ETH_ALEN));
2435 for (i = ETH_HLEN; i < pkt_size; i++)
2436 packet[i] = (unsigned char) (i & 0xff);
2437 mapping = dma_map_single(&bp->pdev->dev, skb->data,
2438 skb_headlen(skb), DMA_TO_DEVICE);
2439 if (unlikely(dma_mapping_error(&bp->pdev->dev, mapping))) {
2440 rc = -ENOMEM;
2441 dev_kfree_skb(skb);
2442 DP(BNX2X_MSG_ETHTOOL, "Unable to map SKB\n");
2443 goto test_loopback_exit;
2444 }
2445
2446 /* send the loopback packet */
2447 num_pkts = 0;
2448 tx_start_idx = le16_to_cpu(*txdata->tx_cons_sb);
2449 rx_start_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2450
2451 netdev_tx_sent_queue(txq, skb->len);
2452
2453 pkt_prod = txdata->tx_pkt_prod++;
2454 tx_buf = &txdata->tx_buf_ring[TX_BD(pkt_prod)];
2455 tx_buf->first_bd = txdata->tx_bd_prod;
2456 tx_buf->skb = skb;
2457 tx_buf->flags = 0;
2458
2459 bd_prod = TX_BD(txdata->tx_bd_prod);
2460 tx_start_bd = &txdata->tx_desc_ring[bd_prod].start_bd;
2461 tx_start_bd->addr_hi = cpu_to_le32(U64_HI(mapping));
2462 tx_start_bd->addr_lo = cpu_to_le32(U64_LO(mapping));
2463 tx_start_bd->nbd = cpu_to_le16(2); /* start + pbd */
2464 tx_start_bd->nbytes = cpu_to_le16(skb_headlen(skb));
2465 tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
2466 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
2467 SET_FLAG(tx_start_bd->general_data,
2468 ETH_TX_START_BD_HDR_NBDS,
2469 1);
2470 SET_FLAG(tx_start_bd->general_data,
2471 ETH_TX_START_BD_PARSE_NBDS,
2472 0);
2473
2474 /* turn on parsing and get a BD */
2475 bd_prod = TX_BD(NEXT_TX_IDX(bd_prod));
2476
2477 if (CHIP_IS_E1x(bp)) {
2478 u16 global_data = 0;
2479 struct eth_tx_parse_bd_e1x *pbd_e1x =
2480 &txdata->tx_desc_ring[bd_prod].parse_bd_e1x;
2481 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x));
2482 SET_FLAG(global_data,
2483 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2484 pbd_e1x->global_data = cpu_to_le16(global_data);
2485 } else {
2486 u32 parsing_data = 0;
2487 struct eth_tx_parse_bd_e2 *pbd_e2 =
2488 &txdata->tx_desc_ring[bd_prod].parse_bd_e2;
2489 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2));
2490 SET_FLAG(parsing_data,
2491 ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, UNICAST_ADDRESS);
2492 pbd_e2->parsing_data = cpu_to_le32(parsing_data);
2493 }
2494 wmb();
2495
2496 txdata->tx_db.data.prod += 2;
2497 barrier();
2498 DOORBELL(bp, txdata->cid, txdata->tx_db.raw);
2499
2500 mmiowb();
2501 barrier();
2502
2503 num_pkts++;
2504 txdata->tx_bd_prod += 2; /* start + pbd */
2505
2506 udelay(100);
2507
2508 tx_idx = le16_to_cpu(*txdata->tx_cons_sb);
2509 if (tx_idx != tx_start_idx + num_pkts)
2510 goto test_loopback_exit;
2511
2512 /* Unlike HC IGU won't generate an interrupt for status block
2513 * updates that have been performed while interrupts were
2514 * disabled.
2515 */
2516 if (bp->common.int_block == INT_BLOCK_IGU) {
2517 /* Disable local BHes to prevent a dead-lock situation between
2518 * sch_direct_xmit() and bnx2x_run_loopback() (calling
2519 * bnx2x_tx_int()), as both are taking netif_tx_lock().
2520 */
2521 local_bh_disable();
2522 bnx2x_tx_int(bp, txdata);
2523 local_bh_enable();
2524 }
2525
2526 rx_idx = le16_to_cpu(*fp_rx->rx_cons_sb);
2527 if (rx_idx != rx_start_idx + num_pkts)
2528 goto test_loopback_exit;
2529
2530 cqe = &fp_rx->rx_comp_ring[RCQ_BD(fp_rx->rx_comp_cons)];
2531 cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
2532 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE;
2533 if (!CQE_TYPE_FAST(cqe_fp_type) || (cqe_fp_flags & ETH_RX_ERROR_FALGS))
2534 goto test_loopback_rx_exit;
2535
2536 len = le16_to_cpu(cqe->fast_path_cqe.pkt_len_or_gro_seg_len);
2537 if (len != pkt_size)
2538 goto test_loopback_rx_exit;
2539
2540 rx_buf = &fp_rx->rx_buf_ring[RX_BD(fp_rx->rx_bd_cons)];
2541 dma_sync_single_for_cpu(&bp->pdev->dev,
2542 dma_unmap_addr(rx_buf, mapping),
2543 fp_rx->rx_buf_size, DMA_FROM_DEVICE);
2544 data = rx_buf->data + NET_SKB_PAD + cqe->fast_path_cqe.placement_offset;
2545 for (i = ETH_HLEN; i < pkt_size; i++)
2546 if (*(data + i) != (unsigned char) (i & 0xff))
2547 goto test_loopback_rx_exit;
2548
2549 rc = 0;
2550
2551 test_loopback_rx_exit:
2552
2553 fp_rx->rx_bd_cons = NEXT_RX_IDX(fp_rx->rx_bd_cons);
2554 fp_rx->rx_bd_prod = NEXT_RX_IDX(fp_rx->rx_bd_prod);
2555 fp_rx->rx_comp_cons = NEXT_RCQ_IDX(fp_rx->rx_comp_cons);
2556 fp_rx->rx_comp_prod = NEXT_RCQ_IDX(fp_rx->rx_comp_prod);
2557
2558 /* Update producers */
2559 bnx2x_update_rx_prod(bp, fp_rx, fp_rx->rx_bd_prod, fp_rx->rx_comp_prod,
2560 fp_rx->rx_sge_prod);
2561
2562 test_loopback_exit:
2563 bp->link_params.loopback_mode = LOOPBACK_NONE;
2564
2565 return rc;
2566 }
2567
2568 static int bnx2x_test_loopback(struct bnx2x *bp)
2569 {
2570 int rc = 0, res;
2571
2572 if (BP_NOMCP(bp))
2573 return rc;
2574
2575 if (!netif_running(bp->dev))
2576 return BNX2X_LOOPBACK_FAILED;
2577
2578 bnx2x_netif_stop(bp, 1);
2579 bnx2x_acquire_phy_lock(bp);
2580
2581 res = bnx2x_run_loopback(bp, BNX2X_PHY_LOOPBACK);
2582 if (res) {
2583 DP(BNX2X_MSG_ETHTOOL, " PHY loopback failed (res %d)\n", res);
2584 rc |= BNX2X_PHY_LOOPBACK_FAILED;
2585 }
2586
2587 res = bnx2x_run_loopback(bp, BNX2X_MAC_LOOPBACK);
2588 if (res) {
2589 DP(BNX2X_MSG_ETHTOOL, " MAC loopback failed (res %d)\n", res);
2590 rc |= BNX2X_MAC_LOOPBACK_FAILED;
2591 }
2592
2593 bnx2x_release_phy_lock(bp);
2594 bnx2x_netif_start(bp);
2595
2596 return rc;
2597 }
2598
2599 static int bnx2x_test_ext_loopback(struct bnx2x *bp)
2600 {
2601 int rc;
2602 u8 is_serdes =
2603 (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2604
2605 if (BP_NOMCP(bp))
2606 return -ENODEV;
2607
2608 if (!netif_running(bp->dev))
2609 return BNX2X_EXT_LOOPBACK_FAILED;
2610
2611 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2612 rc = bnx2x_nic_load(bp, LOAD_LOOPBACK_EXT);
2613 if (rc) {
2614 DP(BNX2X_MSG_ETHTOOL,
2615 "Can't perform self-test, nic_load (for external lb) failed\n");
2616 return -ENODEV;
2617 }
2618 bnx2x_wait_for_link(bp, 1, is_serdes);
2619
2620 bnx2x_netif_stop(bp, 1);
2621
2622 rc = bnx2x_run_loopback(bp, BNX2X_EXT_LOOPBACK);
2623 if (rc)
2624 DP(BNX2X_MSG_ETHTOOL, "EXT loopback failed (res %d)\n", rc);
2625
2626 bnx2x_netif_start(bp);
2627
2628 return rc;
2629 }
2630
2631 struct code_entry {
2632 u32 sram_start_addr;
2633 u32 code_attribute;
2634 #define CODE_IMAGE_TYPE_MASK 0xf0800003
2635 #define CODE_IMAGE_VNTAG_PROFILES_DATA 0xd0000003
2636 #define CODE_IMAGE_LENGTH_MASK 0x007ffffc
2637 #define CODE_IMAGE_TYPE_EXTENDED_DIR 0xe0000000
2638 u32 nvm_start_addr;
2639 };
2640
2641 #define CODE_ENTRY_MAX 16
2642 #define CODE_ENTRY_EXTENDED_DIR_IDX 15
2643 #define MAX_IMAGES_IN_EXTENDED_DIR 64
2644 #define NVRAM_DIR_OFFSET 0x14
2645
2646 #define EXTENDED_DIR_EXISTS(code) \
2647 ((code & CODE_IMAGE_TYPE_MASK) == CODE_IMAGE_TYPE_EXTENDED_DIR && \
2648 (code & CODE_IMAGE_LENGTH_MASK) != 0)
2649
2650 #define CRC32_RESIDUAL 0xdebb20e3
2651 #define CRC_BUFF_SIZE 256
2652
2653 static int bnx2x_nvram_crc(struct bnx2x *bp,
2654 int offset,
2655 int size,
2656 u8 *buff)
2657 {
2658 u32 crc = ~0;
2659 int rc = 0, done = 0;
2660
2661 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2662 "NVRAM CRC from 0x%08x to 0x%08x\n", offset, offset + size);
2663
2664 while (done < size) {
2665 int count = min_t(int, size - done, CRC_BUFF_SIZE);
2666
2667 rc = bnx2x_nvram_read(bp, offset + done, buff, count);
2668
2669 if (rc)
2670 return rc;
2671
2672 crc = crc32_le(crc, buff, count);
2673 done += count;
2674 }
2675
2676 if (crc != CRC32_RESIDUAL)
2677 rc = -EINVAL;
2678
2679 return rc;
2680 }
2681
2682 static int bnx2x_test_nvram_dir(struct bnx2x *bp,
2683 struct code_entry *entry,
2684 u8 *buff)
2685 {
2686 size_t size = entry->code_attribute & CODE_IMAGE_LENGTH_MASK;
2687 u32 type = entry->code_attribute & CODE_IMAGE_TYPE_MASK;
2688 int rc;
2689
2690 /* Zero-length images and AFEX profiles do not have CRC */
2691 if (size == 0 || type == CODE_IMAGE_VNTAG_PROFILES_DATA)
2692 return 0;
2693
2694 rc = bnx2x_nvram_crc(bp, entry->nvm_start_addr, size, buff);
2695 if (rc)
2696 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2697 "image %x has failed crc test (rc %d)\n", type, rc);
2698
2699 return rc;
2700 }
2701
2702 static int bnx2x_test_dir_entry(struct bnx2x *bp, u32 addr, u8 *buff)
2703 {
2704 int rc;
2705 struct code_entry entry;
2706
2707 rc = bnx2x_nvram_read32(bp, addr, (u32 *)&entry, sizeof(entry));
2708 if (rc)
2709 return rc;
2710
2711 return bnx2x_test_nvram_dir(bp, &entry, buff);
2712 }
2713
2714 static int bnx2x_test_nvram_ext_dirs(struct bnx2x *bp, u8 *buff)
2715 {
2716 u32 rc, cnt, dir_offset = NVRAM_DIR_OFFSET;
2717 struct code_entry entry;
2718 int i;
2719
2720 rc = bnx2x_nvram_read32(bp,
2721 dir_offset +
2722 sizeof(entry) * CODE_ENTRY_EXTENDED_DIR_IDX,
2723 (u32 *)&entry, sizeof(entry));
2724 if (rc)
2725 return rc;
2726
2727 if (!EXTENDED_DIR_EXISTS(entry.code_attribute))
2728 return 0;
2729
2730 rc = bnx2x_nvram_read32(bp, entry.nvm_start_addr,
2731 &cnt, sizeof(u32));
2732 if (rc)
2733 return rc;
2734
2735 dir_offset = entry.nvm_start_addr + 8;
2736
2737 for (i = 0; i < cnt && i < MAX_IMAGES_IN_EXTENDED_DIR; i++) {
2738 rc = bnx2x_test_dir_entry(bp, dir_offset +
2739 sizeof(struct code_entry) * i,
2740 buff);
2741 if (rc)
2742 return rc;
2743 }
2744
2745 return 0;
2746 }
2747
2748 static int bnx2x_test_nvram_dirs(struct bnx2x *bp, u8 *buff)
2749 {
2750 u32 rc, dir_offset = NVRAM_DIR_OFFSET;
2751 int i;
2752
2753 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "NVRAM DIRS CRC test-set\n");
2754
2755 for (i = 0; i < CODE_ENTRY_EXTENDED_DIR_IDX; i++) {
2756 rc = bnx2x_test_dir_entry(bp, dir_offset +
2757 sizeof(struct code_entry) * i,
2758 buff);
2759 if (rc)
2760 return rc;
2761 }
2762
2763 return bnx2x_test_nvram_ext_dirs(bp, buff);
2764 }
2765
2766 struct crc_pair {
2767 int offset;
2768 int size;
2769 };
2770
2771 static int bnx2x_test_nvram_tbl(struct bnx2x *bp,
2772 const struct crc_pair *nvram_tbl, u8 *buf)
2773 {
2774 int i;
2775
2776 for (i = 0; nvram_tbl[i].size; i++) {
2777 int rc = bnx2x_nvram_crc(bp, nvram_tbl[i].offset,
2778 nvram_tbl[i].size, buf);
2779 if (rc) {
2780 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2781 "nvram_tbl[%d] has failed crc test (rc %d)\n",
2782 i, rc);
2783 return rc;
2784 }
2785 }
2786
2787 return 0;
2788 }
2789
2790 static int bnx2x_test_nvram(struct bnx2x *bp)
2791 {
2792 const struct crc_pair nvram_tbl[] = {
2793 { 0, 0x14 }, /* bootstrap */
2794 { 0x14, 0xec }, /* dir */
2795 { 0x100, 0x350 }, /* manuf_info */
2796 { 0x450, 0xf0 }, /* feature_info */
2797 { 0x640, 0x64 }, /* upgrade_key_info */
2798 { 0x708, 0x70 }, /* manuf_key_info */
2799 { 0, 0 }
2800 };
2801 const struct crc_pair nvram_tbl2[] = {
2802 { 0x7e8, 0x350 }, /* manuf_info2 */
2803 { 0xb38, 0xf0 }, /* feature_info */
2804 { 0, 0 }
2805 };
2806
2807 u8 *buf;
2808 int rc;
2809 u32 magic;
2810
2811 if (BP_NOMCP(bp))
2812 return 0;
2813
2814 buf = kmalloc(CRC_BUFF_SIZE, GFP_KERNEL);
2815 if (!buf) {
2816 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "kmalloc failed\n");
2817 rc = -ENOMEM;
2818 goto test_nvram_exit;
2819 }
2820
2821 rc = bnx2x_nvram_read32(bp, 0, &magic, sizeof(magic));
2822 if (rc) {
2823 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2824 "magic value read (rc %d)\n", rc);
2825 goto test_nvram_exit;
2826 }
2827
2828 if (magic != 0x669955aa) {
2829 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2830 "wrong magic value (0x%08x)\n", magic);
2831 rc = -ENODEV;
2832 goto test_nvram_exit;
2833 }
2834
2835 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM, "Port 0 CRC test-set\n");
2836 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl, buf);
2837 if (rc)
2838 goto test_nvram_exit;
2839
2840 if (!CHIP_IS_E1x(bp) && !CHIP_IS_57811xx(bp)) {
2841 u32 hide = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
2842 SHARED_HW_CFG_HIDE_PORT1;
2843
2844 if (!hide) {
2845 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2846 "Port 1 CRC test-set\n");
2847 rc = bnx2x_test_nvram_tbl(bp, nvram_tbl2, buf);
2848 if (rc)
2849 goto test_nvram_exit;
2850 }
2851 }
2852
2853 rc = bnx2x_test_nvram_dirs(bp, buf);
2854
2855 test_nvram_exit:
2856 kfree(buf);
2857 return rc;
2858 }
2859
2860 /* Send an EMPTY ramrod on the first queue */
2861 static int bnx2x_test_intr(struct bnx2x *bp)
2862 {
2863 struct bnx2x_queue_state_params params = {NULL};
2864
2865 if (!netif_running(bp->dev)) {
2866 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
2867 "cannot access eeprom when the interface is down\n");
2868 return -ENODEV;
2869 }
2870
2871 params.q_obj = &bp->sp_objs->q_obj;
2872 params.cmd = BNX2X_Q_CMD_EMPTY;
2873
2874 __set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);
2875
2876 return bnx2x_queue_state_change(bp, &params);
2877 }
2878
2879 static void bnx2x_self_test(struct net_device *dev,
2880 struct ethtool_test *etest, u64 *buf)
2881 {
2882 struct bnx2x *bp = netdev_priv(dev);
2883 u8 is_serdes, link_up;
2884 int rc, cnt = 0;
2885
2886 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
2887 netdev_err(bp->dev,
2888 "Handling parity error recovery. Try again later\n");
2889 etest->flags |= ETH_TEST_FL_FAILED;
2890 return;
2891 }
2892
2893 DP(BNX2X_MSG_ETHTOOL,
2894 "Self-test command parameters: offline = %d, external_lb = %d\n",
2895 (etest->flags & ETH_TEST_FL_OFFLINE),
2896 (etest->flags & ETH_TEST_FL_EXTERNAL_LB)>>2);
2897
2898 memset(buf, 0, sizeof(u64) * BNX2X_NUM_TESTS(bp));
2899
2900 if (!netif_running(dev)) {
2901 DP(BNX2X_MSG_ETHTOOL,
2902 "Can't perform self-test when interface is down\n");
2903 return;
2904 }
2905
2906 is_serdes = (bp->link_vars.link_status & LINK_STATUS_SERDES_LINK) > 0;
2907 link_up = bp->link_vars.link_up;
2908 /* offline tests are not supported in MF mode */
2909 if ((etest->flags & ETH_TEST_FL_OFFLINE) && !IS_MF(bp)) {
2910 int port = BP_PORT(bp);
2911 u32 val;
2912
2913 /* save current value of input enable for TX port IF */
2914 val = REG_RD(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4);
2915 /* disable input for TX port IF */
2916 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, 0);
2917
2918 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2919 rc = bnx2x_nic_load(bp, LOAD_DIAG);
2920 if (rc) {
2921 etest->flags |= ETH_TEST_FL_FAILED;
2922 DP(BNX2X_MSG_ETHTOOL,
2923 "Can't perform self-test, nic_load (for offline) failed\n");
2924 return;
2925 }
2926
2927 /* wait until link state is restored */
2928 bnx2x_wait_for_link(bp, 1, is_serdes);
2929
2930 if (bnx2x_test_registers(bp) != 0) {
2931 buf[0] = 1;
2932 etest->flags |= ETH_TEST_FL_FAILED;
2933 }
2934 if (bnx2x_test_memory(bp) != 0) {
2935 buf[1] = 1;
2936 etest->flags |= ETH_TEST_FL_FAILED;
2937 }
2938
2939 buf[2] = bnx2x_test_loopback(bp); /* internal LB */
2940 if (buf[2] != 0)
2941 etest->flags |= ETH_TEST_FL_FAILED;
2942
2943 if (etest->flags & ETH_TEST_FL_EXTERNAL_LB) {
2944 buf[3] = bnx2x_test_ext_loopback(bp); /* external LB */
2945 if (buf[3] != 0)
2946 etest->flags |= ETH_TEST_FL_FAILED;
2947 etest->flags |= ETH_TEST_FL_EXTERNAL_LB_DONE;
2948 }
2949
2950 bnx2x_nic_unload(bp, UNLOAD_NORMAL, false);
2951
2952 /* restore input for TX port IF */
2953 REG_WR(bp, NIG_REG_EGRESS_UMP0_IN_EN + port*4, val);
2954 rc = bnx2x_nic_load(bp, LOAD_NORMAL);
2955 if (rc) {
2956 etest->flags |= ETH_TEST_FL_FAILED;
2957 DP(BNX2X_MSG_ETHTOOL,
2958 "Can't perform self-test, nic_load (for online) failed\n");
2959 return;
2960 }
2961 /* wait until link state is restored */
2962 bnx2x_wait_for_link(bp, link_up, is_serdes);
2963 }
2964 if (bnx2x_test_nvram(bp) != 0) {
2965 if (!IS_MF(bp))
2966 buf[4] = 1;
2967 else
2968 buf[0] = 1;
2969 etest->flags |= ETH_TEST_FL_FAILED;
2970 }
2971 if (bnx2x_test_intr(bp) != 0) {
2972 if (!IS_MF(bp))
2973 buf[5] = 1;
2974 else
2975 buf[1] = 1;
2976 etest->flags |= ETH_TEST_FL_FAILED;
2977 }
2978
2979 if (link_up) {
2980 cnt = 100;
2981 while (bnx2x_link_test(bp, is_serdes) && --cnt)
2982 msleep(20);
2983 }
2984
2985 if (!cnt) {
2986 if (!IS_MF(bp))
2987 buf[6] = 1;
2988 else
2989 buf[2] = 1;
2990 etest->flags |= ETH_TEST_FL_FAILED;
2991 }
2992 }
2993
2994 #define IS_PORT_STAT(i) \
2995 ((bnx2x_stats_arr[i].flags & STATS_FLAGS_BOTH) == STATS_FLAGS_PORT)
2996 #define IS_FUNC_STAT(i) (bnx2x_stats_arr[i].flags & STATS_FLAGS_FUNC)
2997 #define IS_MF_MODE_STAT(bp) \
2998 (IS_MF(bp) && !(bp->msg_enable & BNX2X_MSG_STATS))
2999
3000 /* ethtool statistics are displayed for all regular ethernet queues and the
3001 * fcoe L2 queue if not disabled
3002 */
3003 static int bnx2x_num_stat_queues(struct bnx2x *bp)
3004 {
3005 return BNX2X_NUM_ETH_QUEUES(bp);
3006 }
3007
3008 static int bnx2x_get_sset_count(struct net_device *dev, int stringset)
3009 {
3010 struct bnx2x *bp = netdev_priv(dev);
3011 int i, num_strings = 0;
3012
3013 switch (stringset) {
3014 case ETH_SS_STATS:
3015 if (is_multi(bp)) {
3016 num_strings = bnx2x_num_stat_queues(bp) *
3017 BNX2X_NUM_Q_STATS;
3018 } else
3019 num_strings = 0;
3020 if (IS_MF_MODE_STAT(bp)) {
3021 for (i = 0; i < BNX2X_NUM_STATS; i++)
3022 if (IS_FUNC_STAT(i))
3023 num_strings++;
3024 } else
3025 num_strings += BNX2X_NUM_STATS;
3026
3027 return num_strings;
3028
3029 case ETH_SS_TEST:
3030 return BNX2X_NUM_TESTS(bp);
3031
3032 case ETH_SS_PRIV_FLAGS:
3033 return BNX2X_PRI_FLAG_LEN;
3034
3035 default:
3036 return -EINVAL;
3037 }
3038 }
3039
3040 static u32 bnx2x_get_private_flags(struct net_device *dev)
3041 {
3042 struct bnx2x *bp = netdev_priv(dev);
3043 u32 flags = 0;
3044
3045 flags |= (!(bp->flags & NO_ISCSI_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_ISCSI;
3046 flags |= (!(bp->flags & NO_FCOE_FLAG) ? 1 : 0) << BNX2X_PRI_FLAG_FCOE;
3047 flags |= (!!IS_MF_STORAGE_ONLY(bp)) << BNX2X_PRI_FLAG_STORAGE;
3048
3049 return flags;
3050 }
3051
3052 static void bnx2x_get_strings(struct net_device *dev, u32 stringset, u8 *buf)
3053 {
3054 struct bnx2x *bp = netdev_priv(dev);
3055 int i, j, k, start;
3056 char queue_name[MAX_QUEUE_NAME_LEN+1];
3057
3058 switch (stringset) {
3059 case ETH_SS_STATS:
3060 k = 0;
3061 if (is_multi(bp)) {
3062 for_each_eth_queue(bp, i) {
3063 memset(queue_name, 0, sizeof(queue_name));
3064 sprintf(queue_name, "%d", i);
3065 for (j = 0; j < BNX2X_NUM_Q_STATS; j++)
3066 snprintf(buf + (k + j)*ETH_GSTRING_LEN,
3067 ETH_GSTRING_LEN,
3068 bnx2x_q_stats_arr[j].string,
3069 queue_name);
3070 k += BNX2X_NUM_Q_STATS;
3071 }
3072 }
3073
3074
3075 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3076 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
3077 continue;
3078 strcpy(buf + (k + j)*ETH_GSTRING_LEN,
3079 bnx2x_stats_arr[i].string);
3080 j++;
3081 }
3082
3083 break;
3084
3085 case ETH_SS_TEST:
3086 /* First 4 tests cannot be done in MF mode */
3087 if (!IS_MF(bp))
3088 start = 0;
3089 else
3090 start = 4;
3091 memcpy(buf, bnx2x_tests_str_arr + start,
3092 ETH_GSTRING_LEN * BNX2X_NUM_TESTS(bp));
3093 break;
3094
3095 case ETH_SS_PRIV_FLAGS:
3096 memcpy(buf, bnx2x_private_arr,
3097 ETH_GSTRING_LEN * BNX2X_PRI_FLAG_LEN);
3098 break;
3099 }
3100 }
3101
3102 static void bnx2x_get_ethtool_stats(struct net_device *dev,
3103 struct ethtool_stats *stats, u64 *buf)
3104 {
3105 struct bnx2x *bp = netdev_priv(dev);
3106 u32 *hw_stats, *offset;
3107 int i, j, k = 0;
3108
3109 if (is_multi(bp)) {
3110 for_each_eth_queue(bp, i) {
3111 hw_stats = (u32 *)&bp->fp_stats[i].eth_q_stats;
3112 for (j = 0; j < BNX2X_NUM_Q_STATS; j++) {
3113 if (bnx2x_q_stats_arr[j].size == 0) {
3114 /* skip this counter */
3115 buf[k + j] = 0;
3116 continue;
3117 }
3118 offset = (hw_stats +
3119 bnx2x_q_stats_arr[j].offset);
3120 if (bnx2x_q_stats_arr[j].size == 4) {
3121 /* 4-byte counter */
3122 buf[k + j] = (u64) *offset;
3123 continue;
3124 }
3125 /* 8-byte counter */
3126 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3127 }
3128 k += BNX2X_NUM_Q_STATS;
3129 }
3130 }
3131
3132 hw_stats = (u32 *)&bp->eth_stats;
3133 for (i = 0, j = 0; i < BNX2X_NUM_STATS; i++) {
3134 if (IS_MF_MODE_STAT(bp) && IS_PORT_STAT(i))
3135 continue;
3136 if (bnx2x_stats_arr[i].size == 0) {
3137 /* skip this counter */
3138 buf[k + j] = 0;
3139 j++;
3140 continue;
3141 }
3142 offset = (hw_stats + bnx2x_stats_arr[i].offset);
3143 if (bnx2x_stats_arr[i].size == 4) {
3144 /* 4-byte counter */
3145 buf[k + j] = (u64) *offset;
3146 j++;
3147 continue;
3148 }
3149 /* 8-byte counter */
3150 buf[k + j] = HILO_U64(*offset, *(offset + 1));
3151 j++;
3152 }
3153 }
3154
3155 static int bnx2x_set_phys_id(struct net_device *dev,
3156 enum ethtool_phys_id_state state)
3157 {
3158 struct bnx2x *bp = netdev_priv(dev);
3159
3160 if (!bnx2x_is_nvm_accessible(bp)) {
3161 DP(BNX2X_MSG_ETHTOOL | BNX2X_MSG_NVM,
3162 "cannot access eeprom when the interface is down\n");
3163 return -EAGAIN;
3164 }
3165
3166 switch (state) {
3167 case ETHTOOL_ID_ACTIVE:
3168 return 1; /* cycle on/off once per second */
3169
3170 case ETHTOOL_ID_ON:
3171 bnx2x_acquire_phy_lock(bp);
3172 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3173 LED_MODE_ON, SPEED_1000);
3174 bnx2x_release_phy_lock(bp);
3175 break;
3176
3177 case ETHTOOL_ID_OFF:
3178 bnx2x_acquire_phy_lock(bp);
3179 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3180 LED_MODE_FRONT_PANEL_OFF, 0);
3181 bnx2x_release_phy_lock(bp);
3182 break;
3183
3184 case ETHTOOL_ID_INACTIVE:
3185 bnx2x_acquire_phy_lock(bp);
3186 bnx2x_set_led(&bp->link_params, &bp->link_vars,
3187 LED_MODE_OPER,
3188 bp->link_vars.line_speed);
3189 bnx2x_release_phy_lock(bp);
3190 }
3191
3192 return 0;
3193 }
3194
3195 static int bnx2x_get_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3196 {
3197
3198 switch (info->flow_type) {
3199 case TCP_V4_FLOW:
3200 case TCP_V6_FLOW:
3201 info->data = RXH_IP_SRC | RXH_IP_DST |
3202 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3203 break;
3204 case UDP_V4_FLOW:
3205 if (bp->rss_conf_obj.udp_rss_v4)
3206 info->data = RXH_IP_SRC | RXH_IP_DST |
3207 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3208 else
3209 info->data = RXH_IP_SRC | RXH_IP_DST;
3210 break;
3211 case UDP_V6_FLOW:
3212 if (bp->rss_conf_obj.udp_rss_v6)
3213 info->data = RXH_IP_SRC | RXH_IP_DST |
3214 RXH_L4_B_0_1 | RXH_L4_B_2_3;
3215 else
3216 info->data = RXH_IP_SRC | RXH_IP_DST;
3217 break;
3218 case IPV4_FLOW:
3219 case IPV6_FLOW:
3220 info->data = RXH_IP_SRC | RXH_IP_DST;
3221 break;
3222 default:
3223 info->data = 0;
3224 break;
3225 }
3226
3227 return 0;
3228 }
3229
3230 static int bnx2x_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info,
3231 u32 *rules __always_unused)
3232 {
3233 struct bnx2x *bp = netdev_priv(dev);
3234
3235 switch (info->cmd) {
3236 case ETHTOOL_GRXRINGS:
3237 info->data = BNX2X_NUM_ETH_QUEUES(bp);
3238 return 0;
3239 case ETHTOOL_GRXFH:
3240 return bnx2x_get_rss_flags(bp, info);
3241 default:
3242 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3243 return -EOPNOTSUPP;
3244 }
3245 }
3246
3247 static int bnx2x_set_rss_flags(struct bnx2x *bp, struct ethtool_rxnfc *info)
3248 {
3249 int udp_rss_requested;
3250
3251 DP(BNX2X_MSG_ETHTOOL,
3252 "Set rss flags command parameters: flow type = %d, data = %llu\n",
3253 info->flow_type, info->data);
3254
3255 switch (info->flow_type) {
3256 case TCP_V4_FLOW:
3257 case TCP_V6_FLOW:
3258 /* For TCP only 4-tupple hash is supported */
3259 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST |
3260 RXH_L4_B_0_1 | RXH_L4_B_2_3)) {
3261 DP(BNX2X_MSG_ETHTOOL,
3262 "Command parameters not supported\n");
3263 return -EINVAL;
3264 }
3265 return 0;
3266
3267 case UDP_V4_FLOW:
3268 case UDP_V6_FLOW:
3269 /* For UDP either 2-tupple hash or 4-tupple hash is supported */
3270 if (info->data == (RXH_IP_SRC | RXH_IP_DST |
3271 RXH_L4_B_0_1 | RXH_L4_B_2_3))
3272 udp_rss_requested = 1;
3273 else if (info->data == (RXH_IP_SRC | RXH_IP_DST))
3274 udp_rss_requested = 0;
3275 else
3276 return -EINVAL;
3277 if ((info->flow_type == UDP_V4_FLOW) &&
3278 (bp->rss_conf_obj.udp_rss_v4 != udp_rss_requested)) {
3279 bp->rss_conf_obj.udp_rss_v4 = udp_rss_requested;
3280 DP(BNX2X_MSG_ETHTOOL,
3281 "rss re-configured, UDP 4-tupple %s\n",
3282 udp_rss_requested ? "enabled" : "disabled");
3283 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3284 } else if ((info->flow_type == UDP_V6_FLOW) &&
3285 (bp->rss_conf_obj.udp_rss_v6 != udp_rss_requested)) {
3286 bp->rss_conf_obj.udp_rss_v6 = udp_rss_requested;
3287 DP(BNX2X_MSG_ETHTOOL,
3288 "rss re-configured, UDP 4-tupple %s\n",
3289 udp_rss_requested ? "enabled" : "disabled");
3290 return bnx2x_config_rss_pf(bp, &bp->rss_conf_obj, 0);
3291 }
3292 return 0;
3293
3294 case IPV4_FLOW:
3295 case IPV6_FLOW:
3296 /* For IP only 2-tupple hash is supported */
3297 if (info->data ^ (RXH_IP_SRC | RXH_IP_DST)) {
3298 DP(BNX2X_MSG_ETHTOOL,
3299 "Command parameters not supported\n");
3300 return -EINVAL;
3301 }
3302 return 0;
3303
3304 case SCTP_V4_FLOW:
3305 case AH_ESP_V4_FLOW:
3306 case AH_V4_FLOW:
3307 case ESP_V4_FLOW:
3308 case SCTP_V6_FLOW:
3309 case AH_ESP_V6_FLOW:
3310 case AH_V6_FLOW:
3311 case ESP_V6_FLOW:
3312 case IP_USER_FLOW:
3313 case ETHER_FLOW:
3314 /* RSS is not supported for these protocols */
3315 if (info->data) {
3316 DP(BNX2X_MSG_ETHTOOL,
3317 "Command parameters not supported\n");
3318 return -EINVAL;
3319 }
3320 return 0;
3321
3322 default:
3323 return -EINVAL;
3324 }
3325 }
3326
3327 static int bnx2x_set_rxnfc(struct net_device *dev, struct ethtool_rxnfc *info)
3328 {
3329 struct bnx2x *bp = netdev_priv(dev);
3330
3331 switch (info->cmd) {
3332 case ETHTOOL_SRXFH:
3333 return bnx2x_set_rss_flags(bp, info);
3334 default:
3335 DP(BNX2X_MSG_ETHTOOL, "Command parameters not supported\n");
3336 return -EOPNOTSUPP;
3337 }
3338 }
3339
3340 static u32 bnx2x_get_rxfh_indir_size(struct net_device *dev)
3341 {
3342 return T_ETH_INDIRECTION_TABLE_SIZE;
3343 }
3344
3345 static int bnx2x_get_rxfh_indir(struct net_device *dev, u32 *indir)
3346 {
3347 struct bnx2x *bp = netdev_priv(dev);
3348 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE] = {0};
3349 size_t i;
3350
3351 /* Get the current configuration of the RSS indirection table */
3352 bnx2x_get_rss_ind_table(&bp->rss_conf_obj, ind_table);
3353
3354 /*
3355 * We can't use a memcpy() as an internal storage of an
3356 * indirection table is a u8 array while indir->ring_index
3357 * points to an array of u32.
3358 *
3359 * Indirection table contains the FW Client IDs, so we need to
3360 * align the returned table to the Client ID of the leading RSS
3361 * queue.
3362 */
3363 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++)
3364 indir[i] = ind_table[i] - bp->fp->cl_id;
3365
3366 return 0;
3367 }
3368
3369 static int bnx2x_set_rxfh_indir(struct net_device *dev, const u32 *indir)
3370 {
3371 struct bnx2x *bp = netdev_priv(dev);
3372 size_t i;
3373
3374 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) {
3375 /*
3376 * The same as in bnx2x_get_rxfh_indir: we can't use a memcpy()
3377 * as an internal storage of an indirection table is a u8 array
3378 * while indir->ring_index points to an array of u32.
3379 *
3380 * Indirection table contains the FW Client IDs, so we need to
3381 * align the received table to the Client ID of the leading RSS
3382 * queue
3383 */
3384 bp->rss_conf_obj.ind_table[i] = indir[i] + bp->fp->cl_id;
3385 }
3386
3387 return bnx2x_config_rss_eth(bp, false);
3388 }
3389
3390 /**
3391 * bnx2x_get_channels - gets the number of RSS queues.
3392 *
3393 * @dev: net device
3394 * @channels: returns the number of max / current queues
3395 */
3396 static void bnx2x_get_channels(struct net_device *dev,
3397 struct ethtool_channels *channels)
3398 {
3399 struct bnx2x *bp = netdev_priv(dev);
3400
3401 channels->max_combined = BNX2X_MAX_RSS_COUNT(bp);
3402 channels->combined_count = BNX2X_NUM_ETH_QUEUES(bp);
3403 }
3404
3405 /**
3406 * bnx2x_change_num_queues - change the number of RSS queues.
3407 *
3408 * @bp: bnx2x private structure
3409 *
3410 * Re-configure interrupt mode to get the new number of MSI-X
3411 * vectors and re-add NAPI objects.
3412 */
3413 static void bnx2x_change_num_queues(struct bnx2x *bp, int num_rss)
3414 {
3415 bnx2x_disable_msi(bp);
3416 bp->num_ethernet_queues = num_rss;
3417 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
3418 BNX2X_DEV_INFO("set number of queues to %d\n", bp->num_queues);
3419 bnx2x_set_int_mode(bp);
3420 }
3421
3422 /**
3423 * bnx2x_set_channels - sets the number of RSS queues.
3424 *
3425 * @dev: net device
3426 * @channels: includes the number of queues requested
3427 */
3428 static int bnx2x_set_channels(struct net_device *dev,
3429 struct ethtool_channels *channels)
3430 {
3431 struct bnx2x *bp = netdev_priv(dev);
3432
3433
3434 DP(BNX2X_MSG_ETHTOOL,
3435 "set-channels command parameters: rx = %d, tx = %d, other = %d, combined = %d\n",
3436 channels->rx_count, channels->tx_count, channels->other_count,
3437 channels->combined_count);
3438
3439 /* We don't support separate rx / tx channels.
3440 * We don't allow setting 'other' channels.
3441 */
3442 if (channels->rx_count || channels->tx_count || channels->other_count
3443 || (channels->combined_count == 0) ||
3444 (channels->combined_count > BNX2X_MAX_RSS_COUNT(bp))) {
3445 DP(BNX2X_MSG_ETHTOOL, "command parameters not supported\n");
3446 return -EINVAL;
3447 }
3448
3449 /* Check if there was a change in the active parameters */
3450 if (channels->combined_count == BNX2X_NUM_ETH_QUEUES(bp)) {
3451 DP(BNX2X_MSG_ETHTOOL, "No change in active parameters\n");
3452 return 0;
3453 }
3454
3455 /* Set the requested number of queues in bp context.
3456 * Note that the actual number of queues created during load may be
3457 * less than requested if memory is low.
3458 */
3459 if (unlikely(!netif_running(dev))) {
3460 bnx2x_change_num_queues(bp, channels->combined_count);
3461 return 0;
3462 }
3463 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
3464 bnx2x_change_num_queues(bp, channels->combined_count);
3465 return bnx2x_nic_load(bp, LOAD_NORMAL);
3466 }
3467
3468 static const struct ethtool_ops bnx2x_ethtool_ops = {
3469 .get_settings = bnx2x_get_settings,
3470 .set_settings = bnx2x_set_settings,
3471 .get_drvinfo = bnx2x_get_drvinfo,
3472 .get_regs_len = bnx2x_get_regs_len,
3473 .get_regs = bnx2x_get_regs,
3474 .get_dump_flag = bnx2x_get_dump_flag,
3475 .get_dump_data = bnx2x_get_dump_data,
3476 .set_dump = bnx2x_set_dump,
3477 .get_wol = bnx2x_get_wol,
3478 .set_wol = bnx2x_set_wol,
3479 .get_msglevel = bnx2x_get_msglevel,
3480 .set_msglevel = bnx2x_set_msglevel,
3481 .nway_reset = bnx2x_nway_reset,
3482 .get_link = bnx2x_get_link,
3483 .get_eeprom_len = bnx2x_get_eeprom_len,
3484 .get_eeprom = bnx2x_get_eeprom,
3485 .set_eeprom = bnx2x_set_eeprom,
3486 .get_coalesce = bnx2x_get_coalesce,
3487 .set_coalesce = bnx2x_set_coalesce,
3488 .get_ringparam = bnx2x_get_ringparam,
3489 .set_ringparam = bnx2x_set_ringparam,
3490 .get_pauseparam = bnx2x_get_pauseparam,
3491 .set_pauseparam = bnx2x_set_pauseparam,
3492 .self_test = bnx2x_self_test,
3493 .get_sset_count = bnx2x_get_sset_count,
3494 .get_priv_flags = bnx2x_get_private_flags,
3495 .get_strings = bnx2x_get_strings,
3496 .set_phys_id = bnx2x_set_phys_id,
3497 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3498 .get_rxnfc = bnx2x_get_rxnfc,
3499 .set_rxnfc = bnx2x_set_rxnfc,
3500 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3501 .get_rxfh_indir = bnx2x_get_rxfh_indir,
3502 .set_rxfh_indir = bnx2x_set_rxfh_indir,
3503 .get_channels = bnx2x_get_channels,
3504 .set_channels = bnx2x_set_channels,
3505 .get_module_info = bnx2x_get_module_info,
3506 .get_module_eeprom = bnx2x_get_module_eeprom,
3507 .get_eee = bnx2x_get_eee,
3508 .set_eee = bnx2x_set_eee,
3509 .get_ts_info = ethtool_op_get_ts_info,
3510 };
3511
3512 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
3513 .get_settings = bnx2x_get_settings,
3514 .set_settings = bnx2x_set_settings,
3515 .get_drvinfo = bnx2x_get_drvinfo,
3516 .get_msglevel = bnx2x_get_msglevel,
3517 .set_msglevel = bnx2x_set_msglevel,
3518 .get_link = bnx2x_get_link,
3519 .get_coalesce = bnx2x_get_coalesce,
3520 .get_ringparam = bnx2x_get_ringparam,
3521 .set_ringparam = bnx2x_set_ringparam,
3522 .get_sset_count = bnx2x_get_sset_count,
3523 .get_strings = bnx2x_get_strings,
3524 .get_ethtool_stats = bnx2x_get_ethtool_stats,
3525 .get_rxnfc = bnx2x_get_rxnfc,
3526 .set_rxnfc = bnx2x_set_rxnfc,
3527 .get_rxfh_indir_size = bnx2x_get_rxfh_indir_size,
3528 .get_rxfh_indir = bnx2x_get_rxfh_indir,
3529 .set_rxfh_indir = bnx2x_set_rxfh_indir,
3530 .get_channels = bnx2x_get_channels,
3531 .set_channels = bnx2x_set_channels,
3532 };
3533
3534 void bnx2x_set_ethtool_ops(struct bnx2x *bp, struct net_device *netdev)
3535 {
3536 if (IS_PF(bp))
3537 SET_ETHTOOL_OPS(netdev, &bnx2x_ethtool_ops);
3538 else /* vf */
3539 SET_ETHTOOL_OPS(netdev, &bnx2x_vf_ethtool_ops);
3540 }
Linux kernel - Deliverables
This page took 0.108402 seconds and 5 git commands to generate.