1 /* bnx2x_hsi.h: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
12 #include "bnx2x_fw_defs.h"
14 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
20 #define BNX2X_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
21 #define BNX2X_MAX_ISCSI_TRGT_CONN_SHIFT 0
22 #define BNX2X_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
23 #define BNX2X_MAX_ISCSI_INIT_CONN_SHIFT 16
28 #define BNX2X_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
29 #define BNX2X_MAX_FCOE_TRGT_CONN_SHIFT 0
30 #define BNX2X_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
31 #define BNX2X_MAX_FCOE_INIT_CONN_SHIFT 16
40 #define NVM_PATH_MAX 2
42 /****************************************************************************
43 * Shared HW configuration *
44 ****************************************************************************/
45 #define PIN_CFG_NA 0x00000000
46 #define PIN_CFG_GPIO0_P0 0x00000001
47 #define PIN_CFG_GPIO1_P0 0x00000002
48 #define PIN_CFG_GPIO2_P0 0x00000003
49 #define PIN_CFG_GPIO3_P0 0x00000004
50 #define PIN_CFG_GPIO0_P1 0x00000005
51 #define PIN_CFG_GPIO1_P1 0x00000006
52 #define PIN_CFG_GPIO2_P1 0x00000007
53 #define PIN_CFG_GPIO3_P1 0x00000008
54 #define PIN_CFG_EPIO0 0x00000009
55 #define PIN_CFG_EPIO1 0x0000000a
56 #define PIN_CFG_EPIO2 0x0000000b
57 #define PIN_CFG_EPIO3 0x0000000c
58 #define PIN_CFG_EPIO4 0x0000000d
59 #define PIN_CFG_EPIO5 0x0000000e
60 #define PIN_CFG_EPIO6 0x0000000f
61 #define PIN_CFG_EPIO7 0x00000010
62 #define PIN_CFG_EPIO8 0x00000011
63 #define PIN_CFG_EPIO9 0x00000012
64 #define PIN_CFG_EPIO10 0x00000013
65 #define PIN_CFG_EPIO11 0x00000014
66 #define PIN_CFG_EPIO12 0x00000015
67 #define PIN_CFG_EPIO13 0x00000016
68 #define PIN_CFG_EPIO14 0x00000017
69 #define PIN_CFG_EPIO15 0x00000018
70 #define PIN_CFG_EPIO16 0x00000019
71 #define PIN_CFG_EPIO17 0x0000001a
72 #define PIN_CFG_EPIO18 0x0000001b
73 #define PIN_CFG_EPIO19 0x0000001c
74 #define PIN_CFG_EPIO20 0x0000001d
75 #define PIN_CFG_EPIO21 0x0000001e
76 #define PIN_CFG_EPIO22 0x0000001f
77 #define PIN_CFG_EPIO23 0x00000020
78 #define PIN_CFG_EPIO24 0x00000021
79 #define PIN_CFG_EPIO25 0x00000022
80 #define PIN_CFG_EPIO26 0x00000023
81 #define PIN_CFG_EPIO27 0x00000024
82 #define PIN_CFG_EPIO28 0x00000025
83 #define PIN_CFG_EPIO29 0x00000026
84 #define PIN_CFG_EPIO30 0x00000027
85 #define PIN_CFG_EPIO31 0x00000028
88 #define EPIO_CFG_NA 0x00000000
89 #define EPIO_CFG_EPIO0 0x00000001
90 #define EPIO_CFG_EPIO1 0x00000002
91 #define EPIO_CFG_EPIO2 0x00000003
92 #define EPIO_CFG_EPIO3 0x00000004
93 #define EPIO_CFG_EPIO4 0x00000005
94 #define EPIO_CFG_EPIO5 0x00000006
95 #define EPIO_CFG_EPIO6 0x00000007
96 #define EPIO_CFG_EPIO7 0x00000008
97 #define EPIO_CFG_EPIO8 0x00000009
98 #define EPIO_CFG_EPIO9 0x0000000a
99 #define EPIO_CFG_EPIO10 0x0000000b
100 #define EPIO_CFG_EPIO11 0x0000000c
101 #define EPIO_CFG_EPIO12 0x0000000d
102 #define EPIO_CFG_EPIO13 0x0000000e
103 #define EPIO_CFG_EPIO14 0x0000000f
104 #define EPIO_CFG_EPIO15 0x00000010
105 #define EPIO_CFG_EPIO16 0x00000011
106 #define EPIO_CFG_EPIO17 0x00000012
107 #define EPIO_CFG_EPIO18 0x00000013
108 #define EPIO_CFG_EPIO19 0x00000014
109 #define EPIO_CFG_EPIO20 0x00000015
110 #define EPIO_CFG_EPIO21 0x00000016
111 #define EPIO_CFG_EPIO22 0x00000017
112 #define EPIO_CFG_EPIO23 0x00000018
113 #define EPIO_CFG_EPIO24 0x00000019
114 #define EPIO_CFG_EPIO25 0x0000001a
115 #define EPIO_CFG_EPIO26 0x0000001b
116 #define EPIO_CFG_EPIO27 0x0000001c
117 #define EPIO_CFG_EPIO28 0x0000001d
118 #define EPIO_CFG_EPIO29 0x0000001e
119 #define EPIO_CFG_EPIO30 0x0000001f
120 #define EPIO_CFG_EPIO31 0x00000020
123 struct shared_hw_cfg
{ /* NVRAM Offset */
124 /* Up to 16 bytes of NULL-terminated string */
125 u8 part_num
[16]; /* 0x104 */
127 u32 config
; /* 0x114 */
128 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
129 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
130 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
131 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
132 #define SHARED_HW_CFG_MCP_RST_ON_CORE_RST_EN 0x00000002
134 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
136 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
138 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
139 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
141 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
142 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
143 /* Whatever MFW found in NVM
144 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
145 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
146 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
147 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
148 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
149 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
150 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
151 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
152 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
153 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
154 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
155 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
156 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
157 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
159 #define SHARED_HW_CFG_LED_MODE_MASK 0x000f0000
160 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
161 #define SHARED_HW_CFG_LED_MAC1 0x00000000
162 #define SHARED_HW_CFG_LED_PHY1 0x00010000
163 #define SHARED_HW_CFG_LED_PHY2 0x00020000
164 #define SHARED_HW_CFG_LED_PHY3 0x00030000
165 #define SHARED_HW_CFG_LED_MAC2 0x00040000
166 #define SHARED_HW_CFG_LED_PHY4 0x00050000
167 #define SHARED_HW_CFG_LED_PHY5 0x00060000
168 #define SHARED_HW_CFG_LED_PHY6 0x00070000
169 #define SHARED_HW_CFG_LED_MAC3 0x00080000
170 #define SHARED_HW_CFG_LED_PHY7 0x00090000
171 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
172 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
173 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
174 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
175 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
178 #define SHARED_HW_CFG_AN_ENABLE_MASK 0x3f000000
179 #define SHARED_HW_CFG_AN_ENABLE_SHIFT 24
180 #define SHARED_HW_CFG_AN_ENABLE_CL37 0x01000000
181 #define SHARED_HW_CFG_AN_ENABLE_CL73 0x02000000
182 #define SHARED_HW_CFG_AN_ENABLE_BAM 0x04000000
183 #define SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 0x08000000
184 #define SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 0x10000000
185 #define SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 0x20000000
187 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
188 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
189 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
191 #define SHARED_HW_CFG_ATC_MASK 0x80000000
192 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
193 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
195 u32 config2
; /* 0x118 */
196 /* one time auto detect grace period (in sec) */
197 #define SHARED_HW_CFG_GRACE_PERIOD_MASK 0x000000ff
198 #define SHARED_HW_CFG_GRACE_PERIOD_SHIFT 0
200 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
201 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
203 /* The default value for the core clock is 250MHz and it is
204 achieved by setting the clock change to 4 */
205 #define SHARED_HW_CFG_CLOCK_CHANGE_MASK 0x00000e00
206 #define SHARED_HW_CFG_CLOCK_CHANGE_SHIFT 9
208 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
209 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
210 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
212 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
214 #define SHARED_HW_CFG_WOL_CAPABLE_MASK 0x00004000
215 #define SHARED_HW_CFG_WOL_CAPABLE_DISABLED 0x00000000
216 #define SHARED_HW_CFG_WOL_CAPABLE_ENABLED 0x00004000
218 /* Output low when PERST is asserted */
219 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
220 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
221 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
223 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
224 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
225 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
226 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
227 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
228 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
230 /* The fan failure mechanism is usually related to the PHY type
231 since the power consumption of the board is determined by the PHY.
232 Currently, fan is required for most designs with SFX7101, BCM8727
233 and BCM8481. If a fan is not required for a board which uses one
234 of those PHYs, this field should be set to "Disabled". If a fan is
235 required for a different PHY type, this option should be set to
236 "Enabled". The fan failure indication is expected on SPIO5 */
237 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
238 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
239 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
240 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
241 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
243 /* ASPM Power Management support */
244 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
245 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
246 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
247 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
248 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
249 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
251 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
252 tl_control_0 (register 0x2800) */
253 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
254 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
255 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
257 #define SHARED_HW_CFG_PORT_MODE_MASK 0x01000000
258 #define SHARED_HW_CFG_PORT_MODE_2 0x00000000
259 #define SHARED_HW_CFG_PORT_MODE_4 0x01000000
261 #define SHARED_HW_CFG_PATH_SWAP_MASK 0x02000000
262 #define SHARED_HW_CFG_PATH_SWAP_DISABLED 0x00000000
263 #define SHARED_HW_CFG_PATH_SWAP_ENABLED 0x02000000
265 /* Set the MDC/MDIO access for the first external phy */
266 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
267 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
274 /* Set the MDC/MDIO access for the second external phy */
275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
284 u32 power_dissipated
; /* 0x11c */
285 #define SHARED_HW_CFG_POWER_MGNT_SCALE_MASK 0x00ff0000
286 #define SHARED_HW_CFG_POWER_MGNT_SCALE_SHIFT 16
287 #define SHARED_HW_CFG_POWER_MGNT_UNKNOWN_SCALE 0x00000000
288 #define SHARED_HW_CFG_POWER_MGNT_DOT_1_WATT 0x00010000
289 #define SHARED_HW_CFG_POWER_MGNT_DOT_01_WATT 0x00020000
290 #define SHARED_HW_CFG_POWER_MGNT_DOT_001_WATT 0x00030000
292 #define SHARED_HW_CFG_POWER_DIS_CMN_MASK 0xff000000
293 #define SHARED_HW_CFG_POWER_DIS_CMN_SHIFT 24
295 u32 ump_nc_si_config
; /* 0x120 */
296 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
297 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
303 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_MASK 0x00000f00
304 #define SHARED_HW_CFG_UMP_NC_SI_NUM_DEVS_SHIFT 8
306 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_MASK 0x00ff0000
307 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_SHIFT 16
308 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_NONE 0x00000000
309 #define SHARED_HW_CFG_UMP_NC_SI_EXT_PHY_TYPE_BCM5221 0x00010000
311 u32 board
; /* 0x124 */
312 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
313 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
314 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
315 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
316 /* Use the PIN_CFG_XXX defines on top */
317 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00ff0000
318 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0f000000
321 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
323 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xf0000000
324 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
326 u32 wc_lane_config
; /* 0x128 */
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
333 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
334 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
335 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
336 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
338 /* TX lane Polarity swap */
339 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
340 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
341 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
342 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
343 /* TX lane Polarity swap */
344 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
345 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
346 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
347 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
349 /* Selects the port layout of the board */
350 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
361 /****************************************************************************
362 * Port HW configuration *
363 ****************************************************************************/
364 struct port_hw_cfg
{ /* port 0: 0x12c port 1: 0x2bc */
367 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xffff0000
368 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000ffff
371 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xffff0000
372 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000ffff
374 u32 power_dissipated
;
375 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000ff
376 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
377 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000ff00
378 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
379 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00ff0000
380 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
381 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xff000000
382 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
385 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000ff
386 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
387 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000ff00
388 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
389 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00ff0000
390 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
391 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xff000000
392 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
395 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000ffff
396 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
399 u32 iscsi_mac_upper
; /* Upper 16 bits are always zeroes */
402 u32 rdma_mac_upper
; /* Upper 16 bits are always zeroes */
406 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000ffff
407 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
409 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xffff0000
410 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
413 /* Default values: 2P-64, 4P-32 */
414 u32 pf_config
; /* 0x158 */
415 #define PORT_HW_CFG_PF_NUM_VF_MASK 0x0000007F
416 #define PORT_HW_CFG_PF_NUM_VF_SHIFT 0
418 /* Default values: 17 */
419 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_MASK 0x00007F00
420 #define PORT_HW_CFG_PF_NUM_MSIX_VECTORS_SHIFT 8
422 #define PORT_HW_CFG_ENABLE_FLR_MASK 0x00010000
423 #define PORT_HW_CFG_FLR_ENABLED 0x00010000
425 u32 vf_config
; /* 0x15C */
426 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_MASK 0x0000007F
427 #define PORT_HW_CFG_VF_NUM_MSIX_VECTORS_SHIFT 0
429 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
430 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
432 u32 mf_pci_id
; /* 0x160 */
433 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
434 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
436 /* Controls the TX laser of the SFP+ module */
437 u32 sfp_ctrl
; /* 0x164 */
438 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
439 #define PORT_HW_CFG_TX_LASER_SHIFT 0
440 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
441 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
442 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
443 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
444 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
446 /* Controls the fault module LED of the SFP+ */
447 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
448 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
450 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
451 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
452 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
453 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
455 /* The output pin TX_DIS that controls the TX laser of the SFP+
456 module. Use the PIN_CFG_XXX defines on top */
457 u32 e3_sfp_ctrl
; /* 0x168 */
458 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
459 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
461 /* The output pin for SFPP_TYPE which turns on the Fault module LED */
462 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
463 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
465 /* The input pin MOD_ABS that indicates whether SFP+ module is
466 present or not. Use the PIN_CFG_XXX defines on top */
467 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
468 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
470 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
471 module. Use the PIN_CFG_XXX defines on top */
472 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
473 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
476 * The input pin which signals module transmit fault. Use the
477 * PIN_CFG_XXX defines on top
479 u32 e3_cmn_pin_cfg
; /* 0x16C */
480 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
481 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
483 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
485 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
486 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
489 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
492 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
493 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
495 /* The output pin values BSC_SEL which selects the I2C for this port
497 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
498 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
502 * The input pin I_FAULT which indicate over-current has occurred.
503 * Use the PIN_CFG_XXX defines on top
505 u32 e3_cmn_pin_cfg1
; /* 0x170 */
506 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
507 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
508 u32 reserved0
[7]; /* 0x174 */
510 u32 aeu_int_mask
; /* 0x190 */
512 u32 media_type
; /* 0x194 */
513 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
514 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
516 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
517 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
519 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
520 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
522 /* 4 times 16 bits for all 4 lanes. In case external PHY is present
523 (not direct mode), those values will not take effect on the 4 XGXS
524 lanes. For some external PHYs (such as 8706 and 8726) the values
525 will be used to configure the external PHY in those cases, not
526 all 4 values are needed. */
527 u16 xgxs_config_rx
[4]; /* 0x198 */
528 u16 xgxs_config_tx
[4]; /* 0x1A0 */
530 /* For storing FCOE mac on shared memory */
531 u32 fcoe_fip_mac_upper
;
532 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
533 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
534 u32 fcoe_fip_mac_lower
;
536 u32 fcoe_wwn_port_name_upper
;
537 u32 fcoe_wwn_port_name_lower
;
539 u32 fcoe_wwn_node_name_upper
;
540 u32 fcoe_wwn_node_name_lower
;
542 u32 Reserved1
[49]; /* 0x1C0 */
544 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
546 u32 xgbt_phy_cfg
; /* 0x284 */
547 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
548 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
550 u32 default_cfg
; /* 0x288 */
551 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
552 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
553 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
554 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
555 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
556 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
558 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
559 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
560 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
561 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
562 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
563 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
565 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
566 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
567 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
568 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
569 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
570 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
572 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
573 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
574 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
575 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
576 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
577 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
579 /* When KR link is required to be set to force which is not
580 KR-compliant, this parameter determine what is the trigger for it.
581 When GPIO is selected, low input will force the speed. Currently
582 default speed is 1G. In the future, it may be widen to select the
583 forced speed in with another parameter. Note when force-1G is
584 enabled, it override option 56: Link Speed option. */
585 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
586 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
587 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
588 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
589 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
590 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
591 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
592 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
593 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
594 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
595 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
596 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
597 /* Enable to determine with which GPIO to reset the external phy */
598 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
599 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
600 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
601 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
602 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
603 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
604 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
605 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
606 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
607 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
608 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
610 /* Enable BAM on KR */
611 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
612 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
613 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
614 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
616 /* Enable Common Mode Sense */
617 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
618 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
619 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
620 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
622 /* Determine the Serdes electrical interface */
623 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
624 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
625 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
626 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
627 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
628 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
629 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
630 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
633 u32 speed_capability_mask2
; /* 0x28C */
634 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
635 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
636 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
637 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3__ 0x00000002
638 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3___ 0x00000004
639 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
640 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
641 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_DOT_5G 0x00000020
642 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
643 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
645 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
646 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
647 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
648 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0__ 0x00020000
649 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0___ 0x00040000
650 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
651 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
652 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_DOT_5G 0x00200000
653 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
654 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
657 /* In the case where two media types (e.g. copper and fiber) are
658 present and electrically active at the same time, PHY Selection
659 will determine which of the two PHYs will be designated as the
660 Active PHY and used for a connection to the network. */
661 u32 multi_phy_config
; /* 0x290 */
662 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
663 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
664 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
665 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
666 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
667 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
668 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
670 /* When enabled, all second phy nvram parameters will be swapped
671 with the first phy parameters */
672 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
673 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
674 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
675 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
678 /* Address of the second external phy */
679 u32 external_phy_config2
; /* 0x294 */
680 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
681 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
683 /* The second XGXS external PHY type */
684 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
685 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
686 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
687 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
688 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
689 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
690 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
691 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
692 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
693 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
694 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
695 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
696 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
697 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
698 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
699 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
700 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
701 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
702 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
703 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
704 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
707 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
708 8706, 8726 and 8727) not all 4 values are needed. */
709 u16 xgxs_config2_rx
[4]; /* 0x296 */
710 u16 xgxs_config2_tx
[4]; /* 0x2A0 */
713 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000ffff
714 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
716 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
718 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
720 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
722 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
723 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000ff
724 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
725 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000ff00
726 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
727 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000c000
728 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
730 /* Indicate whether to swap the external phy polarity */
731 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
732 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
733 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
736 u32 external_phy_config
;
737 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000ff
738 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
740 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000ff00
741 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
742 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
743 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
744 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
745 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
746 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
747 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
748 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
749 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
750 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
751 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
752 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
753 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
754 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
755 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
756 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
757 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
758 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
759 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
760 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
761 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
763 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00ff0000
764 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
766 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xff000000
767 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
768 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
769 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
770 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
771 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
773 u32 speed_capability_mask
;
774 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000ffff
775 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
776 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
777 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
778 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
779 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
780 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
781 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
782 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
783 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
784 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
786 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xffff0000
787 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
788 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
789 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
790 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
791 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
792 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
793 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
794 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
795 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
796 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
798 /* A place to hold the original MAC address as a backup */
799 u32 backup_mac_upper
; /* 0x2B4 */
800 u32 backup_mac_lower
; /* 0x2B8 */
805 /****************************************************************************
806 * Shared Feature configuration *
807 ****************************************************************************/
808 struct shared_feat_cfg
{ /* NVRAM Offset */
810 u32 config
; /* 0x450 */
811 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
813 /* Use NVRAM values instead of HW default values */
814 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
816 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
818 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
821 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
822 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
823 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
825 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
826 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
828 /* Override the OTP back to single function mode. When using GPIO,
829 high means only SF, 0 is according to CLP configuration */
830 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
831 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
832 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
833 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
834 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
835 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
837 /* The interval in seconds between sending LLDP packets. Set to zero
838 to disable the feature */
839 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00ff0000
840 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
842 /* The assigned device type ID for LLDP usage */
843 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xff000000
844 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
849 /****************************************************************************
850 * Port Feature configuration *
851 ****************************************************************************/
852 struct port_feat_cfg
{ /* port 0: 0x454 port 1: 0x4c8 */
855 #define PORT_FEATURE_BAR1_SIZE_MASK 0x0000000f
856 #define PORT_FEATURE_BAR1_SIZE_SHIFT 0
857 #define PORT_FEATURE_BAR1_SIZE_DISABLED 0x00000000
858 #define PORT_FEATURE_BAR1_SIZE_64K 0x00000001
859 #define PORT_FEATURE_BAR1_SIZE_128K 0x00000002
860 #define PORT_FEATURE_BAR1_SIZE_256K 0x00000003
861 #define PORT_FEATURE_BAR1_SIZE_512K 0x00000004
862 #define PORT_FEATURE_BAR1_SIZE_1M 0x00000005
863 #define PORT_FEATURE_BAR1_SIZE_2M 0x00000006
864 #define PORT_FEATURE_BAR1_SIZE_4M 0x00000007
865 #define PORT_FEATURE_BAR1_SIZE_8M 0x00000008
866 #define PORT_FEATURE_BAR1_SIZE_16M 0x00000009
867 #define PORT_FEATURE_BAR1_SIZE_32M 0x0000000a
868 #define PORT_FEATURE_BAR1_SIZE_64M 0x0000000b
869 #define PORT_FEATURE_BAR1_SIZE_128M 0x0000000c
870 #define PORT_FEATURE_BAR1_SIZE_256M 0x0000000d
871 #define PORT_FEATURE_BAR1_SIZE_512M 0x0000000e
872 #define PORT_FEATURE_BAR1_SIZE_1G 0x0000000f
873 #define PORT_FEATURE_BAR2_SIZE_MASK 0x000000f0
874 #define PORT_FEATURE_BAR2_SIZE_SHIFT 4
875 #define PORT_FEATURE_BAR2_SIZE_DISABLED 0x00000000
876 #define PORT_FEATURE_BAR2_SIZE_64K 0x00000010
877 #define PORT_FEATURE_BAR2_SIZE_128K 0x00000020
878 #define PORT_FEATURE_BAR2_SIZE_256K 0x00000030
879 #define PORT_FEATURE_BAR2_SIZE_512K 0x00000040
880 #define PORT_FEATURE_BAR2_SIZE_1M 0x00000050
881 #define PORT_FEATURE_BAR2_SIZE_2M 0x00000060
882 #define PORT_FEATURE_BAR2_SIZE_4M 0x00000070
883 #define PORT_FEATURE_BAR2_SIZE_8M 0x00000080
884 #define PORT_FEATURE_BAR2_SIZE_16M 0x00000090
885 #define PORT_FEATURE_BAR2_SIZE_32M 0x000000a0
886 #define PORT_FEATURE_BAR2_SIZE_64M 0x000000b0
887 #define PORT_FEATURE_BAR2_SIZE_128M 0x000000c0
888 #define PORT_FEATURE_BAR2_SIZE_256M 0x000000d0
889 #define PORT_FEATURE_BAR2_SIZE_512M 0x000000e0
890 #define PORT_FEATURE_BAR2_SIZE_1G 0x000000f0
892 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
893 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
894 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
896 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
897 #define PORT_FEATURE_EN_SIZE_SHIFT 24
898 #define PORT_FEATURE_WOL_ENABLED 0x01000000
899 #define PORT_FEATURE_MBA_ENABLED 0x02000000
900 #define PORT_FEATURE_MFW_ENABLED 0x04000000
902 /* Advertise expansion ROM even if MBA is disabled */
903 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
904 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
905 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
907 /* Check the optic vendor via i2c against a list of approved modules
908 in a separate nvram image */
909 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xe0000000
910 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
911 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
913 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
915 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
916 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
919 /* Default is used when driver sets to "auto" mode */
920 #define PORT_FEATURE_WOL_DEFAULT_MASK 0x00000003
921 #define PORT_FEATURE_WOL_DEFAULT_SHIFT 0
922 #define PORT_FEATURE_WOL_DEFAULT_DISABLE 0x00000000
923 #define PORT_FEATURE_WOL_DEFAULT_MAGIC 0x00000001
924 #define PORT_FEATURE_WOL_DEFAULT_ACPI 0x00000002
925 #define PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x00000003
926 #define PORT_FEATURE_WOL_RES_PAUSE_CAP 0x00000004
927 #define PORT_FEATURE_WOL_RES_ASYM_PAUSE_CAP 0x00000008
928 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
931 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
932 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
933 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
934 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
935 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
936 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
937 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
938 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
940 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
941 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
943 #define PORT_FEATURE_MBA_RES_PAUSE_CAP 0x00000100
944 #define PORT_FEATURE_MBA_RES_ASYM_PAUSE_CAP 0x00000200
945 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
946 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
947 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
948 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
949 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000ff000
950 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
951 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
952 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
953 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
954 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
955 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
956 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
957 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
958 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
959 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
960 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
961 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
962 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
963 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
964 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
965 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
966 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
967 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00f00000
968 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
969 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
970 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
971 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
972 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
973 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
974 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
975 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c000000
976 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
977 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
978 #define PORT_FEATURE_MBA_LINK_SPEED_10HD 0x04000000
979 #define PORT_FEATURE_MBA_LINK_SPEED_10FD 0x08000000
980 #define PORT_FEATURE_MBA_LINK_SPEED_100HD 0x0c000000
981 #define PORT_FEATURE_MBA_LINK_SPEED_100FD 0x10000000
982 #define PORT_FEATURE_MBA_LINK_SPEED_1GBPS 0x14000000
983 #define PORT_FEATURE_MBA_LINK_SPEED_2_5GBPS 0x18000000
984 #define PORT_FEATURE_MBA_LINK_SPEED_10GBPS_CX4 0x1c000000
985 #define PORT_FEATURE_MBA_LINK_SPEED_20GBPS 0x20000000
987 #define PORT_FEATURE_BMC_LINK_OVERRIDE_MASK 0x00000001
988 #define PORT_FEATURE_BMC_LINK_OVERRIDE_DEFAULT 0x00000000
989 #define PORT_FEATURE_BMC_LINK_OVERRIDE_EN 0x00000001
992 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000ffff
993 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
994 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
997 #define PORT_FEATURE_RESOURCE_CFG_VALID 0x00000001
998 #define PORT_FEATURE_RESOURCE_CFG_DIAG 0x00000002
999 #define PORT_FEATURE_RESOURCE_CFG_L2 0x00000004
1000 #define PORT_FEATURE_RESOURCE_CFG_ISCSI 0x00000008
1001 #define PORT_FEATURE_RESOURCE_CFG_RDMA 0x00000010
1004 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1005 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1008 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000f
1009 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1010 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1011 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1012 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1013 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1014 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1015 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1016 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1017 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1018 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1019 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1020 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1021 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1022 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1023 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1024 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1025 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1027 u32 link_config
; /* Used as HW defaults for the driver */
1028 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1029 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1030 /* (forced) low speed switch (< 10G) */
1031 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1032 /* (forced) high speed switch (>= 10G) */
1033 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1034 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1035 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1037 #define PORT_FEATURE_LINK_SPEED_MASK 0x000f0000
1038 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1039 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1040 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000
1041 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000
1042 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1043 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1044 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1045 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1046 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1047 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1049 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1050 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1051 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1052 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1053 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1054 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1055 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1057 /* The default for MCP link configuration,
1058 uses the same defines as link_config */
1059 u32 mfw_wol_link_cfg
;
1061 /* The default for the driver of the second external phy,
1062 uses the same defines as link_config */
1063 u32 link_config2
; /* 0x47C */
1065 /* The default for MCP of the second external phy,
1066 uses the same defines as link_config */
1067 u32 mfw_wol_link_cfg2
; /* 0x480 */
1069 u32 Reserved2
[17]; /* 0x484 */
1074 /****************************************************************************
1075 * Device Information *
1076 ****************************************************************************/
1077 struct shm_dev_info
{ /* size */
1079 u32 bc_rev
; /* 8 bits each: major, minor, build */ /* 4 */
1081 struct shared_hw_cfg shared_hw_config
; /* 40 */
1083 struct port_hw_cfg port_hw_config
[PORT_MAX
]; /* 400*2=800 */
1085 struct shared_feat_cfg shared_feature_config
; /* 4 */
1087 struct port_feat_cfg port_feature_config
[PORT_MAX
];/* 116*2=232 */
1092 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1093 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1104 #define E1_FUNC_MAX 2
1105 #define E1H_FUNC_MAX 8
1106 #define E2_FUNC_MAX 4 /* per path */
1115 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1116 /* This value (in milliseconds) determines the frequency of the driver
1117 * issuing the PULSE message code. The firmware monitors this periodic
1118 * pulse to determine when to switch to an OS-absent mode. */
1119 #define DRV_PULSE_PERIOD_MS 250
1121 /* This value (in milliseconds) determines how long the driver should
1122 * wait for an acknowledgement from the firmware before timing out. Once
1123 * the firmware has timed out, the driver will assume there is no firmware
1124 * running and there won't be any firmware-driver synchronization during a
1126 #define FW_ACK_TIME_OUT_MS 5000
1128 #define FW_ACK_POLL_TIME_MS 1
1130 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1132 #define MFW_TRACE_SIGNATURE 0x54524342
1134 /****************************************************************************
1135 * Driver <-> FW Mailbox *
1136 ****************************************************************************/
1137 struct drv_port_mb
{
1140 /* Driver should update this field on any link change event */
1142 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1143 #define LINK_STATUS_LINK_UP 0x00000001
1144 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1145 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1146 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1147 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1148 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1149 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1150 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1151 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1152 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1153 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1154 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1155 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1156 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1157 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1158 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1159 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1160 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1162 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1163 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1165 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1166 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1167 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1169 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1170 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1171 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1172 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1173 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1174 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1175 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1177 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1178 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1180 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1181 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1183 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1184 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1185 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1186 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1187 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1189 #define LINK_STATUS_SERDES_LINK 0x00100000
1191 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1192 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1193 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1194 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1196 #define LINK_STATUS_PFC_ENABLED 0x20000000
1198 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1204 /* MCP firmware does not use this field */
1205 u32 ext_phy_fw_version
;
1210 struct drv_func_mb
{
1213 #define DRV_MSG_CODE_MASK 0xffff0000
1214 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1215 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1216 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1217 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1218 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1219 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1220 #define DRV_MSG_CODE_DCC_OK 0x30000000
1221 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1222 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1223 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1224 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1225 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1226 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1227 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1228 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1230 * The optic module verification command requires bootcode
1231 * v5.0.6 or later, te specific optic module verification command
1232 * requires bootcode v5.2.12 or later
1234 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1235 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1236 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1237 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1238 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1239 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1241 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1242 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1244 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1245 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1246 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1248 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1249 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1250 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1252 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1254 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1255 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1256 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1257 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1259 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1262 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1263 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1266 #define FW_MSG_CODE_MASK 0xffff0000
1267 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1268 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1269 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1270 /* Load common chip is supported from bc 6.0.0 */
1271 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1272 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1274 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1275 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1276 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1277 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1278 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1279 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1280 #define FW_MSG_CODE_DCC_DONE 0x30100000
1281 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1282 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1283 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1284 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1285 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1286 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1287 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1288 #define FW_MSG_CODE_NO_KEY 0x80f00000
1289 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1290 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1291 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1292 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1293 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1294 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1295 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1296 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1297 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1298 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1299 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1300 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1302 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1303 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1305 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1307 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1308 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1309 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1310 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1312 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1317 #define DRV_PULSE_SEQ_MASK 0x00007fff
1318 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1320 * The system time is in the format of
1321 * (year-2001)*12*32 + month*32 + day.
1323 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1325 * Indicate to the firmware not to go into the
1326 * OS-absent when it is not getting driver pulse.
1327 * This is used for debugging as well for PXE(MBA).
1331 #define MCP_PULSE_SEQ_MASK 0x00007fff
1332 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1333 /* Indicates to the driver not to assert due to lack
1334 * of MCP response */
1335 #define MCP_EVENT_MASK 0xffff0000
1336 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1338 u32 iscsi_boot_signature
;
1339 u32 iscsi_boot_block_offset
;
1342 #define DRV_STATUS_PMF 0x00000001
1343 #define DRV_STATUS_VF_DISABLED 0x00000002
1344 #define DRV_STATUS_SET_MF_BW 0x00000004
1345 #define DRV_STATUS_LINK_EVENT 0x00000008
1347 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1348 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1349 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1350 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1351 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1352 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1353 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1355 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1356 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1357 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1360 #define VIRT_MAC_SIGN_MASK 0xffff0000
1361 #define VIRT_MAC_SIGNATURE 0x564d0000
1367 /****************************************************************************
1368 * Management firmware state *
1369 ****************************************************************************/
1370 /* Allocate 440 bytes for management firmware */
1371 #define MGMTFW_STATE_WORD_SIZE 110
1373 struct mgmtfw_state
{
1374 u32 opaque
[MGMTFW_STATE_WORD_SIZE
];
1378 /****************************************************************************
1379 * Multi-Function configuration *
1380 ****************************************************************************/
1381 struct shared_mf_cfg
{
1384 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1386 #define SHARED_MF_CLP_EXIT 0x00000001
1388 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1392 struct port_mf_cfg
{
1394 u32 dynamic_cfg
; /* device control channel */
1395 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1396 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1397 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1403 struct func_mf_cfg
{
1407 /* function 0 of each port cannot be hidden */
1408 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1410 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1411 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1412 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1413 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1414 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1415 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1416 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1418 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1419 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1422 /* 0 - low priority, 3 - high priority */
1423 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1424 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1425 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1428 /* value range - 0..100, increments in 100Mbps */
1429 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1430 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1431 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1432 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1433 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1434 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1436 u32 mac_upper
; /* MAC */
1437 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1438 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1439 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1441 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1443 u32 e1hov_tag
; /* VNI */
1444 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1445 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1446 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1451 /* This structure is not applicable and should not be accessed on 57711 */
1452 struct func_ext_cfg
{
1454 #define MACP_FUNC_CFG_FLAGS_MASK 0x000000FF
1455 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
1456 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
1457 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
1458 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
1459 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
1461 u32 iscsi_mac_addr_upper
;
1462 u32 iscsi_mac_addr_lower
;
1464 u32 fcoe_mac_addr_upper
;
1465 u32 fcoe_mac_addr_lower
;
1467 u32 fcoe_wwn_port_name_upper
;
1468 u32 fcoe_wwn_port_name_lower
;
1470 u32 fcoe_wwn_node_name_upper
;
1471 u32 fcoe_wwn_node_name_lower
;
1474 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
1475 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
1476 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
1477 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
1478 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
1479 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
1484 struct shared_mf_cfg shared_mf_config
; /* 0x4 */
1486 struct port_mf_cfg port_mf_config
[NVM_PATH_MAX
][PORT_MAX
];
1487 /* for all chips, there are 8 mf functions */
1488 struct func_mf_cfg func_mf_config
[E1H_FUNC_MAX
]; /* 0x18 * 8 = 0xc0 */
1490 * Extended configuration per function - this array does not exist and
1491 * should not be accessed on 57711
1493 struct func_ext_cfg func_ext_config
[E1H_FUNC_MAX
]; /* 0x28 * 8 = 0x140*/
1496 /****************************************************************************
1497 * Shared Memory Region *
1498 ****************************************************************************/
1499 struct shmem_region
{ /* SharedMem Offset (size) */
1501 u32 validity_map
[PORT_MAX
]; /* 0x0 (4*2 = 0x8) */
1502 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
1503 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
1505 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
1506 #define SHR_MEM_VALIDITY_MB 0x00200000
1507 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
1508 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
1509 /* One licensing bit should be set */
1510 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
1511 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
1512 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
1513 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
1515 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
1516 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
1517 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
1518 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
1519 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
1520 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
1522 struct shm_dev_info dev_info
; /* 0x8 (0x438) */
1524 struct license_key drv_lic_key
[PORT_MAX
]; /* 0x440 (52*2=0x68) */
1526 /* FW information (for internal FW use) */
1527 u32 fw_info_fio_offset
; /* 0x4a8 (0x4) */
1528 struct mgmtfw_state mgmtfw_state
; /* 0x4ac (0x1b8) */
1530 struct drv_port_mb port_mb
[PORT_MAX
]; /* 0x664 (16*2=0x20) */
1533 /* This is a variable length array */
1534 /* the number of function depends on the chip type */
1535 struct drv_func_mb func_mb
[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1537 /* the number of function depends on the chip type */
1538 struct drv_func_mb func_mb
[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
1541 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
1543 /****************************************************************************
1544 * Shared Memory 2 Region *
1545 ****************************************************************************/
1546 /* The fw_flr_ack is actually built in the following way: */
1548 /* 64 bit: VF ack */
1549 /* 8 bit: ios_dis_ack */
1550 /* In order to maintain endianity in the mailbox hsi, we want to keep using */
1551 /* u32. The fw must have the VF right after the PF since this is how it */
1552 /* access arrays(it expects always the VF to reside after the PF, and that */
1553 /* makes the calculation much easier for it. ) */
1554 /* In order to answer both limitations, and keep the struct small, the code */
1555 /* will abuse the structure defined here to achieve the actual partition */
1557 /****************************************************************************/
1567 struct fw_flr_ack ack
;
1570 /**** SUPPORT FOR SHMEM ARRRAYS ***
1571 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
1572 * define arrays with storage types smaller then unsigned dwords.
1573 * The macros below add generic support for SHMEM arrays with numeric elements
1574 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
1575 * array with individual bit-filed elements accessed using shifts and masks.
1579 /* eb is the bitwidth of a single element */
1580 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
1581 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
1583 /* the bit-position macro allows the used to flip the order of the arrays
1584 * elements on a per byte or word boundary.
1586 * example: an array with 8 entries each 4 bit wide. This array will fit into
1587 * a single dword. The diagrmas below show the array order of the nibbles.
1589 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
1592 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
1595 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
1598 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
1601 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
1604 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
1607 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \
1608 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
1609 (((i)%((fb)/(eb))) * (eb)))
1611 #define SHMEM_ARRAY_GET(a, i, eb, fb) \
1612 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
1613 SHMEM_ARRAY_MASK(eb))
1615 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
1617 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
1618 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1619 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
1620 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
1624 /****START OF DCBX STRUCTURES DECLARATIONS****/
1625 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
1626 #define DCBX_PRI_PG_BITWIDTH 4
1627 #define DCBX_PRI_PG_FBITS 8
1628 #define DCBX_PRI_PG_GET(a, i) \
1629 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
1630 #define DCBX_PRI_PG_SET(a, i, val) \
1631 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
1632 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8
1633 #define DCBX_BW_PG_BITWIDTH 8
1634 #define DCBX_PG_BW_GET(a, i) \
1635 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
1636 #define DCBX_PG_BW_SET(a, i, val) \
1637 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
1638 #define DCBX_STRICT_PRI_PG 15
1639 #define DCBX_MAX_APP_PROTOCOL 16
1640 #define FCOE_APP_IDX 0
1641 #define ISCSI_APP_IDX 1
1642 #define PREDEFINED_APP_IDX_MAX 2
1645 /* Big/Little endian have the same representation. */
1646 struct dcbx_ets_feature
{
1648 * For Admin MIB - is this feature supported by the
1649 * driver | For Local MIB - should this feature be enabled.
1656 /* Driver structure in LE */
1657 struct dcbx_pfc_feature
{
1660 #define DCBX_PFC_PRI_0 0x01
1661 #define DCBX_PFC_PRI_1 0x02
1662 #define DCBX_PFC_PRI_2 0x04
1663 #define DCBX_PFC_PRI_3 0x08
1664 #define DCBX_PFC_PRI_4 0x10
1665 #define DCBX_PFC_PRI_5 0x20
1666 #define DCBX_PFC_PRI_6 0x40
1667 #define DCBX_PFC_PRI_7 0x80
1671 #elif defined(__LITTLE_ENDIAN)
1676 #define DCBX_PFC_PRI_0 0x01
1677 #define DCBX_PFC_PRI_1 0x02
1678 #define DCBX_PFC_PRI_2 0x04
1679 #define DCBX_PFC_PRI_3 0x08
1680 #define DCBX_PFC_PRI_4 0x10
1681 #define DCBX_PFC_PRI_5 0x20
1682 #define DCBX_PFC_PRI_6 0x40
1683 #define DCBX_PFC_PRI_7 0x80
1687 struct dcbx_app_priority_entry
{
1692 #define DCBX_APP_ENTRY_VALID 0x01
1693 #define DCBX_APP_ENTRY_SF_MASK 0x30
1694 #define DCBX_APP_ENTRY_SF_SHIFT 4
1695 #define DCBX_APP_SF_ETH_TYPE 0x10
1696 #define DCBX_APP_SF_PORT 0x20
1697 #elif defined(__LITTLE_ENDIAN)
1699 #define DCBX_APP_ENTRY_VALID 0x01
1700 #define DCBX_APP_ENTRY_SF_MASK 0x30
1701 #define DCBX_APP_ENTRY_SF_SHIFT 4
1702 #define DCBX_APP_SF_ETH_TYPE 0x10
1703 #define DCBX_APP_SF_PORT 0x20
1710 /* FW structure in BE */
1711 struct dcbx_app_priority_feature
{
1717 #elif defined(__LITTLE_ENDIAN)
1723 struct dcbx_app_priority_entry app_pri_tbl
[DCBX_MAX_APP_PROTOCOL
];
1726 /* FW structure in BE */
1727 struct dcbx_features
{
1729 struct dcbx_ets_feature ets
;
1731 struct dcbx_pfc_feature pfc
;
1733 struct dcbx_app_priority_feature app
;
1736 /* LLDP protocol parameters */
1737 /* FW structure in BE */
1738 struct lldp_params
{
1740 u8 msg_fast_tx_interval
;
1744 #define LLDP_TX_ONLY 0x01
1745 #define LLDP_RX_ONLY 0x02
1746 #define LLDP_TX_RX 0x03
1747 #define LLDP_DISABLED 0x04
1752 #elif defined(__LITTLE_ENDIAN)
1754 #define LLDP_TX_ONLY 0x01
1755 #define LLDP_RX_ONLY 0x02
1756 #define LLDP_TX_RX 0x03
1757 #define LLDP_DISABLED 0x04
1760 u8 msg_fast_tx_interval
;
1766 #define REM_CHASSIS_ID_STAT_LEN 4
1767 #define REM_PORT_ID_STAT_LEN 4
1768 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
1769 u32 peer_chassis_id
[REM_CHASSIS_ID_STAT_LEN
];
1770 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
1771 u32 peer_port_id
[REM_PORT_ID_STAT_LEN
];
1774 struct lldp_dcbx_stat
{
1775 #define LOCAL_CHASSIS_ID_STAT_LEN 2
1776 #define LOCAL_PORT_ID_STAT_LEN 2
1777 /* Holds local Chassis ID 8B payload of constant subtype 4. */
1778 u32 local_chassis_id
[LOCAL_CHASSIS_ID_STAT_LEN
];
1779 /* Holds local Port ID 8B payload of constant subtype 3. */
1780 u32 local_port_id
[LOCAL_PORT_ID_STAT_LEN
];
1781 /* Number of DCBX frames transmitted. */
1782 u32 num_tx_dcbx_pkts
;
1783 /* Number of DCBX frames received. */
1784 u32 num_rx_dcbx_pkts
;
1787 /* ADMIN MIB - DCBX local machine default configuration. */
1788 struct lldp_admin_mib
{
1790 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
1791 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
1792 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
1793 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
1794 #define DCBX_ETS_RECO_VALID 0x00000010
1795 #define DCBX_ETS_WILLING 0x00000020
1796 #define DCBX_PFC_WILLING 0x00000040
1797 #define DCBX_APP_WILLING 0x00000080
1798 #define DCBX_VERSION_CEE 0x00000100
1799 #define DCBX_VERSION_IEEE 0x00000200
1800 #define DCBX_DCBX_ENABLED 0x00000400
1801 #define DCBX_CEE_VERSION_MASK 0x0000f000
1802 #define DCBX_CEE_VERSION_SHIFT 12
1803 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
1804 #define DCBX_CEE_MAX_VERSION_SHIFT 16
1805 struct dcbx_features features
;
1808 /* REMOTE MIB - remote machine DCBX configuration. */
1809 struct lldp_remote_mib
{
1812 #define DCBX_ETS_TLV_RX 0x00000001
1813 #define DCBX_PFC_TLV_RX 0x00000002
1814 #define DCBX_APP_TLV_RX 0x00000004
1815 #define DCBX_ETS_RX_ERROR 0x00000010
1816 #define DCBX_PFC_RX_ERROR 0x00000020
1817 #define DCBX_APP_RX_ERROR 0x00000040
1818 #define DCBX_ETS_REM_WILLING 0x00000100
1819 #define DCBX_PFC_REM_WILLING 0x00000200
1820 #define DCBX_APP_REM_WILLING 0x00000400
1821 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
1822 #define DCBX_REMOTE_MIB_VALID 0x00002000
1823 struct dcbx_features features
;
1827 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
1828 struct lldp_local_mib
{
1830 /* Indicates if there is mismatch with negotiation results. */
1832 #define DCBX_LOCAL_ETS_ERROR 0x00000001
1833 #define DCBX_LOCAL_PFC_ERROR 0x00000002
1834 #define DCBX_LOCAL_APP_ERROR 0x00000004
1835 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
1836 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
1837 #define DCBX_REMOTE_MIB_ERROR 0x00000040
1838 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
1839 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
1840 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
1841 struct dcbx_features features
;
1844 /***END OF DCBX STRUCTURES DECLARATIONS***/
1846 struct ncsi_oem_fcoe_features
{
1848 #define FCOE_FEATURES1_IOS_PER_CONNECTION_MASK 0x0000FFFF
1849 #define FCOE_FEATURES1_IOS_PER_CONNECTION_OFFSET 0
1851 #define FCOE_FEATURES1_LOGINS_PER_PORT_MASK 0xFFFF0000
1852 #define FCOE_FEATURES1_LOGINS_PER_PORT_OFFSET 16
1855 #define FCOE_FEATURES2_EXCHANGES_MASK 0x0000FFFF
1856 #define FCOE_FEATURES2_EXCHANGES_OFFSET 0
1858 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_MASK 0xFFFF0000
1859 #define FCOE_FEATURES2_NPIV_WWN_PER_PORT_OFFSET 16
1862 #define FCOE_FEATURES3_TARGETS_SUPPORTED_MASK 0x0000FFFF
1863 #define FCOE_FEATURES3_TARGETS_SUPPORTED_OFFSET 0
1865 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_MASK 0xFFFF0000
1866 #define FCOE_FEATURES3_OUTSTANDING_COMMANDS_OFFSET 16
1869 #define FCOE_FEATURES4_FEATURE_SETTINGS_MASK 0x0000000F
1870 #define FCOE_FEATURES4_FEATURE_SETTINGS_OFFSET 0
1873 struct ncsi_oem_data
{
1874 u32 driver_version
[4];
1875 struct ncsi_oem_fcoe_features ncsi_oem_fcoe_features
;
1878 struct shmem2_region
{
1880 u32 size
; /* 0x0000 */
1882 u32 dcc_support
; /* 0x0004 */
1883 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
1884 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
1885 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
1886 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
1887 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
1888 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
1890 u32 ext_phy_fw_version2
[PORT_MAX
]; /* 0x0008 */
1892 * For backwards compatibility, if the mf_cfg_addr does not exist
1893 * (the size filed is smaller than 0xc) the mf_cfg resides at the
1894 * end of struct shmem_region
1896 u32 mf_cfg_addr
; /* 0x0010 */
1897 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
1899 struct fw_flr_mb flr_mb
; /* 0x0014 */
1900 u32 dcbx_lldp_params_offset
; /* 0x0028 */
1901 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
1902 u32 dcbx_neg_res_offset
; /* 0x002c */
1903 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
1904 u32 dcbx_remote_mib_offset
; /* 0x0030 */
1905 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
1907 * The other shmemX_base_addr holds the other path's shmem address
1908 * required for example in case of common phy init, or for path1 to know
1909 * the address of mcp debug trace which is located in offset from shmem
1912 u32 other_shmem_base_addr
; /* 0x0034 */
1913 u32 other_shmem2_base_addr
; /* 0x0038 */
1915 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
1916 * which were disabled/flred
1918 u32 mcp_vf_disabled
[E2_VF_MAX
/ 32]; /* 0x003c */
1921 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
1924 u32 drv_ack_vf_disabled
[E2_FUNC_MAX
][E2_VF_MAX
/ 32]; /* 0x0044 */
1926 u32 dcbx_lldp_dcbx_stat_offset
; /* 0x0064 */
1927 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
1930 * edebug_driver_if field is used to transfer messages between edebug
1931 * app to the driver through shmem2.
1934 * bits 0-2 - function number / instance of driver to perform request
1935 * bits 3-5 - op code / is_ack?
1938 u32 edebug_driver_if
[2]; /* 0x0068 */
1939 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
1940 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
1941 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
1943 u32 nvm_retain_bitmap_addr
; /* 0x0070 */
1945 u32 reserved1
; /* 0x0074 */
1947 u32 reserved2
[E2_FUNC_MAX
];
1949 u32 reserved3
[E2_FUNC_MAX
];/* 0x0088 */
1950 u32 reserved4
[E2_FUNC_MAX
];/* 0x0098 */
1952 u32 swim_base_addr
; /* 0x0108 */
1958 /* generic flags controlled by the driver */
1960 #define DRV_FLAGS_DCB_CONFIGURED 0x1
1962 /* pointer to extended dev_info shared data copied from nvm image */
1963 u32 extended_dev_info_shared_addr
;
1964 u32 ncsi_oem_data_addr
;
1966 u32 ocsd_host_addr
; /* initialized by option ROM */
1967 u32 ocbb_host_addr
; /* initialized by option ROM */
1968 u32 ocsd_req_update_interval
; /* initialized by option ROM */
1969 u32 temperature_in_half_celsius
;
1970 u32 glob_struct_in_host
;
1972 u32 dcbx_neg_res_ext_offset
;
1973 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
1975 u32 drv_capabilities_flag
[E2_FUNC_MAX
];
1976 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
1977 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
1978 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
1979 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
1981 u32 extended_dev_info_shared_cfg_size
;
1983 u32 dcbx_en
[PORT_MAX
];
1985 /* The offset points to the multi threaded meta structure */
1986 u32 multi_thread_data_offset
;
1988 /* address of DMAable host address holding values from the drivers */
1989 u32 drv_info_host_addr_lo
;
1990 u32 drv_info_host_addr_hi
;
1992 /* general values written by the MFW (such as current version) */
1993 u32 drv_info_control
;
1994 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
1995 #define DRV_INFO_CONTROL_VER_SHIFT 0
1996 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
1997 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
1998 u32 ibft_host_addr
; /* initialized by option ROM */
2003 u32 rx_stat_ifhcinoctets
;
2004 u32 rx_stat_ifhcinbadoctets
;
2005 u32 rx_stat_etherstatsfragments
;
2006 u32 rx_stat_ifhcinucastpkts
;
2007 u32 rx_stat_ifhcinmulticastpkts
;
2008 u32 rx_stat_ifhcinbroadcastpkts
;
2009 u32 rx_stat_dot3statsfcserrors
;
2010 u32 rx_stat_dot3statsalignmenterrors
;
2011 u32 rx_stat_dot3statscarriersenseerrors
;
2012 u32 rx_stat_xonpauseframesreceived
;
2013 u32 rx_stat_xoffpauseframesreceived
;
2014 u32 rx_stat_maccontrolframesreceived
;
2015 u32 rx_stat_xoffstateentered
;
2016 u32 rx_stat_dot3statsframestoolong
;
2017 u32 rx_stat_etherstatsjabbers
;
2018 u32 rx_stat_etherstatsundersizepkts
;
2019 u32 rx_stat_etherstatspkts64octets
;
2020 u32 rx_stat_etherstatspkts65octetsto127octets
;
2021 u32 rx_stat_etherstatspkts128octetsto255octets
;
2022 u32 rx_stat_etherstatspkts256octetsto511octets
;
2023 u32 rx_stat_etherstatspkts512octetsto1023octets
;
2024 u32 rx_stat_etherstatspkts1024octetsto1522octets
;
2025 u32 rx_stat_etherstatspktsover1522octets
;
2027 u32 rx_stat_falsecarriererrors
;
2029 u32 tx_stat_ifhcoutoctets
;
2030 u32 tx_stat_ifhcoutbadoctets
;
2031 u32 tx_stat_etherstatscollisions
;
2032 u32 tx_stat_outxonsent
;
2033 u32 tx_stat_outxoffsent
;
2034 u32 tx_stat_flowcontroldone
;
2035 u32 tx_stat_dot3statssinglecollisionframes
;
2036 u32 tx_stat_dot3statsmultiplecollisionframes
;
2037 u32 tx_stat_dot3statsdeferredtransmissions
;
2038 u32 tx_stat_dot3statsexcessivecollisions
;
2039 u32 tx_stat_dot3statslatecollisions
;
2040 u32 tx_stat_ifhcoutucastpkts
;
2041 u32 tx_stat_ifhcoutmulticastpkts
;
2042 u32 tx_stat_ifhcoutbroadcastpkts
;
2043 u32 tx_stat_etherstatspkts64octets
;
2044 u32 tx_stat_etherstatspkts65octetsto127octets
;
2045 u32 tx_stat_etherstatspkts128octetsto255octets
;
2046 u32 tx_stat_etherstatspkts256octetsto511octets
;
2047 u32 tx_stat_etherstatspkts512octetsto1023octets
;
2048 u32 tx_stat_etherstatspkts1024octetsto1522octets
;
2049 u32 tx_stat_etherstatspktsover1522octets
;
2050 u32 tx_stat_dot3statsinternalmactransmiterrors
;
2054 struct bmac1_stats
{
2055 u32 tx_stat_gtpkt_lo
;
2056 u32 tx_stat_gtpkt_hi
;
2057 u32 tx_stat_gtxpf_lo
;
2058 u32 tx_stat_gtxpf_hi
;
2059 u32 tx_stat_gtfcs_lo
;
2060 u32 tx_stat_gtfcs_hi
;
2061 u32 tx_stat_gtmca_lo
;
2062 u32 tx_stat_gtmca_hi
;
2063 u32 tx_stat_gtbca_lo
;
2064 u32 tx_stat_gtbca_hi
;
2065 u32 tx_stat_gtfrg_lo
;
2066 u32 tx_stat_gtfrg_hi
;
2067 u32 tx_stat_gtovr_lo
;
2068 u32 tx_stat_gtovr_hi
;
2069 u32 tx_stat_gt64_lo
;
2070 u32 tx_stat_gt64_hi
;
2071 u32 tx_stat_gt127_lo
;
2072 u32 tx_stat_gt127_hi
;
2073 u32 tx_stat_gt255_lo
;
2074 u32 tx_stat_gt255_hi
;
2075 u32 tx_stat_gt511_lo
;
2076 u32 tx_stat_gt511_hi
;
2077 u32 tx_stat_gt1023_lo
;
2078 u32 tx_stat_gt1023_hi
;
2079 u32 tx_stat_gt1518_lo
;
2080 u32 tx_stat_gt1518_hi
;
2081 u32 tx_stat_gt2047_lo
;
2082 u32 tx_stat_gt2047_hi
;
2083 u32 tx_stat_gt4095_lo
;
2084 u32 tx_stat_gt4095_hi
;
2085 u32 tx_stat_gt9216_lo
;
2086 u32 tx_stat_gt9216_hi
;
2087 u32 tx_stat_gt16383_lo
;
2088 u32 tx_stat_gt16383_hi
;
2089 u32 tx_stat_gtmax_lo
;
2090 u32 tx_stat_gtmax_hi
;
2091 u32 tx_stat_gtufl_lo
;
2092 u32 tx_stat_gtufl_hi
;
2093 u32 tx_stat_gterr_lo
;
2094 u32 tx_stat_gterr_hi
;
2095 u32 tx_stat_gtbyt_lo
;
2096 u32 tx_stat_gtbyt_hi
;
2098 u32 rx_stat_gr64_lo
;
2099 u32 rx_stat_gr64_hi
;
2100 u32 rx_stat_gr127_lo
;
2101 u32 rx_stat_gr127_hi
;
2102 u32 rx_stat_gr255_lo
;
2103 u32 rx_stat_gr255_hi
;
2104 u32 rx_stat_gr511_lo
;
2105 u32 rx_stat_gr511_hi
;
2106 u32 rx_stat_gr1023_lo
;
2107 u32 rx_stat_gr1023_hi
;
2108 u32 rx_stat_gr1518_lo
;
2109 u32 rx_stat_gr1518_hi
;
2110 u32 rx_stat_gr2047_lo
;
2111 u32 rx_stat_gr2047_hi
;
2112 u32 rx_stat_gr4095_lo
;
2113 u32 rx_stat_gr4095_hi
;
2114 u32 rx_stat_gr9216_lo
;
2115 u32 rx_stat_gr9216_hi
;
2116 u32 rx_stat_gr16383_lo
;
2117 u32 rx_stat_gr16383_hi
;
2118 u32 rx_stat_grmax_lo
;
2119 u32 rx_stat_grmax_hi
;
2120 u32 rx_stat_grpkt_lo
;
2121 u32 rx_stat_grpkt_hi
;
2122 u32 rx_stat_grfcs_lo
;
2123 u32 rx_stat_grfcs_hi
;
2124 u32 rx_stat_grmca_lo
;
2125 u32 rx_stat_grmca_hi
;
2126 u32 rx_stat_grbca_lo
;
2127 u32 rx_stat_grbca_hi
;
2128 u32 rx_stat_grxcf_lo
;
2129 u32 rx_stat_grxcf_hi
;
2130 u32 rx_stat_grxpf_lo
;
2131 u32 rx_stat_grxpf_hi
;
2132 u32 rx_stat_grxuo_lo
;
2133 u32 rx_stat_grxuo_hi
;
2134 u32 rx_stat_grjbr_lo
;
2135 u32 rx_stat_grjbr_hi
;
2136 u32 rx_stat_grovr_lo
;
2137 u32 rx_stat_grovr_hi
;
2138 u32 rx_stat_grflr_lo
;
2139 u32 rx_stat_grflr_hi
;
2140 u32 rx_stat_grmeg_lo
;
2141 u32 rx_stat_grmeg_hi
;
2142 u32 rx_stat_grmeb_lo
;
2143 u32 rx_stat_grmeb_hi
;
2144 u32 rx_stat_grbyt_lo
;
2145 u32 rx_stat_grbyt_hi
;
2146 u32 rx_stat_grund_lo
;
2147 u32 rx_stat_grund_hi
;
2148 u32 rx_stat_grfrg_lo
;
2149 u32 rx_stat_grfrg_hi
;
2150 u32 rx_stat_grerb_lo
;
2151 u32 rx_stat_grerb_hi
;
2152 u32 rx_stat_grfre_lo
;
2153 u32 rx_stat_grfre_hi
;
2154 u32 rx_stat_gripj_lo
;
2155 u32 rx_stat_gripj_hi
;
2158 struct bmac2_stats
{
2159 u32 tx_stat_gtpk_lo
; /* gtpok */
2160 u32 tx_stat_gtpk_hi
; /* gtpok */
2161 u32 tx_stat_gtxpf_lo
; /* gtpf */
2162 u32 tx_stat_gtxpf_hi
; /* gtpf */
2163 u32 tx_stat_gtpp_lo
; /* NEW BMAC2 */
2164 u32 tx_stat_gtpp_hi
; /* NEW BMAC2 */
2165 u32 tx_stat_gtfcs_lo
;
2166 u32 tx_stat_gtfcs_hi
;
2167 u32 tx_stat_gtuca_lo
; /* NEW BMAC2 */
2168 u32 tx_stat_gtuca_hi
; /* NEW BMAC2 */
2169 u32 tx_stat_gtmca_lo
;
2170 u32 tx_stat_gtmca_hi
;
2171 u32 tx_stat_gtbca_lo
;
2172 u32 tx_stat_gtbca_hi
;
2173 u32 tx_stat_gtovr_lo
;
2174 u32 tx_stat_gtovr_hi
;
2175 u32 tx_stat_gtfrg_lo
;
2176 u32 tx_stat_gtfrg_hi
;
2177 u32 tx_stat_gtpkt1_lo
; /* gtpkt */
2178 u32 tx_stat_gtpkt1_hi
; /* gtpkt */
2179 u32 tx_stat_gt64_lo
;
2180 u32 tx_stat_gt64_hi
;
2181 u32 tx_stat_gt127_lo
;
2182 u32 tx_stat_gt127_hi
;
2183 u32 tx_stat_gt255_lo
;
2184 u32 tx_stat_gt255_hi
;
2185 u32 tx_stat_gt511_lo
;
2186 u32 tx_stat_gt511_hi
;
2187 u32 tx_stat_gt1023_lo
;
2188 u32 tx_stat_gt1023_hi
;
2189 u32 tx_stat_gt1518_lo
;
2190 u32 tx_stat_gt1518_hi
;
2191 u32 tx_stat_gt2047_lo
;
2192 u32 tx_stat_gt2047_hi
;
2193 u32 tx_stat_gt4095_lo
;
2194 u32 tx_stat_gt4095_hi
;
2195 u32 tx_stat_gt9216_lo
;
2196 u32 tx_stat_gt9216_hi
;
2197 u32 tx_stat_gt16383_lo
;
2198 u32 tx_stat_gt16383_hi
;
2199 u32 tx_stat_gtmax_lo
;
2200 u32 tx_stat_gtmax_hi
;
2201 u32 tx_stat_gtufl_lo
;
2202 u32 tx_stat_gtufl_hi
;
2203 u32 tx_stat_gterr_lo
;
2204 u32 tx_stat_gterr_hi
;
2205 u32 tx_stat_gtbyt_lo
;
2206 u32 tx_stat_gtbyt_hi
;
2208 u32 rx_stat_gr64_lo
;
2209 u32 rx_stat_gr64_hi
;
2210 u32 rx_stat_gr127_lo
;
2211 u32 rx_stat_gr127_hi
;
2212 u32 rx_stat_gr255_lo
;
2213 u32 rx_stat_gr255_hi
;
2214 u32 rx_stat_gr511_lo
;
2215 u32 rx_stat_gr511_hi
;
2216 u32 rx_stat_gr1023_lo
;
2217 u32 rx_stat_gr1023_hi
;
2218 u32 rx_stat_gr1518_lo
;
2219 u32 rx_stat_gr1518_hi
;
2220 u32 rx_stat_gr2047_lo
;
2221 u32 rx_stat_gr2047_hi
;
2222 u32 rx_stat_gr4095_lo
;
2223 u32 rx_stat_gr4095_hi
;
2224 u32 rx_stat_gr9216_lo
;
2225 u32 rx_stat_gr9216_hi
;
2226 u32 rx_stat_gr16383_lo
;
2227 u32 rx_stat_gr16383_hi
;
2228 u32 rx_stat_grmax_lo
;
2229 u32 rx_stat_grmax_hi
;
2230 u32 rx_stat_grpkt_lo
;
2231 u32 rx_stat_grpkt_hi
;
2232 u32 rx_stat_grfcs_lo
;
2233 u32 rx_stat_grfcs_hi
;
2234 u32 rx_stat_gruca_lo
;
2235 u32 rx_stat_gruca_hi
;
2236 u32 rx_stat_grmca_lo
;
2237 u32 rx_stat_grmca_hi
;
2238 u32 rx_stat_grbca_lo
;
2239 u32 rx_stat_grbca_hi
;
2240 u32 rx_stat_grxpf_lo
; /* grpf */
2241 u32 rx_stat_grxpf_hi
; /* grpf */
2242 u32 rx_stat_grpp_lo
;
2243 u32 rx_stat_grpp_hi
;
2244 u32 rx_stat_grxuo_lo
; /* gruo */
2245 u32 rx_stat_grxuo_hi
; /* gruo */
2246 u32 rx_stat_grjbr_lo
;
2247 u32 rx_stat_grjbr_hi
;
2248 u32 rx_stat_grovr_lo
;
2249 u32 rx_stat_grovr_hi
;
2250 u32 rx_stat_grxcf_lo
; /* grcf */
2251 u32 rx_stat_grxcf_hi
; /* grcf */
2252 u32 rx_stat_grflr_lo
;
2253 u32 rx_stat_grflr_hi
;
2254 u32 rx_stat_grpok_lo
;
2255 u32 rx_stat_grpok_hi
;
2256 u32 rx_stat_grmeg_lo
;
2257 u32 rx_stat_grmeg_hi
;
2258 u32 rx_stat_grmeb_lo
;
2259 u32 rx_stat_grmeb_hi
;
2260 u32 rx_stat_grbyt_lo
;
2261 u32 rx_stat_grbyt_hi
;
2262 u32 rx_stat_grund_lo
;
2263 u32 rx_stat_grund_hi
;
2264 u32 rx_stat_grfrg_lo
;
2265 u32 rx_stat_grfrg_hi
;
2266 u32 rx_stat_grerb_lo
; /* grerrbyt */
2267 u32 rx_stat_grerb_hi
; /* grerrbyt */
2268 u32 rx_stat_grfre_lo
; /* grfrerr */
2269 u32 rx_stat_grfre_hi
; /* grfrerr */
2270 u32 rx_stat_gripj_lo
;
2271 u32 rx_stat_gripj_hi
;
2274 struct mstat_stats
{
2276 /* OTE MSTAT on E3 has a bug where this register's contents are
2277 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
2321 u32 tx_collisions_lo
;
2322 u32 tx_collisions_hi
;
2323 u32 tx_singlecollision_lo
;
2324 u32 tx_singlecollision_hi
;
2325 u32 tx_multiplecollisions_lo
;
2326 u32 tx_multiplecollisions_hi
;
2329 u32 tx_excessivecollisions_lo
;
2330 u32 tx_excessivecollisions_hi
;
2331 u32 tx_latecollisions_lo
;
2332 u32 tx_latecollisions_hi
;
2391 u32 rx_alignmenterrors_lo
;
2392 u32 rx_alignmenterrors_hi
;
2393 u32 rx_falsecarrier_lo
;
2394 u32 rx_falsecarrier_hi
;
2395 u32 rx_llfcmsgcnt_lo
;
2396 u32 rx_llfcmsgcnt_hi
;
2401 struct emac_stats emac_stats
;
2402 struct bmac1_stats bmac1_stats
;
2403 struct bmac2_stats bmac2_stats
;
2404 struct mstat_stats mstat_stats
;
2410 u32 rx_stat_ifhcinbadoctets_hi
;
2411 u32 rx_stat_ifhcinbadoctets_lo
;
2413 /* out_bad_octets */
2414 u32 tx_stat_ifhcoutbadoctets_hi
;
2415 u32 tx_stat_ifhcoutbadoctets_lo
;
2417 /* crc_receive_errors */
2418 u32 rx_stat_dot3statsfcserrors_hi
;
2419 u32 rx_stat_dot3statsfcserrors_lo
;
2420 /* alignment_errors */
2421 u32 rx_stat_dot3statsalignmenterrors_hi
;
2422 u32 rx_stat_dot3statsalignmenterrors_lo
;
2423 /* carrier_sense_errors */
2424 u32 rx_stat_dot3statscarriersenseerrors_hi
;
2425 u32 rx_stat_dot3statscarriersenseerrors_lo
;
2426 /* false_carrier_detections */
2427 u32 rx_stat_falsecarriererrors_hi
;
2428 u32 rx_stat_falsecarriererrors_lo
;
2430 /* runt_packets_received */
2431 u32 rx_stat_etherstatsundersizepkts_hi
;
2432 u32 rx_stat_etherstatsundersizepkts_lo
;
2433 /* jabber_packets_received */
2434 u32 rx_stat_dot3statsframestoolong_hi
;
2435 u32 rx_stat_dot3statsframestoolong_lo
;
2437 /* error_runt_packets_received */
2438 u32 rx_stat_etherstatsfragments_hi
;
2439 u32 rx_stat_etherstatsfragments_lo
;
2440 /* error_jabber_packets_received */
2441 u32 rx_stat_etherstatsjabbers_hi
;
2442 u32 rx_stat_etherstatsjabbers_lo
;
2444 /* control_frames_received */
2445 u32 rx_stat_maccontrolframesreceived_hi
;
2446 u32 rx_stat_maccontrolframesreceived_lo
;
2447 u32 rx_stat_mac_xpf_hi
;
2448 u32 rx_stat_mac_xpf_lo
;
2449 u32 rx_stat_mac_xcf_hi
;
2450 u32 rx_stat_mac_xcf_lo
;
2452 /* xoff_state_entered */
2453 u32 rx_stat_xoffstateentered_hi
;
2454 u32 rx_stat_xoffstateentered_lo
;
2455 /* pause_xon_frames_received */
2456 u32 rx_stat_xonpauseframesreceived_hi
;
2457 u32 rx_stat_xonpauseframesreceived_lo
;
2458 /* pause_xoff_frames_received */
2459 u32 rx_stat_xoffpauseframesreceived_hi
;
2460 u32 rx_stat_xoffpauseframesreceived_lo
;
2461 /* pause_xon_frames_transmitted */
2462 u32 tx_stat_outxonsent_hi
;
2463 u32 tx_stat_outxonsent_lo
;
2464 /* pause_xoff_frames_transmitted */
2465 u32 tx_stat_outxoffsent_hi
;
2466 u32 tx_stat_outxoffsent_lo
;
2467 /* flow_control_done */
2468 u32 tx_stat_flowcontroldone_hi
;
2469 u32 tx_stat_flowcontroldone_lo
;
2471 /* ether_stats_collisions */
2472 u32 tx_stat_etherstatscollisions_hi
;
2473 u32 tx_stat_etherstatscollisions_lo
;
2474 /* single_collision_transmit_frames */
2475 u32 tx_stat_dot3statssinglecollisionframes_hi
;
2476 u32 tx_stat_dot3statssinglecollisionframes_lo
;
2477 /* multiple_collision_transmit_frames */
2478 u32 tx_stat_dot3statsmultiplecollisionframes_hi
;
2479 u32 tx_stat_dot3statsmultiplecollisionframes_lo
;
2480 /* deferred_transmissions */
2481 u32 tx_stat_dot3statsdeferredtransmissions_hi
;
2482 u32 tx_stat_dot3statsdeferredtransmissions_lo
;
2483 /* excessive_collision_frames */
2484 u32 tx_stat_dot3statsexcessivecollisions_hi
;
2485 u32 tx_stat_dot3statsexcessivecollisions_lo
;
2486 /* late_collision_frames */
2487 u32 tx_stat_dot3statslatecollisions_hi
;
2488 u32 tx_stat_dot3statslatecollisions_lo
;
2490 /* frames_transmitted_64_bytes */
2491 u32 tx_stat_etherstatspkts64octets_hi
;
2492 u32 tx_stat_etherstatspkts64octets_lo
;
2493 /* frames_transmitted_65_127_bytes */
2494 u32 tx_stat_etherstatspkts65octetsto127octets_hi
;
2495 u32 tx_stat_etherstatspkts65octetsto127octets_lo
;
2496 /* frames_transmitted_128_255_bytes */
2497 u32 tx_stat_etherstatspkts128octetsto255octets_hi
;
2498 u32 tx_stat_etherstatspkts128octetsto255octets_lo
;
2499 /* frames_transmitted_256_511_bytes */
2500 u32 tx_stat_etherstatspkts256octetsto511octets_hi
;
2501 u32 tx_stat_etherstatspkts256octetsto511octets_lo
;
2502 /* frames_transmitted_512_1023_bytes */
2503 u32 tx_stat_etherstatspkts512octetsto1023octets_hi
;
2504 u32 tx_stat_etherstatspkts512octetsto1023octets_lo
;
2505 /* frames_transmitted_1024_1522_bytes */
2506 u32 tx_stat_etherstatspkts1024octetsto1522octets_hi
;
2507 u32 tx_stat_etherstatspkts1024octetsto1522octets_lo
;
2508 /* frames_transmitted_1523_9022_bytes */
2509 u32 tx_stat_etherstatspktsover1522octets_hi
;
2510 u32 tx_stat_etherstatspktsover1522octets_lo
;
2511 u32 tx_stat_mac_2047_hi
;
2512 u32 tx_stat_mac_2047_lo
;
2513 u32 tx_stat_mac_4095_hi
;
2514 u32 tx_stat_mac_4095_lo
;
2515 u32 tx_stat_mac_9216_hi
;
2516 u32 tx_stat_mac_9216_lo
;
2517 u32 tx_stat_mac_16383_hi
;
2518 u32 tx_stat_mac_16383_lo
;
2520 /* internal_mac_transmit_errors */
2521 u32 tx_stat_dot3statsinternalmactransmiterrors_hi
;
2522 u32 tx_stat_dot3statsinternalmactransmiterrors_lo
;
2524 /* if_out_discards */
2525 u32 tx_stat_mac_ufl_hi
;
2526 u32 tx_stat_mac_ufl_lo
;
2530 #define MAC_STX_IDX_MAX 2
2532 struct host_port_stats
{
2533 u32 host_port_stats_counter
;
2535 struct mac_stx mac_stx
[MAC_STX_IDX_MAX
];
2540 u32 not_used
; /* obsolete */
2541 u32 pfc_frames_tx_hi
;
2542 u32 pfc_frames_tx_lo
;
2543 u32 pfc_frames_rx_hi
;
2544 u32 pfc_frames_rx_lo
;
2548 struct host_func_stats
{
2549 u32 host_func_stats_start
;
2551 u32 total_bytes_received_hi
;
2552 u32 total_bytes_received_lo
;
2554 u32 total_bytes_transmitted_hi
;
2555 u32 total_bytes_transmitted_lo
;
2557 u32 total_unicast_packets_received_hi
;
2558 u32 total_unicast_packets_received_lo
;
2560 u32 total_multicast_packets_received_hi
;
2561 u32 total_multicast_packets_received_lo
;
2563 u32 total_broadcast_packets_received_hi
;
2564 u32 total_broadcast_packets_received_lo
;
2566 u32 total_unicast_packets_transmitted_hi
;
2567 u32 total_unicast_packets_transmitted_lo
;
2569 u32 total_multicast_packets_transmitted_hi
;
2570 u32 total_multicast_packets_transmitted_lo
;
2572 u32 total_broadcast_packets_transmitted_hi
;
2573 u32 total_broadcast_packets_transmitted_lo
;
2575 u32 valid_bytes_received_hi
;
2576 u32 valid_bytes_received_lo
;
2578 u32 host_func_stats_end
;
2581 /* VIC definitions */
2582 #define VICSTATST_UIF_INDEX 2
2584 /* current drv_info version */
2585 #define DRV_INFO_CUR_VER 1
2587 /* drv_info op codes supported */
2588 enum drv_info_opcode
{
2594 #define ETH_STAT_INFO_VERSION_LEN 12
2595 /* Per PCI Function Ethernet Statistics required from the driver */
2596 struct eth_stats_info
{
2597 /* Function's Driver Version. padded to 12 */
2598 u8 version
[ETH_STAT_INFO_VERSION_LEN
];
2599 /* Locally Admin Addr. BigEndian EIU48. Actual size is 6 bytes */
2601 u8 mac_add1
[8]; /* Additional Programmed MAC Addr 1. */
2602 u8 mac_add2
[8]; /* Additional Programmed MAC Addr 2. */
2603 u32 mtu_size
; /* MTU Size. Note : Negotiated MTU */
2604 u32 feature_flags
; /* Feature_Flags. */
2605 #define FEATURE_ETH_CHKSUM_OFFLOAD_MASK 0x01
2606 #define FEATURE_ETH_LSO_MASK 0x02
2607 #define FEATURE_ETH_BOOTMODE_MASK 0x1C
2608 #define FEATURE_ETH_BOOTMODE_SHIFT 2
2609 #define FEATURE_ETH_BOOTMODE_NONE (0x0 << 2)
2610 #define FEATURE_ETH_BOOTMODE_PXE (0x1 << 2)
2611 #define FEATURE_ETH_BOOTMODE_ISCSI (0x2 << 2)
2612 #define FEATURE_ETH_BOOTMODE_FCOE (0x3 << 2)
2613 #define FEATURE_ETH_TOE_MASK 0x20
2614 u32 lso_max_size
; /* LSO MaxOffloadSize. */
2615 u32 lso_min_seg_cnt
; /* LSO MinSegmentCount. */
2616 /* Num Offloaded Connections TCP_IPv4. */
2618 /* Num Offloaded Connections TCP_IPv6. */
2620 u32 promiscuous_mode
; /* Promiscuous Mode. non-zero true */
2621 u32 txq_size
; /* TX Descriptors Queue Size */
2622 u32 rxq_size
; /* RX Descriptors Queue Size */
2623 /* TX Descriptor Queue Avg Depth. % Avg Queue Depth since last poll */
2625 /* RX Descriptors Queue Avg Depth. % Avg Queue Depth since last poll */
2627 /* IOV_Offload. 0=none; 1=MultiQueue, 2=VEB 3= VEPA*/
2629 /* Number of NetQueue/VMQ Config'd. */
2631 u32 vf_cnt
; /* Num VF assigned to this PF. */
2634 /* Per PCI Function FCOE Statistics required from the driver */
2635 struct fcoe_stats_info
{
2636 u8 version
[12]; /* Function's Driver Version. */
2637 u8 mac_local
[8]; /* Locally Admin Addr. */
2638 u8 mac_add1
[8]; /* Additional Programmed MAC Addr 1. */
2639 u8 mac_add2
[8]; /* Additional Programmed MAC Addr 2. */
2640 /* QoS Priority (per 802.1p). 0-7255 */
2642 u32 txq_size
; /* FCoE TX Descriptors Queue Size. */
2643 u32 rxq_size
; /* FCoE RX Descriptors Queue Size. */
2644 /* FCoE TX Descriptor Queue Avg Depth. */
2646 /* FCoE RX Descriptors Queue Avg Depth. */
2648 u32 rx_frames_lo
; /* FCoE RX Frames received. */
2649 u32 rx_frames_hi
; /* FCoE RX Frames received. */
2650 u32 rx_bytes_lo
; /* FCoE RX Bytes received. */
2651 u32 rx_bytes_hi
; /* FCoE RX Bytes received. */
2652 u32 tx_frames_lo
; /* FCoE TX Frames sent. */
2653 u32 tx_frames_hi
; /* FCoE TX Frames sent. */
2654 u32 tx_bytes_lo
; /* FCoE TX Bytes sent. */
2655 u32 tx_bytes_hi
; /* FCoE TX Bytes sent. */
2658 /* Per PCI Function iSCSI Statistics required from the driver*/
2659 struct iscsi_stats_info
{
2660 u8 version
[12]; /* Function's Driver Version. */
2661 u8 mac_local
[8]; /* Locally Admin iSCSI MAC Addr. */
2662 u8 mac_add1
[8]; /* Additional Programmed MAC Addr 1. */
2663 /* QoS Priority (per 802.1p). 0-7255 */
2665 u8 initiator_name
[64]; /* iSCSI Boot Initiator Node name. */
2666 u8 ww_port_name
[64]; /* iSCSI World wide port name */
2667 u8 boot_target_name
[64];/* iSCSI Boot Target Name. */
2668 u8 boot_target_ip
[16]; /* iSCSI Boot Target IP. */
2669 u32 boot_target_portal
; /* iSCSI Boot Target Portal. */
2670 u8 boot_init_ip
[16]; /* iSCSI Boot Initiator IP Address. */
2671 u32 max_frame_size
; /* Max Frame Size. bytes */
2672 u32 txq_size
; /* PDU TX Descriptors Queue Size. */
2673 u32 rxq_size
; /* PDU RX Descriptors Queue Size. */
2674 u32 txq_avg_depth
; /* PDU TX Descriptor Queue Avg Depth. */
2675 u32 rxq_avg_depth
; /* PDU RX Descriptors Queue Avg Depth. */
2676 u32 rx_pdus_lo
; /* iSCSI PDUs received. */
2677 u32 rx_pdus_hi
; /* iSCSI PDUs received. */
2678 u32 rx_bytes_lo
; /* iSCSI RX Bytes received. */
2679 u32 rx_bytes_hi
; /* iSCSI RX Bytes received. */
2680 u32 tx_pdus_lo
; /* iSCSI PDUs sent. */
2681 u32 tx_pdus_hi
; /* iSCSI PDUs sent. */
2682 u32 tx_bytes_lo
; /* iSCSI PDU TX Bytes sent. */
2683 u32 tx_bytes_hi
; /* iSCSI PDU TX Bytes sent. */
2684 u32 pcp_prior_map_tbl
; /* C-PCP to S-PCP Priority MapTable.
2685 * 9 nibbles, the position of each nibble
2686 * represents the C-PCP value, the value
2687 * of the nibble = S-PCP value.
2691 union drv_info_to_mcp
{
2692 struct eth_stats_info ether_stat
;
2693 struct fcoe_stats_info fcoe_stat
;
2694 struct iscsi_stats_info iscsi_stat
;
2696 #define BCM_5710_FW_MAJOR_VERSION 7
2697 #define BCM_5710_FW_MINOR_VERSION 2
2698 #define BCM_5710_FW_REVISION_VERSION 16
2699 #define BCM_5710_FW_ENGINEERING_VERSION 0
2700 #define BCM_5710_FW_COMPILE_FLAGS 1
2706 struct atten_sp_status_block
{
2708 __le32 attn_bits_ack
;
2711 __le16 attn_bits_index
;
2717 * The eth aggregative context of Cstorm
2719 struct cstorm_eth_ag_context
{
2720 u32 __reserved0
[10];
2725 * dmae command structure
2727 struct dmae_command
{
2729 #define DMAE_COMMAND_SRC (0x1<<0)
2730 #define DMAE_COMMAND_SRC_SHIFT 0
2731 #define DMAE_COMMAND_DST (0x3<<1)
2732 #define DMAE_COMMAND_DST_SHIFT 1
2733 #define DMAE_COMMAND_C_DST (0x1<<3)
2734 #define DMAE_COMMAND_C_DST_SHIFT 3
2735 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4)
2736 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4
2737 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5)
2738 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5
2739 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6)
2740 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6
2741 #define DMAE_COMMAND_ENDIANITY (0x3<<9)
2742 #define DMAE_COMMAND_ENDIANITY_SHIFT 9
2743 #define DMAE_COMMAND_PORT (0x1<<11)
2744 #define DMAE_COMMAND_PORT_SHIFT 11
2745 #define DMAE_COMMAND_CRC_RESET (0x1<<12)
2746 #define DMAE_COMMAND_CRC_RESET_SHIFT 12
2747 #define DMAE_COMMAND_SRC_RESET (0x1<<13)
2748 #define DMAE_COMMAND_SRC_RESET_SHIFT 13
2749 #define DMAE_COMMAND_DST_RESET (0x1<<14)
2750 #define DMAE_COMMAND_DST_RESET_SHIFT 14
2751 #define DMAE_COMMAND_E1HVN (0x3<<15)
2752 #define DMAE_COMMAND_E1HVN_SHIFT 15
2753 #define DMAE_COMMAND_DST_VN (0x3<<17)
2754 #define DMAE_COMMAND_DST_VN_SHIFT 17
2755 #define DMAE_COMMAND_C_FUNC (0x1<<19)
2756 #define DMAE_COMMAND_C_FUNC_SHIFT 19
2757 #define DMAE_COMMAND_ERR_POLICY (0x3<<20)
2758 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20
2759 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22)
2760 #define DMAE_COMMAND_RESERVED0_SHIFT 22
2765 #if defined(__BIG_ENDIAN)
2767 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2768 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2769 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2770 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2771 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2772 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2773 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2774 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2775 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2776 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2777 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2778 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2780 #elif defined(__LITTLE_ENDIAN)
2783 #define DMAE_COMMAND_SRC_VFID (0x3F<<0)
2784 #define DMAE_COMMAND_SRC_VFID_SHIFT 0
2785 #define DMAE_COMMAND_SRC_VFPF (0x1<<6)
2786 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6
2787 #define DMAE_COMMAND_RESERVED1 (0x1<<7)
2788 #define DMAE_COMMAND_RESERVED1_SHIFT 7
2789 #define DMAE_COMMAND_DST_VFID (0x3F<<8)
2790 #define DMAE_COMMAND_DST_VFID_SHIFT 8
2791 #define DMAE_COMMAND_DST_VFPF (0x1<<14)
2792 #define DMAE_COMMAND_DST_VFPF_SHIFT 14
2793 #define DMAE_COMMAND_RESERVED2 (0x1<<15)
2794 #define DMAE_COMMAND_RESERVED2_SHIFT 15
2801 #if defined(__BIG_ENDIAN)
2804 #elif defined(__LITTLE_ENDIAN)
2808 #if defined(__BIG_ENDIAN)
2811 #elif defined(__LITTLE_ENDIAN)
2815 #if defined(__BIG_ENDIAN)
2818 #elif defined(__LITTLE_ENDIAN)
2826 * common data for all protocols
2828 struct doorbell_hdr
{
2830 #define DOORBELL_HDR_RX (0x1<<0)
2831 #define DOORBELL_HDR_RX_SHIFT 0
2832 #define DOORBELL_HDR_DB_TYPE (0x1<<1)
2833 #define DOORBELL_HDR_DB_TYPE_SHIFT 1
2834 #define DOORBELL_HDR_DPM_SIZE (0x3<<2)
2835 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2
2836 #define DOORBELL_HDR_CONN_TYPE (0xF<<4)
2837 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4
2843 struct eth_tx_doorbell
{
2844 #if defined(__BIG_ENDIAN)
2847 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2848 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2849 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2850 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2851 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2852 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2853 struct doorbell_hdr hdr
;
2854 #elif defined(__LITTLE_ENDIAN)
2855 struct doorbell_hdr hdr
;
2857 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0)
2858 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
2859 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6)
2860 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
2861 #define ETH_TX_DOORBELL_SPARE (0x1<<7)
2862 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
2869 * 3 lines. status block
2871 struct hc_status_block_e1x
{
2872 __le16 index_values
[HC_SB_MAX_INDICES_E1X
];
2873 __le16 running_index
[HC_SB_MAX_SM
];
2880 struct host_hc_status_block_e1x
{
2881 struct hc_status_block_e1x sb
;
2886 * 3 lines. status block
2888 struct hc_status_block_e2
{
2889 __le16 index_values
[HC_SB_MAX_INDICES_E2
];
2890 __le16 running_index
[HC_SB_MAX_SM
];
2891 __le32 reserved
[11];
2897 struct host_hc_status_block_e2
{
2898 struct hc_status_block_e2 sb
;
2903 * 5 lines. slow-path status block
2905 struct hc_sp_status_block
{
2906 __le16 index_values
[HC_SP_SB_MAX_INDICES
];
2907 __le16 running_index
;
2915 struct host_sp_status_block
{
2916 struct atten_sp_status_block atten_status_block
;
2917 struct hc_sp_status_block sp_sb
;
2922 * IGU driver acknowledgment register
2924 struct igu_ack_register
{
2925 #if defined(__BIG_ENDIAN)
2926 u16 sb_id_and_flags
;
2927 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2928 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2929 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2930 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2931 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2932 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2933 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2934 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2935 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2936 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2937 u16 status_block_index
;
2938 #elif defined(__LITTLE_ENDIAN)
2939 u16 status_block_index
;
2940 u16 sb_id_and_flags
;
2941 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0)
2942 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
2943 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5)
2944 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
2945 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8)
2946 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
2947 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9)
2948 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
2949 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11)
2950 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
2956 * IGU driver acknowledgement register
2958 struct igu_backward_compatible
{
2959 u32 sb_id_and_flags
;
2960 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0)
2961 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
2962 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16)
2963 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
2964 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21)
2965 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
2966 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24)
2967 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
2968 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25)
2969 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
2970 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27)
2971 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
2977 * IGU driver acknowledgement register
2979 struct igu_regular
{
2980 u32 sb_id_and_flags
;
2981 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0)
2982 #define IGU_REGULAR_SB_INDEX_SHIFT 0
2983 #define IGU_REGULAR_RESERVED0 (0x1<<20)
2984 #define IGU_REGULAR_RESERVED0_SHIFT 20
2985 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21)
2986 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
2987 #define IGU_REGULAR_BUPDATE (0x1<<24)
2988 #define IGU_REGULAR_BUPDATE_SHIFT 24
2989 #define IGU_REGULAR_ENABLE_INT (0x3<<25)
2990 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
2991 #define IGU_REGULAR_RESERVED_1 (0x1<<27)
2992 #define IGU_REGULAR_RESERVED_1_SHIFT 27
2993 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28)
2994 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
2995 #define IGU_REGULAR_CLEANUP_SET (0x1<<30)
2996 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
2997 #define IGU_REGULAR_BCLEANUP (0x1<<31)
2998 #define IGU_REGULAR_BCLEANUP_SHIFT 31
3003 * IGU driver acknowledgement register
3005 union igu_consprod_reg
{
3006 struct igu_regular regular
;
3007 struct igu_backward_compatible backward_compatible
;
3012 * Igu control commands
3015 IGU_CTRL_CMD_TYPE_RD
,
3016 IGU_CTRL_CMD_TYPE_WR
,
3022 * Control register for the IGU command register
3024 struct igu_ctrl_reg
{
3026 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0)
3027 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
3028 #define IGU_CTRL_REG_FID (0x7F<<12)
3029 #define IGU_CTRL_REG_FID_SHIFT 12
3030 #define IGU_CTRL_REG_RESERVED (0x1<<19)
3031 #define IGU_CTRL_REG_RESERVED_SHIFT 19
3032 #define IGU_CTRL_REG_TYPE (0x1<<20)
3033 #define IGU_CTRL_REG_TYPE_SHIFT 20
3034 #define IGU_CTRL_REG_UNUSED (0x7FF<<21)
3035 #define IGU_CTRL_REG_UNUSED_SHIFT 21
3040 * Igu interrupt command
3054 enum igu_seg_access
{
3055 IGU_SEG_ACCESS_NORM
,
3057 IGU_SEG_ACCESS_ATTN
,
3063 * Parser parsing flags field
3065 struct parsing_flags
{
3067 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0)
3068 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
3069 #define PARSING_FLAGS_VLAN (0x1<<1)
3070 #define PARSING_FLAGS_VLAN_SHIFT 1
3071 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2)
3072 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2
3073 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3)
3074 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
3075 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5)
3076 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
3077 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6)
3078 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
3079 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7)
3080 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
3081 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9)
3082 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
3083 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10)
3084 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
3085 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11)
3086 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
3087 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12)
3088 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
3089 #define PARSING_FLAGS_LLC_SNAP (0x1<<13)
3090 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
3091 #define PARSING_FLAGS_RESERVED0 (0x3<<14)
3092 #define PARSING_FLAGS_RESERVED0_SHIFT 14
3097 * Parsing flags for TCP ACK type
3099 enum prs_flags_ack_type
{
3100 PRS_FLAG_PUREACK_PIGGY
,
3101 PRS_FLAG_PUREACK_PURE
,
3102 MAX_PRS_FLAGS_ACK_TYPE
3107 * Parsing flags for Ethernet address type
3109 enum prs_flags_eth_addr_type
{
3110 PRS_FLAG_ETHTYPE_NON_UNICAST
,
3111 PRS_FLAG_ETHTYPE_UNICAST
,
3112 MAX_PRS_FLAGS_ETH_ADDR_TYPE
3117 * Parsing flags for over-ethernet protocol
3119 enum prs_flags_over_eth
{
3120 PRS_FLAG_OVERETH_UNKNOWN
,
3121 PRS_FLAG_OVERETH_IPV4
,
3122 PRS_FLAG_OVERETH_IPV6
,
3123 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN
,
3124 MAX_PRS_FLAGS_OVER_ETH
3129 * Parsing flags for over-IP protocol
3131 enum prs_flags_over_ip
{
3132 PRS_FLAG_OVERIP_UNKNOWN
,
3133 PRS_FLAG_OVERIP_TCP
,
3134 PRS_FLAG_OVERIP_UDP
,
3135 MAX_PRS_FLAGS_OVER_IP
3140 * SDM operation gen command (generate aggregative interrupt)
3144 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0)
3145 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
3146 #define SDM_OP_GEN_COMP_TYPE (0x7<<5)
3147 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
3148 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8)
3149 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
3150 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16)
3151 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
3152 #define SDM_OP_GEN_RESERVED (0x7FFF<<17)
3153 #define SDM_OP_GEN_RESERVED_SHIFT 17
3158 * Timers connection context
3160 struct timers_block_context
{
3165 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0)
3166 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
3167 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2)
3168 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
3169 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3)
3170 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
3175 * The eth aggregative context of Tstorm
3177 struct tstorm_eth_ag_context
{
3178 u32 __reserved0
[14];
3183 * The eth aggregative context of Ustorm
3185 struct ustorm_eth_ag_context
{
3187 #if defined(__BIG_ENDIAN)
3191 #elif defined(__LITTLE_ENDIAN)
3201 * The eth aggregative context of Xstorm
3203 struct xstorm_eth_ag_context
{
3205 #if defined(__BIG_ENDIAN)
3209 #elif defined(__LITTLE_ENDIAN)
3219 * doorbell message sent to the chip
3222 #if defined(__BIG_ENDIAN)
3225 struct doorbell_hdr header
;
3226 #elif defined(__LITTLE_ENDIAN)
3227 struct doorbell_hdr header
;
3235 * doorbell message sent to the chip
3237 struct doorbell_set_prod
{
3238 #if defined(__BIG_ENDIAN)
3241 struct doorbell_hdr header
;
3242 #elif defined(__LITTLE_ENDIAN)
3243 struct doorbell_hdr header
;
3257 * Classify rule opcodes in E2/E3
3259 enum classify_rule
{
3260 CLASSIFY_RULE_OPCODE_MAC
,
3261 CLASSIFY_RULE_OPCODE_VLAN
,
3262 CLASSIFY_RULE_OPCODE_PAIR
,
3268 * Classify rule types in E2/E3
3270 enum classify_rule_action_type
{
3271 CLASSIFY_RULE_REMOVE
,
3273 MAX_CLASSIFY_RULE_ACTION_TYPE
3278 * client init ramrod data
3280 struct client_init_general_data
{
3282 u8 statistics_counter_id
;
3283 u8 statistics_en_flg
;
3288 u8 statistics_zero_flg
;
3297 * client init rx data
3299 struct client_init_rx_data
{
3301 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0)
3302 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
3303 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1)
3304 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
3305 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2)
3306 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
3307 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3)
3308 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
3309 u8 vmqueue_mode_en_flg
;
3310 u8 extra_data_over_sgl_en_flg
;
3311 u8 cache_line_alignment_log_size
;
3312 u8 enable_dynamic_hc
;
3313 u8 max_sges_for_packet
;
3315 u8 drop_ip_cs_err_flg
;
3316 u8 drop_tcp_cs_err_flg
;
3318 u8 drop_udp_cs_err_flg
;
3319 u8 inner_vlan_removal_enable_flg
;
3320 u8 outer_vlan_removal_enable_flg
;
3322 u8 rx_sb_index_number
;
3323 u8 dont_verify_rings_pause_thr_flg
;
3325 u8 silent_vlan_removal_flg
;
3326 __le16 max_bytes_on_bd
;
3327 __le16 sge_buff_size
;
3328 u8 approx_mcast_engine_id
;
3330 struct regpair bd_page_base
;
3331 struct regpair sge_page_base
;
3332 struct regpair cqe_page_base
;
3335 __le16 max_agg_size
;
3337 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0)
3338 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
3339 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1)
3340 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
3341 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3342 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3343 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3)
3344 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
3345 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4)
3346 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
3347 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5)
3348 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
3349 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6)
3350 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
3351 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7)
3352 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
3353 __le16 cqe_pause_thr_low
;
3354 __le16 cqe_pause_thr_high
;
3355 __le16 bd_pause_thr_low
;
3356 __le16 bd_pause_thr_high
;
3357 __le16 sge_pause_thr_low
;
3358 __le16 sge_pause_thr_high
;
3360 __le16 silent_vlan_value
;
3361 __le16 silent_vlan_mask
;
3362 __le32 reserved6
[2];
3366 * client init tx data
3368 struct client_init_tx_data
{
3369 u8 enforce_security_flg
;
3370 u8 tx_status_block_id
;
3371 u8 tx_sb_index_number
;
3372 u8 tss_leading_client_id
;
3373 u8 tx_switching_flg
;
3374 u8 anti_spoofing_flg
;
3375 __le16 default_vlan
;
3376 struct regpair tx_bd_page_base
;
3378 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0)
3379 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
3380 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1)
3381 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
3382 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2)
3383 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
3384 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3)
3385 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
3386 #define CLIENT_INIT_TX_DATA_RESERVED1 (0xFFF<<4)
3387 #define CLIENT_INIT_TX_DATA_RESERVED1_SHIFT 4
3388 u8 default_vlan_flg
;
3394 * client init ramrod data
3396 struct client_init_ramrod_data
{
3397 struct client_init_general_data general
;
3398 struct client_init_rx_data rx
;
3399 struct client_init_tx_data tx
;
3404 * client update ramrod data
3406 struct client_update_ramrod_data
{
3409 u8 inner_vlan_removal_enable_flg
;
3410 u8 inner_vlan_removal_change_flg
;
3411 u8 outer_vlan_removal_enable_flg
;
3412 u8 outer_vlan_removal_change_flg
;
3413 u8 anti_spoofing_enable_flg
;
3414 u8 anti_spoofing_change_flg
;
3416 u8 activate_change_flg
;
3417 __le16 default_vlan
;
3418 u8 default_vlan_enable_flg
;
3419 u8 default_vlan_change_flg
;
3420 __le16 silent_vlan_value
;
3421 __le16 silent_vlan_mask
;
3422 u8 silent_vlan_removal_flg
;
3423 u8 silent_vlan_change_flg
;
3429 * The eth storm context of Cstorm
3431 struct cstorm_eth_st_context
{
3436 struct double_regpair
{
3445 * Ethernet address typesm used in ethernet tx BDs
3447 enum eth_addr_type
{
3459 struct eth_classify_cmd_header
{
3460 u8 cmd_general_data
;
3461 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0)
3462 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
3463 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1)
3464 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
3465 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2)
3466 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
3467 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4)
3468 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
3469 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5)
3470 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
3478 * header for eth classification config ramrod
3480 struct eth_classify_header
{
3489 * Command for adding/removing a MAC classification rule
3491 struct eth_classify_mac_cmd
{
3492 struct eth_classify_cmd_header header
;
3502 * Command for adding/removing a MAC-VLAN pair classification rule
3504 struct eth_classify_pair_cmd
{
3505 struct eth_classify_cmd_header header
;
3515 * Command for adding/removing a VLAN classification rule
3517 struct eth_classify_vlan_cmd
{
3518 struct eth_classify_cmd_header header
;
3526 * union for eth classification rule
3528 union eth_classify_rule_cmd
{
3529 struct eth_classify_mac_cmd mac
;
3530 struct eth_classify_vlan_cmd vlan
;
3531 struct eth_classify_pair_cmd pair
;
3535 * parameters for eth classification configuration ramrod
3537 struct eth_classify_rules_ramrod_data
{
3538 struct eth_classify_header header
;
3539 union eth_classify_rule_cmd rules
[CLASSIFY_RULES_COUNT
];
3544 * The data contain client ID need to the ramrod
3546 struct eth_common_ramrod_data
{
3553 * The eth storm context of Ustorm
3555 struct ustorm_eth_st_context
{
3560 * The eth storm context of Tstorm
3562 struct tstorm_eth_st_context
{
3563 u32 __reserved0
[28];
3567 * The eth storm context of Xstorm
3569 struct xstorm_eth_st_context
{
3574 * Ethernet connection context
3576 struct eth_context
{
3577 struct ustorm_eth_st_context ustorm_st_context
;
3578 struct tstorm_eth_st_context tstorm_st_context
;
3579 struct xstorm_eth_ag_context xstorm_ag_context
;
3580 struct tstorm_eth_ag_context tstorm_ag_context
;
3581 struct cstorm_eth_ag_context cstorm_ag_context
;
3582 struct ustorm_eth_ag_context ustorm_ag_context
;
3583 struct timers_block_context timers_context
;
3584 struct xstorm_eth_st_context xstorm_st_context
;
3585 struct cstorm_eth_st_context cstorm_st_context
;
3590 * union for sgl and raw data.
3592 union eth_sgl_or_raw_data
{
3598 * eth FP end aggregation CQE parameters struct
3600 struct eth_end_agg_rx_cqe
{
3601 u8 type_error_flags
;
3602 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0)
3603 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
3604 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2)
3605 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
3606 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3)
3607 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
3611 __le32 timestamp_delta
;
3612 __le16 num_of_coalesced_segs
;
3617 union eth_sgl_or_raw_data sgl_or_raw_data
;
3618 __le32 reserved5
[8];
3623 * regular eth FP CQE parameters struct
3625 struct eth_fast_path_rx_cqe
{
3626 u8 type_error_flags
;
3627 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0)
3628 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
3629 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2)
3630 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
3631 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3)
3632 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
3633 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4)
3634 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
3635 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
3636 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
3637 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
3638 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
3640 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
3641 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
3642 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3)
3643 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
3644 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4)
3645 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
3646 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5)
3647 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
3648 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6)
3649 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
3650 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7)
3651 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
3653 u8 placement_offset
;
3654 __le32 rss_hash_result
;
3656 __le16 pkt_len_or_gro_seg_len
;
3658 struct parsing_flags pars_flags
;
3659 union eth_sgl_or_raw_data sgl_or_raw_data
;
3660 __le32 reserved1
[8];
3665 * Command for setting classification flags for a client
3667 struct eth_filter_rules_cmd
{
3668 u8 cmd_general_data
;
3669 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0)
3670 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
3671 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1)
3672 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
3673 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2)
3674 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
3679 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0)
3680 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
3681 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1)
3682 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
3683 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2)
3684 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
3685 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3)
3686 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
3687 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4)
3688 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
3689 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5)
3690 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
3691 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6)
3692 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
3693 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7)
3694 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
3696 struct regpair reserved4
;
3701 * parameters for eth classification filters ramrod
3703 struct eth_filter_rules_ramrod_data
{
3704 struct eth_classify_header header
;
3705 struct eth_filter_rules_cmd rules
[FILTER_RULES_COUNT
];
3710 * parameters for eth classification configuration ramrod
3712 struct eth_general_rules_ramrod_data
{
3713 struct eth_classify_header header
;
3714 union eth_classify_rule_cmd rules
[CLASSIFY_RULES_COUNT
];
3719 * The data for Halt ramrod
3721 struct eth_halt_ramrod_data
{
3728 * Command for setting multicast classification for a client
3730 struct eth_multicast_rules_cmd
{
3731 u8 cmd_general_data
;
3732 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0)
3733 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
3734 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1)
3735 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
3736 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2)
3737 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
3738 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3)
3739 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
3744 struct regpair reserved3
;
3749 * parameters for multicast classification ramrod
3751 struct eth_multicast_rules_ramrod_data
{
3752 struct eth_classify_header header
;
3753 struct eth_multicast_rules_cmd rules
[MULTICAST_RULES_COUNT
];
3758 * Place holder for ramrods protocol specific data
3760 struct ramrod_data
{
3766 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
3768 union eth_ramrod_data
{
3769 struct ramrod_data general
;
3774 * RSS toeplitz hash type, as reported in CQE
3776 enum eth_rss_hash_type
{
3783 E1HOV_PRI_HASH_TYPE
,
3785 MAX_ETH_RSS_HASH_TYPE
3793 ETH_RSS_MODE_DISABLED
,
3794 ETH_RSS_MODE_REGULAR
,
3795 ETH_RSS_MODE_VLAN_PRI
,
3796 ETH_RSS_MODE_E1HOV_PRI
,
3797 ETH_RSS_MODE_IP_DSCP
,
3803 * parameters for RSS update ramrod (E2)
3805 struct eth_rss_update_ramrod_data
{
3808 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
3809 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
3810 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
3811 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
3812 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
3813 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
3814 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
3815 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
3816 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
3817 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
3818 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
3819 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
3820 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<6)
3821 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 6
3822 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0 (0x1<<7)
3823 #define __ETH_RSS_UPDATE_RAMROD_DATA_RESERVED0_SHIFT 7
3827 u8 indirection_table
[T_ETH_INDIRECTION_TABLE_SIZE
];
3828 __le32 rss_key
[T_ETH_RSS_KEY
];
3835 * The eth Rx Buffer Descriptor
3844 * Eth Rx Cqe structure- general structure for ramrods
3846 struct common_ramrod_eth_rx_cqe
{
3848 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0)
3849 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
3850 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2)
3851 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
3852 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3)
3853 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
3856 __le32 conn_and_cmd_data
;
3857 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0)
3858 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
3859 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24)
3860 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
3861 struct ramrod_data protocol_data
;
3863 __le32 reserved2
[11];
3867 * Rx Last CQE in page (in ETH)
3869 struct eth_rx_cqe_next_page
{
3872 __le32 reserved
[14];
3876 * union for all eth rx cqe types (fix their sizes)
3879 struct eth_fast_path_rx_cqe fast_path_cqe
;
3880 struct common_ramrod_eth_rx_cqe ramrod_cqe
;
3881 struct eth_rx_cqe_next_page next_page_cqe
;
3882 struct eth_end_agg_rx_cqe end_agg_cqe
;
3887 * Values for RX ETH CQE type field
3889 enum eth_rx_cqe_type
{
3890 RX_ETH_CQE_TYPE_ETH_FASTPATH
,
3891 RX_ETH_CQE_TYPE_ETH_RAMROD
,
3892 RX_ETH_CQE_TYPE_ETH_START_AGG
,
3893 RX_ETH_CQE_TYPE_ETH_STOP_AGG
,
3899 * Type of SGL/Raw field in ETH RX fast path CQE
3901 enum eth_rx_fp_sel
{
3909 * The eth Rx SGE Descriptor
3918 * common data for all protocols
3921 __le32 conn_and_cmd_data
;
3922 #define SPE_HDR_CID (0xFFFFFF<<0)
3923 #define SPE_HDR_CID_SHIFT 0
3924 #define SPE_HDR_CMD_ID (0xFF<<24)
3925 #define SPE_HDR_CMD_ID_SHIFT 24
3927 #define SPE_HDR_CONN_TYPE (0xFF<<0)
3928 #define SPE_HDR_CONN_TYPE_SHIFT 0
3929 #define SPE_HDR_FUNCTION_ID (0xFF<<8)
3930 #define SPE_HDR_FUNCTION_ID_SHIFT 8
3935 * specific data for ethernet slow path element
3937 union eth_specific_data
{
3938 u8 protocol_data
[8];
3939 struct regpair client_update_ramrod_data
;
3940 struct regpair client_init_ramrod_init_data
;
3941 struct eth_halt_ramrod_data halt_ramrod_data
;
3942 struct regpair update_data_addr
;
3943 struct eth_common_ramrod_data common_ramrod_data
;
3944 struct regpair classify_cfg_addr
;
3945 struct regpair filter_cfg_addr
;
3946 struct regpair mcast_cfg_addr
;
3950 * Ethernet slow path element
3954 union eth_specific_data data
;
3959 * Ethernet command ID for slow path elements
3961 enum eth_spqe_cmd_id
{
3962 RAMROD_CMD_ID_ETH_UNUSED
,
3963 RAMROD_CMD_ID_ETH_CLIENT_SETUP
,
3964 RAMROD_CMD_ID_ETH_HALT
,
3965 RAMROD_CMD_ID_ETH_FORWARD_SETUP
,
3966 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
,
3967 RAMROD_CMD_ID_ETH_CLIENT_UPDATE
,
3968 RAMROD_CMD_ID_ETH_EMPTY
,
3969 RAMROD_CMD_ID_ETH_TERMINATE
,
3970 RAMROD_CMD_ID_ETH_TPA_UPDATE
,
3971 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
,
3972 RAMROD_CMD_ID_ETH_FILTER_RULES
,
3973 RAMROD_CMD_ID_ETH_MULTICAST_RULES
,
3974 RAMROD_CMD_ID_ETH_RSS_UPDATE
,
3975 RAMROD_CMD_ID_ETH_SET_MAC
,
3981 * eth tpa update command
3983 enum eth_tpa_update_command
{
3984 TPA_UPDATE_NONE_COMMAND
,
3985 TPA_UPDATE_ENABLE_COMMAND
,
3986 TPA_UPDATE_DISABLE_COMMAND
,
3987 MAX_ETH_TPA_UPDATE_COMMAND
3992 * Tx regular BD structure
3997 __le16 total_pkt_bytes
;
4004 * structure for easy accessibility to assembler
4006 struct eth_tx_bd_flags
{
4008 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0)
4009 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
4010 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1)
4011 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
4012 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2)
4013 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
4014 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4)
4015 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
4016 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5)
4017 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
4018 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6)
4019 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
4020 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7)
4021 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
4025 * The eth Tx Buffer Descriptor
4027 struct eth_tx_start_bd
{
4032 __le16 vlan_or_ethertype
;
4033 struct eth_tx_bd_flags bd_flags
;
4035 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
4036 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
4037 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
4038 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
4039 #define ETH_TX_START_BD_RESREVED (0x1<<5)
4040 #define ETH_TX_START_BD_RESREVED_SHIFT 5
4041 #define ETH_TX_START_BD_ETH_ADDR_TYPE (0x3<<6)
4042 #define ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT 6
4046 * Tx parsing BD structure for ETH E1/E1h
4048 struct eth_tx_parse_bd_e1x
{
4050 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0)
4051 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
4052 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x1<<4)
4053 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 4
4054 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<5)
4055 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 5
4056 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<6)
4057 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 6
4058 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<7)
4059 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 7
4061 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0)
4062 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
4063 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1)
4064 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
4065 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2)
4066 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
4067 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3)
4068 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
4069 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4)
4070 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
4071 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5)
4072 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
4073 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6)
4074 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
4075 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7)
4076 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
4079 __le16 total_hlen_w
;
4080 __le16 tcp_pseudo_csum
;
4083 __le32 tcp_send_seq
;
4087 * Tx parsing BD structure for ETH E2
4089 struct eth_tx_parse_bd_e2
{
4090 __le16 dst_mac_addr_lo
;
4091 __le16 dst_mac_addr_mid
;
4092 __le16 dst_mac_addr_hi
;
4093 __le16 src_mac_addr_lo
;
4094 __le16 src_mac_addr_mid
;
4095 __le16 src_mac_addr_hi
;
4096 __le32 parsing_data
;
4097 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W (0x1FFF<<0)
4098 #define ETH_TX_PARSE_BD_E2_TCP_HDR_START_OFFSET_W_SHIFT 0
4099 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<13)
4100 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 13
4101 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<17)
4102 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 17
4103 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<31)
4104 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 31
4108 * The last BD in the BD memory will hold a pointer to the next BD memory
4110 struct eth_tx_next_bd
{
4117 * union for 4 Bd types
4119 union eth_tx_bd_types
{
4120 struct eth_tx_start_bd start_bd
;
4121 struct eth_tx_bd reg_bd
;
4122 struct eth_tx_parse_bd_e1x parse_bd_e1x
;
4123 struct eth_tx_parse_bd_e2 parse_bd_e2
;
4124 struct eth_tx_next_bd next_bd
;
4128 * array of 13 bds as appears in the eth xstorm context
4130 struct eth_tx_bds_array
{
4131 union eth_tx_bd_types bds
[13];
4136 * VLAN mode on TX BDs
4138 enum eth_tx_vlan_type
{
4142 X_ETH_FW_ADDED_VLAN
,
4143 MAX_ETH_TX_VLAN_TYPE
4148 * Ethernet VLAN filtering mode in E1x
4150 enum eth_vlan_filter_mode
{
4151 ETH_VLAN_FILTER_ANY_VLAN
,
4152 ETH_VLAN_FILTER_SPECIFIC_VLAN
,
4153 ETH_VLAN_FILTER_CLASSIFY
,
4154 MAX_ETH_VLAN_FILTER_MODE
4159 * MAC filtering configuration command header
4161 struct mac_configuration_hdr
{
4169 * MAC address in list for ramrod
4171 struct mac_configuration_entry
{
4172 __le16 lsb_mac_addr
;
4173 __le16 middle_mac_addr
;
4174 __le16 msb_mac_addr
;
4178 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0)
4179 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
4180 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1)
4181 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
4182 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2)
4183 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
4184 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4)
4185 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
4186 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5)
4187 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
4188 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6)
4189 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
4191 __le32 clients_bit_vector
;
4195 * MAC filtering configuration command
4197 struct mac_configuration_cmd
{
4198 struct mac_configuration_hdr hdr
;
4199 struct mac_configuration_entry config_table
[64];
4204 * Set-MAC command type (in E1x)
4206 enum set_mac_action_type
{
4207 T_ETH_MAC_COMMAND_INVALIDATE
,
4208 T_ETH_MAC_COMMAND_SET
,
4209 MAX_SET_MAC_ACTION_TYPE
4214 * Ethernet TPA Modes
4223 * tpa update ramrod data
4225 struct tpa_update_ramrod_data
{
4230 u8 max_sges_for_packet
;
4231 u8 complete_on_both_clients
;
4232 u8 dont_verify_rings_pause_thr_flg
;
4234 __le16 sge_buff_size
;
4235 __le16 max_agg_size
;
4236 __le32 sge_page_base_lo
;
4237 __le32 sge_page_base_hi
;
4238 __le16 sge_pause_thr_low
;
4239 __le16 sge_pause_thr_high
;
4244 * approximate-match multicast filtering for E1H per function in Tstorm
4246 struct tstorm_eth_approximate_match_multicast_filtering
{
4247 u32 mcast_add_hash_bit_array
[8];
4252 * Common configuration parameters per function in Tstorm
4254 struct tstorm_eth_function_common_config
{
4255 __le16 config_flags
;
4256 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0)
4257 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
4258 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1)
4259 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
4260 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2)
4261 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
4262 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3)
4263 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
4264 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4)
4265 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
4266 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7)
4267 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
4268 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8)
4269 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
4277 * MAC filtering configuration parameters per port in Tstorm
4279 struct tstorm_eth_mac_filter_config
{
4280 __le32 ucast_drop_all
;
4281 __le32 ucast_accept_all
;
4282 __le32 mcast_drop_all
;
4283 __le32 mcast_accept_all
;
4284 __le32 bcast_accept_all
;
4285 __le32 vlan_filter
[2];
4286 __le32 unmatched_unicast
;
4291 * tx only queue init ramrod data
4293 struct tx_queue_init_ramrod_data
{
4294 struct client_init_general_data general
;
4295 struct client_init_tx_data tx
;
4300 * Three RX producers for ETH
4302 struct ustorm_eth_rx_producers
{
4303 #if defined(__BIG_ENDIAN)
4306 #elif defined(__LITTLE_ENDIAN)
4310 #if defined(__BIG_ENDIAN)
4313 #elif defined(__LITTLE_ENDIAN)
4321 * FCoE RX statistics parameters section#0
4323 struct fcoe_rx_stat_params_section0
{
4324 __le32 fcoe_rx_pkt_cnt
;
4325 __le32 fcoe_rx_byte_cnt
;
4330 * FCoE RX statistics parameters section#1
4332 struct fcoe_rx_stat_params_section1
{
4333 __le32 fcoe_ver_cnt
;
4334 __le32 fcoe_rx_drop_pkt_cnt
;
4339 * FCoE RX statistics parameters section#2
4341 struct fcoe_rx_stat_params_section2
{
4343 __le32 eofa_del_cnt
;
4344 __le32 miss_frame_cnt
;
4345 __le32 seq_timeout_cnt
;
4346 __le32 drop_seq_cnt
;
4347 __le32 fcoe_rx_drop_pkt_cnt
;
4348 __le32 fcp_rx_pkt_cnt
;
4354 * FCoE TX statistics parameters
4356 struct fcoe_tx_stat_params
{
4357 __le32 fcoe_tx_pkt_cnt
;
4358 __le32 fcoe_tx_byte_cnt
;
4359 __le32 fcp_tx_pkt_cnt
;
4364 * FCoE statistics parameters
4366 struct fcoe_statistics_params
{
4367 struct fcoe_tx_stat_params tx_stat
;
4368 struct fcoe_rx_stat_params_section0 rx_stat0
;
4369 struct fcoe_rx_stat_params_section1 rx_stat1
;
4370 struct fcoe_rx_stat_params_section2 rx_stat2
;
4375 * cfc delete event data
4377 struct cfc_del_event_data
{
4385 * per-port SAFC demo variables
4387 struct cmng_flags_per_port
{
4389 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0)
4390 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
4391 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1)
4392 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
4393 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2)
4394 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
4395 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3)
4396 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
4397 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4)
4398 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
4404 * per-port rate shaping variables
4406 struct rate_shaping_vars_per_port
{
4407 u32 rs_periodic_timeout
;
4412 * per-port fairness variables
4414 struct fairness_vars_per_port
{
4417 u32 fairness_timeout
;
4422 * per-port SAFC variables
4424 struct safc_struct_per_port
{
4425 #if defined(__BIG_ENDIAN)
4428 u8 safc_timeout_usec
;
4429 #elif defined(__LITTLE_ENDIAN)
4430 u8 safc_timeout_usec
;
4434 u8 cos_to_traffic_types
[MAX_COS_NUMBER
];
4435 u16 cos_to_pause_mask
[NUM_OF_SAFC_BITS
];
4439 * Per-port congestion management variables
4441 struct cmng_struct_per_port
{
4442 struct rate_shaping_vars_per_port rs_vars
;
4443 struct fairness_vars_per_port fair_vars
;
4444 struct safc_struct_per_port safc_vars
;
4445 struct cmng_flags_per_port flags
;
4450 * Protocol-common command ID for slow path elements
4452 enum common_spqe_cmd_id
{
4453 RAMROD_CMD_ID_COMMON_UNUSED
,
4454 RAMROD_CMD_ID_COMMON_FUNCTION_START
,
4455 RAMROD_CMD_ID_COMMON_FUNCTION_STOP
,
4456 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE
,
4457 RAMROD_CMD_ID_COMMON_CFC_DEL
,
4458 RAMROD_CMD_ID_COMMON_CFC_DEL_WB
,
4459 RAMROD_CMD_ID_COMMON_STAT_QUERY
,
4460 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC
,
4461 RAMROD_CMD_ID_COMMON_START_TRAFFIC
,
4462 RAMROD_CMD_ID_COMMON_RESERVED1
,
4463 MAX_COMMON_SPQE_CMD_ID
4468 * Per-protocol connection types
4470 enum connection_type
{
4471 ETH_CONNECTION_TYPE
,
4472 TOE_CONNECTION_TYPE
,
4473 RDMA_CONNECTION_TYPE
,
4474 ISCSI_CONNECTION_TYPE
,
4475 FCOE_CONNECTION_TYPE
,
4476 RESERVED_CONNECTION_TYPE_0
,
4477 RESERVED_CONNECTION_TYPE_1
,
4478 RESERVED_CONNECTION_TYPE_2
,
4479 NONE_CONNECTION_TYPE
,
4496 * Dynamic HC counters set by the driver
4498 struct hc_dynamic_drv_counter
{
4499 u32 val
[HC_SB_MAX_DYNAMIC_INDICES
];
4503 * zone A per-queue data
4505 struct cstorm_queue_zone_data
{
4506 struct hc_dynamic_drv_counter hc_dyn_drv_cnt
;
4507 struct regpair reserved
[2];
4512 * Vf-PF channel data in cstorm ram (non-triggered zone)
4514 struct vf_pf_channel_zone_data
{
4520 * zone for VF non-triggered data
4522 struct non_trigger_vf_zone
{
4523 struct vf_pf_channel_zone_data vf_pf_channel
;
4527 * Vf-PF channel trigger zone in cstorm ram
4529 struct vf_pf_channel_zone_trigger
{
4534 * zone that triggers the in-bound interrupt
4536 struct trigger_vf_zone
{
4537 #if defined(__BIG_ENDIAN)
4540 struct vf_pf_channel_zone_trigger vf_pf_channel
;
4541 #elif defined(__LITTLE_ENDIAN)
4542 struct vf_pf_channel_zone_trigger vf_pf_channel
;
4550 * zone B per-VF data
4552 struct cstorm_vf_zone_data
{
4553 struct non_trigger_vf_zone non_trigger
;
4554 struct trigger_vf_zone trigger
;
4559 * Dynamic host coalescing init parameters, per state machine
4561 struct dynamic_hc_sm_config
{
4563 u8 shift_per_protocol
[HC_SB_MAX_DYNAMIC_INDICES
];
4564 u8 hc_timeout0
[HC_SB_MAX_DYNAMIC_INDICES
];
4565 u8 hc_timeout1
[HC_SB_MAX_DYNAMIC_INDICES
];
4566 u8 hc_timeout2
[HC_SB_MAX_DYNAMIC_INDICES
];
4567 u8 hc_timeout3
[HC_SB_MAX_DYNAMIC_INDICES
];
4571 * Dynamic host coalescing init parameters
4573 struct dynamic_hc_config
{
4574 struct dynamic_hc_sm_config sm_config
[HC_SB_MAX_SM
];
4578 struct e2_integ_data
{
4579 #if defined(__BIG_ENDIAN)
4581 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4582 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4583 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4584 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4585 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4586 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4587 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4588 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4589 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4590 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4591 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4592 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4596 #elif defined(__LITTLE_ENDIAN)
4601 #define E2_INTEG_DATA_TESTING_EN (0x1<<0)
4602 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
4603 #define E2_INTEG_DATA_LB_TX (0x1<<1)
4604 #define E2_INTEG_DATA_LB_TX_SHIFT 1
4605 #define E2_INTEG_DATA_COS_TX (0x1<<2)
4606 #define E2_INTEG_DATA_COS_TX_SHIFT 2
4607 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3)
4608 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
4609 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4)
4610 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
4611 #define E2_INTEG_DATA_RESERVED (0x7<<5)
4612 #define E2_INTEG_DATA_RESERVED_SHIFT 5
4614 #if defined(__BIG_ENDIAN)
4618 #elif defined(__LITTLE_ENDIAN)
4627 * set mac event data
4629 struct eth_event_data
{
4639 struct vf_pf_event_data
{
4650 struct vf_flr_event_data
{
4659 * malicious VF event data
4661 struct malicious_vf_event_data
{
4670 * union for all event ring message types
4673 struct vf_pf_event_data vf_pf_event
;
4674 struct eth_event_data eth_event
;
4675 struct cfc_del_event_data cfc_del_event
;
4676 struct vf_flr_event_data vf_flr_event
;
4677 struct malicious_vf_event_data malicious_vf_event
;
4682 * per PF event ring data
4684 struct event_ring_data
{
4685 struct regpair base_addr
;
4686 #if defined(__BIG_ENDIAN)
4690 #elif defined(__LITTLE_ENDIAN)
4700 * event ring message element (each element is 128 bits)
4702 struct event_ring_msg
{
4706 union event_data data
;
4710 * event ring next page element (128 bits)
4712 struct event_ring_next
{
4713 struct regpair addr
;
4718 * union for event ring element types (each element is 128 bits)
4720 union event_ring_elem
{
4721 struct event_ring_msg message
;
4722 struct event_ring_next next_page
;
4727 * Common event ring opcodes
4729 enum event_ring_opcode
{
4730 EVENT_RING_OPCODE_VF_PF_CHANNEL
,
4731 EVENT_RING_OPCODE_FUNCTION_START
,
4732 EVENT_RING_OPCODE_FUNCTION_STOP
,
4733 EVENT_RING_OPCODE_CFC_DEL
,
4734 EVENT_RING_OPCODE_CFC_DEL_WB
,
4735 EVENT_RING_OPCODE_STAT_QUERY
,
4736 EVENT_RING_OPCODE_STOP_TRAFFIC
,
4737 EVENT_RING_OPCODE_START_TRAFFIC
,
4738 EVENT_RING_OPCODE_VF_FLR
,
4739 EVENT_RING_OPCODE_MALICIOUS_VF
,
4740 EVENT_RING_OPCODE_FORWARD_SETUP
,
4741 EVENT_RING_OPCODE_RSS_UPDATE_RULES
,
4742 EVENT_RING_OPCODE_FUNCTION_UPDATE
,
4743 EVENT_RING_OPCODE_RESERVED1
,
4744 EVENT_RING_OPCODE_SET_MAC
,
4745 EVENT_RING_OPCODE_CLASSIFICATION_RULES
,
4746 EVENT_RING_OPCODE_FILTERS_RULES
,
4747 EVENT_RING_OPCODE_MULTICAST_RULES
,
4748 MAX_EVENT_RING_OPCODE
4753 * Modes for fairness algorithm
4755 enum fairness_mode
{
4756 FAIRNESS_COS_WRR_MODE
,
4757 FAIRNESS_COS_ETS_MODE
,
4763 * per-vnic fairness variables
4765 struct fairness_vars_per_vn
{
4766 u32 cos_credit_delta
[MAX_COS_NUMBER
];
4767 u32 vn_credit_delta
;
4775 struct priority_cos
{
4782 * The data for flow control configuration
4784 struct flow_control_configuration
{
4785 struct priority_cos traffic_type_to_priority_cos
[MAX_TRAFFIC_TYPES
];
4788 u8 dont_add_pri_0_en
;
4797 struct function_start_data
{
4798 __le16 function_mode
;
4802 u8 network_cos_mode
;
4807 * FW version stored in the Xstorm RAM
4810 #if defined(__BIG_ENDIAN)
4815 #elif defined(__LITTLE_ENDIAN)
4822 #define FW_VERSION_OPTIMIZED (0x1<<0)
4823 #define FW_VERSION_OPTIMIZED_SHIFT 0
4824 #define FW_VERSION_BIG_ENDIEN (0x1<<1)
4825 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
4826 #define FW_VERSION_CHIP_VERSION (0x3<<2)
4827 #define FW_VERSION_CHIP_VERSION_SHIFT 2
4828 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4)
4829 #define __FW_VERSION_RESERVED_SHIFT 4
4834 * Dynamic Host-Coalescing - Driver(host) counters
4836 struct hc_dynamic_sb_drv_counters
{
4837 u32 dynamic_hc_drv_counter
[HC_SB_MAX_DYNAMIC_INDICES
];
4842 * 2 bytes. configuration/state parameters for a single protocol index
4844 struct hc_index_data
{
4845 #if defined(__BIG_ENDIAN)
4847 #define HC_INDEX_DATA_SM_ID (0x1<<0)
4848 #define HC_INDEX_DATA_SM_ID_SHIFT 0
4849 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4850 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4851 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4852 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4853 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
4854 #define HC_INDEX_DATA_RESERVE_SHIFT 3
4856 #elif defined(__LITTLE_ENDIAN)
4859 #define HC_INDEX_DATA_SM_ID (0x1<<0)
4860 #define HC_INDEX_DATA_SM_ID_SHIFT 0
4861 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1)
4862 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
4863 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2)
4864 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
4865 #define HC_INDEX_DATA_RESERVE (0x1F<<3)
4866 #define HC_INDEX_DATA_RESERVE_SHIFT 3
4874 struct hc_status_block_sm
{
4875 #if defined(__BIG_ENDIAN)
4880 #elif defined(__LITTLE_ENDIAN)
4890 * hold PCI identification variables- used in various places in firmware
4893 #if defined(__BIG_ENDIAN)
4898 #elif defined(__LITTLE_ENDIAN)
4907 * The fast-path status block meta-data, common to all chips
4910 struct regpair host_sb_addr
;
4911 struct hc_status_block_sm state_machine
[HC_SB_MAX_SM
];
4912 struct pci_entity p_func
;
4913 #if defined(__BIG_ENDIAN)
4918 #elif defined(__LITTLE_ENDIAN)
4924 struct regpair rsrv1
[2];
4929 * Segment types for host coaslescing
4939 * The fast-path status block meta-data
4941 struct hc_sp_status_block_data
{
4942 struct regpair host_sb_addr
;
4943 #if defined(__BIG_ENDIAN)
4948 #elif defined(__LITTLE_ENDIAN)
4954 struct pci_entity p_func
;
4959 * The fast-path status block meta-data
4961 struct hc_status_block_data_e1x
{
4962 struct hc_index_data index_data
[HC_SB_MAX_INDICES_E1X
];
4963 struct hc_sb_data common
;
4968 * The fast-path status block meta-data
4970 struct hc_status_block_data_e2
{
4971 struct hc_index_data index_data
[HC_SB_MAX_INDICES_E2
];
4972 struct hc_sb_data common
;
4977 * IGU block operartion modes (in Everest2)
4997 * Multi-function modes
5003 MULTI_FUNCTION_RESERVED
,
5008 * Protocol-common statistics collected by the Tstorm (per pf)
5010 struct tstorm_per_pf_stats
{
5011 struct regpair rcv_error_bytes
;
5017 struct per_pf_stats
{
5018 struct tstorm_per_pf_stats tstorm_pf_statistics
;
5023 * Protocol-common statistics collected by the Tstorm (per port)
5025 struct tstorm_per_port_stats
{
5027 __le32 mac_filter_discard
;
5028 __le32 brb_truncate_discard
;
5029 __le32 mf_tag_discard
;
5037 struct per_port_stats
{
5038 struct tstorm_per_port_stats tstorm_port_statistics
;
5043 * Protocol-common statistics collected by the Tstorm (per client)
5045 struct tstorm_per_queue_stats
{
5046 struct regpair rcv_ucast_bytes
;
5047 __le32 rcv_ucast_pkts
;
5048 __le32 checksum_discard
;
5049 struct regpair rcv_bcast_bytes
;
5050 __le32 rcv_bcast_pkts
;
5051 __le32 pkts_too_big_discard
;
5052 struct regpair rcv_mcast_bytes
;
5053 __le32 rcv_mcast_pkts
;
5054 __le32 ttl0_discard
;
5055 __le16 no_buff_discard
;
5061 * Protocol-common statistics collected by the Ustorm (per client)
5063 struct ustorm_per_queue_stats
{
5064 struct regpair ucast_no_buff_bytes
;
5065 struct regpair mcast_no_buff_bytes
;
5066 struct regpair bcast_no_buff_bytes
;
5067 __le32 ucast_no_buff_pkts
;
5068 __le32 mcast_no_buff_pkts
;
5069 __le32 bcast_no_buff_pkts
;
5070 __le32 coalesced_pkts
;
5071 struct regpair coalesced_bytes
;
5072 __le32 coalesced_events
;
5073 __le32 coalesced_aborts
;
5077 * Protocol-common statistics collected by the Xstorm (per client)
5079 struct xstorm_per_queue_stats
{
5080 struct regpair ucast_bytes_sent
;
5081 struct regpair mcast_bytes_sent
;
5082 struct regpair bcast_bytes_sent
;
5083 __le32 ucast_pkts_sent
;
5084 __le32 mcast_pkts_sent
;
5085 __le32 bcast_pkts_sent
;
5086 __le32 error_drop_pkts
;
5092 struct per_queue_stats
{
5093 struct tstorm_per_queue_stats tstorm_queue_statistics
;
5094 struct ustorm_per_queue_stats ustorm_queue_statistics
;
5095 struct xstorm_per_queue_stats xstorm_queue_statistics
;
5100 * FW version stored in first line of pram
5102 struct pram_fw_version
{
5108 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0)
5109 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
5110 #define PRAM_FW_VERSION_STORM_ID (0x3<<1)
5111 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
5112 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3)
5113 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
5114 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4)
5115 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
5116 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6)
5117 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
5122 * Ethernet slow path element
5124 union protocol_common_specific_data
{
5125 u8 protocol_data
[8];
5126 struct regpair phy_address
;
5127 struct regpair mac_config_addr
;
5131 * The send queue element
5133 struct protocol_common_spe
{
5135 union protocol_common_specific_data data
;
5140 * a single rate shaping counter. can be used as protocol or vnic counter
5142 struct rate_shaping_counter
{
5144 #if defined(__BIG_ENDIAN)
5147 #elif defined(__LITTLE_ENDIAN)
5155 * per-vnic rate shaping variables
5157 struct rate_shaping_vars_per_vn
{
5158 struct rate_shaping_counter vn_counter
;
5163 * The send queue element
5165 struct slow_path_element
{
5167 struct regpair protocol_data
;
5172 * Protocol-common statistics counter
5174 struct stats_counter
{
5175 __le16 xstats_counter
;
5178 __le16 tstats_counter
;
5181 __le16 ustats_counter
;
5184 __le16 cstats_counter
;
5193 struct stats_query_entry
{
5198 struct regpair address
;
5204 struct stats_query_cmd_group
{
5205 struct stats_query_entry query
[STATS_QUERY_CMD_COUNT
];
5210 * statistic command header
5212 struct stats_query_header
{
5215 __le16 drv_stats_counter
;
5217 struct regpair stats_counters_addrs
;
5222 * Types of statistcis query entry
5224 enum stats_query_type
{
5230 MAX_STATS_QUERY_TYPE
5235 * Indicate of the function status block state
5237 enum status_block_state
{
5241 MAX_STATUS_BLOCK_STATE
5246 * Storm IDs (including attentions for IGU related enums)
5259 * Taffic types used in ETS and flow control algorithms
5262 LLFC_TRAFFIC_TYPE_NW
,
5263 LLFC_TRAFFIC_TYPE_FCOE
,
5264 LLFC_TRAFFIC_TYPE_ISCSI
,
5270 * zone A per-queue data
5272 struct tstorm_queue_zone_data
{
5273 struct regpair reserved
[4];
5278 * zone B per-VF data
5280 struct tstorm_vf_zone_data
{
5281 struct regpair reserved
;
5286 * zone A per-queue data
5288 struct ustorm_queue_zone_data
{
5289 struct ustorm_eth_rx_producers eth_rx_producers
;
5290 struct regpair reserved
[3];
5295 * zone B per-VF data
5297 struct ustorm_vf_zone_data
{
5298 struct regpair reserved
;
5303 * data per VF-PF channel
5305 struct vf_pf_channel_data
{
5306 #if defined(__BIG_ENDIAN)
5310 #elif defined(__LITTLE_ENDIAN)
5320 * State of VF-PF channel
5322 enum vf_pf_channel_state
{
5323 VF_PF_CHANNEL_STATE_READY
,
5324 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK
,
5325 MAX_VF_PF_CHANNEL_STATE
5330 * zone A per-queue data
5332 struct xstorm_queue_zone_data
{
5333 struct regpair reserved
[4];
5338 * zone B per-VF data
5340 struct xstorm_vf_zone_data
{
5341 struct regpair reserved
;
5344 #endif /* BNX2X_HSI_H */