1 /* Copyright 2008-2012 Broadcom Corporation
3 * Unless you and Broadcom execute a separate written software license
4 * agreement governing use of this software, this software is licensed to you
5 * under the terms of the GNU General Public License version 2, available
6 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
8 * Notwithstanding the above, under no circumstances may you combine this
9 * software in any way with any other Broadcom software provided under a
10 * license other than the GPL, without Broadcom's express prior written
13 * Written by Yaniv Rosner
17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/delay.h>
24 #include <linux/ethtool.h>
25 #include <linux/mutex.h>
28 #include "bnx2x_cmn.h"
30 /********************************************************/
32 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
33 #define ETH_OVREHEAD (ETH_HLEN + 8 + 8)
34 #define ETH_MIN_PACKET_SIZE 60
35 #define ETH_MAX_PACKET_SIZE 1500
36 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
37 #define MDIO_ACCESS_TIMEOUT 1000
39 #define I2C_SWITCH_WIDTH 2
42 #define I2C_WA_RETRY_CNT 3
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
44 #define MCPR_IMC_COMMAND_READ_OP 1
45 #define MCPR_IMC_COMMAND_WRITE_OP 2
47 /* LED Blink rate that will achieve ~15.9Hz */
48 #define LED_BLINK_RATE_VAL_E3 354
49 #define LED_BLINK_RATE_VAL_E1X_E2 480
50 /***********************************************************/
51 /* Shortcut definitions */
52 /***********************************************************/
54 #define NIG_LATCH_BC_ENABLE_MI_INT 0
56 #define NIG_STATUS_EMAC0_MI_INT \
57 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
58 #define NIG_STATUS_XGXS0_LINK10G \
59 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
60 #define NIG_STATUS_XGXS0_LINK_STATUS \
61 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
62 #define NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
63 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
64 #define NIG_STATUS_SERDES0_LINK_STATUS \
65 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
66 #define NIG_MASK_MI_INT \
67 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
68 #define NIG_MASK_XGXS0_LINK10G \
69 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
70 #define NIG_MASK_XGXS0_LINK_STATUS \
71 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
72 #define NIG_MASK_SERDES0_LINK_STATUS \
73 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
75 #define MDIO_AN_CL73_OR_37_COMPLETE \
76 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
77 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
79 #define XGXS_RESET_BITS \
80 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
81 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
82 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
83 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
84 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
86 #define SERDES_RESET_BITS \
87 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
88 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
89 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
90 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
92 #define AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
93 #define AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
94 #define AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
95 #define AUTONEG_PARALLEL \
96 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
97 #define AUTONEG_SGMII_FIBER_AUTODET \
98 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
99 #define AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
101 #define GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
102 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
103 #define GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
104 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
105 #define GP_STATUS_SPEED_MASK \
106 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
107 #define GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
108 #define GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
109 #define GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
110 #define GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
111 #define GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
112 #define GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
113 #define GP_STATUS_10G_HIG \
114 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
115 #define GP_STATUS_10G_CX4 \
116 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
117 #define GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
118 #define GP_STATUS_10G_KX4 \
119 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
120 #define GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
121 #define GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
122 #define GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
123 #define GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
124 #define LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
125 #define LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
126 #define LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
127 #define LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
128 #define LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
129 #define LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
130 #define LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
131 #define LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
132 #define LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
133 #define LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
134 #define LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
135 #define LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
136 #define LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
137 #define LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
138 #define LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
142 #define SFP_EEPROM_CON_TYPE_ADDR 0x2
143 #define SFP_EEPROM_CON_TYPE_VAL_LC 0x7
144 #define SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
147 #define SFP_EEPROM_COMP_CODE_ADDR 0x3
148 #define SFP_EEPROM_COMP_CODE_SR_MASK (1<<4)
149 #define SFP_EEPROM_COMP_CODE_LR_MASK (1<<5)
150 #define SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6)
152 #define SFP_EEPROM_FC_TX_TECH_ADDR 0x8
153 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
154 #define SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
156 #define SFP_EEPROM_OPTIONS_ADDR 0x40
157 #define SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
158 #define SFP_EEPROM_OPTIONS_SIZE 2
160 #define EDC_MODE_LINEAR 0x0022
161 #define EDC_MODE_LIMITING 0x0044
162 #define EDC_MODE_PASSIVE_DAC 0x0055
164 /* BRB default for class 0 E2 */
165 #define DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR 170
166 #define DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR 250
167 #define DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR 10
168 #define DEFAULT0_E2_BRB_MAC_FULL_XON_THR 50
170 /* BRB thresholds for E2*/
171 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE 170
172 #define PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
174 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE 250
175 #define PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
177 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE 10
178 #define PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 90
180 #define PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE 50
181 #define PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE 250
183 /* BRB default for class 0 E3A0 */
184 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR 290
185 #define DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR 410
186 #define DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR 10
187 #define DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR 50
189 /* BRB thresholds for E3A0 */
190 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE 290
191 #define PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
193 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE 410
194 #define PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
196 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE 10
197 #define PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 170
199 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE 50
200 #define PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE 410
202 /* BRB default for E3B0 */
203 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR 330
204 #define DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR 490
205 #define DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR 15
206 #define DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR 55
208 /* BRB thresholds for E3B0 2 port mode*/
209 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 1025
210 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
212 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE 1025
213 #define PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
215 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
216 #define PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 1025
218 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE 50
219 #define PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE 1025
222 #define PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR 1025
223 #define PFC_E3B0_2P_BRB_FULL_LB_XON_THR 1025
225 /* Lossy +Lossless GUARANTIED == GUART */
226 #define PFC_E3B0_2P_MIX_PAUSE_LB_GUART 284
227 /* Lossless +Lossless*/
228 #define PFC_E3B0_2P_PAUSE_LB_GUART 236
230 #define PFC_E3B0_2P_NON_PAUSE_LB_GUART 342
233 #define PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART 284
234 /* Lossless +Lossless*/
235 #define PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART 236
237 #define PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART 336
238 #define PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST 80
240 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART 0
241 #define PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST 0
243 /* BRB thresholds for E3B0 4 port mode */
244 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE 304
245 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE 0
247 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE 384
248 #define PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE 0
250 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE 10
251 #define PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE 304
253 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE 50
254 #define PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE 384
257 #define PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR 304
258 #define PFC_E3B0_4P_BRB_FULL_LB_XON_THR 384
259 #define PFC_E3B0_4P_LB_GUART 120
261 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART 120
262 #define PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST 80
264 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART 80
265 #define PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST 120
268 #define DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR 330
269 #define DEFAULT_E3B0_BRB_FULL_LB_XON_THR 490
270 #define DEFAULT_E3B0_LB_GUART 40
272 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART 40
273 #define DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST 0
275 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART 40
276 #define DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST 0
279 #define DCBX_INVALID_COS (0xFF)
281 #define ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
282 #define ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
283 #define ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
284 #define ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
285 #define ETS_E3B0_PBF_MIN_W_VAL (10000)
287 #define MAX_PACKET_SIZE (9700)
288 #define MAX_KR_LINK_RETRY 4
290 /**********************************************************/
292 /**********************************************************/
294 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
295 bnx2x_cl45_write(_bp, _phy, \
296 (_phy)->def_md_devad, \
297 (_bank + (_addr & 0xf)), \
300 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \
301 bnx2x_cl45_read(_bp, _phy, \
302 (_phy)->def_md_devad, \
303 (_bank + (_addr & 0xf)), \
306 static u32
bnx2x_bits_en(struct bnx2x
*bp
, u32 reg
, u32 bits
)
308 u32 val
= REG_RD(bp
, reg
);
311 REG_WR(bp
, reg
, val
);
315 static u32
bnx2x_bits_dis(struct bnx2x
*bp
, u32 reg
, u32 bits
)
317 u32 val
= REG_RD(bp
, reg
);
320 REG_WR(bp
, reg
, val
);
324 /******************************************************************/
325 /* EPIO/GPIO section */
326 /******************************************************************/
327 static void bnx2x_get_epio(struct bnx2x
*bp
, u32 epio_pin
, u32
*en
)
329 u32 epio_mask
, gp_oenable
;
333 DP(NETIF_MSG_LINK
, "Invalid EPIO pin %d to get\n", epio_pin
);
337 epio_mask
= 1 << epio_pin
;
338 /* Set this EPIO to output */
339 gp_oenable
= REG_RD(bp
, MCP_REG_MCPR_GP_OENABLE
);
340 REG_WR(bp
, MCP_REG_MCPR_GP_OENABLE
, gp_oenable
& ~epio_mask
);
342 *en
= (REG_RD(bp
, MCP_REG_MCPR_GP_INPUTS
) & epio_mask
) >> epio_pin
;
344 static void bnx2x_set_epio(struct bnx2x
*bp
, u32 epio_pin
, u32 en
)
346 u32 epio_mask
, gp_output
, gp_oenable
;
350 DP(NETIF_MSG_LINK
, "Invalid EPIO pin %d to set\n", epio_pin
);
353 DP(NETIF_MSG_LINK
, "Setting EPIO pin %d to %d\n", epio_pin
, en
);
354 epio_mask
= 1 << epio_pin
;
355 /* Set this EPIO to output */
356 gp_output
= REG_RD(bp
, MCP_REG_MCPR_GP_OUTPUTS
);
358 gp_output
|= epio_mask
;
360 gp_output
&= ~epio_mask
;
362 REG_WR(bp
, MCP_REG_MCPR_GP_OUTPUTS
, gp_output
);
364 /* Set the value for this EPIO */
365 gp_oenable
= REG_RD(bp
, MCP_REG_MCPR_GP_OENABLE
);
366 REG_WR(bp
, MCP_REG_MCPR_GP_OENABLE
, gp_oenable
| epio_mask
);
369 static void bnx2x_set_cfg_pin(struct bnx2x
*bp
, u32 pin_cfg
, u32 val
)
371 if (pin_cfg
== PIN_CFG_NA
)
373 if (pin_cfg
>= PIN_CFG_EPIO0
) {
374 bnx2x_set_epio(bp
, pin_cfg
- PIN_CFG_EPIO0
, val
);
376 u8 gpio_num
= (pin_cfg
- PIN_CFG_GPIO0_P0
) & 0x3;
377 u8 gpio_port
= (pin_cfg
- PIN_CFG_GPIO0_P0
) >> 2;
378 bnx2x_set_gpio(bp
, gpio_num
, (u8
)val
, gpio_port
);
382 static u32
bnx2x_get_cfg_pin(struct bnx2x
*bp
, u32 pin_cfg
, u32
*val
)
384 if (pin_cfg
== PIN_CFG_NA
)
386 if (pin_cfg
>= PIN_CFG_EPIO0
) {
387 bnx2x_get_epio(bp
, pin_cfg
- PIN_CFG_EPIO0
, val
);
389 u8 gpio_num
= (pin_cfg
- PIN_CFG_GPIO0_P0
) & 0x3;
390 u8 gpio_port
= (pin_cfg
- PIN_CFG_GPIO0_P0
) >> 2;
391 *val
= bnx2x_get_gpio(bp
, gpio_num
, gpio_port
);
396 /******************************************************************/
398 /******************************************************************/
399 static void bnx2x_ets_e2e3a0_disabled(struct link_params
*params
)
401 /* ETS disabled configuration*/
402 struct bnx2x
*bp
= params
->bp
;
404 DP(NETIF_MSG_LINK
, "ETS E2E3 disabled configuration\n");
406 /* mapping between entry priority to client number (0,1,2 -debug and
407 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
409 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
410 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
413 REG_WR(bp
, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT
, 0x4688);
414 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
415 * as strict. Bits 0,1,2 - debug and management entries, 3 -
416 * COS0 entry, 4 - COS1 entry.
417 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
418 * bit4 bit3 bit2 bit1 bit0
419 * MCP and debug are strict
422 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT
, 0x7);
423 /* defines which entries (clients) are subjected to WFQ arbitration */
424 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ
, 0);
425 /* For strict priority entries defines the number of consecutive
426 * slots for the highest priority.
428 REG_WR(bp
, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS
, 0x100);
429 /* mapping between the CREDIT_WEIGHT registers and actual client
432 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP
, 0);
433 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0
, 0);
434 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1
, 0);
436 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0
, 0);
437 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1
, 0);
438 REG_WR(bp
, PBF_REG_HIGH_PRIORITY_COS_NUM
, 0);
439 /* ETS mode disable */
440 REG_WR(bp
, PBF_REG_ETS_ENABLED
, 0);
441 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
442 * weight for COS0/COS1.
444 REG_WR(bp
, PBF_REG_COS0_WEIGHT
, 0x2710);
445 REG_WR(bp
, PBF_REG_COS1_WEIGHT
, 0x2710);
446 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
447 REG_WR(bp
, PBF_REG_COS0_UPPER_BOUND
, 0x989680);
448 REG_WR(bp
, PBF_REG_COS1_UPPER_BOUND
, 0x989680);
449 /* Defines the number of consecutive slots for the strict priority */
450 REG_WR(bp
, PBF_REG_NUM_STRICT_ARB_SLOTS
, 0);
452 /******************************************************************************
454 * Getting min_w_val will be set according to line speed .
456 ******************************************************************************/
457 static u32
bnx2x_ets_get_min_w_val_nig(const struct link_vars
*vars
)
460 /* Calculate min_w_val.*/
462 if (vars
->line_speed
== SPEED_20000
)
463 min_w_val
= ETS_E3B0_NIG_MIN_W_VAL_20GBPS
;
465 min_w_val
= ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS
;
467 min_w_val
= ETS_E3B0_NIG_MIN_W_VAL_20GBPS
;
468 /* If the link isn't up (static configuration for example ) The
469 * link will be according to 20GBPS.
473 /******************************************************************************
475 * Getting credit upper bound form min_w_val.
477 ******************************************************************************/
478 static u32
bnx2x_ets_get_credit_upper_bound(const u32 min_w_val
)
480 const u32 credit_upper_bound
= (u32
)MAXVAL((150 * min_w_val
),
482 return credit_upper_bound
;
484 /******************************************************************************
486 * Set credit upper bound for NIG.
488 ******************************************************************************/
489 static void bnx2x_ets_e3b0_set_credit_upper_bound_nig(
490 const struct link_params
*params
,
493 struct bnx2x
*bp
= params
->bp
;
494 const u8 port
= params
->port
;
495 const u32 credit_upper_bound
=
496 bnx2x_ets_get_credit_upper_bound(min_w_val
);
498 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0
:
499 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0
, credit_upper_bound
);
500 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1
:
501 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1
, credit_upper_bound
);
502 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2
:
503 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2
, credit_upper_bound
);
504 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3
:
505 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3
, credit_upper_bound
);
506 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4
:
507 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4
, credit_upper_bound
);
508 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5
:
509 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5
, credit_upper_bound
);
512 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6
,
514 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7
,
516 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8
,
520 /******************************************************************************
522 * Will return the NIG ETS registers to init values.Except
523 * credit_upper_bound.
524 * That isn't used in this configuration (No WFQ is enabled) and will be
525 * configured acording to spec
527 ******************************************************************************/
528 static void bnx2x_ets_e3b0_nig_disabled(const struct link_params
*params
,
529 const struct link_vars
*vars
)
531 struct bnx2x
*bp
= params
->bp
;
532 const u8 port
= params
->port
;
533 const u32 min_w_val
= bnx2x_ets_get_min_w_val_nig(vars
);
534 /* Mapping between entry priority to client number (0,1,2 -debug and
535 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
536 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
537 * reset value or init tool
540 REG_WR(bp
, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB
, 0x543210);
541 REG_WR(bp
, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB
, 0x0);
543 REG_WR(bp
, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB
, 0x76543210);
544 REG_WR(bp
, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB
, 0x8);
546 /* For strict priority entries defines the number of consecutive
547 * slots for the highest priority.
549 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS
:
550 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS
, 0x100);
551 /* Mapping between the CREDIT_WEIGHT registers and actual client
556 REG_WR(bp
, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB
, 0x210543);
557 REG_WR(bp
, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB
, 0x0);
560 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB
,
562 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB
, 0x5);
565 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
566 * as strict. Bits 0,1,2 - debug and management entries, 3 -
567 * COS0 entry, 4 - COS1 entry.
568 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
569 * bit4 bit3 bit2 bit1 bit0
570 * MCP and debug are strict
573 REG_WR(bp
, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT
, 0x3f);
575 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT
, 0x1ff);
576 /* defines which entries (clients) are subjected to WFQ arbitration */
577 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ
:
578 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ
, 0);
580 /* Please notice the register address are note continuous and a
581 * for here is note appropriate.In 2 port mode port0 only COS0-5
582 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
583 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
584 * are never used for WFQ
586 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0
:
587 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0
, 0x0);
588 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1
:
589 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1
, 0x0);
590 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2
:
591 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2
, 0x0);
592 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3
:
593 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3
, 0x0);
594 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4
:
595 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4
, 0x0);
596 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5
:
597 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5
, 0x0);
599 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6
, 0x0);
600 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7
, 0x0);
601 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8
, 0x0);
604 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params
, min_w_val
);
606 /******************************************************************************
608 * Set credit upper bound for PBF.
610 ******************************************************************************/
611 static void bnx2x_ets_e3b0_set_credit_upper_bound_pbf(
612 const struct link_params
*params
,
615 struct bnx2x
*bp
= params
->bp
;
616 const u32 credit_upper_bound
=
617 bnx2x_ets_get_credit_upper_bound(min_w_val
);
618 const u8 port
= params
->port
;
619 u32 base_upper_bound
= 0;
622 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
623 * port mode port1 has COS0-2 that can be used for WFQ.
626 base_upper_bound
= PBF_REG_COS0_UPPER_BOUND_P0
;
627 max_cos
= DCBX_E3B0_MAX_NUM_COS_PORT0
;
629 base_upper_bound
= PBF_REG_COS0_UPPER_BOUND_P1
;
630 max_cos
= DCBX_E3B0_MAX_NUM_COS_PORT1
;
633 for (i
= 0; i
< max_cos
; i
++)
634 REG_WR(bp
, base_upper_bound
+ (i
<< 2), credit_upper_bound
);
637 /******************************************************************************
639 * Will return the PBF ETS registers to init values.Except
640 * credit_upper_bound.
641 * That isn't used in this configuration (No WFQ is enabled) and will be
642 * configured acording to spec
644 ******************************************************************************/
645 static void bnx2x_ets_e3b0_pbf_disabled(const struct link_params
*params
)
647 struct bnx2x
*bp
= params
->bp
;
648 const u8 port
= params
->port
;
649 const u32 min_w_val_pbf
= ETS_E3B0_PBF_MIN_W_VAL
;
654 /* Mapping between entry priority to client number 0 - COS0
655 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
656 * TODO_ETS - Should be done by reset value or init tool
659 /* 0x688 (|011|0 10|00 1|000) */
660 REG_WR(bp
, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1
, 0x688);
662 /* (10 1|100 |011|0 10|00 1|000) */
663 REG_WR(bp
, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0
, 0x2C688);
665 /* TODO_ETS - Should be done by reset value or init tool */
667 /* 0x688 (|011|0 10|00 1|000)*/
668 REG_WR(bp
, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1
, 0x688);
670 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
671 REG_WR(bp
, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0
, 0x2C688);
673 REG_WR(bp
, (port
) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1
:
674 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0
, 0x100);
677 REG_WR(bp
, (port
) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1
:
678 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0
, 0);
680 REG_WR(bp
, (port
) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1
:
681 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0
, 0);
682 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
683 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
686 base_weight
= PBF_REG_COS0_WEIGHT_P0
;
687 max_cos
= DCBX_E3B0_MAX_NUM_COS_PORT0
;
689 base_weight
= PBF_REG_COS0_WEIGHT_P1
;
690 max_cos
= DCBX_E3B0_MAX_NUM_COS_PORT1
;
693 for (i
= 0; i
< max_cos
; i
++)
694 REG_WR(bp
, base_weight
+ (0x4 * i
), 0);
696 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params
, min_w_val_pbf
);
698 /******************************************************************************
700 * E3B0 disable will return basicly the values to init values.
702 ******************************************************************************/
703 static int bnx2x_ets_e3b0_disabled(const struct link_params
*params
,
704 const struct link_vars
*vars
)
706 struct bnx2x
*bp
= params
->bp
;
708 if (!CHIP_IS_E3B0(bp
)) {
710 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
714 bnx2x_ets_e3b0_nig_disabled(params
, vars
);
716 bnx2x_ets_e3b0_pbf_disabled(params
);
721 /******************************************************************************
723 * Disable will return basicly the values to init values.
725 ******************************************************************************/
726 int bnx2x_ets_disabled(struct link_params
*params
,
727 struct link_vars
*vars
)
729 struct bnx2x
*bp
= params
->bp
;
730 int bnx2x_status
= 0;
732 if ((CHIP_IS_E2(bp
)) || (CHIP_IS_E3A0(bp
)))
733 bnx2x_ets_e2e3a0_disabled(params
);
734 else if (CHIP_IS_E3B0(bp
))
735 bnx2x_status
= bnx2x_ets_e3b0_disabled(params
, vars
);
737 DP(NETIF_MSG_LINK
, "bnx2x_ets_disabled - chip not supported\n");
744 /******************************************************************************
746 * Set the COS mappimg to SP and BW until this point all the COS are not
748 ******************************************************************************/
749 static int bnx2x_ets_e3b0_cli_map(const struct link_params
*params
,
750 const struct bnx2x_ets_params
*ets_params
,
751 const u8 cos_sp_bitmap
,
752 const u8 cos_bw_bitmap
)
754 struct bnx2x
*bp
= params
->bp
;
755 const u8 port
= params
->port
;
756 const u8 nig_cli_sp_bitmap
= 0x7 | (cos_sp_bitmap
<< 3);
757 const u8 pbf_cli_sp_bitmap
= cos_sp_bitmap
;
758 const u8 nig_cli_subject2wfq_bitmap
= cos_bw_bitmap
<< 3;
759 const u8 pbf_cli_subject2wfq_bitmap
= cos_bw_bitmap
;
761 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT
:
762 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT
, nig_cli_sp_bitmap
);
764 REG_WR(bp
, (port
) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1
:
765 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0
, pbf_cli_sp_bitmap
);
767 REG_WR(bp
, (port
) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ
:
768 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ
,
769 nig_cli_subject2wfq_bitmap
);
771 REG_WR(bp
, (port
) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1
:
772 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0
,
773 pbf_cli_subject2wfq_bitmap
);
778 /******************************************************************************
780 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
781 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
782 ******************************************************************************/
783 static int bnx2x_ets_e3b0_set_cos_bw(struct bnx2x
*bp
,
785 const u32 min_w_val_nig
,
786 const u32 min_w_val_pbf
,
791 u32 nig_reg_adress_crd_weight
= 0;
792 u32 pbf_reg_adress_crd_weight
= 0;
793 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
794 const u32 cos_bw_nig
= ((bw
? bw
: 1) * min_w_val_nig
) / total_bw
;
795 const u32 cos_bw_pbf
= ((bw
? bw
: 1) * min_w_val_pbf
) / total_bw
;
799 nig_reg_adress_crd_weight
=
800 (port
) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0
:
801 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0
;
802 pbf_reg_adress_crd_weight
= (port
) ?
803 PBF_REG_COS0_WEIGHT_P1
: PBF_REG_COS0_WEIGHT_P0
;
806 nig_reg_adress_crd_weight
= (port
) ?
807 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1
:
808 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1
;
809 pbf_reg_adress_crd_weight
= (port
) ?
810 PBF_REG_COS1_WEIGHT_P1
: PBF_REG_COS1_WEIGHT_P0
;
813 nig_reg_adress_crd_weight
= (port
) ?
814 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2
:
815 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2
;
817 pbf_reg_adress_crd_weight
= (port
) ?
818 PBF_REG_COS2_WEIGHT_P1
: PBF_REG_COS2_WEIGHT_P0
;
823 nig_reg_adress_crd_weight
=
824 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3
;
825 pbf_reg_adress_crd_weight
=
826 PBF_REG_COS3_WEIGHT_P0
;
831 nig_reg_adress_crd_weight
=
832 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4
;
833 pbf_reg_adress_crd_weight
= PBF_REG_COS4_WEIGHT_P0
;
838 nig_reg_adress_crd_weight
=
839 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5
;
840 pbf_reg_adress_crd_weight
= PBF_REG_COS5_WEIGHT_P0
;
844 REG_WR(bp
, nig_reg_adress_crd_weight
, cos_bw_nig
);
846 REG_WR(bp
, pbf_reg_adress_crd_weight
, cos_bw_pbf
);
850 /******************************************************************************
852 * Calculate the total BW.A value of 0 isn't legal.
854 ******************************************************************************/
855 static int bnx2x_ets_e3b0_get_total_bw(
856 const struct link_params
*params
,
857 struct bnx2x_ets_params
*ets_params
,
860 struct bnx2x
*bp
= params
->bp
;
862 u8 is_bw_cos_exist
= 0;
865 /* Calculate total BW requested */
866 for (cos_idx
= 0; cos_idx
< ets_params
->num_of_cos
; cos_idx
++) {
867 if (ets_params
->cos
[cos_idx
].state
== bnx2x_cos_state_bw
) {
869 if (!ets_params
->cos
[cos_idx
].params
.bw_params
.bw
) {
870 DP(NETIF_MSG_LINK
, "bnx2x_ets_E3B0_config BW"
872 /* This is to prevent a state when ramrods
875 ets_params
->cos
[cos_idx
].params
.bw_params
.bw
879 ets_params
->cos
[cos_idx
].params
.bw_params
.bw
;
883 /* Check total BW is valid */
884 if ((is_bw_cos_exist
== 1) && (*total_bw
!= 100)) {
885 if (*total_bw
== 0) {
887 "bnx2x_ets_E3B0_config total BW shouldn't be 0\n");
891 "bnx2x_ets_E3B0_config total BW should be 100\n");
892 /* We can handle a case whre the BW isn't 100 this can happen
893 * if the TC are joined.
899 /******************************************************************************
901 * Invalidate all the sp_pri_to_cos.
903 ******************************************************************************/
904 static void bnx2x_ets_e3b0_sp_pri_to_cos_init(u8
*sp_pri_to_cos
)
907 for (pri
= 0; pri
< DCBX_MAX_NUM_COS
; pri
++)
908 sp_pri_to_cos
[pri
] = DCBX_INVALID_COS
;
910 /******************************************************************************
912 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
913 * according to sp_pri_to_cos.
915 ******************************************************************************/
916 static int bnx2x_ets_e3b0_sp_pri_to_cos_set(const struct link_params
*params
,
917 u8
*sp_pri_to_cos
, const u8 pri
,
920 struct bnx2x
*bp
= params
->bp
;
921 const u8 port
= params
->port
;
922 const u8 max_num_of_cos
= (port
) ? DCBX_E3B0_MAX_NUM_COS_PORT1
:
923 DCBX_E3B0_MAX_NUM_COS_PORT0
;
925 if (pri
>= max_num_of_cos
) {
926 DP(NETIF_MSG_LINK
, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
927 "parameter Illegal strict priority\n");
931 if (sp_pri_to_cos
[pri
] != DCBX_INVALID_COS
) {
932 DP(NETIF_MSG_LINK
, "bnx2x_ets_e3b0_sp_pri_to_cos_set invalid "
933 "parameter There can't be two COS's with "
934 "the same strict pri\n");
938 sp_pri_to_cos
[pri
] = cos_entry
;
943 /******************************************************************************
945 * Returns the correct value according to COS and priority in
946 * the sp_pri_cli register.
948 ******************************************************************************/
949 static u64
bnx2x_e3b0_sp_get_pri_cli_reg(const u8 cos
, const u8 cos_offset
,
955 pri_cli_nig
= ((u64
)(cos
+ cos_offset
)) << (entry_size
*
956 (pri_set
+ pri_offset
));
960 /******************************************************************************
962 * Returns the correct value according to COS and priority in the
963 * sp_pri_cli register for NIG.
965 ******************************************************************************/
966 static u64
bnx2x_e3b0_sp_get_pri_cli_reg_nig(const u8 cos
, const u8 pri_set
)
968 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
969 const u8 nig_cos_offset
= 3;
970 const u8 nig_pri_offset
= 3;
972 return bnx2x_e3b0_sp_get_pri_cli_reg(cos
, nig_cos_offset
, pri_set
,
976 /******************************************************************************
978 * Returns the correct value according to COS and priority in the
979 * sp_pri_cli register for PBF.
981 ******************************************************************************/
982 static u64
bnx2x_e3b0_sp_get_pri_cli_reg_pbf(const u8 cos
, const u8 pri_set
)
984 const u8 pbf_cos_offset
= 0;
985 const u8 pbf_pri_offset
= 0;
987 return bnx2x_e3b0_sp_get_pri_cli_reg(cos
, pbf_cos_offset
, pri_set
,
992 /******************************************************************************
994 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
995 * according to sp_pri_to_cos.(which COS has higher priority)
997 ******************************************************************************/
998 static int bnx2x_ets_e3b0_sp_set_pri_cli_reg(const struct link_params
*params
,
1001 struct bnx2x
*bp
= params
->bp
;
1003 const u8 port
= params
->port
;
1004 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1005 u64 pri_cli_nig
= 0x210;
1006 u32 pri_cli_pbf
= 0x0;
1009 const u8 max_num_of_cos
= (port
) ? DCBX_E3B0_MAX_NUM_COS_PORT1
:
1010 DCBX_E3B0_MAX_NUM_COS_PORT0
;
1012 u8 cos_bit_to_set
= (1 << max_num_of_cos
) - 1;
1014 /* Set all the strict priority first */
1015 for (i
= 0; i
< max_num_of_cos
; i
++) {
1016 if (sp_pri_to_cos
[i
] != DCBX_INVALID_COS
) {
1017 if (sp_pri_to_cos
[i
] >= DCBX_MAX_NUM_COS
) {
1019 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1020 "invalid cos entry\n");
1024 pri_cli_nig
|= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1025 sp_pri_to_cos
[i
], pri_set
);
1027 pri_cli_pbf
|= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1028 sp_pri_to_cos
[i
], pri_set
);
1029 pri_bitmask
= 1 << sp_pri_to_cos
[i
];
1030 /* COS is used remove it from bitmap.*/
1031 if (!(pri_bitmask
& cos_bit_to_set
)) {
1033 "bnx2x_ets_e3b0_sp_set_pri_cli_reg "
1034 "invalid There can't be two COS's with"
1035 " the same strict pri\n");
1038 cos_bit_to_set
&= ~pri_bitmask
;
1043 /* Set all the Non strict priority i= COS*/
1044 for (i
= 0; i
< max_num_of_cos
; i
++) {
1045 pri_bitmask
= 1 << i
;
1046 /* Check if COS was already used for SP */
1047 if (pri_bitmask
& cos_bit_to_set
) {
1048 /* COS wasn't used for SP */
1049 pri_cli_nig
|= bnx2x_e3b0_sp_get_pri_cli_reg_nig(
1052 pri_cli_pbf
|= bnx2x_e3b0_sp_get_pri_cli_reg_pbf(
1054 /* COS is used remove it from bitmap.*/
1055 cos_bit_to_set
&= ~pri_bitmask
;
1060 if (pri_set
!= max_num_of_cos
) {
1061 DP(NETIF_MSG_LINK
, "bnx2x_ets_e3b0_sp_set_pri_cli_reg not all "
1062 "entries were set\n");
1067 /* Only 6 usable clients*/
1068 REG_WR(bp
, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB
,
1071 REG_WR(bp
, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1
, pri_cli_pbf
);
1073 /* Only 9 usable clients*/
1074 const u32 pri_cli_nig_lsb
= (u32
) (pri_cli_nig
);
1075 const u32 pri_cli_nig_msb
= (u32
) ((pri_cli_nig
>> 32) & 0xF);
1077 REG_WR(bp
, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB
,
1079 REG_WR(bp
, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB
,
1082 REG_WR(bp
, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0
, pri_cli_pbf
);
1087 /******************************************************************************
1089 * Configure the COS to ETS according to BW and SP settings.
1090 ******************************************************************************/
1091 int bnx2x_ets_e3b0_config(const struct link_params
*params
,
1092 const struct link_vars
*vars
,
1093 struct bnx2x_ets_params
*ets_params
)
1095 struct bnx2x
*bp
= params
->bp
;
1096 int bnx2x_status
= 0;
1097 const u8 port
= params
->port
;
1099 const u32 min_w_val_nig
= bnx2x_ets_get_min_w_val_nig(vars
);
1100 const u32 min_w_val_pbf
= ETS_E3B0_PBF_MIN_W_VAL
;
1101 u8 cos_bw_bitmap
= 0;
1102 u8 cos_sp_bitmap
= 0;
1103 u8 sp_pri_to_cos
[DCBX_MAX_NUM_COS
] = {0};
1104 const u8 max_num_of_cos
= (port
) ? DCBX_E3B0_MAX_NUM_COS_PORT1
:
1105 DCBX_E3B0_MAX_NUM_COS_PORT0
;
1108 if (!CHIP_IS_E3B0(bp
)) {
1110 "bnx2x_ets_e3b0_disabled the chip isn't E3B0\n");
1114 if ((ets_params
->num_of_cos
> max_num_of_cos
)) {
1115 DP(NETIF_MSG_LINK
, "bnx2x_ets_E3B0_config the number of COS "
1116 "isn't supported\n");
1120 /* Prepare sp strict priority parameters*/
1121 bnx2x_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos
);
1123 /* Prepare BW parameters*/
1124 bnx2x_status
= bnx2x_ets_e3b0_get_total_bw(params
, ets_params
,
1128 "bnx2x_ets_E3B0_config get_total_bw failed\n");
1132 /* Upper bound is set according to current link speed (min_w_val
1133 * should be the same for upper bound and COS credit val).
1135 bnx2x_ets_e3b0_set_credit_upper_bound_nig(params
, min_w_val_nig
);
1136 bnx2x_ets_e3b0_set_credit_upper_bound_pbf(params
, min_w_val_pbf
);
1139 for (cos_entry
= 0; cos_entry
< ets_params
->num_of_cos
; cos_entry
++) {
1140 if (bnx2x_cos_state_bw
== ets_params
->cos
[cos_entry
].state
) {
1141 cos_bw_bitmap
|= (1 << cos_entry
);
1142 /* The function also sets the BW in HW(not the mappin
1145 bnx2x_status
= bnx2x_ets_e3b0_set_cos_bw(
1146 bp
, cos_entry
, min_w_val_nig
, min_w_val_pbf
,
1148 ets_params
->cos
[cos_entry
].params
.bw_params
.bw
,
1150 } else if (bnx2x_cos_state_strict
==
1151 ets_params
->cos
[cos_entry
].state
){
1152 cos_sp_bitmap
|= (1 << cos_entry
);
1154 bnx2x_status
= bnx2x_ets_e3b0_sp_pri_to_cos_set(
1157 ets_params
->cos
[cos_entry
].params
.sp_params
.pri
,
1162 "bnx2x_ets_e3b0_config cos state not valid\n");
1167 "bnx2x_ets_e3b0_config set cos bw failed\n");
1168 return bnx2x_status
;
1172 /* Set SP register (which COS has higher priority) */
1173 bnx2x_status
= bnx2x_ets_e3b0_sp_set_pri_cli_reg(params
,
1178 "bnx2x_ets_E3B0_config set_pri_cli_reg failed\n");
1179 return bnx2x_status
;
1182 /* Set client mapping of BW and strict */
1183 bnx2x_status
= bnx2x_ets_e3b0_cli_map(params
, ets_params
,
1188 DP(NETIF_MSG_LINK
, "bnx2x_ets_E3B0_config SP failed\n");
1189 return bnx2x_status
;
1193 static void bnx2x_ets_bw_limit_common(const struct link_params
*params
)
1195 /* ETS disabled configuration */
1196 struct bnx2x
*bp
= params
->bp
;
1197 DP(NETIF_MSG_LINK
, "ETS enabled BW limit configuration\n");
1198 /* Defines which entries (clients) are subjected to WFQ arbitration
1202 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ
, 0x18);
1203 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1204 * client numbers (WEIGHT_0 does not actually have to represent
1206 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1207 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1209 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP
, 0x111A);
1211 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0
,
1212 ETS_BW_LIMIT_CREDIT_UPPER_BOUND
);
1213 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1
,
1214 ETS_BW_LIMIT_CREDIT_UPPER_BOUND
);
1216 /* ETS mode enabled*/
1217 REG_WR(bp
, PBF_REG_ETS_ENABLED
, 1);
1219 /* Defines the number of consecutive slots for the strict priority */
1220 REG_WR(bp
, PBF_REG_NUM_STRICT_ARB_SLOTS
, 0);
1221 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1222 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1223 * entry, 4 - COS1 entry.
1224 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1225 * bit4 bit3 bit2 bit1 bit0
1226 * MCP and debug are strict
1228 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT
, 0x7);
1230 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
1231 REG_WR(bp
, PBF_REG_COS0_UPPER_BOUND
,
1232 ETS_BW_LIMIT_CREDIT_UPPER_BOUND
);
1233 REG_WR(bp
, PBF_REG_COS1_UPPER_BOUND
,
1234 ETS_BW_LIMIT_CREDIT_UPPER_BOUND
);
1237 void bnx2x_ets_bw_limit(const struct link_params
*params
, const u32 cos0_bw
,
1240 /* ETS disabled configuration*/
1241 struct bnx2x
*bp
= params
->bp
;
1242 const u32 total_bw
= cos0_bw
+ cos1_bw
;
1243 u32 cos0_credit_weight
= 0;
1244 u32 cos1_credit_weight
= 0;
1246 DP(NETIF_MSG_LINK
, "ETS enabled BW limit configuration\n");
1251 DP(NETIF_MSG_LINK
, "Total BW can't be zero\n");
1255 cos0_credit_weight
= (cos0_bw
* ETS_BW_LIMIT_CREDIT_WEIGHT
)/
1257 cos1_credit_weight
= (cos1_bw
* ETS_BW_LIMIT_CREDIT_WEIGHT
)/
1260 bnx2x_ets_bw_limit_common(params
);
1262 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0
, cos0_credit_weight
);
1263 REG_WR(bp
, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1
, cos1_credit_weight
);
1265 REG_WR(bp
, PBF_REG_COS0_WEIGHT
, cos0_credit_weight
);
1266 REG_WR(bp
, PBF_REG_COS1_WEIGHT
, cos1_credit_weight
);
1269 int bnx2x_ets_strict(const struct link_params
*params
, const u8 strict_cos
)
1271 /* ETS disabled configuration*/
1272 struct bnx2x
*bp
= params
->bp
;
1275 DP(NETIF_MSG_LINK
, "ETS enabled strict configuration\n");
1276 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1277 * as strict. Bits 0,1,2 - debug and management entries,
1278 * 3 - COS0 entry, 4 - COS1 entry.
1279 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1280 * bit4 bit3 bit2 bit1 bit0
1281 * MCP and debug are strict
1283 REG_WR(bp
, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT
, 0x1F);
1284 /* For strict priority entries defines the number of consecutive slots
1285 * for the highest priority.
1287 REG_WR(bp
, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS
, 0x100);
1288 /* ETS mode disable */
1289 REG_WR(bp
, PBF_REG_ETS_ENABLED
, 0);
1290 /* Defines the number of consecutive slots for the strict priority */
1291 REG_WR(bp
, PBF_REG_NUM_STRICT_ARB_SLOTS
, 0x100);
1293 /* Defines the number of consecutive slots for the strict priority */
1294 REG_WR(bp
, PBF_REG_HIGH_PRIORITY_COS_NUM
, strict_cos
);
1296 /* Mapping between entry priority to client number (0,1,2 -debug and
1297 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1299 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1300 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
1301 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
1303 val
= (!strict_cos
) ? 0x2318 : 0x22E0;
1304 REG_WR(bp
, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT
, val
);
1309 /******************************************************************/
1311 /******************************************************************/
1312 static u8
bnx2x_eee_has_cap(struct link_params
*params
)
1314 struct bnx2x
*bp
= params
->bp
;
1316 if (REG_RD(bp
, params
->shmem2_base
) <=
1317 offsetof(struct shmem2_region
, eee_status
[params
->port
]))
1323 static int bnx2x_eee_nvram_to_time(u32 nvram_mode
, u32
*idle_timer
)
1325 switch (nvram_mode
) {
1326 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED
:
1327 *idle_timer
= EEE_MODE_NVRAM_BALANCED_TIME
;
1329 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE
:
1330 *idle_timer
= EEE_MODE_NVRAM_AGGRESSIVE_TIME
;
1332 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY
:
1333 *idle_timer
= EEE_MODE_NVRAM_LATENCY_TIME
;
1343 static int bnx2x_eee_time_to_nvram(u32 idle_timer
, u32
*nvram_mode
)
1345 switch (idle_timer
) {
1346 case EEE_MODE_NVRAM_BALANCED_TIME
:
1347 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED
;
1349 case EEE_MODE_NVRAM_AGGRESSIVE_TIME
:
1350 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE
;
1352 case EEE_MODE_NVRAM_LATENCY_TIME
:
1353 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY
;
1356 *nvram_mode
= PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
;
1363 static u32
bnx2x_eee_calc_timer(struct link_params
*params
)
1365 u32 eee_mode
, eee_idle
;
1366 struct bnx2x
*bp
= params
->bp
;
1368 if (params
->eee_mode
& EEE_MODE_OVERRIDE_NVRAM
) {
1369 if (params
->eee_mode
& EEE_MODE_OUTPUT_TIME
) {
1370 /* time value in eee_mode --> used directly*/
1371 eee_idle
= params
->eee_mode
& EEE_MODE_TIMER_MASK
;
1373 /* hsi value in eee_mode --> time */
1374 if (bnx2x_eee_nvram_to_time(params
->eee_mode
&
1375 EEE_MODE_NVRAM_MASK
,
1380 /* hsi values in nvram --> time*/
1381 eee_mode
= ((REG_RD(bp
, params
->shmem_base
+
1382 offsetof(struct shmem_region
, dev_info
.
1383 port_feature_config
[params
->port
].
1385 PORT_FEAT_CFG_EEE_POWER_MODE_MASK
) >>
1386 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
);
1388 if (bnx2x_eee_nvram_to_time(eee_mode
, &eee_idle
))
1396 /******************************************************************/
1398 /******************************************************************/
1399 static void bnx2x_update_pfc_xmac(struct link_params
*params
,
1400 struct link_vars
*vars
,
1403 struct bnx2x
*bp
= params
->bp
;
1405 u32 pause_val
, pfc0_val
, pfc1_val
;
1407 /* XMAC base adrr */
1408 xmac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
1410 /* Initialize pause and pfc registers */
1411 pause_val
= 0x18000;
1412 pfc0_val
= 0xFFFF8000;
1415 /* No PFC support */
1416 if (!(params
->feature_config_flags
&
1417 FEATURE_CONFIG_PFC_ENABLED
)) {
1419 /* RX flow control - Process pause frame in receive direction
1421 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
)
1422 pause_val
|= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN
;
1424 /* TX flow control - Send pause packet when buffer is full */
1425 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
1426 pause_val
|= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN
;
1427 } else {/* PFC support */
1428 pfc1_val
|= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN
|
1429 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN
|
1430 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN
|
1431 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN
|
1432 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON
;
1433 /* Write pause and PFC registers */
1434 REG_WR(bp
, xmac_base
+ XMAC_REG_PAUSE_CTRL
, pause_val
);
1435 REG_WR(bp
, xmac_base
+ XMAC_REG_PFC_CTRL
, pfc0_val
);
1436 REG_WR(bp
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
, pfc1_val
);
1437 pfc1_val
&= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON
;
1441 /* Write pause and PFC registers */
1442 REG_WR(bp
, xmac_base
+ XMAC_REG_PAUSE_CTRL
, pause_val
);
1443 REG_WR(bp
, xmac_base
+ XMAC_REG_PFC_CTRL
, pfc0_val
);
1444 REG_WR(bp
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
, pfc1_val
);
1447 /* Set MAC address for source TX Pause/PFC frames */
1448 REG_WR(bp
, xmac_base
+ XMAC_REG_CTRL_SA_LO
,
1449 ((params
->mac_addr
[2] << 24) |
1450 (params
->mac_addr
[3] << 16) |
1451 (params
->mac_addr
[4] << 8) |
1452 (params
->mac_addr
[5])));
1453 REG_WR(bp
, xmac_base
+ XMAC_REG_CTRL_SA_HI
,
1454 ((params
->mac_addr
[0] << 8) |
1455 (params
->mac_addr
[1])));
1461 static void bnx2x_emac_get_pfc_stat(struct link_params
*params
,
1462 u32 pfc_frames_sent
[2],
1463 u32 pfc_frames_received
[2])
1465 /* Read pfc statistic */
1466 struct bnx2x
*bp
= params
->bp
;
1467 u32 emac_base
= params
->port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
1471 DP(NETIF_MSG_LINK
, "pfc statistic read from EMAC\n");
1473 /* PFC received frames */
1474 val_xoff
= REG_RD(bp
, emac_base
+
1475 EMAC_REG_RX_PFC_STATS_XOFF_RCVD
);
1476 val_xoff
&= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT
;
1477 val_xon
= REG_RD(bp
, emac_base
+ EMAC_REG_RX_PFC_STATS_XON_RCVD
);
1478 val_xon
&= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT
;
1480 pfc_frames_received
[0] = val_xon
+ val_xoff
;
1482 /* PFC received sent */
1483 val_xoff
= REG_RD(bp
, emac_base
+
1484 EMAC_REG_RX_PFC_STATS_XOFF_SENT
);
1485 val_xoff
&= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT
;
1486 val_xon
= REG_RD(bp
, emac_base
+ EMAC_REG_RX_PFC_STATS_XON_SENT
);
1487 val_xon
&= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT
;
1489 pfc_frames_sent
[0] = val_xon
+ val_xoff
;
1492 /* Read pfc statistic*/
1493 void bnx2x_pfc_statistic(struct link_params
*params
, struct link_vars
*vars
,
1494 u32 pfc_frames_sent
[2],
1495 u32 pfc_frames_received
[2])
1497 /* Read pfc statistic */
1498 struct bnx2x
*bp
= params
->bp
;
1500 DP(NETIF_MSG_LINK
, "pfc statistic\n");
1505 if (vars
->mac_type
== MAC_TYPE_EMAC
) {
1506 DP(NETIF_MSG_LINK
, "About to read PFC stats from EMAC\n");
1507 bnx2x_emac_get_pfc_stat(params
, pfc_frames_sent
,
1508 pfc_frames_received
);
1511 /******************************************************************/
1512 /* MAC/PBF section */
1513 /******************************************************************/
1514 static void bnx2x_set_mdio_clk(struct bnx2x
*bp
, u32 chip_id
, u8 port
)
1516 u32 mode
, emac_base
;
1517 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
1518 * (a value of 49==0x31) and make sure that the AUTO poll is off
1522 emac_base
= GRCBASE_EMAC0
;
1524 emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
1525 mode
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MDIO_MODE
);
1526 mode
&= ~(EMAC_MDIO_MODE_AUTO_POLL
|
1527 EMAC_MDIO_MODE_CLOCK_CNT
);
1528 if (USES_WARPCORE(bp
))
1529 mode
|= (74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
);
1531 mode
|= (49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT
);
1533 mode
|= (EMAC_MDIO_MODE_CLAUSE_45
);
1534 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_MDIO_MODE
, mode
);
1538 static u8
bnx2x_is_4_port_mode(struct bnx2x
*bp
)
1540 u32 port4mode_ovwr_val
;
1541 /* Check 4-port override enabled */
1542 port4mode_ovwr_val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
);
1543 if (port4mode_ovwr_val
& (1<<0)) {
1544 /* Return 4-port mode override value */
1545 return ((port4mode_ovwr_val
& (1<<1)) == (1<<1));
1547 /* Return 4-port mode from input pin */
1548 return (u8
)REG_RD(bp
, MISC_REG_PORT4MODE_EN
);
1551 static void bnx2x_emac_init(struct link_params
*params
,
1552 struct link_vars
*vars
)
1554 /* reset and unreset the emac core */
1555 struct bnx2x
*bp
= params
->bp
;
1556 u8 port
= params
->port
;
1557 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
1561 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1562 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
1564 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1565 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
<< port
));
1567 /* init emac - use read-modify-write */
1568 /* self clear reset */
1569 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
1570 EMAC_WR(bp
, EMAC_REG_EMAC_MODE
, (val
| EMAC_MODE_RESET
));
1574 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
1575 DP(NETIF_MSG_LINK
, "EMAC reset reg is %u\n", val
);
1577 DP(NETIF_MSG_LINK
, "EMAC timeout!\n");
1581 } while (val
& EMAC_MODE_RESET
);
1582 bnx2x_set_mdio_clk(bp
, params
->chip_id
, port
);
1583 /* Set mac address */
1584 val
= ((params
->mac_addr
[0] << 8) |
1585 params
->mac_addr
[1]);
1586 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
, val
);
1588 val
= ((params
->mac_addr
[2] << 24) |
1589 (params
->mac_addr
[3] << 16) |
1590 (params
->mac_addr
[4] << 8) |
1591 params
->mac_addr
[5]);
1592 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ 4, val
);
1595 static void bnx2x_set_xumac_nig(struct link_params
*params
,
1599 struct bnx2x
*bp
= params
->bp
;
1601 REG_WR(bp
, params
->port
? NIG_REG_P1_MAC_IN_EN
: NIG_REG_P0_MAC_IN_EN
,
1603 REG_WR(bp
, params
->port
? NIG_REG_P1_MAC_OUT_EN
: NIG_REG_P0_MAC_OUT_EN
,
1605 REG_WR(bp
, params
->port
? NIG_REG_P1_MAC_PAUSE_OUT_EN
:
1606 NIG_REG_P0_MAC_PAUSE_OUT_EN
, tx_pause_en
);
1609 static void bnx2x_umac_disable(struct link_params
*params
)
1611 u32 umac_base
= params
->port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
1612 struct bnx2x
*bp
= params
->bp
;
1613 if (!(REG_RD(bp
, MISC_REG_RESET_REG_2
) &
1614 (MISC_REGISTERS_RESET_REG_2_UMAC0
<< params
->port
)))
1617 /* Disable RX and TX */
1618 REG_WR(bp
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, 0);
1621 static void bnx2x_umac_enable(struct link_params
*params
,
1622 struct link_vars
*vars
, u8 lb
)
1625 u32 umac_base
= params
->port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
1626 struct bnx2x
*bp
= params
->bp
;
1628 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1629 (MISC_REGISTERS_RESET_REG_2_UMAC0
<< params
->port
));
1630 usleep_range(1000, 2000);
1632 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1633 (MISC_REGISTERS_RESET_REG_2_UMAC0
<< params
->port
));
1635 DP(NETIF_MSG_LINK
, "enabling UMAC\n");
1637 /* This register opens the gate for the UMAC despite its name */
1638 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
*4, 1);
1640 val
= UMAC_COMMAND_CONFIG_REG_PROMIS_EN
|
1641 UMAC_COMMAND_CONFIG_REG_PAD_EN
|
1642 UMAC_COMMAND_CONFIG_REG_SW_RESET
|
1643 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK
;
1644 switch (vars
->line_speed
) {
1658 DP(NETIF_MSG_LINK
, "Invalid speed for UMAC %d\n",
1662 if (!(vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
))
1663 val
|= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE
;
1665 if (!(vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
))
1666 val
|= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE
;
1668 if (vars
->duplex
== DUPLEX_HALF
)
1669 val
|= UMAC_COMMAND_CONFIG_REG_HD_ENA
;
1671 REG_WR(bp
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1674 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
1675 REG_WR(bp
, umac_base
+ UMAC_REG_MAC_ADDR0
,
1676 ((params
->mac_addr
[2] << 24) |
1677 (params
->mac_addr
[3] << 16) |
1678 (params
->mac_addr
[4] << 8) |
1679 (params
->mac_addr
[5])));
1680 REG_WR(bp
, umac_base
+ UMAC_REG_MAC_ADDR1
,
1681 ((params
->mac_addr
[0] << 8) |
1682 (params
->mac_addr
[1])));
1684 /* Enable RX and TX */
1685 val
&= ~UMAC_COMMAND_CONFIG_REG_PAD_EN
;
1686 val
|= UMAC_COMMAND_CONFIG_REG_TX_ENA
|
1687 UMAC_COMMAND_CONFIG_REG_RX_ENA
;
1688 REG_WR(bp
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1691 /* Remove SW Reset */
1692 val
&= ~UMAC_COMMAND_CONFIG_REG_SW_RESET
;
1694 /* Check loopback mode */
1696 val
|= UMAC_COMMAND_CONFIG_REG_LOOP_ENA
;
1697 REG_WR(bp
, umac_base
+ UMAC_REG_COMMAND_CONFIG
, val
);
1699 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
1700 * length used by the MAC receive logic to check frames.
1702 REG_WR(bp
, umac_base
+ UMAC_REG_MAXFR
, 0x2710);
1703 bnx2x_set_xumac_nig(params
,
1704 ((vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
) != 0), 1);
1705 vars
->mac_type
= MAC_TYPE_UMAC
;
1709 /* Define the XMAC mode */
1710 static void bnx2x_xmac_init(struct link_params
*params
, u32 max_speed
)
1712 struct bnx2x
*bp
= params
->bp
;
1713 u32 is_port4mode
= bnx2x_is_4_port_mode(bp
);
1715 /* In 4-port mode, need to set the mode only once, so if XMAC is
1716 * already out of reset, it means the mode has already been set,
1717 * and it must not* reset the XMAC again, since it controls both
1721 if ((CHIP_NUM(bp
) == CHIP_NUM_57840_4_10
) &&
1722 (REG_RD(bp
, MISC_REG_RESET_REG_2
) &
1723 MISC_REGISTERS_RESET_REG_2_XMAC
)) {
1725 "XMAC already out of reset in 4-port mode\n");
1730 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1731 MISC_REGISTERS_RESET_REG_2_XMAC
);
1732 usleep_range(1000, 2000);
1734 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1735 MISC_REGISTERS_RESET_REG_2_XMAC
);
1737 DP(NETIF_MSG_LINK
, "Init XMAC to 2 ports x 10G per path\n");
1739 /* Set the number of ports on the system side to up to 2 */
1740 REG_WR(bp
, MISC_REG_XMAC_CORE_PORT_MODE
, 1);
1742 /* Set the number of ports on the Warp Core to 10G */
1743 REG_WR(bp
, MISC_REG_XMAC_PHY_PORT_MODE
, 3);
1745 /* Set the number of ports on the system side to 1 */
1746 REG_WR(bp
, MISC_REG_XMAC_CORE_PORT_MODE
, 0);
1747 if (max_speed
== SPEED_10000
) {
1749 "Init XMAC to 10G x 1 port per path\n");
1750 /* Set the number of ports on the Warp Core to 10G */
1751 REG_WR(bp
, MISC_REG_XMAC_PHY_PORT_MODE
, 3);
1754 "Init XMAC to 20G x 2 ports per path\n");
1755 /* Set the number of ports on the Warp Core to 20G */
1756 REG_WR(bp
, MISC_REG_XMAC_PHY_PORT_MODE
, 1);
1760 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1761 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
);
1762 usleep_range(1000, 2000);
1764 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
1765 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
);
1769 static void bnx2x_xmac_disable(struct link_params
*params
)
1771 u8 port
= params
->port
;
1772 struct bnx2x
*bp
= params
->bp
;
1773 u32 pfc_ctrl
, xmac_base
= (port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
1775 if (REG_RD(bp
, MISC_REG_RESET_REG_2
) &
1776 MISC_REGISTERS_RESET_REG_2_XMAC
) {
1777 /* Send an indication to change the state in the NIG back to XON
1778 * Clearing this bit enables the next set of this bit to get
1781 pfc_ctrl
= REG_RD(bp
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
);
1782 REG_WR(bp
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
,
1783 (pfc_ctrl
& ~(1<<1)));
1784 REG_WR(bp
, xmac_base
+ XMAC_REG_PFC_CTRL_HI
,
1785 (pfc_ctrl
| (1<<1)));
1786 DP(NETIF_MSG_LINK
, "Disable XMAC on port %x\n", port
);
1787 REG_WR(bp
, xmac_base
+ XMAC_REG_CTRL
, 0);
1791 static int bnx2x_xmac_enable(struct link_params
*params
,
1792 struct link_vars
*vars
, u8 lb
)
1795 struct bnx2x
*bp
= params
->bp
;
1796 DP(NETIF_MSG_LINK
, "enabling XMAC\n");
1798 xmac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
1800 bnx2x_xmac_init(params
, vars
->line_speed
);
1802 /* This register determines on which events the MAC will assert
1803 * error on the i/f to the NIG along w/ EOP.
1806 /* This register tells the NIG whether to send traffic to UMAC
1809 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
*4, 0);
1811 /* Set Max packet size */
1812 REG_WR(bp
, xmac_base
+ XMAC_REG_RX_MAX_SIZE
, 0x2710);
1814 /* CRC append for Tx packets */
1815 REG_WR(bp
, xmac_base
+ XMAC_REG_TX_CTRL
, 0xC800);
1818 bnx2x_update_pfc_xmac(params
, vars
, 0);
1820 if (vars
->eee_status
& SHMEM_EEE_ADV_STATUS_MASK
) {
1821 DP(NETIF_MSG_LINK
, "Setting XMAC for EEE\n");
1822 REG_WR(bp
, xmac_base
+ XMAC_REG_EEE_TIMERS_HI
, 0x1380008);
1823 REG_WR(bp
, xmac_base
+ XMAC_REG_EEE_CTRL
, 0x1);
1825 REG_WR(bp
, xmac_base
+ XMAC_REG_EEE_CTRL
, 0x0);
1828 /* Enable TX and RX */
1829 val
= XMAC_CTRL_REG_TX_EN
| XMAC_CTRL_REG_RX_EN
;
1831 /* Check loopback mode */
1833 val
|= XMAC_CTRL_REG_LINE_LOCAL_LPBK
;
1834 REG_WR(bp
, xmac_base
+ XMAC_REG_CTRL
, val
);
1835 bnx2x_set_xumac_nig(params
,
1836 ((vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
) != 0), 1);
1838 vars
->mac_type
= MAC_TYPE_XMAC
;
1843 static int bnx2x_emac_enable(struct link_params
*params
,
1844 struct link_vars
*vars
, u8 lb
)
1846 struct bnx2x
*bp
= params
->bp
;
1847 u8 port
= params
->port
;
1848 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
1851 DP(NETIF_MSG_LINK
, "enabling EMAC\n");
1854 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
1855 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
1857 /* enable emac and not bmac */
1858 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ port
*4, 1);
1861 if (vars
->phy_flags
& PHY_XGXS_FLAG
) {
1862 u32 ser_lane
= ((params
->lane_config
&
1863 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
1864 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
1866 DP(NETIF_MSG_LINK
, "XGXS\n");
1867 /* select the master lanes (out of 0-3) */
1868 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+ port
*4, ser_lane
);
1870 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
1872 } else { /* SerDes */
1873 DP(NETIF_MSG_LINK
, "SerDes\n");
1875 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 0);
1878 bnx2x_bits_en(bp
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
1879 EMAC_RX_MODE_RESET
);
1880 bnx2x_bits_en(bp
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
1881 EMAC_TX_MODE_RESET
);
1883 /* pause enable/disable */
1884 bnx2x_bits_dis(bp
, emac_base
+ EMAC_REG_EMAC_RX_MODE
,
1885 EMAC_RX_MODE_FLOW_EN
);
1887 bnx2x_bits_dis(bp
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
1888 (EMAC_TX_MODE_EXT_PAUSE_EN
|
1889 EMAC_TX_MODE_FLOW_EN
));
1890 if (!(params
->feature_config_flags
&
1891 FEATURE_CONFIG_PFC_ENABLED
)) {
1892 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
)
1893 bnx2x_bits_en(bp
, emac_base
+
1894 EMAC_REG_EMAC_RX_MODE
,
1895 EMAC_RX_MODE_FLOW_EN
);
1897 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
1898 bnx2x_bits_en(bp
, emac_base
+
1899 EMAC_REG_EMAC_TX_MODE
,
1900 (EMAC_TX_MODE_EXT_PAUSE_EN
|
1901 EMAC_TX_MODE_FLOW_EN
));
1903 bnx2x_bits_en(bp
, emac_base
+ EMAC_REG_EMAC_TX_MODE
,
1904 EMAC_TX_MODE_FLOW_EN
);
1906 /* KEEP_VLAN_TAG, promiscuous */
1907 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_RX_MODE
);
1908 val
|= EMAC_RX_MODE_KEEP_VLAN_TAG
| EMAC_RX_MODE_PROMISCUOUS
;
1910 /* Setting this bit causes MAC control frames (except for pause
1911 * frames) to be passed on for processing. This setting has no
1912 * affect on the operation of the pause frames. This bit effects
1913 * all packets regardless of RX Parser packet sorting logic.
1914 * Turn the PFC off to make sure we are in Xon state before
1917 EMAC_WR(bp
, EMAC_REG_RX_PFC_MODE
, 0);
1918 if (params
->feature_config_flags
& FEATURE_CONFIG_PFC_ENABLED
) {
1919 DP(NETIF_MSG_LINK
, "PFC is enabled\n");
1920 /* Enable PFC again */
1921 EMAC_WR(bp
, EMAC_REG_RX_PFC_MODE
,
1922 EMAC_REG_RX_PFC_MODE_RX_EN
|
1923 EMAC_REG_RX_PFC_MODE_TX_EN
|
1924 EMAC_REG_RX_PFC_MODE_PRIORITIES
);
1926 EMAC_WR(bp
, EMAC_REG_RX_PFC_PARAM
,
1928 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT
) |
1930 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT
)));
1931 val
|= EMAC_RX_MODE_KEEP_MAC_CONTROL
;
1933 EMAC_WR(bp
, EMAC_REG_EMAC_RX_MODE
, val
);
1936 val
= REG_RD(bp
, emac_base
+ EMAC_REG_EMAC_MODE
);
1941 EMAC_WR(bp
, EMAC_REG_EMAC_MODE
, val
);
1944 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 1);
1946 /* Enable emac for jumbo packets */
1947 EMAC_WR(bp
, EMAC_REG_EMAC_RX_MTU_SIZE
,
1948 (EMAC_RX_MTU_SIZE_JUMBO_ENA
|
1949 (ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
)));
1952 REG_WR(bp
, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC
+ port
*4, 0x1);
1954 /* Disable the NIG in/out to the bmac */
1955 REG_WR(bp
, NIG_REG_BMAC0_IN_EN
+ port
*4, 0x0);
1956 REG_WR(bp
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
*4, 0x0);
1957 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0x0);
1959 /* Enable the NIG in/out to the emac */
1960 REG_WR(bp
, NIG_REG_EMAC0_IN_EN
+ port
*4, 0x1);
1962 if ((params
->feature_config_flags
&
1963 FEATURE_CONFIG_PFC_ENABLED
) ||
1964 (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
))
1967 REG_WR(bp
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
*4, val
);
1968 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0x1);
1970 REG_WR(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4, 0x0);
1972 vars
->mac_type
= MAC_TYPE_EMAC
;
1976 static void bnx2x_update_pfc_bmac1(struct link_params
*params
,
1977 struct link_vars
*vars
)
1980 struct bnx2x
*bp
= params
->bp
;
1981 u32 bmac_addr
= params
->port
? NIG_REG_INGRESS_BMAC1_MEM
:
1982 NIG_REG_INGRESS_BMAC0_MEM
;
1985 if ((!(params
->feature_config_flags
&
1986 FEATURE_CONFIG_PFC_ENABLED
)) &&
1987 (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
))
1988 /* Enable BigMAC to react on received Pause packets */
1992 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_RX_CONTROL
, wb_data
, 2);
1996 if (!(params
->feature_config_flags
&
1997 FEATURE_CONFIG_PFC_ENABLED
) &&
1998 (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
))
2002 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_TX_CONTROL
, wb_data
, 2);
2005 static void bnx2x_update_pfc_bmac2(struct link_params
*params
,
2006 struct link_vars
*vars
,
2009 /* Set rx control: Strip CRC and enable BigMAC to relay
2010 * control packets to the system as well
2013 struct bnx2x
*bp
= params
->bp
;
2014 u32 bmac_addr
= params
->port
? NIG_REG_INGRESS_BMAC1_MEM
:
2015 NIG_REG_INGRESS_BMAC0_MEM
;
2018 if ((!(params
->feature_config_flags
&
2019 FEATURE_CONFIG_PFC_ENABLED
)) &&
2020 (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
))
2021 /* Enable BigMAC to react on received Pause packets */
2025 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_RX_CONTROL
, wb_data
, 2);
2030 if (!(params
->feature_config_flags
&
2031 FEATURE_CONFIG_PFC_ENABLED
) &&
2032 (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
))
2036 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_TX_CONTROL
, wb_data
, 2);
2038 if (params
->feature_config_flags
& FEATURE_CONFIG_PFC_ENABLED
) {
2039 DP(NETIF_MSG_LINK
, "PFC is enabled\n");
2040 /* Enable PFC RX & TX & STATS and set 8 COS */
2042 wb_data
[0] |= (1<<0); /* RX */
2043 wb_data
[0] |= (1<<1); /* TX */
2044 wb_data
[0] |= (1<<2); /* Force initial Xon */
2045 wb_data
[0] |= (1<<3); /* 8 cos */
2046 wb_data
[0] |= (1<<5); /* STATS */
2048 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_PFC_CONTROL
,
2050 /* Clear the force Xon */
2051 wb_data
[0] &= ~(1<<2);
2053 DP(NETIF_MSG_LINK
, "PFC is disabled\n");
2054 /* Disable PFC RX & TX & STATS and set 8 COS */
2059 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_PFC_CONTROL
, wb_data
, 2);
2061 /* Set Time (based unit is 512 bit time) between automatic
2062 * re-sending of PP packets amd enable automatic re-send of
2063 * Per-Priroity Packet as long as pp_gen is asserted and
2064 * pp_disable is low.
2067 if (params
->feature_config_flags
& FEATURE_CONFIG_PFC_ENABLED
)
2068 val
|= (1<<16); /* enable automatic re-send */
2072 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_TX_PAUSE_CONTROL
,
2076 val
= 0x3; /* Enable RX and TX */
2078 val
|= 0x4; /* Local loopback */
2079 DP(NETIF_MSG_LINK
, "enable bmac loopback\n");
2081 /* When PFC enabled, Pass pause frames towards the NIG. */
2082 if (params
->feature_config_flags
& FEATURE_CONFIG_PFC_ENABLED
)
2083 val
|= ((1<<6)|(1<<5));
2087 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_BMAC_CONTROL
, wb_data
, 2);
2090 /* PFC BRB internal port configuration params */
2091 struct bnx2x_pfc_brb_threshold_val
{
2098 struct bnx2x_pfc_brb_e3b0_val
{
2099 u32 per_class_guaranty_mode
;
2100 u32 lb_guarantied_hyst
;
2101 u32 full_lb_xoff_th
;
2102 u32 full_lb_xon_threshold
;
2104 u32 mac_0_class_t_guarantied
;
2105 u32 mac_0_class_t_guarantied_hyst
;
2106 u32 mac_1_class_t_guarantied
;
2107 u32 mac_1_class_t_guarantied_hyst
;
2110 struct bnx2x_pfc_brb_th_val
{
2111 struct bnx2x_pfc_brb_threshold_val pauseable_th
;
2112 struct bnx2x_pfc_brb_threshold_val non_pauseable_th
;
2113 struct bnx2x_pfc_brb_threshold_val default_class0
;
2114 struct bnx2x_pfc_brb_threshold_val default_class1
;
2117 static int bnx2x_pfc_brb_get_config_params(
2118 struct link_params
*params
,
2119 struct bnx2x_pfc_brb_th_val
*config_val
)
2121 struct bnx2x
*bp
= params
->bp
;
2122 DP(NETIF_MSG_LINK
, "Setting PFC BRB configuration\n");
2124 config_val
->default_class1
.pause_xoff
= 0;
2125 config_val
->default_class1
.pause_xon
= 0;
2126 config_val
->default_class1
.full_xoff
= 0;
2127 config_val
->default_class1
.full_xon
= 0;
2129 if (CHIP_IS_E2(bp
)) {
2130 /* Class0 defaults */
2131 config_val
->default_class0
.pause_xoff
=
2132 DEFAULT0_E2_BRB_MAC_PAUSE_XOFF_THR
;
2133 config_val
->default_class0
.pause_xon
=
2134 DEFAULT0_E2_BRB_MAC_PAUSE_XON_THR
;
2135 config_val
->default_class0
.full_xoff
=
2136 DEFAULT0_E2_BRB_MAC_FULL_XOFF_THR
;
2137 config_val
->default_class0
.full_xon
=
2138 DEFAULT0_E2_BRB_MAC_FULL_XON_THR
;
2140 config_val
->pauseable_th
.pause_xoff
=
2141 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_PAUSE
;
2142 config_val
->pauseable_th
.pause_xon
=
2143 PFC_E2_BRB_MAC_PAUSE_XON_THR_PAUSE
;
2144 config_val
->pauseable_th
.full_xoff
=
2145 PFC_E2_BRB_MAC_FULL_XOFF_THR_PAUSE
;
2146 config_val
->pauseable_th
.full_xon
=
2147 PFC_E2_BRB_MAC_FULL_XON_THR_PAUSE
;
2149 config_val
->non_pauseable_th
.pause_xoff
=
2150 PFC_E2_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE
;
2151 config_val
->non_pauseable_th
.pause_xon
=
2152 PFC_E2_BRB_MAC_PAUSE_XON_THR_NON_PAUSE
;
2153 config_val
->non_pauseable_th
.full_xoff
=
2154 PFC_E2_BRB_MAC_FULL_XOFF_THR_NON_PAUSE
;
2155 config_val
->non_pauseable_th
.full_xon
=
2156 PFC_E2_BRB_MAC_FULL_XON_THR_NON_PAUSE
;
2157 } else if (CHIP_IS_E3A0(bp
)) {
2158 /* Class0 defaults */
2159 config_val
->default_class0
.pause_xoff
=
2160 DEFAULT0_E3A0_BRB_MAC_PAUSE_XOFF_THR
;
2161 config_val
->default_class0
.pause_xon
=
2162 DEFAULT0_E3A0_BRB_MAC_PAUSE_XON_THR
;
2163 config_val
->default_class0
.full_xoff
=
2164 DEFAULT0_E3A0_BRB_MAC_FULL_XOFF_THR
;
2165 config_val
->default_class0
.full_xon
=
2166 DEFAULT0_E3A0_BRB_MAC_FULL_XON_THR
;
2168 config_val
->pauseable_th
.pause_xoff
=
2169 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_PAUSE
;
2170 config_val
->pauseable_th
.pause_xon
=
2171 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_PAUSE
;
2172 config_val
->pauseable_th
.full_xoff
=
2173 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_PAUSE
;
2174 config_val
->pauseable_th
.full_xon
=
2175 PFC_E3A0_BRB_MAC_FULL_XON_THR_PAUSE
;
2177 config_val
->non_pauseable_th
.pause_xoff
=
2178 PFC_E3A0_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE
;
2179 config_val
->non_pauseable_th
.pause_xon
=
2180 PFC_E3A0_BRB_MAC_PAUSE_XON_THR_NON_PAUSE
;
2181 config_val
->non_pauseable_th
.full_xoff
=
2182 PFC_E3A0_BRB_MAC_FULL_XOFF_THR_NON_PAUSE
;
2183 config_val
->non_pauseable_th
.full_xon
=
2184 PFC_E3A0_BRB_MAC_FULL_XON_THR_NON_PAUSE
;
2185 } else if (CHIP_IS_E3B0(bp
)) {
2186 /* Class0 defaults */
2187 config_val
->default_class0
.pause_xoff
=
2188 DEFAULT0_E3B0_BRB_MAC_PAUSE_XOFF_THR
;
2189 config_val
->default_class0
.pause_xon
=
2190 DEFAULT0_E3B0_BRB_MAC_PAUSE_XON_THR
;
2191 config_val
->default_class0
.full_xoff
=
2192 DEFAULT0_E3B0_BRB_MAC_FULL_XOFF_THR
;
2193 config_val
->default_class0
.full_xon
=
2194 DEFAULT0_E3B0_BRB_MAC_FULL_XON_THR
;
2196 if (params
->phy
[INT_PHY
].flags
&
2197 FLAGS_4_PORT_MODE
) {
2198 config_val
->pauseable_th
.pause_xoff
=
2199 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_PAUSE
;
2200 config_val
->pauseable_th
.pause_xon
=
2201 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_PAUSE
;
2202 config_val
->pauseable_th
.full_xoff
=
2203 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_PAUSE
;
2204 config_val
->pauseable_th
.full_xon
=
2205 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_PAUSE
;
2207 config_val
->non_pauseable_th
.pause_xoff
=
2208 PFC_E3B0_4P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE
;
2209 config_val
->non_pauseable_th
.pause_xon
=
2210 PFC_E3B0_4P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE
;
2211 config_val
->non_pauseable_th
.full_xoff
=
2212 PFC_E3B0_4P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE
;
2213 config_val
->non_pauseable_th
.full_xon
=
2214 PFC_E3B0_4P_BRB_MAC_FULL_XON_THR_NON_PAUSE
;
2216 config_val
->pauseable_th
.pause_xoff
=
2217 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_PAUSE
;
2218 config_val
->pauseable_th
.pause_xon
=
2219 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_PAUSE
;
2220 config_val
->pauseable_th
.full_xoff
=
2221 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_PAUSE
;
2222 config_val
->pauseable_th
.full_xon
=
2223 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_PAUSE
;
2225 config_val
->non_pauseable_th
.pause_xoff
=
2226 PFC_E3B0_2P_BRB_MAC_PAUSE_XOFF_THR_NON_PAUSE
;
2227 config_val
->non_pauseable_th
.pause_xon
=
2228 PFC_E3B0_2P_BRB_MAC_PAUSE_XON_THR_NON_PAUSE
;
2229 config_val
->non_pauseable_th
.full_xoff
=
2230 PFC_E3B0_2P_BRB_MAC_FULL_XOFF_THR_NON_PAUSE
;
2231 config_val
->non_pauseable_th
.full_xon
=
2232 PFC_E3B0_2P_BRB_MAC_FULL_XON_THR_NON_PAUSE
;
2240 static void bnx2x_pfc_brb_get_e3b0_config_params(
2241 struct link_params
*params
,
2242 struct bnx2x_pfc_brb_e3b0_val
2244 struct bnx2x_nig_brb_pfc_port_params
*pfc_params
,
2245 const u8 pfc_enabled
)
2247 if (pfc_enabled
&& pfc_params
) {
2248 e3b0_val
->per_class_guaranty_mode
= 1;
2249 e3b0_val
->lb_guarantied_hyst
= 80;
2251 if (params
->phy
[INT_PHY
].flags
&
2252 FLAGS_4_PORT_MODE
) {
2253 e3b0_val
->full_lb_xoff_th
=
2254 PFC_E3B0_4P_BRB_FULL_LB_XOFF_THR
;
2255 e3b0_val
->full_lb_xon_threshold
=
2256 PFC_E3B0_4P_BRB_FULL_LB_XON_THR
;
2257 e3b0_val
->lb_guarantied
=
2258 PFC_E3B0_4P_LB_GUART
;
2259 e3b0_val
->mac_0_class_t_guarantied
=
2260 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART
;
2261 e3b0_val
->mac_0_class_t_guarantied_hyst
=
2262 PFC_E3B0_4P_BRB_MAC_0_CLASS_T_GUART_HYST
;
2263 e3b0_val
->mac_1_class_t_guarantied
=
2264 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART
;
2265 e3b0_val
->mac_1_class_t_guarantied_hyst
=
2266 PFC_E3B0_4P_BRB_MAC_1_CLASS_T_GUART_HYST
;
2268 e3b0_val
->full_lb_xoff_th
=
2269 PFC_E3B0_2P_BRB_FULL_LB_XOFF_THR
;
2270 e3b0_val
->full_lb_xon_threshold
=
2271 PFC_E3B0_2P_BRB_FULL_LB_XON_THR
;
2272 e3b0_val
->mac_0_class_t_guarantied_hyst
=
2273 PFC_E3B0_2P_BRB_MAC_0_CLASS_T_GUART_HYST
;
2274 e3b0_val
->mac_1_class_t_guarantied
=
2275 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART
;
2276 e3b0_val
->mac_1_class_t_guarantied_hyst
=
2277 PFC_E3B0_2P_BRB_MAC_1_CLASS_T_GUART_HYST
;
2279 if (pfc_params
->cos0_pauseable
!=
2280 pfc_params
->cos1_pauseable
) {
2281 /* Nonpauseable= Lossy + pauseable = Lossless*/
2282 e3b0_val
->lb_guarantied
=
2283 PFC_E3B0_2P_MIX_PAUSE_LB_GUART
;
2284 e3b0_val
->mac_0_class_t_guarantied
=
2285 PFC_E3B0_2P_MIX_PAUSE_MAC_0_CLASS_T_GUART
;
2286 } else if (pfc_params
->cos0_pauseable
) {
2287 /* Lossless +Lossless*/
2288 e3b0_val
->lb_guarantied
=
2289 PFC_E3B0_2P_PAUSE_LB_GUART
;
2290 e3b0_val
->mac_0_class_t_guarantied
=
2291 PFC_E3B0_2P_PAUSE_MAC_0_CLASS_T_GUART
;
2294 e3b0_val
->lb_guarantied
=
2295 PFC_E3B0_2P_NON_PAUSE_LB_GUART
;
2296 e3b0_val
->mac_0_class_t_guarantied
=
2297 PFC_E3B0_2P_NON_PAUSE_MAC_0_CLASS_T_GUART
;
2301 e3b0_val
->per_class_guaranty_mode
= 0;
2302 e3b0_val
->lb_guarantied_hyst
= 0;
2303 e3b0_val
->full_lb_xoff_th
=
2304 DEFAULT_E3B0_BRB_FULL_LB_XOFF_THR
;
2305 e3b0_val
->full_lb_xon_threshold
=
2306 DEFAULT_E3B0_BRB_FULL_LB_XON_THR
;
2307 e3b0_val
->lb_guarantied
=
2308 DEFAULT_E3B0_LB_GUART
;
2309 e3b0_val
->mac_0_class_t_guarantied
=
2310 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART
;
2311 e3b0_val
->mac_0_class_t_guarantied_hyst
=
2312 DEFAULT_E3B0_BRB_MAC_0_CLASS_T_GUART_HYST
;
2313 e3b0_val
->mac_1_class_t_guarantied
=
2314 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART
;
2315 e3b0_val
->mac_1_class_t_guarantied_hyst
=
2316 DEFAULT_E3B0_BRB_MAC_1_CLASS_T_GUART_HYST
;
2319 static int bnx2x_update_pfc_brb(struct link_params
*params
,
2320 struct link_vars
*vars
,
2321 struct bnx2x_nig_brb_pfc_port_params
2324 struct bnx2x
*bp
= params
->bp
;
2325 struct bnx2x_pfc_brb_th_val config_val
= { {0} };
2326 struct bnx2x_pfc_brb_threshold_val
*reg_th_config
=
2327 &config_val
.pauseable_th
;
2328 struct bnx2x_pfc_brb_e3b0_val e3b0_val
= {0};
2329 const int set_pfc
= params
->feature_config_flags
&
2330 FEATURE_CONFIG_PFC_ENABLED
;
2331 const u8 pfc_enabled
= (set_pfc
&& pfc_params
);
2332 int bnx2x_status
= 0;
2333 u8 port
= params
->port
;
2335 /* default - pause configuration */
2336 reg_th_config
= &config_val
.pauseable_th
;
2337 bnx2x_status
= bnx2x_pfc_brb_get_config_params(params
, &config_val
);
2339 return bnx2x_status
;
2343 if (pfc_params
->cos0_pauseable
)
2344 reg_th_config
= &config_val
.pauseable_th
;
2346 reg_th_config
= &config_val
.non_pauseable_th
;
2348 reg_th_config
= &config_val
.default_class0
;
2349 /* The number of free blocks below which the pause signal to class 0
2350 * of MAC #n is asserted. n=0,1
2352 REG_WR(bp
, (port
) ? BRB1_REG_PAUSE_0_XOFF_THRESHOLD_1
:
2353 BRB1_REG_PAUSE_0_XOFF_THRESHOLD_0
,
2354 reg_th_config
->pause_xoff
);
2355 /* The number of free blocks above which the pause signal to class 0
2356 * of MAC #n is de-asserted. n=0,1
2358 REG_WR(bp
, (port
) ? BRB1_REG_PAUSE_0_XON_THRESHOLD_1
:
2359 BRB1_REG_PAUSE_0_XON_THRESHOLD_0
, reg_th_config
->pause_xon
);
2360 /* The number of free blocks below which the full signal to class 0
2361 * of MAC #n is asserted. n=0,1
2363 REG_WR(bp
, (port
) ? BRB1_REG_FULL_0_XOFF_THRESHOLD_1
:
2364 BRB1_REG_FULL_0_XOFF_THRESHOLD_0
, reg_th_config
->full_xoff
);
2365 /* The number of free blocks above which the full signal to class 0
2366 * of MAC #n is de-asserted. n=0,1
2368 REG_WR(bp
, (port
) ? BRB1_REG_FULL_0_XON_THRESHOLD_1
:
2369 BRB1_REG_FULL_0_XON_THRESHOLD_0
, reg_th_config
->full_xon
);
2373 if (pfc_params
->cos1_pauseable
)
2374 reg_th_config
= &config_val
.pauseable_th
;
2376 reg_th_config
= &config_val
.non_pauseable_th
;
2378 reg_th_config
= &config_val
.default_class1
;
2379 /* The number of free blocks below which the pause signal to
2380 * class 1 of MAC #n is asserted. n=0,1
2382 REG_WR(bp
, (port
) ? BRB1_REG_PAUSE_1_XOFF_THRESHOLD_1
:
2383 BRB1_REG_PAUSE_1_XOFF_THRESHOLD_0
,
2384 reg_th_config
->pause_xoff
);
2386 /* The number of free blocks above which the pause signal to
2387 * class 1 of MAC #n is de-asserted. n=0,1
2389 REG_WR(bp
, (port
) ? BRB1_REG_PAUSE_1_XON_THRESHOLD_1
:
2390 BRB1_REG_PAUSE_1_XON_THRESHOLD_0
,
2391 reg_th_config
->pause_xon
);
2392 /* The number of free blocks below which the full signal to
2393 * class 1 of MAC #n is asserted. n=0,1
2395 REG_WR(bp
, (port
) ? BRB1_REG_FULL_1_XOFF_THRESHOLD_1
:
2396 BRB1_REG_FULL_1_XOFF_THRESHOLD_0
,
2397 reg_th_config
->full_xoff
);
2398 /* The number of free blocks above which the full signal to
2399 * class 1 of MAC #n is de-asserted. n=0,1
2401 REG_WR(bp
, (port
) ? BRB1_REG_FULL_1_XON_THRESHOLD_1
:
2402 BRB1_REG_FULL_1_XON_THRESHOLD_0
,
2403 reg_th_config
->full_xon
);
2405 if (CHIP_IS_E3B0(bp
)) {
2406 bnx2x_pfc_brb_get_e3b0_config_params(
2412 REG_WR(bp
, BRB1_REG_PER_CLASS_GUARANTY_MODE
,
2413 e3b0_val
.per_class_guaranty_mode
);
2415 /* The hysteresis on the guarantied buffer space for the Lb
2416 * port before signaling XON.
2418 REG_WR(bp
, BRB1_REG_LB_GUARANTIED_HYST
,
2419 e3b0_val
.lb_guarantied_hyst
);
2421 /* The number of free blocks below which the full signal to the
2422 * LB port is asserted.
2424 REG_WR(bp
, BRB1_REG_FULL_LB_XOFF_THRESHOLD
,
2425 e3b0_val
.full_lb_xoff_th
);
2426 /* The number of free blocks above which the full signal to the
2427 * LB port is de-asserted.
2429 REG_WR(bp
, BRB1_REG_FULL_LB_XON_THRESHOLD
,
2430 e3b0_val
.full_lb_xon_threshold
);
2431 /* The number of blocks guarantied for the MAC #n port. n=0,1
2434 /* The number of blocks guarantied for the LB port. */
2435 REG_WR(bp
, BRB1_REG_LB_GUARANTIED
,
2436 e3b0_val
.lb_guarantied
);
2438 /* The number of blocks guarantied for the MAC #n port. */
2439 REG_WR(bp
, BRB1_REG_MAC_GUARANTIED_0
,
2440 2 * e3b0_val
.mac_0_class_t_guarantied
);
2441 REG_WR(bp
, BRB1_REG_MAC_GUARANTIED_1
,
2442 2 * e3b0_val
.mac_1_class_t_guarantied
);
2443 /* The number of blocks guarantied for class #t in MAC0. t=0,1
2445 REG_WR(bp
, BRB1_REG_MAC_0_CLASS_0_GUARANTIED
,
2446 e3b0_val
.mac_0_class_t_guarantied
);
2447 REG_WR(bp
, BRB1_REG_MAC_0_CLASS_1_GUARANTIED
,
2448 e3b0_val
.mac_0_class_t_guarantied
);
2449 /* The hysteresis on the guarantied buffer space for class in
2452 REG_WR(bp
, BRB1_REG_MAC_0_CLASS_0_GUARANTIED_HYST
,
2453 e3b0_val
.mac_0_class_t_guarantied_hyst
);
2454 REG_WR(bp
, BRB1_REG_MAC_0_CLASS_1_GUARANTIED_HYST
,
2455 e3b0_val
.mac_0_class_t_guarantied_hyst
);
2457 /* The number of blocks guarantied for class #t in MAC1.t=0,1
2459 REG_WR(bp
, BRB1_REG_MAC_1_CLASS_0_GUARANTIED
,
2460 e3b0_val
.mac_1_class_t_guarantied
);
2461 REG_WR(bp
, BRB1_REG_MAC_1_CLASS_1_GUARANTIED
,
2462 e3b0_val
.mac_1_class_t_guarantied
);
2463 /* The hysteresis on the guarantied buffer space for class #t
2466 REG_WR(bp
, BRB1_REG_MAC_1_CLASS_0_GUARANTIED_HYST
,
2467 e3b0_val
.mac_1_class_t_guarantied_hyst
);
2468 REG_WR(bp
, BRB1_REG_MAC_1_CLASS_1_GUARANTIED_HYST
,
2469 e3b0_val
.mac_1_class_t_guarantied_hyst
);
2472 return bnx2x_status
;
2475 /******************************************************************************
2477 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2478 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2479 ******************************************************************************/
2480 static int bnx2x_pfc_nig_rx_priority_mask(struct bnx2x
*bp
,
2482 u32 priority_mask
, u8 port
)
2484 u32 nig_reg_rx_priority_mask_add
= 0;
2486 switch (cos_entry
) {
2488 nig_reg_rx_priority_mask_add
= (port
) ?
2489 NIG_REG_P1_RX_COS0_PRIORITY_MASK
:
2490 NIG_REG_P0_RX_COS0_PRIORITY_MASK
;
2493 nig_reg_rx_priority_mask_add
= (port
) ?
2494 NIG_REG_P1_RX_COS1_PRIORITY_MASK
:
2495 NIG_REG_P0_RX_COS1_PRIORITY_MASK
;
2498 nig_reg_rx_priority_mask_add
= (port
) ?
2499 NIG_REG_P1_RX_COS2_PRIORITY_MASK
:
2500 NIG_REG_P0_RX_COS2_PRIORITY_MASK
;
2505 nig_reg_rx_priority_mask_add
= NIG_REG_P0_RX_COS3_PRIORITY_MASK
;
2510 nig_reg_rx_priority_mask_add
= NIG_REG_P0_RX_COS4_PRIORITY_MASK
;
2515 nig_reg_rx_priority_mask_add
= NIG_REG_P0_RX_COS5_PRIORITY_MASK
;
2519 REG_WR(bp
, nig_reg_rx_priority_mask_add
, priority_mask
);
2523 static void bnx2x_update_mng(struct link_params
*params
, u32 link_status
)
2525 struct bnx2x
*bp
= params
->bp
;
2527 REG_WR(bp
, params
->shmem_base
+
2528 offsetof(struct shmem_region
,
2529 port_mb
[params
->port
].link_status
), link_status
);
2532 static void bnx2x_update_mng_eee(struct link_params
*params
, u32 eee_status
)
2534 struct bnx2x
*bp
= params
->bp
;
2536 if (bnx2x_eee_has_cap(params
))
2537 REG_WR(bp
, params
->shmem2_base
+
2538 offsetof(struct shmem2_region
,
2539 eee_status
[params
->port
]), eee_status
);
2542 static void bnx2x_update_pfc_nig(struct link_params
*params
,
2543 struct link_vars
*vars
,
2544 struct bnx2x_nig_brb_pfc_port_params
*nig_params
)
2546 u32 xcm_mask
= 0, ppp_enable
= 0, pause_enable
= 0, llfc_out_en
= 0;
2547 u32 llfc_enable
= 0, xcm_out_en
= 0, hwpfc_enable
= 0;
2548 u32 pkt_priority_to_cos
= 0;
2549 struct bnx2x
*bp
= params
->bp
;
2550 u8 port
= params
->port
;
2552 int set_pfc
= params
->feature_config_flags
&
2553 FEATURE_CONFIG_PFC_ENABLED
;
2554 DP(NETIF_MSG_LINK
, "updating pfc nig parameters\n");
2556 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2557 * MAC control frames (that are not pause packets)
2558 * will be forwarded to the XCM.
2560 xcm_mask
= REG_RD(bp
, port
? NIG_REG_LLH1_XCM_MASK
:
2561 NIG_REG_LLH0_XCM_MASK
);
2562 /* NIG params will override non PFC params, since it's possible to
2563 * do transition from PFC to SAFC
2573 xcm_mask
&= ~(port
? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN
:
2574 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN
);
2579 llfc_out_en
= nig_params
->llfc_out_en
;
2580 llfc_enable
= nig_params
->llfc_enable
;
2581 pause_enable
= nig_params
->pause_enable
;
2582 } else /* Default non PFC mode - PAUSE */
2585 xcm_mask
|= (port
? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN
:
2586 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN
);
2591 REG_WR(bp
, port
? NIG_REG_BRB1_PAUSE_IN_EN
:
2592 NIG_REG_BRB0_PAUSE_IN_EN
, pause_enable
);
2593 REG_WR(bp
, port
? NIG_REG_LLFC_OUT_EN_1
:
2594 NIG_REG_LLFC_OUT_EN_0
, llfc_out_en
);
2595 REG_WR(bp
, port
? NIG_REG_LLFC_ENABLE_1
:
2596 NIG_REG_LLFC_ENABLE_0
, llfc_enable
);
2597 REG_WR(bp
, port
? NIG_REG_PAUSE_ENABLE_1
:
2598 NIG_REG_PAUSE_ENABLE_0
, pause_enable
);
2600 REG_WR(bp
, port
? NIG_REG_PPP_ENABLE_1
:
2601 NIG_REG_PPP_ENABLE_0
, ppp_enable
);
2603 REG_WR(bp
, port
? NIG_REG_LLH1_XCM_MASK
:
2604 NIG_REG_LLH0_XCM_MASK
, xcm_mask
);
2606 REG_WR(bp
, port
? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1
:
2607 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0
, 0x7);
2609 /* Output enable for RX_XCM # IF */
2610 REG_WR(bp
, port
? NIG_REG_XCM1_OUT_EN
:
2611 NIG_REG_XCM0_OUT_EN
, xcm_out_en
);
2613 /* HW PFC TX enable */
2614 REG_WR(bp
, port
? NIG_REG_P1_HWPFC_ENABLE
:
2615 NIG_REG_P0_HWPFC_ENABLE
, hwpfc_enable
);
2619 pkt_priority_to_cos
= nig_params
->pkt_priority_to_cos
;
2621 for (i
= 0; i
< nig_params
->num_of_rx_cos_priority_mask
; i
++)
2622 bnx2x_pfc_nig_rx_priority_mask(bp
, i
,
2623 nig_params
->rx_cos_priority_mask
[i
], port
);
2625 REG_WR(bp
, port
? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1
:
2626 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0
,
2627 nig_params
->llfc_high_priority_classes
);
2629 REG_WR(bp
, port
? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1
:
2630 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0
,
2631 nig_params
->llfc_low_priority_classes
);
2633 REG_WR(bp
, port
? NIG_REG_P1_PKT_PRIORITY_TO_COS
:
2634 NIG_REG_P0_PKT_PRIORITY_TO_COS
,
2635 pkt_priority_to_cos
);
2638 int bnx2x_update_pfc(struct link_params
*params
,
2639 struct link_vars
*vars
,
2640 struct bnx2x_nig_brb_pfc_port_params
*pfc_params
)
2642 /* The PFC and pause are orthogonal to one another, meaning when
2643 * PFC is enabled, the pause are disabled, and when PFC is
2644 * disabled, pause are set according to the pause result.
2647 struct bnx2x
*bp
= params
->bp
;
2648 int bnx2x_status
= 0;
2649 u8 bmac_loopback
= (params
->loopback_mode
== LOOPBACK_BMAC
);
2651 if (params
->feature_config_flags
& FEATURE_CONFIG_PFC_ENABLED
)
2652 vars
->link_status
|= LINK_STATUS_PFC_ENABLED
;
2654 vars
->link_status
&= ~LINK_STATUS_PFC_ENABLED
;
2656 bnx2x_update_mng(params
, vars
->link_status
);
2658 /* Update NIG params */
2659 bnx2x_update_pfc_nig(params
, vars
, pfc_params
);
2661 /* Update BRB params */
2662 bnx2x_status
= bnx2x_update_pfc_brb(params
, vars
, pfc_params
);
2664 return bnx2x_status
;
2667 return bnx2x_status
;
2669 DP(NETIF_MSG_LINK
, "About to update PFC in BMAC\n");
2671 if (CHIP_IS_E3(bp
)) {
2672 if (vars
->mac_type
== MAC_TYPE_XMAC
)
2673 bnx2x_update_pfc_xmac(params
, vars
, 0);
2675 val
= REG_RD(bp
, MISC_REG_RESET_REG_2
);
2677 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< params
->port
))
2679 DP(NETIF_MSG_LINK
, "About to update PFC in EMAC\n");
2680 bnx2x_emac_enable(params
, vars
, 0);
2681 return bnx2x_status
;
2684 bnx2x_update_pfc_bmac2(params
, vars
, bmac_loopback
);
2686 bnx2x_update_pfc_bmac1(params
, vars
);
2689 if ((params
->feature_config_flags
&
2690 FEATURE_CONFIG_PFC_ENABLED
) ||
2691 (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
))
2693 REG_WR(bp
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ params
->port
*4, val
);
2695 return bnx2x_status
;
2699 static int bnx2x_bmac1_enable(struct link_params
*params
,
2700 struct link_vars
*vars
,
2703 struct bnx2x
*bp
= params
->bp
;
2704 u8 port
= params
->port
;
2705 u32 bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
2706 NIG_REG_INGRESS_BMAC0_MEM
;
2710 DP(NETIF_MSG_LINK
, "Enabling BigMAC1\n");
2715 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_BMAC_XGXS_CONTROL
,
2719 wb_data
[0] = ((params
->mac_addr
[2] << 24) |
2720 (params
->mac_addr
[3] << 16) |
2721 (params
->mac_addr
[4] << 8) |
2722 params
->mac_addr
[5]);
2723 wb_data
[1] = ((params
->mac_addr
[0] << 8) |
2724 params
->mac_addr
[1]);
2725 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_TX_SOURCE_ADDR
, wb_data
, 2);
2731 DP(NETIF_MSG_LINK
, "enable bmac loopback\n");
2735 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_BMAC_CONTROL
, wb_data
, 2);
2738 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
2740 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_RX_MAX_SIZE
, wb_data
, 2);
2742 bnx2x_update_pfc_bmac1(params
, vars
);
2745 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
2747 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_TX_MAX_SIZE
, wb_data
, 2);
2749 /* Set cnt max size */
2750 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
2752 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_CNT_MAX_SIZE
, wb_data
, 2);
2754 /* Configure SAFC */
2755 wb_data
[0] = 0x1000200;
2757 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC_REGISTER_RX_LLFC_MSG_FLDS
,
2763 static int bnx2x_bmac2_enable(struct link_params
*params
,
2764 struct link_vars
*vars
,
2767 struct bnx2x
*bp
= params
->bp
;
2768 u8 port
= params
->port
;
2769 u32 bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
2770 NIG_REG_INGRESS_BMAC0_MEM
;
2773 DP(NETIF_MSG_LINK
, "Enabling BigMAC2\n");
2777 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_BMAC_CONTROL
, wb_data
, 2);
2780 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
2783 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_BMAC_XGXS_CONTROL
,
2789 wb_data
[0] = ((params
->mac_addr
[2] << 24) |
2790 (params
->mac_addr
[3] << 16) |
2791 (params
->mac_addr
[4] << 8) |
2792 params
->mac_addr
[5]);
2793 wb_data
[1] = ((params
->mac_addr
[0] << 8) |
2794 params
->mac_addr
[1]);
2795 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_TX_SOURCE_ADDR
,
2800 /* Configure SAFC */
2801 wb_data
[0] = 0x1000200;
2803 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS
,
2808 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
2810 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_RX_MAX_SIZE
, wb_data
, 2);
2814 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
;
2816 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_TX_MAX_SIZE
, wb_data
, 2);
2818 /* Set cnt max size */
2819 wb_data
[0] = ETH_MAX_JUMBO_PACKET_SIZE
+ ETH_OVREHEAD
- 2;
2821 REG_WR_DMAE(bp
, bmac_addr
+ BIGMAC2_REGISTER_CNT_MAX_SIZE
, wb_data
, 2);
2823 bnx2x_update_pfc_bmac2(params
, vars
, is_lb
);
2828 static int bnx2x_bmac_enable(struct link_params
*params
,
2829 struct link_vars
*vars
,
2833 u8 port
= params
->port
;
2834 struct bnx2x
*bp
= params
->bp
;
2836 /* Reset and unreset the BigMac */
2837 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
2838 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
2839 usleep_range(1000, 2000);
2841 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
2842 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
2844 /* Enable access for bmac registers */
2845 REG_WR(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4, 0x1);
2847 /* Enable BMAC according to BMAC type*/
2849 rc
= bnx2x_bmac2_enable(params
, vars
, is_lb
);
2851 rc
= bnx2x_bmac1_enable(params
, vars
, is_lb
);
2852 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 0x1);
2853 REG_WR(bp
, NIG_REG_XGXS_LANE_SEL_P0
+ port
*4, 0x0);
2854 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ port
*4, 0x0);
2856 if ((params
->feature_config_flags
&
2857 FEATURE_CONFIG_PFC_ENABLED
) ||
2858 (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
))
2860 REG_WR(bp
, NIG_REG_BMAC0_PAUSE_OUT_EN
+ port
*4, val
);
2861 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0x0);
2862 REG_WR(bp
, NIG_REG_EMAC0_IN_EN
+ port
*4, 0x0);
2863 REG_WR(bp
, NIG_REG_EMAC0_PAUSE_OUT_EN
+ port
*4, 0x0);
2864 REG_WR(bp
, NIG_REG_BMAC0_IN_EN
+ port
*4, 0x1);
2865 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0x1);
2867 vars
->mac_type
= MAC_TYPE_BMAC
;
2871 static void bnx2x_bmac_rx_disable(struct bnx2x
*bp
, u8 port
)
2873 u32 bmac_addr
= port
? NIG_REG_INGRESS_BMAC1_MEM
:
2874 NIG_REG_INGRESS_BMAC0_MEM
;
2876 u32 nig_bmac_enable
= REG_RD(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
*4);
2878 /* Only if the bmac is out of reset */
2879 if (REG_RD(bp
, MISC_REG_RESET_REG_2
) &
2880 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
) &&
2883 if (CHIP_IS_E2(bp
)) {
2884 /* Clear Rx Enable bit in BMAC_CONTROL register */
2885 REG_RD_DMAE(bp
, bmac_addr
+
2886 BIGMAC2_REGISTER_BMAC_CONTROL
,
2888 wb_data
[0] &= ~BMAC_CONTROL_RX_ENABLE
;
2889 REG_WR_DMAE(bp
, bmac_addr
+
2890 BIGMAC2_REGISTER_BMAC_CONTROL
,
2893 /* Clear Rx Enable bit in BMAC_CONTROL register */
2894 REG_RD_DMAE(bp
, bmac_addr
+
2895 BIGMAC_REGISTER_BMAC_CONTROL
,
2897 wb_data
[0] &= ~BMAC_CONTROL_RX_ENABLE
;
2898 REG_WR_DMAE(bp
, bmac_addr
+
2899 BIGMAC_REGISTER_BMAC_CONTROL
,
2902 usleep_range(1000, 2000);
2906 static int bnx2x_pbf_update(struct link_params
*params
, u32 flow_ctrl
,
2909 struct bnx2x
*bp
= params
->bp
;
2910 u8 port
= params
->port
;
2915 REG_WR(bp
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
*4, 0x1);
2917 /* Wait for init credit */
2918 init_crd
= REG_RD(bp
, PBF_REG_P0_INIT_CRD
+ port
*4);
2919 crd
= REG_RD(bp
, PBF_REG_P0_CREDIT
+ port
*8);
2920 DP(NETIF_MSG_LINK
, "init_crd 0x%x crd 0x%x\n", init_crd
, crd
);
2922 while ((init_crd
!= crd
) && count
) {
2923 usleep_range(5000, 10000);
2924 crd
= REG_RD(bp
, PBF_REG_P0_CREDIT
+ port
*8);
2927 crd
= REG_RD(bp
, PBF_REG_P0_CREDIT
+ port
*8);
2928 if (init_crd
!= crd
) {
2929 DP(NETIF_MSG_LINK
, "BUG! init_crd 0x%x != crd 0x%x\n",
2934 if (flow_ctrl
& BNX2X_FLOW_CTRL_RX
||
2935 line_speed
== SPEED_10
||
2936 line_speed
== SPEED_100
||
2937 line_speed
== SPEED_1000
||
2938 line_speed
== SPEED_2500
) {
2939 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 1);
2940 /* Update threshold */
2941 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, 0);
2942 /* Update init credit */
2943 init_crd
= 778; /* (800-18-4) */
2946 u32 thresh
= (ETH_MAX_JUMBO_PACKET_SIZE
+
2948 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
2949 /* Update threshold */
2950 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, thresh
);
2951 /* Update init credit */
2952 switch (line_speed
) {
2954 init_crd
= thresh
+ 553 - 22;
2957 DP(NETIF_MSG_LINK
, "Invalid line_speed 0x%x\n",
2962 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, init_crd
);
2963 DP(NETIF_MSG_LINK
, "PBF updated to speed %d credit %d\n",
2964 line_speed
, init_crd
);
2966 /* Probe the credit changes */
2967 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0x1);
2968 usleep_range(5000, 10000);
2969 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0x0);
2972 REG_WR(bp
, PBF_REG_DISABLE_NEW_TASK_PROC_P0
+ port
*4, 0x0);
2977 * bnx2x_get_emac_base - retrive emac base address
2979 * @bp: driver handle
2980 * @mdc_mdio_access: access type
2983 * This function selects the MDC/MDIO access (through emac0 or
2984 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
2985 * phy has a default access mode, which could also be overridden
2986 * by nvram configuration. This parameter, whether this is the
2987 * default phy configuration, or the nvram overrun
2988 * configuration, is passed here as mdc_mdio_access and selects
2989 * the emac_base for the CL45 read/writes operations
2991 static u32
bnx2x_get_emac_base(struct bnx2x
*bp
,
2992 u32 mdc_mdio_access
, u8 port
)
2995 switch (mdc_mdio_access
) {
2996 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE
:
2998 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0
:
2999 if (REG_RD(bp
, NIG_REG_PORT_SWAP
))
3000 emac_base
= GRCBASE_EMAC1
;
3002 emac_base
= GRCBASE_EMAC0
;
3004 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
:
3005 if (REG_RD(bp
, NIG_REG_PORT_SWAP
))
3006 emac_base
= GRCBASE_EMAC0
;
3008 emac_base
= GRCBASE_EMAC1
;
3010 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
:
3011 emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
3013 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED
:
3014 emac_base
= (port
) ? GRCBASE_EMAC0
: GRCBASE_EMAC1
;
3023 /******************************************************************/
3024 /* CL22 access functions */
3025 /******************************************************************/
3026 static int bnx2x_cl22_write(struct bnx2x
*bp
,
3027 struct bnx2x_phy
*phy
,
3033 /* Switch to CL22 */
3034 mode
= REG_RD(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
3035 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
,
3036 mode
& ~EMAC_MDIO_MODE_CLAUSE_45
);
3039 tmp
= ((phy
->addr
<< 21) | (reg
<< 16) | val
|
3040 EMAC_MDIO_COMM_COMMAND_WRITE_22
|
3041 EMAC_MDIO_COMM_START_BUSY
);
3042 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
3044 for (i
= 0; i
< 50; i
++) {
3047 tmp
= REG_RD(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
3048 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
3053 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
3054 DP(NETIF_MSG_LINK
, "write phy register failed\n");
3057 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, mode
);
3061 static int bnx2x_cl22_read(struct bnx2x
*bp
,
3062 struct bnx2x_phy
*phy
,
3063 u16 reg
, u16
*ret_val
)
3069 /* Switch to CL22 */
3070 mode
= REG_RD(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
);
3071 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
,
3072 mode
& ~EMAC_MDIO_MODE_CLAUSE_45
);
3075 val
= ((phy
->addr
<< 21) | (reg
<< 16) |
3076 EMAC_MDIO_COMM_COMMAND_READ_22
|
3077 EMAC_MDIO_COMM_START_BUSY
);
3078 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
3080 for (i
= 0; i
< 50; i
++) {
3083 val
= REG_RD(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
3084 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
3085 *ret_val
= (u16
)(val
& EMAC_MDIO_COMM_DATA
);
3090 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
3091 DP(NETIF_MSG_LINK
, "read phy register failed\n");
3096 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_MODE
, mode
);
3100 /******************************************************************/
3101 /* CL45 access functions */
3102 /******************************************************************/
3103 static int bnx2x_cl45_read(struct bnx2x
*bp
, struct bnx2x_phy
*phy
,
3104 u8 devad
, u16 reg
, u16
*ret_val
)
3109 if (phy
->flags
& FLAGS_MDC_MDIO_WA_B0
)
3110 bnx2x_bits_en(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
3111 EMAC_MDIO_STATUS_10MB
);
3113 val
= ((phy
->addr
<< 21) | (devad
<< 16) | reg
|
3114 EMAC_MDIO_COMM_COMMAND_ADDRESS
|
3115 EMAC_MDIO_COMM_START_BUSY
);
3116 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
3118 for (i
= 0; i
< 50; i
++) {
3121 val
= REG_RD(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
3122 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
3127 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
3128 DP(NETIF_MSG_LINK
, "read phy register failed\n");
3129 netdev_err(bp
->dev
, "MDC/MDIO access timeout\n");
3134 val
= ((phy
->addr
<< 21) | (devad
<< 16) |
3135 EMAC_MDIO_COMM_COMMAND_READ_45
|
3136 EMAC_MDIO_COMM_START_BUSY
);
3137 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, val
);
3139 for (i
= 0; i
< 50; i
++) {
3142 val
= REG_RD(bp
, phy
->mdio_ctrl
+
3143 EMAC_REG_EMAC_MDIO_COMM
);
3144 if (!(val
& EMAC_MDIO_COMM_START_BUSY
)) {
3145 *ret_val
= (u16
)(val
& EMAC_MDIO_COMM_DATA
);
3149 if (val
& EMAC_MDIO_COMM_START_BUSY
) {
3150 DP(NETIF_MSG_LINK
, "read phy register failed\n");
3151 netdev_err(bp
->dev
, "MDC/MDIO access timeout\n");
3156 /* Work around for E3 A0 */
3157 if (phy
->flags
& FLAGS_MDC_MDIO_WA
) {
3158 phy
->flags
^= FLAGS_DUMMY_READ
;
3159 if (phy
->flags
& FLAGS_DUMMY_READ
) {
3161 bnx2x_cl45_read(bp
, phy
, devad
, 0xf, &temp_val
);
3165 if (phy
->flags
& FLAGS_MDC_MDIO_WA_B0
)
3166 bnx2x_bits_dis(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
3167 EMAC_MDIO_STATUS_10MB
);
3171 static int bnx2x_cl45_write(struct bnx2x
*bp
, struct bnx2x_phy
*phy
,
3172 u8 devad
, u16 reg
, u16 val
)
3177 if (phy
->flags
& FLAGS_MDC_MDIO_WA_B0
)
3178 bnx2x_bits_en(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
3179 EMAC_MDIO_STATUS_10MB
);
3182 tmp
= ((phy
->addr
<< 21) | (devad
<< 16) | reg
|
3183 EMAC_MDIO_COMM_COMMAND_ADDRESS
|
3184 EMAC_MDIO_COMM_START_BUSY
);
3185 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
3187 for (i
= 0; i
< 50; i
++) {
3190 tmp
= REG_RD(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
);
3191 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
3196 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
3197 DP(NETIF_MSG_LINK
, "write phy register failed\n");
3198 netdev_err(bp
->dev
, "MDC/MDIO access timeout\n");
3202 tmp
= ((phy
->addr
<< 21) | (devad
<< 16) | val
|
3203 EMAC_MDIO_COMM_COMMAND_WRITE_45
|
3204 EMAC_MDIO_COMM_START_BUSY
);
3205 REG_WR(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_COMM
, tmp
);
3207 for (i
= 0; i
< 50; i
++) {
3210 tmp
= REG_RD(bp
, phy
->mdio_ctrl
+
3211 EMAC_REG_EMAC_MDIO_COMM
);
3212 if (!(tmp
& EMAC_MDIO_COMM_START_BUSY
)) {
3217 if (tmp
& EMAC_MDIO_COMM_START_BUSY
) {
3218 DP(NETIF_MSG_LINK
, "write phy register failed\n");
3219 netdev_err(bp
->dev
, "MDC/MDIO access timeout\n");
3223 /* Work around for E3 A0 */
3224 if (phy
->flags
& FLAGS_MDC_MDIO_WA
) {
3225 phy
->flags
^= FLAGS_DUMMY_READ
;
3226 if (phy
->flags
& FLAGS_DUMMY_READ
) {
3228 bnx2x_cl45_read(bp
, phy
, devad
, 0xf, &temp_val
);
3231 if (phy
->flags
& FLAGS_MDC_MDIO_WA_B0
)
3232 bnx2x_bits_dis(bp
, phy
->mdio_ctrl
+ EMAC_REG_EMAC_MDIO_STATUS
,
3233 EMAC_MDIO_STATUS_10MB
);
3236 /******************************************************************/
3237 /* BSC access functions from E3 */
3238 /******************************************************************/
3239 static void bnx2x_bsc_module_sel(struct link_params
*params
)
3242 u32 board_cfg
, sfp_ctrl
;
3243 u32 i2c_pins
[I2C_SWITCH_WIDTH
], i2c_val
[I2C_SWITCH_WIDTH
];
3244 struct bnx2x
*bp
= params
->bp
;
3245 u8 port
= params
->port
;
3246 /* Read I2C output PINs */
3247 board_cfg
= REG_RD(bp
, params
->shmem_base
+
3248 offsetof(struct shmem_region
,
3249 dev_info
.shared_hw_config
.board
));
3250 i2c_pins
[I2C_BSC0
] = board_cfg
& SHARED_HW_CFG_E3_I2C_MUX0_MASK
;
3251 i2c_pins
[I2C_BSC1
] = (board_cfg
& SHARED_HW_CFG_E3_I2C_MUX1_MASK
) >>
3252 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT
;
3254 /* Read I2C output value */
3255 sfp_ctrl
= REG_RD(bp
, params
->shmem_base
+
3256 offsetof(struct shmem_region
,
3257 dev_info
.port_hw_config
[port
].e3_cmn_pin_cfg
));
3258 i2c_val
[I2C_BSC0
] = (sfp_ctrl
& PORT_HW_CFG_E3_I2C_MUX0_MASK
) > 0;
3259 i2c_val
[I2C_BSC1
] = (sfp_ctrl
& PORT_HW_CFG_E3_I2C_MUX1_MASK
) > 0;
3260 DP(NETIF_MSG_LINK
, "Setting BSC switch\n");
3261 for (idx
= 0; idx
< I2C_SWITCH_WIDTH
; idx
++)
3262 bnx2x_set_cfg_pin(bp
, i2c_pins
[idx
], i2c_val
[idx
]);
3265 static int bnx2x_bsc_read(struct link_params
*params
,
3266 struct bnx2x_phy
*phy
,
3275 struct bnx2x
*bp
= params
->bp
;
3277 if ((sl_devid
!= 0xa0) && (sl_devid
!= 0xa2)) {
3278 DP(NETIF_MSG_LINK
, "invalid sl_devid 0x%x\n", sl_devid
);
3282 if (xfer_cnt
> 16) {
3283 DP(NETIF_MSG_LINK
, "invalid xfer_cnt %d. Max is 16 bytes\n",
3287 bnx2x_bsc_module_sel(params
);
3289 xfer_cnt
= 16 - lc_addr
;
3291 /* Enable the engine */
3292 val
= REG_RD(bp
, MCP_REG_MCPR_IMC_COMMAND
);
3293 val
|= MCPR_IMC_COMMAND_ENABLE
;
3294 REG_WR(bp
, MCP_REG_MCPR_IMC_COMMAND
, val
);
3296 /* Program slave device ID */
3297 val
= (sl_devid
<< 16) | sl_addr
;
3298 REG_WR(bp
, MCP_REG_MCPR_IMC_SLAVE_CONTROL
, val
);
3300 /* Start xfer with 0 byte to update the address pointer ???*/
3301 val
= (MCPR_IMC_COMMAND_ENABLE
) |
3302 (MCPR_IMC_COMMAND_WRITE_OP
<<
3303 MCPR_IMC_COMMAND_OPERATION_BITSHIFT
) |
3304 (lc_addr
<< MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT
) | (0);
3305 REG_WR(bp
, MCP_REG_MCPR_IMC_COMMAND
, val
);
3307 /* Poll for completion */
3309 val
= REG_RD(bp
, MCP_REG_MCPR_IMC_COMMAND
);
3310 while (((val
>> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT
) & 0x3) != 1) {
3312 val
= REG_RD(bp
, MCP_REG_MCPR_IMC_COMMAND
);
3314 DP(NETIF_MSG_LINK
, "wr 0 byte timed out after %d try\n",
3323 /* Start xfer with read op */
3324 val
= (MCPR_IMC_COMMAND_ENABLE
) |
3325 (MCPR_IMC_COMMAND_READ_OP
<<
3326 MCPR_IMC_COMMAND_OPERATION_BITSHIFT
) |
3327 (lc_addr
<< MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT
) |
3329 REG_WR(bp
, MCP_REG_MCPR_IMC_COMMAND
, val
);
3331 /* Poll for completion */
3333 val
= REG_RD(bp
, MCP_REG_MCPR_IMC_COMMAND
);
3334 while (((val
>> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT
) & 0x3) != 1) {
3336 val
= REG_RD(bp
, MCP_REG_MCPR_IMC_COMMAND
);
3338 DP(NETIF_MSG_LINK
, "rd op timed out after %d try\n", i
);
3346 for (i
= (lc_addr
>> 2); i
< 4; i
++) {
3347 data_array
[i
] = REG_RD(bp
, (MCP_REG_MCPR_IMC_DATAREG0
+ i
*4));
3349 data_array
[i
] = ((data_array
[i
] & 0x000000ff) << 24) |
3350 ((data_array
[i
] & 0x0000ff00) << 8) |
3351 ((data_array
[i
] & 0x00ff0000) >> 8) |
3352 ((data_array
[i
] & 0xff000000) >> 24);
3358 static void bnx2x_cl45_read_or_write(struct bnx2x
*bp
, struct bnx2x_phy
*phy
,
3359 u8 devad
, u16 reg
, u16 or_val
)
3362 bnx2x_cl45_read(bp
, phy
, devad
, reg
, &val
);
3363 bnx2x_cl45_write(bp
, phy
, devad
, reg
, val
| or_val
);
3366 int bnx2x_phy_read(struct link_params
*params
, u8 phy_addr
,
3367 u8 devad
, u16 reg
, u16
*ret_val
)
3370 /* Probe for the phy according to the given phy_addr, and execute
3371 * the read request on it
3373 for (phy_index
= 0; phy_index
< params
->num_phys
; phy_index
++) {
3374 if (params
->phy
[phy_index
].addr
== phy_addr
) {
3375 return bnx2x_cl45_read(params
->bp
,
3376 ¶ms
->phy
[phy_index
], devad
,
3383 int bnx2x_phy_write(struct link_params
*params
, u8 phy_addr
,
3384 u8 devad
, u16 reg
, u16 val
)
3387 /* Probe for the phy according to the given phy_addr, and execute
3388 * the write request on it
3390 for (phy_index
= 0; phy_index
< params
->num_phys
; phy_index
++) {
3391 if (params
->phy
[phy_index
].addr
== phy_addr
) {
3392 return bnx2x_cl45_write(params
->bp
,
3393 ¶ms
->phy
[phy_index
], devad
,
3399 static u8
bnx2x_get_warpcore_lane(struct bnx2x_phy
*phy
,
3400 struct link_params
*params
)
3403 struct bnx2x
*bp
= params
->bp
;
3404 u32 path_swap
, path_swap_ovr
;
3408 port
= params
->port
;
3410 if (bnx2x_is_4_port_mode(bp
)) {
3411 u32 port_swap
, port_swap_ovr
;
3413 /* Figure out path swap value */
3414 path_swap_ovr
= REG_RD(bp
, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR
);
3415 if (path_swap_ovr
& 0x1)
3416 path_swap
= (path_swap_ovr
& 0x2);
3418 path_swap
= REG_RD(bp
, MISC_REG_FOUR_PORT_PATH_SWAP
);
3423 /* Figure out port swap value */
3424 port_swap_ovr
= REG_RD(bp
, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR
);
3425 if (port_swap_ovr
& 0x1)
3426 port_swap
= (port_swap_ovr
& 0x2);
3428 port_swap
= REG_RD(bp
, MISC_REG_FOUR_PORT_PORT_SWAP
);
3433 lane
= (port
<<1) + path
;
3434 } else { /* Two port mode - no port swap */
3436 /* Figure out path swap value */
3438 REG_RD(bp
, MISC_REG_TWO_PORT_PATH_SWAP_OVWR
);
3439 if (path_swap_ovr
& 0x1) {
3440 path_swap
= (path_swap_ovr
& 0x2);
3443 REG_RD(bp
, MISC_REG_TWO_PORT_PATH_SWAP
);
3453 static void bnx2x_set_aer_mmd(struct link_params
*params
,
3454 struct bnx2x_phy
*phy
)
3457 u16 offset
, aer_val
;
3458 struct bnx2x
*bp
= params
->bp
;
3459 ser_lane
= ((params
->lane_config
&
3460 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
3461 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
3463 offset
= (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) ?
3464 (phy
->addr
+ ser_lane
) : 0;
3466 if (USES_WARPCORE(bp
)) {
3467 aer_val
= bnx2x_get_warpcore_lane(phy
, params
);
3468 /* In Dual-lane mode, two lanes are joined together,
3469 * so in order to configure them, the AER broadcast method is
3471 * 0x200 is the broadcast address for lanes 0,1
3472 * 0x201 is the broadcast address for lanes 2,3
3474 if (phy
->flags
& FLAGS_WC_DUAL_MODE
)
3475 aer_val
= (aer_val
>> 1) | 0x200;
3476 } else if (CHIP_IS_E2(bp
))
3477 aer_val
= 0x3800 + offset
- 1;
3479 aer_val
= 0x3800 + offset
;
3481 CL22_WR_OVER_CL45(bp
, phy
, MDIO_REG_BANK_AER_BLOCK
,
3482 MDIO_AER_BLOCK_AER_REG
, aer_val
);
3486 /******************************************************************/
3487 /* Internal phy section */
3488 /******************************************************************/
3490 static void bnx2x_set_serdes_access(struct bnx2x
*bp
, u8 port
)
3492 u32 emac_base
= (port
) ? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
3495 REG_WR(bp
, NIG_REG_SERDES0_CTRL_MD_ST
+ port
*0x10, 1);
3496 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245f8000);
3498 REG_WR(bp
, emac_base
+ EMAC_REG_EMAC_MDIO_COMM
, 0x245d000f);
3501 REG_WR(bp
, NIG_REG_SERDES0_CTRL_MD_ST
+ port
*0x10, 0);
3504 static void bnx2x_serdes_deassert(struct bnx2x
*bp
, u8 port
)
3508 DP(NETIF_MSG_LINK
, "bnx2x_serdes_deassert\n");
3510 val
= SERDES_RESET_BITS
<< (port
*16);
3512 /* Reset and unreset the SerDes/XGXS */
3513 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
, val
);
3515 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_SET
, val
);
3517 bnx2x_set_serdes_access(bp
, port
);
3519 REG_WR(bp
, NIG_REG_SERDES0_CTRL_MD_DEVAD
+ port
*0x10,
3520 DEFAULT_PHY_DEV_ADDR
);
3523 static void bnx2x_xgxs_deassert(struct link_params
*params
)
3525 struct bnx2x
*bp
= params
->bp
;
3528 DP(NETIF_MSG_LINK
, "bnx2x_xgxs_deassert\n");
3529 port
= params
->port
;
3531 val
= XGXS_RESET_BITS
<< (port
*16);
3533 /* Reset and unreset the SerDes/XGXS */
3534 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
, val
);
3536 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_SET
, val
);
3538 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_ST
+ port
*0x18, 0);
3539 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
*0x18,
3540 params
->phy
[INT_PHY
].def_md_devad
);
3543 static void bnx2x_calc_ieee_aneg_adv(struct bnx2x_phy
*phy
,
3544 struct link_params
*params
, u16
*ieee_fc
)
3546 struct bnx2x
*bp
= params
->bp
;
3547 *ieee_fc
= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX
;
3548 /* Resolve pause mode and advertisement Please refer to Table
3549 * 28B-3 of the 802.3ab-1999 spec
3552 switch (phy
->req_flow_ctrl
) {
3553 case BNX2X_FLOW_CTRL_AUTO
:
3554 if (params
->req_fc_auto_adv
== BNX2X_FLOW_CTRL_BOTH
)
3555 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3558 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
3561 case BNX2X_FLOW_CTRL_TX
:
3562 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
3565 case BNX2X_FLOW_CTRL_RX
:
3566 case BNX2X_FLOW_CTRL_BOTH
:
3567 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
3570 case BNX2X_FLOW_CTRL_NONE
:
3572 *ieee_fc
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
;
3575 DP(NETIF_MSG_LINK
, "ieee_fc = 0x%x\n", *ieee_fc
);
3578 static void set_phy_vars(struct link_params
*params
,
3579 struct link_vars
*vars
)
3581 struct bnx2x
*bp
= params
->bp
;
3582 u8 actual_phy_idx
, phy_index
, link_cfg_idx
;
3583 u8 phy_config_swapped
= params
->multi_phy_config
&
3584 PORT_HW_CFG_PHY_SWAPPED_ENABLED
;
3585 for (phy_index
= INT_PHY
; phy_index
< params
->num_phys
;
3587 link_cfg_idx
= LINK_CONFIG_IDX(phy_index
);
3588 actual_phy_idx
= phy_index
;
3589 if (phy_config_swapped
) {
3590 if (phy_index
== EXT_PHY1
)
3591 actual_phy_idx
= EXT_PHY2
;
3592 else if (phy_index
== EXT_PHY2
)
3593 actual_phy_idx
= EXT_PHY1
;
3595 params
->phy
[actual_phy_idx
].req_flow_ctrl
=
3596 params
->req_flow_ctrl
[link_cfg_idx
];
3598 params
->phy
[actual_phy_idx
].req_line_speed
=
3599 params
->req_line_speed
[link_cfg_idx
];
3601 params
->phy
[actual_phy_idx
].speed_cap_mask
=
3602 params
->speed_cap_mask
[link_cfg_idx
];
3604 params
->phy
[actual_phy_idx
].req_duplex
=
3605 params
->req_duplex
[link_cfg_idx
];
3607 if (params
->req_line_speed
[link_cfg_idx
] ==
3609 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_ENABLED
;
3611 DP(NETIF_MSG_LINK
, "req_flow_ctrl %x, req_line_speed %x,"
3612 " speed_cap_mask %x\n",
3613 params
->phy
[actual_phy_idx
].req_flow_ctrl
,
3614 params
->phy
[actual_phy_idx
].req_line_speed
,
3615 params
->phy
[actual_phy_idx
].speed_cap_mask
);
3619 static void bnx2x_ext_phy_set_pause(struct link_params
*params
,
3620 struct bnx2x_phy
*phy
,
3621 struct link_vars
*vars
)
3624 struct bnx2x
*bp
= params
->bp
;
3625 /* Read modify write pause advertizing */
3626 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV_PAUSE
, &val
);
3628 val
&= ~MDIO_AN_REG_ADV_PAUSE_BOTH
;
3630 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
3631 bnx2x_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
3632 if ((vars
->ieee_fc
&
3633 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
3634 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
3635 val
|= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC
;
3637 if ((vars
->ieee_fc
&
3638 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
3639 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
3640 val
|= MDIO_AN_REG_ADV_PAUSE_PAUSE
;
3642 DP(NETIF_MSG_LINK
, "Ext phy AN advertize 0x%x\n", val
);
3643 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV_PAUSE
, val
);
3646 static void bnx2x_pause_resolve(struct link_vars
*vars
, u32 pause_result
)
3648 switch (pause_result
) { /* ASYM P ASYM P */
3649 case 0xb: /* 1 0 1 1 */
3650 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_TX
;
3653 case 0xe: /* 1 1 1 0 */
3654 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_RX
;
3657 case 0x5: /* 0 1 0 1 */
3658 case 0x7: /* 0 1 1 1 */
3659 case 0xd: /* 1 1 0 1 */
3660 case 0xf: /* 1 1 1 1 */
3661 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_BOTH
;
3667 if (pause_result
& (1<<0))
3668 vars
->link_status
|= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE
;
3669 if (pause_result
& (1<<1))
3670 vars
->link_status
|= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE
;
3674 static void bnx2x_ext_phy_update_adv_fc(struct bnx2x_phy
*phy
,
3675 struct link_params
*params
,
3676 struct link_vars
*vars
)
3678 u16 ld_pause
; /* local */
3679 u16 lp_pause
; /* link partner */
3681 struct bnx2x
*bp
= params
->bp
;
3682 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE
) {
3683 bnx2x_cl22_read(bp
, phy
, 0x4, &ld_pause
);
3684 bnx2x_cl22_read(bp
, phy
, 0x5, &lp_pause
);
3685 } else if (CHIP_IS_E3(bp
) &&
3686 SINGLE_MEDIA_DIRECT(params
)) {
3687 u8 lane
= bnx2x_get_warpcore_lane(phy
, params
);
3688 u16 gp_status
, gp_mask
;
3689 bnx2x_cl45_read(bp
, phy
,
3690 MDIO_AN_DEVAD
, MDIO_WC_REG_GP2_STATUS_GP_2_4
,
3692 gp_mask
= (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL
|
3693 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP
) <<
3695 if ((gp_status
& gp_mask
) == gp_mask
) {
3696 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
3697 MDIO_AN_REG_ADV_PAUSE
, &ld_pause
);
3698 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
3699 MDIO_AN_REG_LP_AUTO_NEG
, &lp_pause
);
3701 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
3702 MDIO_AN_REG_CL37_FC_LD
, &ld_pause
);
3703 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
3704 MDIO_AN_REG_CL37_FC_LP
, &lp_pause
);
3705 ld_pause
= ((ld_pause
&
3706 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
)
3708 lp_pause
= ((lp_pause
&
3709 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
)
3713 bnx2x_cl45_read(bp
, phy
,
3715 MDIO_AN_REG_ADV_PAUSE
, &ld_pause
);
3716 bnx2x_cl45_read(bp
, phy
,
3718 MDIO_AN_REG_LP_AUTO_NEG
, &lp_pause
);
3720 pause_result
= (ld_pause
&
3721 MDIO_AN_REG_ADV_PAUSE_MASK
) >> 8;
3722 pause_result
|= (lp_pause
&
3723 MDIO_AN_REG_ADV_PAUSE_MASK
) >> 10;
3724 DP(NETIF_MSG_LINK
, "Ext PHY pause result 0x%x\n", pause_result
);
3725 bnx2x_pause_resolve(vars
, pause_result
);
3729 static u8
bnx2x_ext_phy_resolve_fc(struct bnx2x_phy
*phy
,
3730 struct link_params
*params
,
3731 struct link_vars
*vars
)
3734 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
3735 if (phy
->req_flow_ctrl
!= BNX2X_FLOW_CTRL_AUTO
) {
3736 /* Update the advertised flow-controled of LD/LP in AN */
3737 if (phy
->req_line_speed
== SPEED_AUTO_NEG
)
3738 bnx2x_ext_phy_update_adv_fc(phy
, params
, vars
);
3739 /* But set the flow-control result as the requested one */
3740 vars
->flow_ctrl
= phy
->req_flow_ctrl
;
3741 } else if (phy
->req_line_speed
!= SPEED_AUTO_NEG
)
3742 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
3743 else if (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
3745 bnx2x_ext_phy_update_adv_fc(phy
, params
, vars
);
3749 /******************************************************************/
3750 /* Warpcore section */
3751 /******************************************************************/
3752 /* The init_internal_warpcore should mirror the xgxs,
3753 * i.e. reset the lane (if needed), set aer for the
3754 * init configuration, and set/clear SGMII flag. Internal
3755 * phy init is done purely in phy_init stage.
3757 static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy
*phy
,
3758 struct link_params
*params
,
3759 struct link_vars
*vars
) {
3760 u16 val16
= 0, lane
, i
;
3761 struct bnx2x
*bp
= params
->bp
;
3762 static struct bnx2x_reg_set reg_set
[] = {
3763 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, 0x7},
3764 {MDIO_AN_DEVAD
, MDIO_WC_REG_PAR_DET_10G_CTRL
, 0},
3765 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
, 0},
3766 {MDIO_WC_DEVAD
, MDIO_WC_REG_XGXSBLK1_LANECTRL0
, 0xff},
3767 {MDIO_WC_DEVAD
, MDIO_WC_REG_XGXSBLK1_LANECTRL1
, 0x5555},
3768 {MDIO_PMA_DEVAD
, MDIO_WC_REG_IEEE0BLK_AUTONEGNP
, 0x0},
3769 {MDIO_WC_DEVAD
, MDIO_WC_REG_RX66_CONTROL
, 0x7415},
3770 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_MISC2
, 0x6190},
3771 /* Disable Autoneg: re-enable it after adv is done. */
3772 {MDIO_AN_DEVAD
, MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0}
3774 DP(NETIF_MSG_LINK
, "Enable Auto Negotiation for KR\n");
3775 /* Set to default registers that may be overriden by 10G force */
3776 for (i
= 0; i
< sizeof(reg_set
)/sizeof(struct bnx2x_reg_set
); i
++)
3777 bnx2x_cl45_write(bp
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3780 /* Check adding advertisement for 1G KX */
3781 if (((vars
->line_speed
== SPEED_AUTO_NEG
) &&
3782 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
3783 (vars
->line_speed
== SPEED_1000
)) {
3784 u32 addr
= MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
;
3787 /* Enable CL37 1G Parallel Detect */
3788 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
, addr
, 0x1);
3789 DP(NETIF_MSG_LINK
, "Advertize 1G\n");
3791 if (((vars
->line_speed
== SPEED_AUTO_NEG
) &&
3792 (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) ||
3793 (vars
->line_speed
== SPEED_10000
)) {
3794 /* Check adding advertisement for 10G KR */
3796 /* Enable 10G Parallel Detect */
3797 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
,
3798 MDIO_WC_REG_PAR_DET_10G_CTRL
, 1);
3800 DP(NETIF_MSG_LINK
, "Advertize 10G\n");
3803 /* Set Transmit PMD settings */
3804 lane
= bnx2x_get_warpcore_lane(phy
, params
);
3805 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3806 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10*lane
,
3807 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET
) |
3808 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET
) |
3809 (0x09 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET
)));
3810 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3811 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL
,
3813 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3814 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL
,
3817 /* Advertised speeds */
3818 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
,
3819 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1
, val16
);
3821 /* Advertised and set FEC (Forward Error Correction) */
3822 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
,
3823 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2
,
3824 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY
|
3825 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ
));
3827 /* Enable CL37 BAM */
3828 if (REG_RD(bp
, params
->shmem_base
+
3829 offsetof(struct shmem_region
, dev_info
.
3830 port_hw_config
[params
->port
].default_cfg
)) &
3831 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED
) {
3832 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
3833 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL
,
3835 DP(NETIF_MSG_LINK
, "Enable CL37 BAM on KR\n");
3838 /* Advertise pause */
3839 bnx2x_ext_phy_set_pause(params
, phy
, vars
);
3840 /* Set KR Autoneg Work-Around flag for Warpcore version older than D108
3842 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
3843 MDIO_WC_REG_UC_INFO_B1_VERSION
, &val16
);
3844 if (val16
< 0xd108) {
3845 DP(NETIF_MSG_LINK
, "Enable AN KR work-around\n");
3846 vars
->rx_tx_asic_rst
= MAX_KR_LINK_RETRY
;
3848 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
3849 MDIO_WC_REG_DIGITAL5_MISC7
, 0x100);
3851 /* Over 1G - AN local device user page 1 */
3852 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3853 MDIO_WC_REG_DIGITAL3_UP1
, 0x1f);
3855 /* Enable Autoneg */
3856 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
,
3857 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x1200);
3861 static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy
*phy
,
3862 struct link_params
*params
,
3863 struct link_vars
*vars
)
3865 struct bnx2x
*bp
= params
->bp
;
3867 static struct bnx2x_reg_set reg_set
[] = {
3868 /* Disable Autoneg */
3869 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, 0x7},
3870 {MDIO_AN_DEVAD
, MDIO_WC_REG_PAR_DET_10G_CTRL
, 0},
3871 {MDIO_WC_DEVAD
, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
,
3873 {MDIO_AN_DEVAD
, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1
, 0},
3874 {MDIO_AN_DEVAD
, MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x0},
3875 {MDIO_WC_DEVAD
, MDIO_WC_REG_DIGITAL3_UP1
, 0x1},
3876 {MDIO_WC_DEVAD
, MDIO_WC_REG_DIGITAL5_MISC7
, 0xa},
3877 /* Disable CL36 PCS Tx */
3878 {MDIO_WC_DEVAD
, MDIO_WC_REG_XGXSBLK1_LANECTRL0
, 0x0},
3879 /* Double Wide Single Data Rate @ pll rate */
3880 {MDIO_WC_DEVAD
, MDIO_WC_REG_XGXSBLK1_LANECTRL1
, 0xFFFF},
3881 /* Leave cl72 training enable, needed for KR */
3883 MDIO_WC_REG_PMD_IEEE9BLK_TENGBASE_KR_PMD_CONTROL_REGISTER_150
,
3887 for (i
= 0; i
< sizeof(reg_set
)/sizeof(struct bnx2x_reg_set
); i
++)
3888 bnx2x_cl45_write(bp
, phy
, reg_set
[i
].devad
, reg_set
[i
].reg
,
3891 /* Leave CL72 enabled */
3892 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
3893 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL
,
3896 /* Set speed via PMA/PMD register */
3897 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
,
3898 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x2040);
3900 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
,
3901 MDIO_WC_REG_IEEE0BLK_AUTONEGNP
, 0xB);
3903 /* Enable encoded forced speed */
3904 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3905 MDIO_WC_REG_SERDESDIGITAL_MISC2
, 0x30);
3907 /* Turn TX scramble payload only the 64/66 scrambler */
3908 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3909 MDIO_WC_REG_TX66_CONTROL
, 0x9);
3911 /* Turn RX scramble payload only the 64/66 scrambler */
3912 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
3913 MDIO_WC_REG_RX66_CONTROL
, 0xF9);
3915 /* Set and clear loopback to cause a reset to 64/66 decoder */
3916 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3917 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x4000);
3918 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3919 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x0);
3923 static void bnx2x_warpcore_set_10G_XFI(struct bnx2x_phy
*phy
,
3924 struct link_params
*params
,
3927 struct bnx2x
*bp
= params
->bp
;
3928 u16 misc1_val
, tap_val
, tx_driver_val
, lane
, val
;
3929 /* Hold rxSeqStart */
3930 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
3931 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0
, 0x8000);
3933 /* Hold tx_fifo_reset */
3934 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
3935 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
, 0x1);
3937 /* Disable CL73 AN */
3938 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0);
3940 /* Disable 100FX Enable and Auto-Detect */
3941 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
3942 MDIO_WC_REG_FX100_CTRL1
, &val
);
3943 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3944 MDIO_WC_REG_FX100_CTRL1
, (val
& 0xFFFA));
3946 /* Disable 100FX Idle detect */
3947 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
3948 MDIO_WC_REG_FX100_CTRL3
, 0x0080);
3950 /* Set Block address to Remote PHY & Clear forced_speed[5] */
3951 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
3952 MDIO_WC_REG_DIGITAL4_MISC3
, &val
);
3953 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3954 MDIO_WC_REG_DIGITAL4_MISC3
, (val
& 0xFF7F));
3956 /* Turn off auto-detect & fiber mode */
3957 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
3958 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
, &val
);
3959 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3960 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
3963 /* Set filter_force_link, disable_false_link and parallel_detect */
3964 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
3965 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, &val
);
3966 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3967 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
3968 ((val
| 0x0006) & 0xFFFE));
3971 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
3972 MDIO_WC_REG_SERDESDIGITAL_MISC1
, &misc1_val
);
3974 misc1_val
&= ~(0x1f);
3978 tap_val
= ((0x08 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET
) |
3979 (0x37 << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET
) |
3980 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET
));
3982 ((0x00 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET
) |
3983 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET
) |
3984 (0x03 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET
));
3988 tap_val
= ((0x0f << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET
) |
3989 (0x2b << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET
) |
3990 (0x02 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET
));
3992 ((0x03 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET
) |
3993 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET
) |
3994 (0x06 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET
));
3996 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
3997 MDIO_WC_REG_SERDESDIGITAL_MISC1
, misc1_val
);
3999 /* Set Transmit PMD settings */
4000 lane
= bnx2x_get_warpcore_lane(phy
, params
);
4001 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4002 MDIO_WC_REG_TX_FIR_TAP
,
4003 tap_val
| MDIO_WC_REG_TX_FIR_TAP_ENABLE
);
4004 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4005 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10*lane
,
4008 /* Enable fiber mode, enable and invert sig_det */
4009 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
4010 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
, 0xd);
4012 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4013 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
4014 MDIO_WC_REG_DIGITAL4_MISC3
, 0x8080);
4016 /* Enable LPI pass through */
4017 DP(NETIF_MSG_LINK
, "Configure WC for LPI pass through\n");
4018 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4019 MDIO_WC_REG_EEE_COMBO_CONTROL0
,
4021 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
4022 MDIO_WC_REG_DIGITAL4_MISC5
, 0xc000);
4024 /* 10G XFI Full Duplex */
4025 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4026 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x100);
4028 /* Release tx_fifo_reset */
4029 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4030 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
, &val
);
4031 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4032 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
, val
& 0xFFFE);
4034 /* Release rxSeqStart */
4035 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4036 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0
, &val
);
4037 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4038 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0
, (val
& 0x7FFF));
4041 static void bnx2x_warpcore_set_20G_KR2(struct bnx2x
*bp
,
4042 struct bnx2x_phy
*phy
)
4044 DP(NETIF_MSG_LINK
, "KR2 still not supported !!!\n");
4047 static void bnx2x_warpcore_set_20G_DXGXS(struct bnx2x
*bp
,
4048 struct bnx2x_phy
*phy
,
4051 /* Rx0 anaRxControl1G */
4052 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4053 MDIO_WC_REG_RX0_ANARXCONTROL1G
, 0x90);
4055 /* Rx2 anaRxControl1G */
4056 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4057 MDIO_WC_REG_RX2_ANARXCONTROL1G
, 0x90);
4059 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4060 MDIO_WC_REG_RX66_SCW0
, 0xE070);
4062 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4063 MDIO_WC_REG_RX66_SCW1
, 0xC0D0);
4065 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4066 MDIO_WC_REG_RX66_SCW2
, 0xA0B0);
4068 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4069 MDIO_WC_REG_RX66_SCW3
, 0x8090);
4071 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4072 MDIO_WC_REG_RX66_SCW0_MASK
, 0xF0F0);
4074 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4075 MDIO_WC_REG_RX66_SCW1_MASK
, 0xF0F0);
4077 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4078 MDIO_WC_REG_RX66_SCW2_MASK
, 0xF0F0);
4080 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4081 MDIO_WC_REG_RX66_SCW3_MASK
, 0xF0F0);
4083 /* Serdes Digital Misc1 */
4084 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4085 MDIO_WC_REG_SERDESDIGITAL_MISC1
, 0x6008);
4087 /* Serdes Digital4 Misc3 */
4088 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4089 MDIO_WC_REG_DIGITAL4_MISC3
, 0x8088);
4091 /* Set Transmit PMD settings */
4092 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4093 MDIO_WC_REG_TX_FIR_TAP
,
4094 ((0x12 << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET
) |
4095 (0x2d << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET
) |
4096 (0x00 << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET
) |
4097 MDIO_WC_REG_TX_FIR_TAP_ENABLE
));
4098 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4099 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10*lane
,
4100 ((0x02 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET
) |
4101 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET
) |
4102 (0x02 << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET
)));
4105 static void bnx2x_warpcore_set_sgmii_speed(struct bnx2x_phy
*phy
,
4106 struct link_params
*params
,
4110 struct bnx2x
*bp
= params
->bp
;
4111 u16 val16
, digctrl_kx1
, digctrl_kx2
;
4113 /* Clear XFI clock comp in non-10G single lane mode. */
4114 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4115 MDIO_WC_REG_RX66_CONTROL
, &val16
);
4116 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4117 MDIO_WC_REG_RX66_CONTROL
, val16
& ~(3<<13));
4119 if (always_autoneg
|| phy
->req_line_speed
== SPEED_AUTO_NEG
) {
4121 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4122 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, &val16
);
4123 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4124 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
,
4126 DP(NETIF_MSG_LINK
, "set SGMII AUTONEG\n");
4128 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4129 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, &val16
);
4131 switch (phy
->req_line_speed
) {
4142 "Speed not supported: 0x%x\n", phy
->req_line_speed
);
4146 if (phy
->req_duplex
== DUPLEX_FULL
)
4149 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4150 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, val16
);
4152 DP(NETIF_MSG_LINK
, "set SGMII force speed %d\n",
4153 phy
->req_line_speed
);
4154 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4155 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, &val16
);
4156 DP(NETIF_MSG_LINK
, " (readback) %x\n", val16
);
4159 /* SGMII Slave mode and disable signal detect */
4160 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4161 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
, &digctrl_kx1
);
4165 digctrl_kx1
&= 0xff4a;
4167 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4168 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
4171 /* Turn off parallel detect */
4172 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4173 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
, &digctrl_kx2
);
4174 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4175 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
4176 (digctrl_kx2
& ~(1<<2)));
4178 /* Re-enable parallel detect */
4179 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4180 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
4181 (digctrl_kx2
| (1<<2)));
4183 /* Enable autodet */
4184 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4185 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
4186 (digctrl_kx1
| 0x10));
4189 static void bnx2x_warpcore_reset_lane(struct bnx2x
*bp
,
4190 struct bnx2x_phy
*phy
,
4194 /* Take lane out of reset after configuration is finished */
4195 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4196 MDIO_WC_REG_DIGITAL5_MISC6
, &val
);
4201 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4202 MDIO_WC_REG_DIGITAL5_MISC6
, val
);
4203 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4204 MDIO_WC_REG_DIGITAL5_MISC6
, &val
);
4206 /* Clear SFI/XFI link settings registers */
4207 static void bnx2x_warpcore_clear_regs(struct bnx2x_phy
*phy
,
4208 struct link_params
*params
,
4211 struct bnx2x
*bp
= params
->bp
;
4213 static struct bnx2x_reg_set wc_regs
[] = {
4214 {MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0},
4215 {MDIO_WC_DEVAD
, MDIO_WC_REG_FX100_CTRL1
, 0x014a},
4216 {MDIO_WC_DEVAD
, MDIO_WC_REG_FX100_CTRL3
, 0x0800},
4217 {MDIO_WC_DEVAD
, MDIO_WC_REG_DIGITAL4_MISC3
, 0x8008},
4218 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1
,
4220 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2
,
4222 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3
,
4224 {MDIO_WC_DEVAD
, MDIO_WC_REG_SERDESDIGITAL_MISC1
, 0x6000},
4225 {MDIO_WC_DEVAD
, MDIO_WC_REG_TX_FIR_TAP
, 0x0000},
4226 {MDIO_WC_DEVAD
, MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x2040},
4227 {MDIO_WC_DEVAD
, MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, 0x0140}
4229 /* Set XFI clock comp as default. */
4230 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
4231 MDIO_WC_REG_RX66_CONTROL
, (3<<13));
4233 for (i
= 0; i
< sizeof(wc_regs
)/sizeof(struct bnx2x_reg_set
); i
++)
4234 bnx2x_cl45_write(bp
, phy
, wc_regs
[i
].devad
, wc_regs
[i
].reg
,
4237 lane
= bnx2x_get_warpcore_lane(phy
, params
);
4238 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4239 MDIO_WC_REG_TX0_TX_DRIVER
+ 0x10*lane
, 0x0990);
4243 static int bnx2x_get_mod_abs_int_cfg(struct bnx2x
*bp
,
4245 u32 shmem_base
, u8 port
,
4246 u8
*gpio_num
, u8
*gpio_port
)
4251 if (CHIP_IS_E3(bp
)) {
4252 cfg_pin
= (REG_RD(bp
, shmem_base
+
4253 offsetof(struct shmem_region
,
4254 dev_info
.port_hw_config
[port
].e3_sfp_ctrl
)) &
4255 PORT_HW_CFG_E3_MOD_ABS_MASK
) >>
4256 PORT_HW_CFG_E3_MOD_ABS_SHIFT
;
4258 /* Should not happen. This function called upon interrupt
4259 * triggered by GPIO ( since EPIO can only generate interrupts
4261 * So if this function was called and none of the GPIOs was set,
4262 * it means the shit hit the fan.
4264 if ((cfg_pin
< PIN_CFG_GPIO0_P0
) ||
4265 (cfg_pin
> PIN_CFG_GPIO3_P1
)) {
4267 "ERROR: Invalid cfg pin %x for module detect indication\n",
4272 *gpio_num
= (cfg_pin
- PIN_CFG_GPIO0_P0
) & 0x3;
4273 *gpio_port
= (cfg_pin
- PIN_CFG_GPIO0_P0
) >> 2;
4275 *gpio_num
= MISC_REGISTERS_GPIO_3
;
4278 DP(NETIF_MSG_LINK
, "MOD_ABS int GPIO%d_P%d\n", *gpio_num
, *gpio_port
);
4282 static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy
*phy
,
4283 struct link_params
*params
)
4285 struct bnx2x
*bp
= params
->bp
;
4286 u8 gpio_num
, gpio_port
;
4288 if (bnx2x_get_mod_abs_int_cfg(bp
, params
->chip_id
,
4289 params
->shmem_base
, params
->port
,
4290 &gpio_num
, &gpio_port
) != 0)
4292 gpio_val
= bnx2x_get_gpio(bp
, gpio_num
, gpio_port
);
4294 /* Call the handling function in case module is detected */
4300 static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy
*phy
,
4301 struct link_params
*params
)
4303 u16 gp2_status_reg0
, lane
;
4304 struct bnx2x
*bp
= params
->bp
;
4306 lane
= bnx2x_get_warpcore_lane(phy
, params
);
4308 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
, MDIO_WC_REG_GP2_STATUS_GP_2_0
,
4311 return (gp2_status_reg0
>> (8+lane
)) & 0x1;
4314 static void bnx2x_warpcore_config_runtime(struct bnx2x_phy
*phy
,
4315 struct link_params
*params
,
4316 struct link_vars
*vars
)
4318 struct bnx2x
*bp
= params
->bp
;
4320 u16 gp_status1
= 0, lnkup
= 0, lnkup_kr
= 0;
4321 u16 lane
= bnx2x_get_warpcore_lane(phy
, params
);
4323 vars
->turn_to_run_wc_rt
= vars
->turn_to_run_wc_rt
? 0 : 1;
4325 if (!vars
->turn_to_run_wc_rt
)
4328 /* Return if there is no link partner */
4329 if (!(bnx2x_warpcore_get_sigdet(phy
, params
))) {
4330 DP(NETIF_MSG_LINK
, "bnx2x_warpcore_get_sigdet false\n");
4334 if (vars
->rx_tx_asic_rst
) {
4335 serdes_net_if
= (REG_RD(bp
, params
->shmem_base
+
4336 offsetof(struct shmem_region
, dev_info
.
4337 port_hw_config
[params
->port
].default_cfg
)) &
4338 PORT_HW_CFG_NET_SERDES_IF_MASK
);
4340 switch (serdes_net_if
) {
4341 case PORT_HW_CFG_NET_SERDES_IF_KR
:
4342 /* Do we get link yet? */
4343 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
, 0x81d1,
4345 lnkup
= (gp_status1
>> (8+lane
)) & 0x1;/* 1G */
4347 lnkup_kr
= (gp_status1
>> (12+lane
)) & 0x1;
4350 "gp_status1 0x%x\n", gp_status1
);
4352 if (lnkup_kr
|| lnkup
) {
4353 vars
->rx_tx_asic_rst
= 0;
4355 "link up, rx_tx_asic_rst 0x%x\n",
4356 vars
->rx_tx_asic_rst
);
4358 /* Reset the lane to see if link comes up.*/
4359 bnx2x_warpcore_reset_lane(bp
, phy
, 1);
4360 bnx2x_warpcore_reset_lane(bp
, phy
, 0);
4362 /* Restart Autoneg */
4363 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
,
4364 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x1200);
4366 vars
->rx_tx_asic_rst
--;
4367 DP(NETIF_MSG_LINK
, "0x%x retry left\n",
4368 vars
->rx_tx_asic_rst
);
4376 } /*params->rx_tx_asic_rst*/
4379 static void bnx2x_warpcore_config_sfi(struct bnx2x_phy
*phy
,
4380 struct link_params
*params
)
4382 u16 lane
= bnx2x_get_warpcore_lane(phy
, params
);
4383 struct bnx2x
*bp
= params
->bp
;
4384 bnx2x_warpcore_clear_regs(phy
, params
, lane
);
4385 if ((params
->req_line_speed
[LINK_CONFIG_IDX(INT_PHY
)] ==
4387 (phy
->media_type
!= ETH_PHY_SFP_1G_FIBER
)) {
4388 DP(NETIF_MSG_LINK
, "Setting 10G SFI\n");
4389 bnx2x_warpcore_set_10G_XFI(phy
, params
, 0);
4391 DP(NETIF_MSG_LINK
, "Setting 1G Fiber\n");
4392 bnx2x_warpcore_set_sgmii_speed(phy
, params
, 1, 0);
4396 static void bnx2x_warpcore_config_init(struct bnx2x_phy
*phy
,
4397 struct link_params
*params
,
4398 struct link_vars
*vars
)
4400 struct bnx2x
*bp
= params
->bp
;
4403 u16 lane
= bnx2x_get_warpcore_lane(phy
, params
);
4404 serdes_net_if
= (REG_RD(bp
, params
->shmem_base
+
4405 offsetof(struct shmem_region
, dev_info
.
4406 port_hw_config
[params
->port
].default_cfg
)) &
4407 PORT_HW_CFG_NET_SERDES_IF_MASK
);
4408 DP(NETIF_MSG_LINK
, "Begin Warpcore init, link_speed %d, "
4409 "serdes_net_if = 0x%x\n",
4410 vars
->line_speed
, serdes_net_if
);
4411 bnx2x_set_aer_mmd(params
, phy
);
4413 vars
->phy_flags
|= PHY_XGXS_FLAG
;
4414 if ((serdes_net_if
== PORT_HW_CFG_NET_SERDES_IF_SGMII
) ||
4415 (phy
->req_line_speed
&&
4416 ((phy
->req_line_speed
== SPEED_100
) ||
4417 (phy
->req_line_speed
== SPEED_10
)))) {
4418 vars
->phy_flags
|= PHY_SGMII_FLAG
;
4419 DP(NETIF_MSG_LINK
, "Setting SGMII mode\n");
4420 bnx2x_warpcore_clear_regs(phy
, params
, lane
);
4421 bnx2x_warpcore_set_sgmii_speed(phy
, params
, 0, 1);
4423 switch (serdes_net_if
) {
4424 case PORT_HW_CFG_NET_SERDES_IF_KR
:
4425 /* Enable KR Auto Neg */
4426 if (params
->loopback_mode
!= LOOPBACK_EXT
)
4427 bnx2x_warpcore_enable_AN_KR(phy
, params
, vars
);
4429 DP(NETIF_MSG_LINK
, "Setting KR 10G-Force\n");
4430 bnx2x_warpcore_set_10G_KR(phy
, params
, vars
);
4434 case PORT_HW_CFG_NET_SERDES_IF_XFI
:
4435 bnx2x_warpcore_clear_regs(phy
, params
, lane
);
4436 if (vars
->line_speed
== SPEED_10000
) {
4437 DP(NETIF_MSG_LINK
, "Setting 10G XFI\n");
4438 bnx2x_warpcore_set_10G_XFI(phy
, params
, 1);
4440 if (SINGLE_MEDIA_DIRECT(params
)) {
4441 DP(NETIF_MSG_LINK
, "1G Fiber\n");
4444 DP(NETIF_MSG_LINK
, "10/100/1G SGMII\n");
4447 bnx2x_warpcore_set_sgmii_speed(phy
,
4455 case PORT_HW_CFG_NET_SERDES_IF_SFI
:
4456 /* Issue Module detection */
4457 if (bnx2x_is_sfp_module_plugged(phy
, params
))
4458 bnx2x_sfp_module_detection(phy
, params
);
4460 bnx2x_warpcore_config_sfi(phy
, params
);
4463 case PORT_HW_CFG_NET_SERDES_IF_DXGXS
:
4464 if (vars
->line_speed
!= SPEED_20000
) {
4465 DP(NETIF_MSG_LINK
, "Speed not supported yet\n");
4468 DP(NETIF_MSG_LINK
, "Setting 20G DXGXS\n");
4469 bnx2x_warpcore_set_20G_DXGXS(bp
, phy
, lane
);
4470 /* Issue Module detection */
4472 bnx2x_sfp_module_detection(phy
, params
);
4475 case PORT_HW_CFG_NET_SERDES_IF_KR2
:
4476 if (vars
->line_speed
!= SPEED_20000
) {
4477 DP(NETIF_MSG_LINK
, "Speed not supported yet\n");
4480 DP(NETIF_MSG_LINK
, "Setting 20G KR2\n");
4481 bnx2x_warpcore_set_20G_KR2(bp
, phy
);
4486 "Unsupported Serdes Net Interface 0x%x\n",
4492 /* Take lane out of reset after configuration is finished */
4493 bnx2x_warpcore_reset_lane(bp
, phy
, 0);
4494 DP(NETIF_MSG_LINK
, "Exit config init\n");
4497 static void bnx2x_sfp_e3_set_transmitter(struct link_params
*params
,
4498 struct bnx2x_phy
*phy
,
4501 struct bnx2x
*bp
= params
->bp
;
4503 u8 port
= params
->port
;
4505 cfg_pin
= REG_RD(bp
, params
->shmem_base
+
4506 offsetof(struct shmem_region
,
4507 dev_info
.port_hw_config
[port
].e3_sfp_ctrl
)) &
4508 PORT_HW_CFG_TX_LASER_MASK
;
4509 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
4510 DP(NETIF_MSG_LINK
, "Setting WC TX to %d\n", tx_en
);
4511 /* For 20G, the expected pin to be used is 3 pins after the current */
4513 bnx2x_set_cfg_pin(bp
, cfg_pin
, tx_en
^ 1);
4514 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
)
4515 bnx2x_set_cfg_pin(bp
, cfg_pin
+ 3, tx_en
^ 1);
4518 static void bnx2x_warpcore_link_reset(struct bnx2x_phy
*phy
,
4519 struct link_params
*params
)
4521 struct bnx2x
*bp
= params
->bp
;
4523 bnx2x_sfp_e3_set_transmitter(params
, phy
, 0);
4524 bnx2x_set_mdio_clk(bp
, params
->chip_id
, params
->port
);
4525 bnx2x_set_aer_mmd(params
, phy
);
4526 /* Global register */
4527 bnx2x_warpcore_reset_lane(bp
, phy
, 1);
4529 /* Clear loopback settings (if any) */
4531 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4532 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, &val16
);
4533 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4534 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
, val16
&
4537 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4538 MDIO_WC_REG_IEEE0BLK_MIICNTL
, &val16
);
4539 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4540 MDIO_WC_REG_IEEE0BLK_MIICNTL
, val16
& 0xfffe);
4542 /* Update those 1-copy registers */
4543 CL22_WR_OVER_CL45(bp
, phy
, MDIO_REG_BANK_AER_BLOCK
,
4544 MDIO_AER_BLOCK_AER_REG
, 0);
4545 /* Enable 1G MDIO (1-copy) */
4546 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4547 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
,
4549 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4550 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
,
4553 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4554 MDIO_WC_REG_XGXSBLK1_LANECTRL2
, &val16
);
4555 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4556 MDIO_WC_REG_XGXSBLK1_LANECTRL2
,
4561 static void bnx2x_set_warpcore_loopback(struct bnx2x_phy
*phy
,
4562 struct link_params
*params
)
4564 struct bnx2x
*bp
= params
->bp
;
4567 DP(NETIF_MSG_LINK
, "Setting Warpcore loopback type %x, speed %d\n",
4568 params
->loopback_mode
, phy
->req_line_speed
);
4570 if (phy
->req_line_speed
< SPEED_10000
) {
4573 /* Update those 1-copy registers */
4574 CL22_WR_OVER_CL45(bp
, phy
, MDIO_REG_BANK_AER_BLOCK
,
4575 MDIO_AER_BLOCK_AER_REG
, 0);
4576 /* Enable 1G MDIO (1-copy) */
4577 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
4578 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL
,
4580 /* Set 1G loopback based on lane (1-copy) */
4581 lane
= bnx2x_get_warpcore_lane(phy
, params
);
4582 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
4583 MDIO_WC_REG_XGXSBLK1_LANECTRL2
, &val16
);
4584 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
4585 MDIO_WC_REG_XGXSBLK1_LANECTRL2
,
4588 /* Switch back to 4-copy registers */
4589 bnx2x_set_aer_mmd(params
, phy
);
4592 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
4593 MDIO_WC_REG_COMBO_IEEE0_MIICTRL
,
4596 bnx2x_cl45_read_or_write(bp
, phy
, MDIO_WC_DEVAD
,
4597 MDIO_WC_REG_IEEE0BLK_MIICNTL
, 0x1);
4603 static void bnx2x_sync_link(struct link_params
*params
,
4604 struct link_vars
*vars
)
4606 struct bnx2x
*bp
= params
->bp
;
4608 if (vars
->link_status
& LINK_STATUS_PHYSICAL_LINK_FLAG
)
4609 vars
->phy_flags
|= PHY_PHYSICAL_LINK_FLAG
;
4610 vars
->link_up
= (vars
->link_status
& LINK_STATUS_LINK_UP
);
4611 if (vars
->link_up
) {
4612 DP(NETIF_MSG_LINK
, "phy link up\n");
4614 vars
->phy_link_up
= 1;
4615 vars
->duplex
= DUPLEX_FULL
;
4616 switch (vars
->link_status
&
4617 LINK_STATUS_SPEED_AND_DUPLEX_MASK
) {
4619 vars
->duplex
= DUPLEX_HALF
;
4622 vars
->line_speed
= SPEED_10
;
4626 vars
->duplex
= DUPLEX_HALF
;
4630 vars
->line_speed
= SPEED_100
;
4634 vars
->duplex
= DUPLEX_HALF
;
4637 vars
->line_speed
= SPEED_1000
;
4641 vars
->duplex
= DUPLEX_HALF
;
4644 vars
->line_speed
= SPEED_2500
;
4648 vars
->line_speed
= SPEED_10000
;
4651 vars
->line_speed
= SPEED_20000
;
4656 vars
->flow_ctrl
= 0;
4657 if (vars
->link_status
& LINK_STATUS_TX_FLOW_CONTROL_ENABLED
)
4658 vars
->flow_ctrl
|= BNX2X_FLOW_CTRL_TX
;
4660 if (vars
->link_status
& LINK_STATUS_RX_FLOW_CONTROL_ENABLED
)
4661 vars
->flow_ctrl
|= BNX2X_FLOW_CTRL_RX
;
4663 if (!vars
->flow_ctrl
)
4664 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
4666 if (vars
->line_speed
&&
4667 ((vars
->line_speed
== SPEED_10
) ||
4668 (vars
->line_speed
== SPEED_100
))) {
4669 vars
->phy_flags
|= PHY_SGMII_FLAG
;
4671 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
4673 if (vars
->line_speed
&&
4674 USES_WARPCORE(bp
) &&
4675 (vars
->line_speed
== SPEED_1000
))
4676 vars
->phy_flags
|= PHY_SGMII_FLAG
;
4677 /* Anything 10 and over uses the bmac */
4678 link_10g_plus
= (vars
->line_speed
>= SPEED_10000
);
4680 if (link_10g_plus
) {
4681 if (USES_WARPCORE(bp
))
4682 vars
->mac_type
= MAC_TYPE_XMAC
;
4684 vars
->mac_type
= MAC_TYPE_BMAC
;
4686 if (USES_WARPCORE(bp
))
4687 vars
->mac_type
= MAC_TYPE_UMAC
;
4689 vars
->mac_type
= MAC_TYPE_EMAC
;
4691 } else { /* Link down */
4692 DP(NETIF_MSG_LINK
, "phy link down\n");
4694 vars
->phy_link_up
= 0;
4696 vars
->line_speed
= 0;
4697 vars
->duplex
= DUPLEX_FULL
;
4698 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
4700 /* Indicate no mac active */
4701 vars
->mac_type
= MAC_TYPE_NONE
;
4702 if (vars
->link_status
& LINK_STATUS_PHYSICAL_LINK_FLAG
)
4703 vars
->phy_flags
|= PHY_HALF_OPEN_CONN_FLAG
;
4704 if (vars
->link_status
& LINK_STATUS_SFP_TX_FAULT
)
4705 vars
->phy_flags
|= PHY_SFP_TX_FAULT_FLAG
;
4709 void bnx2x_link_status_update(struct link_params
*params
,
4710 struct link_vars
*vars
)
4712 struct bnx2x
*bp
= params
->bp
;
4713 u8 port
= params
->port
;
4714 u32 sync_offset
, media_types
;
4715 /* Update PHY configuration */
4716 set_phy_vars(params
, vars
);
4718 vars
->link_status
= REG_RD(bp
, params
->shmem_base
+
4719 offsetof(struct shmem_region
,
4720 port_mb
[port
].link_status
));
4722 vars
->phy_flags
= PHY_XGXS_FLAG
;
4723 bnx2x_sync_link(params
, vars
);
4724 /* Sync media type */
4725 sync_offset
= params
->shmem_base
+
4726 offsetof(struct shmem_region
,
4727 dev_info
.port_hw_config
[port
].media_type
);
4728 media_types
= REG_RD(bp
, sync_offset
);
4730 params
->phy
[INT_PHY
].media_type
=
4731 (media_types
& PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
) >>
4732 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT
;
4733 params
->phy
[EXT_PHY1
].media_type
=
4734 (media_types
& PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK
) >>
4735 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
;
4736 params
->phy
[EXT_PHY2
].media_type
=
4737 (media_types
& PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK
) >>
4738 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT
;
4739 DP(NETIF_MSG_LINK
, "media_types = 0x%x\n", media_types
);
4741 /* Sync AEU offset */
4742 sync_offset
= params
->shmem_base
+
4743 offsetof(struct shmem_region
,
4744 dev_info
.port_hw_config
[port
].aeu_int_mask
);
4746 vars
->aeu_int_mask
= REG_RD(bp
, sync_offset
);
4748 /* Sync PFC status */
4749 if (vars
->link_status
& LINK_STATUS_PFC_ENABLED
)
4750 params
->feature_config_flags
|=
4751 FEATURE_CONFIG_PFC_ENABLED
;
4753 params
->feature_config_flags
&=
4754 ~FEATURE_CONFIG_PFC_ENABLED
;
4756 DP(NETIF_MSG_LINK
, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
4757 vars
->link_status
, vars
->phy_link_up
, vars
->aeu_int_mask
);
4758 DP(NETIF_MSG_LINK
, "line_speed %x duplex %x flow_ctrl 0x%x\n",
4759 vars
->line_speed
, vars
->duplex
, vars
->flow_ctrl
);
4762 static void bnx2x_set_master_ln(struct link_params
*params
,
4763 struct bnx2x_phy
*phy
)
4765 struct bnx2x
*bp
= params
->bp
;
4766 u16 new_master_ln
, ser_lane
;
4767 ser_lane
= ((params
->lane_config
&
4768 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
4769 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
4771 /* Set the master_ln for AN */
4772 CL22_RD_OVER_CL45(bp
, phy
,
4773 MDIO_REG_BANK_XGXS_BLOCK2
,
4774 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
,
4777 CL22_WR_OVER_CL45(bp
, phy
,
4778 MDIO_REG_BANK_XGXS_BLOCK2
,
4779 MDIO_XGXS_BLOCK2_TEST_MODE_LANE
,
4780 (new_master_ln
| ser_lane
));
4783 static int bnx2x_reset_unicore(struct link_params
*params
,
4784 struct bnx2x_phy
*phy
,
4787 struct bnx2x
*bp
= params
->bp
;
4790 CL22_RD_OVER_CL45(bp
, phy
,
4791 MDIO_REG_BANK_COMBO_IEEE0
,
4792 MDIO_COMBO_IEEE0_MII_CONTROL
, &mii_control
);
4794 /* Reset the unicore */
4795 CL22_WR_OVER_CL45(bp
, phy
,
4796 MDIO_REG_BANK_COMBO_IEEE0
,
4797 MDIO_COMBO_IEEE0_MII_CONTROL
,
4799 MDIO_COMBO_IEEO_MII_CONTROL_RESET
));
4801 bnx2x_set_serdes_access(bp
, params
->port
);
4803 /* Wait for the reset to self clear */
4804 for (i
= 0; i
< MDIO_ACCESS_TIMEOUT
; i
++) {
4807 /* The reset erased the previous bank value */
4808 CL22_RD_OVER_CL45(bp
, phy
,
4809 MDIO_REG_BANK_COMBO_IEEE0
,
4810 MDIO_COMBO_IEEE0_MII_CONTROL
,
4813 if (!(mii_control
& MDIO_COMBO_IEEO_MII_CONTROL_RESET
)) {
4819 netdev_err(bp
->dev
, "Warning: PHY was not initialized,"
4822 DP(NETIF_MSG_LINK
, "BUG! XGXS is still in reset!\n");
4827 static void bnx2x_set_swap_lanes(struct link_params
*params
,
4828 struct bnx2x_phy
*phy
)
4830 struct bnx2x
*bp
= params
->bp
;
4831 /* Each two bits represents a lane number:
4832 * No swap is 0123 => 0x1b no need to enable the swap
4834 u16 rx_lane_swap
, tx_lane_swap
;
4836 rx_lane_swap
= ((params
->lane_config
&
4837 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK
) >>
4838 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT
);
4839 tx_lane_swap
= ((params
->lane_config
&
4840 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK
) >>
4841 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT
);
4843 if (rx_lane_swap
!= 0x1b) {
4844 CL22_WR_OVER_CL45(bp
, phy
,
4845 MDIO_REG_BANK_XGXS_BLOCK2
,
4846 MDIO_XGXS_BLOCK2_RX_LN_SWAP
,
4848 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE
|
4849 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE
));
4851 CL22_WR_OVER_CL45(bp
, phy
,
4852 MDIO_REG_BANK_XGXS_BLOCK2
,
4853 MDIO_XGXS_BLOCK2_RX_LN_SWAP
, 0);
4856 if (tx_lane_swap
!= 0x1b) {
4857 CL22_WR_OVER_CL45(bp
, phy
,
4858 MDIO_REG_BANK_XGXS_BLOCK2
,
4859 MDIO_XGXS_BLOCK2_TX_LN_SWAP
,
4861 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE
));
4863 CL22_WR_OVER_CL45(bp
, phy
,
4864 MDIO_REG_BANK_XGXS_BLOCK2
,
4865 MDIO_XGXS_BLOCK2_TX_LN_SWAP
, 0);
4869 static void bnx2x_set_parallel_detection(struct bnx2x_phy
*phy
,
4870 struct link_params
*params
)
4872 struct bnx2x
*bp
= params
->bp
;
4874 CL22_RD_OVER_CL45(bp
, phy
,
4875 MDIO_REG_BANK_SERDES_DIGITAL
,
4876 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
,
4878 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
4879 control2
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN
;
4881 control2
&= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN
;
4882 DP(NETIF_MSG_LINK
, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
4883 phy
->speed_cap_mask
, control2
);
4884 CL22_WR_OVER_CL45(bp
, phy
,
4885 MDIO_REG_BANK_SERDES_DIGITAL
,
4886 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2
,
4889 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
4890 (phy
->speed_cap_mask
&
4891 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
4892 DP(NETIF_MSG_LINK
, "XGXS\n");
4894 CL22_WR_OVER_CL45(bp
, phy
,
4895 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4896 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK
,
4897 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT
);
4899 CL22_RD_OVER_CL45(bp
, phy
,
4900 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4901 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
4906 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN
;
4908 CL22_WR_OVER_CL45(bp
, phy
,
4909 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
4910 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL
,
4913 /* Disable parallel detection of HiG */
4914 CL22_WR_OVER_CL45(bp
, phy
,
4915 MDIO_REG_BANK_XGXS_BLOCK2
,
4916 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G
,
4917 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS
|
4918 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS
);
4922 static void bnx2x_set_autoneg(struct bnx2x_phy
*phy
,
4923 struct link_params
*params
,
4924 struct link_vars
*vars
,
4927 struct bnx2x
*bp
= params
->bp
;
4931 CL22_RD_OVER_CL45(bp
, phy
,
4932 MDIO_REG_BANK_COMBO_IEEE0
,
4933 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
4935 /* CL37 Autoneg Enabled */
4936 if (vars
->line_speed
== SPEED_AUTO_NEG
)
4937 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
;
4938 else /* CL37 Autoneg Disabled */
4939 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
4940 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
);
4942 CL22_WR_OVER_CL45(bp
, phy
,
4943 MDIO_REG_BANK_COMBO_IEEE0
,
4944 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
4946 /* Enable/Disable Autodetection */
4948 CL22_RD_OVER_CL45(bp
, phy
,
4949 MDIO_REG_BANK_SERDES_DIGITAL
,
4950 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, ®_val
);
4951 reg_val
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN
|
4952 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
);
4953 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
;
4954 if (vars
->line_speed
== SPEED_AUTO_NEG
)
4955 reg_val
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
4957 reg_val
&= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
;
4959 CL22_WR_OVER_CL45(bp
, phy
,
4960 MDIO_REG_BANK_SERDES_DIGITAL
,
4961 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
, reg_val
);
4963 /* Enable TetonII and BAM autoneg */
4964 CL22_RD_OVER_CL45(bp
, phy
,
4965 MDIO_REG_BANK_BAM_NEXT_PAGE
,
4966 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
,
4968 if (vars
->line_speed
== SPEED_AUTO_NEG
) {
4969 /* Enable BAM aneg Mode and TetonII aneg Mode */
4970 reg_val
|= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
4971 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
4973 /* TetonII and BAM Autoneg Disabled */
4974 reg_val
&= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE
|
4975 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN
);
4977 CL22_WR_OVER_CL45(bp
, phy
,
4978 MDIO_REG_BANK_BAM_NEXT_PAGE
,
4979 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL
,
4983 /* Enable Cl73 FSM status bits */
4984 CL22_WR_OVER_CL45(bp
, phy
,
4985 MDIO_REG_BANK_CL73_USERB0
,
4986 MDIO_CL73_USERB0_CL73_UCTRL
,
4989 /* Enable BAM Station Manager*/
4990 CL22_WR_OVER_CL45(bp
, phy
,
4991 MDIO_REG_BANK_CL73_USERB0
,
4992 MDIO_CL73_USERB0_CL73_BAM_CTRL1
,
4993 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN
|
4994 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN
|
4995 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN
);
4997 /* Advertise CL73 link speeds */
4998 CL22_RD_OVER_CL45(bp
, phy
,
4999 MDIO_REG_BANK_CL73_IEEEB1
,
5000 MDIO_CL73_IEEEB1_AN_ADV2
,
5002 if (phy
->speed_cap_mask
&
5003 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
5004 reg_val
|= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
;
5005 if (phy
->speed_cap_mask
&
5006 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)
5007 reg_val
|= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
;
5009 CL22_WR_OVER_CL45(bp
, phy
,
5010 MDIO_REG_BANK_CL73_IEEEB1
,
5011 MDIO_CL73_IEEEB1_AN_ADV2
,
5014 /* CL73 Autoneg Enabled */
5015 reg_val
= MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
;
5017 } else /* CL73 Autoneg Disabled */
5020 CL22_WR_OVER_CL45(bp
, phy
,
5021 MDIO_REG_BANK_CL73_IEEEB0
,
5022 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
, reg_val
);
5025 /* Program SerDes, forced speed */
5026 static void bnx2x_program_serdes(struct bnx2x_phy
*phy
,
5027 struct link_params
*params
,
5028 struct link_vars
*vars
)
5030 struct bnx2x
*bp
= params
->bp
;
5033 /* Program duplex, disable autoneg and sgmii*/
5034 CL22_RD_OVER_CL45(bp
, phy
,
5035 MDIO_REG_BANK_COMBO_IEEE0
,
5036 MDIO_COMBO_IEEE0_MII_CONTROL
, ®_val
);
5037 reg_val
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
|
5038 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
5039 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
);
5040 if (phy
->req_duplex
== DUPLEX_FULL
)
5041 reg_val
|= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
5042 CL22_WR_OVER_CL45(bp
, phy
,
5043 MDIO_REG_BANK_COMBO_IEEE0
,
5044 MDIO_COMBO_IEEE0_MII_CONTROL
, reg_val
);
5047 * - needed only if the speed is greater than 1G (2.5G or 10G)
5049 CL22_RD_OVER_CL45(bp
, phy
,
5050 MDIO_REG_BANK_SERDES_DIGITAL
,
5051 MDIO_SERDES_DIGITAL_MISC1
, ®_val
);
5052 /* Clearing the speed value before setting the right speed */
5053 DP(NETIF_MSG_LINK
, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val
);
5055 reg_val
&= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK
|
5056 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
5058 if (!((vars
->line_speed
== SPEED_1000
) ||
5059 (vars
->line_speed
== SPEED_100
) ||
5060 (vars
->line_speed
== SPEED_10
))) {
5062 reg_val
|= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M
|
5063 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL
);
5064 if (vars
->line_speed
== SPEED_10000
)
5066 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4
;
5069 CL22_WR_OVER_CL45(bp
, phy
,
5070 MDIO_REG_BANK_SERDES_DIGITAL
,
5071 MDIO_SERDES_DIGITAL_MISC1
, reg_val
);
5075 static void bnx2x_set_brcm_cl37_advertisement(struct bnx2x_phy
*phy
,
5076 struct link_params
*params
)
5078 struct bnx2x
*bp
= params
->bp
;
5081 /* Set extended capabilities */
5082 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
)
5083 val
|= MDIO_OVER_1G_UP1_2_5G
;
5084 if (phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
5085 val
|= MDIO_OVER_1G_UP1_10G
;
5086 CL22_WR_OVER_CL45(bp
, phy
,
5087 MDIO_REG_BANK_OVER_1G
,
5088 MDIO_OVER_1G_UP1
, val
);
5090 CL22_WR_OVER_CL45(bp
, phy
,
5091 MDIO_REG_BANK_OVER_1G
,
5092 MDIO_OVER_1G_UP3
, 0x400);
5095 static void bnx2x_set_ieee_aneg_advertisement(struct bnx2x_phy
*phy
,
5096 struct link_params
*params
,
5099 struct bnx2x
*bp
= params
->bp
;
5101 /* For AN, we are always publishing full duplex */
5103 CL22_WR_OVER_CL45(bp
, phy
,
5104 MDIO_REG_BANK_COMBO_IEEE0
,
5105 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
, ieee_fc
);
5106 CL22_RD_OVER_CL45(bp
, phy
,
5107 MDIO_REG_BANK_CL73_IEEEB1
,
5108 MDIO_CL73_IEEEB1_AN_ADV1
, &val
);
5109 val
&= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH
;
5110 val
|= ((ieee_fc
<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK
);
5111 CL22_WR_OVER_CL45(bp
, phy
,
5112 MDIO_REG_BANK_CL73_IEEEB1
,
5113 MDIO_CL73_IEEEB1_AN_ADV1
, val
);
5116 static void bnx2x_restart_autoneg(struct bnx2x_phy
*phy
,
5117 struct link_params
*params
,
5120 struct bnx2x
*bp
= params
->bp
;
5123 DP(NETIF_MSG_LINK
, "bnx2x_restart_autoneg\n");
5124 /* Enable and restart BAM/CL37 aneg */
5127 CL22_RD_OVER_CL45(bp
, phy
,
5128 MDIO_REG_BANK_CL73_IEEEB0
,
5129 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
5132 CL22_WR_OVER_CL45(bp
, phy
,
5133 MDIO_REG_BANK_CL73_IEEEB0
,
5134 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
5136 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
|
5137 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN
));
5140 CL22_RD_OVER_CL45(bp
, phy
,
5141 MDIO_REG_BANK_COMBO_IEEE0
,
5142 MDIO_COMBO_IEEE0_MII_CONTROL
,
5145 "bnx2x_restart_autoneg mii_control before = 0x%x\n",
5147 CL22_WR_OVER_CL45(bp
, phy
,
5148 MDIO_REG_BANK_COMBO_IEEE0
,
5149 MDIO_COMBO_IEEE0_MII_CONTROL
,
5151 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
5152 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN
));
5156 static void bnx2x_initialize_sgmii_process(struct bnx2x_phy
*phy
,
5157 struct link_params
*params
,
5158 struct link_vars
*vars
)
5160 struct bnx2x
*bp
= params
->bp
;
5163 /* In SGMII mode, the unicore is always slave */
5165 CL22_RD_OVER_CL45(bp
, phy
,
5166 MDIO_REG_BANK_SERDES_DIGITAL
,
5167 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
,
5169 control1
|= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT
;
5170 /* Set sgmii mode (and not fiber) */
5171 control1
&= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE
|
5172 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET
|
5173 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE
);
5174 CL22_WR_OVER_CL45(bp
, phy
,
5175 MDIO_REG_BANK_SERDES_DIGITAL
,
5176 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1
,
5179 /* If forced speed */
5180 if (!(vars
->line_speed
== SPEED_AUTO_NEG
)) {
5181 /* Set speed, disable autoneg */
5184 CL22_RD_OVER_CL45(bp
, phy
,
5185 MDIO_REG_BANK_COMBO_IEEE0
,
5186 MDIO_COMBO_IEEE0_MII_CONTROL
,
5188 mii_control
&= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN
|
5189 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK
|
5190 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
);
5192 switch (vars
->line_speed
) {
5195 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100
;
5199 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000
;
5202 /* There is nothing to set for 10M */
5205 /* Invalid speed for SGMII */
5206 DP(NETIF_MSG_LINK
, "Invalid line_speed 0x%x\n",
5211 /* Setting the full duplex */
5212 if (phy
->req_duplex
== DUPLEX_FULL
)
5214 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX
;
5215 CL22_WR_OVER_CL45(bp
, phy
,
5216 MDIO_REG_BANK_COMBO_IEEE0
,
5217 MDIO_COMBO_IEEE0_MII_CONTROL
,
5220 } else { /* AN mode */
5221 /* Enable and restart AN */
5222 bnx2x_restart_autoneg(phy
, params
, 0);
5228 static int bnx2x_direct_parallel_detect_used(struct bnx2x_phy
*phy
,
5229 struct link_params
*params
)
5231 struct bnx2x
*bp
= params
->bp
;
5232 u16 pd_10g
, status2_1000x
;
5233 if (phy
->req_line_speed
!= SPEED_AUTO_NEG
)
5235 CL22_RD_OVER_CL45(bp
, phy
,
5236 MDIO_REG_BANK_SERDES_DIGITAL
,
5237 MDIO_SERDES_DIGITAL_A_1000X_STATUS2
,
5239 CL22_RD_OVER_CL45(bp
, phy
,
5240 MDIO_REG_BANK_SERDES_DIGITAL
,
5241 MDIO_SERDES_DIGITAL_A_1000X_STATUS2
,
5243 if (status2_1000x
& MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED
) {
5244 DP(NETIF_MSG_LINK
, "1G parallel detect link on port %d\n",
5249 CL22_RD_OVER_CL45(bp
, phy
,
5250 MDIO_REG_BANK_10G_PARALLEL_DETECT
,
5251 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS
,
5254 if (pd_10g
& MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK
) {
5255 DP(NETIF_MSG_LINK
, "10G parallel detect link on port %d\n",
5262 static void bnx2x_update_adv_fc(struct bnx2x_phy
*phy
,
5263 struct link_params
*params
,
5264 struct link_vars
*vars
,
5267 u16 ld_pause
; /* local driver */
5268 u16 lp_pause
; /* link partner */
5270 struct bnx2x
*bp
= params
->bp
;
5272 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE
|
5273 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE
)) ==
5274 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE
|
5275 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE
)) {
5277 CL22_RD_OVER_CL45(bp
, phy
,
5278 MDIO_REG_BANK_CL73_IEEEB1
,
5279 MDIO_CL73_IEEEB1_AN_ADV1
,
5281 CL22_RD_OVER_CL45(bp
, phy
,
5282 MDIO_REG_BANK_CL73_IEEEB1
,
5283 MDIO_CL73_IEEEB1_AN_LP_ADV1
,
5285 pause_result
= (ld_pause
&
5286 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK
) >> 8;
5287 pause_result
|= (lp_pause
&
5288 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK
) >> 10;
5289 DP(NETIF_MSG_LINK
, "pause_result CL73 0x%x\n", pause_result
);
5291 CL22_RD_OVER_CL45(bp
, phy
,
5292 MDIO_REG_BANK_COMBO_IEEE0
,
5293 MDIO_COMBO_IEEE0_AUTO_NEG_ADV
,
5295 CL22_RD_OVER_CL45(bp
, phy
,
5296 MDIO_REG_BANK_COMBO_IEEE0
,
5297 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1
,
5299 pause_result
= (ld_pause
&
5300 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
)>>5;
5301 pause_result
|= (lp_pause
&
5302 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
)>>7;
5303 DP(NETIF_MSG_LINK
, "pause_result CL37 0x%x\n", pause_result
);
5305 bnx2x_pause_resolve(vars
, pause_result
);
5309 static void bnx2x_flow_ctrl_resolve(struct bnx2x_phy
*phy
,
5310 struct link_params
*params
,
5311 struct link_vars
*vars
,
5314 struct bnx2x
*bp
= params
->bp
;
5315 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
5317 /* Resolve from gp_status in case of AN complete and not sgmii */
5318 if (phy
->req_flow_ctrl
!= BNX2X_FLOW_CTRL_AUTO
) {
5319 /* Update the advertised flow-controled of LD/LP in AN */
5320 if (phy
->req_line_speed
== SPEED_AUTO_NEG
)
5321 bnx2x_update_adv_fc(phy
, params
, vars
, gp_status
);
5322 /* But set the flow-control result as the requested one */
5323 vars
->flow_ctrl
= phy
->req_flow_ctrl
;
5324 } else if (phy
->req_line_speed
!= SPEED_AUTO_NEG
)
5325 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
5326 else if ((gp_status
& MDIO_AN_CL73_OR_37_COMPLETE
) &&
5327 (!(vars
->phy_flags
& PHY_SGMII_FLAG
))) {
5328 if (bnx2x_direct_parallel_detect_used(phy
, params
)) {
5329 vars
->flow_ctrl
= params
->req_fc_auto_adv
;
5332 bnx2x_update_adv_fc(phy
, params
, vars
, gp_status
);
5334 DP(NETIF_MSG_LINK
, "flow_ctrl 0x%x\n", vars
->flow_ctrl
);
5337 static void bnx2x_check_fallback_to_cl37(struct bnx2x_phy
*phy
,
5338 struct link_params
*params
)
5340 struct bnx2x
*bp
= params
->bp
;
5341 u16 rx_status
, ustat_val
, cl37_fsm_received
;
5342 DP(NETIF_MSG_LINK
, "bnx2x_check_fallback_to_cl37\n");
5343 /* Step 1: Make sure signal is detected */
5344 CL22_RD_OVER_CL45(bp
, phy
,
5348 if ((rx_status
& MDIO_RX0_RX_STATUS_SIGDET
) !=
5349 (MDIO_RX0_RX_STATUS_SIGDET
)) {
5350 DP(NETIF_MSG_LINK
, "Signal is not detected. Restoring CL73."
5351 "rx_status(0x80b0) = 0x%x\n", rx_status
);
5352 CL22_WR_OVER_CL45(bp
, phy
,
5353 MDIO_REG_BANK_CL73_IEEEB0
,
5354 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
5355 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN
);
5358 /* Step 2: Check CL73 state machine */
5359 CL22_RD_OVER_CL45(bp
, phy
,
5360 MDIO_REG_BANK_CL73_USERB0
,
5361 MDIO_CL73_USERB0_CL73_USTAT1
,
5364 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
5365 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) !=
5366 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK
|
5367 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37
)) {
5368 DP(NETIF_MSG_LINK
, "CL73 state-machine is not stable. "
5369 "ustat_val(0x8371) = 0x%x\n", ustat_val
);
5372 /* Step 3: Check CL37 Message Pages received to indicate LP
5373 * supports only CL37
5375 CL22_RD_OVER_CL45(bp
, phy
,
5376 MDIO_REG_BANK_REMOTE_PHY
,
5377 MDIO_REMOTE_PHY_MISC_RX_STATUS
,
5378 &cl37_fsm_received
);
5379 if ((cl37_fsm_received
&
5380 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
5381 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) !=
5382 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG
|
5383 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG
)) {
5384 DP(NETIF_MSG_LINK
, "No CL37 FSM were received. "
5385 "misc_rx_status(0x8330) = 0x%x\n",
5389 /* The combined cl37/cl73 fsm state information indicating that
5390 * we are connected to a device which does not support cl73, but
5391 * does support cl37 BAM. In this case we disable cl73 and
5392 * restart cl37 auto-neg
5396 CL22_WR_OVER_CL45(bp
, phy
,
5397 MDIO_REG_BANK_CL73_IEEEB0
,
5398 MDIO_CL73_IEEEB0_CL73_AN_CONTROL
,
5400 /* Restart CL37 autoneg */
5401 bnx2x_restart_autoneg(phy
, params
, 0);
5402 DP(NETIF_MSG_LINK
, "Disabling CL73, and restarting CL37 autoneg\n");
5405 static void bnx2x_xgxs_an_resolve(struct bnx2x_phy
*phy
,
5406 struct link_params
*params
,
5407 struct link_vars
*vars
,
5410 if (gp_status
& MDIO_AN_CL73_OR_37_COMPLETE
)
5411 vars
->link_status
|=
5412 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
5414 if (bnx2x_direct_parallel_detect_used(phy
, params
))
5415 vars
->link_status
|=
5416 LINK_STATUS_PARALLEL_DETECTION_USED
;
5418 static int bnx2x_get_link_speed_duplex(struct bnx2x_phy
*phy
,
5419 struct link_params
*params
,
5420 struct link_vars
*vars
,
5425 struct bnx2x
*bp
= params
->bp
;
5426 if (phy
->req_line_speed
== SPEED_AUTO_NEG
)
5427 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_ENABLED
;
5429 DP(NETIF_MSG_LINK
, "phy link up\n");
5431 vars
->phy_link_up
= 1;
5432 vars
->link_status
|= LINK_STATUS_LINK_UP
;
5434 switch (speed_mask
) {
5436 vars
->line_speed
= SPEED_10
;
5437 if (is_duplex
== DUPLEX_FULL
)
5438 vars
->link_status
|= LINK_10TFD
;
5440 vars
->link_status
|= LINK_10THD
;
5443 case GP_STATUS_100M
:
5444 vars
->line_speed
= SPEED_100
;
5445 if (is_duplex
== DUPLEX_FULL
)
5446 vars
->link_status
|= LINK_100TXFD
;
5448 vars
->link_status
|= LINK_100TXHD
;
5452 case GP_STATUS_1G_KX
:
5453 vars
->line_speed
= SPEED_1000
;
5454 if (is_duplex
== DUPLEX_FULL
)
5455 vars
->link_status
|= LINK_1000TFD
;
5457 vars
->link_status
|= LINK_1000THD
;
5460 case GP_STATUS_2_5G
:
5461 vars
->line_speed
= SPEED_2500
;
5462 if (is_duplex
== DUPLEX_FULL
)
5463 vars
->link_status
|= LINK_2500TFD
;
5465 vars
->link_status
|= LINK_2500THD
;
5471 "link speed unsupported gp_status 0x%x\n",
5475 case GP_STATUS_10G_KX4
:
5476 case GP_STATUS_10G_HIG
:
5477 case GP_STATUS_10G_CX4
:
5478 case GP_STATUS_10G_KR
:
5479 case GP_STATUS_10G_SFI
:
5480 case GP_STATUS_10G_XFI
:
5481 vars
->line_speed
= SPEED_10000
;
5482 vars
->link_status
|= LINK_10GTFD
;
5484 case GP_STATUS_20G_DXGXS
:
5485 vars
->line_speed
= SPEED_20000
;
5486 vars
->link_status
|= LINK_20GTFD
;
5490 "link speed unsupported gp_status 0x%x\n",
5494 } else { /* link_down */
5495 DP(NETIF_MSG_LINK
, "phy link down\n");
5497 vars
->phy_link_up
= 0;
5499 vars
->duplex
= DUPLEX_FULL
;
5500 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
5501 vars
->mac_type
= MAC_TYPE_NONE
;
5503 DP(NETIF_MSG_LINK
, " phy_link_up %x line_speed %d\n",
5504 vars
->phy_link_up
, vars
->line_speed
);
5508 static int bnx2x_link_settings_status(struct bnx2x_phy
*phy
,
5509 struct link_params
*params
,
5510 struct link_vars
*vars
)
5512 struct bnx2x
*bp
= params
->bp
;
5514 u16 gp_status
, duplex
= DUPLEX_HALF
, link_up
= 0, speed_mask
;
5517 /* Read gp_status */
5518 CL22_RD_OVER_CL45(bp
, phy
,
5519 MDIO_REG_BANK_GP_STATUS
,
5520 MDIO_GP_STATUS_TOP_AN_STATUS1
,
5522 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS
)
5523 duplex
= DUPLEX_FULL
;
5524 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
)
5526 speed_mask
= gp_status
& GP_STATUS_SPEED_MASK
;
5527 DP(NETIF_MSG_LINK
, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
5528 gp_status
, link_up
, speed_mask
);
5529 rc
= bnx2x_get_link_speed_duplex(phy
, params
, vars
, link_up
, speed_mask
,
5534 if (gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
) {
5535 if (SINGLE_MEDIA_DIRECT(params
)) {
5536 vars
->duplex
= duplex
;
5537 bnx2x_flow_ctrl_resolve(phy
, params
, vars
, gp_status
);
5538 if (phy
->req_line_speed
== SPEED_AUTO_NEG
)
5539 bnx2x_xgxs_an_resolve(phy
, params
, vars
,
5542 } else { /* Link_down */
5543 if ((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
5544 SINGLE_MEDIA_DIRECT(params
)) {
5545 /* Check signal is detected */
5546 bnx2x_check_fallback_to_cl37(phy
, params
);
5550 /* Read LP advertised speeds*/
5551 if (SINGLE_MEDIA_DIRECT(params
) &&
5552 (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
)) {
5555 CL22_RD_OVER_CL45(bp
, phy
, MDIO_REG_BANK_CL73_IEEEB1
,
5556 MDIO_CL73_IEEEB1_AN_LP_ADV2
, &val
);
5558 if (val
& MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
)
5559 vars
->link_status
|=
5560 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
5561 if (val
& (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
|
5562 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR
))
5563 vars
->link_status
|=
5564 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5566 CL22_RD_OVER_CL45(bp
, phy
, MDIO_REG_BANK_OVER_1G
,
5567 MDIO_OVER_1G_LP_UP1
, &val
);
5569 if (val
& MDIO_OVER_1G_UP1_2_5G
)
5570 vars
->link_status
|=
5571 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE
;
5572 if (val
& (MDIO_OVER_1G_UP1_10G
| MDIO_OVER_1G_UP1_10GH
))
5573 vars
->link_status
|=
5574 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5577 DP(NETIF_MSG_LINK
, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5578 vars
->duplex
, vars
->flow_ctrl
, vars
->link_status
);
5582 static int bnx2x_warpcore_read_status(struct bnx2x_phy
*phy
,
5583 struct link_params
*params
,
5584 struct link_vars
*vars
)
5586 struct bnx2x
*bp
= params
->bp
;
5588 u16 gp_status1
, gp_speed
, link_up
, duplex
= DUPLEX_FULL
;
5590 lane
= bnx2x_get_warpcore_lane(phy
, params
);
5591 /* Read gp_status */
5592 if (phy
->req_line_speed
> SPEED_10000
) {
5594 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
5596 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
5598 DP(NETIF_MSG_LINK
, "PCS RX link status = 0x%x-->0x%x\n",
5599 temp_link_up
, link_up
);
5602 bnx2x_ext_phy_resolve_fc(phy
, params
, vars
);
5604 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
5605 MDIO_WC_REG_GP2_STATUS_GP_2_1
, &gp_status1
);
5606 DP(NETIF_MSG_LINK
, "0x81d1 = 0x%x\n", gp_status1
);
5607 /* Check for either KR or generic link up. */
5608 gp_status1
= ((gp_status1
>> 8) & 0xf) |
5609 ((gp_status1
>> 12) & 0xf);
5610 link_up
= gp_status1
& (1 << lane
);
5611 if (link_up
&& SINGLE_MEDIA_DIRECT(params
)) {
5613 if (phy
->req_line_speed
== SPEED_AUTO_NEG
) {
5614 /* Check Autoneg complete */
5615 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
5616 MDIO_WC_REG_GP2_STATUS_GP_2_4
,
5618 if (gp_status4
& ((1<<12)<<lane
))
5619 vars
->link_status
|=
5620 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
5622 /* Check parallel detect used */
5623 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
5624 MDIO_WC_REG_PAR_DET_10G_STATUS
,
5627 vars
->link_status
|=
5628 LINK_STATUS_PARALLEL_DETECTION_USED
;
5630 bnx2x_ext_phy_resolve_fc(phy
, params
, vars
);
5631 vars
->duplex
= duplex
;
5635 if ((vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) &&
5636 SINGLE_MEDIA_DIRECT(params
)) {
5639 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
5640 MDIO_AN_REG_LP_AUTO_NEG2
, &val
);
5642 if (val
& MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX
)
5643 vars
->link_status
|=
5644 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
5645 if (val
& (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4
|
5646 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR
))
5647 vars
->link_status
|=
5648 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5650 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
5651 MDIO_WC_REG_DIGITAL3_LP_UP1
, &val
);
5653 if (val
& MDIO_OVER_1G_UP1_2_5G
)
5654 vars
->link_status
|=
5655 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE
;
5656 if (val
& (MDIO_OVER_1G_UP1_10G
| MDIO_OVER_1G_UP1_10GH
))
5657 vars
->link_status
|=
5658 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
5664 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
5665 MDIO_WC_REG_GP2_STATUS_GP_2_2
, &gp_speed
);
5667 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
5668 MDIO_WC_REG_GP2_STATUS_GP_2_3
, &gp_speed
);
5670 DP(NETIF_MSG_LINK
, "lane %d gp_speed 0x%x\n", lane
, gp_speed
);
5672 if ((lane
& 1) == 0)
5677 rc
= bnx2x_get_link_speed_duplex(phy
, params
, vars
, link_up
, gp_speed
,
5680 DP(NETIF_MSG_LINK
, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
5681 vars
->duplex
, vars
->flow_ctrl
, vars
->link_status
);
5684 static void bnx2x_set_gmii_tx_driver(struct link_params
*params
)
5686 struct bnx2x
*bp
= params
->bp
;
5687 struct bnx2x_phy
*phy
= ¶ms
->phy
[INT_PHY
];
5693 CL22_RD_OVER_CL45(bp
, phy
,
5694 MDIO_REG_BANK_OVER_1G
,
5695 MDIO_OVER_1G_LP_UP2
, &lp_up2
);
5697 /* Bits [10:7] at lp_up2, positioned at [15:12] */
5698 lp_up2
= (((lp_up2
& MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK
) >>
5699 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT
) <<
5700 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT
);
5705 for (bank
= MDIO_REG_BANK_TX0
; bank
<= MDIO_REG_BANK_TX3
;
5706 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
)) {
5707 CL22_RD_OVER_CL45(bp
, phy
,
5709 MDIO_TX0_TX_DRIVER
, &tx_driver
);
5711 /* Replace tx_driver bits [15:12] */
5713 (tx_driver
& MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
)) {
5714 tx_driver
&= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK
;
5715 tx_driver
|= lp_up2
;
5716 CL22_WR_OVER_CL45(bp
, phy
,
5718 MDIO_TX0_TX_DRIVER
, tx_driver
);
5723 static int bnx2x_emac_program(struct link_params
*params
,
5724 struct link_vars
*vars
)
5726 struct bnx2x
*bp
= params
->bp
;
5727 u8 port
= params
->port
;
5730 DP(NETIF_MSG_LINK
, "setting link speed & duplex\n");
5731 bnx2x_bits_dis(bp
, GRCBASE_EMAC0
+ port
*0x400 +
5733 (EMAC_MODE_25G_MODE
|
5734 EMAC_MODE_PORT_MII_10M
|
5735 EMAC_MODE_HALF_DUPLEX
));
5736 switch (vars
->line_speed
) {
5738 mode
|= EMAC_MODE_PORT_MII_10M
;
5742 mode
|= EMAC_MODE_PORT_MII
;
5746 mode
|= EMAC_MODE_PORT_GMII
;
5750 mode
|= (EMAC_MODE_25G_MODE
| EMAC_MODE_PORT_GMII
);
5754 /* 10G not valid for EMAC */
5755 DP(NETIF_MSG_LINK
, "Invalid line_speed 0x%x\n",
5760 if (vars
->duplex
== DUPLEX_HALF
)
5761 mode
|= EMAC_MODE_HALF_DUPLEX
;
5763 GRCBASE_EMAC0
+ port
*0x400 + EMAC_REG_EMAC_MODE
,
5766 bnx2x_set_led(params
, vars
, LED_MODE_OPER
, vars
->line_speed
);
5770 static void bnx2x_set_preemphasis(struct bnx2x_phy
*phy
,
5771 struct link_params
*params
)
5775 struct bnx2x
*bp
= params
->bp
;
5777 for (bank
= MDIO_REG_BANK_RX0
, i
= 0; bank
<= MDIO_REG_BANK_RX3
;
5778 bank
+= (MDIO_REG_BANK_RX1
-MDIO_REG_BANK_RX0
), i
++) {
5779 CL22_WR_OVER_CL45(bp
, phy
,
5781 MDIO_RX0_RX_EQ_BOOST
,
5782 phy
->rx_preemphasis
[i
]);
5785 for (bank
= MDIO_REG_BANK_TX0
, i
= 0; bank
<= MDIO_REG_BANK_TX3
;
5786 bank
+= (MDIO_REG_BANK_TX1
- MDIO_REG_BANK_TX0
), i
++) {
5787 CL22_WR_OVER_CL45(bp
, phy
,
5790 phy
->tx_preemphasis
[i
]);
5794 static void bnx2x_xgxs_config_init(struct bnx2x_phy
*phy
,
5795 struct link_params
*params
,
5796 struct link_vars
*vars
)
5798 struct bnx2x
*bp
= params
->bp
;
5799 u8 enable_cl73
= (SINGLE_MEDIA_DIRECT(params
) ||
5800 (params
->loopback_mode
== LOOPBACK_XGXS
));
5801 if (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) {
5802 if (SINGLE_MEDIA_DIRECT(params
) &&
5803 (params
->feature_config_flags
&
5804 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
))
5805 bnx2x_set_preemphasis(phy
, params
);
5807 /* Forced speed requested? */
5808 if (vars
->line_speed
!= SPEED_AUTO_NEG
||
5809 (SINGLE_MEDIA_DIRECT(params
) &&
5810 params
->loopback_mode
== LOOPBACK_EXT
)) {
5811 DP(NETIF_MSG_LINK
, "not SGMII, no AN\n");
5813 /* Disable autoneg */
5814 bnx2x_set_autoneg(phy
, params
, vars
, 0);
5816 /* Program speed and duplex */
5817 bnx2x_program_serdes(phy
, params
, vars
);
5819 } else { /* AN_mode */
5820 DP(NETIF_MSG_LINK
, "not SGMII, AN\n");
5823 bnx2x_set_brcm_cl37_advertisement(phy
, params
);
5825 /* Program duplex & pause advertisement (for aneg) */
5826 bnx2x_set_ieee_aneg_advertisement(phy
, params
,
5829 /* Enable autoneg */
5830 bnx2x_set_autoneg(phy
, params
, vars
, enable_cl73
);
5832 /* Enable and restart AN */
5833 bnx2x_restart_autoneg(phy
, params
, enable_cl73
);
5836 } else { /* SGMII mode */
5837 DP(NETIF_MSG_LINK
, "SGMII\n");
5839 bnx2x_initialize_sgmii_process(phy
, params
, vars
);
5843 static int bnx2x_prepare_xgxs(struct bnx2x_phy
*phy
,
5844 struct link_params
*params
,
5845 struct link_vars
*vars
)
5848 vars
->phy_flags
|= PHY_XGXS_FLAG
;
5849 if ((phy
->req_line_speed
&&
5850 ((phy
->req_line_speed
== SPEED_100
) ||
5851 (phy
->req_line_speed
== SPEED_10
))) ||
5852 (!phy
->req_line_speed
&&
5853 (phy
->speed_cap_mask
>=
5854 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
) &&
5855 (phy
->speed_cap_mask
<
5856 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
5857 (phy
->type
== PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD
))
5858 vars
->phy_flags
|= PHY_SGMII_FLAG
;
5860 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
5862 bnx2x_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
5863 bnx2x_set_aer_mmd(params
, phy
);
5864 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
5865 bnx2x_set_master_ln(params
, phy
);
5867 rc
= bnx2x_reset_unicore(params
, phy
, 0);
5868 /* Reset the SerDes and wait for reset bit return low */
5872 bnx2x_set_aer_mmd(params
, phy
);
5873 /* Setting the masterLn_def again after the reset */
5874 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) {
5875 bnx2x_set_master_ln(params
, phy
);
5876 bnx2x_set_swap_lanes(params
, phy
);
5882 static u16
bnx2x_wait_reset_complete(struct bnx2x
*bp
,
5883 struct bnx2x_phy
*phy
,
5884 struct link_params
*params
)
5887 /* Wait for soft reset to get cleared up to 1 sec */
5888 for (cnt
= 0; cnt
< 1000; cnt
++) {
5889 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE
)
5890 bnx2x_cl22_read(bp
, phy
,
5891 MDIO_PMA_REG_CTRL
, &ctrl
);
5893 bnx2x_cl45_read(bp
, phy
,
5895 MDIO_PMA_REG_CTRL
, &ctrl
);
5896 if (!(ctrl
& (1<<15)))
5898 usleep_range(1000, 2000);
5902 netdev_err(bp
->dev
, "Warning: PHY was not initialized,"
5905 DP(NETIF_MSG_LINK
, "control reg 0x%x (after %d ms)\n", ctrl
, cnt
);
5909 static void bnx2x_link_int_enable(struct link_params
*params
)
5911 u8 port
= params
->port
;
5913 struct bnx2x
*bp
= params
->bp
;
5915 /* Setting the status to report on link up for either XGXS or SerDes */
5916 if (CHIP_IS_E3(bp
)) {
5917 mask
= NIG_MASK_XGXS0_LINK_STATUS
;
5918 if (!(SINGLE_MEDIA_DIRECT(params
)))
5919 mask
|= NIG_MASK_MI_INT
;
5920 } else if (params
->switch_cfg
== SWITCH_CFG_10G
) {
5921 mask
= (NIG_MASK_XGXS0_LINK10G
|
5922 NIG_MASK_XGXS0_LINK_STATUS
);
5923 DP(NETIF_MSG_LINK
, "enabled XGXS interrupt\n");
5924 if (!(SINGLE_MEDIA_DIRECT(params
)) &&
5925 params
->phy
[INT_PHY
].type
!=
5926 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) {
5927 mask
|= NIG_MASK_MI_INT
;
5928 DP(NETIF_MSG_LINK
, "enabled external phy int\n");
5931 } else { /* SerDes */
5932 mask
= NIG_MASK_SERDES0_LINK_STATUS
;
5933 DP(NETIF_MSG_LINK
, "enabled SerDes interrupt\n");
5934 if (!(SINGLE_MEDIA_DIRECT(params
)) &&
5935 params
->phy
[INT_PHY
].type
!=
5936 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN
) {
5937 mask
|= NIG_MASK_MI_INT
;
5938 DP(NETIF_MSG_LINK
, "enabled external phy int\n");
5942 NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
5945 DP(NETIF_MSG_LINK
, "port %x, is_xgxs %x, int_status 0x%x\n", port
,
5946 (params
->switch_cfg
== SWITCH_CFG_10G
),
5947 REG_RD(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4));
5948 DP(NETIF_MSG_LINK
, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
5949 REG_RD(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4),
5950 REG_RD(bp
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+ port
*0x18),
5951 REG_RD(bp
, NIG_REG_SERDES0_STATUS_LINK_STATUS
+port
*0x3c));
5952 DP(NETIF_MSG_LINK
, " 10G %x, XGXS_LINK %x\n",
5953 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
*0x68),
5954 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
*0x68));
5957 static void bnx2x_rearm_latch_signal(struct bnx2x
*bp
, u8 port
,
5960 u32 latch_status
= 0;
5962 /* Disable the MI INT ( external phy int ) by writing 1 to the
5963 * status register. Link down indication is high-active-signal,
5964 * so in this case we need to write the status to clear the XOR
5966 /* Read Latched signals */
5967 latch_status
= REG_RD(bp
,
5968 NIG_REG_LATCH_STATUS_0
+ port
*8);
5969 DP(NETIF_MSG_LINK
, "latch_status = 0x%x\n", latch_status
);
5970 /* Handle only those with latched-signal=up.*/
5973 NIG_REG_STATUS_INTERRUPT_PORT0
5975 NIG_STATUS_EMAC0_MI_INT
);
5978 NIG_REG_STATUS_INTERRUPT_PORT0
5980 NIG_STATUS_EMAC0_MI_INT
);
5982 if (latch_status
& 1) {
5984 /* For all latched-signal=up : Re-Arm Latch signals */
5985 REG_WR(bp
, NIG_REG_LATCH_STATUS_0
+ port
*8,
5986 (latch_status
& 0xfffe) | (latch_status
& 1));
5988 /* For all latched-signal=up,Write original_signal to status */
5991 static void bnx2x_link_int_ack(struct link_params
*params
,
5992 struct link_vars
*vars
, u8 is_10g_plus
)
5994 struct bnx2x
*bp
= params
->bp
;
5995 u8 port
= params
->port
;
5997 /* First reset all status we assume only one line will be
6000 bnx2x_bits_dis(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
6001 (NIG_STATUS_XGXS0_LINK10G
|
6002 NIG_STATUS_XGXS0_LINK_STATUS
|
6003 NIG_STATUS_SERDES0_LINK_STATUS
));
6004 if (vars
->phy_link_up
) {
6005 if (USES_WARPCORE(bp
))
6006 mask
= NIG_STATUS_XGXS0_LINK_STATUS
;
6009 mask
= NIG_STATUS_XGXS0_LINK10G
;
6010 else if (params
->switch_cfg
== SWITCH_CFG_10G
) {
6011 /* Disable the link interrupt by writing 1 to
6012 * the relevant lane in the status register
6015 ((params
->lane_config
&
6016 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK
) >>
6017 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT
);
6018 mask
= ((1 << ser_lane
) <<
6019 NIG_STATUS_XGXS0_LINK_STATUS_SIZE
);
6021 mask
= NIG_STATUS_SERDES0_LINK_STATUS
;
6023 DP(NETIF_MSG_LINK
, "Ack link up interrupt with mask 0x%x\n",
6026 NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4,
6031 static int bnx2x_format_ver(u32 num
, u8
*str
, u16
*len
)
6034 u32 mask
= 0xf0000000;
6037 u8 remove_leading_zeros
= 1;
6039 /* Need more than 10chars for this format */
6047 digit
= ((num
& mask
) >> shift
);
6048 if (digit
== 0 && remove_leading_zeros
) {
6051 } else if (digit
< 0xa)
6052 *str_ptr
= digit
+ '0';
6054 *str_ptr
= digit
- 0xa + 'a';
6055 remove_leading_zeros
= 0;
6063 remove_leading_zeros
= 1;
6070 static int bnx2x_null_format_ver(u32 spirom_ver
, u8
*str
, u16
*len
)
6077 int bnx2x_get_ext_phy_fw_version(struct link_params
*params
, u8
*version
,
6083 u8
*ver_p
= version
;
6084 u16 remain_len
= len
;
6085 if (version
== NULL
|| params
== NULL
)
6089 /* Extract first external phy*/
6091 spirom_ver
= REG_RD(bp
, params
->phy
[EXT_PHY1
].ver_addr
);
6093 if (params
->phy
[EXT_PHY1
].format_fw_ver
) {
6094 status
|= params
->phy
[EXT_PHY1
].format_fw_ver(spirom_ver
,
6097 ver_p
+= (len
- remain_len
);
6099 if ((params
->num_phys
== MAX_PHYS
) &&
6100 (params
->phy
[EXT_PHY2
].ver_addr
!= 0)) {
6101 spirom_ver
= REG_RD(bp
, params
->phy
[EXT_PHY2
].ver_addr
);
6102 if (params
->phy
[EXT_PHY2
].format_fw_ver
) {
6106 status
|= params
->phy
[EXT_PHY2
].format_fw_ver(
6110 ver_p
= version
+ (len
- remain_len
);
6117 static void bnx2x_set_xgxs_loopback(struct bnx2x_phy
*phy
,
6118 struct link_params
*params
)
6120 u8 port
= params
->port
;
6121 struct bnx2x
*bp
= params
->bp
;
6123 if (phy
->req_line_speed
!= SPEED_1000
) {
6126 DP(NETIF_MSG_LINK
, "XGXS 10G loopback enable\n");
6128 if (!CHIP_IS_E3(bp
)) {
6129 /* Change the uni_phy_addr in the nig */
6130 md_devad
= REG_RD(bp
, (NIG_REG_XGXS0_CTRL_MD_DEVAD
+
6133 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
*0x18,
6137 bnx2x_cl45_write(bp
, phy
,
6139 (MDIO_REG_BANK_AER_BLOCK
+
6140 (MDIO_AER_BLOCK_AER_REG
& 0xf)),
6143 bnx2x_cl45_write(bp
, phy
,
6145 (MDIO_REG_BANK_CL73_IEEEB0
+
6146 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL
& 0xf)),
6149 /* Set aer mmd back */
6150 bnx2x_set_aer_mmd(params
, phy
);
6152 if (!CHIP_IS_E3(bp
)) {
6154 REG_WR(bp
, NIG_REG_XGXS0_CTRL_MD_DEVAD
+ port
*0x18,
6159 DP(NETIF_MSG_LINK
, "XGXS 1G loopback enable\n");
6160 bnx2x_cl45_read(bp
, phy
, 5,
6161 (MDIO_REG_BANK_COMBO_IEEE0
+
6162 (MDIO_COMBO_IEEE0_MII_CONTROL
& 0xf)),
6164 bnx2x_cl45_write(bp
, phy
, 5,
6165 (MDIO_REG_BANK_COMBO_IEEE0
+
6166 (MDIO_COMBO_IEEE0_MII_CONTROL
& 0xf)),
6168 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK
);
6172 int bnx2x_set_led(struct link_params
*params
,
6173 struct link_vars
*vars
, u8 mode
, u32 speed
)
6175 u8 port
= params
->port
;
6176 u16 hw_led_mode
= params
->hw_led_mode
;
6180 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
6181 struct bnx2x
*bp
= params
->bp
;
6182 DP(NETIF_MSG_LINK
, "bnx2x_set_led: port %x, mode %d\n", port
, mode
);
6183 DP(NETIF_MSG_LINK
, "speed 0x%x, hw_led_mode 0x%x\n",
6184 speed
, hw_led_mode
);
6186 for (phy_idx
= EXT_PHY1
; phy_idx
< MAX_PHYS
; phy_idx
++) {
6187 if (params
->phy
[phy_idx
].set_link_led
) {
6188 params
->phy
[phy_idx
].set_link_led(
6189 ¶ms
->phy
[phy_idx
], params
, mode
);
6194 case LED_MODE_FRONT_PANEL_OFF
:
6196 REG_WR(bp
, NIG_REG_LED_10G_P0
+ port
*4, 0);
6197 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4,
6198 SHARED_HW_CFG_LED_MAC1
);
6200 tmp
= EMAC_RD(bp
, EMAC_REG_EMAC_LED
);
6201 if (params
->phy
[EXT_PHY1
].type
==
6202 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE
)
6203 tmp
&= ~(EMAC_LED_1000MB_OVERRIDE
|
6204 EMAC_LED_100MB_OVERRIDE
|
6205 EMAC_LED_10MB_OVERRIDE
);
6207 tmp
|= EMAC_LED_OVERRIDE
;
6209 EMAC_WR(bp
, EMAC_REG_EMAC_LED
, tmp
);
6213 /* For all other phys, OPER mode is same as ON, so in case
6214 * link is down, do nothing
6219 if (((params
->phy
[EXT_PHY1
].type
==
6220 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
) ||
6221 (params
->phy
[EXT_PHY1
].type
==
6222 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722
)) &&
6223 CHIP_IS_E2(bp
) && params
->num_phys
== 2) {
6224 /* This is a work-around for E2+8727 Configurations */
6225 if (mode
== LED_MODE_ON
||
6226 speed
== SPEED_10000
){
6227 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4, 0);
6228 REG_WR(bp
, NIG_REG_LED_10G_P0
+ port
*4, 1);
6230 tmp
= EMAC_RD(bp
, EMAC_REG_EMAC_LED
);
6231 EMAC_WR(bp
, EMAC_REG_EMAC_LED
,
6232 (tmp
| EMAC_LED_OVERRIDE
));
6233 /* Return here without enabling traffic
6234 * LED blink and setting rate in ON mode.
6235 * In oper mode, enabling LED blink
6236 * and setting rate is needed.
6238 if (mode
== LED_MODE_ON
)
6241 } else if (SINGLE_MEDIA_DIRECT(params
)) {
6242 /* This is a work-around for HW issue found when link
6245 if ((!CHIP_IS_E3(bp
)) ||
6247 mode
== LED_MODE_ON
))
6248 REG_WR(bp
, NIG_REG_LED_10G_P0
+ port
*4, 1);
6250 if (CHIP_IS_E1x(bp
) ||
6252 (mode
== LED_MODE_ON
))
6253 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4, 0);
6255 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4,
6257 } else if ((params
->phy
[EXT_PHY1
].type
==
6258 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE
) &&
6259 (mode
== LED_MODE_ON
)) {
6260 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4, 0);
6261 tmp
= EMAC_RD(bp
, EMAC_REG_EMAC_LED
);
6262 EMAC_WR(bp
, EMAC_REG_EMAC_LED
, tmp
|
6263 EMAC_LED_OVERRIDE
| EMAC_LED_1000MB_OVERRIDE
);
6264 /* Break here; otherwise, it'll disable the
6265 * intended override.
6269 REG_WR(bp
, NIG_REG_LED_MODE_P0
+ port
*4,
6272 REG_WR(bp
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
+ port
*4, 0);
6273 /* Set blinking rate to ~15.9Hz */
6275 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_RATE_P0
+ port
*4,
6276 LED_BLINK_RATE_VAL_E3
);
6278 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_RATE_P0
+ port
*4,
6279 LED_BLINK_RATE_VAL_E1X_E2
);
6280 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0
+
6282 tmp
= EMAC_RD(bp
, EMAC_REG_EMAC_LED
);
6283 EMAC_WR(bp
, EMAC_REG_EMAC_LED
,
6284 (tmp
& (~EMAC_LED_OVERRIDE
)));
6286 if (CHIP_IS_E1(bp
) &&
6287 ((speed
== SPEED_2500
) ||
6288 (speed
== SPEED_1000
) ||
6289 (speed
== SPEED_100
) ||
6290 (speed
== SPEED_10
))) {
6291 /* For speeds less than 10G LED scheme is different */
6292 REG_WR(bp
, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
6294 REG_WR(bp
, NIG_REG_LED_CONTROL_TRAFFIC_P0
+
6296 REG_WR(bp
, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0
+
6303 DP(NETIF_MSG_LINK
, "bnx2x_set_led: Invalid led mode %d\n",
6311 /* This function comes to reflect the actual link state read DIRECTLY from the
6314 int bnx2x_test_link(struct link_params
*params
, struct link_vars
*vars
,
6317 struct bnx2x
*bp
= params
->bp
;
6318 u16 gp_status
= 0, phy_index
= 0;
6319 u8 ext_phy_link_up
= 0, serdes_phy_type
;
6320 struct link_vars temp_vars
;
6321 struct bnx2x_phy
*int_phy
= ¶ms
->phy
[INT_PHY
];
6323 if (CHIP_IS_E3(bp
)) {
6325 if (params
->req_line_speed
[LINK_CONFIG_IDX(INT_PHY
)]
6327 /* Check 20G link */
6328 bnx2x_cl45_read(bp
, int_phy
, MDIO_WC_DEVAD
,
6330 bnx2x_cl45_read(bp
, int_phy
, MDIO_WC_DEVAD
,
6334 /* Check 10G link and below*/
6335 u8 lane
= bnx2x_get_warpcore_lane(int_phy
, params
);
6336 bnx2x_cl45_read(bp
, int_phy
, MDIO_WC_DEVAD
,
6337 MDIO_WC_REG_GP2_STATUS_GP_2_1
,
6339 gp_status
= ((gp_status
>> 8) & 0xf) |
6340 ((gp_status
>> 12) & 0xf);
6341 link_up
= gp_status
& (1 << lane
);
6346 CL22_RD_OVER_CL45(bp
, int_phy
,
6347 MDIO_REG_BANK_GP_STATUS
,
6348 MDIO_GP_STATUS_TOP_AN_STATUS1
,
6350 /* Link is up only if both local phy and external phy are up */
6351 if (!(gp_status
& MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS
))
6354 /* In XGXS loopback mode, do not check external PHY */
6355 if (params
->loopback_mode
== LOOPBACK_XGXS
)
6358 switch (params
->num_phys
) {
6360 /* No external PHY */
6363 ext_phy_link_up
= params
->phy
[EXT_PHY1
].read_status(
6364 ¶ms
->phy
[EXT_PHY1
],
6365 params
, &temp_vars
);
6367 case 3: /* Dual Media */
6368 for (phy_index
= EXT_PHY1
; phy_index
< params
->num_phys
;
6370 serdes_phy_type
= ((params
->phy
[phy_index
].media_type
==
6371 ETH_PHY_SFPP_10G_FIBER
) ||
6372 (params
->phy
[phy_index
].media_type
==
6373 ETH_PHY_SFP_1G_FIBER
) ||
6374 (params
->phy
[phy_index
].media_type
==
6375 ETH_PHY_XFP_FIBER
) ||
6376 (params
->phy
[phy_index
].media_type
==
6377 ETH_PHY_DA_TWINAX
));
6379 if (is_serdes
!= serdes_phy_type
)
6381 if (params
->phy
[phy_index
].read_status
) {
6383 params
->phy
[phy_index
].read_status(
6384 ¶ms
->phy
[phy_index
],
6385 params
, &temp_vars
);
6390 if (ext_phy_link_up
)
6395 static int bnx2x_link_initialize(struct link_params
*params
,
6396 struct link_vars
*vars
)
6399 u8 phy_index
, non_ext_phy
;
6400 struct bnx2x
*bp
= params
->bp
;
6401 /* In case of external phy existence, the line speed would be the
6402 * line speed linked up by the external phy. In case it is direct
6403 * only, then the line_speed during initialization will be
6404 * equal to the req_line_speed
6406 vars
->line_speed
= params
->phy
[INT_PHY
].req_line_speed
;
6408 /* Initialize the internal phy in case this is a direct board
6409 * (no external phys), or this board has external phy which requires
6412 if (!USES_WARPCORE(bp
))
6413 bnx2x_prepare_xgxs(¶ms
->phy
[INT_PHY
], params
, vars
);
6414 /* init ext phy and enable link state int */
6415 non_ext_phy
= (SINGLE_MEDIA_DIRECT(params
) ||
6416 (params
->loopback_mode
== LOOPBACK_XGXS
));
6419 (params
->phy
[EXT_PHY1
].flags
& FLAGS_INIT_XGXS_FIRST
) ||
6420 (params
->loopback_mode
== LOOPBACK_EXT_PHY
)) {
6421 struct bnx2x_phy
*phy
= ¶ms
->phy
[INT_PHY
];
6422 if (vars
->line_speed
== SPEED_AUTO_NEG
&&
6425 bnx2x_set_parallel_detection(phy
, params
);
6426 if (params
->phy
[INT_PHY
].config_init
)
6427 params
->phy
[INT_PHY
].config_init(phy
,
6432 /* Init external phy*/
6434 if (params
->phy
[INT_PHY
].supported
&
6436 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
6438 for (phy_index
= EXT_PHY1
; phy_index
< params
->num_phys
;
6440 /* No need to initialize second phy in case of first
6441 * phy only selection. In case of second phy, we do
6442 * need to initialize the first phy, since they are
6445 if (params
->phy
[phy_index
].supported
&
6447 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
6449 if (phy_index
== EXT_PHY2
&&
6450 (bnx2x_phy_selection(params
) ==
6451 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
)) {
6453 "Not initializing second phy\n");
6456 params
->phy
[phy_index
].config_init(
6457 ¶ms
->phy
[phy_index
],
6461 /* Reset the interrupt indication after phy was initialized */
6462 bnx2x_bits_dis(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+
6464 (NIG_STATUS_XGXS0_LINK10G
|
6465 NIG_STATUS_XGXS0_LINK_STATUS
|
6466 NIG_STATUS_SERDES0_LINK_STATUS
|
6471 static void bnx2x_int_link_reset(struct bnx2x_phy
*phy
,
6472 struct link_params
*params
)
6474 /* Reset the SerDes/XGXS */
6475 REG_WR(params
->bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_3_CLEAR
,
6476 (0x1ff << (params
->port
*16)));
6479 static void bnx2x_common_ext_link_reset(struct bnx2x_phy
*phy
,
6480 struct link_params
*params
)
6482 struct bnx2x
*bp
= params
->bp
;
6486 gpio_port
= BP_PATH(bp
);
6488 gpio_port
= params
->port
;
6489 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
6490 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
6492 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
6493 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
6495 DP(NETIF_MSG_LINK
, "reset external PHY\n");
6498 static int bnx2x_update_link_down(struct link_params
*params
,
6499 struct link_vars
*vars
)
6501 struct bnx2x
*bp
= params
->bp
;
6502 u8 port
= params
->port
;
6504 DP(NETIF_MSG_LINK
, "Port %x: Link is down\n", port
);
6505 bnx2x_set_led(params
, vars
, LED_MODE_OFF
, 0);
6506 vars
->phy_flags
&= ~PHY_PHYSICAL_LINK_FLAG
;
6507 /* Indicate no mac active */
6508 vars
->mac_type
= MAC_TYPE_NONE
;
6510 /* Update shared memory */
6511 vars
->link_status
&= ~(LINK_STATUS_SPEED_AND_DUPLEX_MASK
|
6512 LINK_STATUS_LINK_UP
|
6513 LINK_STATUS_PHYSICAL_LINK_FLAG
|
6514 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
|
6515 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK
|
6516 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK
|
6517 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK
|
6518 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE
|
6519 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE
);
6520 vars
->line_speed
= 0;
6521 bnx2x_update_mng(params
, vars
->link_status
);
6523 /* Activate nig drain */
6524 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
*4, 1);
6527 if (!CHIP_IS_E3(bp
))
6528 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 0);
6530 usleep_range(10000, 20000);
6531 /* Reset BigMac/Xmac */
6532 if (CHIP_IS_E1x(bp
) ||
6534 bnx2x_bmac_rx_disable(bp
, params
->port
);
6535 REG_WR(bp
, GRCBASE_MISC
+
6536 MISC_REGISTERS_RESET_REG_2_CLEAR
,
6537 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
6539 if (CHIP_IS_E3(bp
)) {
6540 /* Prevent LPI Generation by chip */
6541 REG_WR(bp
, MISC_REG_CPMU_LP_FW_ENABLE_P0
+ (params
->port
<< 2),
6543 REG_WR(bp
, MISC_REG_CPMU_LP_DR_ENABLE
, 0);
6544 REG_WR(bp
, MISC_REG_CPMU_LP_MASK_ENT_P0
+ (params
->port
<< 2),
6546 vars
->eee_status
&= ~(SHMEM_EEE_LP_ADV_STATUS_MASK
|
6547 SHMEM_EEE_ACTIVE_BIT
);
6549 bnx2x_update_mng_eee(params
, vars
->eee_status
);
6550 bnx2x_xmac_disable(params
);
6551 bnx2x_umac_disable(params
);
6557 static int bnx2x_update_link_up(struct link_params
*params
,
6558 struct link_vars
*vars
,
6561 struct bnx2x
*bp
= params
->bp
;
6562 u8 phy_idx
, port
= params
->port
;
6565 vars
->link_status
|= (LINK_STATUS_LINK_UP
|
6566 LINK_STATUS_PHYSICAL_LINK_FLAG
);
6567 vars
->phy_flags
|= PHY_PHYSICAL_LINK_FLAG
;
6569 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
6570 vars
->link_status
|=
6571 LINK_STATUS_TX_FLOW_CONTROL_ENABLED
;
6573 if (vars
->flow_ctrl
& BNX2X_FLOW_CTRL_RX
)
6574 vars
->link_status
|=
6575 LINK_STATUS_RX_FLOW_CONTROL_ENABLED
;
6576 if (USES_WARPCORE(bp
)) {
6578 if (bnx2x_xmac_enable(params
, vars
, 0) ==
6580 DP(NETIF_MSG_LINK
, "Found errors on XMAC\n");
6582 vars
->phy_flags
|= PHY_HALF_OPEN_CONN_FLAG
;
6583 vars
->link_status
&= ~LINK_STATUS_LINK_UP
;
6586 bnx2x_umac_enable(params
, vars
, 0);
6587 bnx2x_set_led(params
, vars
,
6588 LED_MODE_OPER
, vars
->line_speed
);
6590 if ((vars
->eee_status
& SHMEM_EEE_ACTIVE_BIT
) &&
6591 (vars
->eee_status
& SHMEM_EEE_LPI_REQUESTED_BIT
)) {
6592 DP(NETIF_MSG_LINK
, "Enabling LPI assertion\n");
6593 REG_WR(bp
, MISC_REG_CPMU_LP_FW_ENABLE_P0
+
6594 (params
->port
<< 2), 1);
6595 REG_WR(bp
, MISC_REG_CPMU_LP_DR_ENABLE
, 1);
6596 REG_WR(bp
, MISC_REG_CPMU_LP_MASK_ENT_P0
+
6597 (params
->port
<< 2), 0xfc20);
6600 if ((CHIP_IS_E1x(bp
) ||
6603 if (bnx2x_bmac_enable(params
, vars
, 0) ==
6605 DP(NETIF_MSG_LINK
, "Found errors on BMAC\n");
6607 vars
->phy_flags
|= PHY_HALF_OPEN_CONN_FLAG
;
6608 vars
->link_status
&= ~LINK_STATUS_LINK_UP
;
6611 bnx2x_set_led(params
, vars
,
6612 LED_MODE_OPER
, SPEED_10000
);
6614 rc
= bnx2x_emac_program(params
, vars
);
6615 bnx2x_emac_enable(params
, vars
, 0);
6618 if ((vars
->link_status
&
6619 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
)
6620 && (!(vars
->phy_flags
& PHY_SGMII_FLAG
)) &&
6621 SINGLE_MEDIA_DIRECT(params
))
6622 bnx2x_set_gmii_tx_driver(params
);
6627 if (CHIP_IS_E1x(bp
))
6628 rc
|= bnx2x_pbf_update(params
, vars
->flow_ctrl
,
6632 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
*4, 0);
6634 /* Update shared memory */
6635 bnx2x_update_mng(params
, vars
->link_status
);
6636 bnx2x_update_mng_eee(params
, vars
->eee_status
);
6637 /* Check remote fault */
6638 for (phy_idx
= INT_PHY
; phy_idx
< MAX_PHYS
; phy_idx
++) {
6639 if (params
->phy
[phy_idx
].flags
& FLAGS_TX_ERROR_CHECK
) {
6640 bnx2x_check_half_open_conn(params
, vars
, 0);
6647 /* The bnx2x_link_update function should be called upon link
6649 * Link is considered up as follows:
6650 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
6652 * - SINGLE_MEDIA - The link between the 577xx and the external
6653 * phy (XGXS) need to up as well as the external link of the
6655 * - DUAL_MEDIA - The link between the 577xx and the first
6656 * external phy needs to be up, and at least one of the 2
6657 * external phy link must be up.
6659 int bnx2x_link_update(struct link_params
*params
, struct link_vars
*vars
)
6661 struct bnx2x
*bp
= params
->bp
;
6662 struct link_vars phy_vars
[MAX_PHYS
];
6663 u8 port
= params
->port
;
6664 u8 link_10g_plus
, phy_index
;
6665 u8 ext_phy_link_up
= 0, cur_link_up
;
6668 u16 ext_phy_line_speed
= 0, prev_line_speed
= vars
->line_speed
;
6669 u8 active_external_phy
= INT_PHY
;
6670 vars
->phy_flags
&= ~PHY_HALF_OPEN_CONN_FLAG
;
6671 for (phy_index
= INT_PHY
; phy_index
< params
->num_phys
;
6673 phy_vars
[phy_index
].flow_ctrl
= 0;
6674 phy_vars
[phy_index
].link_status
= 0;
6675 phy_vars
[phy_index
].line_speed
= 0;
6676 phy_vars
[phy_index
].duplex
= DUPLEX_FULL
;
6677 phy_vars
[phy_index
].phy_link_up
= 0;
6678 phy_vars
[phy_index
].link_up
= 0;
6679 phy_vars
[phy_index
].fault_detected
= 0;
6680 /* different consideration, since vars holds inner state */
6681 phy_vars
[phy_index
].eee_status
= vars
->eee_status
;
6684 if (USES_WARPCORE(bp
))
6685 bnx2x_set_aer_mmd(params
, ¶ms
->phy
[INT_PHY
]);
6687 DP(NETIF_MSG_LINK
, "port %x, XGXS?%x, int_status 0x%x\n",
6688 port
, (vars
->phy_flags
& PHY_XGXS_FLAG
),
6689 REG_RD(bp
, NIG_REG_STATUS_INTERRUPT_PORT0
+ port
*4));
6691 is_mi_int
= (u8
)(REG_RD(bp
, NIG_REG_EMAC0_STATUS_MISC_MI_INT
+
6693 DP(NETIF_MSG_LINK
, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
6694 REG_RD(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4),
6696 REG_RD(bp
, NIG_REG_SERDES0_STATUS_LINK_STATUS
+ port
*0x3c));
6698 DP(NETIF_MSG_LINK
, " 10G %x, XGXS_LINK %x\n",
6699 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK10G
+ port
*0x68),
6700 REG_RD(bp
, NIG_REG_XGXS0_STATUS_LINK_STATUS
+ port
*0x68));
6703 if (!CHIP_IS_E3(bp
))
6704 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 0);
6707 * Check external link change only for external phys, and apply
6708 * priority selection between them in case the link on both phys
6709 * is up. Note that instead of the common vars, a temporary
6710 * vars argument is used since each phy may have different link/
6711 * speed/duplex result
6713 for (phy_index
= EXT_PHY1
; phy_index
< params
->num_phys
;
6715 struct bnx2x_phy
*phy
= ¶ms
->phy
[phy_index
];
6716 if (!phy
->read_status
)
6718 /* Read link status and params of this ext phy */
6719 cur_link_up
= phy
->read_status(phy
, params
,
6720 &phy_vars
[phy_index
]);
6722 DP(NETIF_MSG_LINK
, "phy in index %d link is up\n",
6725 DP(NETIF_MSG_LINK
, "phy in index %d link is down\n",
6730 if (!ext_phy_link_up
) {
6731 ext_phy_link_up
= 1;
6732 active_external_phy
= phy_index
;
6734 switch (bnx2x_phy_selection(params
)) {
6735 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
:
6736 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
:
6737 /* In this option, the first PHY makes sure to pass the
6738 * traffic through itself only.
6739 * Its not clear how to reset the link on the second phy
6741 active_external_phy
= EXT_PHY1
;
6743 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
:
6744 /* In this option, the first PHY makes sure to pass the
6745 * traffic through the second PHY.
6747 active_external_phy
= EXT_PHY2
;
6750 /* Link indication on both PHYs with the following cases
6752 * - FIRST_PHY means that second phy wasn't initialized,
6753 * hence its link is expected to be down
6754 * - SECOND_PHY means that first phy should not be able
6755 * to link up by itself (using configuration)
6756 * - DEFAULT should be overriden during initialiazation
6758 DP(NETIF_MSG_LINK
, "Invalid link indication"
6759 "mpc=0x%x. DISABLING LINK !!!\n",
6760 params
->multi_phy_config
);
6761 ext_phy_link_up
= 0;
6766 prev_line_speed
= vars
->line_speed
;
6768 * Read the status of the internal phy. In case of
6769 * DIRECT_SINGLE_MEDIA board, this link is the external link,
6770 * otherwise this is the link between the 577xx and the first
6773 if (params
->phy
[INT_PHY
].read_status
)
6774 params
->phy
[INT_PHY
].read_status(
6775 ¶ms
->phy
[INT_PHY
],
6777 /* The INT_PHY flow control reside in the vars. This include the
6778 * case where the speed or flow control are not set to AUTO.
6779 * Otherwise, the active external phy flow control result is set
6780 * to the vars. The ext_phy_line_speed is needed to check if the
6781 * speed is different between the internal phy and external phy.
6782 * This case may be result of intermediate link speed change.
6784 if (active_external_phy
> INT_PHY
) {
6785 vars
->flow_ctrl
= phy_vars
[active_external_phy
].flow_ctrl
;
6786 /* Link speed is taken from the XGXS. AN and FC result from
6789 vars
->link_status
|= phy_vars
[active_external_phy
].link_status
;
6791 /* if active_external_phy is first PHY and link is up - disable
6792 * disable TX on second external PHY
6794 if (active_external_phy
== EXT_PHY1
) {
6795 if (params
->phy
[EXT_PHY2
].phy_specific_func
) {
6797 "Disabling TX on EXT_PHY2\n");
6798 params
->phy
[EXT_PHY2
].phy_specific_func(
6799 ¶ms
->phy
[EXT_PHY2
],
6800 params
, DISABLE_TX
);
6804 ext_phy_line_speed
= phy_vars
[active_external_phy
].line_speed
;
6805 vars
->duplex
= phy_vars
[active_external_phy
].duplex
;
6806 if (params
->phy
[active_external_phy
].supported
&
6808 vars
->link_status
|= LINK_STATUS_SERDES_LINK
;
6810 vars
->link_status
&= ~LINK_STATUS_SERDES_LINK
;
6812 vars
->eee_status
= phy_vars
[active_external_phy
].eee_status
;
6814 DP(NETIF_MSG_LINK
, "Active external phy selected: %x\n",
6815 active_external_phy
);
6818 for (phy_index
= EXT_PHY1
; phy_index
< params
->num_phys
;
6820 if (params
->phy
[phy_index
].flags
&
6821 FLAGS_REARM_LATCH_SIGNAL
) {
6822 bnx2x_rearm_latch_signal(bp
, port
,
6824 active_external_phy
);
6828 DP(NETIF_MSG_LINK
, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
6829 " ext_phy_line_speed = %d\n", vars
->flow_ctrl
,
6830 vars
->link_status
, ext_phy_line_speed
);
6831 /* Upon link speed change set the NIG into drain mode. Comes to
6832 * deals with possible FIFO glitch due to clk change when speed
6833 * is decreased without link down indicator
6836 if (vars
->phy_link_up
) {
6837 if (!(SINGLE_MEDIA_DIRECT(params
)) && ext_phy_link_up
&&
6838 (ext_phy_line_speed
!= vars
->line_speed
)) {
6839 DP(NETIF_MSG_LINK
, "Internal link speed %d is"
6840 " different than the external"
6841 " link speed %d\n", vars
->line_speed
,
6842 ext_phy_line_speed
);
6843 vars
->phy_link_up
= 0;
6844 } else if (prev_line_speed
!= vars
->line_speed
) {
6845 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
*4,
6847 usleep_range(1000, 2000);
6851 /* Anything 10 and over uses the bmac */
6852 link_10g_plus
= (vars
->line_speed
>= SPEED_10000
);
6854 bnx2x_link_int_ack(params
, vars
, link_10g_plus
);
6856 /* In case external phy link is up, and internal link is down
6857 * (not initialized yet probably after link initialization, it
6858 * needs to be initialized.
6859 * Note that after link down-up as result of cable plug, the xgxs
6860 * link would probably become up again without the need
6863 if (!(SINGLE_MEDIA_DIRECT(params
))) {
6864 DP(NETIF_MSG_LINK
, "ext_phy_link_up = %d, int_link_up = %d,"
6865 " init_preceding = %d\n", ext_phy_link_up
,
6867 params
->phy
[EXT_PHY1
].flags
&
6868 FLAGS_INIT_XGXS_FIRST
);
6869 if (!(params
->phy
[EXT_PHY1
].flags
&
6870 FLAGS_INIT_XGXS_FIRST
)
6871 && ext_phy_link_up
&& !vars
->phy_link_up
) {
6872 vars
->line_speed
= ext_phy_line_speed
;
6873 if (vars
->line_speed
< SPEED_1000
)
6874 vars
->phy_flags
|= PHY_SGMII_FLAG
;
6876 vars
->phy_flags
&= ~PHY_SGMII_FLAG
;
6878 if (params
->phy
[INT_PHY
].config_init
)
6879 params
->phy
[INT_PHY
].config_init(
6880 ¶ms
->phy
[INT_PHY
], params
,
6884 /* Link is up only if both local phy and external phy (in case of
6885 * non-direct board) are up and no fault detected on active PHY.
6887 vars
->link_up
= (vars
->phy_link_up
&&
6889 SINGLE_MEDIA_DIRECT(params
)) &&
6890 (phy_vars
[active_external_phy
].fault_detected
== 0));
6892 /* Update the PFC configuration in case it was changed */
6893 if (params
->feature_config_flags
& FEATURE_CONFIG_PFC_ENABLED
)
6894 vars
->link_status
|= LINK_STATUS_PFC_ENABLED
;
6896 vars
->link_status
&= ~LINK_STATUS_PFC_ENABLED
;
6899 rc
= bnx2x_update_link_up(params
, vars
, link_10g_plus
);
6901 rc
= bnx2x_update_link_down(params
, vars
);
6903 /* Update MCP link status was changed */
6904 if (params
->feature_config_flags
& FEATURE_CONFIG_BC_SUPPORTS_AFEX
)
6905 bnx2x_fw_command(bp
, DRV_MSG_CODE_LINK_STATUS_CHANGED
, 0);
6910 /*****************************************************************************/
6911 /* External Phy section */
6912 /*****************************************************************************/
6913 void bnx2x_ext_phy_hw_reset(struct bnx2x
*bp
, u8 port
)
6915 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
6916 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
6917 usleep_range(1000, 2000);
6918 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
6919 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, port
);
6922 static void bnx2x_save_spirom_version(struct bnx2x
*bp
, u8 port
,
6923 u32 spirom_ver
, u32 ver_addr
)
6925 DP(NETIF_MSG_LINK
, "FW version 0x%x:0x%x for port %d\n",
6926 (u16
)(spirom_ver
>>16), (u16
)spirom_ver
, port
);
6929 REG_WR(bp
, ver_addr
, spirom_ver
);
6932 static void bnx2x_save_bcm_spirom_ver(struct bnx2x
*bp
,
6933 struct bnx2x_phy
*phy
,
6936 u16 fw_ver1
, fw_ver2
;
6938 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
,
6939 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
6940 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
,
6941 MDIO_PMA_REG_ROM_VER2
, &fw_ver2
);
6942 bnx2x_save_spirom_version(bp
, port
, (u32
)(fw_ver1
<<16 | fw_ver2
),
6946 static void bnx2x_ext_phy_10G_an_resolve(struct bnx2x
*bp
,
6947 struct bnx2x_phy
*phy
,
6948 struct link_vars
*vars
)
6951 bnx2x_cl45_read(bp
, phy
,
6953 MDIO_AN_REG_STATUS
, &val
);
6954 bnx2x_cl45_read(bp
, phy
,
6956 MDIO_AN_REG_STATUS
, &val
);
6958 vars
->link_status
|= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
6959 if ((val
& (1<<0)) == 0)
6960 vars
->link_status
|= LINK_STATUS_PARALLEL_DETECTION_USED
;
6963 /******************************************************************/
6964 /* common BCM8073/BCM8727 PHY SECTION */
6965 /******************************************************************/
6966 static void bnx2x_8073_resolve_fc(struct bnx2x_phy
*phy
,
6967 struct link_params
*params
,
6968 struct link_vars
*vars
)
6970 struct bnx2x
*bp
= params
->bp
;
6971 if (phy
->req_line_speed
== SPEED_10
||
6972 phy
->req_line_speed
== SPEED_100
) {
6973 vars
->flow_ctrl
= phy
->req_flow_ctrl
;
6977 if (bnx2x_ext_phy_resolve_fc(phy
, params
, vars
) &&
6978 (vars
->flow_ctrl
== BNX2X_FLOW_CTRL_NONE
)) {
6980 u16 ld_pause
; /* local */
6981 u16 lp_pause
; /* link partner */
6982 bnx2x_cl45_read(bp
, phy
,
6984 MDIO_AN_REG_CL37_FC_LD
, &ld_pause
);
6986 bnx2x_cl45_read(bp
, phy
,
6988 MDIO_AN_REG_CL37_FC_LP
, &lp_pause
);
6989 pause_result
= (ld_pause
&
6990 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 5;
6991 pause_result
|= (lp_pause
&
6992 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) >> 7;
6994 bnx2x_pause_resolve(vars
, pause_result
);
6995 DP(NETIF_MSG_LINK
, "Ext PHY CL37 pause result 0x%x\n",
6999 static int bnx2x_8073_8727_external_rom_boot(struct bnx2x
*bp
,
7000 struct bnx2x_phy
*phy
,
7004 u16 fw_ver1
, fw_msgout
;
7007 /* Boot port from external ROM */
7009 bnx2x_cl45_write(bp
, phy
,
7011 MDIO_PMA_REG_GEN_CTRL
,
7014 /* Ucode reboot and rst */
7015 bnx2x_cl45_write(bp
, phy
,
7017 MDIO_PMA_REG_GEN_CTRL
,
7020 bnx2x_cl45_write(bp
, phy
,
7022 MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
7024 /* Reset internal microprocessor */
7025 bnx2x_cl45_write(bp
, phy
,
7027 MDIO_PMA_REG_GEN_CTRL
,
7028 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
7030 /* Release srst bit */
7031 bnx2x_cl45_write(bp
, phy
,
7033 MDIO_PMA_REG_GEN_CTRL
,
7034 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
7036 /* Delay 100ms per the PHY specifications */
7039 /* 8073 sometimes taking longer to download */
7044 "bnx2x_8073_8727_external_rom_boot port %x:"
7045 "Download failed. fw version = 0x%x\n",
7051 bnx2x_cl45_read(bp
, phy
,
7053 MDIO_PMA_REG_ROM_VER1
, &fw_ver1
);
7054 bnx2x_cl45_read(bp
, phy
,
7056 MDIO_PMA_REG_M8051_MSGOUT_REG
, &fw_msgout
);
7058 usleep_range(1000, 2000);
7059 } while (fw_ver1
== 0 || fw_ver1
== 0x4321 ||
7060 ((fw_msgout
& 0xff) != 0x03 && (phy
->type
==
7061 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
)));
7063 /* Clear ser_boot_ctl bit */
7064 bnx2x_cl45_write(bp
, phy
,
7066 MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
7067 bnx2x_save_bcm_spirom_ver(bp
, phy
, port
);
7070 "bnx2x_8073_8727_external_rom_boot port %x:"
7071 "Download complete. fw version = 0x%x\n",
7077 /******************************************************************/
7078 /* BCM8073 PHY SECTION */
7079 /******************************************************************/
7080 static int bnx2x_8073_is_snr_needed(struct bnx2x
*bp
, struct bnx2x_phy
*phy
)
7082 /* This is only required for 8073A1, version 102 only */
7085 /* Read 8073 HW revision*/
7086 bnx2x_cl45_read(bp
, phy
,
7088 MDIO_PMA_REG_8073_CHIP_REV
, &val
);
7091 /* No need to workaround in 8073 A1 */
7095 bnx2x_cl45_read(bp
, phy
,
7097 MDIO_PMA_REG_ROM_VER2
, &val
);
7099 /* SNR should be applied only for version 0x102 */
7106 static int bnx2x_8073_xaui_wa(struct bnx2x
*bp
, struct bnx2x_phy
*phy
)
7108 u16 val
, cnt
, cnt1
;
7110 bnx2x_cl45_read(bp
, phy
,
7112 MDIO_PMA_REG_8073_CHIP_REV
, &val
);
7115 /* No need to workaround in 8073 A1 */
7118 /* XAUI workaround in 8073 A0: */
7120 /* After loading the boot ROM and restarting Autoneg, poll
7124 for (cnt
= 0; cnt
< 1000; cnt
++) {
7125 bnx2x_cl45_read(bp
, phy
,
7127 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
7129 /* If bit [14] = 0 or bit [13] = 0, continue on with
7130 * system initialization (XAUI work-around not required, as
7131 * these bits indicate 2.5G or 1G link up).
7133 if (!(val
& (1<<14)) || !(val
& (1<<13))) {
7134 DP(NETIF_MSG_LINK
, "XAUI work-around not required\n");
7136 } else if (!(val
& (1<<15))) {
7137 DP(NETIF_MSG_LINK
, "bit 15 went off\n");
7138 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
7139 * MSB (bit15) goes to 1 (indicating that the XAUI
7140 * workaround has completed), then continue on with
7141 * system initialization.
7143 for (cnt1
= 0; cnt1
< 1000; cnt1
++) {
7144 bnx2x_cl45_read(bp
, phy
,
7146 MDIO_PMA_REG_8073_XAUI_WA
, &val
);
7147 if (val
& (1<<15)) {
7149 "XAUI workaround has completed\n");
7152 usleep_range(3000, 6000);
7156 usleep_range(3000, 6000);
7158 DP(NETIF_MSG_LINK
, "Warning: XAUI work-around timeout !!!\n");
7162 static void bnx2x_807x_force_10G(struct bnx2x
*bp
, struct bnx2x_phy
*phy
)
7164 /* Force KR or KX */
7165 bnx2x_cl45_write(bp
, phy
,
7166 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x2040);
7167 bnx2x_cl45_write(bp
, phy
,
7168 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, 0x000b);
7169 bnx2x_cl45_write(bp
, phy
,
7170 MDIO_PMA_DEVAD
, MDIO_PMA_REG_BCM_CTRL
, 0x0000);
7171 bnx2x_cl45_write(bp
, phy
,
7172 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x0000);
7175 static void bnx2x_8073_set_pause_cl37(struct link_params
*params
,
7176 struct bnx2x_phy
*phy
,
7177 struct link_vars
*vars
)
7180 struct bnx2x
*bp
= params
->bp
;
7181 bnx2x_cl45_read(bp
, phy
,
7182 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, &cl37_val
);
7184 cl37_val
&= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
7185 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
7186 bnx2x_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
7187 if ((vars
->ieee_fc
&
7188 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) ==
7189 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
) {
7190 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC
;
7192 if ((vars
->ieee_fc
&
7193 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
7194 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) {
7195 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
;
7197 if ((vars
->ieee_fc
&
7198 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
7199 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) {
7200 cl37_val
|= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
;
7203 "Ext phy AN advertize cl37 0x%x\n", cl37_val
);
7205 bnx2x_cl45_write(bp
, phy
,
7206 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, cl37_val
);
7210 static int bnx2x_8073_config_init(struct bnx2x_phy
*phy
,
7211 struct link_params
*params
,
7212 struct link_vars
*vars
)
7214 struct bnx2x
*bp
= params
->bp
;
7217 DP(NETIF_MSG_LINK
, "Init 8073\n");
7220 gpio_port
= BP_PATH(bp
);
7222 gpio_port
= params
->port
;
7223 /* Restore normal power mode*/
7224 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
7225 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, gpio_port
);
7227 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
7228 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, gpio_port
);
7231 bnx2x_cl45_write(bp
, phy
,
7232 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
, (1<<2));
7233 bnx2x_cl45_write(bp
, phy
,
7234 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x0004);
7236 bnx2x_8073_set_pause_cl37(params
, phy
, vars
);
7238 bnx2x_cl45_read(bp
, phy
,
7239 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &tmp1
);
7241 bnx2x_cl45_read(bp
, phy
,
7242 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &tmp1
);
7244 DP(NETIF_MSG_LINK
, "Before rom RX_ALARM(port1): 0x%x\n", tmp1
);
7246 /* Swap polarity if required - Must be done only in non-1G mode */
7247 if (params
->lane_config
& PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED
) {
7248 /* Configure the 8073 to swap _P and _N of the KR lines */
7249 DP(NETIF_MSG_LINK
, "Swapping polarity for the 8073\n");
7250 /* 10G Rx/Tx and 1G Tx signal polarity swap */
7251 bnx2x_cl45_read(bp
, phy
,
7253 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL
, &val
);
7254 bnx2x_cl45_write(bp
, phy
,
7256 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL
,
7261 /* Enable CL37 BAM */
7262 if (REG_RD(bp
, params
->shmem_base
+
7263 offsetof(struct shmem_region
, dev_info
.
7264 port_hw_config
[params
->port
].default_cfg
)) &
7265 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED
) {
7267 bnx2x_cl45_read(bp
, phy
,
7269 MDIO_AN_REG_8073_BAM
, &val
);
7270 bnx2x_cl45_write(bp
, phy
,
7272 MDIO_AN_REG_8073_BAM
, val
| 1);
7273 DP(NETIF_MSG_LINK
, "Enable CL37 BAM on KR\n");
7275 if (params
->loopback_mode
== LOOPBACK_EXT
) {
7276 bnx2x_807x_force_10G(bp
, phy
);
7277 DP(NETIF_MSG_LINK
, "Forced speed 10G on 807X\n");
7280 bnx2x_cl45_write(bp
, phy
,
7281 MDIO_PMA_DEVAD
, MDIO_PMA_REG_BCM_CTRL
, 0x0002);
7283 if (phy
->req_line_speed
!= SPEED_AUTO_NEG
) {
7284 if (phy
->req_line_speed
== SPEED_10000
) {
7286 } else if (phy
->req_line_speed
== SPEED_2500
) {
7288 /* Note that 2.5G works only when used with 1G
7295 if (phy
->speed_cap_mask
&
7296 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
7299 /* Note that 2.5G works only when used with 1G advertisement */
7300 if (phy
->speed_cap_mask
&
7301 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
|
7302 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
7304 DP(NETIF_MSG_LINK
, "807x autoneg val = 0x%x\n", val
);
7307 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV
, val
);
7308 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_8073_2_5G
, &tmp1
);
7310 if (((phy
->speed_cap_mask
& PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
) &&
7311 (phy
->req_line_speed
== SPEED_AUTO_NEG
)) ||
7312 (phy
->req_line_speed
== SPEED_2500
)) {
7314 /* Allow 2.5G for A1 and above */
7315 bnx2x_cl45_read(bp
, phy
,
7316 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_CHIP_REV
,
7318 DP(NETIF_MSG_LINK
, "Add 2.5G\n");
7324 DP(NETIF_MSG_LINK
, "Disable 2.5G\n");
7328 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_8073_2_5G
, tmp1
);
7329 /* Add support for CL37 (passive mode) II */
7331 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, &tmp1
);
7332 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
,
7333 (tmp1
| ((phy
->req_duplex
== DUPLEX_FULL
) ?
7336 /* Add support for CL37 (passive mode) III */
7337 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1000);
7339 /* The SNR will improve about 2db by changing BW and FEE main
7340 * tap. Rest commands are executed after link is up
7341 * Change FFE main cursor to 5 in EDC register
7343 if (bnx2x_8073_is_snr_needed(bp
, phy
))
7344 bnx2x_cl45_write(bp
, phy
,
7345 MDIO_PMA_DEVAD
, MDIO_PMA_REG_EDC_FFE_MAIN
,
7348 /* Enable FEC (Forware Error Correction) Request in the AN */
7349 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV2
, &tmp1
);
7351 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_ADV2
, tmp1
);
7353 bnx2x_ext_phy_set_pause(params
, phy
, vars
);
7355 /* Restart autoneg */
7357 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x1200);
7358 DP(NETIF_MSG_LINK
, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
7359 ((val
& (1<<5)) > 0), ((val
& (1<<7)) > 0));
7363 static u8
bnx2x_8073_read_status(struct bnx2x_phy
*phy
,
7364 struct link_params
*params
,
7365 struct link_vars
*vars
)
7367 struct bnx2x
*bp
= params
->bp
;
7370 u16 link_status
= 0;
7371 u16 an1000_status
= 0;
7373 bnx2x_cl45_read(bp
, phy
,
7374 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
7376 DP(NETIF_MSG_LINK
, "8703 LASI status 0x%x\n", val1
);
7378 /* Clear the interrupt LASI status register */
7379 bnx2x_cl45_read(bp
, phy
,
7380 MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &val2
);
7381 bnx2x_cl45_read(bp
, phy
,
7382 MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &val1
);
7383 DP(NETIF_MSG_LINK
, "807x PCS status 0x%x->0x%x\n", val2
, val1
);
7385 bnx2x_cl45_read(bp
, phy
,
7386 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &val1
);
7388 /* Check the LASI */
7389 bnx2x_cl45_read(bp
, phy
,
7390 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &val2
);
7392 DP(NETIF_MSG_LINK
, "KR 0x9003 0x%x\n", val2
);
7394 /* Check the link status */
7395 bnx2x_cl45_read(bp
, phy
,
7396 MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &val2
);
7397 DP(NETIF_MSG_LINK
, "KR PCS status 0x%x\n", val2
);
7399 bnx2x_cl45_read(bp
, phy
,
7400 MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val2
);
7401 bnx2x_cl45_read(bp
, phy
,
7402 MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val1
);
7403 link_up
= ((val1
& 4) == 4);
7404 DP(NETIF_MSG_LINK
, "PMA_REG_STATUS=0x%x\n", val1
);
7407 ((phy
->req_line_speed
!= SPEED_10000
))) {
7408 if (bnx2x_8073_xaui_wa(bp
, phy
) != 0)
7411 bnx2x_cl45_read(bp
, phy
,
7412 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &an1000_status
);
7413 bnx2x_cl45_read(bp
, phy
,
7414 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &an1000_status
);
7416 /* Check the link status on 1.1.2 */
7417 bnx2x_cl45_read(bp
, phy
,
7418 MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val2
);
7419 bnx2x_cl45_read(bp
, phy
,
7420 MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val1
);
7421 DP(NETIF_MSG_LINK
, "KR PMA status 0x%x->0x%x,"
7422 "an_link_status=0x%x\n", val2
, val1
, an1000_status
);
7424 link_up
= (((val1
& 4) == 4) || (an1000_status
& (1<<1)));
7425 if (link_up
&& bnx2x_8073_is_snr_needed(bp
, phy
)) {
7426 /* The SNR will improve about 2dbby changing the BW and FEE main
7427 * tap. The 1st write to change FFE main tap is set before
7428 * restart AN. Change PLL Bandwidth in EDC register
7430 bnx2x_cl45_write(bp
, phy
,
7431 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PLL_BANDWIDTH
,
7434 /* Change CDR Bandwidth in EDC register */
7435 bnx2x_cl45_write(bp
, phy
,
7436 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CDR_BANDWIDTH
,
7439 bnx2x_cl45_read(bp
, phy
,
7440 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8073_SPEED_LINK_STATUS
,
7443 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
7444 if ((link_status
& (1<<2)) && (!(link_status
& (1<<15)))) {
7446 vars
->line_speed
= SPEED_10000
;
7447 DP(NETIF_MSG_LINK
, "port %x: External link up in 10G\n",
7449 } else if ((link_status
& (1<<1)) && (!(link_status
& (1<<14)))) {
7451 vars
->line_speed
= SPEED_2500
;
7452 DP(NETIF_MSG_LINK
, "port %x: External link up in 2.5G\n",
7454 } else if ((link_status
& (1<<0)) && (!(link_status
& (1<<13)))) {
7456 vars
->line_speed
= SPEED_1000
;
7457 DP(NETIF_MSG_LINK
, "port %x: External link up in 1G\n",
7461 DP(NETIF_MSG_LINK
, "port %x: External link is down\n",
7466 /* Swap polarity if required */
7467 if (params
->lane_config
&
7468 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED
) {
7469 /* Configure the 8073 to swap P and N of the KR lines */
7470 bnx2x_cl45_read(bp
, phy
,
7472 MDIO_XS_REG_8073_RX_CTRL_PCIE
, &val1
);
7473 /* Set bit 3 to invert Rx in 1G mode and clear this bit
7474 * when it`s in 10G mode.
7476 if (vars
->line_speed
== SPEED_1000
) {
7477 DP(NETIF_MSG_LINK
, "Swapping 1G polarity for"
7483 bnx2x_cl45_write(bp
, phy
,
7485 MDIO_XS_REG_8073_RX_CTRL_PCIE
,
7488 bnx2x_ext_phy_10G_an_resolve(bp
, phy
, vars
);
7489 bnx2x_8073_resolve_fc(phy
, params
, vars
);
7490 vars
->duplex
= DUPLEX_FULL
;
7493 if (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
7494 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
7495 MDIO_AN_REG_LP_AUTO_NEG2
, &val1
);
7498 vars
->link_status
|=
7499 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
7501 vars
->link_status
|=
7502 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
7508 static void bnx2x_8073_link_reset(struct bnx2x_phy
*phy
,
7509 struct link_params
*params
)
7511 struct bnx2x
*bp
= params
->bp
;
7514 gpio_port
= BP_PATH(bp
);
7516 gpio_port
= params
->port
;
7517 DP(NETIF_MSG_LINK
, "Setting 8073 port %d into low power mode\n",
7519 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
7520 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
7524 /******************************************************************/
7525 /* BCM8705 PHY SECTION */
7526 /******************************************************************/
7527 static int bnx2x_8705_config_init(struct bnx2x_phy
*phy
,
7528 struct link_params
*params
,
7529 struct link_vars
*vars
)
7531 struct bnx2x
*bp
= params
->bp
;
7532 DP(NETIF_MSG_LINK
, "init 8705\n");
7533 /* Restore normal power mode*/
7534 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
7535 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
7537 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
7538 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0xa040);
7539 bnx2x_wait_reset_complete(bp
, phy
, params
);
7541 bnx2x_cl45_write(bp
, phy
,
7542 MDIO_PMA_DEVAD
, MDIO_PMA_REG_MISC_CTRL
, 0x8288);
7543 bnx2x_cl45_write(bp
, phy
,
7544 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
, 0x7fbf);
7545 bnx2x_cl45_write(bp
, phy
,
7546 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CMU_PLL_BYPASS
, 0x0100);
7547 bnx2x_cl45_write(bp
, phy
,
7548 MDIO_WIS_DEVAD
, MDIO_WIS_REG_LASI_CNTL
, 0x1);
7549 /* BCM8705 doesn't have microcode, hence the 0 */
7550 bnx2x_save_spirom_version(bp
, params
->port
, params
->shmem_base
, 0);
7554 static u8
bnx2x_8705_read_status(struct bnx2x_phy
*phy
,
7555 struct link_params
*params
,
7556 struct link_vars
*vars
)
7560 struct bnx2x
*bp
= params
->bp
;
7561 DP(NETIF_MSG_LINK
, "read status 8705\n");
7562 bnx2x_cl45_read(bp
, phy
,
7563 MDIO_WIS_DEVAD
, MDIO_WIS_REG_LASI_STATUS
, &val1
);
7564 DP(NETIF_MSG_LINK
, "8705 LASI status 0x%x\n", val1
);
7566 bnx2x_cl45_read(bp
, phy
,
7567 MDIO_WIS_DEVAD
, MDIO_WIS_REG_LASI_STATUS
, &val1
);
7568 DP(NETIF_MSG_LINK
, "8705 LASI status 0x%x\n", val1
);
7570 bnx2x_cl45_read(bp
, phy
,
7571 MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_SD
, &rx_sd
);
7573 bnx2x_cl45_read(bp
, phy
,
7574 MDIO_PMA_DEVAD
, 0xc809, &val1
);
7575 bnx2x_cl45_read(bp
, phy
,
7576 MDIO_PMA_DEVAD
, 0xc809, &val1
);
7578 DP(NETIF_MSG_LINK
, "8705 1.c809 val=0x%x\n", val1
);
7579 link_up
= ((rx_sd
& 0x1) && (val1
& (1<<9)) && ((val1
& (1<<8)) == 0));
7581 vars
->line_speed
= SPEED_10000
;
7582 bnx2x_ext_phy_resolve_fc(phy
, params
, vars
);
7587 /******************************************************************/
7588 /* SFP+ module Section */
7589 /******************************************************************/
7590 static void bnx2x_set_disable_pmd_transmit(struct link_params
*params
,
7591 struct bnx2x_phy
*phy
,
7594 struct bnx2x
*bp
= params
->bp
;
7595 /* Disable transmitter only for bootcodes which can enable it afterwards
7599 if (params
->feature_config_flags
&
7600 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
)
7601 DP(NETIF_MSG_LINK
, "Disabling PMD transmitter\n");
7603 DP(NETIF_MSG_LINK
, "NOT disabling PMD transmitter\n");
7607 DP(NETIF_MSG_LINK
, "Enabling PMD transmitter\n");
7608 bnx2x_cl45_write(bp
, phy
,
7610 MDIO_PMA_REG_TX_DISABLE
, pmd_dis
);
7613 static u8
bnx2x_get_gpio_port(struct link_params
*params
)
7616 u32 swap_val
, swap_override
;
7617 struct bnx2x
*bp
= params
->bp
;
7619 gpio_port
= BP_PATH(bp
);
7621 gpio_port
= params
->port
;
7622 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
7623 swap_override
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
7624 return gpio_port
^ (swap_val
&& swap_override
);
7627 static void bnx2x_sfp_e1e2_set_transmitter(struct link_params
*params
,
7628 struct bnx2x_phy
*phy
,
7632 u8 port
= params
->port
;
7633 struct bnx2x
*bp
= params
->bp
;
7636 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
7637 tx_en_mode
= REG_RD(bp
, params
->shmem_base
+
7638 offsetof(struct shmem_region
,
7639 dev_info
.port_hw_config
[port
].sfp_ctrl
)) &
7640 PORT_HW_CFG_TX_LASER_MASK
;
7641 DP(NETIF_MSG_LINK
, "Setting transmitter tx_en=%x for port %x "
7642 "mode = %x\n", tx_en
, port
, tx_en_mode
);
7643 switch (tx_en_mode
) {
7644 case PORT_HW_CFG_TX_LASER_MDIO
:
7646 bnx2x_cl45_read(bp
, phy
,
7648 MDIO_PMA_REG_PHY_IDENTIFIER
,
7656 bnx2x_cl45_write(bp
, phy
,
7658 MDIO_PMA_REG_PHY_IDENTIFIER
,
7661 case PORT_HW_CFG_TX_LASER_GPIO0
:
7662 case PORT_HW_CFG_TX_LASER_GPIO1
:
7663 case PORT_HW_CFG_TX_LASER_GPIO2
:
7664 case PORT_HW_CFG_TX_LASER_GPIO3
:
7667 u8 gpio_port
, gpio_mode
;
7669 gpio_mode
= MISC_REGISTERS_GPIO_OUTPUT_HIGH
;
7671 gpio_mode
= MISC_REGISTERS_GPIO_OUTPUT_LOW
;
7673 gpio_pin
= tx_en_mode
- PORT_HW_CFG_TX_LASER_GPIO0
;
7674 gpio_port
= bnx2x_get_gpio_port(params
);
7675 bnx2x_set_gpio(bp
, gpio_pin
, gpio_mode
, gpio_port
);
7679 DP(NETIF_MSG_LINK
, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode
);
7684 static void bnx2x_sfp_set_transmitter(struct link_params
*params
,
7685 struct bnx2x_phy
*phy
,
7688 struct bnx2x
*bp
= params
->bp
;
7689 DP(NETIF_MSG_LINK
, "Setting SFP+ transmitter to %d\n", tx_en
);
7691 bnx2x_sfp_e3_set_transmitter(params
, phy
, tx_en
);
7693 bnx2x_sfp_e1e2_set_transmitter(params
, phy
, tx_en
);
7696 static int bnx2x_8726_read_sfp_module_eeprom(struct bnx2x_phy
*phy
,
7697 struct link_params
*params
,
7698 u16 addr
, u8 byte_cnt
, u8
*o_buf
)
7700 struct bnx2x
*bp
= params
->bp
;
7703 if (byte_cnt
> SFP_EEPROM_PAGE_SIZE
) {
7705 "Reading from eeprom is limited to 0xf\n");
7708 /* Set the read command byte count */
7709 bnx2x_cl45_write(bp
, phy
,
7710 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
7711 (byte_cnt
| 0xa000));
7713 /* Set the read command address */
7714 bnx2x_cl45_write(bp
, phy
,
7715 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
,
7718 /* Activate read command */
7719 bnx2x_cl45_write(bp
, phy
,
7720 MDIO_PMA_DEVAD
, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
7723 /* Wait up to 500us for command complete status */
7724 for (i
= 0; i
< 100; i
++) {
7725 bnx2x_cl45_read(bp
, phy
,
7727 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7728 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7729 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
7734 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
7735 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
7737 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7738 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
7742 /* Read the buffer */
7743 for (i
= 0; i
< byte_cnt
; i
++) {
7744 bnx2x_cl45_read(bp
, phy
,
7746 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF
+ i
, &val
);
7747 o_buf
[i
] = (u8
)(val
& MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK
);
7750 for (i
= 0; i
< 100; i
++) {
7751 bnx2x_cl45_read(bp
, phy
,
7753 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7754 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7755 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
7757 usleep_range(1000, 2000);
7762 static void bnx2x_warpcore_power_module(struct link_params
*params
,
7763 struct bnx2x_phy
*phy
,
7767 struct bnx2x
*bp
= params
->bp
;
7769 pin_cfg
= (REG_RD(bp
, params
->shmem_base
+
7770 offsetof(struct shmem_region
,
7771 dev_info
.port_hw_config
[params
->port
].e3_sfp_ctrl
)) &
7772 PORT_HW_CFG_E3_PWR_DIS_MASK
) >>
7773 PORT_HW_CFG_E3_PWR_DIS_SHIFT
;
7775 if (pin_cfg
== PIN_CFG_NA
)
7777 DP(NETIF_MSG_LINK
, "Setting SFP+ module power to %d using pin cfg %d\n",
7779 /* Low ==> corresponding SFP+ module is powered
7780 * high ==> the SFP+ module is powered down
7782 bnx2x_set_cfg_pin(bp
, pin_cfg
, power
^ 1);
7784 static int bnx2x_warpcore_read_sfp_module_eeprom(struct bnx2x_phy
*phy
,
7785 struct link_params
*params
,
7786 u16 addr
, u8 byte_cnt
,
7790 u8 i
, j
= 0, cnt
= 0;
7793 struct bnx2x
*bp
= params
->bp
;
7795 if (byte_cnt
> SFP_EEPROM_PAGE_SIZE
) {
7797 "Reading from eeprom is limited to 16 bytes\n");
7801 /* 4 byte aligned address */
7802 addr32
= addr
& (~0x3);
7804 if (cnt
== I2C_WA_PWR_ITER
) {
7805 bnx2x_warpcore_power_module(params
, phy
, 0);
7806 /* Note that 100us are not enough here */
7807 usleep_range(1000,1000);
7808 bnx2x_warpcore_power_module(params
, phy
, 1);
7810 rc
= bnx2x_bsc_read(params
, phy
, 0xa0, addr32
, 0, byte_cnt
,
7812 } while ((rc
!= 0) && (++cnt
< I2C_WA_RETRY_CNT
));
7815 for (i
= (addr
- addr32
); i
< byte_cnt
+ (addr
- addr32
); i
++) {
7816 o_buf
[j
] = *((u8
*)data_array
+ i
);
7824 static int bnx2x_8727_read_sfp_module_eeprom(struct bnx2x_phy
*phy
,
7825 struct link_params
*params
,
7826 u16 addr
, u8 byte_cnt
, u8
*o_buf
)
7828 struct bnx2x
*bp
= params
->bp
;
7831 if (byte_cnt
> SFP_EEPROM_PAGE_SIZE
) {
7833 "Reading from eeprom is limited to 0xf\n");
7837 /* Need to read from 1.8000 to clear it */
7838 bnx2x_cl45_read(bp
, phy
,
7840 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
7843 /* Set the read command byte count */
7844 bnx2x_cl45_write(bp
, phy
,
7846 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT
,
7847 ((byte_cnt
< 2) ? 2 : byte_cnt
));
7849 /* Set the read command address */
7850 bnx2x_cl45_write(bp
, phy
,
7852 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR
,
7854 /* Set the destination address */
7855 bnx2x_cl45_write(bp
, phy
,
7858 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
);
7860 /* Activate read command */
7861 bnx2x_cl45_write(bp
, phy
,
7863 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
,
7865 /* Wait appropriate time for two-wire command to finish before
7866 * polling the status register
7868 usleep_range(1000, 2000);
7870 /* Wait up to 500us for command complete status */
7871 for (i
= 0; i
< 100; i
++) {
7872 bnx2x_cl45_read(bp
, phy
,
7874 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7875 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7876 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
)
7881 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) !=
7882 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE
) {
7884 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
7885 (val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
));
7889 /* Read the buffer */
7890 for (i
= 0; i
< byte_cnt
; i
++) {
7891 bnx2x_cl45_read(bp
, phy
,
7893 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF
+ i
, &val
);
7894 o_buf
[i
] = (u8
)(val
& MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK
);
7897 for (i
= 0; i
< 100; i
++) {
7898 bnx2x_cl45_read(bp
, phy
,
7900 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL
, &val
);
7901 if ((val
& MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK
) ==
7902 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE
)
7904 usleep_range(1000, 2000);
7910 int bnx2x_read_sfp_module_eeprom(struct bnx2x_phy
*phy
,
7911 struct link_params
*params
, u16 addr
,
7912 u8 byte_cnt
, u8
*o_buf
)
7914 int rc
= -EOPNOTSUPP
;
7915 switch (phy
->type
) {
7916 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
7917 rc
= bnx2x_8726_read_sfp_module_eeprom(phy
, params
, addr
,
7920 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
7921 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722
:
7922 rc
= bnx2x_8727_read_sfp_module_eeprom(phy
, params
, addr
,
7925 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
7926 rc
= bnx2x_warpcore_read_sfp_module_eeprom(phy
, params
, addr
,
7933 static int bnx2x_get_edc_mode(struct bnx2x_phy
*phy
,
7934 struct link_params
*params
,
7937 struct bnx2x
*bp
= params
->bp
;
7938 u32 sync_offset
= 0, phy_idx
, media_types
;
7939 u8 val
[2], check_limiting_mode
= 0;
7940 *edc_mode
= EDC_MODE_LIMITING
;
7942 phy
->media_type
= ETH_PHY_UNSPECIFIED
;
7943 /* First check for copper cable */
7944 if (bnx2x_read_sfp_module_eeprom(phy
,
7946 SFP_EEPROM_CON_TYPE_ADDR
,
7949 DP(NETIF_MSG_LINK
, "Failed to read from SFP+ module EEPROM\n");
7954 case SFP_EEPROM_CON_TYPE_VAL_COPPER
:
7956 u8 copper_module_type
;
7957 phy
->media_type
= ETH_PHY_DA_TWINAX
;
7958 /* Check if its active cable (includes SFP+ module)
7961 if (bnx2x_read_sfp_module_eeprom(phy
,
7963 SFP_EEPROM_FC_TX_TECH_ADDR
,
7965 &copper_module_type
) != 0) {
7967 "Failed to read copper-cable-type"
7968 " from SFP+ EEPROM\n");
7972 if (copper_module_type
&
7973 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE
) {
7974 DP(NETIF_MSG_LINK
, "Active Copper cable detected\n");
7975 check_limiting_mode
= 1;
7976 } else if (copper_module_type
&
7977 SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE
) {
7979 "Passive Copper cable detected\n");
7981 EDC_MODE_PASSIVE_DAC
;
7984 "Unknown copper-cable-type 0x%x !!!\n",
7985 copper_module_type
);
7990 case SFP_EEPROM_CON_TYPE_VAL_LC
:
7991 check_limiting_mode
= 1;
7992 if ((val
[1] & (SFP_EEPROM_COMP_CODE_SR_MASK
|
7993 SFP_EEPROM_COMP_CODE_LR_MASK
|
7994 SFP_EEPROM_COMP_CODE_LRM_MASK
)) == 0) {
7995 DP(NETIF_MSG_LINK
, "1G Optic module detected\n");
7996 phy
->media_type
= ETH_PHY_SFP_1G_FIBER
;
7997 phy
->req_line_speed
= SPEED_1000
;
7999 int idx
, cfg_idx
= 0;
8000 DP(NETIF_MSG_LINK
, "10G Optic module detected\n");
8001 for (idx
= INT_PHY
; idx
< MAX_PHYS
; idx
++) {
8002 if (params
->phy
[idx
].type
== phy
->type
) {
8003 cfg_idx
= LINK_CONFIG_IDX(idx
);
8007 phy
->media_type
= ETH_PHY_SFPP_10G_FIBER
;
8008 phy
->req_line_speed
= params
->req_line_speed
[cfg_idx
];
8012 DP(NETIF_MSG_LINK
, "Unable to determine module type 0x%x !!!\n",
8016 sync_offset
= params
->shmem_base
+
8017 offsetof(struct shmem_region
,
8018 dev_info
.port_hw_config
[params
->port
].media_type
);
8019 media_types
= REG_RD(bp
, sync_offset
);
8020 /* Update media type for non-PMF sync */
8021 for (phy_idx
= INT_PHY
; phy_idx
< MAX_PHYS
; phy_idx
++) {
8022 if (&(params
->phy
[phy_idx
]) == phy
) {
8023 media_types
&= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
<<
8024 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
* phy_idx
));
8025 media_types
|= ((phy
->media_type
&
8026 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
) <<
8027 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
* phy_idx
));
8031 REG_WR(bp
, sync_offset
, media_types
);
8032 if (check_limiting_mode
) {
8033 u8 options
[SFP_EEPROM_OPTIONS_SIZE
];
8034 if (bnx2x_read_sfp_module_eeprom(phy
,
8036 SFP_EEPROM_OPTIONS_ADDR
,
8037 SFP_EEPROM_OPTIONS_SIZE
,
8040 "Failed to read Option field from module EEPROM\n");
8043 if ((options
[0] & SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK
))
8044 *edc_mode
= EDC_MODE_LINEAR
;
8046 *edc_mode
= EDC_MODE_LIMITING
;
8048 DP(NETIF_MSG_LINK
, "EDC mode is set to 0x%x\n", *edc_mode
);
8051 /* This function read the relevant field from the module (SFP+), and verify it
8052 * is compliant with this board
8054 static int bnx2x_verify_sfp_module(struct bnx2x_phy
*phy
,
8055 struct link_params
*params
)
8057 struct bnx2x
*bp
= params
->bp
;
8059 u32 fw_resp
, fw_cmd_param
;
8060 char vendor_name
[SFP_EEPROM_VENDOR_NAME_SIZE
+1];
8061 char vendor_pn
[SFP_EEPROM_PART_NO_SIZE
+1];
8062 phy
->flags
&= ~FLAGS_SFP_NOT_APPROVED
;
8063 val
= REG_RD(bp
, params
->shmem_base
+
8064 offsetof(struct shmem_region
, dev_info
.
8065 port_feature_config
[params
->port
].config
));
8066 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
8067 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT
) {
8068 DP(NETIF_MSG_LINK
, "NOT enforcing module verification\n");
8072 if (params
->feature_config_flags
&
8073 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
) {
8074 /* Use specific phy request */
8075 cmd
= DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL
;
8076 } else if (params
->feature_config_flags
&
8077 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
) {
8078 /* Use first phy request only in case of non-dual media*/
8079 if (DUAL_MEDIA(params
)) {
8081 "FW does not support OPT MDL verification\n");
8084 cmd
= DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL
;
8086 /* No support in OPT MDL detection */
8088 "FW does not support OPT MDL verification\n");
8092 fw_cmd_param
= FW_PARAM_SET(phy
->addr
, phy
->type
, phy
->mdio_ctrl
);
8093 fw_resp
= bnx2x_fw_command(bp
, cmd
, fw_cmd_param
);
8094 if (fw_resp
== FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS
) {
8095 DP(NETIF_MSG_LINK
, "Approved module\n");
8099 /* Format the warning message */
8100 if (bnx2x_read_sfp_module_eeprom(phy
,
8102 SFP_EEPROM_VENDOR_NAME_ADDR
,
8103 SFP_EEPROM_VENDOR_NAME_SIZE
,
8105 vendor_name
[0] = '\0';
8107 vendor_name
[SFP_EEPROM_VENDOR_NAME_SIZE
] = '\0';
8108 if (bnx2x_read_sfp_module_eeprom(phy
,
8110 SFP_EEPROM_PART_NO_ADDR
,
8111 SFP_EEPROM_PART_NO_SIZE
,
8113 vendor_pn
[0] = '\0';
8115 vendor_pn
[SFP_EEPROM_PART_NO_SIZE
] = '\0';
8117 netdev_err(bp
->dev
, "Warning: Unqualified SFP+ module detected,"
8118 " Port %d from %s part number %s\n",
8119 params
->port
, vendor_name
, vendor_pn
);
8120 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) !=
8121 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG
)
8122 phy
->flags
|= FLAGS_SFP_NOT_APPROVED
;
8126 static int bnx2x_wait_for_sfp_module_initialized(struct bnx2x_phy
*phy
,
8127 struct link_params
*params
)
8131 struct bnx2x
*bp
= params
->bp
;
8133 /* Initialization time after hot-plug may take up to 300ms for
8134 * some phys type ( e.g. JDSU )
8137 for (timeout
= 0; timeout
< 60; timeout
++) {
8138 if (bnx2x_read_sfp_module_eeprom(phy
, params
, 1, 1, &val
)
8141 "SFP+ module initialization took %d ms\n",
8145 usleep_range(5000, 10000);
8150 static void bnx2x_8727_power_module(struct bnx2x
*bp
,
8151 struct bnx2x_phy
*phy
,
8153 /* Make sure GPIOs are not using for LED mode */
8155 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
8156 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
8158 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
8159 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
8160 * where the 1st bit is the over-current(only input), and 2nd bit is
8161 * for power( only output )
8163 * In case of NOC feature is disabled and power is up, set GPIO control
8164 * as input to enable listening of over-current indication
8166 if (phy
->flags
& FLAGS_NOC
)
8171 /* Set GPIO control to OUTPUT, and set the power bit
8172 * to according to the is_power_up
8176 bnx2x_cl45_write(bp
, phy
,
8178 MDIO_PMA_REG_8727_GPIO_CTRL
,
8182 static int bnx2x_8726_set_limiting_mode(struct bnx2x
*bp
,
8183 struct bnx2x_phy
*phy
,
8186 u16 cur_limiting_mode
;
8188 bnx2x_cl45_read(bp
, phy
,
8190 MDIO_PMA_REG_ROM_VER2
,
8191 &cur_limiting_mode
);
8192 DP(NETIF_MSG_LINK
, "Current Limiting mode is 0x%x\n",
8195 if (edc_mode
== EDC_MODE_LIMITING
) {
8196 DP(NETIF_MSG_LINK
, "Setting LIMITING MODE\n");
8197 bnx2x_cl45_write(bp
, phy
,
8199 MDIO_PMA_REG_ROM_VER2
,
8201 } else { /* LRM mode ( default )*/
8203 DP(NETIF_MSG_LINK
, "Setting LRM MODE\n");
8205 /* Changing to LRM mode takes quite few seconds. So do it only
8206 * if current mode is limiting (default is LRM)
8208 if (cur_limiting_mode
!= EDC_MODE_LIMITING
)
8211 bnx2x_cl45_write(bp
, phy
,
8213 MDIO_PMA_REG_LRM_MODE
,
8215 bnx2x_cl45_write(bp
, phy
,
8217 MDIO_PMA_REG_ROM_VER2
,
8219 bnx2x_cl45_write(bp
, phy
,
8221 MDIO_PMA_REG_MISC_CTRL0
,
8223 bnx2x_cl45_write(bp
, phy
,
8225 MDIO_PMA_REG_LRM_MODE
,
8231 static int bnx2x_8727_set_limiting_mode(struct bnx2x
*bp
,
8232 struct bnx2x_phy
*phy
,
8237 bnx2x_cl45_read(bp
, phy
,
8239 MDIO_PMA_REG_PHY_IDENTIFIER
,
8242 bnx2x_cl45_write(bp
, phy
,
8244 MDIO_PMA_REG_PHY_IDENTIFIER
,
8245 (phy_identifier
& ~(1<<9)));
8247 bnx2x_cl45_read(bp
, phy
,
8249 MDIO_PMA_REG_ROM_VER2
,
8251 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
8252 bnx2x_cl45_write(bp
, phy
,
8254 MDIO_PMA_REG_ROM_VER2
,
8255 (rom_ver2_val
& 0xff00) | (edc_mode
& 0x00ff));
8257 bnx2x_cl45_write(bp
, phy
,
8259 MDIO_PMA_REG_PHY_IDENTIFIER
,
8260 (phy_identifier
| (1<<9)));
8265 static void bnx2x_8727_specific_func(struct bnx2x_phy
*phy
,
8266 struct link_params
*params
,
8269 struct bnx2x
*bp
= params
->bp
;
8273 bnx2x_sfp_set_transmitter(params
, phy
, 0);
8276 if (!(phy
->flags
& FLAGS_SFP_NOT_APPROVED
))
8277 bnx2x_sfp_set_transmitter(params
, phy
, 1);
8280 DP(NETIF_MSG_LINK
, "Function 0x%x not supported by 8727\n",
8286 static void bnx2x_set_e1e2_module_fault_led(struct link_params
*params
,
8289 struct bnx2x
*bp
= params
->bp
;
8291 u32 fault_led_gpio
= REG_RD(bp
, params
->shmem_base
+
8292 offsetof(struct shmem_region
,
8293 dev_info
.port_hw_config
[params
->port
].sfp_ctrl
)) &
8294 PORT_HW_CFG_FAULT_MODULE_LED_MASK
;
8295 switch (fault_led_gpio
) {
8296 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED
:
8298 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0
:
8299 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1
:
8300 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2
:
8301 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3
:
8303 u8 gpio_port
= bnx2x_get_gpio_port(params
);
8304 u16 gpio_pin
= fault_led_gpio
-
8305 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0
;
8306 DP(NETIF_MSG_LINK
, "Set fault module-detected led "
8307 "pin %x port %x mode %x\n",
8308 gpio_pin
, gpio_port
, gpio_mode
);
8309 bnx2x_set_gpio(bp
, gpio_pin
, gpio_mode
, gpio_port
);
8313 DP(NETIF_MSG_LINK
, "Error: Invalid fault led mode 0x%x\n",
8318 static void bnx2x_set_e3_module_fault_led(struct link_params
*params
,
8322 u8 port
= params
->port
;
8323 struct bnx2x
*bp
= params
->bp
;
8324 pin_cfg
= (REG_RD(bp
, params
->shmem_base
+
8325 offsetof(struct shmem_region
,
8326 dev_info
.port_hw_config
[port
].e3_sfp_ctrl
)) &
8327 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK
) >>
8328 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT
;
8329 DP(NETIF_MSG_LINK
, "Setting Fault LED to %d using pin cfg %d\n",
8330 gpio_mode
, pin_cfg
);
8331 bnx2x_set_cfg_pin(bp
, pin_cfg
, gpio_mode
);
8334 static void bnx2x_set_sfp_module_fault_led(struct link_params
*params
,
8337 struct bnx2x
*bp
= params
->bp
;
8338 DP(NETIF_MSG_LINK
, "Setting SFP+ module fault LED to %d\n", gpio_mode
);
8339 if (CHIP_IS_E3(bp
)) {
8340 /* Low ==> if SFP+ module is supported otherwise
8341 * High ==> if SFP+ module is not on the approved vendor list
8343 bnx2x_set_e3_module_fault_led(params
, gpio_mode
);
8345 bnx2x_set_e1e2_module_fault_led(params
, gpio_mode
);
8348 static void bnx2x_warpcore_hw_reset(struct bnx2x_phy
*phy
,
8349 struct link_params
*params
)
8351 struct bnx2x
*bp
= params
->bp
;
8352 bnx2x_warpcore_power_module(params
, phy
, 0);
8353 /* Put Warpcore in low power mode */
8354 REG_WR(bp
, MISC_REG_WC0_RESET
, 0x0c0e);
8356 /* Put LCPLL in low power mode */
8357 REG_WR(bp
, MISC_REG_LCPLL_E40_PWRDWN
, 1);
8358 REG_WR(bp
, MISC_REG_LCPLL_E40_RESETB_ANA
, 0);
8359 REG_WR(bp
, MISC_REG_LCPLL_E40_RESETB_DIG
, 0);
8362 static void bnx2x_power_sfp_module(struct link_params
*params
,
8363 struct bnx2x_phy
*phy
,
8366 struct bnx2x
*bp
= params
->bp
;
8367 DP(NETIF_MSG_LINK
, "Setting SFP+ power to %x\n", power
);
8369 switch (phy
->type
) {
8370 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
8371 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722
:
8372 bnx2x_8727_power_module(params
->bp
, phy
, power
);
8374 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
8375 bnx2x_warpcore_power_module(params
, phy
, power
);
8381 static void bnx2x_warpcore_set_limiting_mode(struct link_params
*params
,
8382 struct bnx2x_phy
*phy
,
8386 u16 mode
= MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT
;
8387 struct bnx2x
*bp
= params
->bp
;
8389 u8 lane
= bnx2x_get_warpcore_lane(phy
, params
);
8390 /* This is a global register which controls all lanes */
8391 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
8392 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE
, &val
);
8393 val
&= ~(0xf << (lane
<< 2));
8396 case EDC_MODE_LINEAR
:
8397 case EDC_MODE_LIMITING
:
8398 mode
= MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT
;
8400 case EDC_MODE_PASSIVE_DAC
:
8401 mode
= MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC
;
8407 val
|= (mode
<< (lane
<< 2));
8408 bnx2x_cl45_write(bp
, phy
, MDIO_WC_DEVAD
,
8409 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE
, val
);
8411 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
8412 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE
, &val
);
8414 /* Restart microcode to re-read the new mode */
8415 bnx2x_warpcore_reset_lane(bp
, phy
, 1);
8416 bnx2x_warpcore_reset_lane(bp
, phy
, 0);
8420 static void bnx2x_set_limiting_mode(struct link_params
*params
,
8421 struct bnx2x_phy
*phy
,
8424 switch (phy
->type
) {
8425 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
8426 bnx2x_8726_set_limiting_mode(params
->bp
, phy
, edc_mode
);
8428 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
8429 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722
:
8430 bnx2x_8727_set_limiting_mode(params
->bp
, phy
, edc_mode
);
8432 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
:
8433 bnx2x_warpcore_set_limiting_mode(params
, phy
, edc_mode
);
8438 int bnx2x_sfp_module_detection(struct bnx2x_phy
*phy
,
8439 struct link_params
*params
)
8441 struct bnx2x
*bp
= params
->bp
;
8445 u32 val
= REG_RD(bp
, params
->shmem_base
+
8446 offsetof(struct shmem_region
, dev_info
.
8447 port_feature_config
[params
->port
].config
));
8449 DP(NETIF_MSG_LINK
, "SFP+ module plugged in/out detected on port %d\n",
8451 /* Power up module */
8452 bnx2x_power_sfp_module(params
, phy
, 1);
8453 if (bnx2x_get_edc_mode(phy
, params
, &edc_mode
) != 0) {
8454 DP(NETIF_MSG_LINK
, "Failed to get valid module type\n");
8456 } else if (bnx2x_verify_sfp_module(phy
, params
) != 0) {
8457 /* Check SFP+ module compatibility */
8458 DP(NETIF_MSG_LINK
, "Module verification failed!!\n");
8460 /* Turn on fault module-detected led */
8461 bnx2x_set_sfp_module_fault_led(params
,
8462 MISC_REGISTERS_GPIO_HIGH
);
8464 /* Check if need to power down the SFP+ module */
8465 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
8466 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN
) {
8467 DP(NETIF_MSG_LINK
, "Shutdown SFP+ module!!\n");
8468 bnx2x_power_sfp_module(params
, phy
, 0);
8472 /* Turn off fault module-detected led */
8473 bnx2x_set_sfp_module_fault_led(params
, MISC_REGISTERS_GPIO_LOW
);
8476 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
8477 * is done automatically
8479 bnx2x_set_limiting_mode(params
, phy
, edc_mode
);
8481 /* Enable transmit for this module if the module is approved, or
8482 * if unapproved modules should also enable the Tx laser
8485 (val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) !=
8486 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
8487 bnx2x_sfp_set_transmitter(params
, phy
, 1);
8489 bnx2x_sfp_set_transmitter(params
, phy
, 0);
8494 void bnx2x_handle_module_detect_int(struct link_params
*params
)
8496 struct bnx2x
*bp
= params
->bp
;
8497 struct bnx2x_phy
*phy
;
8499 u8 gpio_num
, gpio_port
;
8501 phy
= ¶ms
->phy
[INT_PHY
];
8503 phy
= ¶ms
->phy
[EXT_PHY1
];
8505 if (bnx2x_get_mod_abs_int_cfg(bp
, params
->chip_id
, params
->shmem_base
,
8506 params
->port
, &gpio_num
, &gpio_port
) ==
8508 DP(NETIF_MSG_LINK
, "Failed to get MOD_ABS interrupt config\n");
8512 /* Set valid module led off */
8513 bnx2x_set_sfp_module_fault_led(params
, MISC_REGISTERS_GPIO_HIGH
);
8515 /* Get current gpio val reflecting module plugged in / out*/
8516 gpio_val
= bnx2x_get_gpio(bp
, gpio_num
, gpio_port
);
8518 /* Call the handling function in case module is detected */
8519 if (gpio_val
== 0) {
8520 bnx2x_set_mdio_clk(bp
, params
->chip_id
, params
->port
);
8521 bnx2x_set_aer_mmd(params
, phy
);
8523 bnx2x_power_sfp_module(params
, phy
, 1);
8524 bnx2x_set_gpio_int(bp
, gpio_num
,
8525 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
,
8527 if (bnx2x_wait_for_sfp_module_initialized(phy
, params
) == 0) {
8528 bnx2x_sfp_module_detection(phy
, params
);
8529 if (CHIP_IS_E3(bp
)) {
8531 /* In case WC is out of reset, reconfigure the
8532 * link speed while taking into account 1G
8533 * module limitation.
8535 bnx2x_cl45_read(bp
, phy
,
8537 MDIO_WC_REG_DIGITAL5_MISC6
,
8539 if (!rx_tx_in_reset
) {
8540 bnx2x_warpcore_reset_lane(bp
, phy
, 1);
8541 bnx2x_warpcore_config_sfi(phy
, params
);
8542 bnx2x_warpcore_reset_lane(bp
, phy
, 0);
8546 DP(NETIF_MSG_LINK
, "SFP+ module is not initialized\n");
8549 u32 val
= REG_RD(bp
, params
->shmem_base
+
8550 offsetof(struct shmem_region
, dev_info
.
8551 port_feature_config
[params
->port
].
8553 bnx2x_set_gpio_int(bp
, gpio_num
,
8554 MISC_REGISTERS_GPIO_INT_OUTPUT_SET
,
8556 /* Module was plugged out.
8557 * Disable transmit for this module
8559 phy
->media_type
= ETH_PHY_NOT_PRESENT
;
8560 if (((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
8561 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
) ||
8563 bnx2x_sfp_set_transmitter(params
, phy
, 0);
8567 /******************************************************************/
8568 /* Used by 8706 and 8727 */
8569 /******************************************************************/
8570 static void bnx2x_sfp_mask_fault(struct bnx2x
*bp
,
8571 struct bnx2x_phy
*phy
,
8572 u16 alarm_status_offset
,
8573 u16 alarm_ctrl_offset
)
8575 u16 alarm_status
, val
;
8576 bnx2x_cl45_read(bp
, phy
,
8577 MDIO_PMA_DEVAD
, alarm_status_offset
,
8579 bnx2x_cl45_read(bp
, phy
,
8580 MDIO_PMA_DEVAD
, alarm_status_offset
,
8582 /* Mask or enable the fault event. */
8583 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
, alarm_ctrl_offset
, &val
);
8584 if (alarm_status
& (1<<0))
8588 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, alarm_ctrl_offset
, val
);
8590 /******************************************************************/
8591 /* common BCM8706/BCM8726 PHY SECTION */
8592 /******************************************************************/
8593 static u8
bnx2x_8706_8726_read_status(struct bnx2x_phy
*phy
,
8594 struct link_params
*params
,
8595 struct link_vars
*vars
)
8598 u16 val1
, val2
, rx_sd
, pcs_status
;
8599 struct bnx2x
*bp
= params
->bp
;
8600 DP(NETIF_MSG_LINK
, "XGXS 8706/8726\n");
8602 bnx2x_cl45_read(bp
, phy
,
8603 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &val2
);
8605 bnx2x_sfp_mask_fault(bp
, phy
, MDIO_PMA_LASI_TXSTAT
,
8606 MDIO_PMA_LASI_TXCTRL
);
8608 /* Clear LASI indication*/
8609 bnx2x_cl45_read(bp
, phy
,
8610 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
8611 bnx2x_cl45_read(bp
, phy
,
8612 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val2
);
8613 DP(NETIF_MSG_LINK
, "8706/8726 LASI status 0x%x--> 0x%x\n", val1
, val2
);
8615 bnx2x_cl45_read(bp
, phy
,
8616 MDIO_PMA_DEVAD
, MDIO_PMA_REG_RX_SD
, &rx_sd
);
8617 bnx2x_cl45_read(bp
, phy
,
8618 MDIO_PCS_DEVAD
, MDIO_PCS_REG_STATUS
, &pcs_status
);
8619 bnx2x_cl45_read(bp
, phy
,
8620 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &val2
);
8621 bnx2x_cl45_read(bp
, phy
,
8622 MDIO_AN_DEVAD
, MDIO_AN_REG_LINK_STATUS
, &val2
);
8624 DP(NETIF_MSG_LINK
, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
8625 " link_status 0x%x\n", rx_sd
, pcs_status
, val2
);
8626 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
8627 * are set, or if the autoneg bit 1 is set
8629 link_up
= ((rx_sd
& pcs_status
& 0x1) || (val2
& (1<<1)));
8632 vars
->line_speed
= SPEED_1000
;
8634 vars
->line_speed
= SPEED_10000
;
8635 bnx2x_ext_phy_resolve_fc(phy
, params
, vars
);
8636 vars
->duplex
= DUPLEX_FULL
;
8639 /* Capture 10G link fault. Read twice to clear stale value. */
8640 if (vars
->line_speed
== SPEED_10000
) {
8641 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
,
8642 MDIO_PMA_LASI_TXSTAT
, &val1
);
8643 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
,
8644 MDIO_PMA_LASI_TXSTAT
, &val1
);
8646 vars
->fault_detected
= 1;
8652 /******************************************************************/
8653 /* BCM8706 PHY SECTION */
8654 /******************************************************************/
8655 static u8
bnx2x_8706_config_init(struct bnx2x_phy
*phy
,
8656 struct link_params
*params
,
8657 struct link_vars
*vars
)
8661 struct bnx2x
*bp
= params
->bp
;
8663 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
8664 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
8666 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
8667 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0xa040);
8668 bnx2x_wait_reset_complete(bp
, phy
, params
);
8670 /* Wait until fw is loaded */
8671 for (cnt
= 0; cnt
< 100; cnt
++) {
8672 bnx2x_cl45_read(bp
, phy
,
8673 MDIO_PMA_DEVAD
, MDIO_PMA_REG_ROM_VER1
, &val
);
8676 usleep_range(10000, 20000);
8678 DP(NETIF_MSG_LINK
, "XGXS 8706 is initialized after %d ms\n", cnt
);
8679 if ((params
->feature_config_flags
&
8680 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
8683 for (i
= 0; i
< 4; i
++) {
8684 reg
= MDIO_XS_8706_REG_BANK_RX0
+
8685 i
*(MDIO_XS_8706_REG_BANK_RX1
-
8686 MDIO_XS_8706_REG_BANK_RX0
);
8687 bnx2x_cl45_read(bp
, phy
, MDIO_XS_DEVAD
, reg
, &val
);
8688 /* Clear first 3 bits of the control */
8690 /* Set control bits according to configuration */
8691 val
|= (phy
->rx_preemphasis
[i
] & 0x7);
8692 DP(NETIF_MSG_LINK
, "Setting RX Equalizer to BCM8706"
8693 " reg 0x%x <-- val 0x%x\n", reg
, val
);
8694 bnx2x_cl45_write(bp
, phy
, MDIO_XS_DEVAD
, reg
, val
);
8698 if (phy
->req_line_speed
== SPEED_10000
) {
8699 DP(NETIF_MSG_LINK
, "XGXS 8706 force 10Gbps\n");
8701 bnx2x_cl45_write(bp
, phy
,
8703 MDIO_PMA_REG_DIGITAL_CTRL
, 0x400);
8704 bnx2x_cl45_write(bp
, phy
,
8705 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_TXCTRL
,
8707 /* Arm LASI for link and Tx fault. */
8708 bnx2x_cl45_write(bp
, phy
,
8709 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 3);
8711 /* Force 1Gbps using autoneg with 1G advertisement */
8713 /* Allow CL37 through CL73 */
8714 DP(NETIF_MSG_LINK
, "XGXS 8706 AutoNeg\n");
8715 bnx2x_cl45_write(bp
, phy
,
8716 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_CL73
, 0x040c);
8718 /* Enable Full-Duplex advertisement on CL37 */
8719 bnx2x_cl45_write(bp
, phy
,
8720 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LP
, 0x0020);
8721 /* Enable CL37 AN */
8722 bnx2x_cl45_write(bp
, phy
,
8723 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1000);
8725 bnx2x_cl45_write(bp
, phy
,
8726 MDIO_AN_DEVAD
, MDIO_AN_REG_ADV
, (1<<5));
8728 /* Enable clause 73 AN */
8729 bnx2x_cl45_write(bp
, phy
,
8730 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x1200);
8731 bnx2x_cl45_write(bp
, phy
,
8732 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
8734 bnx2x_cl45_write(bp
, phy
,
8735 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
,
8738 bnx2x_save_bcm_spirom_ver(bp
, phy
, params
->port
);
8740 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
8741 * power mode, if TX Laser is disabled
8744 tx_en_mode
= REG_RD(bp
, params
->shmem_base
+
8745 offsetof(struct shmem_region
,
8746 dev_info
.port_hw_config
[params
->port
].sfp_ctrl
))
8747 & PORT_HW_CFG_TX_LASER_MASK
;
8749 if (tx_en_mode
== PORT_HW_CFG_TX_LASER_GPIO0
) {
8750 DP(NETIF_MSG_LINK
, "Enabling TXONOFF_PWRDN_DIS\n");
8751 bnx2x_cl45_read(bp
, phy
,
8752 MDIO_PMA_DEVAD
, MDIO_PMA_REG_DIGITAL_CTRL
, &tmp1
);
8754 bnx2x_cl45_write(bp
, phy
,
8755 MDIO_PMA_DEVAD
, MDIO_PMA_REG_DIGITAL_CTRL
, tmp1
);
8761 static int bnx2x_8706_read_status(struct bnx2x_phy
*phy
,
8762 struct link_params
*params
,
8763 struct link_vars
*vars
)
8765 return bnx2x_8706_8726_read_status(phy
, params
, vars
);
8768 /******************************************************************/
8769 /* BCM8726 PHY SECTION */
8770 /******************************************************************/
8771 static void bnx2x_8726_config_loopback(struct bnx2x_phy
*phy
,
8772 struct link_params
*params
)
8774 struct bnx2x
*bp
= params
->bp
;
8775 DP(NETIF_MSG_LINK
, "PMA/PMD ext_phy_loopback: 8726\n");
8776 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x0001);
8779 static void bnx2x_8726_external_rom_boot(struct bnx2x_phy
*phy
,
8780 struct link_params
*params
)
8782 struct bnx2x
*bp
= params
->bp
;
8783 /* Need to wait 100ms after reset */
8786 /* Micro controller re-boot */
8787 bnx2x_cl45_write(bp
, phy
,
8788 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x018B);
8790 /* Set soft reset */
8791 bnx2x_cl45_write(bp
, phy
,
8793 MDIO_PMA_REG_GEN_CTRL
,
8794 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET
);
8796 bnx2x_cl45_write(bp
, phy
,
8798 MDIO_PMA_REG_MISC_CTRL1
, 0x0001);
8800 bnx2x_cl45_write(bp
, phy
,
8802 MDIO_PMA_REG_GEN_CTRL
,
8803 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP
);
8805 /* Wait for 150ms for microcode load */
8808 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
8809 bnx2x_cl45_write(bp
, phy
,
8811 MDIO_PMA_REG_MISC_CTRL1
, 0x0000);
8814 bnx2x_save_bcm_spirom_ver(bp
, phy
, params
->port
);
8817 static u8
bnx2x_8726_read_status(struct bnx2x_phy
*phy
,
8818 struct link_params
*params
,
8819 struct link_vars
*vars
)
8821 struct bnx2x
*bp
= params
->bp
;
8823 u8 link_up
= bnx2x_8706_8726_read_status(phy
, params
, vars
);
8825 bnx2x_cl45_read(bp
, phy
,
8826 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
,
8828 if (val1
& (1<<15)) {
8829 DP(NETIF_MSG_LINK
, "Tx is disabled\n");
8831 vars
->line_speed
= 0;
8838 static int bnx2x_8726_config_init(struct bnx2x_phy
*phy
,
8839 struct link_params
*params
,
8840 struct link_vars
*vars
)
8842 struct bnx2x
*bp
= params
->bp
;
8843 DP(NETIF_MSG_LINK
, "Initializing BCM8726\n");
8845 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1<<15);
8846 bnx2x_wait_reset_complete(bp
, phy
, params
);
8848 bnx2x_8726_external_rom_boot(phy
, params
);
8850 /* Need to call module detected on initialization since the module
8851 * detection triggered by actual module insertion might occur before
8852 * driver is loaded, and when driver is loaded, it reset all
8853 * registers, including the transmitter
8855 bnx2x_sfp_module_detection(phy
, params
);
8857 if (phy
->req_line_speed
== SPEED_1000
) {
8858 DP(NETIF_MSG_LINK
, "Setting 1G force\n");
8859 bnx2x_cl45_write(bp
, phy
,
8860 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x40);
8861 bnx2x_cl45_write(bp
, phy
,
8862 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, 0xD);
8863 bnx2x_cl45_write(bp
, phy
,
8864 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x5);
8865 bnx2x_cl45_write(bp
, phy
,
8866 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
8868 } else if ((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
8869 (phy
->speed_cap_mask
&
8870 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
) &&
8871 ((phy
->speed_cap_mask
&
8872 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
) !=
8873 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
8874 DP(NETIF_MSG_LINK
, "Setting 1G clause37\n");
8875 /* Set Flow control */
8876 bnx2x_ext_phy_set_pause(params
, phy
, vars
);
8877 bnx2x_cl45_write(bp
, phy
,
8878 MDIO_AN_DEVAD
, MDIO_AN_REG_ADV
, 0x20);
8879 bnx2x_cl45_write(bp
, phy
,
8880 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_CL73
, 0x040c);
8881 bnx2x_cl45_write(bp
, phy
,
8882 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_FC_LD
, 0x0020);
8883 bnx2x_cl45_write(bp
, phy
,
8884 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1000);
8885 bnx2x_cl45_write(bp
, phy
,
8886 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x1200);
8887 /* Enable RX-ALARM control to receive interrupt for 1G speed
8890 bnx2x_cl45_write(bp
, phy
,
8891 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x4);
8892 bnx2x_cl45_write(bp
, phy
,
8893 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
8896 } else { /* Default 10G. Set only LASI control */
8897 bnx2x_cl45_write(bp
, phy
,
8898 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 1);
8901 /* Set TX PreEmphasis if needed */
8902 if ((params
->feature_config_flags
&
8903 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
8905 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
8906 phy
->tx_preemphasis
[0],
8907 phy
->tx_preemphasis
[1]);
8908 bnx2x_cl45_write(bp
, phy
,
8910 MDIO_PMA_REG_8726_TX_CTRL1
,
8911 phy
->tx_preemphasis
[0]);
8913 bnx2x_cl45_write(bp
, phy
,
8915 MDIO_PMA_REG_8726_TX_CTRL2
,
8916 phy
->tx_preemphasis
[1]);
8923 static void bnx2x_8726_link_reset(struct bnx2x_phy
*phy
,
8924 struct link_params
*params
)
8926 struct bnx2x
*bp
= params
->bp
;
8927 DP(NETIF_MSG_LINK
, "bnx2x_8726_link_reset port %d\n", params
->port
);
8928 /* Set serial boot control for external load */
8929 bnx2x_cl45_write(bp
, phy
,
8931 MDIO_PMA_REG_GEN_CTRL
, 0x0001);
8934 /******************************************************************/
8935 /* BCM8727 PHY SECTION */
8936 /******************************************************************/
8938 static void bnx2x_8727_set_link_led(struct bnx2x_phy
*phy
,
8939 struct link_params
*params
, u8 mode
)
8941 struct bnx2x
*bp
= params
->bp
;
8942 u16 led_mode_bitmask
= 0;
8943 u16 gpio_pins_bitmask
= 0;
8945 /* Only NOC flavor requires to set the LED specifically */
8946 if (!(phy
->flags
& FLAGS_NOC
))
8949 case LED_MODE_FRONT_PANEL_OFF
:
8951 led_mode_bitmask
= 0;
8952 gpio_pins_bitmask
= 0x03;
8955 led_mode_bitmask
= 0;
8956 gpio_pins_bitmask
= 0x02;
8959 led_mode_bitmask
= 0x60;
8960 gpio_pins_bitmask
= 0x11;
8963 bnx2x_cl45_read(bp
, phy
,
8965 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
8968 val
|= led_mode_bitmask
;
8969 bnx2x_cl45_write(bp
, phy
,
8971 MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
8973 bnx2x_cl45_read(bp
, phy
,
8975 MDIO_PMA_REG_8727_GPIO_CTRL
,
8978 val
|= gpio_pins_bitmask
;
8979 bnx2x_cl45_write(bp
, phy
,
8981 MDIO_PMA_REG_8727_GPIO_CTRL
,
8984 static void bnx2x_8727_hw_reset(struct bnx2x_phy
*phy
,
8985 struct link_params
*params
) {
8986 u32 swap_val
, swap_override
;
8988 /* The PHY reset is controlled by GPIO 1. Fake the port number
8989 * to cancel the swap done in set_gpio()
8991 struct bnx2x
*bp
= params
->bp
;
8992 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
8993 swap_override
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
8994 port
= (swap_val
&& swap_override
) ^ 1;
8995 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_1
,
8996 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
8999 static void bnx2x_8727_config_speed(struct bnx2x_phy
*phy
,
9000 struct link_params
*params
)
9002 struct bnx2x
*bp
= params
->bp
;
9004 /* Set option 1G speed */
9005 if ((phy
->req_line_speed
== SPEED_1000
) ||
9006 (phy
->media_type
== ETH_PHY_SFP_1G_FIBER
)) {
9007 DP(NETIF_MSG_LINK
, "Setting 1G force\n");
9008 bnx2x_cl45_write(bp
, phy
,
9009 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x40);
9010 bnx2x_cl45_write(bp
, phy
,
9011 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, 0xD);
9012 bnx2x_cl45_read(bp
, phy
,
9013 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
, &tmp1
);
9014 DP(NETIF_MSG_LINK
, "1.7 = 0x%x\n", tmp1
);
9015 /* Power down the XAUI until link is up in case of dual-media
9018 if (DUAL_MEDIA(params
)) {
9019 bnx2x_cl45_read(bp
, phy
,
9021 MDIO_PMA_REG_8727_PCS_GP
, &val
);
9023 bnx2x_cl45_write(bp
, phy
,
9025 MDIO_PMA_REG_8727_PCS_GP
, val
);
9027 } else if ((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
9028 ((phy
->speed_cap_mask
&
9029 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) &&
9030 ((phy
->speed_cap_mask
&
9031 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
) !=
9032 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) {
9034 DP(NETIF_MSG_LINK
, "Setting 1G clause37\n");
9035 bnx2x_cl45_write(bp
, phy
,
9036 MDIO_AN_DEVAD
, MDIO_AN_REG_8727_MISC_CTRL
, 0);
9037 bnx2x_cl45_write(bp
, phy
,
9038 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x1300);
9040 /* Since the 8727 has only single reset pin, need to set the 10G
9041 * registers although it is default
9043 bnx2x_cl45_write(bp
, phy
,
9044 MDIO_AN_DEVAD
, MDIO_AN_REG_8727_MISC_CTRL
,
9046 bnx2x_cl45_write(bp
, phy
,
9047 MDIO_AN_DEVAD
, MDIO_AN_REG_CL37_AN
, 0x0100);
9048 bnx2x_cl45_write(bp
, phy
,
9049 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x2040);
9050 bnx2x_cl45_write(bp
, phy
,
9051 MDIO_PMA_DEVAD
, MDIO_PMA_REG_10G_CTRL2
,
9056 static int bnx2x_8727_config_init(struct bnx2x_phy
*phy
,
9057 struct link_params
*params
,
9058 struct link_vars
*vars
)
9061 u16 tmp1
, val
, mod_abs
, tmp2
;
9062 u16 rx_alarm_ctrl_val
;
9064 struct bnx2x
*bp
= params
->bp
;
9065 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
9067 bnx2x_wait_reset_complete(bp
, phy
, params
);
9068 rx_alarm_ctrl_val
= (1<<2) | (1<<5) ;
9069 /* Should be 0x6 to enable XS on Tx side. */
9070 lasi_ctrl_val
= 0x0006;
9072 DP(NETIF_MSG_LINK
, "Initializing BCM8727\n");
9074 bnx2x_cl45_write(bp
, phy
,
9075 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
9077 bnx2x_cl45_write(bp
, phy
,
9078 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_TXCTRL
,
9080 bnx2x_cl45_write(bp
, phy
,
9081 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, lasi_ctrl_val
);
9083 /* Initially configure MOD_ABS to interrupt when module is
9086 bnx2x_cl45_read(bp
, phy
,
9087 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
, &mod_abs
);
9088 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
9089 * When the EDC is off it locks onto a reference clock and avoids
9093 if (!(phy
->flags
& FLAGS_NOC
))
9095 bnx2x_cl45_write(bp
, phy
,
9096 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
9099 /* Enable/Disable PHY transmitter output */
9100 bnx2x_set_disable_pmd_transmit(params
, phy
, 0);
9102 /* Make MOD_ABS give interrupt on change */
9103 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_PCS_OPT_CTRL
,
9106 if (phy
->flags
& FLAGS_NOC
)
9109 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9110 * status which reflect SFP+ module over-current
9112 if (!(phy
->flags
& FLAGS_NOC
))
9113 val
&= 0xff8f; /* Reset bits 4-6 */
9114 bnx2x_cl45_write(bp
, phy
,
9115 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_PCS_OPT_CTRL
, val
);
9117 bnx2x_8727_power_module(bp
, phy
, 1);
9119 bnx2x_cl45_read(bp
, phy
,
9120 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &tmp1
);
9122 bnx2x_cl45_read(bp
, phy
,
9123 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
, &tmp1
);
9125 bnx2x_8727_config_speed(phy
, params
);
9126 /* Set 2-wire transfer rate of SFP+ module EEPROM
9127 * to 100Khz since some DACs(direct attached cables) do
9128 * not work at 400Khz.
9130 bnx2x_cl45_write(bp
, phy
,
9131 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR
,
9134 /* Set TX PreEmphasis if needed */
9135 if ((params
->feature_config_flags
&
9136 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
)) {
9137 DP(NETIF_MSG_LINK
, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
9138 phy
->tx_preemphasis
[0],
9139 phy
->tx_preemphasis
[1]);
9140 bnx2x_cl45_write(bp
, phy
,
9141 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_TX_CTRL1
,
9142 phy
->tx_preemphasis
[0]);
9144 bnx2x_cl45_write(bp
, phy
,
9145 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_TX_CTRL2
,
9146 phy
->tx_preemphasis
[1]);
9149 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9150 * power mode, if TX Laser is disabled
9152 tx_en_mode
= REG_RD(bp
, params
->shmem_base
+
9153 offsetof(struct shmem_region
,
9154 dev_info
.port_hw_config
[params
->port
].sfp_ctrl
))
9155 & PORT_HW_CFG_TX_LASER_MASK
;
9157 if (tx_en_mode
== PORT_HW_CFG_TX_LASER_GPIO0
) {
9159 DP(NETIF_MSG_LINK
, "Enabling TXONOFF_PWRDN_DIS\n");
9160 bnx2x_cl45_read(bp
, phy
,
9161 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_OPT_CFG_REG
, &tmp2
);
9164 bnx2x_cl45_write(bp
, phy
,
9165 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_OPT_CFG_REG
, tmp2
);
9166 bnx2x_cl45_read(bp
, phy
,
9167 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
,
9169 bnx2x_cl45_write(bp
, phy
,
9170 MDIO_PMA_DEVAD
, MDIO_PMA_REG_PHY_IDENTIFIER
,
9177 static void bnx2x_8727_handle_mod_abs(struct bnx2x_phy
*phy
,
9178 struct link_params
*params
)
9180 struct bnx2x
*bp
= params
->bp
;
9181 u16 mod_abs
, rx_alarm_status
;
9182 u32 val
= REG_RD(bp
, params
->shmem_base
+
9183 offsetof(struct shmem_region
, dev_info
.
9184 port_feature_config
[params
->port
].
9186 bnx2x_cl45_read(bp
, phy
,
9188 MDIO_PMA_REG_PHY_IDENTIFIER
, &mod_abs
);
9189 if (mod_abs
& (1<<8)) {
9191 /* Module is absent */
9193 "MOD_ABS indication show module is absent\n");
9194 phy
->media_type
= ETH_PHY_NOT_PRESENT
;
9195 /* 1. Set mod_abs to detect next module
9197 * 2. Set EDC off by setting OPTXLOS signal input to low
9199 * When the EDC is off it locks onto a reference clock and
9200 * avoids becoming 'lost'.
9203 if (!(phy
->flags
& FLAGS_NOC
))
9205 bnx2x_cl45_write(bp
, phy
,
9207 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
9209 /* Clear RX alarm since it stays up as long as
9210 * the mod_abs wasn't changed
9212 bnx2x_cl45_read(bp
, phy
,
9214 MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
9217 /* Module is present */
9219 "MOD_ABS indication show module is present\n");
9220 /* First disable transmitter, and if the module is ok, the
9221 * module_detection will enable it
9222 * 1. Set mod_abs to detect next module absent event ( bit 8)
9223 * 2. Restore the default polarity of the OPRXLOS signal and
9224 * this signal will then correctly indicate the presence or
9225 * absence of the Rx signal. (bit 9)
9228 if (!(phy
->flags
& FLAGS_NOC
))
9230 bnx2x_cl45_write(bp
, phy
,
9232 MDIO_PMA_REG_PHY_IDENTIFIER
, mod_abs
);
9234 /* Clear RX alarm since it stays up as long as the mod_abs
9235 * wasn't changed. This is need to be done before calling the
9236 * module detection, otherwise it will clear* the link update
9239 bnx2x_cl45_read(bp
, phy
,
9241 MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
9244 if ((val
& PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK
) ==
9245 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER
)
9246 bnx2x_sfp_set_transmitter(params
, phy
, 0);
9248 if (bnx2x_wait_for_sfp_module_initialized(phy
, params
) == 0)
9249 bnx2x_sfp_module_detection(phy
, params
);
9251 DP(NETIF_MSG_LINK
, "SFP+ module is not initialized\n");
9253 /* Reconfigure link speed based on module type limitations */
9254 bnx2x_8727_config_speed(phy
, params
);
9257 DP(NETIF_MSG_LINK
, "8727 RX_ALARM_STATUS 0x%x\n",
9259 /* No need to check link status in case of module plugged in/out */
9262 static u8
bnx2x_8727_read_status(struct bnx2x_phy
*phy
,
9263 struct link_params
*params
,
9264 struct link_vars
*vars
)
9267 struct bnx2x
*bp
= params
->bp
;
9268 u8 link_up
= 0, oc_port
= params
->port
;
9269 u16 link_status
= 0;
9270 u16 rx_alarm_status
, lasi_ctrl
, val1
;
9272 /* If PHY is not initialized, do not check link status */
9273 bnx2x_cl45_read(bp
, phy
,
9274 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
,
9279 /* Check the LASI on Rx */
9280 bnx2x_cl45_read(bp
, phy
,
9281 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXSTAT
,
9283 vars
->line_speed
= 0;
9284 DP(NETIF_MSG_LINK
, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status
);
9286 bnx2x_sfp_mask_fault(bp
, phy
, MDIO_PMA_LASI_TXSTAT
,
9287 MDIO_PMA_LASI_TXCTRL
);
9289 bnx2x_cl45_read(bp
, phy
,
9290 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
9292 DP(NETIF_MSG_LINK
, "8727 LASI status 0x%x\n", val1
);
9295 bnx2x_cl45_read(bp
, phy
,
9296 MDIO_PMA_DEVAD
, MDIO_PMA_REG_M8051_MSGOUT_REG
, &val1
);
9298 /* If a module is present and there is need to check
9301 if (!(phy
->flags
& FLAGS_NOC
) && !(rx_alarm_status
& (1<<5))) {
9302 /* Check over-current using 8727 GPIO0 input*/
9303 bnx2x_cl45_read(bp
, phy
,
9304 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8727_GPIO_CTRL
,
9307 if ((val1
& (1<<8)) == 0) {
9308 if (!CHIP_IS_E1x(bp
))
9309 oc_port
= BP_PATH(bp
) + (params
->port
<< 1);
9311 "8727 Power fault has been detected on port %d\n",
9313 netdev_err(bp
->dev
, "Error: Power fault on Port %d has "
9314 "been detected and the power to "
9315 "that SFP+ module has been removed "
9316 "to prevent failure of the card. "
9317 "Please remove the SFP+ module and "
9318 "restart the system to clear this "
9321 /* Disable all RX_ALARMs except for mod_abs */
9322 bnx2x_cl45_write(bp
, phy
,
9324 MDIO_PMA_LASI_RXCTRL
, (1<<5));
9326 bnx2x_cl45_read(bp
, phy
,
9328 MDIO_PMA_REG_PHY_IDENTIFIER
, &val1
);
9329 /* Wait for module_absent_event */
9331 bnx2x_cl45_write(bp
, phy
,
9333 MDIO_PMA_REG_PHY_IDENTIFIER
, val1
);
9334 /* Clear RX alarm */
9335 bnx2x_cl45_read(bp
, phy
,
9337 MDIO_PMA_LASI_RXSTAT
, &rx_alarm_status
);
9340 } /* Over current check */
9342 /* When module absent bit is set, check module */
9343 if (rx_alarm_status
& (1<<5)) {
9344 bnx2x_8727_handle_mod_abs(phy
, params
);
9345 /* Enable all mod_abs and link detection bits */
9346 bnx2x_cl45_write(bp
, phy
,
9347 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_RXCTRL
,
9351 if (!(phy
->flags
& FLAGS_SFP_NOT_APPROVED
)) {
9352 DP(NETIF_MSG_LINK
, "Enabling 8727 TX laser\n");
9353 bnx2x_sfp_set_transmitter(params
, phy
, 1);
9355 DP(NETIF_MSG_LINK
, "Tx is disabled\n");
9359 bnx2x_cl45_read(bp
, phy
,
9361 MDIO_PMA_REG_8073_SPEED_LINK_STATUS
, &link_status
);
9363 /* Bits 0..2 --> speed detected,
9364 * Bits 13..15--> link is down
9366 if ((link_status
& (1<<2)) && (!(link_status
& (1<<15)))) {
9368 vars
->line_speed
= SPEED_10000
;
9369 DP(NETIF_MSG_LINK
, "port %x: External link up in 10G\n",
9371 } else if ((link_status
& (1<<0)) && (!(link_status
& (1<<13)))) {
9373 vars
->line_speed
= SPEED_1000
;
9374 DP(NETIF_MSG_LINK
, "port %x: External link up in 1G\n",
9378 DP(NETIF_MSG_LINK
, "port %x: External link is down\n",
9382 /* Capture 10G link fault. */
9383 if (vars
->line_speed
== SPEED_10000
) {
9384 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
,
9385 MDIO_PMA_LASI_TXSTAT
, &val1
);
9387 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
,
9388 MDIO_PMA_LASI_TXSTAT
, &val1
);
9390 if (val1
& (1<<0)) {
9391 vars
->fault_detected
= 1;
9396 bnx2x_ext_phy_resolve_fc(phy
, params
, vars
);
9397 vars
->duplex
= DUPLEX_FULL
;
9398 DP(NETIF_MSG_LINK
, "duplex = 0x%x\n", vars
->duplex
);
9401 if ((DUAL_MEDIA(params
)) &&
9402 (phy
->req_line_speed
== SPEED_1000
)) {
9403 bnx2x_cl45_read(bp
, phy
,
9405 MDIO_PMA_REG_8727_PCS_GP
, &val1
);
9406 /* In case of dual-media board and 1G, power up the XAUI side,
9407 * otherwise power it down. For 10G it is done automatically
9413 bnx2x_cl45_write(bp
, phy
,
9415 MDIO_PMA_REG_8727_PCS_GP
, val1
);
9420 static void bnx2x_8727_link_reset(struct bnx2x_phy
*phy
,
9421 struct link_params
*params
)
9423 struct bnx2x
*bp
= params
->bp
;
9425 /* Enable/Disable PHY transmitter output */
9426 bnx2x_set_disable_pmd_transmit(params
, phy
, 1);
9428 /* Disable Transmitter */
9429 bnx2x_sfp_set_transmitter(params
, phy
, 0);
9431 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0);
9435 /******************************************************************/
9436 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
9437 /******************************************************************/
9438 static void bnx2x_save_848xx_spirom_version(struct bnx2x_phy
*phy
,
9442 u16 val
, fw_ver1
, fw_ver2
, cnt
;
9444 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
) {
9445 bnx2x_cl45_read(bp
, phy
, MDIO_CTL_DEVAD
, 0x400f, &fw_ver1
);
9446 bnx2x_save_spirom_version(bp
, port
, fw_ver1
& 0xfff,
9449 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
9450 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
9451 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, 0xA819, 0x0014);
9452 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, 0xA81A, 0xc200);
9453 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, 0xA81B, 0x0000);
9454 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, 0xA81C, 0x0300);
9455 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, 0xA817, 0x0009);
9457 for (cnt
= 0; cnt
< 100; cnt
++) {
9458 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
, 0xA818, &val
);
9464 DP(NETIF_MSG_LINK
, "Unable to read 848xx "
9465 "phy fw version(1)\n");
9466 bnx2x_save_spirom_version(bp
, port
, 0,
9472 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
9473 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, 0xA819, 0x0000);
9474 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, 0xA81A, 0xc200);
9475 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, 0xA817, 0x000A);
9476 for (cnt
= 0; cnt
< 100; cnt
++) {
9477 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
, 0xA818, &val
);
9483 DP(NETIF_MSG_LINK
, "Unable to read 848xx phy fw "
9485 bnx2x_save_spirom_version(bp
, port
, 0,
9490 /* lower 16 bits of the register SPI_FW_STATUS */
9491 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
, 0xA81B, &fw_ver1
);
9492 /* upper 16 bits of register SPI_FW_STATUS */
9493 bnx2x_cl45_read(bp
, phy
, MDIO_PMA_DEVAD
, 0xA81C, &fw_ver2
);
9495 bnx2x_save_spirom_version(bp
, port
, (fw_ver2
<<16) | fw_ver1
,
9500 static void bnx2x_848xx_set_led(struct bnx2x
*bp
,
9501 struct bnx2x_phy
*phy
)
9505 /* PHYC_CTL_LED_CTL */
9506 bnx2x_cl45_read(bp
, phy
,
9508 MDIO_PMA_REG_8481_LINK_SIGNAL
, &val
);
9512 bnx2x_cl45_write(bp
, phy
,
9514 MDIO_PMA_REG_8481_LINK_SIGNAL
, val
);
9516 bnx2x_cl45_write(bp
, phy
,
9518 MDIO_PMA_REG_8481_LED1_MASK
,
9521 bnx2x_cl45_write(bp
, phy
,
9523 MDIO_PMA_REG_8481_LED2_MASK
,
9526 /* Select activity source by Tx and Rx, as suggested by PHY AE */
9527 bnx2x_cl45_write(bp
, phy
,
9529 MDIO_PMA_REG_8481_LED3_MASK
,
9532 /* Select the closest activity blink rate to that in 10/100/1000 */
9533 bnx2x_cl45_write(bp
, phy
,
9535 MDIO_PMA_REG_8481_LED3_BLINK
,
9538 /* Configure the blink rate to ~15.9 Hz */
9539 bnx2x_cl45_write(bp
, phy
,
9541 MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH
,
9542 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ
);
9544 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
)
9545 offset
= MDIO_PMA_REG_84833_CTL_LED_CTL_1
;
9547 offset
= MDIO_PMA_REG_84823_CTL_LED_CTL_1
;
9549 bnx2x_cl45_read(bp
, phy
,
9550 MDIO_PMA_DEVAD
, offset
, &val
);
9551 val
|= MDIO_PMA_REG_84823_LED3_STRETCH_EN
; /* stretch_en for LED3*/
9552 bnx2x_cl45_write(bp
, phy
,
9553 MDIO_PMA_DEVAD
, offset
, val
);
9555 /* 'Interrupt Mask' */
9556 bnx2x_cl45_write(bp
, phy
,
9561 static int bnx2x_848xx_cmn_config_init(struct bnx2x_phy
*phy
,
9562 struct link_params
*params
,
9563 struct link_vars
*vars
)
9565 struct bnx2x
*bp
= params
->bp
;
9566 u16 autoneg_val
, an_1000_val
, an_10_100_val
, an_10g_val
;
9568 if (phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
) {
9569 /* Save spirom version */
9570 bnx2x_save_848xx_spirom_version(phy
, bp
, params
->port
);
9572 /* This phy uses the NIG latch mechanism since link indication
9573 * arrives through its LED4 and not via its LASI signal, so we
9574 * get steady signal instead of clear on read
9576 bnx2x_bits_en(bp
, NIG_REG_LATCH_BC_0
+ params
->port
*4,
9577 1 << NIG_LATCH_BC_ENABLE_MI_INT
);
9579 bnx2x_cl45_write(bp
, phy
,
9580 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 0x0000);
9582 bnx2x_848xx_set_led(bp
, phy
);
9584 /* set 1000 speed advertisement */
9585 bnx2x_cl45_read(bp
, phy
,
9586 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_1000T_CTRL
,
9589 bnx2x_ext_phy_set_pause(params
, phy
, vars
);
9590 bnx2x_cl45_read(bp
, phy
,
9592 MDIO_AN_REG_8481_LEGACY_AN_ADV
,
9594 bnx2x_cl45_read(bp
, phy
,
9595 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
9597 /* Disable forced speed */
9598 autoneg_val
&= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
9599 an_10_100_val
&= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
9601 if (((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
9602 (phy
->speed_cap_mask
&
9603 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
9604 (phy
->req_line_speed
== SPEED_1000
)) {
9605 an_1000_val
|= (1<<8);
9606 autoneg_val
|= (1<<9 | 1<<12);
9607 if (phy
->req_duplex
== DUPLEX_FULL
)
9608 an_1000_val
|= (1<<9);
9609 DP(NETIF_MSG_LINK
, "Advertising 1G\n");
9611 an_1000_val
&= ~((1<<8) | (1<<9));
9613 bnx2x_cl45_write(bp
, phy
,
9614 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_1000T_CTRL
,
9617 /* set 100 speed advertisement */
9618 if ((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
9619 (phy
->speed_cap_mask
&
9620 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
|
9621 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))) {
9622 an_10_100_val
|= (1<<7);
9623 /* Enable autoneg and restart autoneg for legacy speeds */
9624 autoneg_val
|= (1<<9 | 1<<12);
9626 if (phy
->req_duplex
== DUPLEX_FULL
)
9627 an_10_100_val
|= (1<<8);
9628 DP(NETIF_MSG_LINK
, "Advertising 100M\n");
9630 /* set 10 speed advertisement */
9631 if (((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
9632 (phy
->speed_cap_mask
&
9633 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
|
9634 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
)) &&
9636 (SUPPORTED_10baseT_Half
|
9637 SUPPORTED_10baseT_Full
)))) {
9638 an_10_100_val
|= (1<<5);
9639 autoneg_val
|= (1<<9 | 1<<12);
9640 if (phy
->req_duplex
== DUPLEX_FULL
)
9641 an_10_100_val
|= (1<<6);
9642 DP(NETIF_MSG_LINK
, "Advertising 10M\n");
9645 /* Only 10/100 are allowed to work in FORCE mode */
9646 if ((phy
->req_line_speed
== SPEED_100
) &&
9648 (SUPPORTED_100baseT_Half
|
9649 SUPPORTED_100baseT_Full
))) {
9650 autoneg_val
|= (1<<13);
9651 /* Enabled AUTO-MDIX when autoneg is disabled */
9652 bnx2x_cl45_write(bp
, phy
,
9653 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_AUX_CTRL
,
9654 (1<<15 | 1<<9 | 7<<0));
9655 /* The PHY needs this set even for forced link. */
9656 an_10_100_val
|= (1<<8) | (1<<7);
9657 DP(NETIF_MSG_LINK
, "Setting 100M force\n");
9659 if ((phy
->req_line_speed
== SPEED_10
) &&
9661 (SUPPORTED_10baseT_Half
|
9662 SUPPORTED_10baseT_Full
))) {
9663 /* Enabled AUTO-MDIX when autoneg is disabled */
9664 bnx2x_cl45_write(bp
, phy
,
9665 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_AUX_CTRL
,
9666 (1<<15 | 1<<9 | 7<<0));
9667 DP(NETIF_MSG_LINK
, "Setting 10M force\n");
9670 bnx2x_cl45_write(bp
, phy
,
9671 MDIO_AN_DEVAD
, MDIO_AN_REG_8481_LEGACY_AN_ADV
,
9674 if (phy
->req_duplex
== DUPLEX_FULL
)
9675 autoneg_val
|= (1<<8);
9677 /* Always write this if this is not 84833.
9678 * For 84833, write it only when it's a forced speed.
9680 if ((phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
) ||
9681 ((autoneg_val
& (1<<12)) == 0))
9682 bnx2x_cl45_write(bp
, phy
,
9684 MDIO_AN_REG_8481_LEGACY_MII_CTRL
, autoneg_val
);
9686 if (((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
9687 (phy
->speed_cap_mask
&
9688 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)) ||
9689 (phy
->req_line_speed
== SPEED_10000
)) {
9690 DP(NETIF_MSG_LINK
, "Advertising 10G\n");
9691 /* Restart autoneg for 10G*/
9693 bnx2x_cl45_read(bp
, phy
,
9695 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL
,
9697 bnx2x_cl45_write(bp
, phy
,
9699 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL
,
9700 an_10g_val
| 0x1000);
9701 bnx2x_cl45_write(bp
, phy
,
9702 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
,
9705 bnx2x_cl45_write(bp
, phy
,
9707 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL
,
9713 static int bnx2x_8481_config_init(struct bnx2x_phy
*phy
,
9714 struct link_params
*params
,
9715 struct link_vars
*vars
)
9717 struct bnx2x
*bp
= params
->bp
;
9718 /* Restore normal power mode*/
9719 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
9720 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
9723 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
9724 bnx2x_wait_reset_complete(bp
, phy
, params
);
9726 bnx2x_cl45_write(bp
, phy
, MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1<<15);
9727 return bnx2x_848xx_cmn_config_init(phy
, params
, vars
);
9730 #define PHY84833_CMDHDLR_WAIT 300
9731 #define PHY84833_CMDHDLR_MAX_ARGS 5
9732 static int bnx2x_84833_cmd_hdlr(struct bnx2x_phy
*phy
,
9733 struct link_params
*params
,
9735 u16 cmd_args
[], int argc
)
9739 struct bnx2x
*bp
= params
->bp
;
9740 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
9741 bnx2x_cl45_write(bp
, phy
, MDIO_CTL_DEVAD
,
9742 MDIO_84833_CMD_HDLR_STATUS
,
9743 PHY84833_STATUS_CMD_OPEN_OVERRIDE
);
9744 for (idx
= 0; idx
< PHY84833_CMDHDLR_WAIT
; idx
++) {
9745 bnx2x_cl45_read(bp
, phy
, MDIO_CTL_DEVAD
,
9746 MDIO_84833_CMD_HDLR_STATUS
, &val
);
9747 if (val
== PHY84833_STATUS_CMD_OPEN_FOR_CMDS
)
9749 usleep_range(1000, 2000);
9751 if (idx
>= PHY84833_CMDHDLR_WAIT
) {
9752 DP(NETIF_MSG_LINK
, "FW cmd: FW not ready.\n");
9756 /* Prepare argument(s) and issue command */
9757 for (idx
= 0; idx
< argc
; idx
++) {
9758 bnx2x_cl45_write(bp
, phy
, MDIO_CTL_DEVAD
,
9759 MDIO_84833_CMD_HDLR_DATA1
+ idx
,
9762 bnx2x_cl45_write(bp
, phy
, MDIO_CTL_DEVAD
,
9763 MDIO_84833_CMD_HDLR_COMMAND
, fw_cmd
);
9764 for (idx
= 0; idx
< PHY84833_CMDHDLR_WAIT
; idx
++) {
9765 bnx2x_cl45_read(bp
, phy
, MDIO_CTL_DEVAD
,
9766 MDIO_84833_CMD_HDLR_STATUS
, &val
);
9767 if ((val
== PHY84833_STATUS_CMD_COMPLETE_PASS
) ||
9768 (val
== PHY84833_STATUS_CMD_COMPLETE_ERROR
))
9770 usleep_range(1000, 2000);
9772 if ((idx
>= PHY84833_CMDHDLR_WAIT
) ||
9773 (val
== PHY84833_STATUS_CMD_COMPLETE_ERROR
)) {
9774 DP(NETIF_MSG_LINK
, "FW cmd failed.\n");
9777 /* Gather returning data */
9778 for (idx
= 0; idx
< argc
; idx
++) {
9779 bnx2x_cl45_read(bp
, phy
, MDIO_CTL_DEVAD
,
9780 MDIO_84833_CMD_HDLR_DATA1
+ idx
,
9783 bnx2x_cl45_write(bp
, phy
, MDIO_CTL_DEVAD
,
9784 MDIO_84833_CMD_HDLR_STATUS
,
9785 PHY84833_STATUS_CMD_CLEAR_COMPLETE
);
9790 static int bnx2x_84833_pair_swap_cfg(struct bnx2x_phy
*phy
,
9791 struct link_params
*params
,
9792 struct link_vars
*vars
)
9795 u16 data
[PHY84833_CMDHDLR_MAX_ARGS
];
9797 struct bnx2x
*bp
= params
->bp
;
9799 /* Check for configuration. */
9800 pair_swap
= REG_RD(bp
, params
->shmem_base
+
9801 offsetof(struct shmem_region
,
9802 dev_info
.port_hw_config
[params
->port
].xgbt_phy_cfg
)) &
9803 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK
;
9808 /* Only the second argument is used for this command */
9809 data
[1] = (u16
)pair_swap
;
9811 status
= bnx2x_84833_cmd_hdlr(phy
, params
,
9812 PHY84833_CMD_SET_PAIR_SWAP
, data
, PHY84833_CMDHDLR_MAX_ARGS
);
9814 DP(NETIF_MSG_LINK
, "Pairswap OK, val=0x%x\n", data
[1]);
9819 static u8
bnx2x_84833_get_reset_gpios(struct bnx2x
*bp
,
9820 u32 shmem_base_path
[],
9826 if (CHIP_IS_E3(bp
)) {
9827 /* Assume that these will be GPIOs, not EPIOs. */
9828 for (idx
= 0; idx
< 2; idx
++) {
9829 /* Map config param to register bit. */
9830 reset_pin
[idx
] = REG_RD(bp
, shmem_base_path
[idx
] +
9831 offsetof(struct shmem_region
,
9832 dev_info
.port_hw_config
[0].e3_cmn_pin_cfg
));
9833 reset_pin
[idx
] = (reset_pin
[idx
] &
9834 PORT_HW_CFG_E3_PHY_RESET_MASK
) >>
9835 PORT_HW_CFG_E3_PHY_RESET_SHIFT
;
9836 reset_pin
[idx
] -= PIN_CFG_GPIO0_P0
;
9837 reset_pin
[idx
] = (1 << reset_pin
[idx
]);
9839 reset_gpios
= (u8
)(reset_pin
[0] | reset_pin
[1]);
9841 /* E2, look from diff place of shmem. */
9842 for (idx
= 0; idx
< 2; idx
++) {
9843 reset_pin
[idx
] = REG_RD(bp
, shmem_base_path
[idx
] +
9844 offsetof(struct shmem_region
,
9845 dev_info
.port_hw_config
[0].default_cfg
));
9846 reset_pin
[idx
] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK
;
9847 reset_pin
[idx
] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0
;
9848 reset_pin
[idx
] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT
;
9849 reset_pin
[idx
] = (1 << reset_pin
[idx
]);
9851 reset_gpios
= (u8
)(reset_pin
[0] | reset_pin
[1]);
9857 static int bnx2x_84833_hw_reset_phy(struct bnx2x_phy
*phy
,
9858 struct link_params
*params
)
9860 struct bnx2x
*bp
= params
->bp
;
9862 u32 other_shmem_base_addr
= REG_RD(bp
, params
->shmem2_base
+
9863 offsetof(struct shmem2_region
,
9864 other_shmem_base_addr
));
9866 u32 shmem_base_path
[2];
9868 /* Work around for 84833 LED failure inside RESET status */
9869 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
,
9870 MDIO_AN_REG_8481_LEGACY_MII_CTRL
,
9871 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G
);
9872 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
,
9873 MDIO_AN_REG_8481_1G_100T_EXT_CTRL
,
9874 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF
);
9876 shmem_base_path
[0] = params
->shmem_base
;
9877 shmem_base_path
[1] = other_shmem_base_addr
;
9879 reset_gpios
= bnx2x_84833_get_reset_gpios(bp
, shmem_base_path
,
9882 bnx2x_set_mult_gpio(bp
, reset_gpios
, MISC_REGISTERS_GPIO_OUTPUT_LOW
);
9884 DP(NETIF_MSG_LINK
, "84833 hw reset on pin values 0x%x\n",
9890 static int bnx2x_8483x_eee_timers(struct link_params
*params
,
9891 struct link_vars
*vars
)
9893 u32 eee_idle
= 0, eee_mode
;
9894 struct bnx2x
*bp
= params
->bp
;
9896 eee_idle
= bnx2x_eee_calc_timer(params
);
9899 REG_WR(bp
, MISC_REG_CPMU_LP_IDLE_THR_P0
+ (params
->port
<< 2),
9901 } else if ((params
->eee_mode
& EEE_MODE_ENABLE_LPI
) &&
9902 (params
->eee_mode
& EEE_MODE_OVERRIDE_NVRAM
) &&
9903 (params
->eee_mode
& EEE_MODE_OUTPUT_TIME
)) {
9904 DP(NETIF_MSG_LINK
, "Error: Tx LPI is enabled with timer 0\n");
9908 vars
->eee_status
&= ~(SHMEM_EEE_TIMER_MASK
| SHMEM_EEE_TIME_OUTPUT_BIT
);
9909 if (params
->eee_mode
& EEE_MODE_OUTPUT_TIME
) {
9910 /* eee_idle in 1u --> eee_status in 16u */
9912 vars
->eee_status
|= (eee_idle
& SHMEM_EEE_TIMER_MASK
) |
9913 SHMEM_EEE_TIME_OUTPUT_BIT
;
9915 if (bnx2x_eee_time_to_nvram(eee_idle
, &eee_mode
))
9917 vars
->eee_status
|= eee_mode
;
9923 static int bnx2x_8483x_disable_eee(struct bnx2x_phy
*phy
,
9924 struct link_params
*params
,
9925 struct link_vars
*vars
)
9928 struct bnx2x
*bp
= params
->bp
;
9931 DP(NETIF_MSG_LINK
, "Don't Advertise 10GBase-T EEE\n");
9933 /* Make Certain LPI is disabled */
9934 REG_WR(bp
, MISC_REG_CPMU_LP_FW_ENABLE_P0
+ (params
->port
<< 2), 0);
9935 REG_WR(bp
, MISC_REG_CPMU_LP_DR_ENABLE
, 0);
9937 /* Prevent Phy from working in EEE and advertising it */
9938 rc
= bnx2x_84833_cmd_hdlr(phy
, params
,
9939 PHY84833_CMD_SET_EEE_MODE
, &cmd_args
, 1);
9941 DP(NETIF_MSG_LINK
, "EEE disable failed.\n");
9945 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_EEE_ADV
, 0);
9946 vars
->eee_status
&= ~SHMEM_EEE_ADV_STATUS_MASK
;
9951 static int bnx2x_8483x_enable_eee(struct bnx2x_phy
*phy
,
9952 struct link_params
*params
,
9953 struct link_vars
*vars
)
9956 struct bnx2x
*bp
= params
->bp
;
9959 DP(NETIF_MSG_LINK
, "Advertise 10GBase-T EEE\n");
9961 rc
= bnx2x_84833_cmd_hdlr(phy
, params
,
9962 PHY84833_CMD_SET_EEE_MODE
, &cmd_args
, 1);
9964 DP(NETIF_MSG_LINK
, "EEE enable failed.\n");
9968 bnx2x_cl45_write(bp
, phy
, MDIO_AN_DEVAD
, MDIO_AN_REG_EEE_ADV
, 0x8);
9970 /* Mask events preventing LPI generation */
9971 REG_WR(bp
, MISC_REG_CPMU_LP_MASK_EXT_P0
+ (params
->port
<< 2), 0xfc20);
9973 vars
->eee_status
&= ~SHMEM_EEE_ADV_STATUS_MASK
;
9974 vars
->eee_status
|= (SHMEM_EEE_10G_ADV
<< SHMEM_EEE_ADV_STATUS_SHIFT
);
9979 #define PHY84833_CONSTANT_LATENCY 1193
9980 static int bnx2x_848x3_config_init(struct bnx2x_phy
*phy
,
9981 struct link_params
*params
,
9982 struct link_vars
*vars
)
9984 struct bnx2x
*bp
= params
->bp
;
9985 u8 port
, initialize
= 1;
9987 u32 actual_phy_selection
, cms_enable
;
9988 u16 cmd_args
[PHY84833_CMDHDLR_MAX_ARGS
];
9991 usleep_range(1000, 2000);
9993 if (!(CHIP_IS_E1x(bp
)))
9996 port
= params
->port
;
9998 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
) {
9999 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_3
,
10000 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
10004 bnx2x_cl45_write(bp
, phy
,
10006 MDIO_PMA_REG_CTRL
, 0x8000);
10009 bnx2x_wait_reset_complete(bp
, phy
, params
);
10011 /* Wait for GPHY to come out of reset */
10013 if (phy
->type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
) {
10014 /* BCM84823 requires that XGXS links up first @ 10G for normal
10018 temp
= vars
->line_speed
;
10019 vars
->line_speed
= SPEED_10000
;
10020 bnx2x_set_autoneg(¶ms
->phy
[INT_PHY
], params
, vars
, 0);
10021 bnx2x_program_serdes(¶ms
->phy
[INT_PHY
], params
, vars
);
10022 vars
->line_speed
= temp
;
10025 bnx2x_cl45_read(bp
, phy
, MDIO_CTL_DEVAD
,
10026 MDIO_CTL_REG_84823_MEDIA
, &val
);
10027 val
&= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK
|
10028 MDIO_CTL_REG_84823_MEDIA_LINE_MASK
|
10029 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN
|
10030 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK
|
10031 MDIO_CTL_REG_84823_MEDIA_FIBER_1G
);
10033 if (CHIP_IS_E3(bp
)) {
10034 val
&= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK
|
10035 MDIO_CTL_REG_84823_MEDIA_LINE_MASK
);
10037 val
|= (MDIO_CTL_REG_84823_CTRL_MAC_XFI
|
10038 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L
);
10041 actual_phy_selection
= bnx2x_phy_selection(params
);
10043 switch (actual_phy_selection
) {
10044 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
:
10045 /* Do nothing. Essentially this is like the priority copper */
10047 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
:
10048 val
|= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER
;
10050 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
:
10051 val
|= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER
;
10053 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
:
10054 /* Do nothing here. The first PHY won't be initialized at all */
10056 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
:
10057 val
|= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN
;
10061 if (params
->phy
[EXT_PHY2
].req_line_speed
== SPEED_1000
)
10062 val
|= MDIO_CTL_REG_84823_MEDIA_FIBER_1G
;
10064 bnx2x_cl45_write(bp
, phy
, MDIO_CTL_DEVAD
,
10065 MDIO_CTL_REG_84823_MEDIA
, val
);
10066 DP(NETIF_MSG_LINK
, "Multi_phy config = 0x%x, Media control = 0x%x\n",
10067 params
->multi_phy_config
, val
);
10069 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
) {
10070 bnx2x_84833_pair_swap_cfg(phy
, params
, vars
);
10072 /* Keep AutogrEEEn disabled. */
10075 cmd_args
[2] = PHY84833_CONSTANT_LATENCY
+ 1;
10076 cmd_args
[3] = PHY84833_CONSTANT_LATENCY
;
10077 rc
= bnx2x_84833_cmd_hdlr(phy
, params
,
10078 PHY84833_CMD_SET_EEE_MODE
, cmd_args
,
10079 PHY84833_CMDHDLR_MAX_ARGS
);
10081 DP(NETIF_MSG_LINK
, "Cfg AutogrEEEn failed.\n");
10084 rc
= bnx2x_848xx_cmn_config_init(phy
, params
, vars
);
10086 bnx2x_save_848xx_spirom_version(phy
, bp
, params
->port
);
10087 /* 84833 PHY has a better feature and doesn't need to support this. */
10088 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
) {
10089 cms_enable
= REG_RD(bp
, params
->shmem_base
+
10090 offsetof(struct shmem_region
,
10091 dev_info
.port_hw_config
[params
->port
].default_cfg
)) &
10092 PORT_HW_CFG_ENABLE_CMS_MASK
;
10094 bnx2x_cl45_read(bp
, phy
, MDIO_CTL_DEVAD
,
10095 MDIO_CTL_REG_84823_USER_CTRL_REG
, &val
);
10097 val
|= MDIO_CTL_REG_84823_USER_CTRL_CMS
;
10099 val
&= ~MDIO_CTL_REG_84823_USER_CTRL_CMS
;
10100 bnx2x_cl45_write(bp
, phy
, MDIO_CTL_DEVAD
,
10101 MDIO_CTL_REG_84823_USER_CTRL_REG
, val
);
10104 bnx2x_cl45_read(bp
, phy
, MDIO_CTL_DEVAD
,
10105 MDIO_84833_TOP_CFG_FW_REV
, &val
);
10107 /* Configure EEE support */
10108 if ((val
>= MDIO_84833_TOP_CFG_FW_EEE
) && bnx2x_eee_has_cap(params
)) {
10109 phy
->flags
|= FLAGS_EEE_10GBT
;
10110 vars
->eee_status
|= SHMEM_EEE_10G_ADV
<<
10111 SHMEM_EEE_SUPPORTED_SHIFT
;
10112 /* Propogate params' bits --> vars (for migration exposure) */
10113 if (params
->eee_mode
& EEE_MODE_ENABLE_LPI
)
10114 vars
->eee_status
|= SHMEM_EEE_LPI_REQUESTED_BIT
;
10116 vars
->eee_status
&= ~SHMEM_EEE_LPI_REQUESTED_BIT
;
10118 if (params
->eee_mode
& EEE_MODE_ADV_LPI
)
10119 vars
->eee_status
|= SHMEM_EEE_REQUESTED_BIT
;
10121 vars
->eee_status
&= ~SHMEM_EEE_REQUESTED_BIT
;
10123 rc
= bnx2x_8483x_eee_timers(params
, vars
);
10125 DP(NETIF_MSG_LINK
, "Failed to configure EEE timers\n");
10126 bnx2x_8483x_disable_eee(phy
, params
, vars
);
10130 if ((params
->req_duplex
[actual_phy_selection
] == DUPLEX_FULL
) &&
10131 (params
->eee_mode
& EEE_MODE_ADV_LPI
) &&
10132 (bnx2x_eee_calc_timer(params
) ||
10133 !(params
->eee_mode
& EEE_MODE_ENABLE_LPI
)))
10134 rc
= bnx2x_8483x_enable_eee(phy
, params
, vars
);
10136 rc
= bnx2x_8483x_disable_eee(phy
, params
, vars
);
10138 DP(NETIF_MSG_LINK
, "Failed to set EEE advertisment\n");
10142 phy
->flags
&= ~FLAGS_EEE_10GBT
;
10143 vars
->eee_status
&= ~SHMEM_EEE_SUPPORTED_MASK
;
10146 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
) {
10147 /* Bring PHY out of super isolate mode as the final step. */
10148 bnx2x_cl45_read(bp
, phy
,
10150 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, &val
);
10151 val
&= ~MDIO_84833_SUPER_ISOLATE
;
10152 bnx2x_cl45_write(bp
, phy
,
10154 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, val
);
10159 static u8
bnx2x_848xx_read_status(struct bnx2x_phy
*phy
,
10160 struct link_params
*params
,
10161 struct link_vars
*vars
)
10163 struct bnx2x
*bp
= params
->bp
;
10164 u16 val
, val1
, val2
;
10168 /* Check 10G-BaseT link status */
10169 /* Check PMD signal ok */
10170 bnx2x_cl45_read(bp
, phy
,
10171 MDIO_AN_DEVAD
, 0xFFFA, &val1
);
10172 bnx2x_cl45_read(bp
, phy
,
10173 MDIO_PMA_DEVAD
, MDIO_PMA_REG_8481_PMD_SIGNAL
,
10175 DP(NETIF_MSG_LINK
, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2
);
10177 /* Check link 10G */
10178 if (val2
& (1<<11)) {
10179 vars
->line_speed
= SPEED_10000
;
10180 vars
->duplex
= DUPLEX_FULL
;
10182 bnx2x_ext_phy_10G_an_resolve(bp
, phy
, vars
);
10183 } else { /* Check Legacy speed link */
10184 u16 legacy_status
, legacy_speed
;
10186 /* Enable expansion register 0x42 (Operation mode status) */
10187 bnx2x_cl45_write(bp
, phy
,
10189 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS
, 0xf42);
10191 /* Get legacy speed operation status */
10192 bnx2x_cl45_read(bp
, phy
,
10194 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW
,
10197 DP(NETIF_MSG_LINK
, "Legacy speed status = 0x%x\n",
10199 link_up
= ((legacy_status
& (1<<11)) == (1<<11));
10200 legacy_speed
= (legacy_status
& (3<<9));
10201 if (legacy_speed
== (0<<9))
10202 vars
->line_speed
= SPEED_10
;
10203 else if (legacy_speed
== (1<<9))
10204 vars
->line_speed
= SPEED_100
;
10205 else if (legacy_speed
== (2<<9))
10206 vars
->line_speed
= SPEED_1000
;
10207 else { /* Should not happen: Treat as link down */
10208 vars
->line_speed
= 0;
10213 if (legacy_status
& (1<<8))
10214 vars
->duplex
= DUPLEX_FULL
;
10216 vars
->duplex
= DUPLEX_HALF
;
10219 "Link is up in %dMbps, is_duplex_full= %d\n",
10221 (vars
->duplex
== DUPLEX_FULL
));
10222 /* Check legacy speed AN resolution */
10223 bnx2x_cl45_read(bp
, phy
,
10225 MDIO_AN_REG_8481_LEGACY_MII_STATUS
,
10228 vars
->link_status
|=
10229 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
10230 bnx2x_cl45_read(bp
, phy
,
10232 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION
,
10234 if ((val
& (1<<0)) == 0)
10235 vars
->link_status
|=
10236 LINK_STATUS_PARALLEL_DETECTION_USED
;
10240 DP(NETIF_MSG_LINK
, "BCM848x3: link speed is %d\n",
10242 bnx2x_ext_phy_resolve_fc(phy
, params
, vars
);
10244 /* Read LP advertised speeds */
10245 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
10246 MDIO_AN_REG_CL37_FC_LP
, &val
);
10248 vars
->link_status
|=
10249 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE
;
10251 vars
->link_status
|=
10252 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE
;
10254 vars
->link_status
|=
10255 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE
;
10257 vars
->link_status
|=
10258 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE
;
10260 vars
->link_status
|=
10261 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE
;
10263 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
10264 MDIO_AN_REG_1000T_STATUS
, &val
);
10267 vars
->link_status
|=
10268 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE
;
10270 vars
->link_status
|=
10271 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
10273 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
10274 MDIO_AN_REG_MASTER_STATUS
, &val
);
10277 vars
->link_status
|=
10278 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
10280 /* Determine if EEE was negotiated */
10281 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
) {
10284 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
10285 MDIO_AN_REG_EEE_ADV
, &val1
);
10286 bnx2x_cl45_read(bp
, phy
, MDIO_AN_DEVAD
,
10287 MDIO_AN_REG_LP_EEE_ADV
, &val2
);
10288 if ((val1
& val2
) & 0x8) {
10289 DP(NETIF_MSG_LINK
, "EEE negotiated\n");
10290 vars
->eee_status
|= SHMEM_EEE_ACTIVE_BIT
;
10294 eee_shmem
|= SHMEM_EEE_100M_ADV
;
10296 eee_shmem
|= SHMEM_EEE_1G_ADV
;
10298 eee_shmem
|= SHMEM_EEE_10G_ADV
;
10300 vars
->eee_status
&= ~SHMEM_EEE_LP_ADV_STATUS_MASK
;
10301 vars
->eee_status
|= (eee_shmem
<<
10302 SHMEM_EEE_LP_ADV_STATUS_SHIFT
);
10310 static int bnx2x_848xx_format_ver(u32 raw_ver
, u8
*str
, u16
*len
)
10314 spirom_ver
= ((raw_ver
& 0xF80) >> 7) << 16 | (raw_ver
& 0x7F);
10315 status
= bnx2x_format_ver(spirom_ver
, str
, len
);
10319 static void bnx2x_8481_hw_reset(struct bnx2x_phy
*phy
,
10320 struct link_params
*params
)
10322 bnx2x_set_gpio(params
->bp
, MISC_REGISTERS_GPIO_1
,
10323 MISC_REGISTERS_GPIO_OUTPUT_LOW
, 0);
10324 bnx2x_set_gpio(params
->bp
, MISC_REGISTERS_GPIO_1
,
10325 MISC_REGISTERS_GPIO_OUTPUT_LOW
, 1);
10328 static void bnx2x_8481_link_reset(struct bnx2x_phy
*phy
,
10329 struct link_params
*params
)
10331 bnx2x_cl45_write(params
->bp
, phy
,
10332 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, 0x0000);
10333 bnx2x_cl45_write(params
->bp
, phy
,
10334 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1);
10337 static void bnx2x_848x3_link_reset(struct bnx2x_phy
*phy
,
10338 struct link_params
*params
)
10340 struct bnx2x
*bp
= params
->bp
;
10344 if (!(CHIP_IS_E1x(bp
)))
10345 port
= BP_PATH(bp
);
10347 port
= params
->port
;
10349 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
) {
10350 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_3
,
10351 MISC_REGISTERS_GPIO_OUTPUT_LOW
,
10354 bnx2x_cl45_read(bp
, phy
,
10356 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, &val16
);
10357 val16
|= MDIO_84833_SUPER_ISOLATE
;
10358 bnx2x_cl45_write(bp
, phy
,
10360 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, val16
);
10364 static void bnx2x_848xx_set_link_led(struct bnx2x_phy
*phy
,
10365 struct link_params
*params
, u8 mode
)
10367 struct bnx2x
*bp
= params
->bp
;
10371 if (!(CHIP_IS_E1x(bp
)))
10372 port
= BP_PATH(bp
);
10374 port
= params
->port
;
10379 DP(NETIF_MSG_LINK
, "Port 0x%x: LED MODE OFF\n", port
);
10381 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
10382 SHARED_HW_CFG_LED_EXTPHY1
) {
10384 /* Set LED masks */
10385 bnx2x_cl45_write(bp
, phy
,
10387 MDIO_PMA_REG_8481_LED1_MASK
,
10390 bnx2x_cl45_write(bp
, phy
,
10392 MDIO_PMA_REG_8481_LED2_MASK
,
10395 bnx2x_cl45_write(bp
, phy
,
10397 MDIO_PMA_REG_8481_LED3_MASK
,
10400 bnx2x_cl45_write(bp
, phy
,
10402 MDIO_PMA_REG_8481_LED5_MASK
,
10406 bnx2x_cl45_write(bp
, phy
,
10408 MDIO_PMA_REG_8481_LED1_MASK
,
10412 case LED_MODE_FRONT_PANEL_OFF
:
10414 DP(NETIF_MSG_LINK
, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
10417 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
10418 SHARED_HW_CFG_LED_EXTPHY1
) {
10420 /* Set LED masks */
10421 bnx2x_cl45_write(bp
, phy
,
10423 MDIO_PMA_REG_8481_LED1_MASK
,
10426 bnx2x_cl45_write(bp
, phy
,
10428 MDIO_PMA_REG_8481_LED2_MASK
,
10431 bnx2x_cl45_write(bp
, phy
,
10433 MDIO_PMA_REG_8481_LED3_MASK
,
10436 bnx2x_cl45_write(bp
, phy
,
10438 MDIO_PMA_REG_8481_LED5_MASK
,
10442 bnx2x_cl45_write(bp
, phy
,
10444 MDIO_PMA_REG_8481_LED1_MASK
,
10450 DP(NETIF_MSG_LINK
, "Port 0x%x: LED MODE ON\n", port
);
10452 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
10453 SHARED_HW_CFG_LED_EXTPHY1
) {
10454 /* Set control reg */
10455 bnx2x_cl45_read(bp
, phy
,
10457 MDIO_PMA_REG_8481_LINK_SIGNAL
,
10462 bnx2x_cl45_write(bp
, phy
,
10464 MDIO_PMA_REG_8481_LINK_SIGNAL
,
10467 /* Set LED masks */
10468 bnx2x_cl45_write(bp
, phy
,
10470 MDIO_PMA_REG_8481_LED1_MASK
,
10473 bnx2x_cl45_write(bp
, phy
,
10475 MDIO_PMA_REG_8481_LED2_MASK
,
10478 bnx2x_cl45_write(bp
, phy
,
10480 MDIO_PMA_REG_8481_LED3_MASK
,
10483 bnx2x_cl45_write(bp
, phy
,
10485 MDIO_PMA_REG_8481_LED5_MASK
,
10488 bnx2x_cl45_write(bp
, phy
,
10490 MDIO_PMA_REG_8481_LED1_MASK
,
10495 case LED_MODE_OPER
:
10497 DP(NETIF_MSG_LINK
, "Port 0x%x: LED MODE OPER\n", port
);
10499 if ((params
->hw_led_mode
<< SHARED_HW_CFG_LED_MODE_SHIFT
) ==
10500 SHARED_HW_CFG_LED_EXTPHY1
) {
10502 /* Set control reg */
10503 bnx2x_cl45_read(bp
, phy
,
10505 MDIO_PMA_REG_8481_LINK_SIGNAL
,
10509 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK
)
10510 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT
)) {
10511 DP(NETIF_MSG_LINK
, "Setting LINK_SIGNAL\n");
10512 bnx2x_cl45_write(bp
, phy
,
10514 MDIO_PMA_REG_8481_LINK_SIGNAL
,
10518 /* Set LED masks */
10519 bnx2x_cl45_write(bp
, phy
,
10521 MDIO_PMA_REG_8481_LED1_MASK
,
10524 bnx2x_cl45_write(bp
, phy
,
10526 MDIO_PMA_REG_8481_LED2_MASK
,
10529 bnx2x_cl45_write(bp
, phy
,
10531 MDIO_PMA_REG_8481_LED3_MASK
,
10534 bnx2x_cl45_write(bp
, phy
,
10536 MDIO_PMA_REG_8481_LED5_MASK
,
10540 bnx2x_cl45_write(bp
, phy
,
10542 MDIO_PMA_REG_8481_LED1_MASK
,
10545 /* Tell LED3 to blink on source */
10546 bnx2x_cl45_read(bp
, phy
,
10548 MDIO_PMA_REG_8481_LINK_SIGNAL
,
10551 val
|= (1<<6); /* A83B[8:6]= 1 */
10552 bnx2x_cl45_write(bp
, phy
,
10554 MDIO_PMA_REG_8481_LINK_SIGNAL
,
10560 /* This is a workaround for E3+84833 until autoneg
10561 * restart is fixed in f/w
10563 if (CHIP_IS_E3(bp
)) {
10564 bnx2x_cl45_read(bp
, phy
, MDIO_WC_DEVAD
,
10565 MDIO_WC_REG_GP2_STATUS_GP_2_1
, &val
);
10569 /******************************************************************/
10570 /* 54618SE PHY SECTION */
10571 /******************************************************************/
10572 static int bnx2x_54618se_config_init(struct bnx2x_phy
*phy
,
10573 struct link_params
*params
,
10574 struct link_vars
*vars
)
10576 struct bnx2x
*bp
= params
->bp
;
10578 u16 autoneg_val
, an_1000_val
, an_10_100_val
, fc_val
, temp
;
10581 DP(NETIF_MSG_LINK
, "54618SE cfg init\n");
10582 usleep_range(1000, 2000);
10584 /* This works with E3 only, no need to check the chip
10585 * before determining the port.
10587 port
= params
->port
;
10589 cfg_pin
= (REG_RD(bp
, params
->shmem_base
+
10590 offsetof(struct shmem_region
,
10591 dev_info
.port_hw_config
[port
].e3_cmn_pin_cfg
)) &
10592 PORT_HW_CFG_E3_PHY_RESET_MASK
) >>
10593 PORT_HW_CFG_E3_PHY_RESET_SHIFT
;
10595 /* Drive pin high to bring the GPHY out of reset. */
10596 bnx2x_set_cfg_pin(bp
, cfg_pin
, 1);
10598 /* wait for GPHY to reset */
10602 bnx2x_cl22_write(bp
, phy
,
10603 MDIO_PMA_REG_CTRL
, 0x8000);
10604 bnx2x_wait_reset_complete(bp
, phy
, params
);
10606 /* Wait for GPHY to reset */
10609 /* Configure LED4: set to INTR (0x6). */
10610 /* Accessing shadow register 0xe. */
10611 bnx2x_cl22_write(bp
, phy
,
10612 MDIO_REG_GPHY_SHADOW
,
10613 MDIO_REG_GPHY_SHADOW_LED_SEL2
);
10614 bnx2x_cl22_read(bp
, phy
,
10615 MDIO_REG_GPHY_SHADOW
,
10617 temp
&= ~(0xf << 4);
10618 temp
|= (0x6 << 4);
10619 bnx2x_cl22_write(bp
, phy
,
10620 MDIO_REG_GPHY_SHADOW
,
10621 MDIO_REG_GPHY_SHADOW_WR_ENA
| temp
);
10622 /* Configure INTR based on link status change. */
10623 bnx2x_cl22_write(bp
, phy
,
10624 MDIO_REG_INTR_MASK
,
10625 ~MDIO_REG_INTR_MASK_LINK_STATUS
);
10627 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
10628 bnx2x_cl22_write(bp
, phy
,
10629 MDIO_REG_GPHY_SHADOW
,
10630 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED
);
10631 bnx2x_cl22_read(bp
, phy
,
10632 MDIO_REG_GPHY_SHADOW
,
10634 temp
|= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD
;
10635 bnx2x_cl22_write(bp
, phy
,
10636 MDIO_REG_GPHY_SHADOW
,
10637 MDIO_REG_GPHY_SHADOW_WR_ENA
| temp
);
10640 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
10641 bnx2x_calc_ieee_aneg_adv(phy
, params
, &vars
->ieee_fc
);
10643 if ((vars
->ieee_fc
& MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
) ==
10644 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
)
10645 fc_val
|= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC
;
10647 if ((vars
->ieee_fc
& MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
) ==
10648 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
)
10649 fc_val
|= MDIO_AN_REG_ADV_PAUSE_PAUSE
;
10651 /* Read all advertisement */
10652 bnx2x_cl22_read(bp
, phy
,
10656 bnx2x_cl22_read(bp
, phy
,
10660 bnx2x_cl22_read(bp
, phy
,
10664 /* Disable forced speed */
10665 autoneg_val
&= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10666 an_10_100_val
&= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
10669 if (((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
10670 (phy
->speed_cap_mask
&
10671 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
)) ||
10672 (phy
->req_line_speed
== SPEED_1000
)) {
10673 an_1000_val
|= (1<<8);
10674 autoneg_val
|= (1<<9 | 1<<12);
10675 if (phy
->req_duplex
== DUPLEX_FULL
)
10676 an_1000_val
|= (1<<9);
10677 DP(NETIF_MSG_LINK
, "Advertising 1G\n");
10679 an_1000_val
&= ~((1<<8) | (1<<9));
10681 bnx2x_cl22_write(bp
, phy
,
10684 bnx2x_cl22_read(bp
, phy
,
10688 /* Set 100 speed advertisement */
10689 if (((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
10690 (phy
->speed_cap_mask
&
10691 (PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
|
10692 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
)))) {
10693 an_10_100_val
|= (1<<7);
10694 /* Enable autoneg and restart autoneg for legacy speeds */
10695 autoneg_val
|= (1<<9 | 1<<12);
10697 if (phy
->req_duplex
== DUPLEX_FULL
)
10698 an_10_100_val
|= (1<<8);
10699 DP(NETIF_MSG_LINK
, "Advertising 100M\n");
10702 /* Set 10 speed advertisement */
10703 if (((phy
->req_line_speed
== SPEED_AUTO_NEG
) &&
10704 (phy
->speed_cap_mask
&
10705 (PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
|
10706 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
)))) {
10707 an_10_100_val
|= (1<<5);
10708 autoneg_val
|= (1<<9 | 1<<12);
10709 if (phy
->req_duplex
== DUPLEX_FULL
)
10710 an_10_100_val
|= (1<<6);
10711 DP(NETIF_MSG_LINK
, "Advertising 10M\n");
10714 /* Only 10/100 are allowed to work in FORCE mode */
10715 if (phy
->req_line_speed
== SPEED_100
) {
10716 autoneg_val
|= (1<<13);
10717 /* Enabled AUTO-MDIX when autoneg is disabled */
10718 bnx2x_cl22_write(bp
, phy
,
10720 (1<<15 | 1<<9 | 7<<0));
10721 DP(NETIF_MSG_LINK
, "Setting 100M force\n");
10723 if (phy
->req_line_speed
== SPEED_10
) {
10724 /* Enabled AUTO-MDIX when autoneg is disabled */
10725 bnx2x_cl22_write(bp
, phy
,
10727 (1<<15 | 1<<9 | 7<<0));
10728 DP(NETIF_MSG_LINK
, "Setting 10M force\n");
10731 /* Check if we should turn on Auto-GrEEEn */
10732 bnx2x_cl22_read(bp
, phy
, MDIO_REG_GPHY_PHYID_LSB
, &temp
);
10733 if (temp
== MDIO_REG_GPHY_ID_54618SE
) {
10734 if (params
->feature_config_flags
&
10735 FEATURE_CONFIG_AUTOGREEEN_ENABLED
) {
10737 DP(NETIF_MSG_LINK
, "Enabling Auto-GrEEEn\n");
10740 DP(NETIF_MSG_LINK
, "Disabling Auto-GrEEEn\n");
10742 bnx2x_cl22_write(bp
, phy
,
10743 MDIO_REG_GPHY_CL45_ADDR_REG
, MDIO_AN_DEVAD
);
10744 bnx2x_cl22_write(bp
, phy
,
10745 MDIO_REG_GPHY_CL45_DATA_REG
,
10746 MDIO_REG_GPHY_EEE_ADV
);
10747 bnx2x_cl22_write(bp
, phy
,
10748 MDIO_REG_GPHY_CL45_ADDR_REG
,
10749 (0x1 << 14) | MDIO_AN_DEVAD
);
10750 bnx2x_cl22_write(bp
, phy
,
10751 MDIO_REG_GPHY_CL45_DATA_REG
,
10755 bnx2x_cl22_write(bp
, phy
,
10757 an_10_100_val
| fc_val
);
10759 if (phy
->req_duplex
== DUPLEX_FULL
)
10760 autoneg_val
|= (1<<8);
10762 bnx2x_cl22_write(bp
, phy
,
10763 MDIO_PMA_REG_CTRL
, autoneg_val
);
10769 static void bnx2x_5461x_set_link_led(struct bnx2x_phy
*phy
,
10770 struct link_params
*params
, u8 mode
)
10772 struct bnx2x
*bp
= params
->bp
;
10775 bnx2x_cl22_write(bp
, phy
,
10776 MDIO_REG_GPHY_SHADOW
,
10777 MDIO_REG_GPHY_SHADOW_LED_SEL1
);
10778 bnx2x_cl22_read(bp
, phy
,
10779 MDIO_REG_GPHY_SHADOW
,
10783 DP(NETIF_MSG_LINK
, "54618x set link led (mode=%x)\n", mode
);
10785 case LED_MODE_FRONT_PANEL_OFF
:
10789 case LED_MODE_OPER
:
10798 bnx2x_cl22_write(bp
, phy
,
10799 MDIO_REG_GPHY_SHADOW
,
10800 MDIO_REG_GPHY_SHADOW_WR_ENA
| temp
);
10805 static void bnx2x_54618se_link_reset(struct bnx2x_phy
*phy
,
10806 struct link_params
*params
)
10808 struct bnx2x
*bp
= params
->bp
;
10812 /* In case of no EPIO routed to reset the GPHY, put it
10813 * in low power mode.
10815 bnx2x_cl22_write(bp
, phy
, MDIO_PMA_REG_CTRL
, 0x800);
10816 /* This works with E3 only, no need to check the chip
10817 * before determining the port.
10819 port
= params
->port
;
10820 cfg_pin
= (REG_RD(bp
, params
->shmem_base
+
10821 offsetof(struct shmem_region
,
10822 dev_info
.port_hw_config
[port
].e3_cmn_pin_cfg
)) &
10823 PORT_HW_CFG_E3_PHY_RESET_MASK
) >>
10824 PORT_HW_CFG_E3_PHY_RESET_SHIFT
;
10826 /* Drive pin low to put GPHY in reset. */
10827 bnx2x_set_cfg_pin(bp
, cfg_pin
, 0);
10830 static u8
bnx2x_54618se_read_status(struct bnx2x_phy
*phy
,
10831 struct link_params
*params
,
10832 struct link_vars
*vars
)
10834 struct bnx2x
*bp
= params
->bp
;
10837 u16 legacy_status
, legacy_speed
;
10839 /* Get speed operation status */
10840 bnx2x_cl22_read(bp
, phy
,
10841 MDIO_REG_GPHY_AUX_STATUS
,
10843 DP(NETIF_MSG_LINK
, "54618SE read_status: 0x%x\n", legacy_status
);
10845 /* Read status to clear the PHY interrupt. */
10846 bnx2x_cl22_read(bp
, phy
,
10847 MDIO_REG_INTR_STATUS
,
10850 link_up
= ((legacy_status
& (1<<2)) == (1<<2));
10853 legacy_speed
= (legacy_status
& (7<<8));
10854 if (legacy_speed
== (7<<8)) {
10855 vars
->line_speed
= SPEED_1000
;
10856 vars
->duplex
= DUPLEX_FULL
;
10857 } else if (legacy_speed
== (6<<8)) {
10858 vars
->line_speed
= SPEED_1000
;
10859 vars
->duplex
= DUPLEX_HALF
;
10860 } else if (legacy_speed
== (5<<8)) {
10861 vars
->line_speed
= SPEED_100
;
10862 vars
->duplex
= DUPLEX_FULL
;
10864 /* Omitting 100Base-T4 for now */
10865 else if (legacy_speed
== (3<<8)) {
10866 vars
->line_speed
= SPEED_100
;
10867 vars
->duplex
= DUPLEX_HALF
;
10868 } else if (legacy_speed
== (2<<8)) {
10869 vars
->line_speed
= SPEED_10
;
10870 vars
->duplex
= DUPLEX_FULL
;
10871 } else if (legacy_speed
== (1<<8)) {
10872 vars
->line_speed
= SPEED_10
;
10873 vars
->duplex
= DUPLEX_HALF
;
10874 } else /* Should not happen */
10875 vars
->line_speed
= 0;
10878 "Link is up in %dMbps, is_duplex_full= %d\n",
10880 (vars
->duplex
== DUPLEX_FULL
));
10882 /* Check legacy speed AN resolution */
10883 bnx2x_cl22_read(bp
, phy
,
10887 vars
->link_status
|=
10888 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
;
10889 bnx2x_cl22_read(bp
, phy
,
10892 if ((val
& (1<<0)) == 0)
10893 vars
->link_status
|=
10894 LINK_STATUS_PARALLEL_DETECTION_USED
;
10896 DP(NETIF_MSG_LINK
, "BCM54618SE: link speed is %d\n",
10899 /* Report whether EEE is resolved. */
10900 bnx2x_cl22_read(bp
, phy
, MDIO_REG_GPHY_PHYID_LSB
, &val
);
10901 if (val
== MDIO_REG_GPHY_ID_54618SE
) {
10902 if (vars
->link_status
&
10903 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
)
10906 bnx2x_cl22_write(bp
, phy
,
10907 MDIO_REG_GPHY_CL45_ADDR_REG
,
10909 bnx2x_cl22_write(bp
, phy
,
10910 MDIO_REG_GPHY_CL45_DATA_REG
,
10911 MDIO_REG_GPHY_EEE_RESOLVED
);
10912 bnx2x_cl22_write(bp
, phy
,
10913 MDIO_REG_GPHY_CL45_ADDR_REG
,
10914 (0x1 << 14) | MDIO_AN_DEVAD
);
10915 bnx2x_cl22_read(bp
, phy
,
10916 MDIO_REG_GPHY_CL45_DATA_REG
,
10919 DP(NETIF_MSG_LINK
, "EEE resolution: 0x%x\n", val
);
10922 bnx2x_ext_phy_resolve_fc(phy
, params
, vars
);
10924 if (vars
->link_status
& LINK_STATUS_AUTO_NEGOTIATE_COMPLETE
) {
10925 /* Report LP advertised speeds */
10926 bnx2x_cl22_read(bp
, phy
, 0x5, &val
);
10929 vars
->link_status
|=
10930 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE
;
10932 vars
->link_status
|=
10933 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE
;
10935 vars
->link_status
|=
10936 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE
;
10938 vars
->link_status
|=
10939 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE
;
10941 vars
->link_status
|=
10942 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE
;
10944 bnx2x_cl22_read(bp
, phy
, 0xa, &val
);
10946 vars
->link_status
|=
10947 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE
;
10949 vars
->link_status
|=
10950 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE
;
10956 static void bnx2x_54618se_config_loopback(struct bnx2x_phy
*phy
,
10957 struct link_params
*params
)
10959 struct bnx2x
*bp
= params
->bp
;
10961 u32 umac_base
= params
->port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
10963 DP(NETIF_MSG_LINK
, "2PMA/PMD ext_phy_loopback: 54618se\n");
10965 /* Enable master/slave manual mmode and set to master */
10966 /* mii write 9 [bits set 11 12] */
10967 bnx2x_cl22_write(bp
, phy
, 0x09, 3<<11);
10969 /* forced 1G and disable autoneg */
10970 /* set val [mii read 0] */
10971 /* set val [expr $val & [bits clear 6 12 13]] */
10972 /* set val [expr $val | [bits set 6 8]] */
10973 /* mii write 0 $val */
10974 bnx2x_cl22_read(bp
, phy
, 0x00, &val
);
10975 val
&= ~((1<<6) | (1<<12) | (1<<13));
10976 val
|= (1<<6) | (1<<8);
10977 bnx2x_cl22_write(bp
, phy
, 0x00, val
);
10979 /* Set external loopback and Tx using 6dB coding */
10980 /* mii write 0x18 7 */
10981 /* set val [mii read 0x18] */
10982 /* mii write 0x18 [expr $val | [bits set 10 15]] */
10983 bnx2x_cl22_write(bp
, phy
, 0x18, 7);
10984 bnx2x_cl22_read(bp
, phy
, 0x18, &val
);
10985 bnx2x_cl22_write(bp
, phy
, 0x18, val
| (1<<10) | (1<<15));
10987 /* This register opens the gate for the UMAC despite its name */
10988 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
*4, 1);
10990 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
10991 * length used by the MAC receive logic to check frames.
10993 REG_WR(bp
, umac_base
+ UMAC_REG_MAXFR
, 0x2710);
10996 /******************************************************************/
10997 /* SFX7101 PHY SECTION */
10998 /******************************************************************/
10999 static void bnx2x_7101_config_loopback(struct bnx2x_phy
*phy
,
11000 struct link_params
*params
)
11002 struct bnx2x
*bp
= params
->bp
;
11003 /* SFX7101_XGXS_TEST1 */
11004 bnx2x_cl45_write(bp
, phy
,
11005 MDIO_XS_DEVAD
, MDIO_XS_SFX7101_XGXS_TEST1
, 0x100);
11008 static int bnx2x_7101_config_init(struct bnx2x_phy
*phy
,
11009 struct link_params
*params
,
11010 struct link_vars
*vars
)
11012 u16 fw_ver1
, fw_ver2
, val
;
11013 struct bnx2x
*bp
= params
->bp
;
11014 DP(NETIF_MSG_LINK
, "Setting the SFX7101 LASI indication\n");
11016 /* Restore normal power mode*/
11017 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
11018 MISC_REGISTERS_GPIO_OUTPUT_HIGH
, params
->port
);
11020 bnx2x_ext_phy_hw_reset(bp
, params
->port
);
11021 bnx2x_wait_reset_complete(bp
, phy
, params
);
11023 bnx2x_cl45_write(bp
, phy
,
11024 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_CTRL
, 0x1);
11025 DP(NETIF_MSG_LINK
, "Setting the SFX7101 LED to blink on traffic\n");
11026 bnx2x_cl45_write(bp
, phy
,
11027 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7107_LED_CNTL
, (1<<3));
11029 bnx2x_ext_phy_set_pause(params
, phy
, vars
);
11030 /* Restart autoneg */
11031 bnx2x_cl45_read(bp
, phy
,
11032 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, &val
);
11034 bnx2x_cl45_write(bp
, phy
,
11035 MDIO_AN_DEVAD
, MDIO_AN_REG_CTRL
, val
);
11037 /* Save spirom version */
11038 bnx2x_cl45_read(bp
, phy
,
11039 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7101_VER1
, &fw_ver1
);
11041 bnx2x_cl45_read(bp
, phy
,
11042 MDIO_PMA_DEVAD
, MDIO_PMA_REG_7101_VER2
, &fw_ver2
);
11043 bnx2x_save_spirom_version(bp
, params
->port
,
11044 (u32
)(fw_ver1
<<16 | fw_ver2
), phy
->ver_addr
);
11048 static u8
bnx2x_7101_read_status(struct bnx2x_phy
*phy
,
11049 struct link_params
*params
,
11050 struct link_vars
*vars
)
11052 struct bnx2x
*bp
= params
->bp
;
11055 bnx2x_cl45_read(bp
, phy
,
11056 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val2
);
11057 bnx2x_cl45_read(bp
, phy
,
11058 MDIO_PMA_DEVAD
, MDIO_PMA_LASI_STAT
, &val1
);
11059 DP(NETIF_MSG_LINK
, "10G-base-T LASI status 0x%x->0x%x\n",
11061 bnx2x_cl45_read(bp
, phy
,
11062 MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val2
);
11063 bnx2x_cl45_read(bp
, phy
,
11064 MDIO_PMA_DEVAD
, MDIO_PMA_REG_STATUS
, &val1
);
11065 DP(NETIF_MSG_LINK
, "10G-base-T PMA status 0x%x->0x%x\n",
11067 link_up
= ((val1
& 4) == 4);
11068 /* If link is up print the AN outcome of the SFX7101 PHY */
11070 bnx2x_cl45_read(bp
, phy
,
11071 MDIO_AN_DEVAD
, MDIO_AN_REG_MASTER_STATUS
,
11073 vars
->line_speed
= SPEED_10000
;
11074 vars
->duplex
= DUPLEX_FULL
;
11075 DP(NETIF_MSG_LINK
, "SFX7101 AN status 0x%x->Master=%x\n",
11076 val2
, (val2
& (1<<14)));
11077 bnx2x_ext_phy_10G_an_resolve(bp
, phy
, vars
);
11078 bnx2x_ext_phy_resolve_fc(phy
, params
, vars
);
11080 /* Read LP advertised speeds */
11081 if (val2
& (1<<11))
11082 vars
->link_status
|=
11083 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE
;
11088 static int bnx2x_7101_format_ver(u32 spirom_ver
, u8
*str
, u16
*len
)
11092 str
[0] = (spirom_ver
& 0xFF);
11093 str
[1] = (spirom_ver
& 0xFF00) >> 8;
11094 str
[2] = (spirom_ver
& 0xFF0000) >> 16;
11095 str
[3] = (spirom_ver
& 0xFF000000) >> 24;
11101 void bnx2x_sfx7101_sp_sw_reset(struct bnx2x
*bp
, struct bnx2x_phy
*phy
)
11105 bnx2x_cl45_read(bp
, phy
,
11107 MDIO_PMA_REG_7101_RESET
, &val
);
11109 for (cnt
= 0; cnt
< 10; cnt
++) {
11111 /* Writes a self-clearing reset */
11112 bnx2x_cl45_write(bp
, phy
,
11114 MDIO_PMA_REG_7101_RESET
,
11116 /* Wait for clear */
11117 bnx2x_cl45_read(bp
, phy
,
11119 MDIO_PMA_REG_7101_RESET
, &val
);
11121 if ((val
& (1<<15)) == 0)
11126 static void bnx2x_7101_hw_reset(struct bnx2x_phy
*phy
,
11127 struct link_params
*params
) {
11128 /* Low power mode is controlled by GPIO 2 */
11129 bnx2x_set_gpio(params
->bp
, MISC_REGISTERS_GPIO_2
,
11130 MISC_REGISTERS_GPIO_OUTPUT_LOW
, params
->port
);
11131 /* The PHY reset is controlled by GPIO 1 */
11132 bnx2x_set_gpio(params
->bp
, MISC_REGISTERS_GPIO_1
,
11133 MISC_REGISTERS_GPIO_OUTPUT_LOW
, params
->port
);
11136 static void bnx2x_7101_set_link_led(struct bnx2x_phy
*phy
,
11137 struct link_params
*params
, u8 mode
)
11140 struct bnx2x
*bp
= params
->bp
;
11142 case LED_MODE_FRONT_PANEL_OFF
:
11149 case LED_MODE_OPER
:
11153 bnx2x_cl45_write(bp
, phy
,
11155 MDIO_PMA_REG_7107_LINK_LED_CNTL
,
11159 /******************************************************************/
11160 /* STATIC PHY DECLARATION */
11161 /******************************************************************/
11163 static struct bnx2x_phy phy_null
= {
11164 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
,
11167 .flags
= FLAGS_INIT_XGXS_FIRST
,
11168 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11169 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11172 .media_type
= ETH_PHY_NOT_PRESENT
,
11174 .req_flow_ctrl
= 0,
11175 .req_line_speed
= 0,
11176 .speed_cap_mask
= 0,
11179 .config_init
= (config_init_t
)NULL
,
11180 .read_status
= (read_status_t
)NULL
,
11181 .link_reset
= (link_reset_t
)NULL
,
11182 .config_loopback
= (config_loopback_t
)NULL
,
11183 .format_fw_ver
= (format_fw_ver_t
)NULL
,
11184 .hw_reset
= (hw_reset_t
)NULL
,
11185 .set_link_led
= (set_link_led_t
)NULL
,
11186 .phy_specific_func
= (phy_specific_func_t
)NULL
11189 static struct bnx2x_phy phy_serdes
= {
11190 .type
= PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT
,
11194 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11195 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11197 .supported
= (SUPPORTED_10baseT_Half
|
11198 SUPPORTED_10baseT_Full
|
11199 SUPPORTED_100baseT_Half
|
11200 SUPPORTED_100baseT_Full
|
11201 SUPPORTED_1000baseT_Full
|
11202 SUPPORTED_2500baseX_Full
|
11204 SUPPORTED_Autoneg
|
11206 SUPPORTED_Asym_Pause
),
11207 .media_type
= ETH_PHY_BASE_T
,
11209 .req_flow_ctrl
= 0,
11210 .req_line_speed
= 0,
11211 .speed_cap_mask
= 0,
11214 .config_init
= (config_init_t
)bnx2x_xgxs_config_init
,
11215 .read_status
= (read_status_t
)bnx2x_link_settings_status
,
11216 .link_reset
= (link_reset_t
)bnx2x_int_link_reset
,
11217 .config_loopback
= (config_loopback_t
)NULL
,
11218 .format_fw_ver
= (format_fw_ver_t
)NULL
,
11219 .hw_reset
= (hw_reset_t
)NULL
,
11220 .set_link_led
= (set_link_led_t
)NULL
,
11221 .phy_specific_func
= (phy_specific_func_t
)NULL
11224 static struct bnx2x_phy phy_xgxs
= {
11225 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
,
11229 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11230 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11232 .supported
= (SUPPORTED_10baseT_Half
|
11233 SUPPORTED_10baseT_Full
|
11234 SUPPORTED_100baseT_Half
|
11235 SUPPORTED_100baseT_Full
|
11236 SUPPORTED_1000baseT_Full
|
11237 SUPPORTED_2500baseX_Full
|
11238 SUPPORTED_10000baseT_Full
|
11240 SUPPORTED_Autoneg
|
11242 SUPPORTED_Asym_Pause
),
11243 .media_type
= ETH_PHY_CX4
,
11245 .req_flow_ctrl
= 0,
11246 .req_line_speed
= 0,
11247 .speed_cap_mask
= 0,
11250 .config_init
= (config_init_t
)bnx2x_xgxs_config_init
,
11251 .read_status
= (read_status_t
)bnx2x_link_settings_status
,
11252 .link_reset
= (link_reset_t
)bnx2x_int_link_reset
,
11253 .config_loopback
= (config_loopback_t
)bnx2x_set_xgxs_loopback
,
11254 .format_fw_ver
= (format_fw_ver_t
)NULL
,
11255 .hw_reset
= (hw_reset_t
)NULL
,
11256 .set_link_led
= (set_link_led_t
)NULL
,
11257 .phy_specific_func
= (phy_specific_func_t
)NULL
11259 static struct bnx2x_phy phy_warpcore
= {
11260 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
,
11263 .flags
= (FLAGS_HW_LOCK_REQUIRED
|
11264 FLAGS_TX_ERROR_CHECK
),
11265 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11266 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11268 .supported
= (SUPPORTED_10baseT_Half
|
11269 SUPPORTED_10baseT_Full
|
11270 SUPPORTED_100baseT_Half
|
11271 SUPPORTED_100baseT_Full
|
11272 SUPPORTED_1000baseT_Full
|
11273 SUPPORTED_10000baseT_Full
|
11274 SUPPORTED_20000baseKR2_Full
|
11275 SUPPORTED_20000baseMLD2_Full
|
11277 SUPPORTED_Autoneg
|
11279 SUPPORTED_Asym_Pause
),
11280 .media_type
= ETH_PHY_UNSPECIFIED
,
11282 .req_flow_ctrl
= 0,
11283 .req_line_speed
= 0,
11284 .speed_cap_mask
= 0,
11285 /* req_duplex = */0,
11287 .config_init
= (config_init_t
)bnx2x_warpcore_config_init
,
11288 .read_status
= (read_status_t
)bnx2x_warpcore_read_status
,
11289 .link_reset
= (link_reset_t
)bnx2x_warpcore_link_reset
,
11290 .config_loopback
= (config_loopback_t
)bnx2x_set_warpcore_loopback
,
11291 .format_fw_ver
= (format_fw_ver_t
)NULL
,
11292 .hw_reset
= (hw_reset_t
)bnx2x_warpcore_hw_reset
,
11293 .set_link_led
= (set_link_led_t
)NULL
,
11294 .phy_specific_func
= (phy_specific_func_t
)NULL
11298 static struct bnx2x_phy phy_7101
= {
11299 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
,
11302 .flags
= FLAGS_FAN_FAILURE_DET_REQ
,
11303 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11304 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11306 .supported
= (SUPPORTED_10000baseT_Full
|
11308 SUPPORTED_Autoneg
|
11310 SUPPORTED_Asym_Pause
),
11311 .media_type
= ETH_PHY_BASE_T
,
11313 .req_flow_ctrl
= 0,
11314 .req_line_speed
= 0,
11315 .speed_cap_mask
= 0,
11318 .config_init
= (config_init_t
)bnx2x_7101_config_init
,
11319 .read_status
= (read_status_t
)bnx2x_7101_read_status
,
11320 .link_reset
= (link_reset_t
)bnx2x_common_ext_link_reset
,
11321 .config_loopback
= (config_loopback_t
)bnx2x_7101_config_loopback
,
11322 .format_fw_ver
= (format_fw_ver_t
)bnx2x_7101_format_ver
,
11323 .hw_reset
= (hw_reset_t
)bnx2x_7101_hw_reset
,
11324 .set_link_led
= (set_link_led_t
)bnx2x_7101_set_link_led
,
11325 .phy_specific_func
= (phy_specific_func_t
)NULL
11327 static struct bnx2x_phy phy_8073
= {
11328 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
,
11331 .flags
= FLAGS_HW_LOCK_REQUIRED
,
11332 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11333 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11335 .supported
= (SUPPORTED_10000baseT_Full
|
11336 SUPPORTED_2500baseX_Full
|
11337 SUPPORTED_1000baseT_Full
|
11339 SUPPORTED_Autoneg
|
11341 SUPPORTED_Asym_Pause
),
11342 .media_type
= ETH_PHY_KR
,
11344 .req_flow_ctrl
= 0,
11345 .req_line_speed
= 0,
11346 .speed_cap_mask
= 0,
11349 .config_init
= (config_init_t
)bnx2x_8073_config_init
,
11350 .read_status
= (read_status_t
)bnx2x_8073_read_status
,
11351 .link_reset
= (link_reset_t
)bnx2x_8073_link_reset
,
11352 .config_loopback
= (config_loopback_t
)NULL
,
11353 .format_fw_ver
= (format_fw_ver_t
)bnx2x_format_ver
,
11354 .hw_reset
= (hw_reset_t
)NULL
,
11355 .set_link_led
= (set_link_led_t
)NULL
,
11356 .phy_specific_func
= (phy_specific_func_t
)NULL
11358 static struct bnx2x_phy phy_8705
= {
11359 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
,
11362 .flags
= FLAGS_INIT_XGXS_FIRST
,
11363 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11364 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11366 .supported
= (SUPPORTED_10000baseT_Full
|
11369 SUPPORTED_Asym_Pause
),
11370 .media_type
= ETH_PHY_XFP_FIBER
,
11372 .req_flow_ctrl
= 0,
11373 .req_line_speed
= 0,
11374 .speed_cap_mask
= 0,
11377 .config_init
= (config_init_t
)bnx2x_8705_config_init
,
11378 .read_status
= (read_status_t
)bnx2x_8705_read_status
,
11379 .link_reset
= (link_reset_t
)bnx2x_common_ext_link_reset
,
11380 .config_loopback
= (config_loopback_t
)NULL
,
11381 .format_fw_ver
= (format_fw_ver_t
)bnx2x_null_format_ver
,
11382 .hw_reset
= (hw_reset_t
)NULL
,
11383 .set_link_led
= (set_link_led_t
)NULL
,
11384 .phy_specific_func
= (phy_specific_func_t
)NULL
11386 static struct bnx2x_phy phy_8706
= {
11387 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
,
11390 .flags
= FLAGS_INIT_XGXS_FIRST
,
11391 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11392 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11394 .supported
= (SUPPORTED_10000baseT_Full
|
11395 SUPPORTED_1000baseT_Full
|
11398 SUPPORTED_Asym_Pause
),
11399 .media_type
= ETH_PHY_SFPP_10G_FIBER
,
11401 .req_flow_ctrl
= 0,
11402 .req_line_speed
= 0,
11403 .speed_cap_mask
= 0,
11406 .config_init
= (config_init_t
)bnx2x_8706_config_init
,
11407 .read_status
= (read_status_t
)bnx2x_8706_read_status
,
11408 .link_reset
= (link_reset_t
)bnx2x_common_ext_link_reset
,
11409 .config_loopback
= (config_loopback_t
)NULL
,
11410 .format_fw_ver
= (format_fw_ver_t
)bnx2x_format_ver
,
11411 .hw_reset
= (hw_reset_t
)NULL
,
11412 .set_link_led
= (set_link_led_t
)NULL
,
11413 .phy_specific_func
= (phy_specific_func_t
)NULL
11416 static struct bnx2x_phy phy_8726
= {
11417 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
,
11420 .flags
= (FLAGS_HW_LOCK_REQUIRED
|
11421 FLAGS_INIT_XGXS_FIRST
|
11422 FLAGS_TX_ERROR_CHECK
),
11423 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11424 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11426 .supported
= (SUPPORTED_10000baseT_Full
|
11427 SUPPORTED_1000baseT_Full
|
11428 SUPPORTED_Autoneg
|
11431 SUPPORTED_Asym_Pause
),
11432 .media_type
= ETH_PHY_NOT_PRESENT
,
11434 .req_flow_ctrl
= 0,
11435 .req_line_speed
= 0,
11436 .speed_cap_mask
= 0,
11439 .config_init
= (config_init_t
)bnx2x_8726_config_init
,
11440 .read_status
= (read_status_t
)bnx2x_8726_read_status
,
11441 .link_reset
= (link_reset_t
)bnx2x_8726_link_reset
,
11442 .config_loopback
= (config_loopback_t
)bnx2x_8726_config_loopback
,
11443 .format_fw_ver
= (format_fw_ver_t
)bnx2x_format_ver
,
11444 .hw_reset
= (hw_reset_t
)NULL
,
11445 .set_link_led
= (set_link_led_t
)NULL
,
11446 .phy_specific_func
= (phy_specific_func_t
)NULL
11449 static struct bnx2x_phy phy_8727
= {
11450 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
,
11453 .flags
= (FLAGS_FAN_FAILURE_DET_REQ
|
11454 FLAGS_TX_ERROR_CHECK
),
11455 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11456 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11458 .supported
= (SUPPORTED_10000baseT_Full
|
11459 SUPPORTED_1000baseT_Full
|
11462 SUPPORTED_Asym_Pause
),
11463 .media_type
= ETH_PHY_NOT_PRESENT
,
11465 .req_flow_ctrl
= 0,
11466 .req_line_speed
= 0,
11467 .speed_cap_mask
= 0,
11470 .config_init
= (config_init_t
)bnx2x_8727_config_init
,
11471 .read_status
= (read_status_t
)bnx2x_8727_read_status
,
11472 .link_reset
= (link_reset_t
)bnx2x_8727_link_reset
,
11473 .config_loopback
= (config_loopback_t
)NULL
,
11474 .format_fw_ver
= (format_fw_ver_t
)bnx2x_format_ver
,
11475 .hw_reset
= (hw_reset_t
)bnx2x_8727_hw_reset
,
11476 .set_link_led
= (set_link_led_t
)bnx2x_8727_set_link_led
,
11477 .phy_specific_func
= (phy_specific_func_t
)bnx2x_8727_specific_func
11479 static struct bnx2x_phy phy_8481
= {
11480 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
,
11483 .flags
= FLAGS_FAN_FAILURE_DET_REQ
|
11484 FLAGS_REARM_LATCH_SIGNAL
,
11485 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11486 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11488 .supported
= (SUPPORTED_10baseT_Half
|
11489 SUPPORTED_10baseT_Full
|
11490 SUPPORTED_100baseT_Half
|
11491 SUPPORTED_100baseT_Full
|
11492 SUPPORTED_1000baseT_Full
|
11493 SUPPORTED_10000baseT_Full
|
11495 SUPPORTED_Autoneg
|
11497 SUPPORTED_Asym_Pause
),
11498 .media_type
= ETH_PHY_BASE_T
,
11500 .req_flow_ctrl
= 0,
11501 .req_line_speed
= 0,
11502 .speed_cap_mask
= 0,
11505 .config_init
= (config_init_t
)bnx2x_8481_config_init
,
11506 .read_status
= (read_status_t
)bnx2x_848xx_read_status
,
11507 .link_reset
= (link_reset_t
)bnx2x_8481_link_reset
,
11508 .config_loopback
= (config_loopback_t
)NULL
,
11509 .format_fw_ver
= (format_fw_ver_t
)bnx2x_848xx_format_ver
,
11510 .hw_reset
= (hw_reset_t
)bnx2x_8481_hw_reset
,
11511 .set_link_led
= (set_link_led_t
)bnx2x_848xx_set_link_led
,
11512 .phy_specific_func
= (phy_specific_func_t
)NULL
11515 static struct bnx2x_phy phy_84823
= {
11516 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
,
11519 .flags
= (FLAGS_FAN_FAILURE_DET_REQ
|
11520 FLAGS_REARM_LATCH_SIGNAL
|
11521 FLAGS_TX_ERROR_CHECK
),
11522 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11523 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11525 .supported
= (SUPPORTED_10baseT_Half
|
11526 SUPPORTED_10baseT_Full
|
11527 SUPPORTED_100baseT_Half
|
11528 SUPPORTED_100baseT_Full
|
11529 SUPPORTED_1000baseT_Full
|
11530 SUPPORTED_10000baseT_Full
|
11532 SUPPORTED_Autoneg
|
11534 SUPPORTED_Asym_Pause
),
11535 .media_type
= ETH_PHY_BASE_T
,
11537 .req_flow_ctrl
= 0,
11538 .req_line_speed
= 0,
11539 .speed_cap_mask
= 0,
11542 .config_init
= (config_init_t
)bnx2x_848x3_config_init
,
11543 .read_status
= (read_status_t
)bnx2x_848xx_read_status
,
11544 .link_reset
= (link_reset_t
)bnx2x_848x3_link_reset
,
11545 .config_loopback
= (config_loopback_t
)NULL
,
11546 .format_fw_ver
= (format_fw_ver_t
)bnx2x_848xx_format_ver
,
11547 .hw_reset
= (hw_reset_t
)NULL
,
11548 .set_link_led
= (set_link_led_t
)bnx2x_848xx_set_link_led
,
11549 .phy_specific_func
= (phy_specific_func_t
)NULL
11552 static struct bnx2x_phy phy_84833
= {
11553 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
,
11556 .flags
= (FLAGS_FAN_FAILURE_DET_REQ
|
11557 FLAGS_REARM_LATCH_SIGNAL
|
11558 FLAGS_TX_ERROR_CHECK
|
11560 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11561 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11563 .supported
= (SUPPORTED_100baseT_Half
|
11564 SUPPORTED_100baseT_Full
|
11565 SUPPORTED_1000baseT_Full
|
11566 SUPPORTED_10000baseT_Full
|
11568 SUPPORTED_Autoneg
|
11570 SUPPORTED_Asym_Pause
),
11571 .media_type
= ETH_PHY_BASE_T
,
11573 .req_flow_ctrl
= 0,
11574 .req_line_speed
= 0,
11575 .speed_cap_mask
= 0,
11578 .config_init
= (config_init_t
)bnx2x_848x3_config_init
,
11579 .read_status
= (read_status_t
)bnx2x_848xx_read_status
,
11580 .link_reset
= (link_reset_t
)bnx2x_848x3_link_reset
,
11581 .config_loopback
= (config_loopback_t
)NULL
,
11582 .format_fw_ver
= (format_fw_ver_t
)bnx2x_848xx_format_ver
,
11583 .hw_reset
= (hw_reset_t
)bnx2x_84833_hw_reset_phy
,
11584 .set_link_led
= (set_link_led_t
)bnx2x_848xx_set_link_led
,
11585 .phy_specific_func
= (phy_specific_func_t
)NULL
11588 static struct bnx2x_phy phy_54618se
= {
11589 .type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE
,
11592 .flags
= FLAGS_INIT_XGXS_FIRST
,
11593 .rx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11594 .tx_preemphasis
= {0xffff, 0xffff, 0xffff, 0xffff},
11596 .supported
= (SUPPORTED_10baseT_Half
|
11597 SUPPORTED_10baseT_Full
|
11598 SUPPORTED_100baseT_Half
|
11599 SUPPORTED_100baseT_Full
|
11600 SUPPORTED_1000baseT_Full
|
11602 SUPPORTED_Autoneg
|
11604 SUPPORTED_Asym_Pause
),
11605 .media_type
= ETH_PHY_BASE_T
,
11607 .req_flow_ctrl
= 0,
11608 .req_line_speed
= 0,
11609 .speed_cap_mask
= 0,
11610 /* req_duplex = */0,
11612 .config_init
= (config_init_t
)bnx2x_54618se_config_init
,
11613 .read_status
= (read_status_t
)bnx2x_54618se_read_status
,
11614 .link_reset
= (link_reset_t
)bnx2x_54618se_link_reset
,
11615 .config_loopback
= (config_loopback_t
)bnx2x_54618se_config_loopback
,
11616 .format_fw_ver
= (format_fw_ver_t
)NULL
,
11617 .hw_reset
= (hw_reset_t
)NULL
,
11618 .set_link_led
= (set_link_led_t
)bnx2x_5461x_set_link_led
,
11619 .phy_specific_func
= (phy_specific_func_t
)NULL
11621 /*****************************************************************/
11623 /* Populate the phy according. Main function: bnx2x_populate_phy */
11625 /*****************************************************************/
11627 static void bnx2x_populate_preemphasis(struct bnx2x
*bp
, u32 shmem_base
,
11628 struct bnx2x_phy
*phy
, u8 port
,
11631 /* Get the 4 lanes xgxs config rx and tx */
11632 u32 rx
= 0, tx
= 0, i
;
11633 for (i
= 0; i
< 2; i
++) {
11634 /* INT_PHY and EXT_PHY1 share the same value location in
11635 * the shmem. When num_phys is greater than 1, than this value
11636 * applies only to EXT_PHY1
11638 if (phy_index
== INT_PHY
|| phy_index
== EXT_PHY1
) {
11639 rx
= REG_RD(bp
, shmem_base
+
11640 offsetof(struct shmem_region
,
11641 dev_info
.port_hw_config
[port
].xgxs_config_rx
[i
<<1]));
11643 tx
= REG_RD(bp
, shmem_base
+
11644 offsetof(struct shmem_region
,
11645 dev_info
.port_hw_config
[port
].xgxs_config_tx
[i
<<1]));
11647 rx
= REG_RD(bp
, shmem_base
+
11648 offsetof(struct shmem_region
,
11649 dev_info
.port_hw_config
[port
].xgxs_config2_rx
[i
<<1]));
11651 tx
= REG_RD(bp
, shmem_base
+
11652 offsetof(struct shmem_region
,
11653 dev_info
.port_hw_config
[port
].xgxs_config2_rx
[i
<<1]));
11656 phy
->rx_preemphasis
[i
<< 1] = ((rx
>>16) & 0xffff);
11657 phy
->rx_preemphasis
[(i
<< 1) + 1] = (rx
& 0xffff);
11659 phy
->tx_preemphasis
[i
<< 1] = ((tx
>>16) & 0xffff);
11660 phy
->tx_preemphasis
[(i
<< 1) + 1] = (tx
& 0xffff);
11664 static u32
bnx2x_get_ext_phy_config(struct bnx2x
*bp
, u32 shmem_base
,
11665 u8 phy_index
, u8 port
)
11667 u32 ext_phy_config
= 0;
11668 switch (phy_index
) {
11670 ext_phy_config
= REG_RD(bp
, shmem_base
+
11671 offsetof(struct shmem_region
,
11672 dev_info
.port_hw_config
[port
].external_phy_config
));
11675 ext_phy_config
= REG_RD(bp
, shmem_base
+
11676 offsetof(struct shmem_region
,
11677 dev_info
.port_hw_config
[port
].external_phy_config2
));
11680 DP(NETIF_MSG_LINK
, "Invalid phy_index %d\n", phy_index
);
11684 return ext_phy_config
;
11686 static int bnx2x_populate_int_phy(struct bnx2x
*bp
, u32 shmem_base
, u8 port
,
11687 struct bnx2x_phy
*phy
)
11691 u32 switch_cfg
= (REG_RD(bp
, shmem_base
+
11692 offsetof(struct shmem_region
,
11693 dev_info
.port_feature_config
[port
].link_config
)) &
11694 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
11695 chip_id
= (REG_RD(bp
, MISC_REG_CHIP_NUM
) << 16) |
11696 ((REG_RD(bp
, MISC_REG_CHIP_REV
) & 0xf) << 12);
11698 DP(NETIF_MSG_LINK
, ":chip_id = 0x%x\n", chip_id
);
11699 if (USES_WARPCORE(bp
)) {
11701 phy_addr
= REG_RD(bp
,
11702 MISC_REG_WC0_CTRL_PHY_ADDR
);
11703 *phy
= phy_warpcore
;
11704 if (REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
) == 0x3)
11705 phy
->flags
|= FLAGS_4_PORT_MODE
;
11707 phy
->flags
&= ~FLAGS_4_PORT_MODE
;
11708 /* Check Dual mode */
11709 serdes_net_if
= (REG_RD(bp
, shmem_base
+
11710 offsetof(struct shmem_region
, dev_info
.
11711 port_hw_config
[port
].default_cfg
)) &
11712 PORT_HW_CFG_NET_SERDES_IF_MASK
);
11713 /* Set the appropriate supported and flags indications per
11714 * interface type of the chip
11716 switch (serdes_net_if
) {
11717 case PORT_HW_CFG_NET_SERDES_IF_SGMII
:
11718 phy
->supported
&= (SUPPORTED_10baseT_Half
|
11719 SUPPORTED_10baseT_Full
|
11720 SUPPORTED_100baseT_Half
|
11721 SUPPORTED_100baseT_Full
|
11722 SUPPORTED_1000baseT_Full
|
11724 SUPPORTED_Autoneg
|
11726 SUPPORTED_Asym_Pause
);
11727 phy
->media_type
= ETH_PHY_BASE_T
;
11729 case PORT_HW_CFG_NET_SERDES_IF_XFI
:
11730 phy
->media_type
= ETH_PHY_XFP_FIBER
;
11732 case PORT_HW_CFG_NET_SERDES_IF_SFI
:
11733 phy
->supported
&= (SUPPORTED_1000baseT_Full
|
11734 SUPPORTED_10000baseT_Full
|
11737 SUPPORTED_Asym_Pause
);
11738 phy
->media_type
= ETH_PHY_SFPP_10G_FIBER
;
11740 case PORT_HW_CFG_NET_SERDES_IF_KR
:
11741 phy
->media_type
= ETH_PHY_KR
;
11742 phy
->supported
&= (SUPPORTED_1000baseT_Full
|
11743 SUPPORTED_10000baseT_Full
|
11745 SUPPORTED_Autoneg
|
11747 SUPPORTED_Asym_Pause
);
11749 case PORT_HW_CFG_NET_SERDES_IF_DXGXS
:
11750 phy
->media_type
= ETH_PHY_KR
;
11751 phy
->flags
|= FLAGS_WC_DUAL_MODE
;
11752 phy
->supported
&= (SUPPORTED_20000baseMLD2_Full
|
11755 SUPPORTED_Asym_Pause
);
11757 case PORT_HW_CFG_NET_SERDES_IF_KR2
:
11758 phy
->media_type
= ETH_PHY_KR
;
11759 phy
->flags
|= FLAGS_WC_DUAL_MODE
;
11760 phy
->supported
&= (SUPPORTED_20000baseKR2_Full
|
11763 SUPPORTED_Asym_Pause
);
11766 DP(NETIF_MSG_LINK
, "Unknown WC interface type 0x%x\n",
11771 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
11772 * was not set as expected. For B0, ECO will be enabled so there
11773 * won't be an issue there
11775 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
11776 phy
->flags
|= FLAGS_MDC_MDIO_WA
;
11778 phy
->flags
|= FLAGS_MDC_MDIO_WA_B0
;
11780 switch (switch_cfg
) {
11781 case SWITCH_CFG_1G
:
11782 phy_addr
= REG_RD(bp
,
11783 NIG_REG_SERDES0_CTRL_PHY_ADDR
+
11787 case SWITCH_CFG_10G
:
11788 phy_addr
= REG_RD(bp
,
11789 NIG_REG_XGXS0_CTRL_PHY_ADDR
+
11794 DP(NETIF_MSG_LINK
, "Invalid switch_cfg\n");
11798 phy
->addr
= (u8
)phy_addr
;
11799 phy
->mdio_ctrl
= bnx2x_get_emac_base(bp
,
11800 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
,
11802 if (CHIP_IS_E2(bp
))
11803 phy
->def_md_devad
= E2_DEFAULT_PHY_DEV_ADDR
;
11805 phy
->def_md_devad
= DEFAULT_PHY_DEV_ADDR
;
11807 DP(NETIF_MSG_LINK
, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
11808 port
, phy
->addr
, phy
->mdio_ctrl
);
11810 bnx2x_populate_preemphasis(bp
, shmem_base
, phy
, port
, INT_PHY
);
11814 static int bnx2x_populate_ext_phy(struct bnx2x
*bp
,
11819 struct bnx2x_phy
*phy
)
11821 u32 ext_phy_config
, phy_type
, config2
;
11822 u32 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
;
11823 ext_phy_config
= bnx2x_get_ext_phy_config(bp
, shmem_base
,
11825 phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
11826 /* Select the phy type */
11827 switch (phy_type
) {
11828 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
11829 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED
;
11832 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705
:
11835 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706
:
11838 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
11839 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
;
11842 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC
:
11843 /* BCM8727_NOC => BCM8727 no over current */
11844 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
;
11846 phy
->flags
|= FLAGS_NOC
;
11848 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722
:
11849 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
11850 mdc_mdio_access
= SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1
;
11853 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481
:
11856 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823
:
11859 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
:
11862 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616
:
11863 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE
:
11864 *phy
= phy_54618se
;
11866 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101
:
11869 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
11874 /* In case external PHY wasn't found */
11875 if ((phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
) &&
11876 (phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
11881 phy
->addr
= XGXS_EXT_PHY_ADDR(ext_phy_config
);
11882 bnx2x_populate_preemphasis(bp
, shmem_base
, phy
, port
, phy_index
);
11884 /* The shmem address of the phy version is located on different
11885 * structures. In case this structure is too old, do not set
11888 config2
= REG_RD(bp
, shmem_base
+ offsetof(struct shmem_region
,
11889 dev_info
.shared_hw_config
.config2
));
11890 if (phy_index
== EXT_PHY1
) {
11891 phy
->ver_addr
= shmem_base
+ offsetof(struct shmem_region
,
11892 port_mb
[port
].ext_phy_fw_version
);
11894 /* Check specific mdc mdio settings */
11895 if (config2
& SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK
)
11896 mdc_mdio_access
= config2
&
11897 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK
;
11899 u32 size
= REG_RD(bp
, shmem2_base
);
11902 offsetof(struct shmem2_region
, ext_phy_fw_version2
)) {
11903 phy
->ver_addr
= shmem2_base
+
11904 offsetof(struct shmem2_region
,
11905 ext_phy_fw_version2
[port
]);
11907 /* Check specific mdc mdio settings */
11908 if (config2
& SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK
)
11909 mdc_mdio_access
= (config2
&
11910 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK
) >>
11911 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT
-
11912 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT
);
11914 phy
->mdio_ctrl
= bnx2x_get_emac_base(bp
, mdc_mdio_access
, port
);
11916 if ((phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
) &&
11918 /* Remove 100Mb link supported for BCM84833 when phy fw
11919 * version lower than or equal to 1.39
11921 u32 raw_ver
= REG_RD(bp
, phy
->ver_addr
);
11922 if (((raw_ver
& 0x7F) <= 39) &&
11923 (((raw_ver
& 0xF80) >> 7) <= 1))
11924 phy
->supported
&= ~(SUPPORTED_100baseT_Half
|
11925 SUPPORTED_100baseT_Full
);
11928 /* In case mdc/mdio_access of the external phy is different than the
11929 * mdc/mdio access of the XGXS, a HW lock must be taken in each access
11930 * to prevent one port interfere with another port's CL45 operations.
11932 if (mdc_mdio_access
!= SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH
)
11933 phy
->flags
|= FLAGS_HW_LOCK_REQUIRED
;
11934 DP(NETIF_MSG_LINK
, "phy_type 0x%x port %d found in index %d\n",
11935 phy_type
, port
, phy_index
);
11936 DP(NETIF_MSG_LINK
, " addr=0x%x, mdio_ctl=0x%x\n",
11937 phy
->addr
, phy
->mdio_ctrl
);
11941 static int bnx2x_populate_phy(struct bnx2x
*bp
, u8 phy_index
, u32 shmem_base
,
11942 u32 shmem2_base
, u8 port
, struct bnx2x_phy
*phy
)
11945 phy
->type
= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
;
11946 if (phy_index
== INT_PHY
)
11947 return bnx2x_populate_int_phy(bp
, shmem_base
, port
, phy
);
11948 status
= bnx2x_populate_ext_phy(bp
, phy_index
, shmem_base
, shmem2_base
,
11953 static void bnx2x_phy_def_cfg(struct link_params
*params
,
11954 struct bnx2x_phy
*phy
,
11957 struct bnx2x
*bp
= params
->bp
;
11959 /* Populate the default phy configuration for MF mode */
11960 if (phy_index
== EXT_PHY2
) {
11961 link_config
= REG_RD(bp
, params
->shmem_base
+
11962 offsetof(struct shmem_region
, dev_info
.
11963 port_feature_config
[params
->port
].link_config2
));
11964 phy
->speed_cap_mask
= REG_RD(bp
, params
->shmem_base
+
11965 offsetof(struct shmem_region
,
11967 port_hw_config
[params
->port
].speed_capability_mask2
));
11969 link_config
= REG_RD(bp
, params
->shmem_base
+
11970 offsetof(struct shmem_region
, dev_info
.
11971 port_feature_config
[params
->port
].link_config
));
11972 phy
->speed_cap_mask
= REG_RD(bp
, params
->shmem_base
+
11973 offsetof(struct shmem_region
,
11975 port_hw_config
[params
->port
].speed_capability_mask
));
11978 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
11979 phy_index
, link_config
, phy
->speed_cap_mask
);
11981 phy
->req_duplex
= DUPLEX_FULL
;
11982 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
11983 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
11984 phy
->req_duplex
= DUPLEX_HALF
;
11985 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
11986 phy
->req_line_speed
= SPEED_10
;
11988 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
11989 phy
->req_duplex
= DUPLEX_HALF
;
11990 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
11991 phy
->req_line_speed
= SPEED_100
;
11993 case PORT_FEATURE_LINK_SPEED_1G
:
11994 phy
->req_line_speed
= SPEED_1000
;
11996 case PORT_FEATURE_LINK_SPEED_2_5G
:
11997 phy
->req_line_speed
= SPEED_2500
;
11999 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
12000 phy
->req_line_speed
= SPEED_10000
;
12003 phy
->req_line_speed
= SPEED_AUTO_NEG
;
12007 switch (link_config
& PORT_FEATURE_FLOW_CONTROL_MASK
) {
12008 case PORT_FEATURE_FLOW_CONTROL_AUTO
:
12009 phy
->req_flow_ctrl
= BNX2X_FLOW_CTRL_AUTO
;
12011 case PORT_FEATURE_FLOW_CONTROL_TX
:
12012 phy
->req_flow_ctrl
= BNX2X_FLOW_CTRL_TX
;
12014 case PORT_FEATURE_FLOW_CONTROL_RX
:
12015 phy
->req_flow_ctrl
= BNX2X_FLOW_CTRL_RX
;
12017 case PORT_FEATURE_FLOW_CONTROL_BOTH
:
12018 phy
->req_flow_ctrl
= BNX2X_FLOW_CTRL_BOTH
;
12021 phy
->req_flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
12026 u32
bnx2x_phy_selection(struct link_params
*params
)
12028 u32 phy_config_swapped
, prio_cfg
;
12029 u32 return_cfg
= PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT
;
12031 phy_config_swapped
= params
->multi_phy_config
&
12032 PORT_HW_CFG_PHY_SWAPPED_ENABLED
;
12034 prio_cfg
= params
->multi_phy_config
&
12035 PORT_HW_CFG_PHY_SELECTION_MASK
;
12037 if (phy_config_swapped
) {
12038 switch (prio_cfg
) {
12039 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
:
12040 return_cfg
= PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
;
12042 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY
:
12043 return_cfg
= PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY
;
12045 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
:
12046 return_cfg
= PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
;
12048 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY
:
12049 return_cfg
= PORT_HW_CFG_PHY_SELECTION_SECOND_PHY
;
12053 return_cfg
= prio_cfg
;
12059 int bnx2x_phy_probe(struct link_params
*params
)
12061 u8 phy_index
, actual_phy_idx
;
12062 u32 phy_config_swapped
, sync_offset
, media_types
;
12063 struct bnx2x
*bp
= params
->bp
;
12064 struct bnx2x_phy
*phy
;
12065 params
->num_phys
= 0;
12066 DP(NETIF_MSG_LINK
, "Begin phy probe\n");
12067 phy_config_swapped
= params
->multi_phy_config
&
12068 PORT_HW_CFG_PHY_SWAPPED_ENABLED
;
12070 for (phy_index
= INT_PHY
; phy_index
< MAX_PHYS
;
12072 actual_phy_idx
= phy_index
;
12073 if (phy_config_swapped
) {
12074 if (phy_index
== EXT_PHY1
)
12075 actual_phy_idx
= EXT_PHY2
;
12076 else if (phy_index
== EXT_PHY2
)
12077 actual_phy_idx
= EXT_PHY1
;
12079 DP(NETIF_MSG_LINK
, "phy_config_swapped %x, phy_index %x,"
12080 " actual_phy_idx %x\n", phy_config_swapped
,
12081 phy_index
, actual_phy_idx
);
12082 phy
= ¶ms
->phy
[actual_phy_idx
];
12083 if (bnx2x_populate_phy(bp
, phy_index
, params
->shmem_base
,
12084 params
->shmem2_base
, params
->port
,
12086 params
->num_phys
= 0;
12087 DP(NETIF_MSG_LINK
, "phy probe failed in phy index %d\n",
12089 for (phy_index
= INT_PHY
;
12090 phy_index
< MAX_PHYS
;
12095 if (phy
->type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
)
12098 if (params
->feature_config_flags
&
12099 FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET
)
12100 phy
->flags
&= ~FLAGS_TX_ERROR_CHECK
;
12102 sync_offset
= params
->shmem_base
+
12103 offsetof(struct shmem_region
,
12104 dev_info
.port_hw_config
[params
->port
].media_type
);
12105 media_types
= REG_RD(bp
, sync_offset
);
12107 /* Update media type for non-PMF sync only for the first time
12108 * In case the media type changes afterwards, it will be updated
12109 * using the update_status function
12111 if ((media_types
& (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
<<
12112 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
*
12113 actual_phy_idx
))) == 0) {
12114 media_types
|= ((phy
->media_type
&
12115 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK
) <<
12116 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT
*
12119 REG_WR(bp
, sync_offset
, media_types
);
12121 bnx2x_phy_def_cfg(params
, phy
, phy_index
);
12122 params
->num_phys
++;
12125 DP(NETIF_MSG_LINK
, "End phy probe. #phys found %x\n", params
->num_phys
);
12129 void bnx2x_init_bmac_loopback(struct link_params
*params
,
12130 struct link_vars
*vars
)
12132 struct bnx2x
*bp
= params
->bp
;
12134 vars
->line_speed
= SPEED_10000
;
12135 vars
->duplex
= DUPLEX_FULL
;
12136 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
12137 vars
->mac_type
= MAC_TYPE_BMAC
;
12139 vars
->phy_flags
= PHY_XGXS_FLAG
;
12141 bnx2x_xgxs_deassert(params
);
12143 /* set bmac loopback */
12144 bnx2x_bmac_enable(params
, vars
, 1);
12146 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
*4, 0);
12149 void bnx2x_init_emac_loopback(struct link_params
*params
,
12150 struct link_vars
*vars
)
12152 struct bnx2x
*bp
= params
->bp
;
12154 vars
->line_speed
= SPEED_1000
;
12155 vars
->duplex
= DUPLEX_FULL
;
12156 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
12157 vars
->mac_type
= MAC_TYPE_EMAC
;
12159 vars
->phy_flags
= PHY_XGXS_FLAG
;
12161 bnx2x_xgxs_deassert(params
);
12162 /* set bmac loopback */
12163 bnx2x_emac_enable(params
, vars
, 1);
12164 bnx2x_emac_program(params
, vars
);
12165 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
*4, 0);
12168 void bnx2x_init_xmac_loopback(struct link_params
*params
,
12169 struct link_vars
*vars
)
12171 struct bnx2x
*bp
= params
->bp
;
12173 if (!params
->req_line_speed
[0])
12174 vars
->line_speed
= SPEED_10000
;
12176 vars
->line_speed
= params
->req_line_speed
[0];
12177 vars
->duplex
= DUPLEX_FULL
;
12178 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
12179 vars
->mac_type
= MAC_TYPE_XMAC
;
12180 vars
->phy_flags
= PHY_XGXS_FLAG
;
12181 /* Set WC to loopback mode since link is required to provide clock
12182 * to the XMAC in 20G mode
12184 bnx2x_set_aer_mmd(params
, ¶ms
->phy
[0]);
12185 bnx2x_warpcore_reset_lane(bp
, ¶ms
->phy
[0], 0);
12186 params
->phy
[INT_PHY
].config_loopback(
12187 ¶ms
->phy
[INT_PHY
],
12190 bnx2x_xmac_enable(params
, vars
, 1);
12191 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
*4, 0);
12194 void bnx2x_init_umac_loopback(struct link_params
*params
,
12195 struct link_vars
*vars
)
12197 struct bnx2x
*bp
= params
->bp
;
12199 vars
->line_speed
= SPEED_1000
;
12200 vars
->duplex
= DUPLEX_FULL
;
12201 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
12202 vars
->mac_type
= MAC_TYPE_UMAC
;
12203 vars
->phy_flags
= PHY_XGXS_FLAG
;
12204 bnx2x_umac_enable(params
, vars
, 1);
12206 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
*4, 0);
12209 void bnx2x_init_xgxs_loopback(struct link_params
*params
,
12210 struct link_vars
*vars
)
12212 struct bnx2x
*bp
= params
->bp
;
12214 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
12215 vars
->duplex
= DUPLEX_FULL
;
12216 if (params
->req_line_speed
[0] == SPEED_1000
)
12217 vars
->line_speed
= SPEED_1000
;
12219 vars
->line_speed
= SPEED_10000
;
12221 if (!USES_WARPCORE(bp
))
12222 bnx2x_xgxs_deassert(params
);
12223 bnx2x_link_initialize(params
, vars
);
12225 if (params
->req_line_speed
[0] == SPEED_1000
) {
12226 if (USES_WARPCORE(bp
))
12227 bnx2x_umac_enable(params
, vars
, 0);
12229 bnx2x_emac_program(params
, vars
);
12230 bnx2x_emac_enable(params
, vars
, 0);
12233 if (USES_WARPCORE(bp
))
12234 bnx2x_xmac_enable(params
, vars
, 0);
12236 bnx2x_bmac_enable(params
, vars
, 0);
12239 if (params
->loopback_mode
== LOOPBACK_XGXS
) {
12240 /* set 10G XGXS loopback */
12241 params
->phy
[INT_PHY
].config_loopback(
12242 ¶ms
->phy
[INT_PHY
],
12246 /* set external phy loopback */
12248 for (phy_index
= EXT_PHY1
;
12249 phy_index
< params
->num_phys
; phy_index
++) {
12250 if (params
->phy
[phy_index
].config_loopback
)
12251 params
->phy
[phy_index
].config_loopback(
12252 ¶ms
->phy
[phy_index
],
12256 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
*4, 0);
12258 bnx2x_set_led(params
, vars
, LED_MODE_OPER
, vars
->line_speed
);
12261 int bnx2x_phy_init(struct link_params
*params
, struct link_vars
*vars
)
12263 struct bnx2x
*bp
= params
->bp
;
12264 DP(NETIF_MSG_LINK
, "Phy Initialization started\n");
12265 DP(NETIF_MSG_LINK
, "(1) req_speed %d, req_flowctrl %d\n",
12266 params
->req_line_speed
[0], params
->req_flow_ctrl
[0]);
12267 DP(NETIF_MSG_LINK
, "(2) req_speed %d, req_flowctrl %d\n",
12268 params
->req_line_speed
[1], params
->req_flow_ctrl
[1]);
12269 vars
->link_status
= 0;
12270 vars
->phy_link_up
= 0;
12272 vars
->line_speed
= 0;
12273 vars
->duplex
= DUPLEX_FULL
;
12274 vars
->flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
12275 vars
->mac_type
= MAC_TYPE_NONE
;
12276 vars
->phy_flags
= 0;
12278 /* Disable attentions */
12279 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ params
->port
*4,
12280 (NIG_MASK_XGXS0_LINK_STATUS
|
12281 NIG_MASK_XGXS0_LINK10G
|
12282 NIG_MASK_SERDES0_LINK_STATUS
|
12285 bnx2x_emac_init(params
, vars
);
12287 if (params
->feature_config_flags
& FEATURE_CONFIG_PFC_ENABLED
)
12288 vars
->link_status
|= LINK_STATUS_PFC_ENABLED
;
12290 if (params
->num_phys
== 0) {
12291 DP(NETIF_MSG_LINK
, "No phy found for initialization !!\n");
12294 set_phy_vars(params
, vars
);
12296 DP(NETIF_MSG_LINK
, "Num of phys on board: %d\n", params
->num_phys
);
12297 switch (params
->loopback_mode
) {
12298 case LOOPBACK_BMAC
:
12299 bnx2x_init_bmac_loopback(params
, vars
);
12301 case LOOPBACK_EMAC
:
12302 bnx2x_init_emac_loopback(params
, vars
);
12304 case LOOPBACK_XMAC
:
12305 bnx2x_init_xmac_loopback(params
, vars
);
12307 case LOOPBACK_UMAC
:
12308 bnx2x_init_umac_loopback(params
, vars
);
12310 case LOOPBACK_XGXS
:
12311 case LOOPBACK_EXT_PHY
:
12312 bnx2x_init_xgxs_loopback(params
, vars
);
12315 if (!CHIP_IS_E3(bp
)) {
12316 if (params
->switch_cfg
== SWITCH_CFG_10G
)
12317 bnx2x_xgxs_deassert(params
);
12319 bnx2x_serdes_deassert(bp
, params
->port
);
12321 bnx2x_link_initialize(params
, vars
);
12323 bnx2x_link_int_enable(params
);
12326 bnx2x_update_mng(params
, vars
->link_status
);
12328 bnx2x_update_mng_eee(params
, vars
->eee_status
);
12332 int bnx2x_link_reset(struct link_params
*params
, struct link_vars
*vars
,
12335 struct bnx2x
*bp
= params
->bp
;
12336 u8 phy_index
, port
= params
->port
, clear_latch_ind
= 0;
12337 DP(NETIF_MSG_LINK
, "Resetting the link of port %d\n", port
);
12338 /* Disable attentions */
12339 vars
->link_status
= 0;
12340 bnx2x_update_mng(params
, vars
->link_status
);
12341 vars
->eee_status
&= ~(SHMEM_EEE_LP_ADV_STATUS_MASK
|
12342 SHMEM_EEE_ACTIVE_BIT
);
12343 bnx2x_update_mng_eee(params
, vars
->eee_status
);
12344 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4,
12345 (NIG_MASK_XGXS0_LINK_STATUS
|
12346 NIG_MASK_XGXS0_LINK10G
|
12347 NIG_MASK_SERDES0_LINK_STATUS
|
12350 /* Activate nig drain */
12351 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ port
*4, 1);
12353 /* Disable nig egress interface */
12354 if (!CHIP_IS_E3(bp
)) {
12355 REG_WR(bp
, NIG_REG_BMAC0_OUT_EN
+ port
*4, 0);
12356 REG_WR(bp
, NIG_REG_EGRESS_EMAC0_OUT_EN
+ port
*4, 0);
12359 /* Stop BigMac rx */
12360 if (!CHIP_IS_E3(bp
))
12361 bnx2x_bmac_rx_disable(bp
, port
);
12363 bnx2x_xmac_disable(params
);
12364 bnx2x_umac_disable(params
);
12367 if (!CHIP_IS_E3(bp
))
12368 REG_WR(bp
, NIG_REG_NIG_EMAC0_EN
+ port
*4, 0);
12370 usleep_range(10000, 20000);
12371 /* The PHY reset is controlled by GPIO 1
12372 * Hold it as vars low
12374 /* Clear link led */
12375 bnx2x_set_mdio_clk(bp
, params
->chip_id
, port
);
12376 bnx2x_set_led(params
, vars
, LED_MODE_OFF
, 0);
12378 if (reset_ext_phy
) {
12379 for (phy_index
= EXT_PHY1
; phy_index
< params
->num_phys
;
12381 if (params
->phy
[phy_index
].link_reset
) {
12382 bnx2x_set_aer_mmd(params
,
12383 ¶ms
->phy
[phy_index
]);
12384 params
->phy
[phy_index
].link_reset(
12385 ¶ms
->phy
[phy_index
],
12388 if (params
->phy
[phy_index
].flags
&
12389 FLAGS_REARM_LATCH_SIGNAL
)
12390 clear_latch_ind
= 1;
12394 if (clear_latch_ind
) {
12395 /* Clear latching indication */
12396 bnx2x_rearm_latch_signal(bp
, port
, 0);
12397 bnx2x_bits_dis(bp
, NIG_REG_LATCH_BC_0
+ port
*4,
12398 1 << NIG_LATCH_BC_ENABLE_MI_INT
);
12400 if (params
->phy
[INT_PHY
].link_reset
)
12401 params
->phy
[INT_PHY
].link_reset(
12402 ¶ms
->phy
[INT_PHY
], params
);
12404 /* Disable nig ingress interface */
12405 if (!CHIP_IS_E3(bp
)) {
12407 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
12408 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
));
12409 REG_WR(bp
, NIG_REG_BMAC0_IN_EN
+ port
*4, 0);
12410 REG_WR(bp
, NIG_REG_EMAC0_IN_EN
+ port
*4, 0);
12412 u32 xmac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
12413 bnx2x_set_xumac_nig(params
, 0, 0);
12414 if (REG_RD(bp
, MISC_REG_RESET_REG_2
) &
12415 MISC_REGISTERS_RESET_REG_2_XMAC
)
12416 REG_WR(bp
, xmac_base
+ XMAC_REG_CTRL
,
12417 XMAC_CTRL_REG_SOFT_RESET
);
12420 vars
->phy_flags
= 0;
12424 /****************************************************************************/
12425 /* Common function */
12426 /****************************************************************************/
12427 static int bnx2x_8073_common_init_phy(struct bnx2x
*bp
,
12428 u32 shmem_base_path
[],
12429 u32 shmem2_base_path
[], u8 phy_index
,
12432 struct bnx2x_phy phy
[PORT_MAX
];
12433 struct bnx2x_phy
*phy_blk
[PORT_MAX
];
12436 s8 port_of_path
= 0;
12437 u32 swap_val
, swap_override
;
12438 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
12439 swap_override
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
12440 port
^= (swap_val
&& swap_override
);
12441 bnx2x_ext_phy_hw_reset(bp
, port
);
12442 /* PART1 - Reset both phys */
12443 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12444 u32 shmem_base
, shmem2_base
;
12445 /* In E2, same phy is using for port0 of the two paths */
12446 if (CHIP_IS_E1x(bp
)) {
12447 shmem_base
= shmem_base_path
[0];
12448 shmem2_base
= shmem2_base_path
[0];
12449 port_of_path
= port
;
12451 shmem_base
= shmem_base_path
[port
];
12452 shmem2_base
= shmem2_base_path
[port
];
12456 /* Extract the ext phy address for the port */
12457 if (bnx2x_populate_phy(bp
, phy_index
, shmem_base
, shmem2_base
,
12458 port_of_path
, &phy
[port
]) !=
12460 DP(NETIF_MSG_LINK
, "populate_phy failed\n");
12463 /* Disable attentions */
12464 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+
12466 (NIG_MASK_XGXS0_LINK_STATUS
|
12467 NIG_MASK_XGXS0_LINK10G
|
12468 NIG_MASK_SERDES0_LINK_STATUS
|
12471 /* Need to take the phy out of low power mode in order
12472 * to write to access its registers
12474 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
12475 MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
12478 /* Reset the phy */
12479 bnx2x_cl45_write(bp
, &phy
[port
],
12485 /* Add delay of 150ms after reset */
12488 if (phy
[PORT_0
].addr
& 0x1) {
12489 phy_blk
[PORT_0
] = &(phy
[PORT_1
]);
12490 phy_blk
[PORT_1
] = &(phy
[PORT_0
]);
12492 phy_blk
[PORT_0
] = &(phy
[PORT_0
]);
12493 phy_blk
[PORT_1
] = &(phy
[PORT_1
]);
12496 /* PART2 - Download firmware to both phys */
12497 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12498 if (CHIP_IS_E1x(bp
))
12499 port_of_path
= port
;
12503 DP(NETIF_MSG_LINK
, "Loading spirom for phy address 0x%x\n",
12504 phy_blk
[port
]->addr
);
12505 if (bnx2x_8073_8727_external_rom_boot(bp
, phy_blk
[port
],
12509 /* Only set bit 10 = 1 (Tx power down) */
12510 bnx2x_cl45_read(bp
, phy_blk
[port
],
12512 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
12514 /* Phase1 of TX_POWER_DOWN reset */
12515 bnx2x_cl45_write(bp
, phy_blk
[port
],
12517 MDIO_PMA_REG_TX_POWER_DOWN
,
12521 /* Toggle Transmitter: Power down and then up with 600ms delay
12526 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
12527 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12528 /* Phase2 of POWER_DOWN_RESET */
12529 /* Release bit 10 (Release Tx power down) */
12530 bnx2x_cl45_read(bp
, phy_blk
[port
],
12532 MDIO_PMA_REG_TX_POWER_DOWN
, &val
);
12534 bnx2x_cl45_write(bp
, phy_blk
[port
],
12536 MDIO_PMA_REG_TX_POWER_DOWN
, (val
& (~(1<<10))));
12537 usleep_range(15000, 30000);
12539 /* Read modify write the SPI-ROM version select register */
12540 bnx2x_cl45_read(bp
, phy_blk
[port
],
12542 MDIO_PMA_REG_EDC_FFE_MAIN
, &val
);
12543 bnx2x_cl45_write(bp
, phy_blk
[port
],
12545 MDIO_PMA_REG_EDC_FFE_MAIN
, (val
| (1<<12)));
12547 /* set GPIO2 back to LOW */
12548 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_2
,
12549 MISC_REGISTERS_GPIO_OUTPUT_LOW
, port
);
12553 static int bnx2x_8726_common_init_phy(struct bnx2x
*bp
,
12554 u32 shmem_base_path
[],
12555 u32 shmem2_base_path
[], u8 phy_index
,
12560 struct bnx2x_phy phy
;
12561 /* Use port1 because of the static port-swap */
12562 /* Enable the module detection interrupt */
12563 val
= REG_RD(bp
, MISC_REG_GPIO_EVENT_EN
);
12564 val
|= ((1<<MISC_REGISTERS_GPIO_3
)|
12565 (1<<(MISC_REGISTERS_GPIO_3
+ MISC_REGISTERS_GPIO_PORT_SHIFT
)));
12566 REG_WR(bp
, MISC_REG_GPIO_EVENT_EN
, val
);
12568 bnx2x_ext_phy_hw_reset(bp
, 0);
12569 usleep_range(5000, 10000);
12570 for (port
= 0; port
< PORT_MAX
; port
++) {
12571 u32 shmem_base
, shmem2_base
;
12573 /* In E2, same phy is using for port0 of the two paths */
12574 if (CHIP_IS_E1x(bp
)) {
12575 shmem_base
= shmem_base_path
[0];
12576 shmem2_base
= shmem2_base_path
[0];
12578 shmem_base
= shmem_base_path
[port
];
12579 shmem2_base
= shmem2_base_path
[port
];
12581 /* Extract the ext phy address for the port */
12582 if (bnx2x_populate_phy(bp
, phy_index
, shmem_base
, shmem2_base
,
12585 DP(NETIF_MSG_LINK
, "populate phy failed\n");
12590 bnx2x_cl45_write(bp
, &phy
,
12591 MDIO_PMA_DEVAD
, MDIO_PMA_REG_GEN_CTRL
, 0x0001);
12594 /* Set fault module detected LED on */
12595 bnx2x_set_gpio(bp
, MISC_REGISTERS_GPIO_0
,
12596 MISC_REGISTERS_GPIO_HIGH
,
12602 static void bnx2x_get_ext_phy_reset_gpio(struct bnx2x
*bp
, u32 shmem_base
,
12603 u8
*io_gpio
, u8
*io_port
)
12606 u32 phy_gpio_reset
= REG_RD(bp
, shmem_base
+
12607 offsetof(struct shmem_region
,
12608 dev_info
.port_hw_config
[PORT_0
].default_cfg
));
12609 switch (phy_gpio_reset
) {
12610 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0
:
12614 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0
:
12618 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0
:
12622 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0
:
12626 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1
:
12630 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1
:
12634 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1
:
12638 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1
:
12643 /* Don't override the io_gpio and io_port */
12648 static int bnx2x_8727_common_init_phy(struct bnx2x
*bp
,
12649 u32 shmem_base_path
[],
12650 u32 shmem2_base_path
[], u8 phy_index
,
12653 s8 port
, reset_gpio
;
12654 u32 swap_val
, swap_override
;
12655 struct bnx2x_phy phy
[PORT_MAX
];
12656 struct bnx2x_phy
*phy_blk
[PORT_MAX
];
12658 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
12659 swap_override
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
12661 reset_gpio
= MISC_REGISTERS_GPIO_1
;
12664 /* Retrieve the reset gpio/port which control the reset.
12665 * Default is GPIO1, PORT1
12667 bnx2x_get_ext_phy_reset_gpio(bp
, shmem_base_path
[0],
12668 (u8
*)&reset_gpio
, (u8
*)&port
);
12670 /* Calculate the port based on port swap */
12671 port
^= (swap_val
&& swap_override
);
12673 /* Initiate PHY reset*/
12674 bnx2x_set_gpio(bp
, reset_gpio
, MISC_REGISTERS_GPIO_OUTPUT_LOW
,
12676 usleep_range(1000, 2000);
12677 bnx2x_set_gpio(bp
, reset_gpio
, MISC_REGISTERS_GPIO_OUTPUT_HIGH
,
12680 usleep_range(5000, 10000);
12682 /* PART1 - Reset both phys */
12683 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12684 u32 shmem_base
, shmem2_base
;
12686 /* In E2, same phy is using for port0 of the two paths */
12687 if (CHIP_IS_E1x(bp
)) {
12688 shmem_base
= shmem_base_path
[0];
12689 shmem2_base
= shmem2_base_path
[0];
12690 port_of_path
= port
;
12692 shmem_base
= shmem_base_path
[port
];
12693 shmem2_base
= shmem2_base_path
[port
];
12697 /* Extract the ext phy address for the port */
12698 if (bnx2x_populate_phy(bp
, phy_index
, shmem_base
, shmem2_base
,
12699 port_of_path
, &phy
[port
]) !=
12701 DP(NETIF_MSG_LINK
, "populate phy failed\n");
12704 /* disable attentions */
12705 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+
12707 (NIG_MASK_XGXS0_LINK_STATUS
|
12708 NIG_MASK_XGXS0_LINK10G
|
12709 NIG_MASK_SERDES0_LINK_STATUS
|
12713 /* Reset the phy */
12714 bnx2x_cl45_write(bp
, &phy
[port
],
12715 MDIO_PMA_DEVAD
, MDIO_PMA_REG_CTRL
, 1<<15);
12718 /* Add delay of 150ms after reset */
12720 if (phy
[PORT_0
].addr
& 0x1) {
12721 phy_blk
[PORT_0
] = &(phy
[PORT_1
]);
12722 phy_blk
[PORT_1
] = &(phy
[PORT_0
]);
12724 phy_blk
[PORT_0
] = &(phy
[PORT_0
]);
12725 phy_blk
[PORT_1
] = &(phy
[PORT_1
]);
12727 /* PART2 - Download firmware to both phys */
12728 for (port
= PORT_MAX
- 1; port
>= PORT_0
; port
--) {
12729 if (CHIP_IS_E1x(bp
))
12730 port_of_path
= port
;
12733 DP(NETIF_MSG_LINK
, "Loading spirom for phy address 0x%x\n",
12734 phy_blk
[port
]->addr
);
12735 if (bnx2x_8073_8727_external_rom_boot(bp
, phy_blk
[port
],
12738 /* Disable PHY transmitter output */
12739 bnx2x_cl45_write(bp
, phy_blk
[port
],
12741 MDIO_PMA_REG_TX_DISABLE
, 1);
12747 static int bnx2x_84833_common_init_phy(struct bnx2x
*bp
,
12748 u32 shmem_base_path
[],
12749 u32 shmem2_base_path
[],
12754 reset_gpios
= bnx2x_84833_get_reset_gpios(bp
, shmem_base_path
, chip_id
);
12755 bnx2x_set_mult_gpio(bp
, reset_gpios
, MISC_REGISTERS_GPIO_OUTPUT_LOW
);
12757 bnx2x_set_mult_gpio(bp
, reset_gpios
, MISC_REGISTERS_GPIO_OUTPUT_HIGH
);
12758 DP(NETIF_MSG_LINK
, "84833 reset pulse on pin values 0x%x\n",
12763 static int bnx2x_84833_pre_init_phy(struct bnx2x
*bp
,
12764 struct bnx2x_phy
*phy
)
12767 /* Wait for FW completing its initialization. */
12768 for (cnt
= 0; cnt
< 1500; cnt
++) {
12769 bnx2x_cl45_read(bp
, phy
,
12771 MDIO_PMA_REG_CTRL
, &val
);
12772 if (!(val
& (1<<15)))
12774 usleep_range(1000, 2000);
12777 DP(NETIF_MSG_LINK
, "84833 reset timeout\n");
12781 /* Put the port in super isolate mode. */
12782 bnx2x_cl45_read(bp
, phy
,
12784 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, &val
);
12785 val
|= MDIO_84833_SUPER_ISOLATE
;
12786 bnx2x_cl45_write(bp
, phy
,
12788 MDIO_84833_TOP_CFG_XGPHY_STRAP1
, val
);
12790 /* Save spirom version */
12791 bnx2x_save_848xx_spirom_version(phy
, bp
, PORT_0
);
12795 int bnx2x_pre_init_phy(struct bnx2x
*bp
,
12801 struct bnx2x_phy phy
;
12802 bnx2x_set_mdio_clk(bp
, chip_id
, PORT_0
);
12803 if (bnx2x_populate_phy(bp
, EXT_PHY1
, shmem_base
, shmem2_base
,
12805 DP(NETIF_MSG_LINK
, "populate_phy failed\n");
12808 switch (phy
.type
) {
12809 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
:
12810 rc
= bnx2x_84833_pre_init_phy(bp
, &phy
);
12818 static int bnx2x_ext_phy_common_init(struct bnx2x
*bp
, u32 shmem_base_path
[],
12819 u32 shmem2_base_path
[], u8 phy_index
,
12820 u32 ext_phy_type
, u32 chip_id
)
12824 switch (ext_phy_type
) {
12825 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073
:
12826 rc
= bnx2x_8073_common_init_phy(bp
, shmem_base_path
,
12828 phy_index
, chip_id
);
12830 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722
:
12831 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727
:
12832 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC
:
12833 rc
= bnx2x_8727_common_init_phy(bp
, shmem_base_path
,
12835 phy_index
, chip_id
);
12838 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
:
12839 /* GPIO1 affects both ports, so there's need to pull
12840 * it for single port alone
12842 rc
= bnx2x_8726_common_init_phy(bp
, shmem_base_path
,
12844 phy_index
, chip_id
);
12846 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
:
12847 /* GPIO3's are linked, and so both need to be toggled
12848 * to obtain required 2us pulse.
12850 rc
= bnx2x_84833_common_init_phy(bp
, shmem_base_path
,
12852 phy_index
, chip_id
);
12854 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
:
12859 "ext_phy 0x%x common init not required\n",
12865 netdev_err(bp
->dev
, "Warning: PHY was not initialized,"
12871 int bnx2x_common_init_phy(struct bnx2x
*bp
, u32 shmem_base_path
[],
12872 u32 shmem2_base_path
[], u32 chip_id
)
12877 u32 ext_phy_type
, ext_phy_config
;
12878 bnx2x_set_mdio_clk(bp
, chip_id
, PORT_0
);
12879 bnx2x_set_mdio_clk(bp
, chip_id
, PORT_1
);
12880 DP(NETIF_MSG_LINK
, "Begin common phy init\n");
12881 if (CHIP_IS_E3(bp
)) {
12883 val
= REG_RD(bp
, MISC_REG_GEN_PURP_HWG
);
12884 REG_WR(bp
, MISC_REG_GEN_PURP_HWG
, val
| 1);
12886 /* Check if common init was already done */
12887 phy_ver
= REG_RD(bp
, shmem_base_path
[0] +
12888 offsetof(struct shmem_region
,
12889 port_mb
[PORT_0
].ext_phy_fw_version
));
12891 DP(NETIF_MSG_LINK
, "Not doing common init; phy ver is 0x%x\n",
12896 /* Read the ext_phy_type for arbitrary port(0) */
12897 for (phy_index
= EXT_PHY1
; phy_index
< MAX_PHYS
;
12899 ext_phy_config
= bnx2x_get_ext_phy_config(bp
,
12900 shmem_base_path
[0],
12902 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
12903 rc
|= bnx2x_ext_phy_common_init(bp
, shmem_base_path
,
12905 phy_index
, ext_phy_type
,
12911 static void bnx2x_check_over_curr(struct link_params
*params
,
12912 struct link_vars
*vars
)
12914 struct bnx2x
*bp
= params
->bp
;
12916 u8 port
= params
->port
;
12919 cfg_pin
= (REG_RD(bp
, params
->shmem_base
+
12920 offsetof(struct shmem_region
,
12921 dev_info
.port_hw_config
[port
].e3_cmn_pin_cfg1
)) &
12922 PORT_HW_CFG_E3_OVER_CURRENT_MASK
) >>
12923 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT
;
12925 /* Ignore check if no external input PIN available */
12926 if (bnx2x_get_cfg_pin(bp
, cfg_pin
, &pin_val
) != 0)
12930 if ((vars
->phy_flags
& PHY_OVER_CURRENT_FLAG
) == 0) {
12931 netdev_err(bp
->dev
, "Error: Power fault on Port %d has"
12932 " been detected and the power to "
12933 "that SFP+ module has been removed"
12934 " to prevent failure of the card."
12935 " Please remove the SFP+ module and"
12936 " restart the system to clear this"
12939 vars
->phy_flags
|= PHY_OVER_CURRENT_FLAG
;
12942 vars
->phy_flags
&= ~PHY_OVER_CURRENT_FLAG
;
12945 /* Returns 0 if no change occured since last check; 1 otherwise. */
12946 static u8
bnx2x_analyze_link_error(struct link_params
*params
,
12947 struct link_vars
*vars
, u32 status
,
12948 u32 phy_flag
, u32 link_flag
, u8 notify
)
12950 struct bnx2x
*bp
= params
->bp
;
12951 /* Compare new value with previous value */
12953 u32 old_status
= (vars
->phy_flags
& phy_flag
) ? 1 : 0;
12955 if ((status
^ old_status
) == 0)
12958 /* If values differ */
12959 switch (phy_flag
) {
12960 case PHY_HALF_OPEN_CONN_FLAG
:
12961 DP(NETIF_MSG_LINK
, "Analyze Remote Fault\n");
12963 case PHY_SFP_TX_FAULT_FLAG
:
12964 DP(NETIF_MSG_LINK
, "Analyze TX Fault\n");
12967 DP(NETIF_MSG_LINK
, "Analyze UNKOWN\n");
12969 DP(NETIF_MSG_LINK
, "Link changed:[%x %x]->%x\n", vars
->link_up
,
12970 old_status
, status
);
12972 /* a. Update shmem->link_status accordingly
12973 * b. Update link_vars->link_up
12976 vars
->link_status
&= ~LINK_STATUS_LINK_UP
;
12977 vars
->link_status
|= link_flag
;
12979 vars
->phy_flags
|= phy_flag
;
12981 /* activate nig drain */
12982 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
*4, 1);
12983 /* Set LED mode to off since the PHY doesn't know about these
12986 led_mode
= LED_MODE_OFF
;
12988 vars
->link_status
|= LINK_STATUS_LINK_UP
;
12989 vars
->link_status
&= ~link_flag
;
12991 vars
->phy_flags
&= ~phy_flag
;
12992 led_mode
= LED_MODE_OPER
;
12994 /* Clear nig drain */
12995 REG_WR(bp
, NIG_REG_EGRESS_DRAIN0_MODE
+ params
->port
*4, 0);
12997 bnx2x_sync_link(params
, vars
);
12998 /* Update the LED according to the link state */
12999 bnx2x_set_led(params
, vars
, led_mode
, SPEED_10000
);
13001 /* Update link status in the shared memory */
13002 bnx2x_update_mng(params
, vars
->link_status
);
13004 /* C. Trigger General Attention */
13005 vars
->periodic_flags
|= PERIODIC_FLAGS_LINK_EVENT
;
13007 bnx2x_notify_link_changed(bp
);
13012 /******************************************************************************
13014 * This function checks for half opened connection change indication.
13015 * When such change occurs, it calls the bnx2x_analyze_link_error
13016 * to check if Remote Fault is set or cleared. Reception of remote fault
13017 * status message in the MAC indicates that the peer's MAC has detected
13018 * a fault, for example, due to break in the TX side of fiber.
13020 ******************************************************************************/
13021 int bnx2x_check_half_open_conn(struct link_params
*params
,
13022 struct link_vars
*vars
,
13025 struct bnx2x
*bp
= params
->bp
;
13026 u32 lss_status
= 0;
13028 /* In case link status is physically up @ 10G do */
13029 if (((vars
->phy_flags
& PHY_PHYSICAL_LINK_FLAG
) == 0) ||
13030 (REG_RD(bp
, NIG_REG_EGRESS_EMAC0_PORT
+ params
->port
*4)))
13033 if (CHIP_IS_E3(bp
) &&
13034 (REG_RD(bp
, MISC_REG_RESET_REG_2
) &
13035 (MISC_REGISTERS_RESET_REG_2_XMAC
))) {
13036 /* Check E3 XMAC */
13037 /* Note that link speed cannot be queried here, since it may be
13038 * zero while link is down. In case UMAC is active, LSS will
13039 * simply not be set
13041 mac_base
= (params
->port
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
13043 /* Clear stick bits (Requires rising edge) */
13044 REG_WR(bp
, mac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
, 0);
13045 REG_WR(bp
, mac_base
+ XMAC_REG_CLEAR_RX_LSS_STATUS
,
13046 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS
|
13047 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS
);
13048 if (REG_RD(bp
, mac_base
+ XMAC_REG_RX_LSS_STATUS
))
13051 bnx2x_analyze_link_error(params
, vars
, lss_status
,
13052 PHY_HALF_OPEN_CONN_FLAG
,
13053 LINK_STATUS_NONE
, notify
);
13054 } else if (REG_RD(bp
, MISC_REG_RESET_REG_2
) &
13055 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< params
->port
)) {
13056 /* Check E1X / E2 BMAC */
13057 u32 lss_status_reg
;
13059 mac_base
= params
->port
? NIG_REG_INGRESS_BMAC1_MEM
:
13060 NIG_REG_INGRESS_BMAC0_MEM
;
13061 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
13062 if (CHIP_IS_E2(bp
))
13063 lss_status_reg
= BIGMAC2_REGISTER_RX_LSS_STAT
;
13065 lss_status_reg
= BIGMAC_REGISTER_RX_LSS_STATUS
;
13067 REG_RD_DMAE(bp
, mac_base
+ lss_status_reg
, wb_data
, 2);
13068 lss_status
= (wb_data
[0] > 0);
13070 bnx2x_analyze_link_error(params
, vars
, lss_status
,
13071 PHY_HALF_OPEN_CONN_FLAG
,
13072 LINK_STATUS_NONE
, notify
);
13076 static void bnx2x_sfp_tx_fault_detection(struct bnx2x_phy
*phy
,
13077 struct link_params
*params
,
13078 struct link_vars
*vars
)
13080 struct bnx2x
*bp
= params
->bp
;
13081 u32 cfg_pin
, value
= 0;
13082 u8 led_change
, port
= params
->port
;
13084 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
13085 cfg_pin
= (REG_RD(bp
, params
->shmem_base
+ offsetof(struct shmem_region
,
13086 dev_info
.port_hw_config
[port
].e3_cmn_pin_cfg
)) &
13087 PORT_HW_CFG_E3_TX_FAULT_MASK
) >>
13088 PORT_HW_CFG_E3_TX_FAULT_SHIFT
;
13090 if (bnx2x_get_cfg_pin(bp
, cfg_pin
, &value
)) {
13091 DP(NETIF_MSG_LINK
, "Failed to read pin 0x%02x\n", cfg_pin
);
13095 led_change
= bnx2x_analyze_link_error(params
, vars
, value
,
13096 PHY_SFP_TX_FAULT_FLAG
,
13097 LINK_STATUS_SFP_TX_FAULT
, 1);
13100 /* Change TX_Fault led, set link status for further syncs */
13103 if (vars
->phy_flags
& PHY_SFP_TX_FAULT_FLAG
) {
13104 led_mode
= MISC_REGISTERS_GPIO_HIGH
;
13105 vars
->link_status
|= LINK_STATUS_SFP_TX_FAULT
;
13107 led_mode
= MISC_REGISTERS_GPIO_LOW
;
13108 vars
->link_status
&= ~LINK_STATUS_SFP_TX_FAULT
;
13111 /* If module is unapproved, led should be on regardless */
13112 if (!(phy
->flags
& FLAGS_SFP_NOT_APPROVED
)) {
13113 DP(NETIF_MSG_LINK
, "Change TX_Fault LED: ->%x\n",
13115 bnx2x_set_e3_module_fault_led(params
, led_mode
);
13119 void bnx2x_period_func(struct link_params
*params
, struct link_vars
*vars
)
13122 struct bnx2x
*bp
= params
->bp
;
13123 for (phy_idx
= INT_PHY
; phy_idx
< MAX_PHYS
; phy_idx
++) {
13124 if (params
->phy
[phy_idx
].flags
& FLAGS_TX_ERROR_CHECK
) {
13125 bnx2x_set_aer_mmd(params
, ¶ms
->phy
[phy_idx
]);
13126 if (bnx2x_check_half_open_conn(params
, vars
, 1) !=
13128 DP(NETIF_MSG_LINK
, "Fault detection failed\n");
13133 if (CHIP_IS_E3(bp
)) {
13134 struct bnx2x_phy
*phy
= ¶ms
->phy
[INT_PHY
];
13135 bnx2x_set_aer_mmd(params
, phy
);
13136 bnx2x_check_over_curr(params
, vars
);
13137 if (vars
->rx_tx_asic_rst
)
13138 bnx2x_warpcore_config_runtime(phy
, params
, vars
);
13140 if ((REG_RD(bp
, params
->shmem_base
+
13141 offsetof(struct shmem_region
, dev_info
.
13142 port_hw_config
[params
->port
].default_cfg
))
13143 & PORT_HW_CFG_NET_SERDES_IF_MASK
) ==
13144 PORT_HW_CFG_NET_SERDES_IF_SFI
) {
13145 if (bnx2x_is_sfp_module_plugged(phy
, params
)) {
13146 bnx2x_sfp_tx_fault_detection(phy
, params
, vars
);
13147 } else if (vars
->link_status
&
13148 LINK_STATUS_SFP_TX_FAULT
) {
13149 /* Clean trail, interrupt corrects the leds */
13150 vars
->link_status
&= ~LINK_STATUS_SFP_TX_FAULT
;
13151 vars
->phy_flags
&= ~PHY_SFP_TX_FAULT_FLAG
;
13152 /* Update link status in the shared memory */
13153 bnx2x_update_mng(params
, vars
->link_status
);
13161 u8
bnx2x_hw_lock_required(struct bnx2x
*bp
, u32 shmem_base
, u32 shmem2_base
)
13164 struct bnx2x_phy phy
;
13165 for (phy_index
= INT_PHY
; phy_index
< MAX_PHYS
;
13167 if (bnx2x_populate_phy(bp
, phy_index
, shmem_base
, shmem2_base
,
13169 DP(NETIF_MSG_LINK
, "populate phy failed\n");
13173 if (phy
.flags
& FLAGS_HW_LOCK_REQUIRED
)
13179 u8
bnx2x_fan_failure_det_req(struct bnx2x
*bp
,
13184 u8 phy_index
, fan_failure_det_req
= 0;
13185 struct bnx2x_phy phy
;
13186 for (phy_index
= EXT_PHY1
; phy_index
< MAX_PHYS
;
13188 if (bnx2x_populate_phy(bp
, phy_index
, shmem_base
, shmem2_base
,
13191 DP(NETIF_MSG_LINK
, "populate phy failed\n");
13194 fan_failure_det_req
|= (phy
.flags
&
13195 FLAGS_FAN_FAILURE_DET_REQ
);
13197 return fan_failure_det_req
;
13200 void bnx2x_hw_reset_phy(struct link_params
*params
)
13203 struct bnx2x
*bp
= params
->bp
;
13204 bnx2x_update_mng(params
, 0);
13205 bnx2x_bits_dis(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ params
->port
*4,
13206 (NIG_MASK_XGXS0_LINK_STATUS
|
13207 NIG_MASK_XGXS0_LINK10G
|
13208 NIG_MASK_SERDES0_LINK_STATUS
|
13211 for (phy_index
= INT_PHY
; phy_index
< MAX_PHYS
;
13213 if (params
->phy
[phy_index
].hw_reset
) {
13214 params
->phy
[phy_index
].hw_reset(
13215 ¶ms
->phy
[phy_index
],
13217 params
->phy
[phy_index
] = phy_null
;
13222 void bnx2x_init_mod_abs_int(struct bnx2x
*bp
, struct link_vars
*vars
,
13223 u32 chip_id
, u32 shmem_base
, u32 shmem2_base
,
13226 u8 gpio_num
= 0xff, gpio_port
= 0xff, phy_index
;
13228 u32 offset
, aeu_mask
, swap_val
, swap_override
, sync_offset
;
13229 if (CHIP_IS_E3(bp
)) {
13230 if (bnx2x_get_mod_abs_int_cfg(bp
, chip_id
,
13237 struct bnx2x_phy phy
;
13238 for (phy_index
= EXT_PHY1
; phy_index
< MAX_PHYS
;
13240 if (bnx2x_populate_phy(bp
, phy_index
, shmem_base
,
13241 shmem2_base
, port
, &phy
)
13243 DP(NETIF_MSG_LINK
, "populate phy failed\n");
13246 if (phy
.type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726
) {
13247 gpio_num
= MISC_REGISTERS_GPIO_3
;
13254 if (gpio_num
== 0xff)
13257 /* Set GPIO3 to trigger SFP+ module insertion/removal */
13258 bnx2x_set_gpio(bp
, gpio_num
, MISC_REGISTERS_GPIO_INPUT_HI_Z
, gpio_port
);
13260 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
13261 swap_override
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
13262 gpio_port
^= (swap_val
&& swap_override
);
13264 vars
->aeu_int_mask
= AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0
<<
13265 (gpio_num
+ (gpio_port
<< 2));
13267 sync_offset
= shmem_base
+
13268 offsetof(struct shmem_region
,
13269 dev_info
.port_hw_config
[port
].aeu_int_mask
);
13270 REG_WR(bp
, sync_offset
, vars
->aeu_int_mask
);
13272 DP(NETIF_MSG_LINK
, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
13273 gpio_num
, gpio_port
, vars
->aeu_int_mask
);
13276 offset
= MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
;
13278 offset
= MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
;
13280 /* Open appropriate AEU for interrupts */
13281 aeu_mask
= REG_RD(bp
, offset
);
13282 aeu_mask
|= vars
->aeu_int_mask
;
13283 REG_WR(bp
, offset
, aeu_mask
);
13285 /* Enable the GPIO to trigger interrupt */
13286 val
= REG_RD(bp
, MISC_REG_GPIO_EVENT_EN
);
13287 val
|= 1 << (gpio_num
+ (gpio_port
<< 2));
13288 REG_WR(bp
, MISC_REG_GPIO_EVENT_EN
, val
);