1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_dcb.h"
66 #include <linux/firmware.h>
67 #include "bnx2x_fw_file_hdr.h"
69 #define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
78 /* Time in jiffies before concluding the transmitter is hung */
79 #define TX_TIMEOUT (5*HZ)
81 static char version
[] =
82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
83 DRV_MODULE_NAME
" " DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
85 MODULE_AUTHOR("Eliezer Tamir");
86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
87 "BCM57710/57711/57711E/"
88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
89 "57840/57840_MF Driver");
90 MODULE_LICENSE("GPL");
91 MODULE_VERSION(DRV_MODULE_VERSION
);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1
);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1H
);
94 MODULE_FIRMWARE(FW_FILE_NAME_E2
);
98 module_param(num_queues
, int, 0);
99 MODULE_PARM_DESC(num_queues
,
100 " Set number of queues (default is as a number of CPUs)");
102 static int disable_tpa
;
103 module_param(disable_tpa
, int, 0);
104 MODULE_PARM_DESC(disable_tpa
, " Disable the TPA (LRO) feature");
106 #define INT_MODE_INTx 1
107 #define INT_MODE_MSI 2
109 module_param(int_mode
, int, 0);
110 MODULE_PARM_DESC(int_mode
, " Force interrupt mode other than MSI-X "
113 static int dropless_fc
;
114 module_param(dropless_fc
, int, 0);
115 MODULE_PARM_DESC(dropless_fc
, " Pause on exhausted host ring");
117 static int mrrs
= -1;
118 module_param(mrrs
, int, 0);
119 MODULE_PARM_DESC(mrrs
, " Force Max Read Req Size (0..3) (for debug)");
122 module_param(debug
, int, 0);
123 MODULE_PARM_DESC(debug
, " Default debug msglevel");
127 struct workqueue_struct
*bnx2x_wq
;
129 struct bnx2x_mac_vals
{
140 enum bnx2x_board_type
{
164 /* indexed by board_type, above */
168 [BCM57710
] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
169 [BCM57711
] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
170 [BCM57711E
] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
171 [BCM57712
] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
172 [BCM57712_MF
] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
173 [BCM57712_VF
] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
174 [BCM57800
] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
175 [BCM57800_MF
] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
176 [BCM57800_VF
] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
177 [BCM57810
] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
178 [BCM57810_MF
] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
179 [BCM57810_VF
] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
180 [BCM57840_4_10
] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
181 [BCM57840_2_20
] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
182 [BCM57840_MF
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57840_VF
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
184 [BCM57811
] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
185 [BCM57811_MF
] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
186 [BCM57840_O
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
187 [BCM57840_MFO
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
188 [BCM57811_VF
] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
191 #ifndef PCI_DEVICE_ID_NX2_57710
192 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
194 #ifndef PCI_DEVICE_ID_NX2_57711
195 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
197 #ifndef PCI_DEVICE_ID_NX2_57711E
198 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
200 #ifndef PCI_DEVICE_ID_NX2_57712
201 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
204 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
207 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
209 #ifndef PCI_DEVICE_ID_NX2_57800
210 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
213 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
216 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
218 #ifndef PCI_DEVICE_ID_NX2_57810
219 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
222 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
224 #ifndef PCI_DEVICE_ID_NX2_57840_O
225 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
228 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
231 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
234 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
237 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
240 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
243 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
245 #ifndef PCI_DEVICE_ID_NX2_57811
246 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
249 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
252 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
255 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl
) = {
256 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57710
), BCM57710
},
257 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711
), BCM57711
},
258 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711E
), BCM57711E
},
259 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712
), BCM57712
},
260 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_MF
), BCM57712_MF
},
261 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_VF
), BCM57712_VF
},
262 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800
), BCM57800
},
263 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_MF
), BCM57800_MF
},
264 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_VF
), BCM57800_VF
},
265 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810
), BCM57810
},
266 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_MF
), BCM57810_MF
},
267 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_O
), BCM57840_O
},
268 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_4_10
), BCM57840_4_10
},
269 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_2_20
), BCM57840_2_20
},
270 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_VF
), BCM57810_VF
},
271 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MFO
), BCM57840_MFO
},
272 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
273 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_VF
), BCM57840_VF
},
274 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811
), BCM57811
},
275 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_MF
), BCM57811_MF
},
276 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_VF
), BCM57811_VF
},
280 MODULE_DEVICE_TABLE(pci
, bnx2x_pci_tbl
);
282 /* Global resources for unloading a previously loaded device */
283 #define BNX2X_PREV_WAIT_NEEDED 1
284 static DEFINE_SEMAPHORE(bnx2x_prev_sem
);
285 static LIST_HEAD(bnx2x_prev_list
);
286 /****************************************************************************
287 * General service functions
288 ****************************************************************************/
290 static void __storm_memset_dma_mapping(struct bnx2x
*bp
,
291 u32 addr
, dma_addr_t mapping
)
293 REG_WR(bp
, addr
, U64_LO(mapping
));
294 REG_WR(bp
, addr
+ 4, U64_HI(mapping
));
297 static void storm_memset_spq_addr(struct bnx2x
*bp
,
298 dma_addr_t mapping
, u16 abs_fid
)
300 u32 addr
= XSEM_REG_FAST_MEMORY
+
301 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid
);
303 __storm_memset_dma_mapping(bp
, addr
, mapping
);
306 static void storm_memset_vf_to_pf(struct bnx2x
*bp
, u16 abs_fid
,
309 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_VF_TO_PF_OFFSET(abs_fid
),
311 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_VF_TO_PF_OFFSET(abs_fid
),
313 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_VF_TO_PF_OFFSET(abs_fid
),
315 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_VF_TO_PF_OFFSET(abs_fid
),
319 static void storm_memset_func_en(struct bnx2x
*bp
, u16 abs_fid
,
322 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(abs_fid
),
324 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(abs_fid
),
326 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(abs_fid
),
328 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(abs_fid
),
332 static void storm_memset_eq_data(struct bnx2x
*bp
,
333 struct event_ring_data
*eq_data
,
336 size_t size
= sizeof(struct event_ring_data
);
338 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_DATA_OFFSET(pfid
);
340 __storm_memset_struct(bp
, addr
, size
, (u32
*)eq_data
);
343 static void storm_memset_eq_prod(struct bnx2x
*bp
, u16 eq_prod
,
346 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_PROD_OFFSET(pfid
);
347 REG_WR16(bp
, addr
, eq_prod
);
351 * locking is done by mcp
353 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
)
355 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
356 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, val
);
357 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
358 PCICFG_VENDOR_ID_OFFSET
);
361 static u32
bnx2x_reg_rd_ind(struct bnx2x
*bp
, u32 addr
)
365 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
366 pci_read_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, &val
);
367 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
368 PCICFG_VENDOR_ID_OFFSET
);
373 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
374 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
375 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
376 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
377 #define DMAE_DP_DST_NONE "dst_addr [none]"
379 void bnx2x_dp_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int msglvl
)
381 u32 src_type
= dmae
->opcode
& DMAE_COMMAND_SRC
;
383 switch (dmae
->opcode
& DMAE_COMMAND_DST
) {
384 case DMAE_CMD_DST_PCI
:
385 if (src_type
== DMAE_CMD_SRC_PCI
)
386 DP(msglvl
, "DMAE: opcode 0x%08x\n"
387 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
388 "comp_addr [%x:%08x], comp_val 0x%08x\n",
389 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
390 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
391 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
394 DP(msglvl
, "DMAE: opcode 0x%08x\n"
395 "src [%08x], len [%d*4], dst [%x:%08x]\n"
396 "comp_addr [%x:%08x], comp_val 0x%08x\n",
397 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
398 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
399 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
402 case DMAE_CMD_DST_GRC
:
403 if (src_type
== DMAE_CMD_SRC_PCI
)
404 DP(msglvl
, "DMAE: opcode 0x%08x\n"
405 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
406 "comp_addr [%x:%08x], comp_val 0x%08x\n",
407 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
408 dmae
->len
, dmae
->dst_addr_lo
>> 2,
409 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
412 DP(msglvl
, "DMAE: opcode 0x%08x\n"
413 "src [%08x], len [%d*4], dst [%08x]\n"
414 "comp_addr [%x:%08x], comp_val 0x%08x\n",
415 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
416 dmae
->len
, dmae
->dst_addr_lo
>> 2,
417 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
421 if (src_type
== DMAE_CMD_SRC_PCI
)
422 DP(msglvl
, "DMAE: opcode 0x%08x\n"
423 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
424 "comp_addr [%x:%08x] comp_val 0x%08x\n",
425 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
426 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
429 DP(msglvl
, "DMAE: opcode 0x%08x\n"
430 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
431 "comp_addr [%x:%08x] comp_val 0x%08x\n",
432 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
433 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
439 /* copy command into DMAE command memory and set DMAE command go */
440 void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int idx
)
445 cmd_offset
= (DMAE_REG_CMD_MEM
+ sizeof(struct dmae_command
) * idx
);
446 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++) {
447 REG_WR(bp
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
449 REG_WR(bp
, dmae_reg_go_c
[idx
], 1);
452 u32
bnx2x_dmae_opcode_add_comp(u32 opcode
, u8 comp_type
)
454 return opcode
| ((comp_type
<< DMAE_COMMAND_C_DST_SHIFT
) |
458 u32
bnx2x_dmae_opcode_clr_src_reset(u32 opcode
)
460 return opcode
& ~DMAE_CMD_SRC_RESET
;
463 u32
bnx2x_dmae_opcode(struct bnx2x
*bp
, u8 src_type
, u8 dst_type
,
464 bool with_comp
, u8 comp_type
)
468 opcode
|= ((src_type
<< DMAE_COMMAND_SRC_SHIFT
) |
469 (dst_type
<< DMAE_COMMAND_DST_SHIFT
));
471 opcode
|= (DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
);
473 opcode
|= (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
);
474 opcode
|= ((BP_VN(bp
) << DMAE_CMD_E1HVN_SHIFT
) |
475 (BP_VN(bp
) << DMAE_COMMAND_DST_VN_SHIFT
));
476 opcode
|= (DMAE_COM_SET_ERR
<< DMAE_COMMAND_ERR_POLICY_SHIFT
);
479 opcode
|= DMAE_CMD_ENDIANITY_B_DW_SWAP
;
481 opcode
|= DMAE_CMD_ENDIANITY_DW_SWAP
;
484 opcode
= bnx2x_dmae_opcode_add_comp(opcode
, comp_type
);
488 void bnx2x_prep_dmae_with_comp(struct bnx2x
*bp
,
489 struct dmae_command
*dmae
,
490 u8 src_type
, u8 dst_type
)
492 memset(dmae
, 0, sizeof(struct dmae_command
));
495 dmae
->opcode
= bnx2x_dmae_opcode(bp
, src_type
, dst_type
,
496 true, DMAE_COMP_PCI
);
498 /* fill in the completion parameters */
499 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
500 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
501 dmae
->comp_val
= DMAE_COMP_VAL
;
504 /* issue a dmae command over the init-channel and wait for completion */
505 int bnx2x_issue_dmae_with_comp(struct bnx2x
*bp
, struct dmae_command
*dmae
)
507 u32
*wb_comp
= bnx2x_sp(bp
, wb_comp
);
508 int cnt
= CHIP_REV_IS_SLOW(bp
) ? (400000) : 4000;
512 * Lock the dmae channel. Disable BHs to prevent a dead-lock
513 * as long as this code is called both from syscall context and
514 * from ndo_set_rx_mode() flow that may be called from BH.
516 spin_lock_bh(&bp
->dmae_lock
);
518 /* reset completion */
521 /* post the command on the channel used for initializations */
522 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
524 /* wait for completion */
526 while ((*wb_comp
& ~DMAE_PCI_ERR_FLAG
) != DMAE_COMP_VAL
) {
529 (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
&&
530 bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
531 BNX2X_ERR("DMAE timeout!\n");
538 if (*wb_comp
& DMAE_PCI_ERR_FLAG
) {
539 BNX2X_ERR("DMAE PCI error!\n");
544 spin_unlock_bh(&bp
->dmae_lock
);
548 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
551 struct dmae_command dmae
;
553 if (!bp
->dmae_ready
) {
554 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
557 bnx2x_init_ind_wr(bp
, dst_addr
, data
, len32
);
559 bnx2x_init_str_wr(bp
, dst_addr
, data
, len32
);
563 /* set opcode and fixed command fields */
564 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_PCI
, DMAE_DST_GRC
);
566 /* fill in addresses and len */
567 dmae
.src_addr_lo
= U64_LO(dma_addr
);
568 dmae
.src_addr_hi
= U64_HI(dma_addr
);
569 dmae
.dst_addr_lo
= dst_addr
>> 2;
570 dmae
.dst_addr_hi
= 0;
573 /* issue the command and wait for completion */
574 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
577 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
)
579 struct dmae_command dmae
;
581 if (!bp
->dmae_ready
) {
582 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
586 for (i
= 0; i
< len32
; i
++)
587 data
[i
] = bnx2x_reg_rd_ind(bp
, src_addr
+ i
*4);
589 for (i
= 0; i
< len32
; i
++)
590 data
[i
] = REG_RD(bp
, src_addr
+ i
*4);
595 /* set opcode and fixed command fields */
596 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_GRC
, DMAE_DST_PCI
);
598 /* fill in addresses and len */
599 dmae
.src_addr_lo
= src_addr
>> 2;
600 dmae
.src_addr_hi
= 0;
601 dmae
.dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_data
));
602 dmae
.dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_data
));
605 /* issue the command and wait for completion */
606 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
609 static void bnx2x_write_dmae_phys_len(struct bnx2x
*bp
, dma_addr_t phys_addr
,
612 int dmae_wr_max
= DMAE_LEN32_WR_MAX(bp
);
615 while (len
> dmae_wr_max
) {
616 bnx2x_write_dmae(bp
, phys_addr
+ offset
,
617 addr
+ offset
, dmae_wr_max
);
618 offset
+= dmae_wr_max
* 4;
622 bnx2x_write_dmae(bp
, phys_addr
+ offset
, addr
+ offset
, len
);
625 static int bnx2x_mc_assert(struct bnx2x
*bp
)
629 u32 row0
, row1
, row2
, row3
;
632 last_idx
= REG_RD8(bp
, BAR_XSTRORM_INTMEM
+
633 XSTORM_ASSERT_LIST_INDEX_OFFSET
);
635 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
637 /* print the asserts */
638 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
640 row0
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
641 XSTORM_ASSERT_LIST_OFFSET(i
));
642 row1
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
643 XSTORM_ASSERT_LIST_OFFSET(i
) + 4);
644 row2
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
645 XSTORM_ASSERT_LIST_OFFSET(i
) + 8);
646 row3
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
647 XSTORM_ASSERT_LIST_OFFSET(i
) + 12);
649 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
650 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
651 i
, row3
, row2
, row1
, row0
);
659 last_idx
= REG_RD8(bp
, BAR_TSTRORM_INTMEM
+
660 TSTORM_ASSERT_LIST_INDEX_OFFSET
);
662 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
664 /* print the asserts */
665 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
667 row0
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
668 TSTORM_ASSERT_LIST_OFFSET(i
));
669 row1
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
670 TSTORM_ASSERT_LIST_OFFSET(i
) + 4);
671 row2
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
672 TSTORM_ASSERT_LIST_OFFSET(i
) + 8);
673 row3
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
674 TSTORM_ASSERT_LIST_OFFSET(i
) + 12);
676 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
677 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
678 i
, row3
, row2
, row1
, row0
);
686 last_idx
= REG_RD8(bp
, BAR_CSTRORM_INTMEM
+
687 CSTORM_ASSERT_LIST_INDEX_OFFSET
);
689 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
691 /* print the asserts */
692 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
694 row0
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
695 CSTORM_ASSERT_LIST_OFFSET(i
));
696 row1
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
697 CSTORM_ASSERT_LIST_OFFSET(i
) + 4);
698 row2
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
699 CSTORM_ASSERT_LIST_OFFSET(i
) + 8);
700 row3
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
701 CSTORM_ASSERT_LIST_OFFSET(i
) + 12);
703 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
704 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
705 i
, row3
, row2
, row1
, row0
);
713 last_idx
= REG_RD8(bp
, BAR_USTRORM_INTMEM
+
714 USTORM_ASSERT_LIST_INDEX_OFFSET
);
716 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
718 /* print the asserts */
719 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
721 row0
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
722 USTORM_ASSERT_LIST_OFFSET(i
));
723 row1
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
724 USTORM_ASSERT_LIST_OFFSET(i
) + 4);
725 row2
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
726 USTORM_ASSERT_LIST_OFFSET(i
) + 8);
727 row3
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
728 USTORM_ASSERT_LIST_OFFSET(i
) + 12);
730 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
731 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
732 i
, row3
, row2
, row1
, row0
);
742 void bnx2x_fw_dump_lvl(struct bnx2x
*bp
, const char *lvl
)
748 u32 trace_shmem_base
;
750 BNX2X_ERR("NO MCP - can not dump\n");
753 netdev_printk(lvl
, bp
->dev
, "bc %d.%d.%d\n",
754 (bp
->common
.bc_ver
& 0xff0000) >> 16,
755 (bp
->common
.bc_ver
& 0xff00) >> 8,
756 (bp
->common
.bc_ver
& 0xff));
758 val
= REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
);
759 if (val
== REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
))
760 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl
, val
);
762 if (BP_PATH(bp
) == 0)
763 trace_shmem_base
= bp
->common
.shmem_base
;
765 trace_shmem_base
= SHMEM2_RD(bp
, other_shmem_base_addr
);
766 addr
= trace_shmem_base
- 0x800;
768 /* validate TRCB signature */
769 mark
= REG_RD(bp
, addr
);
770 if (mark
!= MFW_TRACE_SIGNATURE
) {
771 BNX2X_ERR("Trace buffer signature is missing.");
775 /* read cyclic buffer pointer */
777 mark
= REG_RD(bp
, addr
);
778 mark
= (CHIP_IS_E1x(bp
) ? MCP_REG_MCPR_SCRATCH
: MCP_A_REG_MCPR_SCRATCH
)
779 + ((mark
+ 0x3) & ~0x3) - 0x08000000;
780 printk("%s" "begin fw dump (mark 0x%x)\n", lvl
, mark
);
784 /* dump buffer after the mark */
785 for (offset
= mark
; offset
<= trace_shmem_base
; offset
+= 0x8*4) {
786 for (word
= 0; word
< 8; word
++)
787 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
789 pr_cont("%s", (char *)data
);
792 /* dump buffer before the mark */
793 for (offset
= addr
+ 4; offset
<= mark
; offset
+= 0x8*4) {
794 for (word
= 0; word
< 8; word
++)
795 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
797 pr_cont("%s", (char *)data
);
799 printk("%s" "end of fw dump\n", lvl
);
802 static void bnx2x_fw_dump(struct bnx2x
*bp
)
804 bnx2x_fw_dump_lvl(bp
, KERN_ERR
);
807 static void bnx2x_hc_int_disable(struct bnx2x
*bp
)
809 int port
= BP_PORT(bp
);
810 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
811 u32 val
= REG_RD(bp
, addr
);
813 /* in E1 we must use only PCI configuration space to disable
814 * MSI/MSIX capablility
815 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
817 if (CHIP_IS_E1(bp
)) {
818 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
819 * Use mask register to prevent from HC sending interrupts
820 * after we exit the function
822 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0);
824 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
825 HC_CONFIG_0_REG_INT_LINE_EN_0
|
826 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
828 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
829 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
830 HC_CONFIG_0_REG_INT_LINE_EN_0
|
831 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
834 "write %x to HC %d (addr 0x%x)\n",
837 /* flush all outstanding writes */
840 REG_WR(bp
, addr
, val
);
841 if (REG_RD(bp
, addr
) != val
)
842 BNX2X_ERR("BUG! proper val not read from IGU!\n");
845 static void bnx2x_igu_int_disable(struct bnx2x
*bp
)
847 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
849 val
&= ~(IGU_PF_CONF_MSI_MSIX_EN
|
850 IGU_PF_CONF_INT_LINE_EN
|
851 IGU_PF_CONF_ATTN_BIT_EN
);
853 DP(NETIF_MSG_IFDOWN
, "write %x to IGU\n", val
);
855 /* flush all outstanding writes */
858 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
859 if (REG_RD(bp
, IGU_REG_PF_CONFIGURATION
) != val
)
860 BNX2X_ERR("BUG! proper val not read from IGU!\n");
863 static void bnx2x_int_disable(struct bnx2x
*bp
)
865 if (bp
->common
.int_block
== INT_BLOCK_HC
)
866 bnx2x_hc_int_disable(bp
);
868 bnx2x_igu_int_disable(bp
);
871 void bnx2x_panic_dump(struct bnx2x
*bp
, bool disable_int
)
875 struct hc_sp_status_block_data sp_sb_data
;
876 int func
= BP_FUNC(bp
);
877 #ifdef BNX2X_STOP_ON_ERROR
878 u16 start
= 0, end
= 0;
882 bnx2x_int_disable(bp
);
884 bp
->stats_state
= STATS_STATE_DISABLED
;
885 bp
->eth_stats
.unrecoverable_error
++;
886 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
888 BNX2X_ERR("begin crash dump -----------------\n");
892 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
893 bp
->def_idx
, bp
->def_att_idx
, bp
->attn_state
,
894 bp
->spq_prod_idx
, bp
->stats_counter
);
895 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
896 bp
->def_status_blk
->atten_status_block
.attn_bits
,
897 bp
->def_status_blk
->atten_status_block
.attn_bits_ack
,
898 bp
->def_status_blk
->atten_status_block
.status_block_id
,
899 bp
->def_status_blk
->atten_status_block
.attn_bits_index
);
901 for (i
= 0; i
< HC_SP_SB_MAX_INDICES
; i
++)
903 bp
->def_status_blk
->sp_sb
.index_values
[i
],
904 (i
== HC_SP_SB_MAX_INDICES
- 1) ? ") " : " ");
906 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
907 *((u32
*)&sp_sb_data
+ i
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
908 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
911 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
912 sp_sb_data
.igu_sb_id
,
913 sp_sb_data
.igu_seg_id
,
914 sp_sb_data
.p_func
.pf_id
,
915 sp_sb_data
.p_func
.vnic_id
,
916 sp_sb_data
.p_func
.vf_id
,
917 sp_sb_data
.p_func
.vf_valid
,
921 for_each_eth_queue(bp
, i
) {
922 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
924 struct hc_status_block_data_e2 sb_data_e2
;
925 struct hc_status_block_data_e1x sb_data_e1x
;
926 struct hc_status_block_sm
*hc_sm_p
=
928 sb_data_e1x
.common
.state_machine
:
929 sb_data_e2
.common
.state_machine
;
930 struct hc_index_data
*hc_index_p
=
932 sb_data_e1x
.index_data
:
933 sb_data_e2
.index_data
;
936 struct bnx2x_fp_txdata txdata
;
939 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
940 i
, fp
->rx_bd_prod
, fp
->rx_bd_cons
,
942 fp
->rx_comp_cons
, le16_to_cpu(*fp
->rx_cons_sb
));
943 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
944 fp
->rx_sge_prod
, fp
->last_max_sge
,
945 le16_to_cpu(fp
->fp_hc_idx
));
948 for_each_cos_in_tx_queue(fp
, cos
)
950 txdata
= *fp
->txdata_ptr
[cos
];
951 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
952 i
, txdata
.tx_pkt_prod
,
953 txdata
.tx_pkt_cons
, txdata
.tx_bd_prod
,
955 le16_to_cpu(*txdata
.tx_cons_sb
));
958 loop
= CHIP_IS_E1x(bp
) ?
959 HC_SB_MAX_INDICES_E1X
: HC_SB_MAX_INDICES_E2
;
966 BNX2X_ERR(" run indexes (");
967 for (j
= 0; j
< HC_SB_MAX_SM
; j
++)
969 fp
->sb_running_index
[j
],
970 (j
== HC_SB_MAX_SM
- 1) ? ")" : " ");
972 BNX2X_ERR(" indexes (");
973 for (j
= 0; j
< loop
; j
++)
975 fp
->sb_index_values
[j
],
976 (j
== loop
- 1) ? ")" : " ");
978 data_size
= CHIP_IS_E1x(bp
) ?
979 sizeof(struct hc_status_block_data_e1x
) :
980 sizeof(struct hc_status_block_data_e2
);
981 data_size
/= sizeof(u32
);
982 sb_data_p
= CHIP_IS_E1x(bp
) ?
983 (u32
*)&sb_data_e1x
:
985 /* copy sb data in here */
986 for (j
= 0; j
< data_size
; j
++)
987 *(sb_data_p
+ j
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
988 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp
->fw_sb_id
) +
991 if (!CHIP_IS_E1x(bp
)) {
992 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
993 sb_data_e2
.common
.p_func
.pf_id
,
994 sb_data_e2
.common
.p_func
.vf_id
,
995 sb_data_e2
.common
.p_func
.vf_valid
,
996 sb_data_e2
.common
.p_func
.vnic_id
,
997 sb_data_e2
.common
.same_igu_sb_1b
,
998 sb_data_e2
.common
.state
);
1000 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1001 sb_data_e1x
.common
.p_func
.pf_id
,
1002 sb_data_e1x
.common
.p_func
.vf_id
,
1003 sb_data_e1x
.common
.p_func
.vf_valid
,
1004 sb_data_e1x
.common
.p_func
.vnic_id
,
1005 sb_data_e1x
.common
.same_igu_sb_1b
,
1006 sb_data_e1x
.common
.state
);
1010 for (j
= 0; j
< HC_SB_MAX_SM
; j
++) {
1011 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1012 j
, hc_sm_p
[j
].__flags
,
1013 hc_sm_p
[j
].igu_sb_id
,
1014 hc_sm_p
[j
].igu_seg_id
,
1015 hc_sm_p
[j
].time_to_expire
,
1016 hc_sm_p
[j
].timer_value
);
1020 for (j
= 0; j
< loop
; j
++) {
1021 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j
,
1022 hc_index_p
[j
].flags
,
1023 hc_index_p
[j
].timeout
);
1027 #ifdef BNX2X_STOP_ON_ERROR
1030 for (i
= 0; i
< NUM_EQ_DESC
; i
++) {
1031 u32
*data
= (u32
*)&bp
->eq_ring
[i
].message
.data
;
1033 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1034 i
, bp
->eq_ring
[i
].message
.opcode
,
1035 bp
->eq_ring
[i
].message
.error
);
1036 BNX2X_ERR("data: %x %x %x\n", data
[0], data
[1], data
[2]);
1041 for_each_valid_rx_queue(bp
, i
) {
1042 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1044 start
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) - 10);
1045 end
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) + 503);
1046 for (j
= start
; j
!= end
; j
= RX_BD(j
+ 1)) {
1047 u32
*rx_bd
= (u32
*)&fp
->rx_desc_ring
[j
];
1048 struct sw_rx_bd
*sw_bd
= &fp
->rx_buf_ring
[j
];
1050 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1051 i
, j
, rx_bd
[1], rx_bd
[0], sw_bd
->data
);
1054 start
= RX_SGE(fp
->rx_sge_prod
);
1055 end
= RX_SGE(fp
->last_max_sge
);
1056 for (j
= start
; j
!= end
; j
= RX_SGE(j
+ 1)) {
1057 u32
*rx_sge
= (u32
*)&fp
->rx_sge_ring
[j
];
1058 struct sw_rx_page
*sw_page
= &fp
->rx_page_ring
[j
];
1060 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1061 i
, j
, rx_sge
[1], rx_sge
[0], sw_page
->page
);
1064 start
= RCQ_BD(fp
->rx_comp_cons
- 10);
1065 end
= RCQ_BD(fp
->rx_comp_cons
+ 503);
1066 for (j
= start
; j
!= end
; j
= RCQ_BD(j
+ 1)) {
1067 u32
*cqe
= (u32
*)&fp
->rx_comp_ring
[j
];
1069 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070 i
, j
, cqe
[0], cqe
[1], cqe
[2], cqe
[3]);
1075 for_each_valid_tx_queue(bp
, i
) {
1076 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1077 for_each_cos_in_tx_queue(fp
, cos
) {
1078 struct bnx2x_fp_txdata
*txdata
= fp
->txdata_ptr
[cos
];
1080 start
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) - 10);
1081 end
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) + 245);
1082 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1083 struct sw_tx_bd
*sw_bd
=
1084 &txdata
->tx_buf_ring
[j
];
1086 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1087 i
, cos
, j
, sw_bd
->skb
,
1091 start
= TX_BD(txdata
->tx_bd_cons
- 10);
1092 end
= TX_BD(txdata
->tx_bd_cons
+ 254);
1093 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1094 u32
*tx_bd
= (u32
*)&txdata
->tx_desc_ring
[j
];
1096 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1097 i
, cos
, j
, tx_bd
[0], tx_bd
[1],
1098 tx_bd
[2], tx_bd
[3]);
1104 bnx2x_mc_assert(bp
);
1105 BNX2X_ERR("end crash dump -----------------\n");
1109 * FLR Support for E2
1111 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1114 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1115 #define FLR_WAIT_INTERVAL 50 /* usec */
1116 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1118 struct pbf_pN_buf_regs
{
1125 struct pbf_pN_cmd_regs
{
1131 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x
*bp
,
1132 struct pbf_pN_buf_regs
*regs
,
1135 u32 init_crd
, crd
, crd_start
, crd_freed
, crd_freed_start
;
1136 u32 cur_cnt
= poll_count
;
1138 crd_freed
= crd_freed_start
= REG_RD(bp
, regs
->crd_freed
);
1139 crd
= crd_start
= REG_RD(bp
, regs
->crd
);
1140 init_crd
= REG_RD(bp
, regs
->init_crd
);
1142 DP(BNX2X_MSG_SP
, "INIT CREDIT[%d] : %x\n", regs
->pN
, init_crd
);
1143 DP(BNX2X_MSG_SP
, "CREDIT[%d] : s:%x\n", regs
->pN
, crd
);
1144 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: s:%x\n", regs
->pN
, crd_freed
);
1146 while ((crd
!= init_crd
) && ((u32
)SUB_S32(crd_freed
, crd_freed_start
) <
1147 (init_crd
- crd_start
))) {
1149 udelay(FLR_WAIT_INTERVAL
);
1150 crd
= REG_RD(bp
, regs
->crd
);
1151 crd_freed
= REG_RD(bp
, regs
->crd_freed
);
1153 DP(BNX2X_MSG_SP
, "PBF tx buffer[%d] timed out\n",
1155 DP(BNX2X_MSG_SP
, "CREDIT[%d] : c:%x\n",
1157 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: c:%x\n",
1158 regs
->pN
, crd_freed
);
1162 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1163 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1166 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x
*bp
,
1167 struct pbf_pN_cmd_regs
*regs
,
1170 u32 occup
, to_free
, freed
, freed_start
;
1171 u32 cur_cnt
= poll_count
;
1173 occup
= to_free
= REG_RD(bp
, regs
->lines_occup
);
1174 freed
= freed_start
= REG_RD(bp
, regs
->lines_freed
);
1176 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n", regs
->pN
, occup
);
1177 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n", regs
->pN
, freed
);
1179 while (occup
&& ((u32
)SUB_S32(freed
, freed_start
) < to_free
)) {
1181 udelay(FLR_WAIT_INTERVAL
);
1182 occup
= REG_RD(bp
, regs
->lines_occup
);
1183 freed
= REG_RD(bp
, regs
->lines_freed
);
1185 DP(BNX2X_MSG_SP
, "PBF cmd queue[%d] timed out\n",
1187 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n",
1189 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n",
1194 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1195 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1198 static u32
bnx2x_flr_clnup_reg_poll(struct bnx2x
*bp
, u32 reg
,
1199 u32 expected
, u32 poll_count
)
1201 u32 cur_cnt
= poll_count
;
1204 while ((val
= REG_RD(bp
, reg
)) != expected
&& cur_cnt
--)
1205 udelay(FLR_WAIT_INTERVAL
);
1210 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x
*bp
, u32 reg
,
1211 char *msg
, u32 poll_cnt
)
1213 u32 val
= bnx2x_flr_clnup_reg_poll(bp
, reg
, 0, poll_cnt
);
1215 BNX2X_ERR("%s usage count=%d\n", msg
, val
);
1221 /* Common routines with VF FLR cleanup */
1222 u32
bnx2x_flr_clnup_poll_count(struct bnx2x
*bp
)
1224 /* adjust polling timeout */
1225 if (CHIP_REV_IS_EMUL(bp
))
1226 return FLR_POLL_CNT
* 2000;
1228 if (CHIP_REV_IS_FPGA(bp
))
1229 return FLR_POLL_CNT
* 120;
1231 return FLR_POLL_CNT
;
1234 void bnx2x_tx_hw_flushed(struct bnx2x
*bp
, u32 poll_count
)
1236 struct pbf_pN_cmd_regs cmd_regs
[] = {
1237 {0, (CHIP_IS_E3B0(bp
)) ?
1238 PBF_REG_TQ_OCCUPANCY_Q0
:
1239 PBF_REG_P0_TQ_OCCUPANCY
,
1240 (CHIP_IS_E3B0(bp
)) ?
1241 PBF_REG_TQ_LINES_FREED_CNT_Q0
:
1242 PBF_REG_P0_TQ_LINES_FREED_CNT
},
1243 {1, (CHIP_IS_E3B0(bp
)) ?
1244 PBF_REG_TQ_OCCUPANCY_Q1
:
1245 PBF_REG_P1_TQ_OCCUPANCY
,
1246 (CHIP_IS_E3B0(bp
)) ?
1247 PBF_REG_TQ_LINES_FREED_CNT_Q1
:
1248 PBF_REG_P1_TQ_LINES_FREED_CNT
},
1249 {4, (CHIP_IS_E3B0(bp
)) ?
1250 PBF_REG_TQ_OCCUPANCY_LB_Q
:
1251 PBF_REG_P4_TQ_OCCUPANCY
,
1252 (CHIP_IS_E3B0(bp
)) ?
1253 PBF_REG_TQ_LINES_FREED_CNT_LB_Q
:
1254 PBF_REG_P4_TQ_LINES_FREED_CNT
}
1257 struct pbf_pN_buf_regs buf_regs
[] = {
1258 {0, (CHIP_IS_E3B0(bp
)) ?
1259 PBF_REG_INIT_CRD_Q0
:
1260 PBF_REG_P0_INIT_CRD
,
1261 (CHIP_IS_E3B0(bp
)) ?
1264 (CHIP_IS_E3B0(bp
)) ?
1265 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
:
1266 PBF_REG_P0_INTERNAL_CRD_FREED_CNT
},
1267 {1, (CHIP_IS_E3B0(bp
)) ?
1268 PBF_REG_INIT_CRD_Q1
:
1269 PBF_REG_P1_INIT_CRD
,
1270 (CHIP_IS_E3B0(bp
)) ?
1273 (CHIP_IS_E3B0(bp
)) ?
1274 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
:
1275 PBF_REG_P1_INTERNAL_CRD_FREED_CNT
},
1276 {4, (CHIP_IS_E3B0(bp
)) ?
1277 PBF_REG_INIT_CRD_LB_Q
:
1278 PBF_REG_P4_INIT_CRD
,
1279 (CHIP_IS_E3B0(bp
)) ?
1280 PBF_REG_CREDIT_LB_Q
:
1282 (CHIP_IS_E3B0(bp
)) ?
1283 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
:
1284 PBF_REG_P4_INTERNAL_CRD_FREED_CNT
},
1289 /* Verify the command queues are flushed P0, P1, P4 */
1290 for (i
= 0; i
< ARRAY_SIZE(cmd_regs
); i
++)
1291 bnx2x_pbf_pN_cmd_flushed(bp
, &cmd_regs
[i
], poll_count
);
1294 /* Verify the transmission buffers are flushed P0, P1, P4 */
1295 for (i
= 0; i
< ARRAY_SIZE(buf_regs
); i
++)
1296 bnx2x_pbf_pN_buf_flushed(bp
, &buf_regs
[i
], poll_count
);
1299 #define OP_GEN_PARAM(param) \
1300 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1302 #define OP_GEN_TYPE(type) \
1303 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1305 #define OP_GEN_AGG_VECT(index) \
1306 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1309 int bnx2x_send_final_clnup(struct bnx2x
*bp
, u8 clnup_func
, u32 poll_cnt
)
1311 u32 op_gen_command
= 0;
1313 u32 comp_addr
= BAR_CSTRORM_INTMEM
+
1314 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func
);
1317 if (REG_RD(bp
, comp_addr
)) {
1318 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1322 op_gen_command
|= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
);
1323 op_gen_command
|= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
);
1324 op_gen_command
|= OP_GEN_AGG_VECT(clnup_func
);
1325 op_gen_command
|= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT
;
1327 DP(BNX2X_MSG_SP
, "sending FW Final cleanup\n");
1328 REG_WR(bp
, XSDM_REG_OPERATION_GEN
, op_gen_command
);
1330 if (bnx2x_flr_clnup_reg_poll(bp
, comp_addr
, 1, poll_cnt
) != 1) {
1331 BNX2X_ERR("FW final cleanup did not succeed\n");
1332 DP(BNX2X_MSG_SP
, "At timeout completion address contained %x\n",
1333 (REG_RD(bp
, comp_addr
)));
1337 /* Zero completion for nxt FLR */
1338 REG_WR(bp
, comp_addr
, 0);
1343 u8
bnx2x_is_pcie_pending(struct pci_dev
*dev
)
1347 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &status
);
1348 return status
& PCI_EXP_DEVSTA_TRPND
;
1351 /* PF FLR specific routines
1353 static int bnx2x_poll_hw_usage_counters(struct bnx2x
*bp
, u32 poll_cnt
)
1356 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1357 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1358 CFC_REG_NUM_LCIDS_INSIDE_PF
,
1359 "CFC PF usage counter timed out",
1364 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1365 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1366 DORQ_REG_PF_USAGE_CNT
,
1367 "DQ PF usage counter timed out",
1371 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1372 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1373 QM_REG_PF_USG_CNT_0
+ 4*BP_FUNC(bp
),
1374 "QM PF usage counter timed out",
1378 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1379 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1380 TM_REG_LIN0_VNIC_UC
+ 4*BP_PORT(bp
),
1381 "Timers VNIC usage counter timed out",
1384 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1385 TM_REG_LIN0_NUM_SCANS
+ 4*BP_PORT(bp
),
1386 "Timers NUM_SCANS usage counter timed out",
1390 /* Wait DMAE PF usage counter to zero */
1391 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1392 dmae_reg_go_c
[INIT_DMAE_C(bp
)],
1393 "DMAE dommand register timed out",
1400 static void bnx2x_hw_enable_status(struct bnx2x
*bp
)
1404 val
= REG_RD(bp
, CFC_REG_WEAK_ENABLE_PF
);
1405 DP(BNX2X_MSG_SP
, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val
);
1407 val
= REG_RD(bp
, PBF_REG_DISABLE_PF
);
1408 DP(BNX2X_MSG_SP
, "PBF_REG_DISABLE_PF is 0x%x\n", val
);
1410 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSI_EN
);
1411 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val
);
1413 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_EN
);
1414 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val
);
1416 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_FUNC_MASK
);
1417 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val
);
1419 val
= REG_RD(bp
, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
);
1420 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val
);
1422 val
= REG_RD(bp
, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
);
1423 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val
);
1425 val
= REG_RD(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
1426 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1430 static int bnx2x_pf_flr_clnup(struct bnx2x
*bp
)
1432 u32 poll_cnt
= bnx2x_flr_clnup_poll_count(bp
);
1434 DP(BNX2X_MSG_SP
, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp
));
1436 /* Re-enable PF target read access */
1437 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1439 /* Poll HW usage counters */
1440 DP(BNX2X_MSG_SP
, "Polling usage counters\n");
1441 if (bnx2x_poll_hw_usage_counters(bp
, poll_cnt
))
1444 /* Zero the igu 'trailing edge' and 'leading edge' */
1446 /* Send the FW cleanup command */
1447 if (bnx2x_send_final_clnup(bp
, (u8
)BP_FUNC(bp
), poll_cnt
))
1452 /* Verify TX hw is flushed */
1453 bnx2x_tx_hw_flushed(bp
, poll_cnt
);
1455 /* Wait 100ms (not adjusted according to platform) */
1458 /* Verify no pending pci transactions */
1459 if (bnx2x_is_pcie_pending(bp
->pdev
))
1460 BNX2X_ERR("PCIE Transactions still pending\n");
1463 bnx2x_hw_enable_status(bp
);
1466 * Master enable - Due to WB DMAE writes performed before this
1467 * register is re-initialized as part of the regular function init
1469 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
1474 static void bnx2x_hc_int_enable(struct bnx2x
*bp
)
1476 int port
= BP_PORT(bp
);
1477 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1478 u32 val
= REG_RD(bp
, addr
);
1479 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1480 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1481 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1484 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1485 HC_CONFIG_0_REG_INT_LINE_EN_0
);
1486 val
|= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1487 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1489 val
|= HC_CONFIG_0_REG_SINGLE_ISR_EN_0
;
1491 val
&= ~HC_CONFIG_0_REG_INT_LINE_EN_0
;
1492 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1493 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1494 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1496 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1497 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1498 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1499 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1501 if (!CHIP_IS_E1(bp
)) {
1503 "write %x to HC %d (addr 0x%x)\n", val
, port
, addr
);
1505 REG_WR(bp
, addr
, val
);
1507 val
&= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
;
1512 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0x1FFFF);
1515 "write %x to HC %d (addr 0x%x) mode %s\n", val
, port
, addr
,
1516 (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1518 REG_WR(bp
, addr
, val
);
1520 * Ensure that HC_CONFIG is written before leading/trailing edge config
1525 if (!CHIP_IS_E1(bp
)) {
1526 /* init leading/trailing edge */
1528 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1530 /* enable nig and gpio3 attention */
1535 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
1536 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
1539 /* Make sure that interrupts are indeed enabled from here on */
1543 static void bnx2x_igu_int_enable(struct bnx2x
*bp
)
1546 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1547 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1548 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1550 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1553 val
&= ~(IGU_PF_CONF_INT_LINE_EN
|
1554 IGU_PF_CONF_SINGLE_ISR_EN
);
1555 val
|= (IGU_PF_CONF_MSI_MSIX_EN
|
1556 IGU_PF_CONF_ATTN_BIT_EN
);
1559 val
|= IGU_PF_CONF_SINGLE_ISR_EN
;
1561 val
&= ~IGU_PF_CONF_INT_LINE_EN
;
1562 val
|= (IGU_PF_CONF_MSI_MSIX_EN
|
1563 IGU_PF_CONF_ATTN_BIT_EN
|
1564 IGU_PF_CONF_SINGLE_ISR_EN
);
1566 val
&= ~IGU_PF_CONF_MSI_MSIX_EN
;
1567 val
|= (IGU_PF_CONF_INT_LINE_EN
|
1568 IGU_PF_CONF_ATTN_BIT_EN
|
1569 IGU_PF_CONF_SINGLE_ISR_EN
);
1572 /* Clean previous status - need to configure igu prior to ack*/
1573 if ((!msix
) || single_msix
) {
1574 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1578 val
|= IGU_PF_CONF_FUNC_EN
;
1580 DP(NETIF_MSG_IFUP
, "write 0x%x to IGU mode %s\n",
1581 val
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1583 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1585 if (val
& IGU_PF_CONF_INT_LINE_EN
)
1586 pci_intx(bp
->pdev
, true);
1590 /* init leading/trailing edge */
1592 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1594 /* enable nig and gpio3 attention */
1599 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
1600 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
1602 /* Make sure that interrupts are indeed enabled from here on */
1606 void bnx2x_int_enable(struct bnx2x
*bp
)
1608 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1609 bnx2x_hc_int_enable(bp
);
1611 bnx2x_igu_int_enable(bp
);
1614 void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
)
1616 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1620 /* prevent the HW from sending interrupts */
1621 bnx2x_int_disable(bp
);
1623 /* make sure all ISRs are done */
1625 synchronize_irq(bp
->msix_table
[0].vector
);
1627 if (CNIC_SUPPORT(bp
))
1629 for_each_eth_queue(bp
, i
)
1630 synchronize_irq(bp
->msix_table
[offset
++].vector
);
1632 synchronize_irq(bp
->pdev
->irq
);
1634 /* make sure sp_task is not running */
1635 cancel_delayed_work(&bp
->sp_task
);
1636 cancel_delayed_work(&bp
->period_task
);
1637 flush_workqueue(bnx2x_wq
);
1643 * General service functions
1646 /* Return true if succeeded to acquire the lock */
1647 static bool bnx2x_trylock_hw_lock(struct bnx2x
*bp
, u32 resource
)
1650 u32 resource_bit
= (1 << resource
);
1651 int func
= BP_FUNC(bp
);
1652 u32 hw_lock_control_reg
;
1654 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1655 "Trying to take a lock on resource %d\n", resource
);
1657 /* Validating that the resource is within range */
1658 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1659 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1660 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1661 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1666 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1668 hw_lock_control_reg
=
1669 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1671 /* Try to acquire the lock */
1672 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1673 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1674 if (lock_status
& resource_bit
)
1677 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1678 "Failed to get a lock on resource %d\n", resource
);
1683 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1685 * @bp: driver handle
1687 * Returns the recovery leader resource id according to the engine this function
1688 * belongs to. Currently only only 2 engines is supported.
1690 static int bnx2x_get_leader_lock_resource(struct bnx2x
*bp
)
1693 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1
;
1695 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0
;
1699 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1701 * @bp: driver handle
1703 * Tries to acquire a leader lock for current engine.
1705 static bool bnx2x_trylock_leader_lock(struct bnx2x
*bp
)
1707 return bnx2x_trylock_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1710 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
);
1712 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1713 static int bnx2x_schedule_sp_task(struct bnx2x
*bp
)
1715 /* Set the interrupt occurred bit for the sp-task to recognize it
1716 * must ack the interrupt and transition according to the IGU
1719 atomic_set(&bp
->interrupt_occurred
, 1);
1721 /* The sp_task must execute only after this bit
1722 * is set, otherwise we will get out of sync and miss all
1723 * further interrupts. Hence, the barrier.
1727 /* schedule sp_task to workqueue */
1728 return queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
1731 void bnx2x_sp_event(struct bnx2x_fastpath
*fp
, union eth_rx_cqe
*rr_cqe
)
1733 struct bnx2x
*bp
= fp
->bp
;
1734 int cid
= SW_CID(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1735 int command
= CQE_CMD(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1736 enum bnx2x_queue_cmd drv_cmd
= BNX2X_Q_CMD_MAX
;
1737 struct bnx2x_queue_sp_obj
*q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
1740 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1741 fp
->index
, cid
, command
, bp
->state
,
1742 rr_cqe
->ramrod_cqe
.ramrod_type
);
1744 /* If cid is within VF range, replace the slowpath object with the
1745 * one corresponding to this VF
1747 if (cid
>= BNX2X_FIRST_VF_CID
&&
1748 cid
< BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)
1749 bnx2x_iov_set_queue_sp_obj(bp
, cid
, &q_obj
);
1752 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE
):
1753 DP(BNX2X_MSG_SP
, "got UPDATE ramrod. CID %d\n", cid
);
1754 drv_cmd
= BNX2X_Q_CMD_UPDATE
;
1757 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP
):
1758 DP(BNX2X_MSG_SP
, "got MULTI[%d] setup ramrod\n", cid
);
1759 drv_cmd
= BNX2X_Q_CMD_SETUP
;
1762 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
):
1763 DP(BNX2X_MSG_SP
, "got MULTI[%d] tx-only setup ramrod\n", cid
);
1764 drv_cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
1767 case (RAMROD_CMD_ID_ETH_HALT
):
1768 DP(BNX2X_MSG_SP
, "got MULTI[%d] halt ramrod\n", cid
);
1769 drv_cmd
= BNX2X_Q_CMD_HALT
;
1772 case (RAMROD_CMD_ID_ETH_TERMINATE
):
1773 DP(BNX2X_MSG_SP
, "got MULTI[%d] teminate ramrod\n", cid
);
1774 drv_cmd
= BNX2X_Q_CMD_TERMINATE
;
1777 case (RAMROD_CMD_ID_ETH_EMPTY
):
1778 DP(BNX2X_MSG_SP
, "got MULTI[%d] empty ramrod\n", cid
);
1779 drv_cmd
= BNX2X_Q_CMD_EMPTY
;
1783 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1784 command
, fp
->index
);
1788 if ((drv_cmd
!= BNX2X_Q_CMD_MAX
) &&
1789 q_obj
->complete_cmd(bp
, q_obj
, drv_cmd
))
1790 /* q_obj->complete_cmd() failure means that this was
1791 * an unexpected completion.
1793 * In this case we don't want to increase the bp->spq_left
1794 * because apparently we haven't sent this command the first
1797 #ifdef BNX2X_STOP_ON_ERROR
1802 /* SRIOV: reschedule any 'in_progress' operations */
1803 bnx2x_iov_sp_event(bp
, cid
, true);
1805 smp_mb__before_atomic_inc();
1806 atomic_inc(&bp
->cq_spq_left
);
1807 /* push the change in bp->spq_left and towards the memory */
1808 smp_mb__after_atomic_inc();
1810 DP(BNX2X_MSG_SP
, "bp->cq_spq_left %x\n", atomic_read(&bp
->cq_spq_left
));
1812 if ((drv_cmd
== BNX2X_Q_CMD_UPDATE
) && (IS_FCOE_FP(fp
)) &&
1813 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
))) {
1814 /* if Q update ramrod is completed for last Q in AFEX vif set
1815 * flow, then ACK MCP at the end
1817 * mark pending ACK to MCP bit.
1818 * prevent case that both bits are cleared.
1819 * At the end of load/unload driver checks that
1820 * sp_state is cleared, and this order prevents
1823 smp_mb__before_clear_bit();
1824 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
, &bp
->sp_state
);
1826 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
1827 smp_mb__after_clear_bit();
1829 /* schedule the sp task as mcp ack is required */
1830 bnx2x_schedule_sp_task(bp
);
1836 irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
)
1838 struct bnx2x
*bp
= netdev_priv(dev_instance
);
1839 u16 status
= bnx2x_ack_int(bp
);
1844 /* Return here if interrupt is shared and it's not for us */
1845 if (unlikely(status
== 0)) {
1846 DP(NETIF_MSG_INTR
, "not our interrupt!\n");
1849 DP(NETIF_MSG_INTR
, "got an interrupt status 0x%x\n", status
);
1851 #ifdef BNX2X_STOP_ON_ERROR
1852 if (unlikely(bp
->panic
))
1856 for_each_eth_queue(bp
, i
) {
1857 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1859 mask
= 0x2 << (fp
->index
+ CNIC_SUPPORT(bp
));
1860 if (status
& mask
) {
1861 /* Handle Rx or Tx according to SB id */
1862 prefetch(fp
->rx_cons_sb
);
1863 for_each_cos_in_tx_queue(fp
, cos
)
1864 prefetch(fp
->txdata_ptr
[cos
]->tx_cons_sb
);
1865 prefetch(&fp
->sb_running_index
[SM_RX_ID
]);
1866 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
1871 if (CNIC_SUPPORT(bp
)) {
1873 if (status
& (mask
| 0x1)) {
1874 struct cnic_ops
*c_ops
= NULL
;
1877 c_ops
= rcu_dereference(bp
->cnic_ops
);
1878 if (c_ops
&& (bp
->cnic_eth_dev
.drv_state
&
1879 CNIC_DRV_STATE_HANDLES_IRQ
))
1880 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
1887 if (unlikely(status
& 0x1)) {
1889 /* schedule sp task to perform default status block work, ack
1890 * attentions and enable interrupts.
1892 bnx2x_schedule_sp_task(bp
);
1899 if (unlikely(status
))
1900 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
1909 * General service functions
1912 int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
)
1915 u32 resource_bit
= (1 << resource
);
1916 int func
= BP_FUNC(bp
);
1917 u32 hw_lock_control_reg
;
1920 /* Validating that the resource is within range */
1921 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1922 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1923 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1928 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1930 hw_lock_control_reg
=
1931 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1934 /* Validating that the resource is not already taken */
1935 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1936 if (lock_status
& resource_bit
) {
1937 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1938 lock_status
, resource_bit
);
1942 /* Try for 5 second every 5ms */
1943 for (cnt
= 0; cnt
< 1000; cnt
++) {
1944 /* Try to acquire the lock */
1945 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1946 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1947 if (lock_status
& resource_bit
)
1952 BNX2X_ERR("Timeout\n");
1956 int bnx2x_release_leader_lock(struct bnx2x
*bp
)
1958 return bnx2x_release_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1961 int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
)
1964 u32 resource_bit
= (1 << resource
);
1965 int func
= BP_FUNC(bp
);
1966 u32 hw_lock_control_reg
;
1968 /* Validating that the resource is within range */
1969 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1970 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1971 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1976 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1978 hw_lock_control_reg
=
1979 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1982 /* Validating that the resource is currently taken */
1983 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1984 if (!(lock_status
& resource_bit
)) {
1985 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1986 lock_status
, resource_bit
);
1990 REG_WR(bp
, hw_lock_control_reg
, resource_bit
);
1995 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
)
1997 /* The GPIO should be swapped if swap register is set and active */
1998 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
1999 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2000 int gpio_shift
= gpio_num
+
2001 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2002 u32 gpio_mask
= (1 << gpio_shift
);
2006 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2007 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2011 /* read GPIO value */
2012 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2014 /* get the requested pin value */
2015 if ((gpio_reg
& gpio_mask
) == gpio_mask
)
2020 DP(NETIF_MSG_LINK
, "pin %d value 0x%x\n", gpio_num
, value
);
2025 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2027 /* The GPIO should be swapped if swap register is set and active */
2028 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2029 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2030 int gpio_shift
= gpio_num
+
2031 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2032 u32 gpio_mask
= (1 << gpio_shift
);
2035 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2036 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2040 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2041 /* read GPIO and mask except the float bits */
2042 gpio_reg
= (REG_RD(bp
, MISC_REG_GPIO
) & MISC_REGISTERS_GPIO_FLOAT
);
2045 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2047 "Set GPIO %d (shift %d) -> output low\n",
2048 gpio_num
, gpio_shift
);
2049 /* clear FLOAT and set CLR */
2050 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2051 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_CLR_POS
);
2054 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2056 "Set GPIO %d (shift %d) -> output high\n",
2057 gpio_num
, gpio_shift
);
2058 /* clear FLOAT and set SET */
2059 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2060 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_SET_POS
);
2063 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2065 "Set GPIO %d (shift %d) -> input\n",
2066 gpio_num
, gpio_shift
);
2068 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2075 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2076 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2081 int bnx2x_set_mult_gpio(struct bnx2x
*bp
, u8 pins
, u32 mode
)
2086 /* Any port swapping should be handled by caller. */
2088 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2089 /* read GPIO and mask except the float bits */
2090 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2091 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2092 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2093 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2096 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2097 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output low\n", pins
);
2099 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2102 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2103 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output high\n", pins
);
2105 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2108 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2109 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> input\n", pins
);
2111 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2115 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode
);
2121 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2123 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2128 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2130 /* The GPIO should be swapped if swap register is set and active */
2131 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2132 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2133 int gpio_shift
= gpio_num
+
2134 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2135 u32 gpio_mask
= (1 << gpio_shift
);
2138 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2139 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2143 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2145 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO_INT
);
2148 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
:
2150 "Clear GPIO INT %d (shift %d) -> output low\n",
2151 gpio_num
, gpio_shift
);
2152 /* clear SET and set CLR */
2153 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2154 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2157 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET
:
2159 "Set GPIO INT %d (shift %d) -> output high\n",
2160 gpio_num
, gpio_shift
);
2161 /* clear CLR and set SET */
2162 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2163 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2170 REG_WR(bp
, MISC_REG_GPIO_INT
, gpio_reg
);
2171 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2176 static int bnx2x_set_spio(struct bnx2x
*bp
, int spio
, u32 mode
)
2180 /* Only 2 SPIOs are configurable */
2181 if ((spio
!= MISC_SPIO_SPIO4
) && (spio
!= MISC_SPIO_SPIO5
)) {
2182 BNX2X_ERR("Invalid SPIO 0x%x\n", spio
);
2186 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2187 /* read SPIO and mask except the float bits */
2188 spio_reg
= (REG_RD(bp
, MISC_REG_SPIO
) & MISC_SPIO_FLOAT
);
2191 case MISC_SPIO_OUTPUT_LOW
:
2192 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output low\n", spio
);
2193 /* clear FLOAT and set CLR */
2194 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2195 spio_reg
|= (spio
<< MISC_SPIO_CLR_POS
);
2198 case MISC_SPIO_OUTPUT_HIGH
:
2199 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output high\n", spio
);
2200 /* clear FLOAT and set SET */
2201 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2202 spio_reg
|= (spio
<< MISC_SPIO_SET_POS
);
2205 case MISC_SPIO_INPUT_HI_Z
:
2206 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> input\n", spio
);
2208 spio_reg
|= (spio
<< MISC_SPIO_FLOAT_POS
);
2215 REG_WR(bp
, MISC_REG_SPIO
, spio_reg
);
2216 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2221 void bnx2x_calc_fc_adv(struct bnx2x
*bp
)
2223 u8 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
2224 switch (bp
->link_vars
.ieee_fc
&
2225 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) {
2226 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
:
2227 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2231 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
:
2232 bp
->port
.advertising
[cfg_idx
] |= (ADVERTISED_Asym_Pause
|
2236 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
:
2237 bp
->port
.advertising
[cfg_idx
] |= ADVERTISED_Asym_Pause
;
2241 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2247 static void bnx2x_set_requested_fc(struct bnx2x
*bp
)
2249 /* Initialize link parameters structure variables
2250 * It is recommended to turn off RX FC for jumbo frames
2251 * for better performance
2253 if (CHIP_IS_E1x(bp
) && (bp
->dev
->mtu
> 5000))
2254 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_TX
;
2256 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
2259 int bnx2x_initial_phy_init(struct bnx2x
*bp
, int load_mode
)
2261 int rc
, cfx_idx
= bnx2x_get_link_cfg_idx(bp
);
2262 u16 req_line_speed
= bp
->link_params
.req_line_speed
[cfx_idx
];
2264 if (!BP_NOMCP(bp
)) {
2265 bnx2x_set_requested_fc(bp
);
2266 bnx2x_acquire_phy_lock(bp
);
2268 if (load_mode
== LOAD_DIAG
) {
2269 struct link_params
*lp
= &bp
->link_params
;
2270 lp
->loopback_mode
= LOOPBACK_XGXS
;
2271 /* do PHY loopback at 10G speed, if possible */
2272 if (lp
->req_line_speed
[cfx_idx
] < SPEED_10000
) {
2273 if (lp
->speed_cap_mask
[cfx_idx
] &
2274 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
2275 lp
->req_line_speed
[cfx_idx
] =
2278 lp
->req_line_speed
[cfx_idx
] =
2283 if (load_mode
== LOAD_LOOPBACK_EXT
) {
2284 struct link_params
*lp
= &bp
->link_params
;
2285 lp
->loopback_mode
= LOOPBACK_EXT
;
2288 rc
= bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2290 bnx2x_release_phy_lock(bp
);
2292 bnx2x_calc_fc_adv(bp
);
2294 if (bp
->link_vars
.link_up
) {
2295 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2296 bnx2x_link_report(bp
);
2298 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2299 bp
->link_params
.req_line_speed
[cfx_idx
] = req_line_speed
;
2302 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2306 void bnx2x_link_set(struct bnx2x
*bp
)
2308 if (!BP_NOMCP(bp
)) {
2309 bnx2x_acquire_phy_lock(bp
);
2310 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2311 bnx2x_release_phy_lock(bp
);
2313 bnx2x_calc_fc_adv(bp
);
2315 BNX2X_ERR("Bootcode is missing - can not set link\n");
2318 static void bnx2x__link_reset(struct bnx2x
*bp
)
2320 if (!BP_NOMCP(bp
)) {
2321 bnx2x_acquire_phy_lock(bp
);
2322 bnx2x_lfa_reset(&bp
->link_params
, &bp
->link_vars
);
2323 bnx2x_release_phy_lock(bp
);
2325 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2328 void bnx2x_force_link_reset(struct bnx2x
*bp
)
2330 bnx2x_acquire_phy_lock(bp
);
2331 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2332 bnx2x_release_phy_lock(bp
);
2335 u8
bnx2x_link_test(struct bnx2x
*bp
, u8 is_serdes
)
2339 if (!BP_NOMCP(bp
)) {
2340 bnx2x_acquire_phy_lock(bp
);
2341 rc
= bnx2x_test_link(&bp
->link_params
, &bp
->link_vars
,
2343 bnx2x_release_phy_lock(bp
);
2345 BNX2X_ERR("Bootcode is missing - can not test link\n");
2351 /* Calculates the sum of vn_min_rates.
2352 It's needed for further normalizing of the min_rates.
2354 sum of vn_min_rates.
2356 0 - if all the min_rates are 0.
2357 In the later case fainess algorithm should be deactivated.
2358 If not all min_rates are zero then those that are zeroes will be set to 1.
2360 static void bnx2x_calc_vn_min(struct bnx2x
*bp
,
2361 struct cmng_init_input
*input
)
2366 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2367 u32 vn_cfg
= bp
->mf_config
[vn
];
2368 u32 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2369 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2371 /* Skip hidden vns */
2372 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2374 /* If min rate is zero - set it to 1 */
2375 else if (!vn_min_rate
)
2376 vn_min_rate
= DEF_MIN_RATE
;
2380 input
->vnic_min_rate
[vn
] = vn_min_rate
;
2383 /* if ETS or all min rates are zeros - disable fairness */
2384 if (BNX2X_IS_ETS_ENABLED(bp
)) {
2385 input
->flags
.cmng_enables
&=
2386 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2387 DP(NETIF_MSG_IFUP
, "Fairness will be disabled due to ETS\n");
2388 } else if (all_zero
) {
2389 input
->flags
.cmng_enables
&=
2390 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2392 "All MIN values are zeroes fairness will be disabled\n");
2394 input
->flags
.cmng_enables
|=
2395 CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2398 static void bnx2x_calc_vn_max(struct bnx2x
*bp
, int vn
,
2399 struct cmng_init_input
*input
)
2402 u32 vn_cfg
= bp
->mf_config
[vn
];
2404 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2407 u32 maxCfg
= bnx2x_extract_max_cfg(bp
, vn_cfg
);
2410 /* maxCfg in percents of linkspeed */
2411 vn_max_rate
= (bp
->link_vars
.line_speed
* maxCfg
) / 100;
2412 } else /* SD modes */
2413 /* maxCfg is absolute in 100Mb units */
2414 vn_max_rate
= maxCfg
* 100;
2417 DP(NETIF_MSG_IFUP
, "vn %d: vn_max_rate %d\n", vn
, vn_max_rate
);
2419 input
->vnic_max_rate
[vn
] = vn_max_rate
;
2423 static int bnx2x_get_cmng_fns_mode(struct bnx2x
*bp
)
2425 if (CHIP_REV_IS_SLOW(bp
))
2426 return CMNG_FNS_NONE
;
2428 return CMNG_FNS_MINMAX
;
2430 return CMNG_FNS_NONE
;
2433 void bnx2x_read_mf_cfg(struct bnx2x
*bp
)
2435 int vn
, n
= (CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1);
2438 return; /* what should be the default bvalue in this case */
2440 /* For 2 port configuration the absolute function number formula
2442 * abs_func = 2 * vn + BP_PORT + BP_PATH
2444 * and there are 4 functions per port
2446 * For 4 port configuration it is
2447 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2449 * and there are 2 functions per port
2451 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2452 int /*abs*/func
= n
* (2 * vn
+ BP_PORT(bp
)) + BP_PATH(bp
);
2454 if (func
>= E1H_FUNC_MAX
)
2458 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2460 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
2461 DP(NETIF_MSG_IFUP
, "mf_cfg function disabled\n");
2462 bp
->flags
|= MF_FUNC_DIS
;
2464 DP(NETIF_MSG_IFUP
, "mf_cfg function enabled\n");
2465 bp
->flags
&= ~MF_FUNC_DIS
;
2469 static void bnx2x_cmng_fns_init(struct bnx2x
*bp
, u8 read_cfg
, u8 cmng_type
)
2471 struct cmng_init_input input
;
2472 memset(&input
, 0, sizeof(struct cmng_init_input
));
2474 input
.port_rate
= bp
->link_vars
.line_speed
;
2476 if (cmng_type
== CMNG_FNS_MINMAX
) {
2479 /* read mf conf from shmem */
2481 bnx2x_read_mf_cfg(bp
);
2483 /* vn_weight_sum and enable fairness if not 0 */
2484 bnx2x_calc_vn_min(bp
, &input
);
2486 /* calculate and set min-max rate for each vn */
2488 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++)
2489 bnx2x_calc_vn_max(bp
, vn
, &input
);
2491 /* always enable rate shaping and fairness */
2492 input
.flags
.cmng_enables
|=
2493 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN
;
2495 bnx2x_init_cmng(&input
, &bp
->cmng
);
2499 /* rate shaping and fairness are disabled */
2501 "rate shaping and fairness are disabled\n");
2504 static void storm_memset_cmng(struct bnx2x
*bp
,
2505 struct cmng_init
*cmng
,
2509 size_t size
= sizeof(struct cmng_struct_per_port
);
2511 u32 addr
= BAR_XSTRORM_INTMEM
+
2512 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port
);
2514 __storm_memset_struct(bp
, addr
, size
, (u32
*)&cmng
->port
);
2516 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2517 int func
= func_by_vn(bp
, vn
);
2519 addr
= BAR_XSTRORM_INTMEM
+
2520 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func
);
2521 size
= sizeof(struct rate_shaping_vars_per_vn
);
2522 __storm_memset_struct(bp
, addr
, size
,
2523 (u32
*)&cmng
->vnic
.vnic_max_rate
[vn
]);
2525 addr
= BAR_XSTRORM_INTMEM
+
2526 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func
);
2527 size
= sizeof(struct fairness_vars_per_vn
);
2528 __storm_memset_struct(bp
, addr
, size
,
2529 (u32
*)&cmng
->vnic
.vnic_min_rate
[vn
]);
2533 /* This function is called upon link interrupt */
2534 static void bnx2x_link_attn(struct bnx2x
*bp
)
2536 /* Make sure that we are synced with the current statistics */
2537 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2539 bnx2x_link_update(&bp
->link_params
, &bp
->link_vars
);
2541 if (bp
->link_vars
.link_up
) {
2543 /* dropless flow control */
2544 if (!CHIP_IS_E1(bp
) && bp
->dropless_fc
) {
2545 int port
= BP_PORT(bp
);
2546 u32 pause_enabled
= 0;
2548 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
2551 REG_WR(bp
, BAR_USTRORM_INTMEM
+
2552 USTORM_ETH_PAUSE_ENABLED_OFFSET(port
),
2556 if (bp
->link_vars
.mac_type
!= MAC_TYPE_EMAC
) {
2557 struct host_port_stats
*pstats
;
2559 pstats
= bnx2x_sp(bp
, port_stats
);
2560 /* reset old mac stats */
2561 memset(&(pstats
->mac_stx
[0]), 0,
2562 sizeof(struct mac_stx
));
2564 if (bp
->state
== BNX2X_STATE_OPEN
)
2565 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2568 if (bp
->link_vars
.link_up
&& bp
->link_vars
.line_speed
) {
2569 int cmng_fns
= bnx2x_get_cmng_fns_mode(bp
);
2571 if (cmng_fns
!= CMNG_FNS_NONE
) {
2572 bnx2x_cmng_fns_init(bp
, false, cmng_fns
);
2573 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2575 /* rate shaping and fairness are disabled */
2577 "single function mode without fairness\n");
2580 __bnx2x_link_report(bp
);
2583 bnx2x_link_sync_notify(bp
);
2586 void bnx2x__link_status_update(struct bnx2x
*bp
)
2588 if (bp
->state
!= BNX2X_STATE_OPEN
)
2591 /* read updated dcb configuration */
2593 bnx2x_dcbx_pmf_update(bp
);
2594 bnx2x_link_status_update(&bp
->link_params
, &bp
->link_vars
);
2595 if (bp
->link_vars
.link_up
)
2596 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2598 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2599 /* indicate link status */
2600 bnx2x_link_report(bp
);
2603 bp
->port
.supported
[0] |= (SUPPORTED_10baseT_Half
|
2604 SUPPORTED_10baseT_Full
|
2605 SUPPORTED_100baseT_Half
|
2606 SUPPORTED_100baseT_Full
|
2607 SUPPORTED_1000baseT_Full
|
2608 SUPPORTED_2500baseX_Full
|
2609 SUPPORTED_10000baseT_Full
|
2614 SUPPORTED_Asym_Pause
);
2615 bp
->port
.advertising
[0] = bp
->port
.supported
[0];
2617 bp
->link_params
.bp
= bp
;
2618 bp
->link_params
.port
= BP_PORT(bp
);
2619 bp
->link_params
.req_duplex
[0] = DUPLEX_FULL
;
2620 bp
->link_params
.req_flow_ctrl
[0] = BNX2X_FLOW_CTRL_NONE
;
2621 bp
->link_params
.req_line_speed
[0] = SPEED_10000
;
2622 bp
->link_params
.speed_cap_mask
[0] = 0x7f0000;
2623 bp
->link_params
.switch_cfg
= SWITCH_CFG_10G
;
2624 bp
->link_vars
.mac_type
= MAC_TYPE_BMAC
;
2625 bp
->link_vars
.line_speed
= SPEED_10000
;
2626 bp
->link_vars
.link_status
=
2627 (LINK_STATUS_LINK_UP
|
2628 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
);
2629 bp
->link_vars
.link_up
= 1;
2630 bp
->link_vars
.duplex
= DUPLEX_FULL
;
2631 bp
->link_vars
.flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
2632 __bnx2x_link_report(bp
);
2633 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2637 static int bnx2x_afex_func_update(struct bnx2x
*bp
, u16 vifid
,
2638 u16 vlan_val
, u8 allowed_prio
)
2640 struct bnx2x_func_state_params func_params
= {NULL
};
2641 struct bnx2x_func_afex_update_params
*f_update_params
=
2642 &func_params
.params
.afex_update
;
2644 func_params
.f_obj
= &bp
->func_obj
;
2645 func_params
.cmd
= BNX2X_F_CMD_AFEX_UPDATE
;
2647 /* no need to wait for RAMROD completion, so don't
2648 * set RAMROD_COMP_WAIT flag
2651 f_update_params
->vif_id
= vifid
;
2652 f_update_params
->afex_default_vlan
= vlan_val
;
2653 f_update_params
->allowed_priorities
= allowed_prio
;
2655 /* if ramrod can not be sent, response to MCP immediately */
2656 if (bnx2x_func_state_change(bp
, &func_params
) < 0)
2657 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
2662 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x
*bp
, u8 cmd_type
,
2663 u16 vif_index
, u8 func_bit_map
)
2665 struct bnx2x_func_state_params func_params
= {NULL
};
2666 struct bnx2x_func_afex_viflists_params
*update_params
=
2667 &func_params
.params
.afex_viflists
;
2671 /* validate only LIST_SET and LIST_GET are received from switch */
2672 if ((cmd_type
!= VIF_LIST_RULE_GET
) && (cmd_type
!= VIF_LIST_RULE_SET
))
2673 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2676 func_params
.f_obj
= &bp
->func_obj
;
2677 func_params
.cmd
= BNX2X_F_CMD_AFEX_VIFLISTS
;
2679 /* set parameters according to cmd_type */
2680 update_params
->afex_vif_list_command
= cmd_type
;
2681 update_params
->vif_list_index
= vif_index
;
2682 update_params
->func_bit_map
=
2683 (cmd_type
== VIF_LIST_RULE_GET
) ? 0 : func_bit_map
;
2684 update_params
->func_to_clear
= 0;
2686 (cmd_type
== VIF_LIST_RULE_GET
) ?
2687 DRV_MSG_CODE_AFEX_LISTGET_ACK
:
2688 DRV_MSG_CODE_AFEX_LISTSET_ACK
;
2690 /* if ramrod can not be sent, respond to MCP immediately for
2691 * SET and GET requests (other are not triggered from MCP)
2693 rc
= bnx2x_func_state_change(bp
, &func_params
);
2695 bnx2x_fw_command(bp
, drv_msg_code
, 0);
2700 static void bnx2x_handle_afex_cmd(struct bnx2x
*bp
, u32 cmd
)
2702 struct afex_stats afex_stats
;
2703 u32 func
= BP_ABS_FUNC(bp
);
2710 u32 addr_to_write
, vifid
, addrs
, stats_type
, i
;
2712 if (cmd
& DRV_STATUS_AFEX_LISTGET_REQ
) {
2713 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2715 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid
);
2716 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_GET
, vifid
, 0);
2719 if (cmd
& DRV_STATUS_AFEX_LISTSET_REQ
) {
2720 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2721 addrs
= SHMEM2_RD(bp
, afex_param2_to_driver
[BP_FW_MB_IDX(bp
)]);
2723 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2725 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_SET
, vifid
,
2729 if (cmd
& DRV_STATUS_AFEX_STATSGET_REQ
) {
2730 addr_to_write
= SHMEM2_RD(bp
,
2731 afex_scratchpad_addr_to_write
[BP_FW_MB_IDX(bp
)]);
2732 stats_type
= SHMEM2_RD(bp
,
2733 afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2736 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2739 bnx2x_afex_collect_stats(bp
, (void *)&afex_stats
, stats_type
);
2741 /* write response to scratchpad, for MCP */
2742 for (i
= 0; i
< (sizeof(struct afex_stats
)/sizeof(u32
)); i
++)
2743 REG_WR(bp
, addr_to_write
+ i
*sizeof(u32
),
2744 *(((u32
*)(&afex_stats
))+i
));
2746 /* send ack message to MCP */
2747 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_STATSGET_ACK
, 0);
2750 if (cmd
& DRV_STATUS_AFEX_VIFSET_REQ
) {
2751 mf_config
= MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2752 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2754 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2757 /* if VIF_SET is "enabled" */
2758 if (!(mf_config
& FUNC_MF_CFG_FUNC_DISABLED
)) {
2759 /* set rate limit directly to internal RAM */
2760 struct cmng_init_input cmng_input
;
2761 struct rate_shaping_vars_per_vn m_rs_vn
;
2762 size_t size
= sizeof(struct rate_shaping_vars_per_vn
);
2763 u32 addr
= BAR_XSTRORM_INTMEM
+
2764 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp
));
2766 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2768 bnx2x_calc_vn_max(bp
, BP_VN(bp
), &cmng_input
);
2769 m_rs_vn
.vn_counter
.rate
=
2770 cmng_input
.vnic_max_rate
[BP_VN(bp
)];
2771 m_rs_vn
.vn_counter
.quota
=
2772 (m_rs_vn
.vn_counter
.rate
*
2773 RS_PERIODIC_TIMEOUT_USEC
) / 8;
2775 __storm_memset_struct(bp
, addr
, size
, (u32
*)&m_rs_vn
);
2777 /* read relevant values from mf_cfg struct in shmem */
2779 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2780 FUNC_MF_CFG_E1HOV_TAG_MASK
) >>
2781 FUNC_MF_CFG_E1HOV_TAG_SHIFT
;
2783 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2784 FUNC_MF_CFG_AFEX_VLAN_MASK
) >>
2785 FUNC_MF_CFG_AFEX_VLAN_SHIFT
;
2786 vlan_prio
= (mf_config
&
2787 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK
) >>
2788 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT
;
2789 vlan_val
|= (vlan_prio
<< VLAN_PRIO_SHIFT
);
2792 func_mf_config
[func
].afex_config
) &
2793 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK
) >>
2794 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT
;
2797 func_mf_config
[func
].afex_config
) &
2798 FUNC_MF_CFG_AFEX_COS_FILTER_MASK
) >>
2799 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT
;
2801 /* send ramrod to FW, return in case of failure */
2802 if (bnx2x_afex_func_update(bp
, vif_id
, vlan_val
,
2806 bp
->afex_def_vlan_tag
= vlan_val
;
2807 bp
->afex_vlan_mode
= vlan_mode
;
2809 /* notify link down because BP->flags is disabled */
2810 bnx2x_link_report(bp
);
2812 /* send INVALID VIF ramrod to FW */
2813 bnx2x_afex_func_update(bp
, 0xFFFF, 0, 0);
2815 /* Reset the default afex VLAN */
2816 bp
->afex_def_vlan_tag
= -1;
2821 static void bnx2x_pmf_update(struct bnx2x
*bp
)
2823 int port
= BP_PORT(bp
);
2827 DP(BNX2X_MSG_MCP
, "pmf %d\n", bp
->port
.pmf
);
2830 * We need the mb() to ensure the ordering between the writing to
2831 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2835 /* queue a periodic task */
2836 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2838 bnx2x_dcbx_pmf_update(bp
);
2840 /* enable nig attention */
2841 val
= (0xff0f | (1 << (BP_VN(bp
) + 4)));
2842 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
2843 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
2844 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
2845 } else if (!CHIP_IS_E1x(bp
)) {
2846 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
2847 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
2850 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
2858 * General service functions
2861 /* send the MCP a request, block until there is a reply */
2862 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
)
2864 int mb_idx
= BP_FW_MB_IDX(bp
);
2868 u8 delay
= CHIP_REV_IS_SLOW(bp
) ? 100 : 10;
2870 mutex_lock(&bp
->fw_mb_mutex
);
2872 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_param
, param
);
2873 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_header
, (command
| seq
));
2875 DP(BNX2X_MSG_MCP
, "wrote command (%x) to FW MB param 0x%08x\n",
2876 (command
| seq
), param
);
2879 /* let the FW do it's magic ... */
2882 rc
= SHMEM_RD(bp
, func_mb
[mb_idx
].fw_mb_header
);
2884 /* Give the FW up to 5 second (500*10ms) */
2885 } while ((seq
!= (rc
& FW_MSG_SEQ_NUMBER_MASK
)) && (cnt
++ < 500));
2887 DP(BNX2X_MSG_MCP
, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2888 cnt
*delay
, rc
, seq
);
2890 /* is this a reply to our command? */
2891 if (seq
== (rc
& FW_MSG_SEQ_NUMBER_MASK
))
2892 rc
&= FW_MSG_CODE_MASK
;
2895 BNX2X_ERR("FW failed to respond!\n");
2899 mutex_unlock(&bp
->fw_mb_mutex
);
2905 static void storm_memset_func_cfg(struct bnx2x
*bp
,
2906 struct tstorm_eth_function_common_config
*tcfg
,
2909 size_t size
= sizeof(struct tstorm_eth_function_common_config
);
2911 u32 addr
= BAR_TSTRORM_INTMEM
+
2912 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid
);
2914 __storm_memset_struct(bp
, addr
, size
, (u32
*)tcfg
);
2917 void bnx2x_func_init(struct bnx2x
*bp
, struct bnx2x_func_init_params
*p
)
2919 if (CHIP_IS_E1x(bp
)) {
2920 struct tstorm_eth_function_common_config tcfg
= {0};
2922 storm_memset_func_cfg(bp
, &tcfg
, p
->func_id
);
2925 /* Enable the function in the FW */
2926 storm_memset_vf_to_pf(bp
, p
->func_id
, p
->pf_id
);
2927 storm_memset_func_en(bp
, p
->func_id
, 1);
2930 if (p
->func_flgs
& FUNC_FLG_SPQ
) {
2931 storm_memset_spq_addr(bp
, p
->spq_map
, p
->func_id
);
2932 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+
2933 XSTORM_SPQ_PROD_OFFSET(p
->func_id
), p
->spq_prod
);
2938 * bnx2x_get_tx_only_flags - Return common flags
2942 * @zero_stats TRUE if statistics zeroing is needed
2944 * Return the flags that are common for the Tx-only and not normal connections.
2946 static unsigned long bnx2x_get_common_flags(struct bnx2x
*bp
,
2947 struct bnx2x_fastpath
*fp
,
2950 unsigned long flags
= 0;
2952 /* PF driver will always initialize the Queue to an ACTIVE state */
2953 __set_bit(BNX2X_Q_FLG_ACTIVE
, &flags
);
2955 /* tx only connections collect statistics (on the same index as the
2956 * parent connection). The statistics are zeroed when the parent
2957 * connection is initialized.
2960 __set_bit(BNX2X_Q_FLG_STATS
, &flags
);
2962 __set_bit(BNX2X_Q_FLG_ZERO_STATS
, &flags
);
2964 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT
, &flags
);
2965 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
, &flags
);
2967 #ifdef BNX2X_STOP_ON_ERROR
2968 __set_bit(BNX2X_Q_FLG_TX_SEC
, &flags
);
2974 static unsigned long bnx2x_get_q_flags(struct bnx2x
*bp
,
2975 struct bnx2x_fastpath
*fp
,
2978 unsigned long flags
= 0;
2980 /* calculate other queue flags */
2982 __set_bit(BNX2X_Q_FLG_OV
, &flags
);
2984 if (IS_FCOE_FP(fp
)) {
2985 __set_bit(BNX2X_Q_FLG_FCOE
, &flags
);
2986 /* For FCoE - force usage of default priority (for afex) */
2987 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI
, &flags
);
2990 if (!fp
->disable_tpa
) {
2991 __set_bit(BNX2X_Q_FLG_TPA
, &flags
);
2992 __set_bit(BNX2X_Q_FLG_TPA_IPV6
, &flags
);
2993 if (fp
->mode
== TPA_MODE_GRO
)
2994 __set_bit(BNX2X_Q_FLG_TPA_GRO
, &flags
);
2998 __set_bit(BNX2X_Q_FLG_LEADING_RSS
, &flags
);
2999 __set_bit(BNX2X_Q_FLG_MCAST
, &flags
);
3002 /* Always set HW VLAN stripping */
3003 __set_bit(BNX2X_Q_FLG_VLAN
, &flags
);
3005 /* configure silent vlan removal */
3007 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM
, &flags
);
3010 return flags
| bnx2x_get_common_flags(bp
, fp
, true);
3013 static void bnx2x_pf_q_prep_general(struct bnx2x
*bp
,
3014 struct bnx2x_fastpath
*fp
, struct bnx2x_general_setup_params
*gen_init
,
3017 gen_init
->stat_id
= bnx2x_stats_id(fp
);
3018 gen_init
->spcl_id
= fp
->cl_id
;
3020 /* Always use mini-jumbo MTU for FCoE L2 ring */
3022 gen_init
->mtu
= BNX2X_FCOE_MINI_JUMBO_MTU
;
3024 gen_init
->mtu
= bp
->dev
->mtu
;
3026 gen_init
->cos
= cos
;
3029 static void bnx2x_pf_rx_q_prep(struct bnx2x
*bp
,
3030 struct bnx2x_fastpath
*fp
, struct rxq_pause_params
*pause
,
3031 struct bnx2x_rxq_setup_params
*rxq_init
)
3035 u16 tpa_agg_size
= 0;
3037 if (!fp
->disable_tpa
) {
3038 pause
->sge_th_lo
= SGE_TH_LO(bp
);
3039 pause
->sge_th_hi
= SGE_TH_HI(bp
);
3041 /* validate SGE ring has enough to cross high threshold */
3042 WARN_ON(bp
->dropless_fc
&&
3043 pause
->sge_th_hi
+ FW_PREFETCH_CNT
>
3044 MAX_RX_SGE_CNT
* NUM_RX_SGE_PAGES
);
3046 tpa_agg_size
= TPA_AGG_SIZE
;
3047 max_sge
= SGE_PAGE_ALIGN(bp
->dev
->mtu
) >>
3049 max_sge
= ((max_sge
+ PAGES_PER_SGE
- 1) &
3050 (~(PAGES_PER_SGE
-1))) >> PAGES_PER_SGE_SHIFT
;
3051 sge_sz
= (u16
)min_t(u32
, SGE_PAGES
, 0xffff);
3054 /* pause - not for e1 */
3055 if (!CHIP_IS_E1(bp
)) {
3056 pause
->bd_th_lo
= BD_TH_LO(bp
);
3057 pause
->bd_th_hi
= BD_TH_HI(bp
);
3059 pause
->rcq_th_lo
= RCQ_TH_LO(bp
);
3060 pause
->rcq_th_hi
= RCQ_TH_HI(bp
);
3062 * validate that rings have enough entries to cross
3065 WARN_ON(bp
->dropless_fc
&&
3066 pause
->bd_th_hi
+ FW_PREFETCH_CNT
>
3068 WARN_ON(bp
->dropless_fc
&&
3069 pause
->rcq_th_hi
+ FW_PREFETCH_CNT
>
3070 NUM_RCQ_RINGS
* MAX_RCQ_DESC_CNT
);
3076 rxq_init
->dscr_map
= fp
->rx_desc_mapping
;
3077 rxq_init
->sge_map
= fp
->rx_sge_mapping
;
3078 rxq_init
->rcq_map
= fp
->rx_comp_mapping
;
3079 rxq_init
->rcq_np_map
= fp
->rx_comp_mapping
+ BCM_PAGE_SIZE
;
3081 /* This should be a maximum number of data bytes that may be
3082 * placed on the BD (not including paddings).
3084 rxq_init
->buf_sz
= fp
->rx_buf_size
- BNX2X_FW_RX_ALIGN_START
-
3085 BNX2X_FW_RX_ALIGN_END
- IP_HEADER_ALIGNMENT_PADDING
;
3087 rxq_init
->cl_qzone_id
= fp
->cl_qzone_id
;
3088 rxq_init
->tpa_agg_sz
= tpa_agg_size
;
3089 rxq_init
->sge_buf_sz
= sge_sz
;
3090 rxq_init
->max_sges_pkt
= max_sge
;
3091 rxq_init
->rss_engine_id
= BP_FUNC(bp
);
3092 rxq_init
->mcast_engine_id
= BP_FUNC(bp
);
3094 /* Maximum number or simultaneous TPA aggregation for this Queue.
3096 * For PF Clients it should be the maximum available number.
3097 * VF driver(s) may want to define it to a smaller value.
3099 rxq_init
->max_tpa_queues
= MAX_AGG_QS(bp
);
3101 rxq_init
->cache_line_log
= BNX2X_RX_ALIGN_SHIFT
;
3102 rxq_init
->fw_sb_id
= fp
->fw_sb_id
;
3105 rxq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS
;
3107 rxq_init
->sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
3108 /* configure silent vlan removal
3109 * if multi function mode is afex, then mask default vlan
3111 if (IS_MF_AFEX(bp
)) {
3112 rxq_init
->silent_removal_value
= bp
->afex_def_vlan_tag
;
3113 rxq_init
->silent_removal_mask
= VLAN_VID_MASK
;
3117 static void bnx2x_pf_tx_q_prep(struct bnx2x
*bp
,
3118 struct bnx2x_fastpath
*fp
, struct bnx2x_txq_setup_params
*txq_init
,
3121 txq_init
->dscr_map
= fp
->txdata_ptr
[cos
]->tx_desc_mapping
;
3122 txq_init
->sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
+ cos
;
3123 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_NW
;
3124 txq_init
->fw_sb_id
= fp
->fw_sb_id
;
3127 * set the tss leading client id for TX classfication ==
3128 * leading RSS client id
3130 txq_init
->tss_leading_cl_id
= bnx2x_fp(bp
, 0, cl_id
);
3132 if (IS_FCOE_FP(fp
)) {
3133 txq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS
;
3134 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_FCOE
;
3138 static void bnx2x_pf_init(struct bnx2x
*bp
)
3140 struct bnx2x_func_init_params func_init
= {0};
3141 struct event_ring_data eq_data
= { {0} };
3144 if (!CHIP_IS_E1x(bp
)) {
3145 /* reset IGU PF statistics: MSIX + ATTN */
3147 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3148 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3149 (CHIP_MODE_IS_4_PORT(bp
) ?
3150 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3152 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3153 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3154 BNX2X_IGU_STAS_MSG_PF_CNT
*4 +
3155 (CHIP_MODE_IS_4_PORT(bp
) ?
3156 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3159 /* function setup flags */
3160 flags
= (FUNC_FLG_STATS
| FUNC_FLG_LEADING
| FUNC_FLG_SPQ
);
3162 /* This flag is relevant for E1x only.
3163 * E2 doesn't have a TPA configuration in a function level.
3165 flags
|= (bp
->flags
& TPA_ENABLE_FLAG
) ? FUNC_FLG_TPA
: 0;
3167 func_init
.func_flgs
= flags
;
3168 func_init
.pf_id
= BP_FUNC(bp
);
3169 func_init
.func_id
= BP_FUNC(bp
);
3170 func_init
.spq_map
= bp
->spq_mapping
;
3171 func_init
.spq_prod
= bp
->spq_prod_idx
;
3173 bnx2x_func_init(bp
, &func_init
);
3175 memset(&(bp
->cmng
), 0, sizeof(struct cmng_struct_per_port
));
3178 * Congestion management values depend on the link rate
3179 * There is no active link so initial link rate is set to 10 Gbps.
3180 * When the link comes up The congestion management values are
3181 * re-calculated according to the actual link rate.
3183 bp
->link_vars
.line_speed
= SPEED_10000
;
3184 bnx2x_cmng_fns_init(bp
, true, bnx2x_get_cmng_fns_mode(bp
));
3186 /* Only the PMF sets the HW */
3188 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3190 /* init Event Queue - PCI bus guarantees correct endianity*/
3191 eq_data
.base_addr
.hi
= U64_HI(bp
->eq_mapping
);
3192 eq_data
.base_addr
.lo
= U64_LO(bp
->eq_mapping
);
3193 eq_data
.producer
= bp
->eq_prod
;
3194 eq_data
.index_id
= HC_SP_INDEX_EQ_CONS
;
3195 eq_data
.sb_id
= DEF_SB_ID
;
3196 storm_memset_eq_data(bp
, &eq_data
, BP_FUNC(bp
));
3200 static void bnx2x_e1h_disable(struct bnx2x
*bp
)
3202 int port
= BP_PORT(bp
);
3204 bnx2x_tx_disable(bp
);
3206 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
3209 static void bnx2x_e1h_enable(struct bnx2x
*bp
)
3211 int port
= BP_PORT(bp
);
3213 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
3215 /* Tx queue should be only reenabled */
3216 netif_tx_wake_all_queues(bp
->dev
);
3219 * Should not call netif_carrier_on since it will be called if the link
3220 * is up when checking for link state
3224 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3226 static void bnx2x_drv_info_ether_stat(struct bnx2x
*bp
)
3228 struct eth_stats_info
*ether_stat
=
3229 &bp
->slowpath
->drv_info_to_mcp
.ether_stat
;
3230 struct bnx2x_vlan_mac_obj
*mac_obj
=
3231 &bp
->sp_objs
->mac_obj
;
3234 strlcpy(ether_stat
->version
, DRV_MODULE_VERSION
,
3235 ETH_STAT_INFO_VERSION_LEN
);
3237 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3238 * mac_local field in ether_stat struct. The base address is offset by 2
3239 * bytes to account for the field being 8 bytes but a mac address is
3240 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3241 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3242 * allocated by the ether_stat struct, so the macs will land in their
3245 for (i
= 0; i
< DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
; i
++)
3246 memset(ether_stat
->mac_local
+ i
, 0,
3247 sizeof(ether_stat
->mac_local
[0]));
3248 mac_obj
->get_n_elements(bp
, &bp
->sp_objs
[0].mac_obj
,
3249 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
,
3250 ether_stat
->mac_local
+ MAC_PAD
, MAC_PAD
,
3252 ether_stat
->mtu_size
= bp
->dev
->mtu
;
3253 if (bp
->dev
->features
& NETIF_F_RXCSUM
)
3254 ether_stat
->feature_flags
|= FEATURE_ETH_CHKSUM_OFFLOAD_MASK
;
3255 if (bp
->dev
->features
& NETIF_F_TSO
)
3256 ether_stat
->feature_flags
|= FEATURE_ETH_LSO_MASK
;
3257 ether_stat
->feature_flags
|= bp
->common
.boot_mode
;
3259 ether_stat
->promiscuous_mode
= (bp
->dev
->flags
& IFF_PROMISC
) ? 1 : 0;
3261 ether_stat
->txq_size
= bp
->tx_ring_size
;
3262 ether_stat
->rxq_size
= bp
->rx_ring_size
;
3265 static void bnx2x_drv_info_fcoe_stat(struct bnx2x
*bp
)
3267 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3268 struct fcoe_stats_info
*fcoe_stat
=
3269 &bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
;
3271 if (!CNIC_LOADED(bp
))
3274 memcpy(fcoe_stat
->mac_local
+ MAC_PAD
, bp
->fip_mac
, ETH_ALEN
);
3276 fcoe_stat
->qos_priority
=
3277 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_FCOE
];
3279 /* insert FCoE stats from ramrod response */
3281 struct tstorm_per_queue_stats
*fcoe_q_tstorm_stats
=
3282 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3283 tstorm_queue_statistics
;
3285 struct xstorm_per_queue_stats
*fcoe_q_xstorm_stats
=
3286 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3287 xstorm_queue_statistics
;
3289 struct fcoe_statistics_params
*fw_fcoe_stat
=
3290 &bp
->fw_stats_data
->fcoe
;
3292 ADD_64_LE(fcoe_stat
->rx_bytes_hi
, LE32_0
,
3293 fcoe_stat
->rx_bytes_lo
,
3294 fw_fcoe_stat
->rx_stat0
.fcoe_rx_byte_cnt
);
3296 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3297 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.hi
,
3298 fcoe_stat
->rx_bytes_lo
,
3299 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.lo
);
3301 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3302 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.hi
,
3303 fcoe_stat
->rx_bytes_lo
,
3304 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.lo
);
3306 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3307 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.hi
,
3308 fcoe_stat
->rx_bytes_lo
,
3309 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.lo
);
3311 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3312 fcoe_stat
->rx_frames_lo
,
3313 fw_fcoe_stat
->rx_stat0
.fcoe_rx_pkt_cnt
);
3315 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3316 fcoe_stat
->rx_frames_lo
,
3317 fcoe_q_tstorm_stats
->rcv_ucast_pkts
);
3319 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3320 fcoe_stat
->rx_frames_lo
,
3321 fcoe_q_tstorm_stats
->rcv_bcast_pkts
);
3323 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3324 fcoe_stat
->rx_frames_lo
,
3325 fcoe_q_tstorm_stats
->rcv_mcast_pkts
);
3327 ADD_64_LE(fcoe_stat
->tx_bytes_hi
, LE32_0
,
3328 fcoe_stat
->tx_bytes_lo
,
3329 fw_fcoe_stat
->tx_stat
.fcoe_tx_byte_cnt
);
3331 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3332 fcoe_q_xstorm_stats
->ucast_bytes_sent
.hi
,
3333 fcoe_stat
->tx_bytes_lo
,
3334 fcoe_q_xstorm_stats
->ucast_bytes_sent
.lo
);
3336 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3337 fcoe_q_xstorm_stats
->bcast_bytes_sent
.hi
,
3338 fcoe_stat
->tx_bytes_lo
,
3339 fcoe_q_xstorm_stats
->bcast_bytes_sent
.lo
);
3341 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3342 fcoe_q_xstorm_stats
->mcast_bytes_sent
.hi
,
3343 fcoe_stat
->tx_bytes_lo
,
3344 fcoe_q_xstorm_stats
->mcast_bytes_sent
.lo
);
3346 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3347 fcoe_stat
->tx_frames_lo
,
3348 fw_fcoe_stat
->tx_stat
.fcoe_tx_pkt_cnt
);
3350 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3351 fcoe_stat
->tx_frames_lo
,
3352 fcoe_q_xstorm_stats
->ucast_pkts_sent
);
3354 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3355 fcoe_stat
->tx_frames_lo
,
3356 fcoe_q_xstorm_stats
->bcast_pkts_sent
);
3358 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3359 fcoe_stat
->tx_frames_lo
,
3360 fcoe_q_xstorm_stats
->mcast_pkts_sent
);
3363 /* ask L5 driver to add data to the struct */
3364 bnx2x_cnic_notify(bp
, CNIC_CTL_FCOE_STATS_GET_CMD
);
3367 static void bnx2x_drv_info_iscsi_stat(struct bnx2x
*bp
)
3369 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3370 struct iscsi_stats_info
*iscsi_stat
=
3371 &bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
;
3373 if (!CNIC_LOADED(bp
))
3376 memcpy(iscsi_stat
->mac_local
+ MAC_PAD
, bp
->cnic_eth_dev
.iscsi_mac
,
3379 iscsi_stat
->qos_priority
=
3380 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_ISCSI
];
3382 /* ask L5 driver to add data to the struct */
3383 bnx2x_cnic_notify(bp
, CNIC_CTL_ISCSI_STATS_GET_CMD
);
3386 /* called due to MCP event (on pmf):
3387 * reread new bandwidth configuration
3389 * notify others function about the change
3391 static void bnx2x_config_mf_bw(struct bnx2x
*bp
)
3393 if (bp
->link_vars
.link_up
) {
3394 bnx2x_cmng_fns_init(bp
, true, CMNG_FNS_MINMAX
);
3395 bnx2x_link_sync_notify(bp
);
3397 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3400 static void bnx2x_set_mf_bw(struct bnx2x
*bp
)
3402 bnx2x_config_mf_bw(bp
);
3403 bnx2x_fw_command(bp
, DRV_MSG_CODE_SET_MF_BW_ACK
, 0);
3406 static void bnx2x_handle_eee_event(struct bnx2x
*bp
)
3408 DP(BNX2X_MSG_MCP
, "EEE - LLDP event\n");
3409 bnx2x_fw_command(bp
, DRV_MSG_CODE_EEE_RESULTS_ACK
, 0);
3412 static void bnx2x_handle_drv_info_req(struct bnx2x
*bp
)
3414 enum drv_info_opcode op_code
;
3415 u32 drv_info_ctl
= SHMEM2_RD(bp
, drv_info_control
);
3417 /* if drv_info version supported by MFW doesn't match - send NACK */
3418 if ((drv_info_ctl
& DRV_INFO_CONTROL_VER_MASK
) != DRV_INFO_CUR_VER
) {
3419 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3423 op_code
= (drv_info_ctl
& DRV_INFO_CONTROL_OP_CODE_MASK
) >>
3424 DRV_INFO_CONTROL_OP_CODE_SHIFT
;
3426 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3427 sizeof(union drv_info_to_mcp
));
3430 case ETH_STATS_OPCODE
:
3431 bnx2x_drv_info_ether_stat(bp
);
3433 case FCOE_STATS_OPCODE
:
3434 bnx2x_drv_info_fcoe_stat(bp
);
3436 case ISCSI_STATS_OPCODE
:
3437 bnx2x_drv_info_iscsi_stat(bp
);
3440 /* if op code isn't supported - send NACK */
3441 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3445 /* if we got drv_info attn from MFW then these fields are defined in
3448 SHMEM2_WR(bp
, drv_info_host_addr_lo
,
3449 U64_LO(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3450 SHMEM2_WR(bp
, drv_info_host_addr_hi
,
3451 U64_HI(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3453 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_ACK
, 0);
3456 static void bnx2x_dcc_event(struct bnx2x
*bp
, u32 dcc_event
)
3458 DP(BNX2X_MSG_MCP
, "dcc_event 0x%x\n", dcc_event
);
3460 if (dcc_event
& DRV_STATUS_DCC_DISABLE_ENABLE_PF
) {
3463 * This is the only place besides the function initialization
3464 * where the bp->flags can change so it is done without any
3467 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
3468 DP(BNX2X_MSG_MCP
, "mf_cfg function disabled\n");
3469 bp
->flags
|= MF_FUNC_DIS
;
3471 bnx2x_e1h_disable(bp
);
3473 DP(BNX2X_MSG_MCP
, "mf_cfg function enabled\n");
3474 bp
->flags
&= ~MF_FUNC_DIS
;
3476 bnx2x_e1h_enable(bp
);
3478 dcc_event
&= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF
;
3480 if (dcc_event
& DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
) {
3481 bnx2x_config_mf_bw(bp
);
3482 dcc_event
&= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
;
3485 /* Report results to MCP */
3487 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_FAILURE
, 0);
3489 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_OK
, 0);
3492 /* must be called under the spq lock */
3493 static struct eth_spe
*bnx2x_sp_get_next(struct bnx2x
*bp
)
3495 struct eth_spe
*next_spe
= bp
->spq_prod_bd
;
3497 if (bp
->spq_prod_bd
== bp
->spq_last_bd
) {
3498 bp
->spq_prod_bd
= bp
->spq
;
3499 bp
->spq_prod_idx
= 0;
3500 DP(BNX2X_MSG_SP
, "end of spq\n");
3508 /* must be called under the spq lock */
3509 static void bnx2x_sp_prod_update(struct bnx2x
*bp
)
3511 int func
= BP_FUNC(bp
);
3514 * Make sure that BD data is updated before writing the producer:
3515 * BD data is written to the memory, the producer is read from the
3516 * memory, thus we need a full memory barrier to ensure the ordering.
3520 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_PROD_OFFSET(func
),
3526 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3528 * @cmd: command to check
3529 * @cmd_type: command type
3531 static bool bnx2x_is_contextless_ramrod(int cmd
, int cmd_type
)
3533 if ((cmd_type
== NONE_CONNECTION_TYPE
) ||
3534 (cmd
== RAMROD_CMD_ID_ETH_FORWARD_SETUP
) ||
3535 (cmd
== RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
) ||
3536 (cmd
== RAMROD_CMD_ID_ETH_FILTER_RULES
) ||
3537 (cmd
== RAMROD_CMD_ID_ETH_MULTICAST_RULES
) ||
3538 (cmd
== RAMROD_CMD_ID_ETH_SET_MAC
) ||
3539 (cmd
== RAMROD_CMD_ID_ETH_RSS_UPDATE
))
3548 * bnx2x_sp_post - place a single command on an SP ring
3550 * @bp: driver handle
3551 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3552 * @cid: SW CID the command is related to
3553 * @data_hi: command private data address (high 32 bits)
3554 * @data_lo: command private data address (low 32 bits)
3555 * @cmd_type: command type (e.g. NONE, ETH)
3557 * SP data is handled as if it's always an address pair, thus data fields are
3558 * not swapped to little endian in upper functions. Instead this function swaps
3559 * data as if it's two u32 fields.
3561 int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
3562 u32 data_hi
, u32 data_lo
, int cmd_type
)
3564 struct eth_spe
*spe
;
3566 bool common
= bnx2x_is_contextless_ramrod(command
, cmd_type
);
3568 #ifdef BNX2X_STOP_ON_ERROR
3569 if (unlikely(bp
->panic
)) {
3570 BNX2X_ERR("Can't post SP when there is panic\n");
3575 spin_lock_bh(&bp
->spq_lock
);
3578 if (!atomic_read(&bp
->eq_spq_left
)) {
3579 BNX2X_ERR("BUG! EQ ring full!\n");
3580 spin_unlock_bh(&bp
->spq_lock
);
3584 } else if (!atomic_read(&bp
->cq_spq_left
)) {
3585 BNX2X_ERR("BUG! SPQ ring full!\n");
3586 spin_unlock_bh(&bp
->spq_lock
);
3591 spe
= bnx2x_sp_get_next(bp
);
3593 /* CID needs port number to be encoded int it */
3594 spe
->hdr
.conn_and_cmd_data
=
3595 cpu_to_le32((command
<< SPE_HDR_CMD_ID_SHIFT
) |
3598 type
= (cmd_type
<< SPE_HDR_CONN_TYPE_SHIFT
) & SPE_HDR_CONN_TYPE
;
3600 type
|= ((BP_FUNC(bp
) << SPE_HDR_FUNCTION_ID_SHIFT
) &
3601 SPE_HDR_FUNCTION_ID
);
3603 spe
->hdr
.type
= cpu_to_le16(type
);
3605 spe
->data
.update_data_addr
.hi
= cpu_to_le32(data_hi
);
3606 spe
->data
.update_data_addr
.lo
= cpu_to_le32(data_lo
);
3609 * It's ok if the actual decrement is issued towards the memory
3610 * somewhere between the spin_lock and spin_unlock. Thus no
3611 * more explict memory barrier is needed.
3614 atomic_dec(&bp
->eq_spq_left
);
3616 atomic_dec(&bp
->cq_spq_left
);
3620 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3621 bp
->spq_prod_idx
, (u32
)U64_HI(bp
->spq_mapping
),
3622 (u32
)(U64_LO(bp
->spq_mapping
) +
3623 (void *)bp
->spq_prod_bd
- (void *)bp
->spq
), command
, common
,
3624 HW_CID(bp
, cid
), data_hi
, data_lo
, type
,
3625 atomic_read(&bp
->cq_spq_left
), atomic_read(&bp
->eq_spq_left
));
3627 bnx2x_sp_prod_update(bp
);
3628 spin_unlock_bh(&bp
->spq_lock
);
3632 /* acquire split MCP access lock register */
3633 static int bnx2x_acquire_alr(struct bnx2x
*bp
)
3639 for (j
= 0; j
< 1000; j
++) {
3641 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, val
);
3642 val
= REG_RD(bp
, GRCBASE_MCP
+ 0x9c);
3643 if (val
& (1L << 31))
3648 if (!(val
& (1L << 31))) {
3649 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3656 /* release split MCP access lock register */
3657 static void bnx2x_release_alr(struct bnx2x
*bp
)
3659 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, 0);
3662 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3663 #define BNX2X_DEF_SB_IDX 0x0002
3665 static u16
bnx2x_update_dsb_idx(struct bnx2x
*bp
)
3667 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
3670 barrier(); /* status block is written to by the chip */
3671 if (bp
->def_att_idx
!= def_sb
->atten_status_block
.attn_bits_index
) {
3672 bp
->def_att_idx
= def_sb
->atten_status_block
.attn_bits_index
;
3673 rc
|= BNX2X_DEF_SB_ATT_IDX
;
3676 if (bp
->def_idx
!= def_sb
->sp_sb
.running_index
) {
3677 bp
->def_idx
= def_sb
->sp_sb
.running_index
;
3678 rc
|= BNX2X_DEF_SB_IDX
;
3681 /* Do not reorder: indecies reading should complete before handling */
3687 * slow path service functions
3690 static void bnx2x_attn_int_asserted(struct bnx2x
*bp
, u32 asserted
)
3692 int port
= BP_PORT(bp
);
3693 u32 aeu_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
3694 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
3695 u32 nig_int_mask_addr
= port
? NIG_REG_MASK_INTERRUPT_PORT1
:
3696 NIG_REG_MASK_INTERRUPT_PORT0
;
3701 if (bp
->attn_state
& asserted
)
3702 BNX2X_ERR("IGU ERROR\n");
3704 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3705 aeu_mask
= REG_RD(bp
, aeu_addr
);
3707 DP(NETIF_MSG_HW
, "aeu_mask %x newly asserted %x\n",
3708 aeu_mask
, asserted
);
3709 aeu_mask
&= ~(asserted
& 0x3ff);
3710 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
3712 REG_WR(bp
, aeu_addr
, aeu_mask
);
3713 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3715 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
3716 bp
->attn_state
|= asserted
;
3717 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
3719 if (asserted
& ATTN_HARD_WIRED_MASK
) {
3720 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3722 bnx2x_acquire_phy_lock(bp
);
3724 /* save nig interrupt mask */
3725 nig_mask
= REG_RD(bp
, nig_int_mask_addr
);
3727 /* If nig_mask is not set, no need to call the update
3731 REG_WR(bp
, nig_int_mask_addr
, 0);
3733 bnx2x_link_attn(bp
);
3736 /* handle unicore attn? */
3738 if (asserted
& ATTN_SW_TIMER_4_FUNC
)
3739 DP(NETIF_MSG_HW
, "ATTN_SW_TIMER_4_FUNC!\n");
3741 if (asserted
& GPIO_2_FUNC
)
3742 DP(NETIF_MSG_HW
, "GPIO_2_FUNC!\n");
3744 if (asserted
& GPIO_3_FUNC
)
3745 DP(NETIF_MSG_HW
, "GPIO_3_FUNC!\n");
3747 if (asserted
& GPIO_4_FUNC
)
3748 DP(NETIF_MSG_HW
, "GPIO_4_FUNC!\n");
3751 if (asserted
& ATTN_GENERAL_ATTN_1
) {
3752 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_1!\n");
3753 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_1
, 0x0);
3755 if (asserted
& ATTN_GENERAL_ATTN_2
) {
3756 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_2!\n");
3757 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_2
, 0x0);
3759 if (asserted
& ATTN_GENERAL_ATTN_3
) {
3760 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_3!\n");
3761 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_3
, 0x0);
3764 if (asserted
& ATTN_GENERAL_ATTN_4
) {
3765 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_4!\n");
3766 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_4
, 0x0);
3768 if (asserted
& ATTN_GENERAL_ATTN_5
) {
3769 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_5!\n");
3770 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_5
, 0x0);
3772 if (asserted
& ATTN_GENERAL_ATTN_6
) {
3773 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_6!\n");
3774 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_6
, 0x0);
3778 } /* if hardwired */
3780 if (bp
->common
.int_block
== INT_BLOCK_HC
)
3781 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
3782 COMMAND_REG_ATTN_BITS_SET
);
3784 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_SET_UPPER
*8);
3786 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", asserted
,
3787 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
3788 REG_WR(bp
, reg_addr
, asserted
);
3790 /* now set back the mask */
3791 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3792 /* Verify that IGU ack through BAR was written before restoring
3793 * NIG mask. This loop should exit after 2-3 iterations max.
3795 if (bp
->common
.int_block
!= INT_BLOCK_HC
) {
3796 u32 cnt
= 0, igu_acked
;
3798 igu_acked
= REG_RD(bp
,
3799 IGU_REG_ATTENTION_ACK_BITS
);
3800 } while (((igu_acked
& ATTN_NIG_FOR_FUNC
) == 0) &&
3801 (++cnt
< MAX_IGU_ATTN_ACK_TO
));
3804 "Failed to verify IGU ack on time\n");
3807 REG_WR(bp
, nig_int_mask_addr
, nig_mask
);
3808 bnx2x_release_phy_lock(bp
);
3812 static void bnx2x_fan_failure(struct bnx2x
*bp
)
3814 int port
= BP_PORT(bp
);
3816 /* mark the failure */
3819 dev_info
.port_hw_config
[port
].external_phy_config
);
3821 ext_phy_config
&= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
;
3822 ext_phy_config
|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
;
3823 SHMEM_WR(bp
, dev_info
.port_hw_config
[port
].external_phy_config
,
3826 /* log the failure */
3827 netdev_err(bp
->dev
, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3828 "Please contact OEM Support for assistance\n");
3831 * Schedule device reset (unload)
3832 * This is due to some boards consuming sufficient power when driver is
3833 * up to overheat if fan fails.
3835 smp_mb__before_clear_bit();
3836 set_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
);
3837 smp_mb__after_clear_bit();
3838 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
3842 static void bnx2x_attn_int_deasserted0(struct bnx2x
*bp
, u32 attn
)
3844 int port
= BP_PORT(bp
);
3848 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
3849 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
3851 if (attn
& AEU_INPUTS_ATTN_BITS_SPIO5
) {
3853 val
= REG_RD(bp
, reg_offset
);
3854 val
&= ~AEU_INPUTS_ATTN_BITS_SPIO5
;
3855 REG_WR(bp
, reg_offset
, val
);
3857 BNX2X_ERR("SPIO5 hw attention\n");
3859 /* Fan failure attention */
3860 bnx2x_hw_reset_phy(&bp
->link_params
);
3861 bnx2x_fan_failure(bp
);
3864 if ((attn
& bp
->link_vars
.aeu_int_mask
) && bp
->port
.pmf
) {
3865 bnx2x_acquire_phy_lock(bp
);
3866 bnx2x_handle_module_detect_int(&bp
->link_params
);
3867 bnx2x_release_phy_lock(bp
);
3870 if (attn
& HW_INTERRUT_ASSERT_SET_0
) {
3872 val
= REG_RD(bp
, reg_offset
);
3873 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_0
);
3874 REG_WR(bp
, reg_offset
, val
);
3876 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3877 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_0
));
3882 static void bnx2x_attn_int_deasserted1(struct bnx2x
*bp
, u32 attn
)
3886 if (attn
& AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
) {
3888 val
= REG_RD(bp
, DORQ_REG_DORQ_INT_STS_CLR
);
3889 BNX2X_ERR("DB hw attention 0x%x\n", val
);
3890 /* DORQ discard attention */
3892 BNX2X_ERR("FATAL error from DORQ\n");
3895 if (attn
& HW_INTERRUT_ASSERT_SET_1
) {
3897 int port
= BP_PORT(bp
);
3900 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
:
3901 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
);
3903 val
= REG_RD(bp
, reg_offset
);
3904 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_1
);
3905 REG_WR(bp
, reg_offset
, val
);
3907 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3908 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_1
));
3913 static void bnx2x_attn_int_deasserted2(struct bnx2x
*bp
, u32 attn
)
3917 if (attn
& AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
) {
3919 val
= REG_RD(bp
, CFC_REG_CFC_INT_STS_CLR
);
3920 BNX2X_ERR("CFC hw attention 0x%x\n", val
);
3921 /* CFC error attention */
3923 BNX2X_ERR("FATAL error from CFC\n");
3926 if (attn
& AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
) {
3927 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_0
);
3928 BNX2X_ERR("PXP hw attention-0 0x%x\n", val
);
3929 /* RQ_USDMDP_FIFO_OVERFLOW */
3931 BNX2X_ERR("FATAL error from PXP\n");
3933 if (!CHIP_IS_E1x(bp
)) {
3934 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_1
);
3935 BNX2X_ERR("PXP hw attention-1 0x%x\n", val
);
3939 if (attn
& HW_INTERRUT_ASSERT_SET_2
) {
3941 int port
= BP_PORT(bp
);
3944 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
:
3945 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
);
3947 val
= REG_RD(bp
, reg_offset
);
3948 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_2
);
3949 REG_WR(bp
, reg_offset
, val
);
3951 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3952 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_2
));
3957 static void bnx2x_attn_int_deasserted3(struct bnx2x
*bp
, u32 attn
)
3961 if (attn
& EVEREST_GEN_ATTN_IN_USE_MASK
) {
3963 if (attn
& BNX2X_PMF_LINK_ASSERT
) {
3964 int func
= BP_FUNC(bp
);
3966 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
3967 bnx2x_read_mf_cfg(bp
);
3968 bp
->mf_config
[BP_VN(bp
)] = MF_CFG_RD(bp
,
3969 func_mf_config
[BP_ABS_FUNC(bp
)].config
);
3971 func_mb
[BP_FW_MB_IDX(bp
)].drv_status
);
3972 if (val
& DRV_STATUS_DCC_EVENT_MASK
)
3974 (val
& DRV_STATUS_DCC_EVENT_MASK
));
3976 if (val
& DRV_STATUS_SET_MF_BW
)
3977 bnx2x_set_mf_bw(bp
);
3979 if (val
& DRV_STATUS_DRV_INFO_REQ
)
3980 bnx2x_handle_drv_info_req(bp
);
3982 if (val
& DRV_STATUS_VF_DISABLED
)
3983 bnx2x_vf_handle_flr_event(bp
);
3985 if ((bp
->port
.pmf
== 0) && (val
& DRV_STATUS_PMF
))
3986 bnx2x_pmf_update(bp
);
3989 (val
& DRV_STATUS_DCBX_NEGOTIATION_RESULTS
) &&
3990 bp
->dcbx_enabled
> 0)
3991 /* start dcbx state machine */
3992 bnx2x_dcbx_set_params(bp
,
3993 BNX2X_DCBX_STATE_NEG_RECEIVED
);
3994 if (val
& DRV_STATUS_AFEX_EVENT_MASK
)
3995 bnx2x_handle_afex_cmd(bp
,
3996 val
& DRV_STATUS_AFEX_EVENT_MASK
);
3997 if (val
& DRV_STATUS_EEE_NEGOTIATION_RESULTS
)
3998 bnx2x_handle_eee_event(bp
);
3999 if (bp
->link_vars
.periodic_flags
&
4000 PERIODIC_FLAGS_LINK_EVENT
) {
4001 /* sync with link */
4002 bnx2x_acquire_phy_lock(bp
);
4003 bp
->link_vars
.periodic_flags
&=
4004 ~PERIODIC_FLAGS_LINK_EVENT
;
4005 bnx2x_release_phy_lock(bp
);
4007 bnx2x_link_sync_notify(bp
);
4008 bnx2x_link_report(bp
);
4010 /* Always call it here: bnx2x_link_report() will
4011 * prevent the link indication duplication.
4013 bnx2x__link_status_update(bp
);
4014 } else if (attn
& BNX2X_MC_ASSERT_BITS
) {
4016 BNX2X_ERR("MC assert!\n");
4017 bnx2x_mc_assert(bp
);
4018 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_10
, 0);
4019 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_9
, 0);
4020 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_8
, 0);
4021 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_7
, 0);
4024 } else if (attn
& BNX2X_MCP_ASSERT
) {
4026 BNX2X_ERR("MCP assert!\n");
4027 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_11
, 0);
4031 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn
);
4034 if (attn
& EVEREST_LATCHED_ATTN_IN_USE_MASK
) {
4035 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn
);
4036 if (attn
& BNX2X_GRC_TIMEOUT
) {
4037 val
= CHIP_IS_E1(bp
) ? 0 :
4038 REG_RD(bp
, MISC_REG_GRC_TIMEOUT_ATTN
);
4039 BNX2X_ERR("GRC time-out 0x%08x\n", val
);
4041 if (attn
& BNX2X_GRC_RSV
) {
4042 val
= CHIP_IS_E1(bp
) ? 0 :
4043 REG_RD(bp
, MISC_REG_GRC_RSV_ATTN
);
4044 BNX2X_ERR("GRC reserved 0x%08x\n", val
);
4046 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
, 0x7ff);
4052 * 0-7 - Engine0 load counter.
4053 * 8-15 - Engine1 load counter.
4054 * 16 - Engine0 RESET_IN_PROGRESS bit.
4055 * 17 - Engine1 RESET_IN_PROGRESS bit.
4056 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4058 * 19 - Engine1 ONE_IS_LOADED.
4059 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4060 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4061 * just the one belonging to its engine).
4064 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4066 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4067 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4068 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4069 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4070 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4071 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4072 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4075 * Set the GLOBAL_RESET bit.
4077 * Should be run under rtnl lock
4079 void bnx2x_set_reset_global(struct bnx2x
*bp
)
4082 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4083 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4084 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
| BNX2X_GLOBAL_RESET_BIT
);
4085 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4089 * Clear the GLOBAL_RESET bit.
4091 * Should be run under rtnl lock
4093 static void bnx2x_clear_reset_global(struct bnx2x
*bp
)
4096 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4097 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4098 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~BNX2X_GLOBAL_RESET_BIT
));
4099 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4103 * Checks the GLOBAL_RESET bit.
4105 * should be run under rtnl lock
4107 static bool bnx2x_reset_is_global(struct bnx2x
*bp
)
4109 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4111 DP(NETIF_MSG_HW
, "GEN_REG_VAL=0x%08x\n", val
);
4112 return (val
& BNX2X_GLOBAL_RESET_BIT
) ? true : false;
4116 * Clear RESET_IN_PROGRESS bit for the current engine.
4118 * Should be run under rtnl lock
4120 static void bnx2x_set_reset_done(struct bnx2x
*bp
)
4123 u32 bit
= BP_PATH(bp
) ?
4124 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4125 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4126 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4130 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4132 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4136 * Set RESET_IN_PROGRESS for the current engine.
4138 * should be run under rtnl lock
4140 void bnx2x_set_reset_in_progress(struct bnx2x
*bp
)
4143 u32 bit
= BP_PATH(bp
) ?
4144 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4145 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4146 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4150 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4151 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4155 * Checks the RESET_IN_PROGRESS bit for the given engine.
4156 * should be run under rtnl lock
4158 bool bnx2x_reset_is_done(struct bnx2x
*bp
, int engine
)
4160 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4162 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4164 /* return false if bit is set */
4165 return (val
& bit
) ? false : true;
4169 * set pf load for the current pf.
4171 * should be run under rtnl lock
4173 void bnx2x_set_pf_load(struct bnx2x
*bp
)
4176 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4177 BNX2X_PATH0_LOAD_CNT_MASK
;
4178 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4179 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4181 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4182 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4184 DP(NETIF_MSG_IFUP
, "Old GEN_REG_VAL=0x%08x\n", val
);
4186 /* get the current counter value */
4187 val1
= (val
& mask
) >> shift
;
4189 /* set bit of that PF */
4190 val1
|= (1 << bp
->pf_num
);
4192 /* clear the old value */
4195 /* set the new one */
4196 val
|= ((val1
<< shift
) & mask
);
4198 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4199 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4203 * bnx2x_clear_pf_load - clear pf load mark
4205 * @bp: driver handle
4207 * Should be run under rtnl lock.
4208 * Decrements the load counter for the current engine. Returns
4209 * whether other functions are still loaded
4211 bool bnx2x_clear_pf_load(struct bnx2x
*bp
)
4214 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4215 BNX2X_PATH0_LOAD_CNT_MASK
;
4216 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4217 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4219 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4220 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4221 DP(NETIF_MSG_IFDOWN
, "Old GEN_REG_VAL=0x%08x\n", val
);
4223 /* get the current counter value */
4224 val1
= (val
& mask
) >> shift
;
4226 /* clear bit of that PF */
4227 val1
&= ~(1 << bp
->pf_num
);
4229 /* clear the old value */
4232 /* set the new one */
4233 val
|= ((val1
<< shift
) & mask
);
4235 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4236 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4241 * Read the load status for the current engine.
4243 * should be run under rtnl lock
4245 static bool bnx2x_get_load_status(struct bnx2x
*bp
, int engine
)
4247 u32 mask
= (engine
? BNX2X_PATH1_LOAD_CNT_MASK
:
4248 BNX2X_PATH0_LOAD_CNT_MASK
);
4249 u32 shift
= (engine
? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4250 BNX2X_PATH0_LOAD_CNT_SHIFT
);
4251 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4253 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "GLOB_REG=0x%08x\n", val
);
4255 val
= (val
& mask
) >> shift
;
4257 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "load mask for engine %d = 0x%x\n",
4263 static void _print_next_block(int idx
, const char *blk
)
4265 pr_cont("%s%s", idx
? ", " : "", blk
);
4268 static int bnx2x_check_blocks_with_parity0(u32 sig
, int par_num
,
4273 for (i
= 0; sig
; i
++) {
4274 cur_bit
= ((u32
)0x1 << i
);
4275 if (sig
& cur_bit
) {
4277 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
:
4279 _print_next_block(par_num
++, "BRB");
4281 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
:
4283 _print_next_block(par_num
++, "PARSER");
4285 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
:
4287 _print_next_block(par_num
++, "TSDM");
4289 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
:
4291 _print_next_block(par_num
++,
4294 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
:
4296 _print_next_block(par_num
++, "TCM");
4298 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
:
4300 _print_next_block(par_num
++, "TSEMI");
4302 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
:
4304 _print_next_block(par_num
++, "XPB");
4316 static int bnx2x_check_blocks_with_parity1(u32 sig
, int par_num
,
4317 bool *global
, bool print
)
4321 for (i
= 0; sig
; i
++) {
4322 cur_bit
= ((u32
)0x1 << i
);
4323 if (sig
& cur_bit
) {
4325 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
:
4327 _print_next_block(par_num
++, "PBF");
4329 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
:
4331 _print_next_block(par_num
++, "QM");
4333 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
:
4335 _print_next_block(par_num
++, "TM");
4337 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
:
4339 _print_next_block(par_num
++, "XSDM");
4341 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
:
4343 _print_next_block(par_num
++, "XCM");
4345 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
:
4347 _print_next_block(par_num
++, "XSEMI");
4349 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
:
4351 _print_next_block(par_num
++,
4354 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
:
4356 _print_next_block(par_num
++, "NIG");
4358 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
:
4360 _print_next_block(par_num
++,
4364 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
:
4366 _print_next_block(par_num
++, "DEBUG");
4368 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
:
4370 _print_next_block(par_num
++, "USDM");
4372 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
:
4374 _print_next_block(par_num
++, "UCM");
4376 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
:
4378 _print_next_block(par_num
++, "USEMI");
4380 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
:
4382 _print_next_block(par_num
++, "UPB");
4384 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
:
4386 _print_next_block(par_num
++, "CSDM");
4388 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
:
4390 _print_next_block(par_num
++, "CCM");
4402 static int bnx2x_check_blocks_with_parity2(u32 sig
, int par_num
,
4407 for (i
= 0; sig
; i
++) {
4408 cur_bit
= ((u32
)0x1 << i
);
4409 if (sig
& cur_bit
) {
4411 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
:
4413 _print_next_block(par_num
++, "CSEMI");
4415 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
:
4417 _print_next_block(par_num
++, "PXP");
4419 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
:
4421 _print_next_block(par_num
++,
4422 "PXPPCICLOCKCLIENT");
4424 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
:
4426 _print_next_block(par_num
++, "CFC");
4428 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
:
4430 _print_next_block(par_num
++, "CDU");
4432 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
:
4434 _print_next_block(par_num
++, "DMAE");
4436 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
:
4438 _print_next_block(par_num
++, "IGU");
4440 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
:
4442 _print_next_block(par_num
++, "MISC");
4454 static int bnx2x_check_blocks_with_parity3(u32 sig
, int par_num
,
4455 bool *global
, bool print
)
4459 for (i
= 0; sig
; i
++) {
4460 cur_bit
= ((u32
)0x1 << i
);
4461 if (sig
& cur_bit
) {
4463 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
:
4465 _print_next_block(par_num
++, "MCP ROM");
4468 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
:
4470 _print_next_block(par_num
++,
4474 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
:
4476 _print_next_block(par_num
++,
4480 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
:
4482 _print_next_block(par_num
++,
4496 static int bnx2x_check_blocks_with_parity4(u32 sig
, int par_num
,
4501 for (i
= 0; sig
; i
++) {
4502 cur_bit
= ((u32
)0x1 << i
);
4503 if (sig
& cur_bit
) {
4505 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
:
4507 _print_next_block(par_num
++, "PGLUE_B");
4509 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
:
4511 _print_next_block(par_num
++, "ATC");
4523 static bool bnx2x_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
,
4526 if ((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4527 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4528 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4529 (sig
[3] & HW_PRTY_ASSERT_SET_3
) ||
4530 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) {
4532 DP(NETIF_MSG_HW
, "Was parity error: HW block parity attention:\n"
4533 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4534 sig
[0] & HW_PRTY_ASSERT_SET_0
,
4535 sig
[1] & HW_PRTY_ASSERT_SET_1
,
4536 sig
[2] & HW_PRTY_ASSERT_SET_2
,
4537 sig
[3] & HW_PRTY_ASSERT_SET_3
,
4538 sig
[4] & HW_PRTY_ASSERT_SET_4
);
4541 "Parity errors detected in blocks: ");
4542 par_num
= bnx2x_check_blocks_with_parity0(
4543 sig
[0] & HW_PRTY_ASSERT_SET_0
, par_num
, print
);
4544 par_num
= bnx2x_check_blocks_with_parity1(
4545 sig
[1] & HW_PRTY_ASSERT_SET_1
, par_num
, global
, print
);
4546 par_num
= bnx2x_check_blocks_with_parity2(
4547 sig
[2] & HW_PRTY_ASSERT_SET_2
, par_num
, print
);
4548 par_num
= bnx2x_check_blocks_with_parity3(
4549 sig
[3] & HW_PRTY_ASSERT_SET_3
, par_num
, global
, print
);
4550 par_num
= bnx2x_check_blocks_with_parity4(
4551 sig
[4] & HW_PRTY_ASSERT_SET_4
, par_num
, print
);
4562 * bnx2x_chk_parity_attn - checks for parity attentions.
4564 * @bp: driver handle
4565 * @global: true if there was a global attention
4566 * @print: show parity attention in syslog
4568 bool bnx2x_chk_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
)
4570 struct attn_route attn
= { {0} };
4571 int port
= BP_PORT(bp
);
4573 attn
.sig
[0] = REG_RD(bp
,
4574 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+
4576 attn
.sig
[1] = REG_RD(bp
,
4577 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+
4579 attn
.sig
[2] = REG_RD(bp
,
4580 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+
4582 attn
.sig
[3] = REG_RD(bp
,
4583 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+
4586 if (!CHIP_IS_E1x(bp
))
4587 attn
.sig
[4] = REG_RD(bp
,
4588 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+
4591 return bnx2x_parity_attn(bp
, global
, print
, attn
.sig
);
4595 static void bnx2x_attn_int_deasserted4(struct bnx2x
*bp
, u32 attn
)
4598 if (attn
& AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
) {
4600 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS_CLR
);
4601 BNX2X_ERR("PGLUE hw attention 0x%x\n", val
);
4602 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
)
4603 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4604 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
)
4605 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4606 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
)
4607 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4608 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
)
4609 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4611 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
)
4612 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4614 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
)
4615 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4616 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
)
4617 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4618 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
)
4619 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4620 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
)
4621 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4623 if (attn
& AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
) {
4624 val
= REG_RD(bp
, ATC_REG_ATC_INT_STS_CLR
);
4625 BNX2X_ERR("ATC hw attention 0x%x\n", val
);
4626 if (val
& ATC_ATC_INT_STS_REG_ADDRESS_ERROR
)
4627 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4628 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
)
4629 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4630 if (val
& ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
)
4631 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4632 if (val
& ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
)
4633 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4634 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
)
4635 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4636 if (val
& ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
)
4637 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4640 if (attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4641 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)) {
4642 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4643 (u32
)(attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4644 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)));
4649 static void bnx2x_attn_int_deasserted(struct bnx2x
*bp
, u32 deasserted
)
4651 struct attn_route attn
, *group_mask
;
4652 int port
= BP_PORT(bp
);
4657 bool global
= false;
4659 /* need to take HW lock because MCP or other port might also
4660 try to handle this event */
4661 bnx2x_acquire_alr(bp
);
4663 if (bnx2x_chk_parity_attn(bp
, &global
, true)) {
4664 #ifndef BNX2X_STOP_ON_ERROR
4665 bp
->recovery_state
= BNX2X_RECOVERY_INIT
;
4666 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
4667 /* Disable HW interrupts */
4668 bnx2x_int_disable(bp
);
4669 /* In case of parity errors don't handle attentions so that
4670 * other function would "see" parity errors.
4675 bnx2x_release_alr(bp
);
4679 attn
.sig
[0] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ port
*4);
4680 attn
.sig
[1] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+ port
*4);
4681 attn
.sig
[2] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+ port
*4);
4682 attn
.sig
[3] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+ port
*4);
4683 if (!CHIP_IS_E1x(bp
))
4685 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+ port
*4);
4689 DP(NETIF_MSG_HW
, "attn: %08x %08x %08x %08x %08x\n",
4690 attn
.sig
[0], attn
.sig
[1], attn
.sig
[2], attn
.sig
[3], attn
.sig
[4]);
4692 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
4693 if (deasserted
& (1 << index
)) {
4694 group_mask
= &bp
->attn_group
[index
];
4696 DP(NETIF_MSG_HW
, "group[%d]: %08x %08x %08x %08x %08x\n",
4698 group_mask
->sig
[0], group_mask
->sig
[1],
4699 group_mask
->sig
[2], group_mask
->sig
[3],
4700 group_mask
->sig
[4]);
4702 bnx2x_attn_int_deasserted4(bp
,
4703 attn
.sig
[4] & group_mask
->sig
[4]);
4704 bnx2x_attn_int_deasserted3(bp
,
4705 attn
.sig
[3] & group_mask
->sig
[3]);
4706 bnx2x_attn_int_deasserted1(bp
,
4707 attn
.sig
[1] & group_mask
->sig
[1]);
4708 bnx2x_attn_int_deasserted2(bp
,
4709 attn
.sig
[2] & group_mask
->sig
[2]);
4710 bnx2x_attn_int_deasserted0(bp
,
4711 attn
.sig
[0] & group_mask
->sig
[0]);
4715 bnx2x_release_alr(bp
);
4717 if (bp
->common
.int_block
== INT_BLOCK_HC
)
4718 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
4719 COMMAND_REG_ATTN_BITS_CLR
);
4721 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_CLR_UPPER
*8);
4724 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", val
,
4725 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
4726 REG_WR(bp
, reg_addr
, val
);
4728 if (~bp
->attn_state
& deasserted
)
4729 BNX2X_ERR("IGU ERROR\n");
4731 reg_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
4732 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
4734 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4735 aeu_mask
= REG_RD(bp
, reg_addr
);
4737 DP(NETIF_MSG_HW
, "aeu_mask %x newly deasserted %x\n",
4738 aeu_mask
, deasserted
);
4739 aeu_mask
|= (deasserted
& 0x3ff);
4740 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
4742 REG_WR(bp
, reg_addr
, aeu_mask
);
4743 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4745 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
4746 bp
->attn_state
&= ~deasserted
;
4747 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
4750 static void bnx2x_attn_int(struct bnx2x
*bp
)
4752 /* read local copy of bits */
4753 u32 attn_bits
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4755 u32 attn_ack
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4757 u32 attn_state
= bp
->attn_state
;
4759 /* look for changed bits */
4760 u32 asserted
= attn_bits
& ~attn_ack
& ~attn_state
;
4761 u32 deasserted
= ~attn_bits
& attn_ack
& attn_state
;
4764 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4765 attn_bits
, attn_ack
, asserted
, deasserted
);
4767 if (~(attn_bits
^ attn_ack
) & (attn_bits
^ attn_state
))
4768 BNX2X_ERR("BAD attention state\n");
4770 /* handle bits that were raised */
4772 bnx2x_attn_int_asserted(bp
, asserted
);
4775 bnx2x_attn_int_deasserted(bp
, deasserted
);
4778 void bnx2x_igu_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 segment
,
4779 u16 index
, u8 op
, u8 update
)
4781 u32 igu_addr
= bp
->igu_base_addr
;
4782 igu_addr
+= (IGU_CMD_INT_ACK_BASE
+ igu_sb_id
)*8;
4783 bnx2x_igu_ack_sb_gen(bp
, igu_sb_id
, segment
, index
, op
, update
,
4787 static void bnx2x_update_eq_prod(struct bnx2x
*bp
, u16 prod
)
4789 /* No memory barriers */
4790 storm_memset_eq_prod(bp
, prod
, BP_FUNC(bp
));
4791 mmiowb(); /* keep prod updates ordered */
4794 static int bnx2x_cnic_handle_cfc_del(struct bnx2x
*bp
, u32 cid
,
4795 union event_ring_elem
*elem
)
4797 u8 err
= elem
->message
.error
;
4799 if (!bp
->cnic_eth_dev
.starting_cid
||
4800 (cid
< bp
->cnic_eth_dev
.starting_cid
&&
4801 cid
!= bp
->cnic_eth_dev
.iscsi_l2_cid
))
4804 DP(BNX2X_MSG_SP
, "got delete ramrod for CNIC CID %d\n", cid
);
4806 if (unlikely(err
)) {
4808 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4810 bnx2x_panic_dump(bp
, false);
4812 bnx2x_cnic_cfc_comp(bp
, cid
, err
);
4816 static void bnx2x_handle_mcast_eqe(struct bnx2x
*bp
)
4818 struct bnx2x_mcast_ramrod_params rparam
;
4821 memset(&rparam
, 0, sizeof(rparam
));
4823 rparam
.mcast_obj
= &bp
->mcast_obj
;
4825 netif_addr_lock_bh(bp
->dev
);
4827 /* Clear pending state for the last command */
4828 bp
->mcast_obj
.raw
.clear_pending(&bp
->mcast_obj
.raw
);
4830 /* If there are pending mcast commands - send them */
4831 if (bp
->mcast_obj
.check_pending(&bp
->mcast_obj
)) {
4832 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_CONT
);
4834 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4838 netif_addr_unlock_bh(bp
->dev
);
4841 static void bnx2x_handle_classification_eqe(struct bnx2x
*bp
,
4842 union event_ring_elem
*elem
)
4844 unsigned long ramrod_flags
= 0;
4846 u32 cid
= elem
->message
.data
.eth_event
.echo
& BNX2X_SWCID_MASK
;
4847 struct bnx2x_vlan_mac_obj
*vlan_mac_obj
;
4849 /* Always push next commands out, don't wait here */
4850 __set_bit(RAMROD_CONT
, &ramrod_flags
);
4852 switch (le32_to_cpu((__force __le32
)elem
->message
.data
.eth_event
.echo
)
4853 >> BNX2X_SWCID_SHIFT
) {
4854 case BNX2X_FILTER_MAC_PENDING
:
4855 DP(BNX2X_MSG_SP
, "Got SETUP_MAC completions\n");
4856 if (CNIC_LOADED(bp
) && (cid
== BNX2X_ISCSI_ETH_CID(bp
)))
4857 vlan_mac_obj
= &bp
->iscsi_l2_mac_obj
;
4859 vlan_mac_obj
= &bp
->sp_objs
[cid
].mac_obj
;
4862 case BNX2X_FILTER_MCAST_PENDING
:
4863 DP(BNX2X_MSG_SP
, "Got SETUP_MCAST completions\n");
4864 /* This is only relevant for 57710 where multicast MACs are
4865 * configured as unicast MACs using the same ramrod.
4867 bnx2x_handle_mcast_eqe(bp
);
4870 BNX2X_ERR("Unsupported classification command: %d\n",
4871 elem
->message
.data
.eth_event
.echo
);
4875 rc
= vlan_mac_obj
->complete(bp
, vlan_mac_obj
, elem
, &ramrod_flags
);
4878 BNX2X_ERR("Failed to schedule new commands: %d\n", rc
);
4880 DP(BNX2X_MSG_SP
, "Scheduled next pending commands...\n");
4884 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
);
4886 static void bnx2x_handle_rx_mode_eqe(struct bnx2x
*bp
)
4888 netif_addr_lock_bh(bp
->dev
);
4890 clear_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
4892 /* Send rx_mode command again if was requested */
4893 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
))
4894 bnx2x_set_storm_rx_mode(bp
);
4895 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
,
4897 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
4898 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
,
4900 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
4902 netif_addr_unlock_bh(bp
->dev
);
4905 static void bnx2x_after_afex_vif_lists(struct bnx2x
*bp
,
4906 union event_ring_elem
*elem
)
4908 if (elem
->message
.data
.vif_list_event
.echo
== VIF_LIST_RULE_GET
) {
4910 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4911 elem
->message
.data
.vif_list_event
.func_bit_map
);
4912 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTGET_ACK
,
4913 elem
->message
.data
.vif_list_event
.func_bit_map
);
4914 } else if (elem
->message
.data
.vif_list_event
.echo
==
4915 VIF_LIST_RULE_SET
) {
4916 DP(BNX2X_MSG_SP
, "afex: ramrod completed VIF LIST_SET\n");
4917 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTSET_ACK
, 0);
4921 /* called with rtnl_lock */
4922 static void bnx2x_after_function_update(struct bnx2x
*bp
)
4925 struct bnx2x_fastpath
*fp
;
4926 struct bnx2x_queue_state_params queue_params
= {NULL
};
4927 struct bnx2x_queue_update_params
*q_update_params
=
4928 &queue_params
.params
.update
;
4930 /* Send Q update command with afex vlan removal values for all Qs */
4931 queue_params
.cmd
= BNX2X_Q_CMD_UPDATE
;
4933 /* set silent vlan removal values according to vlan mode */
4934 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG
,
4935 &q_update_params
->update_flags
);
4936 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM
,
4937 &q_update_params
->update_flags
);
4938 __set_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
4940 /* in access mode mark mask and value are 0 to strip all vlans */
4941 if (bp
->afex_vlan_mode
== FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE
) {
4942 q_update_params
->silent_removal_value
= 0;
4943 q_update_params
->silent_removal_mask
= 0;
4945 q_update_params
->silent_removal_value
=
4946 (bp
->afex_def_vlan_tag
& VLAN_VID_MASK
);
4947 q_update_params
->silent_removal_mask
= VLAN_VID_MASK
;
4950 for_each_eth_queue(bp
, q
) {
4951 /* Set the appropriate Queue object */
4953 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
4955 /* send the ramrod */
4956 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
4958 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4962 if (!NO_FCOE(bp
) && CNIC_ENABLED(bp
)) {
4963 fp
= &bp
->fp
[FCOE_IDX(bp
)];
4964 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
4966 /* clear pending completion bit */
4967 __clear_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
4969 /* mark latest Q bit */
4970 smp_mb__before_clear_bit();
4971 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
4972 smp_mb__after_clear_bit();
4974 /* send Q update ramrod for FCoE Q */
4975 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
4977 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4980 /* If no FCoE ring - ACK MCP now */
4981 bnx2x_link_report(bp
);
4982 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
4986 static struct bnx2x_queue_sp_obj
*bnx2x_cid_to_q_obj(
4987 struct bnx2x
*bp
, u32 cid
)
4989 DP(BNX2X_MSG_SP
, "retrieving fp from cid %d\n", cid
);
4991 if (CNIC_LOADED(bp
) && (cid
== BNX2X_FCOE_ETH_CID(bp
)))
4992 return &bnx2x_fcoe_sp_obj(bp
, q_obj
);
4994 return &bp
->sp_objs
[CID_TO_FP(cid
, bp
)].q_obj
;
4997 static void bnx2x_eq_int(struct bnx2x
*bp
)
4999 u16 hw_cons
, sw_cons
, sw_prod
;
5000 union event_ring_elem
*elem
;
5004 int rc
, spqe_cnt
= 0;
5005 struct bnx2x_queue_sp_obj
*q_obj
;
5006 struct bnx2x_func_sp_obj
*f_obj
= &bp
->func_obj
;
5007 struct bnx2x_raw_obj
*rss_raw
= &bp
->rss_conf_obj
.raw
;
5009 hw_cons
= le16_to_cpu(*bp
->eq_cons_sb
);
5011 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5012 * when we get the the next-page we nned to adjust so the loop
5013 * condition below will be met. The next element is the size of a
5014 * regular element and hence incrementing by 1
5016 if ((hw_cons
& EQ_DESC_MAX_PAGE
) == EQ_DESC_MAX_PAGE
)
5019 /* This function may never run in parallel with itself for a
5020 * specific bp, thus there is no need in "paired" read memory
5023 sw_cons
= bp
->eq_cons
;
5024 sw_prod
= bp
->eq_prod
;
5026 DP(BNX2X_MSG_SP
, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5027 hw_cons
, sw_cons
, atomic_read(&bp
->eq_spq_left
));
5029 for (; sw_cons
!= hw_cons
;
5030 sw_prod
= NEXT_EQ_IDX(sw_prod
), sw_cons
= NEXT_EQ_IDX(sw_cons
)) {
5032 elem
= &bp
->eq_ring
[EQ_DESC(sw_cons
)];
5034 rc
= bnx2x_iov_eq_sp_event(bp
, elem
);
5036 DP(BNX2X_MSG_IOV
, "bnx2x_iov_eq_sp_event returned %d\n",
5041 /* elem CID originates from FW; actually LE */
5042 cid
= SW_CID((__force __le32
)
5043 elem
->message
.data
.cfc_del_event
.cid
);
5044 opcode
= elem
->message
.opcode
;
5046 /* handle eq element */
5048 case EVENT_RING_OPCODE_VF_PF_CHANNEL
:
5049 DP(BNX2X_MSG_IOV
, "vf pf channel element on eq\n");
5050 bnx2x_vf_mbx(bp
, &elem
->message
.data
.vf_pf_event
);
5053 case EVENT_RING_OPCODE_STAT_QUERY
:
5054 DP(BNX2X_MSG_SP
| BNX2X_MSG_STATS
,
5055 "got statistics comp event %d\n",
5057 /* nothing to do with stats comp */
5060 case EVENT_RING_OPCODE_CFC_DEL
:
5061 /* handle according to cid range */
5063 * we may want to verify here that the bp state is
5067 "got delete ramrod for MULTI[%d]\n", cid
);
5069 if (CNIC_LOADED(bp
) &&
5070 !bnx2x_cnic_handle_cfc_del(bp
, cid
, elem
))
5073 q_obj
= bnx2x_cid_to_q_obj(bp
, cid
);
5075 if (q_obj
->complete_cmd(bp
, q_obj
, BNX2X_Q_CMD_CFC_DEL
))
5082 case EVENT_RING_OPCODE_STOP_TRAFFIC
:
5083 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got STOP TRAFFIC\n");
5084 if (f_obj
->complete_cmd(bp
, f_obj
,
5085 BNX2X_F_CMD_TX_STOP
))
5087 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_PAUSED
);
5090 case EVENT_RING_OPCODE_START_TRAFFIC
:
5091 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got START TRAFFIC\n");
5092 if (f_obj
->complete_cmd(bp
, f_obj
,
5093 BNX2X_F_CMD_TX_START
))
5095 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_RELEASED
);
5098 case EVENT_RING_OPCODE_FUNCTION_UPDATE
:
5099 echo
= elem
->message
.data
.function_update_event
.echo
;
5100 if (echo
== SWITCH_UPDATE
) {
5101 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5102 "got FUNC_SWITCH_UPDATE ramrod\n");
5103 if (f_obj
->complete_cmd(
5104 bp
, f_obj
, BNX2X_F_CMD_SWITCH_UPDATE
))
5108 DP(BNX2X_MSG_SP
| BNX2X_MSG_MCP
,
5109 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5110 f_obj
->complete_cmd(bp
, f_obj
,
5111 BNX2X_F_CMD_AFEX_UPDATE
);
5113 /* We will perform the Queues update from
5114 * sp_rtnl task as all Queue SP operations
5115 * should run under rtnl_lock.
5117 smp_mb__before_clear_bit();
5118 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE
,
5119 &bp
->sp_rtnl_state
);
5120 smp_mb__after_clear_bit();
5122 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
5127 case EVENT_RING_OPCODE_AFEX_VIF_LISTS
:
5128 f_obj
->complete_cmd(bp
, f_obj
,
5129 BNX2X_F_CMD_AFEX_VIFLISTS
);
5130 bnx2x_after_afex_vif_lists(bp
, elem
);
5132 case EVENT_RING_OPCODE_FUNCTION_START
:
5133 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5134 "got FUNC_START ramrod\n");
5135 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_START
))
5140 case EVENT_RING_OPCODE_FUNCTION_STOP
:
5141 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5142 "got FUNC_STOP ramrod\n");
5143 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_STOP
))
5149 switch (opcode
| bp
->state
) {
5150 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5152 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5153 BNX2X_STATE_OPENING_WAIT4_PORT
):
5154 cid
= elem
->message
.data
.eth_event
.echo
&
5156 DP(BNX2X_MSG_SP
, "got RSS_UPDATE ramrod. CID %d\n",
5158 rss_raw
->clear_pending(rss_raw
);
5161 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_OPEN
):
5162 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_DIAG
):
5163 case (EVENT_RING_OPCODE_SET_MAC
|
5164 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5165 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5167 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5169 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5170 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5171 DP(BNX2X_MSG_SP
, "got (un)set mac ramrod\n");
5172 bnx2x_handle_classification_eqe(bp
, elem
);
5175 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5177 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5179 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5180 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5181 DP(BNX2X_MSG_SP
, "got mcast ramrod\n");
5182 bnx2x_handle_mcast_eqe(bp
);
5185 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5187 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5189 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5190 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5191 DP(BNX2X_MSG_SP
, "got rx_mode ramrod\n");
5192 bnx2x_handle_rx_mode_eqe(bp
);
5195 /* unknown event log error and continue */
5196 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5197 elem
->message
.opcode
, bp
->state
);
5203 smp_mb__before_atomic_inc();
5204 atomic_add(spqe_cnt
, &bp
->eq_spq_left
);
5206 bp
->eq_cons
= sw_cons
;
5207 bp
->eq_prod
= sw_prod
;
5208 /* Make sure that above mem writes were issued towards the memory */
5211 /* update producer */
5212 bnx2x_update_eq_prod(bp
, bp
->eq_prod
);
5215 static void bnx2x_sp_task(struct work_struct
*work
)
5217 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_task
.work
);
5219 DP(BNX2X_MSG_SP
, "sp task invoked\n");
5221 /* make sure the atomic interupt_occurred has been written */
5223 if (atomic_read(&bp
->interrupt_occurred
)) {
5225 /* what work needs to be performed? */
5226 u16 status
= bnx2x_update_dsb_idx(bp
);
5228 DP(BNX2X_MSG_SP
, "status %x\n", status
);
5229 DP(BNX2X_MSG_SP
, "setting interrupt_occurred to 0\n");
5230 atomic_set(&bp
->interrupt_occurred
, 0);
5233 if (status
& BNX2X_DEF_SB_ATT_IDX
) {
5235 status
&= ~BNX2X_DEF_SB_ATT_IDX
;
5238 /* SP events: STAT_QUERY and others */
5239 if (status
& BNX2X_DEF_SB_IDX
) {
5240 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
5242 if (FCOE_INIT(bp
) &&
5243 (bnx2x_has_rx_work(fp
) || bnx2x_has_tx_work(fp
))) {
5244 /* Prevent local bottom-halves from running as
5245 * we are going to change the local NAPI list.
5248 napi_schedule(&bnx2x_fcoe(bp
, napi
));
5252 /* Handle EQ completions */
5254 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
,
5255 le16_to_cpu(bp
->def_idx
), IGU_INT_NOP
, 1);
5257 status
&= ~BNX2X_DEF_SB_IDX
;
5260 /* if status is non zero then perhaps something went wrong */
5261 if (unlikely(status
))
5263 "got an unknown interrupt! (status 0x%x)\n", status
);
5265 /* ack status block only if something was actually handled */
5266 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, ATTENTION_ID
,
5267 le16_to_cpu(bp
->def_att_idx
), IGU_INT_ENABLE
, 1);
5271 /* must be called after the EQ processing (since eq leads to sriov
5272 * ramrod completion flows).
5273 * This flow may have been scheduled by the arrival of a ramrod
5274 * completion, or by the sriov code rescheduling itself.
5276 bnx2x_iov_sp_task(bp
);
5278 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5279 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
,
5281 bnx2x_link_report(bp
);
5282 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
5286 irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
)
5288 struct net_device
*dev
= dev_instance
;
5289 struct bnx2x
*bp
= netdev_priv(dev
);
5291 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0,
5292 IGU_INT_DISABLE
, 0);
5294 #ifdef BNX2X_STOP_ON_ERROR
5295 if (unlikely(bp
->panic
))
5299 if (CNIC_LOADED(bp
)) {
5300 struct cnic_ops
*c_ops
;
5303 c_ops
= rcu_dereference(bp
->cnic_ops
);
5305 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
5309 /* schedule sp task to perform default status block work, ack
5310 * attentions and enable interrupts.
5312 bnx2x_schedule_sp_task(bp
);
5317 /* end of slow path */
5320 void bnx2x_drv_pulse(struct bnx2x
*bp
)
5322 SHMEM_WR(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_pulse_mb
,
5323 bp
->fw_drv_pulse_wr_seq
);
5326 static void bnx2x_timer(unsigned long data
)
5328 struct bnx2x
*bp
= (struct bnx2x
*) data
;
5330 if (!netif_running(bp
->dev
))
5335 int mb_idx
= BP_FW_MB_IDX(bp
);
5339 ++bp
->fw_drv_pulse_wr_seq
;
5340 bp
->fw_drv_pulse_wr_seq
&= DRV_PULSE_SEQ_MASK
;
5341 /* TBD - add SYSTEM_TIME */
5342 drv_pulse
= bp
->fw_drv_pulse_wr_seq
;
5343 bnx2x_drv_pulse(bp
);
5345 mcp_pulse
= (SHMEM_RD(bp
, func_mb
[mb_idx
].mcp_pulse_mb
) &
5346 MCP_PULSE_SEQ_MASK
);
5347 /* The delta between driver pulse and mcp response
5348 * should be 1 (before mcp response) or 0 (after mcp response)
5350 if ((drv_pulse
!= mcp_pulse
) &&
5351 (drv_pulse
!= ((mcp_pulse
+ 1) & MCP_PULSE_SEQ_MASK
))) {
5352 /* someone lost a heartbeat... */
5353 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5354 drv_pulse
, mcp_pulse
);
5358 if (bp
->state
== BNX2X_STATE_OPEN
)
5359 bnx2x_stats_handle(bp
, STATS_EVENT_UPDATE
);
5361 /* sample pf vf bulletin board for new posts from pf */
5363 bnx2x_sample_bulletin(bp
);
5365 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5368 /* end of Statistics */
5373 * nic init service functions
5376 static void bnx2x_fill(struct bnx2x
*bp
, u32 addr
, int fill
, u32 len
)
5379 if (!(len
%4) && !(addr
%4))
5380 for (i
= 0; i
< len
; i
+= 4)
5381 REG_WR(bp
, addr
+ i
, fill
);
5383 for (i
= 0; i
< len
; i
++)
5384 REG_WR8(bp
, addr
+ i
, fill
);
5388 /* helper: writes FP SP data to FW - data_size in dwords */
5389 static void bnx2x_wr_fp_sb_data(struct bnx2x
*bp
,
5395 for (index
= 0; index
< data_size
; index
++)
5396 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5397 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id
) +
5399 *(sb_data_p
+ index
));
5402 static void bnx2x_zero_fp_sb(struct bnx2x
*bp
, int fw_sb_id
)
5406 struct hc_status_block_data_e2 sb_data_e2
;
5407 struct hc_status_block_data_e1x sb_data_e1x
;
5409 /* disable the function first */
5410 if (!CHIP_IS_E1x(bp
)) {
5411 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5412 sb_data_e2
.common
.state
= SB_DISABLED
;
5413 sb_data_e2
.common
.p_func
.vf_valid
= false;
5414 sb_data_p
= (u32
*)&sb_data_e2
;
5415 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5417 memset(&sb_data_e1x
, 0,
5418 sizeof(struct hc_status_block_data_e1x
));
5419 sb_data_e1x
.common
.state
= SB_DISABLED
;
5420 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5421 sb_data_p
= (u32
*)&sb_data_e1x
;
5422 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5424 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5426 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5427 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id
), 0,
5428 CSTORM_STATUS_BLOCK_SIZE
);
5429 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5430 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id
), 0,
5431 CSTORM_SYNC_BLOCK_SIZE
);
5434 /* helper: writes SP SB data to FW */
5435 static void bnx2x_wr_sp_sb_data(struct bnx2x
*bp
,
5436 struct hc_sp_status_block_data
*sp_sb_data
)
5438 int func
= BP_FUNC(bp
);
5440 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
5441 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5442 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
5444 *((u32
*)sp_sb_data
+ i
));
5447 static void bnx2x_zero_sp_sb(struct bnx2x
*bp
)
5449 int func
= BP_FUNC(bp
);
5450 struct hc_sp_status_block_data sp_sb_data
;
5451 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
5453 sp_sb_data
.state
= SB_DISABLED
;
5454 sp_sb_data
.p_func
.vf_valid
= false;
5456 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5458 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5459 CSTORM_SP_STATUS_BLOCK_OFFSET(func
), 0,
5460 CSTORM_SP_STATUS_BLOCK_SIZE
);
5461 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5462 CSTORM_SP_SYNC_BLOCK_OFFSET(func
), 0,
5463 CSTORM_SP_SYNC_BLOCK_SIZE
);
5468 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm
*hc_sm
,
5469 int igu_sb_id
, int igu_seg_id
)
5471 hc_sm
->igu_sb_id
= igu_sb_id
;
5472 hc_sm
->igu_seg_id
= igu_seg_id
;
5473 hc_sm
->timer_value
= 0xFF;
5474 hc_sm
->time_to_expire
= 0xFFFFFFFF;
5478 /* allocates state machine ids. */
5479 static void bnx2x_map_sb_state_machines(struct hc_index_data
*index_data
)
5481 /* zero out state machine indices */
5483 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5486 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5487 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5488 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5489 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5493 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
|=
5494 SM_RX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5497 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
|=
5498 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5499 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
|=
5500 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5501 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
|=
5502 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5503 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
|=
5504 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5507 void bnx2x_init_sb(struct bnx2x
*bp
, dma_addr_t mapping
, int vfid
,
5508 u8 vf_valid
, int fw_sb_id
, int igu_sb_id
)
5512 struct hc_status_block_data_e2 sb_data_e2
;
5513 struct hc_status_block_data_e1x sb_data_e1x
;
5514 struct hc_status_block_sm
*hc_sm_p
;
5518 if (CHIP_INT_MODE_IS_BC(bp
))
5519 igu_seg_id
= HC_SEG_ACCESS_NORM
;
5521 igu_seg_id
= IGU_SEG_ACCESS_NORM
;
5523 bnx2x_zero_fp_sb(bp
, fw_sb_id
);
5525 if (!CHIP_IS_E1x(bp
)) {
5526 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5527 sb_data_e2
.common
.state
= SB_ENABLED
;
5528 sb_data_e2
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5529 sb_data_e2
.common
.p_func
.vf_id
= vfid
;
5530 sb_data_e2
.common
.p_func
.vf_valid
= vf_valid
;
5531 sb_data_e2
.common
.p_func
.vnic_id
= BP_VN(bp
);
5532 sb_data_e2
.common
.same_igu_sb_1b
= true;
5533 sb_data_e2
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5534 sb_data_e2
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5535 hc_sm_p
= sb_data_e2
.common
.state_machine
;
5536 sb_data_p
= (u32
*)&sb_data_e2
;
5537 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5538 bnx2x_map_sb_state_machines(sb_data_e2
.index_data
);
5540 memset(&sb_data_e1x
, 0,
5541 sizeof(struct hc_status_block_data_e1x
));
5542 sb_data_e1x
.common
.state
= SB_ENABLED
;
5543 sb_data_e1x
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5544 sb_data_e1x
.common
.p_func
.vf_id
= 0xff;
5545 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5546 sb_data_e1x
.common
.p_func
.vnic_id
= BP_VN(bp
);
5547 sb_data_e1x
.common
.same_igu_sb_1b
= true;
5548 sb_data_e1x
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5549 sb_data_e1x
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5550 hc_sm_p
= sb_data_e1x
.common
.state_machine
;
5551 sb_data_p
= (u32
*)&sb_data_e1x
;
5552 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5553 bnx2x_map_sb_state_machines(sb_data_e1x
.index_data
);
5556 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_RX_ID
],
5557 igu_sb_id
, igu_seg_id
);
5558 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_TX_ID
],
5559 igu_sb_id
, igu_seg_id
);
5561 DP(NETIF_MSG_IFUP
, "Init FW SB %d\n", fw_sb_id
);
5563 /* write indices to HW - PCI guarantees endianity of regpairs */
5564 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5567 static void bnx2x_update_coalesce_sb(struct bnx2x
*bp
, u8 fw_sb_id
,
5568 u16 tx_usec
, u16 rx_usec
)
5570 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
, HC_INDEX_ETH_RX_CQ_CONS
,
5572 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5573 HC_INDEX_ETH_TX_CQ_CONS_COS0
, false,
5575 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5576 HC_INDEX_ETH_TX_CQ_CONS_COS1
, false,
5578 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5579 HC_INDEX_ETH_TX_CQ_CONS_COS2
, false,
5583 static void bnx2x_init_def_sb(struct bnx2x
*bp
)
5585 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
5586 dma_addr_t mapping
= bp
->def_status_blk_mapping
;
5587 int igu_sp_sb_index
;
5589 int port
= BP_PORT(bp
);
5590 int func
= BP_FUNC(bp
);
5591 int reg_offset
, reg_offset_en5
;
5594 struct hc_sp_status_block_data sp_sb_data
;
5595 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
5597 if (CHIP_INT_MODE_IS_BC(bp
)) {
5598 igu_sp_sb_index
= DEF_SB_IGU_ID
;
5599 igu_seg_id
= HC_SEG_ACCESS_DEF
;
5601 igu_sp_sb_index
= bp
->igu_dsb_id
;
5602 igu_seg_id
= IGU_SEG_ACCESS_DEF
;
5606 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
5607 atten_status_block
);
5608 def_sb
->atten_status_block
.status_block_id
= igu_sp_sb_index
;
5612 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
5613 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
5614 reg_offset_en5
= (port
? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0
:
5615 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0
);
5616 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
5618 /* take care of sig[0]..sig[4] */
5619 for (sindex
= 0; sindex
< 4; sindex
++)
5620 bp
->attn_group
[index
].sig
[sindex
] =
5621 REG_RD(bp
, reg_offset
+ sindex
*0x4 + 0x10*index
);
5623 if (!CHIP_IS_E1x(bp
))
5625 * enable5 is separate from the rest of the registers,
5626 * and therefore the address skip is 4
5627 * and not 16 between the different groups
5629 bp
->attn_group
[index
].sig
[4] = REG_RD(bp
,
5630 reg_offset_en5
+ 0x4*index
);
5632 bp
->attn_group
[index
].sig
[4] = 0;
5635 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
5636 reg_offset
= (port
? HC_REG_ATTN_MSG1_ADDR_L
:
5637 HC_REG_ATTN_MSG0_ADDR_L
);
5639 REG_WR(bp
, reg_offset
, U64_LO(section
));
5640 REG_WR(bp
, reg_offset
+ 4, U64_HI(section
));
5641 } else if (!CHIP_IS_E1x(bp
)) {
5642 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_L
, U64_LO(section
));
5643 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_H
, U64_HI(section
));
5646 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
5649 bnx2x_zero_sp_sb(bp
);
5651 /* PCI guarantees endianity of regpairs */
5652 sp_sb_data
.state
= SB_ENABLED
;
5653 sp_sb_data
.host_sb_addr
.lo
= U64_LO(section
);
5654 sp_sb_data
.host_sb_addr
.hi
= U64_HI(section
);
5655 sp_sb_data
.igu_sb_id
= igu_sp_sb_index
;
5656 sp_sb_data
.igu_seg_id
= igu_seg_id
;
5657 sp_sb_data
.p_func
.pf_id
= func
;
5658 sp_sb_data
.p_func
.vnic_id
= BP_VN(bp
);
5659 sp_sb_data
.p_func
.vf_id
= 0xff;
5661 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5663 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0, IGU_INT_ENABLE
, 0);
5666 void bnx2x_update_coalesce(struct bnx2x
*bp
)
5670 for_each_eth_queue(bp
, i
)
5671 bnx2x_update_coalesce_sb(bp
, bp
->fp
[i
].fw_sb_id
,
5672 bp
->tx_ticks
, bp
->rx_ticks
);
5675 static void bnx2x_init_sp_ring(struct bnx2x
*bp
)
5677 spin_lock_init(&bp
->spq_lock
);
5678 atomic_set(&bp
->cq_spq_left
, MAX_SPQ_PENDING
);
5680 bp
->spq_prod_idx
= 0;
5681 bp
->dsb_sp_prod
= BNX2X_SP_DSB_INDEX
;
5682 bp
->spq_prod_bd
= bp
->spq
;
5683 bp
->spq_last_bd
= bp
->spq_prod_bd
+ MAX_SP_DESC_CNT
;
5686 static void bnx2x_init_eq_ring(struct bnx2x
*bp
)
5689 for (i
= 1; i
<= NUM_EQ_PAGES
; i
++) {
5690 union event_ring_elem
*elem
=
5691 &bp
->eq_ring
[EQ_DESC_CNT_PAGE
* i
- 1];
5693 elem
->next_page
.addr
.hi
=
5694 cpu_to_le32(U64_HI(bp
->eq_mapping
+
5695 BCM_PAGE_SIZE
* (i
% NUM_EQ_PAGES
)));
5696 elem
->next_page
.addr
.lo
=
5697 cpu_to_le32(U64_LO(bp
->eq_mapping
+
5698 BCM_PAGE_SIZE
*(i
% NUM_EQ_PAGES
)));
5701 bp
->eq_prod
= NUM_EQ_DESC
;
5702 bp
->eq_cons_sb
= BNX2X_EQ_INDEX
;
5703 /* we want a warning message before it gets rought... */
5704 atomic_set(&bp
->eq_spq_left
,
5705 min_t(int, MAX_SP_DESC_CNT
- MAX_SPQ_PENDING
, NUM_EQ_DESC
) - 1);
5708 /* called with netif_addr_lock_bh() */
5709 int bnx2x_set_q_rx_mode(struct bnx2x
*bp
, u8 cl_id
,
5710 unsigned long rx_mode_flags
,
5711 unsigned long rx_accept_flags
,
5712 unsigned long tx_accept_flags
,
5713 unsigned long ramrod_flags
)
5715 struct bnx2x_rx_mode_ramrod_params ramrod_param
;
5718 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
5720 /* Prepare ramrod parameters */
5721 ramrod_param
.cid
= 0;
5722 ramrod_param
.cl_id
= cl_id
;
5723 ramrod_param
.rx_mode_obj
= &bp
->rx_mode_obj
;
5724 ramrod_param
.func_id
= BP_FUNC(bp
);
5726 ramrod_param
.pstate
= &bp
->sp_state
;
5727 ramrod_param
.state
= BNX2X_FILTER_RX_MODE_PENDING
;
5729 ramrod_param
.rdata
= bnx2x_sp(bp
, rx_mode_rdata
);
5730 ramrod_param
.rdata_mapping
= bnx2x_sp_mapping(bp
, rx_mode_rdata
);
5732 set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
5734 ramrod_param
.ramrod_flags
= ramrod_flags
;
5735 ramrod_param
.rx_mode_flags
= rx_mode_flags
;
5737 ramrod_param
.rx_accept_flags
= rx_accept_flags
;
5738 ramrod_param
.tx_accept_flags
= tx_accept_flags
;
5740 rc
= bnx2x_config_rx_mode(bp
, &ramrod_param
);
5742 BNX2X_ERR("Set rx_mode %d failed\n", bp
->rx_mode
);
5749 static int bnx2x_fill_accept_flags(struct bnx2x
*bp
, u32 rx_mode
,
5750 unsigned long *rx_accept_flags
,
5751 unsigned long *tx_accept_flags
)
5753 /* Clear the flags first */
5754 *rx_accept_flags
= 0;
5755 *tx_accept_flags
= 0;
5758 case BNX2X_RX_MODE_NONE
:
5760 * 'drop all' supersedes any accept flags that may have been
5761 * passed to the function.
5764 case BNX2X_RX_MODE_NORMAL
:
5765 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
5766 __set_bit(BNX2X_ACCEPT_MULTICAST
, rx_accept_flags
);
5767 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
5769 /* internal switching mode */
5770 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
5771 __set_bit(BNX2X_ACCEPT_MULTICAST
, tx_accept_flags
);
5772 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
5775 case BNX2X_RX_MODE_ALLMULTI
:
5776 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
5777 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, rx_accept_flags
);
5778 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
5780 /* internal switching mode */
5781 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
5782 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, tx_accept_flags
);
5783 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
5786 case BNX2X_RX_MODE_PROMISC
:
5787 /* According to deffinition of SI mode, iface in promisc mode
5788 * should receive matched and unmatched (in resolution of port)
5791 __set_bit(BNX2X_ACCEPT_UNMATCHED
, rx_accept_flags
);
5792 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
5793 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, rx_accept_flags
);
5794 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
5796 /* internal switching mode */
5797 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, tx_accept_flags
);
5798 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
5801 __set_bit(BNX2X_ACCEPT_ALL_UNICAST
, tx_accept_flags
);
5803 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
5807 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode
);
5811 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5812 if (bp
->rx_mode
!= BNX2X_RX_MODE_NONE
) {
5813 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
5814 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
5820 /* called with netif_addr_lock_bh() */
5821 int bnx2x_set_storm_rx_mode(struct bnx2x
*bp
)
5823 unsigned long rx_mode_flags
= 0, ramrod_flags
= 0;
5824 unsigned long rx_accept_flags
= 0, tx_accept_flags
= 0;
5828 /* Configure rx_mode of FCoE Queue */
5829 __set_bit(BNX2X_RX_MODE_FCOE_ETH
, &rx_mode_flags
);
5831 rc
= bnx2x_fill_accept_flags(bp
, bp
->rx_mode
, &rx_accept_flags
,
5836 __set_bit(RAMROD_RX
, &ramrod_flags
);
5837 __set_bit(RAMROD_TX
, &ramrod_flags
);
5839 return bnx2x_set_q_rx_mode(bp
, bp
->fp
->cl_id
, rx_mode_flags
,
5840 rx_accept_flags
, tx_accept_flags
,
5844 static void bnx2x_init_internal_common(struct bnx2x
*bp
)
5850 * In switch independent mode, the TSTORM needs to accept
5851 * packets that failed classification, since approximate match
5852 * mac addresses aren't written to NIG LLH
5854 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5855 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 2);
5856 else if (!CHIP_IS_E1(bp
)) /* 57710 doesn't support MF */
5857 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5858 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 0);
5860 /* Zero this manually as its initialization is
5861 currently missing in the initTool */
5862 for (i
= 0; i
< (USTORM_AGG_DATA_SIZE
>> 2); i
++)
5863 REG_WR(bp
, BAR_USTRORM_INTMEM
+
5864 USTORM_AGG_DATA_OFFSET
+ i
* 4, 0);
5865 if (!CHIP_IS_E1x(bp
)) {
5866 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_IGU_MODE_OFFSET
,
5867 CHIP_INT_MODE_IS_BC(bp
) ?
5868 HC_IGU_BC_MODE
: HC_IGU_NBC_MODE
);
5872 static void bnx2x_init_internal(struct bnx2x
*bp
, u32 load_code
)
5874 switch (load_code
) {
5875 case FW_MSG_CODE_DRV_LOAD_COMMON
:
5876 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
:
5877 bnx2x_init_internal_common(bp
);
5880 case FW_MSG_CODE_DRV_LOAD_PORT
:
5884 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
5885 /* internal memory per function is
5886 initialized inside bnx2x_pf_init */
5890 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
5895 static inline u8
bnx2x_fp_igu_sb_id(struct bnx2x_fastpath
*fp
)
5897 return fp
->bp
->igu_base_sb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
5900 static inline u8
bnx2x_fp_fw_sb_id(struct bnx2x_fastpath
*fp
)
5902 return fp
->bp
->base_fw_ndsb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
5905 static u8
bnx2x_fp_cl_id(struct bnx2x_fastpath
*fp
)
5907 if (CHIP_IS_E1x(fp
->bp
))
5908 return BP_L_ID(fp
->bp
) + fp
->index
;
5909 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5910 return bnx2x_fp_igu_sb_id(fp
);
5913 static void bnx2x_init_eth_fp(struct bnx2x
*bp
, int fp_idx
)
5915 struct bnx2x_fastpath
*fp
= &bp
->fp
[fp_idx
];
5917 unsigned long q_type
= 0;
5918 u32 cids
[BNX2X_MULTI_TX_COS
] = { 0 };
5919 fp
->rx_queue
= fp_idx
;
5921 fp
->cl_id
= bnx2x_fp_cl_id(fp
);
5922 fp
->fw_sb_id
= bnx2x_fp_fw_sb_id(fp
);
5923 fp
->igu_sb_id
= bnx2x_fp_igu_sb_id(fp
);
5924 /* qZone id equals to FW (per path) client id */
5925 fp
->cl_qzone_id
= bnx2x_fp_qzone_id(fp
);
5928 fp
->ustorm_rx_prods_offset
= bnx2x_rx_ustorm_prods_offset(fp
);
5930 /* Setup SB indicies */
5931 fp
->rx_cons_sb
= BNX2X_RX_SB_INDEX
;
5933 /* Configure Queue State object */
5934 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
5935 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
5937 BUG_ON(fp
->max_cos
> BNX2X_MULTI_TX_COS
);
5940 for_each_cos_in_tx_queue(fp
, cos
) {
5941 bnx2x_init_txdata(bp
, fp
->txdata_ptr
[cos
],
5942 CID_COS_TO_TX_ONLY_CID(fp
->cid
, cos
, bp
),
5943 FP_COS_TO_TXQ(fp
, cos
, bp
),
5944 BNX2X_TX_SB_INDEX_BASE
+ cos
, fp
);
5945 cids
[cos
] = fp
->txdata_ptr
[cos
]->cid
;
5948 /* nothing more for vf to do here */
5952 bnx2x_init_sb(bp
, fp
->status_blk_mapping
, BNX2X_VF_ID_INVALID
, false,
5953 fp
->fw_sb_id
, fp
->igu_sb_id
);
5954 bnx2x_update_fpsb_idx(fp
);
5955 bnx2x_init_queue_obj(bp
, &bnx2x_sp_obj(bp
, fp
).q_obj
, fp
->cl_id
, cids
,
5956 fp
->max_cos
, BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
5957 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
5960 * Configure classification DBs: Always enable Tx switching
5962 bnx2x_init_vlan_mac_fp_objs(fp
, BNX2X_OBJ_TYPE_RX_TX
);
5965 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5966 fp_idx
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
5970 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata
*txdata
)
5974 for (i
= 1; i
<= NUM_TX_RINGS
; i
++) {
5975 struct eth_tx_next_bd
*tx_next_bd
=
5976 &txdata
->tx_desc_ring
[TX_DESC_CNT
* i
- 1].next_bd
;
5978 tx_next_bd
->addr_hi
=
5979 cpu_to_le32(U64_HI(txdata
->tx_desc_mapping
+
5980 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
5981 tx_next_bd
->addr_lo
=
5982 cpu_to_le32(U64_LO(txdata
->tx_desc_mapping
+
5983 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
5986 SET_FLAG(txdata
->tx_db
.data
.header
.header
, DOORBELL_HDR_DB_TYPE
, 1);
5987 txdata
->tx_db
.data
.zero_fill1
= 0;
5988 txdata
->tx_db
.data
.prod
= 0;
5990 txdata
->tx_pkt_prod
= 0;
5991 txdata
->tx_pkt_cons
= 0;
5992 txdata
->tx_bd_prod
= 0;
5993 txdata
->tx_bd_cons
= 0;
5997 static void bnx2x_init_tx_rings_cnic(struct bnx2x
*bp
)
6001 for_each_tx_queue_cnic(bp
, i
)
6002 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[0]);
6004 static void bnx2x_init_tx_rings(struct bnx2x
*bp
)
6009 for_each_eth_queue(bp
, i
)
6010 for_each_cos_in_tx_queue(&bp
->fp
[i
], cos
)
6011 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[cos
]);
6014 void bnx2x_nic_init_cnic(struct bnx2x
*bp
)
6017 bnx2x_init_fcoe_fp(bp
);
6019 bnx2x_init_sb(bp
, bp
->cnic_sb_mapping
,
6020 BNX2X_VF_ID_INVALID
, false,
6021 bnx2x_cnic_fw_sb_id(bp
), bnx2x_cnic_igu_sb_id(bp
));
6023 /* ensure status block indices were read */
6025 bnx2x_init_rx_rings_cnic(bp
);
6026 bnx2x_init_tx_rings_cnic(bp
);
6033 void bnx2x_pre_irq_nic_init(struct bnx2x
*bp
)
6037 /* Setup NIC internals and enable interrupts */
6038 for_each_eth_queue(bp
, i
)
6039 bnx2x_init_eth_fp(bp
, i
);
6041 /* ensure status block indices were read */
6043 bnx2x_init_rx_rings(bp
);
6044 bnx2x_init_tx_rings(bp
);
6047 bnx2x_memset_stats(bp
);
6052 /* Initialize MOD_ABS interrupts */
6053 bnx2x_init_mod_abs_int(bp
, &bp
->link_vars
, bp
->common
.chip_id
,
6054 bp
->common
.shmem_base
,
6055 bp
->common
.shmem2_base
, BP_PORT(bp
));
6057 /* initialize the default status block and sp ring */
6058 bnx2x_init_def_sb(bp
);
6059 bnx2x_update_dsb_idx(bp
);
6060 bnx2x_init_sp_ring(bp
);
6064 void bnx2x_post_irq_nic_init(struct bnx2x
*bp
, u32 load_code
)
6066 bnx2x_init_eq_ring(bp
);
6067 bnx2x_init_internal(bp
, load_code
);
6069 bnx2x_stats_init(bp
);
6071 /* flush all before enabling interrupts */
6075 bnx2x_int_enable(bp
);
6077 /* Check for SPIO5 */
6078 bnx2x_attn_int_deasserted0(bp
,
6079 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ BP_PORT(bp
)*4) &
6080 AEU_INPUTS_ATTN_BITS_SPIO5
);
6083 /* gzip service functions */
6084 static int bnx2x_gunzip_init(struct bnx2x
*bp
)
6086 bp
->gunzip_buf
= dma_alloc_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
,
6087 &bp
->gunzip_mapping
, GFP_KERNEL
);
6088 if (bp
->gunzip_buf
== NULL
)
6091 bp
->strm
= kmalloc(sizeof(*bp
->strm
), GFP_KERNEL
);
6092 if (bp
->strm
== NULL
)
6095 bp
->strm
->workspace
= vmalloc(zlib_inflate_workspacesize());
6096 if (bp
->strm
->workspace
== NULL
)
6106 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6107 bp
->gunzip_mapping
);
6108 bp
->gunzip_buf
= NULL
;
6111 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6115 static void bnx2x_gunzip_end(struct bnx2x
*bp
)
6118 vfree(bp
->strm
->workspace
);
6123 if (bp
->gunzip_buf
) {
6124 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6125 bp
->gunzip_mapping
);
6126 bp
->gunzip_buf
= NULL
;
6130 static int bnx2x_gunzip(struct bnx2x
*bp
, const u8
*zbuf
, int len
)
6134 /* check gzip header */
6135 if ((zbuf
[0] != 0x1f) || (zbuf
[1] != 0x8b) || (zbuf
[2] != Z_DEFLATED
)) {
6136 BNX2X_ERR("Bad gzip header\n");
6144 if (zbuf
[3] & FNAME
)
6145 while ((zbuf
[n
++] != 0) && (n
< len
));
6147 bp
->strm
->next_in
= (typeof(bp
->strm
->next_in
))zbuf
+ n
;
6148 bp
->strm
->avail_in
= len
- n
;
6149 bp
->strm
->next_out
= bp
->gunzip_buf
;
6150 bp
->strm
->avail_out
= FW_BUF_SIZE
;
6152 rc
= zlib_inflateInit2(bp
->strm
, -MAX_WBITS
);
6156 rc
= zlib_inflate(bp
->strm
, Z_FINISH
);
6157 if ((rc
!= Z_OK
) && (rc
!= Z_STREAM_END
))
6158 netdev_err(bp
->dev
, "Firmware decompression error: %s\n",
6161 bp
->gunzip_outlen
= (FW_BUF_SIZE
- bp
->strm
->avail_out
);
6162 if (bp
->gunzip_outlen
& 0x3)
6164 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6166 bp
->gunzip_outlen
>>= 2;
6168 zlib_inflateEnd(bp
->strm
);
6170 if (rc
== Z_STREAM_END
)
6176 /* nic load/unload */
6179 * General service functions
6182 /* send a NIG loopback debug packet */
6183 static void bnx2x_lb_pckt(struct bnx2x
*bp
)
6187 /* Ethernet source and destination addresses */
6188 wb_write
[0] = 0x55555555;
6189 wb_write
[1] = 0x55555555;
6190 wb_write
[2] = 0x20; /* SOP */
6191 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6193 /* NON-IP protocol */
6194 wb_write
[0] = 0x09000000;
6195 wb_write
[1] = 0x55555555;
6196 wb_write
[2] = 0x10; /* EOP, eop_bvalid = 0 */
6197 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6200 /* some of the internal memories
6201 * are not directly readable from the driver
6202 * to test them we send debug packets
6204 static int bnx2x_int_mem_test(struct bnx2x
*bp
)
6210 if (CHIP_REV_IS_FPGA(bp
))
6212 else if (CHIP_REV_IS_EMUL(bp
))
6217 /* Disable inputs of parser neighbor blocks */
6218 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6219 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6220 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6221 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6223 /* Write 0 to parser credits for CFC search request */
6224 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6226 /* send Ethernet packet */
6229 /* TODO do i reset NIG statistic? */
6230 /* Wait until NIG register shows 1 packet of size 0x10 */
6231 count
= 1000 * factor
;
6234 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6235 val
= *bnx2x_sp(bp
, wb_data
[0]);
6243 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6247 /* Wait until PRS register shows 1 packet */
6248 count
= 1000 * factor
;
6250 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6258 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6262 /* Reset and init BRB, PRS */
6263 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6265 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6267 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6268 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6270 DP(NETIF_MSG_HW
, "part2\n");
6272 /* Disable inputs of parser neighbor blocks */
6273 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6274 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6275 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6276 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6278 /* Write 0 to parser credits for CFC search request */
6279 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6281 /* send 10 Ethernet packets */
6282 for (i
= 0; i
< 10; i
++)
6285 /* Wait until NIG register shows 10 + 1
6286 packets of size 11*0x10 = 0xb0 */
6287 count
= 1000 * factor
;
6290 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6291 val
= *bnx2x_sp(bp
, wb_data
[0]);
6299 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6303 /* Wait until PRS register shows 2 packets */
6304 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6306 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6308 /* Write 1 to parser credits for CFC search request */
6309 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x1);
6311 /* Wait until PRS register shows 3 packets */
6312 msleep(10 * factor
);
6313 /* Wait until NIG register shows 1 packet of size 0x10 */
6314 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6316 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6318 /* clear NIG EOP FIFO */
6319 for (i
= 0; i
< 11; i
++)
6320 REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_FIFO
);
6321 val
= REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_EMPTY
);
6323 BNX2X_ERR("clear of NIG failed\n");
6327 /* Reset and init BRB, PRS, NIG */
6328 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6330 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6332 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6333 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6334 if (!CNIC_SUPPORT(bp
))
6336 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
6338 /* Enable inputs of parser neighbor blocks */
6339 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x7fffffff);
6340 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x1);
6341 REG_WR(bp
, CFC_REG_DEBUG0
, 0x0);
6342 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x1);
6344 DP(NETIF_MSG_HW
, "done\n");
6349 static void bnx2x_enable_blocks_attention(struct bnx2x
*bp
)
6353 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
6354 if (!CHIP_IS_E1x(bp
))
6355 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0x40);
6357 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0);
6358 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6359 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6361 * mask read length error interrupts in brb for parser
6362 * (parsing unit and 'checksum and crc' unit)
6363 * these errors are legal (PU reads fixed length and CAC can cause
6364 * read length error on truncated packets)
6366 REG_WR(bp
, BRB1_REG_BRB1_INT_MASK
, 0xFC00);
6367 REG_WR(bp
, QM_REG_QM_INT_MASK
, 0);
6368 REG_WR(bp
, TM_REG_TM_INT_MASK
, 0);
6369 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_0
, 0);
6370 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_1
, 0);
6371 REG_WR(bp
, XCM_REG_XCM_INT_MASK
, 0);
6372 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6373 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6374 REG_WR(bp
, USDM_REG_USDM_INT_MASK_0
, 0);
6375 REG_WR(bp
, USDM_REG_USDM_INT_MASK_1
, 0);
6376 REG_WR(bp
, UCM_REG_UCM_INT_MASK
, 0);
6377 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6378 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6379 REG_WR(bp
, GRCBASE_UPB
+ PB_REG_PB_INT_MASK
, 0);
6380 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_0
, 0);
6381 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_1
, 0);
6382 REG_WR(bp
, CCM_REG_CCM_INT_MASK
, 0);
6383 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6384 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6386 val
= PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
|
6387 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
|
6388 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
;
6389 if (!CHIP_IS_E1x(bp
))
6390 val
|= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
|
6391 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
;
6392 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, val
);
6394 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_0
, 0);
6395 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_1
, 0);
6396 REG_WR(bp
, TCM_REG_TCM_INT_MASK
, 0);
6397 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6399 if (!CHIP_IS_E1x(bp
))
6400 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6401 REG_WR(bp
, TSEM_REG_TSEM_INT_MASK_1
, 0x07ff);
6403 REG_WR(bp
, CDU_REG_CDU_INT_MASK
, 0);
6404 REG_WR(bp
, DMAE_REG_DMAE_INT_MASK
, 0);
6405 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6406 REG_WR(bp
, PBF_REG_PBF_INT_MASK
, 0x18); /* bit 3,4 masked */
6409 static void bnx2x_reset_common(struct bnx2x
*bp
)
6414 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6417 if (CHIP_IS_E3(bp
)) {
6418 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
6419 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
6422 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
, val
);
6425 static void bnx2x_setup_dmae(struct bnx2x
*bp
)
6428 spin_lock_init(&bp
->dmae_lock
);
6431 static void bnx2x_init_pxp(struct bnx2x
*bp
)
6434 int r_order
, w_order
;
6436 pcie_capability_read_word(bp
->pdev
, PCI_EXP_DEVCTL
, &devctl
);
6437 DP(NETIF_MSG_HW
, "read 0x%x from devctl\n", devctl
);
6438 w_order
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
6440 r_order
= ((devctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
6442 DP(NETIF_MSG_HW
, "force read order to %d\n", bp
->mrrs
);
6446 bnx2x_init_pxp_arb(bp
, r_order
, w_order
);
6449 static void bnx2x_setup_fan_failure_detection(struct bnx2x
*bp
)
6459 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config2
) &
6460 SHARED_HW_CFG_FAN_FAILURE_MASK
;
6462 if (val
== SHARED_HW_CFG_FAN_FAILURE_ENABLED
)
6466 * The fan failure mechanism is usually related to the PHY type since
6467 * the power consumption of the board is affected by the PHY. Currently,
6468 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6470 else if (val
== SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE
)
6471 for (port
= PORT_0
; port
< PORT_MAX
; port
++) {
6473 bnx2x_fan_failure_det_req(
6475 bp
->common
.shmem_base
,
6476 bp
->common
.shmem2_base
,
6480 DP(NETIF_MSG_HW
, "fan detection setting: %d\n", is_required
);
6482 if (is_required
== 0)
6485 /* Fan failure is indicated by SPIO 5 */
6486 bnx2x_set_spio(bp
, MISC_SPIO_SPIO5
, MISC_SPIO_INPUT_HI_Z
);
6488 /* set to active low mode */
6489 val
= REG_RD(bp
, MISC_REG_SPIO_INT
);
6490 val
|= (MISC_SPIO_SPIO5
<< MISC_SPIO_INT_OLD_SET_POS
);
6491 REG_WR(bp
, MISC_REG_SPIO_INT
, val
);
6493 /* enable interrupt to signal the IGU */
6494 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
6495 val
|= MISC_SPIO_SPIO5
;
6496 REG_WR(bp
, MISC_REG_SPIO_EVENT_EN
, val
);
6499 void bnx2x_pf_disable(struct bnx2x
*bp
)
6501 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
6502 val
&= ~IGU_PF_CONF_FUNC_EN
;
6504 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
6505 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
6506 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 0);
6509 static void bnx2x__common_init_phy(struct bnx2x
*bp
)
6511 u32 shmem_base
[2], shmem2_base
[2];
6512 /* Avoid common init in case MFW supports LFA */
6513 if (SHMEM2_RD(bp
, size
) >
6514 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
6516 shmem_base
[0] = bp
->common
.shmem_base
;
6517 shmem2_base
[0] = bp
->common
.shmem2_base
;
6518 if (!CHIP_IS_E1x(bp
)) {
6520 SHMEM2_RD(bp
, other_shmem_base_addr
);
6522 SHMEM2_RD(bp
, other_shmem2_base_addr
);
6524 bnx2x_acquire_phy_lock(bp
);
6525 bnx2x_common_init_phy(bp
, shmem_base
, shmem2_base
,
6526 bp
->common
.chip_id
);
6527 bnx2x_release_phy_lock(bp
);
6531 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6533 * @bp: driver handle
6535 static int bnx2x_init_hw_common(struct bnx2x
*bp
)
6539 DP(NETIF_MSG_HW
, "starting common init func %d\n", BP_ABS_FUNC(bp
));
6542 * take the RESET lock to protect undi_unload flow from accessing
6543 * registers while we're resetting the chip
6545 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
6547 bnx2x_reset_common(bp
);
6548 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0xffffffff);
6551 if (CHIP_IS_E3(bp
)) {
6552 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
6553 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
6555 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
, val
);
6557 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
6559 bnx2x_init_block(bp
, BLOCK_MISC
, PHASE_COMMON
);
6561 if (!CHIP_IS_E1x(bp
)) {
6565 * 4-port mode or 2-port mode we need to turn of master-enable
6566 * for everyone, after that, turn it back on for self.
6567 * so, we disregard multi-function or not, and always disable
6568 * for all functions on the given path, this means 0,2,4,6 for
6569 * path 0 and 1,3,5,7 for path 1
6571 for (abs_func_id
= BP_PATH(bp
);
6572 abs_func_id
< E2_FUNC_MAX
*2; abs_func_id
+= 2) {
6573 if (abs_func_id
== BP_ABS_FUNC(bp
)) {
6575 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
,
6580 bnx2x_pretend_func(bp
, abs_func_id
);
6581 /* clear pf enable */
6582 bnx2x_pf_disable(bp
);
6583 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
6587 bnx2x_init_block(bp
, BLOCK_PXP
, PHASE_COMMON
);
6588 if (CHIP_IS_E1(bp
)) {
6589 /* enable HW interrupt from PXP on USDM overflow
6590 bit 16 on INT_MASK_0 */
6591 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
6594 bnx2x_init_block(bp
, BLOCK_PXP2
, PHASE_COMMON
);
6598 REG_WR(bp
, PXP2_REG_RQ_QM_ENDIAN_M
, 1);
6599 REG_WR(bp
, PXP2_REG_RQ_TM_ENDIAN_M
, 1);
6600 REG_WR(bp
, PXP2_REG_RQ_SRC_ENDIAN_M
, 1);
6601 REG_WR(bp
, PXP2_REG_RQ_CDU_ENDIAN_M
, 1);
6602 REG_WR(bp
, PXP2_REG_RQ_DBG_ENDIAN_M
, 1);
6603 /* make sure this value is 0 */
6604 REG_WR(bp
, PXP2_REG_RQ_HC_ENDIAN_M
, 0);
6606 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6607 REG_WR(bp
, PXP2_REG_RD_QM_SWAP_MODE
, 1);
6608 REG_WR(bp
, PXP2_REG_RD_TM_SWAP_MODE
, 1);
6609 REG_WR(bp
, PXP2_REG_RD_SRC_SWAP_MODE
, 1);
6610 REG_WR(bp
, PXP2_REG_RD_CDURD_SWAP_MODE
, 1);
6613 bnx2x_ilt_init_page_size(bp
, INITOP_SET
);
6615 if (CHIP_REV_IS_FPGA(bp
) && CHIP_IS_E1H(bp
))
6616 REG_WR(bp
, PXP2_REG_PGL_TAGS_LIMIT
, 0x1);
6618 /* let the HW do it's magic ... */
6620 /* finish PXP init */
6621 val
= REG_RD(bp
, PXP2_REG_RQ_CFG_DONE
);
6623 BNX2X_ERR("PXP2 CFG failed\n");
6626 val
= REG_RD(bp
, PXP2_REG_RD_INIT_DONE
);
6628 BNX2X_ERR("PXP2 RD_INIT failed\n");
6632 /* Timers bug workaround E2 only. We need to set the entire ILT to
6633 * have entries with value "0" and valid bit on.
6634 * This needs to be done by the first PF that is loaded in a path
6635 * (i.e. common phase)
6637 if (!CHIP_IS_E1x(bp
)) {
6638 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6639 * (i.e. vnic3) to start even if it is marked as "scan-off".
6640 * This occurs when a different function (func2,3) is being marked
6641 * as "scan-off". Real-life scenario for example: if a driver is being
6642 * load-unloaded while func6,7 are down. This will cause the timer to access
6643 * the ilt, translate to a logical address and send a request to read/write.
6644 * Since the ilt for the function that is down is not valid, this will cause
6645 * a translation error which is unrecoverable.
6646 * The Workaround is intended to make sure that when this happens nothing fatal
6647 * will occur. The workaround:
6648 * 1. First PF driver which loads on a path will:
6649 * a. After taking the chip out of reset, by using pretend,
6650 * it will write "0" to the following registers of
6652 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6653 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6654 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6655 * And for itself it will write '1' to
6656 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6657 * dmae-operations (writing to pram for example.)
6658 * note: can be done for only function 6,7 but cleaner this
6660 * b. Write zero+valid to the entire ILT.
6661 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6662 * VNIC3 (of that port). The range allocated will be the
6663 * entire ILT. This is needed to prevent ILT range error.
6664 * 2. Any PF driver load flow:
6665 * a. ILT update with the physical addresses of the allocated
6667 * b. Wait 20msec. - note that this timeout is needed to make
6668 * sure there are no requests in one of the PXP internal
6669 * queues with "old" ILT addresses.
6670 * c. PF enable in the PGLC.
6671 * d. Clear the was_error of the PF in the PGLC. (could have
6672 * occurred while driver was down)
6673 * e. PF enable in the CFC (WEAK + STRONG)
6674 * f. Timers scan enable
6675 * 3. PF driver unload flow:
6676 * a. Clear the Timers scan_en.
6677 * b. Polling for scan_on=0 for that PF.
6678 * c. Clear the PF enable bit in the PXP.
6679 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6680 * e. Write zero+valid to all ILT entries (The valid bit must
6682 * f. If this is VNIC 3 of a port then also init
6683 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6684 * to the last enrty in the ILT.
6687 * Currently the PF error in the PGLC is non recoverable.
6688 * In the future the there will be a recovery routine for this error.
6689 * Currently attention is masked.
6690 * Having an MCP lock on the load/unload process does not guarantee that
6691 * there is no Timer disable during Func6/7 enable. This is because the
6692 * Timers scan is currently being cleared by the MCP on FLR.
6693 * Step 2.d can be done only for PF6/7 and the driver can also check if
6694 * there is error before clearing it. But the flow above is simpler and
6696 * All ILT entries are written by zero+valid and not just PF6/7
6697 * ILT entries since in the future the ILT entries allocation for
6698 * PF-s might be dynamic.
6700 struct ilt_client_info ilt_cli
;
6701 struct bnx2x_ilt ilt
;
6702 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
6703 memset(&ilt
, 0, sizeof(struct bnx2x_ilt
));
6705 /* initialize dummy TM client */
6707 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
6708 ilt_cli
.client_num
= ILT_CLIENT_TM
;
6710 /* Step 1: set zeroes to all ilt page entries with valid bit on
6711 * Step 2: set the timers first/last ilt entry to point
6712 * to the entire range to prevent ILT range error for 3rd/4th
6713 * vnic (this code assumes existence of the vnic)
6715 * both steps performed by call to bnx2x_ilt_client_init_op()
6716 * with dummy TM client
6718 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6719 * and his brother are split registers
6721 bnx2x_pretend_func(bp
, (BP_PATH(bp
) + 6));
6722 bnx2x_ilt_client_init_op_ilt(bp
, &ilt
, &ilt_cli
, INITOP_CLEAR
);
6723 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
6725 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN
, BNX2X_PXP_DRAM_ALIGN
);
6726 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_RD
, BNX2X_PXP_DRAM_ALIGN
);
6727 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_SEL
, 1);
6730 REG_WR(bp
, PXP2_REG_RQ_DISABLE_INPUTS
, 0);
6731 REG_WR(bp
, PXP2_REG_RD_DISABLE_INPUTS
, 0);
6733 if (!CHIP_IS_E1x(bp
)) {
6734 int factor
= CHIP_REV_IS_EMUL(bp
) ? 1000 :
6735 (CHIP_REV_IS_FPGA(bp
) ? 400 : 0);
6736 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, PHASE_COMMON
);
6738 bnx2x_init_block(bp
, BLOCK_ATC
, PHASE_COMMON
);
6740 /* let the HW do it's magic ... */
6743 val
= REG_RD(bp
, ATC_REG_ATC_INIT_DONE
);
6744 } while (factor
-- && (val
!= 1));
6747 BNX2X_ERR("ATC_INIT failed\n");
6752 bnx2x_init_block(bp
, BLOCK_DMAE
, PHASE_COMMON
);
6754 bnx2x_iov_init_dmae(bp
);
6756 /* clean the DMAE memory */
6758 bnx2x_init_fill(bp
, TSEM_REG_PRAM
, 0, 8, 1);
6760 bnx2x_init_block(bp
, BLOCK_TCM
, PHASE_COMMON
);
6762 bnx2x_init_block(bp
, BLOCK_UCM
, PHASE_COMMON
);
6764 bnx2x_init_block(bp
, BLOCK_CCM
, PHASE_COMMON
);
6766 bnx2x_init_block(bp
, BLOCK_XCM
, PHASE_COMMON
);
6768 bnx2x_read_dmae(bp
, XSEM_REG_PASSIVE_BUFFER
, 3);
6769 bnx2x_read_dmae(bp
, CSEM_REG_PASSIVE_BUFFER
, 3);
6770 bnx2x_read_dmae(bp
, TSEM_REG_PASSIVE_BUFFER
, 3);
6771 bnx2x_read_dmae(bp
, USEM_REG_PASSIVE_BUFFER
, 3);
6773 bnx2x_init_block(bp
, BLOCK_QM
, PHASE_COMMON
);
6776 /* QM queues pointers table */
6777 bnx2x_qm_init_ptr_table(bp
, bp
->qm_cid_count
, INITOP_SET
);
6779 /* soft reset pulse */
6780 REG_WR(bp
, QM_REG_SOFT_RESET
, 1);
6781 REG_WR(bp
, QM_REG_SOFT_RESET
, 0);
6783 if (CNIC_SUPPORT(bp
))
6784 bnx2x_init_block(bp
, BLOCK_TM
, PHASE_COMMON
);
6786 bnx2x_init_block(bp
, BLOCK_DORQ
, PHASE_COMMON
);
6787 REG_WR(bp
, DORQ_REG_DPM_CID_OFST
, BNX2X_DB_SHIFT
);
6788 if (!CHIP_REV_IS_SLOW(bp
))
6789 /* enable hw interrupt from doorbell Q */
6790 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6792 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6794 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6795 REG_WR(bp
, PRS_REG_A_PRSU_20
, 0xf);
6797 if (!CHIP_IS_E1(bp
))
6798 REG_WR(bp
, PRS_REG_E1HOV_MODE
, bp
->path_has_ovlan
);
6800 if (!CHIP_IS_E1x(bp
) && !CHIP_IS_E3B0(bp
)) {
6801 if (IS_MF_AFEX(bp
)) {
6802 /* configure that VNTag and VLAN headers must be
6803 * received in afex mode
6805 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
, 0xE);
6806 REG_WR(bp
, PRS_REG_MUST_HAVE_HDRS
, 0xA);
6807 REG_WR(bp
, PRS_REG_HDRS_AFTER_TAG_0
, 0x6);
6808 REG_WR(bp
, PRS_REG_TAG_ETHERTYPE_0
, 0x8926);
6809 REG_WR(bp
, PRS_REG_TAG_LEN_0
, 0x4);
6811 /* Bit-map indicating which L2 hdrs may appear
6812 * after the basic Ethernet header
6814 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
,
6815 bp
->path_has_ovlan
? 7 : 6);
6819 bnx2x_init_block(bp
, BLOCK_TSDM
, PHASE_COMMON
);
6820 bnx2x_init_block(bp
, BLOCK_CSDM
, PHASE_COMMON
);
6821 bnx2x_init_block(bp
, BLOCK_USDM
, PHASE_COMMON
);
6822 bnx2x_init_block(bp
, BLOCK_XSDM
, PHASE_COMMON
);
6824 if (!CHIP_IS_E1x(bp
)) {
6825 /* reset VFC memories */
6826 REG_WR(bp
, TSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6827 VFC_MEMORIES_RST_REG_CAM_RST
|
6828 VFC_MEMORIES_RST_REG_RAM_RST
);
6829 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6830 VFC_MEMORIES_RST_REG_CAM_RST
|
6831 VFC_MEMORIES_RST_REG_RAM_RST
);
6836 bnx2x_init_block(bp
, BLOCK_TSEM
, PHASE_COMMON
);
6837 bnx2x_init_block(bp
, BLOCK_USEM
, PHASE_COMMON
);
6838 bnx2x_init_block(bp
, BLOCK_CSEM
, PHASE_COMMON
);
6839 bnx2x_init_block(bp
, BLOCK_XSEM
, PHASE_COMMON
);
6842 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6844 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
6847 bnx2x_init_block(bp
, BLOCK_UPB
, PHASE_COMMON
);
6848 bnx2x_init_block(bp
, BLOCK_XPB
, PHASE_COMMON
);
6849 bnx2x_init_block(bp
, BLOCK_PBF
, PHASE_COMMON
);
6851 if (!CHIP_IS_E1x(bp
)) {
6852 if (IS_MF_AFEX(bp
)) {
6853 /* configure that VNTag and VLAN headers must be
6856 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
, 0xE);
6857 REG_WR(bp
, PBF_REG_MUST_HAVE_HDRS
, 0xA);
6858 REG_WR(bp
, PBF_REG_HDRS_AFTER_TAG_0
, 0x6);
6859 REG_WR(bp
, PBF_REG_TAG_ETHERTYPE_0
, 0x8926);
6860 REG_WR(bp
, PBF_REG_TAG_LEN_0
, 0x4);
6862 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
,
6863 bp
->path_has_ovlan
? 7 : 6);
6867 REG_WR(bp
, SRC_REG_SOFT_RST
, 1);
6869 bnx2x_init_block(bp
, BLOCK_SRC
, PHASE_COMMON
);
6871 if (CNIC_SUPPORT(bp
)) {
6872 REG_WR(bp
, SRC_REG_KEYSEARCH_0
, 0x63285672);
6873 REG_WR(bp
, SRC_REG_KEYSEARCH_1
, 0x24b8f2cc);
6874 REG_WR(bp
, SRC_REG_KEYSEARCH_2
, 0x223aef9b);
6875 REG_WR(bp
, SRC_REG_KEYSEARCH_3
, 0x26001e3a);
6876 REG_WR(bp
, SRC_REG_KEYSEARCH_4
, 0x7ae91116);
6877 REG_WR(bp
, SRC_REG_KEYSEARCH_5
, 0x5ce5230b);
6878 REG_WR(bp
, SRC_REG_KEYSEARCH_6
, 0x298d8adf);
6879 REG_WR(bp
, SRC_REG_KEYSEARCH_7
, 0x6eb0ff09);
6880 REG_WR(bp
, SRC_REG_KEYSEARCH_8
, 0x1830f82f);
6881 REG_WR(bp
, SRC_REG_KEYSEARCH_9
, 0x01e46be7);
6883 REG_WR(bp
, SRC_REG_SOFT_RST
, 0);
6885 if (sizeof(union cdu_context
) != 1024)
6886 /* we currently assume that a context is 1024 bytes */
6887 dev_alert(&bp
->pdev
->dev
,
6888 "please adjust the size of cdu_context(%ld)\n",
6889 (long)sizeof(union cdu_context
));
6891 bnx2x_init_block(bp
, BLOCK_CDU
, PHASE_COMMON
);
6892 val
= (4 << 24) + (0 << 12) + 1024;
6893 REG_WR(bp
, CDU_REG_CDU_GLOBAL_PARAMS
, val
);
6895 bnx2x_init_block(bp
, BLOCK_CFC
, PHASE_COMMON
);
6896 REG_WR(bp
, CFC_REG_INIT_REG
, 0x7FF);
6897 /* enable context validation interrupt from CFC */
6898 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6900 /* set the thresholds to prevent CFC/CDU race */
6901 REG_WR(bp
, CFC_REG_DEBUG0
, 0x20020000);
6903 bnx2x_init_block(bp
, BLOCK_HC
, PHASE_COMMON
);
6905 if (!CHIP_IS_E1x(bp
) && BP_NOMCP(bp
))
6906 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x36);
6908 bnx2x_init_block(bp
, BLOCK_IGU
, PHASE_COMMON
);
6909 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, PHASE_COMMON
);
6911 /* Reset PCIE errors for debug */
6912 REG_WR(bp
, 0x2814, 0xffffffff);
6913 REG_WR(bp
, 0x3820, 0xffffffff);
6915 if (!CHIP_IS_E1x(bp
)) {
6916 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_CONTROL_5
,
6917 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
|
6918 PXPCS_TL_CONTROL_5_ERR_UNSPPORT
));
6919 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC345_STAT
,
6920 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
|
6921 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
|
6922 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
));
6923 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC678_STAT
,
6924 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
|
6925 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
|
6926 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
));
6929 bnx2x_init_block(bp
, BLOCK_NIG
, PHASE_COMMON
);
6930 if (!CHIP_IS_E1(bp
)) {
6931 /* in E3 this done in per-port section */
6932 if (!CHIP_IS_E3(bp
))
6933 REG_WR(bp
, NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
6935 if (CHIP_IS_E1H(bp
))
6936 /* not applicable for E2 (and above ...) */
6937 REG_WR(bp
, NIG_REG_LLH_E1HOV_MODE
, IS_MF_SD(bp
));
6939 if (CHIP_REV_IS_SLOW(bp
))
6942 /* finish CFC init */
6943 val
= reg_poll(bp
, CFC_REG_LL_INIT_DONE
, 1, 100, 10);
6945 BNX2X_ERR("CFC LL_INIT failed\n");
6948 val
= reg_poll(bp
, CFC_REG_AC_INIT_DONE
, 1, 100, 10);
6950 BNX2X_ERR("CFC AC_INIT failed\n");
6953 val
= reg_poll(bp
, CFC_REG_CAM_INIT_DONE
, 1, 100, 10);
6955 BNX2X_ERR("CFC CAM_INIT failed\n");
6958 REG_WR(bp
, CFC_REG_DEBUG0
, 0);
6960 if (CHIP_IS_E1(bp
)) {
6961 /* read NIG statistic
6962 to see if this is our first up since powerup */
6963 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6964 val
= *bnx2x_sp(bp
, wb_data
[0]);
6966 /* do internal memory self test */
6967 if ((val
== 0) && bnx2x_int_mem_test(bp
)) {
6968 BNX2X_ERR("internal mem self test failed\n");
6973 bnx2x_setup_fan_failure_detection(bp
);
6975 /* clear PXP2 attentions */
6976 REG_RD(bp
, PXP2_REG_PXP2_INT_STS_CLR_0
);
6978 bnx2x_enable_blocks_attention(bp
);
6979 bnx2x_enable_blocks_parity(bp
);
6981 if (!BP_NOMCP(bp
)) {
6982 if (CHIP_IS_E1x(bp
))
6983 bnx2x__common_init_phy(bp
);
6985 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6991 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6993 * @bp: driver handle
6995 static int bnx2x_init_hw_common_chip(struct bnx2x
*bp
)
6997 int rc
= bnx2x_init_hw_common(bp
);
7002 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7004 bnx2x__common_init_phy(bp
);
7009 static int bnx2x_init_hw_port(struct bnx2x
*bp
)
7011 int port
= BP_PORT(bp
);
7012 int init_phase
= port
? PHASE_PORT1
: PHASE_PORT0
;
7017 DP(NETIF_MSG_HW
, "starting port init port %d\n", port
);
7019 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
7021 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
7022 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
7023 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
7025 /* Timers bug workaround: disables the pf_master bit in pglue at
7026 * common phase, we need to enable it here before any dmae access are
7027 * attempted. Therefore we manually added the enable-master to the
7028 * port phase (it also happens in the function phase)
7030 if (!CHIP_IS_E1x(bp
))
7031 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
7033 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
7034 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
7035 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
7036 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
7038 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
7039 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
7040 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
7041 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
7043 /* QM cid (connection) count */
7044 bnx2x_qm_init_cid_count(bp
, bp
->qm_cid_count
, INITOP_SET
);
7046 if (CNIC_SUPPORT(bp
)) {
7047 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
7048 REG_WR(bp
, TM_REG_LIN0_SCAN_TIME
+ port
*4, 20);
7049 REG_WR(bp
, TM_REG_LIN0_MAX_ACTIVE_CID
+ port
*4, 31);
7052 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
7054 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
7056 if (CHIP_IS_E1(bp
) || CHIP_IS_E1H(bp
)) {
7059 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 160 : 246);
7060 else if (bp
->dev
->mtu
> 4096) {
7061 if (bp
->flags
& ONE_PORT_FLAG
)
7065 /* (24*1024 + val*4)/256 */
7066 low
= 96 + (val
/64) +
7067 ((val
% 64) ? 1 : 0);
7070 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 80 : 160);
7071 high
= low
+ 56; /* 14*1024/256 */
7072 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_0
+ port
*4, low
);
7073 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_0
+ port
*4, high
);
7076 if (CHIP_MODE_IS_4_PORT(bp
))
7077 REG_WR(bp
, (BP_PORT(bp
) ?
7078 BRB1_REG_MAC_GUARANTIED_1
:
7079 BRB1_REG_MAC_GUARANTIED_0
), 40);
7082 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
7083 if (CHIP_IS_E3B0(bp
)) {
7084 if (IS_MF_AFEX(bp
)) {
7085 /* configure headers for AFEX mode */
7086 REG_WR(bp
, BP_PORT(bp
) ?
7087 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7088 PRS_REG_HDRS_AFTER_BASIC_PORT_0
, 0xE);
7089 REG_WR(bp
, BP_PORT(bp
) ?
7090 PRS_REG_HDRS_AFTER_TAG_0_PORT_1
:
7091 PRS_REG_HDRS_AFTER_TAG_0_PORT_0
, 0x6);
7092 REG_WR(bp
, BP_PORT(bp
) ?
7093 PRS_REG_MUST_HAVE_HDRS_PORT_1
:
7094 PRS_REG_MUST_HAVE_HDRS_PORT_0
, 0xA);
7096 /* Ovlan exists only if we are in multi-function +
7097 * switch-dependent mode, in switch-independent there
7098 * is no ovlan headers
7100 REG_WR(bp
, BP_PORT(bp
) ?
7101 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7102 PRS_REG_HDRS_AFTER_BASIC_PORT_0
,
7103 (bp
->path_has_ovlan
? 7 : 6));
7107 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
7108 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
7109 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
7110 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
7112 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
7113 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
7114 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
7115 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
7117 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
7118 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
7120 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
7122 if (CHIP_IS_E1x(bp
)) {
7123 /* configure PBF to work without PAUSE mtu 9000 */
7124 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
7126 /* update threshold */
7127 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, (9040/16));
7128 /* update init credit */
7129 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, (9040/16) + 553 - 22);
7132 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 1);
7134 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0);
7137 if (CNIC_SUPPORT(bp
))
7138 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
7140 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
7141 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
7143 if (CHIP_IS_E1(bp
)) {
7144 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7145 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7147 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
7149 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
7151 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
7152 /* init aeu_mask_attn_func_0/1:
7153 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7154 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7155 * bits 4-7 are used for "per vn group attention" */
7156 val
= IS_MF(bp
) ? 0xF7 : 0x7;
7157 /* Enable DCBX attention for all but E1 */
7158 val
|= CHIP_IS_E1(bp
) ? 0 : 0x10;
7159 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, val
);
7161 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
7163 if (!CHIP_IS_E1x(bp
)) {
7164 /* Bit-map indicating which L2 hdrs may appear after the
7165 * basic Ethernet header
7168 REG_WR(bp
, BP_PORT(bp
) ?
7169 NIG_REG_P1_HDRS_AFTER_BASIC
:
7170 NIG_REG_P0_HDRS_AFTER_BASIC
, 0xE);
7172 REG_WR(bp
, BP_PORT(bp
) ?
7173 NIG_REG_P1_HDRS_AFTER_BASIC
:
7174 NIG_REG_P0_HDRS_AFTER_BASIC
,
7175 IS_MF_SD(bp
) ? 7 : 6);
7178 REG_WR(bp
, BP_PORT(bp
) ?
7179 NIG_REG_LLH1_MF_MODE
:
7180 NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
7182 if (!CHIP_IS_E3(bp
))
7183 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
7185 if (!CHIP_IS_E1(bp
)) {
7186 /* 0x2 disable mf_ov, 0x1 enable */
7187 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ port
*4,
7188 (IS_MF_SD(bp
) ? 0x1 : 0x2));
7190 if (!CHIP_IS_E1x(bp
)) {
7192 switch (bp
->mf_mode
) {
7193 case MULTI_FUNCTION_SD
:
7196 case MULTI_FUNCTION_SI
:
7197 case MULTI_FUNCTION_AFEX
:
7202 REG_WR(bp
, (BP_PORT(bp
) ? NIG_REG_LLH1_CLS_TYPE
:
7203 NIG_REG_LLH0_CLS_TYPE
), val
);
7206 REG_WR(bp
, NIG_REG_LLFC_ENABLE_0
+ port
*4, 0);
7207 REG_WR(bp
, NIG_REG_LLFC_OUT_EN_0
+ port
*4, 0);
7208 REG_WR(bp
, NIG_REG_PAUSE_ENABLE_0
+ port
*4, 1);
7212 /* If SPIO5 is set to generate interrupts, enable it for this port */
7213 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
7214 if (val
& MISC_SPIO_SPIO5
) {
7215 u32 reg_addr
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
7216 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
7217 val
= REG_RD(bp
, reg_addr
);
7218 val
|= AEU_INPUTS_ATTN_BITS_SPIO5
;
7219 REG_WR(bp
, reg_addr
, val
);
7225 static void bnx2x_ilt_wr(struct bnx2x
*bp
, u32 index
, dma_addr_t addr
)
7231 reg
= PXP2_REG_RQ_ONCHIP_AT
+ index
*8;
7233 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ index
*8;
7235 wb_write
[0] = ONCHIP_ADDR1(addr
);
7236 wb_write
[1] = ONCHIP_ADDR2(addr
);
7237 REG_WR_DMAE(bp
, reg
, wb_write
, 2);
7240 void bnx2x_igu_clear_sb_gen(struct bnx2x
*bp
, u8 func
, u8 idu_sb_id
, bool is_pf
)
7242 u32 data
, ctl
, cnt
= 100;
7243 u32 igu_addr_data
= IGU_REG_COMMAND_REG_32LSB_DATA
;
7244 u32 igu_addr_ctl
= IGU_REG_COMMAND_REG_CTRL
;
7245 u32 igu_addr_ack
= IGU_REG_CSTORM_TYPE_0_SB_CLEANUP
+ (idu_sb_id
/32)*4;
7246 u32 sb_bit
= 1 << (idu_sb_id
%32);
7247 u32 func_encode
= func
| (is_pf
? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT
;
7248 u32 addr_encode
= IGU_CMD_E2_PROD_UPD_BASE
+ idu_sb_id
;
7250 /* Not supported in BC mode */
7251 if (CHIP_INT_MODE_IS_BC(bp
))
7254 data
= (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7255 << IGU_REGULAR_CLEANUP_TYPE_SHIFT
) |
7256 IGU_REGULAR_CLEANUP_SET
|
7257 IGU_REGULAR_BCLEANUP
;
7259 ctl
= addr_encode
<< IGU_CTRL_REG_ADDRESS_SHIFT
|
7260 func_encode
<< IGU_CTRL_REG_FID_SHIFT
|
7261 IGU_CTRL_CMD_TYPE_WR
<< IGU_CTRL_REG_TYPE_SHIFT
;
7263 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7264 data
, igu_addr_data
);
7265 REG_WR(bp
, igu_addr_data
, data
);
7268 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7270 REG_WR(bp
, igu_addr_ctl
, ctl
);
7274 /* wait for clean up to finish */
7275 while (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
) && --cnt
)
7279 if (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
)) {
7281 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7282 idu_sb_id
, idu_sb_id
/32, idu_sb_id
%32, cnt
);
7286 static void bnx2x_igu_clear_sb(struct bnx2x
*bp
, u8 idu_sb_id
)
7288 bnx2x_igu_clear_sb_gen(bp
, BP_FUNC(bp
), idu_sb_id
, true /*PF*/);
7291 static void bnx2x_clear_func_ilt(struct bnx2x
*bp
, u32 func
)
7293 u32 i
, base
= FUNC_ILT_BASE(func
);
7294 for (i
= base
; i
< base
+ ILT_PER_FUNC
; i
++)
7295 bnx2x_ilt_wr(bp
, i
, 0);
7299 static void bnx2x_init_searcher(struct bnx2x
*bp
)
7301 int port
= BP_PORT(bp
);
7302 bnx2x_src_init_t2(bp
, bp
->t2
, bp
->t2_mapping
, SRC_CONN_NUM
);
7303 /* T1 hash bits value determines the T1 number of entries */
7304 REG_WR(bp
, SRC_REG_NUMBER_HASH_BITS0
+ port
*4, SRC_HASH_BITS
);
7307 static inline int bnx2x_func_switch_update(struct bnx2x
*bp
, int suspend
)
7310 struct bnx2x_func_state_params func_params
= {NULL
};
7311 struct bnx2x_func_switch_update_params
*switch_update_params
=
7312 &func_params
.params
.switch_update
;
7314 /* Prepare parameters for function state transitions */
7315 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7316 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
7318 func_params
.f_obj
= &bp
->func_obj
;
7319 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
7321 /* Function parameters */
7322 switch_update_params
->suspend
= suspend
;
7324 rc
= bnx2x_func_state_change(bp
, &func_params
);
7329 static int bnx2x_reset_nic_mode(struct bnx2x
*bp
)
7331 int rc
, i
, port
= BP_PORT(bp
);
7332 int vlan_en
= 0, mac_en
[NUM_MACS
];
7335 /* Close input from network */
7336 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7337 bnx2x_set_rx_filter(&bp
->link_params
, 0);
7339 vlan_en
= REG_RD(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7340 NIG_REG_LLH0_FUNC_EN
);
7341 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7342 NIG_REG_LLH0_FUNC_EN
, 0);
7343 for (i
= 0; i
< NUM_MACS
; i
++) {
7344 mac_en
[i
] = REG_RD(bp
, port
?
7345 (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7347 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+
7349 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7351 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
), 0);
7355 /* Close BMC to host */
7356 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7357 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 0);
7359 /* Suspend Tx switching to the PF. Completion of this ramrod
7360 * further guarantees that all the packets of that PF / child
7361 * VFs in BRB were processed by the Parser, so it is safe to
7362 * change the NIC_MODE register.
7364 rc
= bnx2x_func_switch_update(bp
, 1);
7366 BNX2X_ERR("Can't suspend tx-switching!\n");
7370 /* Change NIC_MODE register */
7371 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7373 /* Open input from network */
7374 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7375 bnx2x_set_rx_filter(&bp
->link_params
, 1);
7377 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7378 NIG_REG_LLH0_FUNC_EN
, vlan_en
);
7379 for (i
= 0; i
< NUM_MACS
; i
++) {
7380 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7382 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
),
7387 /* Enable BMC to host */
7388 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7389 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 1);
7391 /* Resume Tx switching to the PF */
7392 rc
= bnx2x_func_switch_update(bp
, 0);
7394 BNX2X_ERR("Can't resume tx-switching!\n");
7398 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7402 int bnx2x_init_hw_func_cnic(struct bnx2x
*bp
)
7406 bnx2x_ilt_init_op_cnic(bp
, INITOP_SET
);
7408 if (CONFIGURE_NIC_MODE(bp
)) {
7409 /* Configrue searcher as part of function hw init */
7410 bnx2x_init_searcher(bp
);
7412 /* Reset NIC mode */
7413 rc
= bnx2x_reset_nic_mode(bp
);
7415 BNX2X_ERR("Can't change NIC mode!\n");
7422 static int bnx2x_init_hw_func(struct bnx2x
*bp
)
7424 int port
= BP_PORT(bp
);
7425 int func
= BP_FUNC(bp
);
7426 int init_phase
= PHASE_PF0
+ func
;
7427 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
7430 u32 main_mem_base
, main_mem_size
, main_mem_prty_clr
;
7431 int i
, main_mem_width
, rc
;
7433 DP(NETIF_MSG_HW
, "starting func init func %d\n", func
);
7435 /* FLR cleanup - hmmm */
7436 if (!CHIP_IS_E1x(bp
)) {
7437 rc
= bnx2x_pf_flr_clnup(bp
);
7444 /* set MSI reconfigure capability */
7445 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7446 addr
= (port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
);
7447 val
= REG_RD(bp
, addr
);
7448 val
|= HC_CONFIG_0_REG_MSI_ATTN_EN_0
;
7449 REG_WR(bp
, addr
, val
);
7452 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
7453 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
7456 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7459 cdu_ilt_start
+= BNX2X_FIRST_VF_CID
/ILT_PAGE_CIDS
;
7460 cdu_ilt_start
= bnx2x_iov_init_ilt(bp
, cdu_ilt_start
);
7462 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7463 * those of the VFs, so start line should be reset
7465 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7466 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++) {
7467 ilt
->lines
[cdu_ilt_start
+ i
].page
= bp
->context
[i
].vcxt
;
7468 ilt
->lines
[cdu_ilt_start
+ i
].page_mapping
=
7469 bp
->context
[i
].cxt_mapping
;
7470 ilt
->lines
[cdu_ilt_start
+ i
].size
= bp
->context
[i
].size
;
7473 bnx2x_ilt_init_op(bp
, INITOP_SET
);
7475 if (!CONFIGURE_NIC_MODE(bp
)) {
7476 bnx2x_init_searcher(bp
);
7477 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7478 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7481 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
7482 DP(NETIF_MSG_IFUP
, "NIC MODE configrued\n");
7486 if (!CHIP_IS_E1x(bp
)) {
7487 u32 pf_conf
= IGU_PF_CONF_FUNC_EN
;
7489 /* Turn on a single ISR mode in IGU if driver is going to use
7492 if (!(bp
->flags
& USING_MSIX_FLAG
))
7493 pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
7495 * Timers workaround bug: function init part.
7496 * Need to wait 20msec after initializing ILT,
7497 * needed to make sure there are no requests in
7498 * one of the PXP internal queues with "old" ILT addresses
7502 * Master enable - Due to WB DMAE writes performed before this
7503 * register is re-initialized as part of the regular function
7506 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
7507 /* Enable the function in IGU */
7508 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, pf_conf
);
7513 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
7515 if (!CHIP_IS_E1x(bp
))
7516 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
, func
);
7518 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
7519 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
7520 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
7521 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
7522 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
7523 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
7524 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
7525 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
7526 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
7527 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
7528 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
7529 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
7530 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
7532 if (!CHIP_IS_E1x(bp
))
7533 REG_WR(bp
, QM_REG_PF_EN
, 1);
7535 if (!CHIP_IS_E1x(bp
)) {
7536 REG_WR(bp
, TSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
7537 REG_WR(bp
, USEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
7538 REG_WR(bp
, CSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
7539 REG_WR(bp
, XSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
7541 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
7543 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
7544 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
7546 bnx2x_iov_init_dq(bp
);
7548 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
7549 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
7550 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
7551 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
7552 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
7553 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
7554 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
7555 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
7556 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
7557 if (!CHIP_IS_E1x(bp
))
7558 REG_WR(bp
, PBF_REG_DISABLE_PF
, 0);
7560 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
7562 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
7564 if (!CHIP_IS_E1x(bp
))
7565 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 1);
7568 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
7569 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ port
*8, bp
->mf_ov
);
7572 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
7574 /* HC init per function */
7575 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7576 if (CHIP_IS_E1H(bp
)) {
7577 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
7579 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7580 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7582 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
7585 int num_segs
, sb_idx
, prod_offset
;
7587 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
7589 if (!CHIP_IS_E1x(bp
)) {
7590 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
7591 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
7594 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
7596 if (!CHIP_IS_E1x(bp
)) {
7600 * E2 mode: address 0-135 match to the mapping memory;
7601 * 136 - PF0 default prod; 137 - PF1 default prod;
7602 * 138 - PF2 default prod; 139 - PF3 default prod;
7603 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7604 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7607 * E1.5 mode - In backward compatible mode;
7608 * for non default SB; each even line in the memory
7609 * holds the U producer and each odd line hold
7610 * the C producer. The first 128 producers are for
7611 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7612 * producers are for the DSB for each PF.
7613 * Each PF has five segments: (the order inside each
7614 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7615 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7616 * 144-147 attn prods;
7618 /* non-default-status-blocks */
7619 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
7620 IGU_BC_NDSB_NUM_SEGS
: IGU_NORM_NDSB_NUM_SEGS
;
7621 for (sb_idx
= 0; sb_idx
< bp
->igu_sb_cnt
; sb_idx
++) {
7622 prod_offset
= (bp
->igu_base_sb
+ sb_idx
) *
7625 for (i
= 0; i
< num_segs
; i
++) {
7626 addr
= IGU_REG_PROD_CONS_MEMORY
+
7627 (prod_offset
+ i
) * 4;
7628 REG_WR(bp
, addr
, 0);
7630 /* send consumer update with value 0 */
7631 bnx2x_ack_sb(bp
, bp
->igu_base_sb
+ sb_idx
,
7632 USTORM_ID
, 0, IGU_INT_NOP
, 1);
7633 bnx2x_igu_clear_sb(bp
,
7634 bp
->igu_base_sb
+ sb_idx
);
7637 /* default-status-blocks */
7638 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
7639 IGU_BC_DSB_NUM_SEGS
: IGU_NORM_DSB_NUM_SEGS
;
7641 if (CHIP_MODE_IS_4_PORT(bp
))
7642 dsb_idx
= BP_FUNC(bp
);
7644 dsb_idx
= BP_VN(bp
);
7646 prod_offset
= (CHIP_INT_MODE_IS_BC(bp
) ?
7647 IGU_BC_BASE_DSB_PROD
+ dsb_idx
:
7648 IGU_NORM_BASE_DSB_PROD
+ dsb_idx
);
7651 * igu prods come in chunks of E1HVN_MAX (4) -
7652 * does not matters what is the current chip mode
7654 for (i
= 0; i
< (num_segs
* E1HVN_MAX
);
7656 addr
= IGU_REG_PROD_CONS_MEMORY
+
7657 (prod_offset
+ i
)*4;
7658 REG_WR(bp
, addr
, 0);
7660 /* send consumer update with 0 */
7661 if (CHIP_INT_MODE_IS_BC(bp
)) {
7662 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7663 USTORM_ID
, 0, IGU_INT_NOP
, 1);
7664 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7665 CSTORM_ID
, 0, IGU_INT_NOP
, 1);
7666 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7667 XSTORM_ID
, 0, IGU_INT_NOP
, 1);
7668 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7669 TSTORM_ID
, 0, IGU_INT_NOP
, 1);
7670 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7671 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
7673 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7674 USTORM_ID
, 0, IGU_INT_NOP
, 1);
7675 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
7676 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
7678 bnx2x_igu_clear_sb(bp
, bp
->igu_dsb_id
);
7680 /* !!! these should become driver const once
7681 rf-tool supports split-68 const */
7682 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_LSB
, 0);
7683 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_MSB
, 0);
7684 REG_WR(bp
, IGU_REG_SB_MASK_LSB
, 0);
7685 REG_WR(bp
, IGU_REG_SB_MASK_MSB
, 0);
7686 REG_WR(bp
, IGU_REG_PBA_STATUS_LSB
, 0);
7687 REG_WR(bp
, IGU_REG_PBA_STATUS_MSB
, 0);
7691 /* Reset PCIE errors for debug */
7692 REG_WR(bp
, 0x2114, 0xffffffff);
7693 REG_WR(bp
, 0x2120, 0xffffffff);
7695 if (CHIP_IS_E1x(bp
)) {
7696 main_mem_size
= HC_REG_MAIN_MEMORY_SIZE
/ 2; /*dwords*/
7697 main_mem_base
= HC_REG_MAIN_MEMORY
+
7698 BP_PORT(bp
) * (main_mem_size
* 4);
7699 main_mem_prty_clr
= HC_REG_HC_PRTY_STS_CLR
;
7702 val
= REG_RD(bp
, main_mem_prty_clr
);
7705 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7708 /* Clear "false" parity errors in MSI-X table */
7709 for (i
= main_mem_base
;
7710 i
< main_mem_base
+ main_mem_size
* 4;
7711 i
+= main_mem_width
) {
7712 bnx2x_read_dmae(bp
, i
, main_mem_width
/ 4);
7713 bnx2x_write_dmae(bp
, bnx2x_sp_mapping(bp
, wb_data
),
7714 i
, main_mem_width
/ 4);
7716 /* Clear HC parity attention */
7717 REG_RD(bp
, main_mem_prty_clr
);
7720 #ifdef BNX2X_STOP_ON_ERROR
7721 /* Enable STORMs SP logging */
7722 REG_WR8(bp
, BAR_USTRORM_INTMEM
+
7723 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
7724 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
7725 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
7726 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7727 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
7728 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+
7729 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
7732 bnx2x_phy_probe(&bp
->link_params
);
7738 void bnx2x_free_mem_cnic(struct bnx2x
*bp
)
7740 bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_FREE
);
7742 if (!CHIP_IS_E1x(bp
))
7743 BNX2X_PCI_FREE(bp
->cnic_sb
.e2_sb
, bp
->cnic_sb_mapping
,
7744 sizeof(struct host_hc_status_block_e2
));
7746 BNX2X_PCI_FREE(bp
->cnic_sb
.e1x_sb
, bp
->cnic_sb_mapping
,
7747 sizeof(struct host_hc_status_block_e1x
));
7749 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
7752 void bnx2x_free_mem(struct bnx2x
*bp
)
7756 BNX2X_PCI_FREE(bp
->def_status_blk
, bp
->def_status_blk_mapping
,
7757 sizeof(struct host_sp_status_block
));
7759 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
7760 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
7762 BNX2X_PCI_FREE(bp
->slowpath
, bp
->slowpath_mapping
,
7763 sizeof(struct bnx2x_slowpath
));
7765 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++)
7766 BNX2X_PCI_FREE(bp
->context
[i
].vcxt
, bp
->context
[i
].cxt_mapping
,
7767 bp
->context
[i
].size
);
7768 bnx2x_ilt_mem_op(bp
, ILT_MEMOP_FREE
);
7770 BNX2X_FREE(bp
->ilt
->lines
);
7772 BNX2X_PCI_FREE(bp
->spq
, bp
->spq_mapping
, BCM_PAGE_SIZE
);
7774 BNX2X_PCI_FREE(bp
->eq_ring
, bp
->eq_mapping
,
7775 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
7777 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
7779 bnx2x_iov_free_mem(bp
);
7783 int bnx2x_alloc_mem_cnic(struct bnx2x
*bp
)
7785 if (!CHIP_IS_E1x(bp
))
7786 /* size = the status block + ramrod buffers */
7787 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e2_sb
, &bp
->cnic_sb_mapping
,
7788 sizeof(struct host_hc_status_block_e2
));
7790 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e1x_sb
,
7791 &bp
->cnic_sb_mapping
,
7793 host_hc_status_block_e1x
));
7795 if (CONFIGURE_NIC_MODE(bp
) && !bp
->t2
)
7796 /* allocate searcher T2 table, as it wan't allocated before */
7797 BNX2X_PCI_ALLOC(bp
->t2
, &bp
->t2_mapping
, SRC_T2_SZ
);
7799 /* write address to which L5 should insert its values */
7800 bp
->cnic_eth_dev
.addr_drv_info_to_mcp
=
7801 &bp
->slowpath
->drv_info_to_mcp
;
7803 if (bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_ALLOC
))
7809 bnx2x_free_mem_cnic(bp
);
7810 BNX2X_ERR("Can't allocate memory\n");
7814 int bnx2x_alloc_mem(struct bnx2x
*bp
)
7816 int i
, allocated
, context_size
;
7818 if (!CONFIGURE_NIC_MODE(bp
) && !bp
->t2
)
7819 /* allocate searcher T2 table */
7820 BNX2X_PCI_ALLOC(bp
->t2
, &bp
->t2_mapping
, SRC_T2_SZ
);
7822 BNX2X_PCI_ALLOC(bp
->def_status_blk
, &bp
->def_status_blk_mapping
,
7823 sizeof(struct host_sp_status_block
));
7825 BNX2X_PCI_ALLOC(bp
->slowpath
, &bp
->slowpath_mapping
,
7826 sizeof(struct bnx2x_slowpath
));
7828 /* Allocate memory for CDU context:
7829 * This memory is allocated separately and not in the generic ILT
7830 * functions because CDU differs in few aspects:
7831 * 1. There are multiple entities allocating memory for context -
7832 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7833 * its own ILT lines.
7834 * 2. Since CDU page-size is not a single 4KB page (which is the case
7835 * for the other ILT clients), to be efficient we want to support
7836 * allocation of sub-page-size in the last entry.
7837 * 3. Context pointers are used by the driver to pass to FW / update
7838 * the context (for the other ILT clients the pointers are used just to
7839 * free the memory during unload).
7841 context_size
= sizeof(union cdu_context
) * BNX2X_L2_CID_COUNT(bp
);
7843 for (i
= 0, allocated
= 0; allocated
< context_size
; i
++) {
7844 bp
->context
[i
].size
= min(CDU_ILT_PAGE_SZ
,
7845 (context_size
- allocated
));
7846 BNX2X_PCI_ALLOC(bp
->context
[i
].vcxt
,
7847 &bp
->context
[i
].cxt_mapping
,
7848 bp
->context
[i
].size
);
7849 allocated
+= bp
->context
[i
].size
;
7851 BNX2X_ALLOC(bp
->ilt
->lines
, sizeof(struct ilt_line
) * ILT_MAX_LINES
);
7853 if (bnx2x_ilt_mem_op(bp
, ILT_MEMOP_ALLOC
))
7856 if (bnx2x_iov_alloc_mem(bp
))
7859 /* Slow path ring */
7860 BNX2X_PCI_ALLOC(bp
->spq
, &bp
->spq_mapping
, BCM_PAGE_SIZE
);
7863 BNX2X_PCI_ALLOC(bp
->eq_ring
, &bp
->eq_mapping
,
7864 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
7870 BNX2X_ERR("Can't allocate memory\n");
7875 * Init service functions
7878 int bnx2x_set_mac_one(struct bnx2x
*bp
, u8
*mac
,
7879 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
7880 int mac_type
, unsigned long *ramrod_flags
)
7883 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
7885 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
7887 /* Fill general parameters */
7888 ramrod_param
.vlan_mac_obj
= obj
;
7889 ramrod_param
.ramrod_flags
= *ramrod_flags
;
7891 /* Fill a user request section if needed */
7892 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
7893 memcpy(ramrod_param
.user_req
.u
.mac
.mac
, mac
, ETH_ALEN
);
7895 __set_bit(mac_type
, &ramrod_param
.user_req
.vlan_mac_flags
);
7897 /* Set the command: ADD or DEL */
7899 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
7901 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
7904 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
7906 if (rc
== -EEXIST
) {
7907 DP(BNX2X_MSG_SP
, "Failed to schedule ADD operations: %d\n", rc
);
7908 /* do not treat adding same MAC as error */
7911 BNX2X_ERR("%s MAC failed\n", (set
? "Set" : "Del"));
7916 int bnx2x_del_all_macs(struct bnx2x
*bp
,
7917 struct bnx2x_vlan_mac_obj
*mac_obj
,
7918 int mac_type
, bool wait_for_comp
)
7921 unsigned long ramrod_flags
= 0, vlan_mac_flags
= 0;
7923 /* Wait for completion of requested */
7925 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7927 /* Set the mac type of addresses we want to clear */
7928 __set_bit(mac_type
, &vlan_mac_flags
);
7930 rc
= mac_obj
->delete_all(bp
, mac_obj
, &vlan_mac_flags
, &ramrod_flags
);
7932 BNX2X_ERR("Failed to delete MACs: %d\n", rc
);
7937 int bnx2x_set_eth_mac(struct bnx2x
*bp
, bool set
)
7939 if (is_zero_ether_addr(bp
->dev
->dev_addr
) &&
7940 (IS_MF_STORAGE_SD(bp
) || IS_MF_FCOE_AFEX(bp
))) {
7941 DP(NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
,
7942 "Ignoring Zero MAC for STORAGE SD mode\n");
7947 unsigned long ramrod_flags
= 0;
7949 DP(NETIF_MSG_IFUP
, "Adding Eth MAC\n");
7950 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7951 return bnx2x_set_mac_one(bp
, bp
->dev
->dev_addr
,
7952 &bp
->sp_objs
->mac_obj
, set
,
7953 BNX2X_ETH_MAC
, &ramrod_flags
);
7955 return bnx2x_vfpf_config_mac(bp
, bp
->dev
->dev_addr
,
7956 bp
->fp
->index
, true);
7960 int bnx2x_setup_leading(struct bnx2x
*bp
)
7962 return bnx2x_setup_queue(bp
, &bp
->fp
[0], 1);
7966 * bnx2x_set_int_mode - configure interrupt mode
7968 * @bp: driver handle
7970 * In case of MSI-X it will also try to enable MSI-X.
7972 int bnx2x_set_int_mode(struct bnx2x
*bp
)
7976 if (IS_VF(bp
) && int_mode
!= BNX2X_INT_MODE_MSIX
)
7980 case BNX2X_INT_MODE_MSIX
:
7981 /* attempt to enable msix */
7982 rc
= bnx2x_enable_msix(bp
);
7988 /* vfs use only msix */
7989 if (rc
&& IS_VF(bp
))
7992 /* failed to enable multiple MSI-X */
7993 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7995 1 + bp
->num_cnic_queues
);
7997 /* falling through... */
7998 case BNX2X_INT_MODE_MSI
:
7999 bnx2x_enable_msi(bp
);
8001 /* falling through... */
8002 case BNX2X_INT_MODE_INTX
:
8003 bp
->num_ethernet_queues
= 1;
8004 bp
->num_queues
= bp
->num_ethernet_queues
+ bp
->num_cnic_queues
;
8005 BNX2X_DEV_INFO("set number of queues to 1\n");
8008 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8014 /* must be called prior to any HW initializations */
8015 static inline u16
bnx2x_cid_ilt_lines(struct bnx2x
*bp
)
8018 return (BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)/ILT_PAGE_CIDS
;
8019 return L2_ILT_LINES(bp
);
8022 void bnx2x_ilt_set_info(struct bnx2x
*bp
)
8024 struct ilt_client_info
*ilt_client
;
8025 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
8028 ilt
->start_line
= FUNC_ILT_BASE(BP_FUNC(bp
));
8029 DP(BNX2X_MSG_SP
, "ilt starts at line %d\n", ilt
->start_line
);
8032 ilt_client
= &ilt
->clients
[ILT_CLIENT_CDU
];
8033 ilt_client
->client_num
= ILT_CLIENT_CDU
;
8034 ilt_client
->page_size
= CDU_ILT_PAGE_SZ
;
8035 ilt_client
->flags
= ILT_CLIENT_SKIP_MEM
;
8036 ilt_client
->start
= line
;
8037 line
+= bnx2x_cid_ilt_lines(bp
);
8039 if (CNIC_SUPPORT(bp
))
8040 line
+= CNIC_ILT_LINES
;
8041 ilt_client
->end
= line
- 1;
8043 DP(NETIF_MSG_IFUP
, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8046 ilt_client
->page_size
,
8048 ilog2(ilt_client
->page_size
>> 12));
8051 if (QM_INIT(bp
->qm_cid_count
)) {
8052 ilt_client
= &ilt
->clients
[ILT_CLIENT_QM
];
8053 ilt_client
->client_num
= ILT_CLIENT_QM
;
8054 ilt_client
->page_size
= QM_ILT_PAGE_SZ
;
8055 ilt_client
->flags
= 0;
8056 ilt_client
->start
= line
;
8058 /* 4 bytes for each cid */
8059 line
+= DIV_ROUND_UP(bp
->qm_cid_count
* QM_QUEUES_PER_FUNC
* 4,
8062 ilt_client
->end
= line
- 1;
8065 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8068 ilt_client
->page_size
,
8070 ilog2(ilt_client
->page_size
>> 12));
8074 if (CNIC_SUPPORT(bp
)) {
8076 ilt_client
= &ilt
->clients
[ILT_CLIENT_SRC
];
8077 ilt_client
->client_num
= ILT_CLIENT_SRC
;
8078 ilt_client
->page_size
= SRC_ILT_PAGE_SZ
;
8079 ilt_client
->flags
= 0;
8080 ilt_client
->start
= line
;
8081 line
+= SRC_ILT_LINES
;
8082 ilt_client
->end
= line
- 1;
8085 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8088 ilt_client
->page_size
,
8090 ilog2(ilt_client
->page_size
>> 12));
8093 ilt_client
= &ilt
->clients
[ILT_CLIENT_TM
];
8094 ilt_client
->client_num
= ILT_CLIENT_TM
;
8095 ilt_client
->page_size
= TM_ILT_PAGE_SZ
;
8096 ilt_client
->flags
= 0;
8097 ilt_client
->start
= line
;
8098 line
+= TM_ILT_LINES
;
8099 ilt_client
->end
= line
- 1;
8102 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8105 ilt_client
->page_size
,
8107 ilog2(ilt_client
->page_size
>> 12));
8110 BUG_ON(line
> ILT_MAX_LINES
);
8114 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8116 * @bp: driver handle
8117 * @fp: pointer to fastpath
8118 * @init_params: pointer to parameters structure
8120 * parameters configured:
8121 * - HC configuration
8122 * - Queue's CDU context
8124 static void bnx2x_pf_q_prep_init(struct bnx2x
*bp
,
8125 struct bnx2x_fastpath
*fp
, struct bnx2x_queue_init_params
*init_params
)
8129 int cxt_index
, cxt_offset
;
8131 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8132 if (!IS_FCOE_FP(fp
)) {
8133 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->rx
.flags
);
8134 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->tx
.flags
);
8136 /* If HC is supporterd, enable host coalescing in the transition
8139 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->rx
.flags
);
8140 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->tx
.flags
);
8143 init_params
->rx
.hc_rate
= bp
->rx_ticks
?
8144 (1000000 / bp
->rx_ticks
) : 0;
8145 init_params
->tx
.hc_rate
= bp
->tx_ticks
?
8146 (1000000 / bp
->tx_ticks
) : 0;
8149 init_params
->rx
.fw_sb_id
= init_params
->tx
.fw_sb_id
=
8153 * CQ index among the SB indices: FCoE clients uses the default
8154 * SB, therefore it's different.
8156 init_params
->rx
.sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
8157 init_params
->tx
.sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
;
8160 /* set maximum number of COSs supported by this queue */
8161 init_params
->max_cos
= fp
->max_cos
;
8163 DP(NETIF_MSG_IFUP
, "fp: %d setting queue params max cos to: %d\n",
8164 fp
->index
, init_params
->max_cos
);
8166 /* set the context pointers queue object */
8167 for (cos
= FIRST_TX_COS_INDEX
; cos
< init_params
->max_cos
; cos
++) {
8168 cxt_index
= fp
->txdata_ptr
[cos
]->cid
/ ILT_PAGE_CIDS
;
8169 cxt_offset
= fp
->txdata_ptr
[cos
]->cid
- (cxt_index
*
8171 init_params
->cxts
[cos
] =
8172 &bp
->context
[cxt_index
].vcxt
[cxt_offset
].eth
;
8176 static int bnx2x_setup_tx_only(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8177 struct bnx2x_queue_state_params
*q_params
,
8178 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
,
8179 int tx_index
, bool leading
)
8181 memset(tx_only_params
, 0, sizeof(*tx_only_params
));
8183 /* Set the command */
8184 q_params
->cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
8186 /* Set tx-only QUEUE flags: don't zero statistics */
8187 tx_only_params
->flags
= bnx2x_get_common_flags(bp
, fp
, false);
8189 /* choose the index of the cid to send the slow path on */
8190 tx_only_params
->cid_index
= tx_index
;
8192 /* Set general TX_ONLY_SETUP parameters */
8193 bnx2x_pf_q_prep_general(bp
, fp
, &tx_only_params
->gen_params
, tx_index
);
8195 /* Set Tx TX_ONLY_SETUP parameters */
8196 bnx2x_pf_tx_q_prep(bp
, fp
, &tx_only_params
->txq_params
, tx_index
);
8199 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8200 tx_index
, q_params
->q_obj
->cids
[FIRST_TX_COS_INDEX
],
8201 q_params
->q_obj
->cids
[tx_index
], q_params
->q_obj
->cl_id
,
8202 tx_only_params
->gen_params
.spcl_id
, tx_only_params
->flags
);
8204 /* send the ramrod */
8205 return bnx2x_queue_state_change(bp
, q_params
);
8210 * bnx2x_setup_queue - setup queue
8212 * @bp: driver handle
8213 * @fp: pointer to fastpath
8214 * @leading: is leading
8216 * This function performs 2 steps in a Queue state machine
8217 * actually: 1) RESET->INIT 2) INIT->SETUP
8220 int bnx2x_setup_queue(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8223 struct bnx2x_queue_state_params q_params
= {NULL
};
8224 struct bnx2x_queue_setup_params
*setup_params
=
8225 &q_params
.params
.setup
;
8226 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
=
8227 &q_params
.params
.tx_only
;
8231 DP(NETIF_MSG_IFUP
, "setting up queue %d\n", fp
->index
);
8233 /* reset IGU state skip FCoE L2 queue */
8234 if (!IS_FCOE_FP(fp
))
8235 bnx2x_ack_sb(bp
, fp
->igu_sb_id
, USTORM_ID
, 0,
8238 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8239 /* We want to wait for completion in this context */
8240 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8242 /* Prepare the INIT parameters */
8243 bnx2x_pf_q_prep_init(bp
, fp
, &q_params
.params
.init
);
8245 /* Set the command */
8246 q_params
.cmd
= BNX2X_Q_CMD_INIT
;
8248 /* Change the state to INIT */
8249 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8251 BNX2X_ERR("Queue(%d) INIT failed\n", fp
->index
);
8255 DP(NETIF_MSG_IFUP
, "init complete\n");
8258 /* Now move the Queue to the SETUP state... */
8259 memset(setup_params
, 0, sizeof(*setup_params
));
8261 /* Set QUEUE flags */
8262 setup_params
->flags
= bnx2x_get_q_flags(bp
, fp
, leading
);
8264 /* Set general SETUP parameters */
8265 bnx2x_pf_q_prep_general(bp
, fp
, &setup_params
->gen_params
,
8266 FIRST_TX_COS_INDEX
);
8268 bnx2x_pf_rx_q_prep(bp
, fp
, &setup_params
->pause_params
,
8269 &setup_params
->rxq_params
);
8271 bnx2x_pf_tx_q_prep(bp
, fp
, &setup_params
->txq_params
,
8272 FIRST_TX_COS_INDEX
);
8274 /* Set the command */
8275 q_params
.cmd
= BNX2X_Q_CMD_SETUP
;
8278 bp
->fcoe_init
= true;
8280 /* Change the state to SETUP */
8281 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8283 BNX2X_ERR("Queue(%d) SETUP failed\n", fp
->index
);
8287 /* loop through the relevant tx-only indices */
8288 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8289 tx_index
< fp
->max_cos
;
8292 /* prepare and send tx-only ramrod*/
8293 rc
= bnx2x_setup_tx_only(bp
, fp
, &q_params
,
8294 tx_only_params
, tx_index
, leading
);
8296 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8297 fp
->index
, tx_index
);
8305 static int bnx2x_stop_queue(struct bnx2x
*bp
, int index
)
8307 struct bnx2x_fastpath
*fp
= &bp
->fp
[index
];
8308 struct bnx2x_fp_txdata
*txdata
;
8309 struct bnx2x_queue_state_params q_params
= {NULL
};
8312 DP(NETIF_MSG_IFDOWN
, "stopping queue %d cid %d\n", index
, fp
->cid
);
8314 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8315 /* We want to wait for completion in this context */
8316 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8319 /* close tx-only connections */
8320 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8321 tx_index
< fp
->max_cos
;
8324 /* ascertain this is a normal queue*/
8325 txdata
= fp
->txdata_ptr
[tx_index
];
8327 DP(NETIF_MSG_IFDOWN
, "stopping tx-only queue %d\n",
8330 /* send halt terminate on tx-only connection */
8331 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8332 memset(&q_params
.params
.terminate
, 0,
8333 sizeof(q_params
.params
.terminate
));
8334 q_params
.params
.terminate
.cid_index
= tx_index
;
8336 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8340 /* send halt terminate on tx-only connection */
8341 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8342 memset(&q_params
.params
.cfc_del
, 0,
8343 sizeof(q_params
.params
.cfc_del
));
8344 q_params
.params
.cfc_del
.cid_index
= tx_index
;
8345 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8349 /* Stop the primary connection: */
8350 /* ...halt the connection */
8351 q_params
.cmd
= BNX2X_Q_CMD_HALT
;
8352 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8356 /* ...terminate the connection */
8357 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8358 memset(&q_params
.params
.terminate
, 0,
8359 sizeof(q_params
.params
.terminate
));
8360 q_params
.params
.terminate
.cid_index
= FIRST_TX_COS_INDEX
;
8361 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8364 /* ...delete cfc entry */
8365 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8366 memset(&q_params
.params
.cfc_del
, 0,
8367 sizeof(q_params
.params
.cfc_del
));
8368 q_params
.params
.cfc_del
.cid_index
= FIRST_TX_COS_INDEX
;
8369 return bnx2x_queue_state_change(bp
, &q_params
);
8373 static void bnx2x_reset_func(struct bnx2x
*bp
)
8375 int port
= BP_PORT(bp
);
8376 int func
= BP_FUNC(bp
);
8379 /* Disable the function in the FW */
8380 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(func
), 0);
8381 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(func
), 0);
8382 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(func
), 0);
8383 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(func
), 0);
8386 for_each_eth_queue(bp
, i
) {
8387 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
8388 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8389 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp
->fw_sb_id
),
8393 if (CNIC_LOADED(bp
))
8395 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8396 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8397 (bnx2x_cnic_fw_sb_id(bp
)), SB_DISABLED
);
8400 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8401 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func
),
8404 for (i
= 0; i
< XSTORM_SPQ_DATA_SIZE
/ 4; i
++)
8405 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_DATA_OFFSET(func
),
8409 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
8410 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
8411 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
8413 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
8414 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
8417 if (CNIC_LOADED(bp
)) {
8418 /* Disable Timer scan */
8419 REG_WR(bp
, TM_REG_EN_LINEAR0_TIMER
+ port
*4, 0);
8421 * Wait for at least 10ms and up to 2 second for the timers
8424 for (i
= 0; i
< 200; i
++) {
8426 if (!REG_RD(bp
, TM_REG_LIN0_SCAN_ON
+ port
*4))
8431 bnx2x_clear_func_ilt(bp
, func
);
8433 /* Timers workaround bug for E2: if this is vnic-3,
8434 * we need to set the entire ilt range for this timers.
8436 if (!CHIP_IS_E1x(bp
) && BP_VN(bp
) == 3) {
8437 struct ilt_client_info ilt_cli
;
8438 /* use dummy TM client */
8439 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
8441 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
8442 ilt_cli
.client_num
= ILT_CLIENT_TM
;
8444 bnx2x_ilt_boundry_init_op(bp
, &ilt_cli
, 0, INITOP_CLEAR
);
8447 /* this assumes that reset_port() called before reset_func()*/
8448 if (!CHIP_IS_E1x(bp
))
8449 bnx2x_pf_disable(bp
);
8454 static void bnx2x_reset_port(struct bnx2x
*bp
)
8456 int port
= BP_PORT(bp
);
8459 /* Reset physical Link */
8460 bnx2x__link_reset(bp
);
8462 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
8464 /* Do not rcv packets to BRB */
8465 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK
+ port
*4, 0x0);
8466 /* Do not direct rcv packets that are not for MCP to the BRB */
8467 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
8468 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
8471 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, 0);
8474 /* Check for BRB port occupancy */
8475 val
= REG_RD(bp
, BRB1_REG_PORT_NUM_OCC_BLOCKS_0
+ port
*4);
8477 DP(NETIF_MSG_IFDOWN
,
8478 "BRB1 is not empty %d blocks are occupied\n", val
);
8480 /* TODO: Close Doorbell port? */
8483 static int bnx2x_reset_hw(struct bnx2x
*bp
, u32 load_code
)
8485 struct bnx2x_func_state_params func_params
= {NULL
};
8487 /* Prepare parameters for function state transitions */
8488 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
8490 func_params
.f_obj
= &bp
->func_obj
;
8491 func_params
.cmd
= BNX2X_F_CMD_HW_RESET
;
8493 func_params
.params
.hw_init
.load_phase
= load_code
;
8495 return bnx2x_func_state_change(bp
, &func_params
);
8498 static int bnx2x_func_stop(struct bnx2x
*bp
)
8500 struct bnx2x_func_state_params func_params
= {NULL
};
8503 /* Prepare parameters for function state transitions */
8504 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
8505 func_params
.f_obj
= &bp
->func_obj
;
8506 func_params
.cmd
= BNX2X_F_CMD_STOP
;
8509 * Try to stop the function the 'good way'. If fails (in case
8510 * of a parity error during bnx2x_chip_cleanup()) and we are
8511 * not in a debug mode, perform a state transaction in order to
8512 * enable further HW_RESET transaction.
8514 rc
= bnx2x_func_state_change(bp
, &func_params
);
8516 #ifdef BNX2X_STOP_ON_ERROR
8519 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8520 __set_bit(RAMROD_DRV_CLR_ONLY
, &func_params
.ramrod_flags
);
8521 return bnx2x_func_state_change(bp
, &func_params
);
8529 * bnx2x_send_unload_req - request unload mode from the MCP.
8531 * @bp: driver handle
8532 * @unload_mode: requested function's unload mode
8534 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8536 u32
bnx2x_send_unload_req(struct bnx2x
*bp
, int unload_mode
)
8539 int port
= BP_PORT(bp
);
8541 /* Select the UNLOAD request mode */
8542 if (unload_mode
== UNLOAD_NORMAL
)
8543 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8545 else if (bp
->flags
& NO_WOL_FLAG
)
8546 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
;
8549 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
8550 u8
*mac_addr
= bp
->dev
->dev_addr
;
8554 /* The mac address is written to entries 1-4 to
8555 * preserve entry 0 which is used by the PMF
8557 u8 entry
= (BP_VN(bp
) + 1)*8;
8559 val
= (mac_addr
[0] << 8) | mac_addr
[1];
8560 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
, val
);
8562 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
8563 (mac_addr
[4] << 8) | mac_addr
[5];
8564 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
+ 4, val
);
8566 /* Enable the PME and clear the status */
8567 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, &pmc
);
8568 pmc
|= PCI_PM_CTRL_PME_ENABLE
| PCI_PM_CTRL_PME_STATUS
;
8569 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, pmc
);
8571 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
;
8574 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8576 /* Send the request to the MCP */
8578 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
8580 int path
= BP_PATH(bp
);
8582 DP(NETIF_MSG_IFDOWN
, "NO MCP - load counts[%d] %d, %d, %d\n",
8583 path
, load_count
[path
][0], load_count
[path
][1],
8584 load_count
[path
][2]);
8585 load_count
[path
][0]--;
8586 load_count
[path
][1 + port
]--;
8587 DP(NETIF_MSG_IFDOWN
, "NO MCP - new load counts[%d] %d, %d, %d\n",
8588 path
, load_count
[path
][0], load_count
[path
][1],
8589 load_count
[path
][2]);
8590 if (load_count
[path
][0] == 0)
8591 reset_code
= FW_MSG_CODE_DRV_UNLOAD_COMMON
;
8592 else if (load_count
[path
][1 + port
] == 0)
8593 reset_code
= FW_MSG_CODE_DRV_UNLOAD_PORT
;
8595 reset_code
= FW_MSG_CODE_DRV_UNLOAD_FUNCTION
;
8602 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8604 * @bp: driver handle
8605 * @keep_link: true iff link should be kept up
8607 void bnx2x_send_unload_done(struct bnx2x
*bp
, bool keep_link
)
8609 u32 reset_param
= keep_link
? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
: 0;
8611 /* Report UNLOAD_DONE to MCP */
8613 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, reset_param
);
8616 static int bnx2x_func_wait_started(struct bnx2x
*bp
)
8619 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
8625 * (assumption: No Attention from MCP at this stage)
8626 * PMF probably in the middle of TXdisable/enable transaction
8627 * 1. Sync IRS for default SB
8628 * 2. Sync SP queue - this guarantes us that attention handling started
8629 * 3. Wait, that TXdisable/enable transaction completes
8631 * 1+2 guranty that if DCBx attention was scheduled it already changed
8632 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8633 * received complettion for the transaction the state is TX_STOPPED.
8634 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8638 /* make sure default SB ISR is done */
8640 synchronize_irq(bp
->msix_table
[0].vector
);
8642 synchronize_irq(bp
->pdev
->irq
);
8644 flush_workqueue(bnx2x_wq
);
8646 while (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
8647 BNX2X_F_STATE_STARTED
&& tout
--)
8650 if (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
8651 BNX2X_F_STATE_STARTED
) {
8652 #ifdef BNX2X_STOP_ON_ERROR
8653 BNX2X_ERR("Wrong function state\n");
8657 * Failed to complete the transaction in a "good way"
8658 * Force both transactions with CLR bit
8660 struct bnx2x_func_state_params func_params
= {NULL
};
8662 DP(NETIF_MSG_IFDOWN
,
8663 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8665 func_params
.f_obj
= &bp
->func_obj
;
8666 __set_bit(RAMROD_DRV_CLR_ONLY
,
8667 &func_params
.ramrod_flags
);
8669 /* STARTED-->TX_ST0PPED */
8670 func_params
.cmd
= BNX2X_F_CMD_TX_STOP
;
8671 bnx2x_func_state_change(bp
, &func_params
);
8673 /* TX_ST0PPED-->STARTED */
8674 func_params
.cmd
= BNX2X_F_CMD_TX_START
;
8675 return bnx2x_func_state_change(bp
, &func_params
);
8682 void bnx2x_chip_cleanup(struct bnx2x
*bp
, int unload_mode
, bool keep_link
)
8684 int port
= BP_PORT(bp
);
8687 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
8690 /* Wait until tx fastpath tasks complete */
8691 for_each_tx_queue(bp
, i
) {
8692 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
8694 for_each_cos_in_tx_queue(fp
, cos
)
8695 rc
= bnx2x_clean_tx_queue(bp
, fp
->txdata_ptr
[cos
]);
8696 #ifdef BNX2X_STOP_ON_ERROR
8702 /* Give HW time to discard old tx messages */
8703 usleep_range(1000, 2000);
8705 /* Clean all ETH MACs */
8706 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_ETH_MAC
,
8709 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc
);
8711 /* Clean up UC list */
8712 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_UC_LIST_MAC
,
8715 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8719 if (!CHIP_IS_E1(bp
))
8720 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
8722 /* Set "drop all" (stop Rx).
8723 * We need to take a netif_addr_lock() here in order to prevent
8724 * a race between the completion code and this code.
8726 netif_addr_lock_bh(bp
->dev
);
8727 /* Schedule the rx_mode command */
8728 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
8729 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
8731 bnx2x_set_storm_rx_mode(bp
);
8733 /* Cleanup multicast configuration */
8734 rparam
.mcast_obj
= &bp
->mcast_obj
;
8735 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
8737 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc
);
8739 netif_addr_unlock_bh(bp
->dev
);
8741 bnx2x_iov_chip_cleanup(bp
);
8745 * Send the UNLOAD_REQUEST to the MCP. This will return if
8746 * this function should perform FUNC, PORT or COMMON HW
8749 reset_code
= bnx2x_send_unload_req(bp
, unload_mode
);
8752 * (assumption: No Attention from MCP at this stage)
8753 * PMF probably in the middle of TXdisable/enable transaction
8755 rc
= bnx2x_func_wait_started(bp
);
8757 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8758 #ifdef BNX2X_STOP_ON_ERROR
8763 /* Close multi and leading connections
8764 * Completions for ramrods are collected in a synchronous way
8766 for_each_eth_queue(bp
, i
)
8767 if (bnx2x_stop_queue(bp
, i
))
8768 #ifdef BNX2X_STOP_ON_ERROR
8774 if (CNIC_LOADED(bp
)) {
8775 for_each_cnic_queue(bp
, i
)
8776 if (bnx2x_stop_queue(bp
, i
))
8777 #ifdef BNX2X_STOP_ON_ERROR
8784 /* If SP settings didn't get completed so far - something
8785 * very wrong has happen.
8787 if (!bnx2x_wait_sp_comp(bp
, ~0x0UL
))
8788 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8790 #ifndef BNX2X_STOP_ON_ERROR
8793 rc
= bnx2x_func_stop(bp
);
8795 BNX2X_ERR("Function stop failed!\n");
8796 #ifdef BNX2X_STOP_ON_ERROR
8801 /* Disable HW interrupts, NAPI */
8802 bnx2x_netif_stop(bp
, 1);
8803 /* Delete all NAPI objects */
8804 bnx2x_del_all_napi(bp
);
8805 if (CNIC_LOADED(bp
))
8806 bnx2x_del_all_napi_cnic(bp
);
8811 /* Reset the chip */
8812 rc
= bnx2x_reset_hw(bp
, reset_code
);
8814 BNX2X_ERR("HW_RESET failed\n");
8817 /* Report UNLOAD_DONE to MCP */
8818 bnx2x_send_unload_done(bp
, keep_link
);
8821 void bnx2x_disable_close_the_gate(struct bnx2x
*bp
)
8825 DP(NETIF_MSG_IFDOWN
, "Disabling \"close the gates\"\n");
8827 if (CHIP_IS_E1(bp
)) {
8828 int port
= BP_PORT(bp
);
8829 u32 addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
8830 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
8832 val
= REG_RD(bp
, addr
);
8834 REG_WR(bp
, addr
, val
);
8836 val
= REG_RD(bp
, MISC_REG_AEU_GENERAL_MASK
);
8837 val
&= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK
|
8838 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK
);
8839 REG_WR(bp
, MISC_REG_AEU_GENERAL_MASK
, val
);
8843 /* Close gates #2, #3 and #4: */
8844 static void bnx2x_set_234_gates(struct bnx2x
*bp
, bool close
)
8848 /* Gates #2 and #4a are closed/opened for "not E1" only */
8849 if (!CHIP_IS_E1(bp
)) {
8851 REG_WR(bp
, PXP_REG_HST_DISCARD_DOORBELLS
, !!close
);
8853 REG_WR(bp
, PXP_REG_HST_DISCARD_INTERNAL_WRITES
, !!close
);
8857 if (CHIP_IS_E1x(bp
)) {
8858 /* Prevent interrupts from HC on both ports */
8859 val
= REG_RD(bp
, HC_REG_CONFIG_1
);
8860 REG_WR(bp
, HC_REG_CONFIG_1
,
8861 (!close
) ? (val
| HC_CONFIG_1_REG_BLOCK_DISABLE_1
) :
8862 (val
& ~(u32
)HC_CONFIG_1_REG_BLOCK_DISABLE_1
));
8864 val
= REG_RD(bp
, HC_REG_CONFIG_0
);
8865 REG_WR(bp
, HC_REG_CONFIG_0
,
8866 (!close
) ? (val
| HC_CONFIG_0_REG_BLOCK_DISABLE_0
) :
8867 (val
& ~(u32
)HC_CONFIG_0_REG_BLOCK_DISABLE_0
));
8869 /* Prevent incoming interrupts in IGU */
8870 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
8872 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
,
8874 (val
| IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
) :
8875 (val
& ~(u32
)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
));
8878 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "%s gates #2, #3 and #4\n",
8879 close
? "closing" : "opening");
8883 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8885 static void bnx2x_clp_reset_prep(struct bnx2x
*bp
, u32
*magic_val
)
8887 /* Do some magic... */
8888 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
8889 *magic_val
= val
& SHARED_MF_CLP_MAGIC
;
8890 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
, val
| SHARED_MF_CLP_MAGIC
);
8894 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8896 * @bp: driver handle
8897 * @magic_val: old value of the `magic' bit.
8899 static void bnx2x_clp_reset_done(struct bnx2x
*bp
, u32 magic_val
)
8901 /* Restore the `magic' bit value... */
8902 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
8903 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
,
8904 (val
& (~SHARED_MF_CLP_MAGIC
)) | magic_val
);
8908 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8910 * @bp: driver handle
8911 * @magic_val: old value of 'magic' bit.
8913 * Takes care of CLP configurations.
8915 static void bnx2x_reset_mcp_prep(struct bnx2x
*bp
, u32
*magic_val
)
8918 u32 validity_offset
;
8920 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "Starting\n");
8922 /* Set `magic' bit in order to save MF config */
8923 if (!CHIP_IS_E1(bp
))
8924 bnx2x_clp_reset_prep(bp
, magic_val
);
8926 /* Get shmem offset */
8927 shmem
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
8929 offsetof(struct shmem_region
, validity_map
[BP_PORT(bp
)]);
8931 /* Clear validity map flags */
8933 REG_WR(bp
, shmem
+ validity_offset
, 0);
8936 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8937 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8940 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8942 * @bp: driver handle
8944 static void bnx2x_mcp_wait_one(struct bnx2x
*bp
)
8946 /* special handling for emulation and FPGA,
8947 wait 10 times longer */
8948 if (CHIP_REV_IS_SLOW(bp
))
8949 msleep(MCP_ONE_TIMEOUT
*10);
8951 msleep(MCP_ONE_TIMEOUT
);
8955 * initializes bp->common.shmem_base and waits for validity signature to appear
8957 static int bnx2x_init_shmem(struct bnx2x
*bp
)
8963 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
8964 if (bp
->common
.shmem_base
) {
8965 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
8966 if (val
& SHR_MEM_VALIDITY_MB
)
8970 bnx2x_mcp_wait_one(bp
);
8972 } while (cnt
++ < (MCP_TIMEOUT
/ MCP_ONE_TIMEOUT
));
8974 BNX2X_ERR("BAD MCP validity signature\n");
8979 static int bnx2x_reset_mcp_comp(struct bnx2x
*bp
, u32 magic_val
)
8981 int rc
= bnx2x_init_shmem(bp
);
8983 /* Restore the `magic' bit value */
8984 if (!CHIP_IS_E1(bp
))
8985 bnx2x_clp_reset_done(bp
, magic_val
);
8990 static void bnx2x_pxp_prep(struct bnx2x
*bp
)
8992 if (!CHIP_IS_E1(bp
)) {
8993 REG_WR(bp
, PXP2_REG_RD_START_INIT
, 0);
8994 REG_WR(bp
, PXP2_REG_RQ_RBC_DONE
, 0);
9000 * Reset the whole chip except for:
9002 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9005 * - MISC (including AEU)
9009 static void bnx2x_process_kill_chip_reset(struct bnx2x
*bp
, bool global
)
9011 u32 not_reset_mask1
, reset_mask1
, not_reset_mask2
, reset_mask2
;
9012 u32 global_bits2
, stay_reset2
;
9015 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9016 * (per chip) blocks.
9019 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU
|
9020 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE
;
9022 /* Don't reset the following blocks.
9023 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9024 * reset, as in 4 port device they might still be owned
9025 * by the MCP (there is only one leader per path).
9028 MISC_REGISTERS_RESET_REG_1_RST_HC
|
9029 MISC_REGISTERS_RESET_REG_1_RST_PXPV
|
9030 MISC_REGISTERS_RESET_REG_1_RST_PXP
;
9033 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO
|
9034 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
|
9035 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE
|
9036 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE
|
9037 MISC_REGISTERS_RESET_REG_2_RST_RBCN
|
9038 MISC_REGISTERS_RESET_REG_2_RST_GRC
|
9039 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE
|
9040 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B
|
9041 MISC_REGISTERS_RESET_REG_2_RST_ATC
|
9042 MISC_REGISTERS_RESET_REG_2_PGLC
|
9043 MISC_REGISTERS_RESET_REG_2_RST_BMAC0
|
9044 MISC_REGISTERS_RESET_REG_2_RST_BMAC1
|
9045 MISC_REGISTERS_RESET_REG_2_RST_EMAC0
|
9046 MISC_REGISTERS_RESET_REG_2_RST_EMAC1
|
9047 MISC_REGISTERS_RESET_REG_2_UMAC0
|
9048 MISC_REGISTERS_RESET_REG_2_UMAC1
;
9051 * Keep the following blocks in reset:
9052 * - all xxMACs are handled by the bnx2x_link code.
9055 MISC_REGISTERS_RESET_REG_2_XMAC
|
9056 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
;
9058 /* Full reset masks according to the chip */
9059 reset_mask1
= 0xffffffff;
9062 reset_mask2
= 0xffff;
9063 else if (CHIP_IS_E1H(bp
))
9064 reset_mask2
= 0x1ffff;
9065 else if (CHIP_IS_E2(bp
))
9066 reset_mask2
= 0xfffff;
9067 else /* CHIP_IS_E3 */
9068 reset_mask2
= 0x3ffffff;
9070 /* Don't reset global blocks unless we need to */
9072 reset_mask2
&= ~global_bits2
;
9075 * In case of attention in the QM, we need to reset PXP
9076 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9077 * because otherwise QM reset would release 'close the gates' shortly
9078 * before resetting the PXP, then the PSWRQ would send a write
9079 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9080 * read the payload data from PSWWR, but PSWWR would not
9081 * respond. The write queue in PGLUE would stuck, dmae commands
9082 * would not return. Therefore it's important to reset the second
9083 * reset register (containing the
9084 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9085 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9088 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
9089 reset_mask2
& (~not_reset_mask2
));
9091 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
9092 reset_mask1
& (~not_reset_mask1
));
9097 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
9098 reset_mask2
& (~stay_reset2
));
9103 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, reset_mask1
);
9108 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9109 * It should get cleared in no more than 1s.
9111 * @bp: driver handle
9113 * It should get cleared in no more than 1s. Returns 0 if
9114 * pending writes bit gets cleared.
9116 static int bnx2x_er_poll_igu_vq(struct bnx2x
*bp
)
9122 pend_bits
= REG_RD(bp
, IGU_REG_PENDING_BITS_STATUS
);
9127 usleep_range(1000, 2000);
9128 } while (cnt
-- > 0);
9131 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9139 static int bnx2x_process_kill(struct bnx2x
*bp
, bool global
)
9143 u32 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
, pgl_exp_rom2
;
9146 /* Empty the Tetris buffer, wait for 1s */
9148 sr_cnt
= REG_RD(bp
, PXP2_REG_RD_SR_CNT
);
9149 blk_cnt
= REG_RD(bp
, PXP2_REG_RD_BLK_CNT
);
9150 port_is_idle_0
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_0
);
9151 port_is_idle_1
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_1
);
9152 pgl_exp_rom2
= REG_RD(bp
, PXP2_REG_PGL_EXP_ROM2
);
9154 tags_63_32
= REG_RD(bp
, PGLUE_B_REG_TAGS_63_32
);
9156 if ((sr_cnt
== 0x7e) && (blk_cnt
== 0xa0) &&
9157 ((port_is_idle_0
& 0x1) == 0x1) &&
9158 ((port_is_idle_1
& 0x1) == 0x1) &&
9159 (pgl_exp_rom2
== 0xffffffff) &&
9160 (!CHIP_IS_E3(bp
) || (tags_63_32
== 0xffffffff)))
9162 usleep_range(1000, 2000);
9163 } while (cnt
-- > 0);
9166 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9167 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9168 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
,
9175 /* Close gates #2, #3 and #4 */
9176 bnx2x_set_234_gates(bp
, true);
9178 /* Poll for IGU VQs for 57712 and newer chips */
9179 if (!CHIP_IS_E1x(bp
) && bnx2x_er_poll_igu_vq(bp
))
9183 /* TBD: Indicate that "process kill" is in progress to MCP */
9185 /* Clear "unprepared" bit */
9186 REG_WR(bp
, MISC_REG_UNPREPARED
, 0);
9189 /* Make sure all is written to the chip before the reset */
9192 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9193 * PSWHST, GRC and PSWRD Tetris buffer.
9195 usleep_range(1000, 2000);
9197 /* Prepare to chip reset: */
9200 bnx2x_reset_mcp_prep(bp
, &val
);
9206 /* reset the chip */
9207 bnx2x_process_kill_chip_reset(bp
, global
);
9210 /* Recover after reset: */
9212 if (global
&& bnx2x_reset_mcp_comp(bp
, val
))
9215 /* TBD: Add resetting the NO_MCP mode DB here */
9217 /* Open the gates #2, #3 and #4 */
9218 bnx2x_set_234_gates(bp
, false);
9220 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9221 * reset state, re-enable attentions. */
9226 static int bnx2x_leader_reset(struct bnx2x
*bp
)
9229 bool global
= bnx2x_reset_is_global(bp
);
9232 /* if not going to reset MCP - load "fake" driver to reset HW while
9233 * driver is owner of the HW
9235 if (!global
&& !BP_NOMCP(bp
)) {
9236 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_REQ
,
9237 DRV_MSG_CODE_LOAD_REQ_WITH_LFA
);
9239 BNX2X_ERR("MCP response failure, aborting\n");
9241 goto exit_leader_reset
;
9243 if ((load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
) &&
9244 (load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON
)) {
9245 BNX2X_ERR("MCP unexpected resp, aborting\n");
9247 goto exit_leader_reset2
;
9249 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_DONE
, 0);
9251 BNX2X_ERR("MCP response failure, aborting\n");
9253 goto exit_leader_reset2
;
9257 /* Try to recover after the failure */
9258 if (bnx2x_process_kill(bp
, global
)) {
9259 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9262 goto exit_leader_reset2
;
9266 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9269 bnx2x_set_reset_done(bp
);
9271 bnx2x_clear_reset_global(bp
);
9274 /* unload "fake driver" if it was loaded */
9275 if (!global
&& !BP_NOMCP(bp
)) {
9276 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
, 0);
9277 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
9281 bnx2x_release_leader_lock(bp
);
9286 static void bnx2x_recovery_failed(struct bnx2x
*bp
)
9288 netdev_err(bp
->dev
, "Recovery has failed. Power cycle is needed.\n");
9290 /* Disconnect this device */
9291 netif_device_detach(bp
->dev
);
9294 * Block ifup for all function on this engine until "process kill"
9297 bnx2x_set_reset_in_progress(bp
);
9299 /* Shut down the power */
9300 bnx2x_set_power_state(bp
, PCI_D3hot
);
9302 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
9308 * Assumption: runs under rtnl lock. This together with the fact
9309 * that it's called only from bnx2x_sp_rtnl() ensure that it
9310 * will never be called when netif_running(bp->dev) is false.
9312 static void bnx2x_parity_recover(struct bnx2x
*bp
)
9314 bool global
= false;
9315 u32 error_recovered
, error_unrecovered
;
9318 DP(NETIF_MSG_HW
, "Handling parity\n");
9320 switch (bp
->recovery_state
) {
9321 case BNX2X_RECOVERY_INIT
:
9322 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_INIT\n");
9323 is_parity
= bnx2x_chk_parity_attn(bp
, &global
, false);
9324 WARN_ON(!is_parity
);
9326 /* Try to get a LEADER_LOCK HW lock */
9327 if (bnx2x_trylock_leader_lock(bp
)) {
9328 bnx2x_set_reset_in_progress(bp
);
9330 * Check if there is a global attention and if
9331 * there was a global attention, set the global
9336 bnx2x_set_reset_global(bp
);
9341 /* Stop the driver */
9342 /* If interface has been removed - break */
9343 if (bnx2x_nic_unload(bp
, UNLOAD_RECOVERY
, false))
9346 bp
->recovery_state
= BNX2X_RECOVERY_WAIT
;
9348 /* Ensure "is_leader", MCP command sequence and
9349 * "recovery_state" update values are seen on other
9355 case BNX2X_RECOVERY_WAIT
:
9356 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_WAIT\n");
9357 if (bp
->is_leader
) {
9358 int other_engine
= BP_PATH(bp
) ? 0 : 1;
9359 bool other_load_status
=
9360 bnx2x_get_load_status(bp
, other_engine
);
9362 bnx2x_get_load_status(bp
, BP_PATH(bp
));
9363 global
= bnx2x_reset_is_global(bp
);
9366 * In case of a parity in a global block, let
9367 * the first leader that performs a
9368 * leader_reset() reset the global blocks in
9369 * order to clear global attentions. Otherwise
9370 * the the gates will remain closed for that
9374 (global
&& other_load_status
)) {
9375 /* Wait until all other functions get
9378 schedule_delayed_work(&bp
->sp_rtnl_task
,
9382 /* If all other functions got down -
9383 * try to bring the chip back to
9384 * normal. In any case it's an exit
9385 * point for a leader.
9387 if (bnx2x_leader_reset(bp
)) {
9388 bnx2x_recovery_failed(bp
);
9392 /* If we are here, means that the
9393 * leader has succeeded and doesn't
9394 * want to be a leader any more. Try
9395 * to continue as a none-leader.
9399 } else { /* non-leader */
9400 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
))) {
9401 /* Try to get a LEADER_LOCK HW lock as
9402 * long as a former leader may have
9403 * been unloaded by the user or
9404 * released a leadership by another
9407 if (bnx2x_trylock_leader_lock(bp
)) {
9408 /* I'm a leader now! Restart a
9415 schedule_delayed_work(&bp
->sp_rtnl_task
,
9421 * If there was a global attention, wait
9422 * for it to be cleared.
9424 if (bnx2x_reset_is_global(bp
)) {
9425 schedule_delayed_work(
9432 bp
->eth_stats
.recoverable_error
;
9434 bp
->eth_stats
.unrecoverable_error
;
9435 bp
->recovery_state
=
9436 BNX2X_RECOVERY_NIC_LOADING
;
9437 if (bnx2x_nic_load(bp
, LOAD_NORMAL
)) {
9438 error_unrecovered
++;
9440 "Recovery failed. Power cycle needed\n");
9441 /* Disconnect this device */
9442 netif_device_detach(bp
->dev
);
9443 /* Shut down the power */
9444 bnx2x_set_power_state(
9448 bp
->recovery_state
=
9449 BNX2X_RECOVERY_DONE
;
9453 bp
->eth_stats
.recoverable_error
=
9455 bp
->eth_stats
.unrecoverable_error
=
9467 static int bnx2x_close(struct net_device
*dev
);
9469 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9470 * scheduled on a general queue in order to prevent a dead lock.
9472 static void bnx2x_sp_rtnl_task(struct work_struct
*work
)
9474 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_rtnl_task
.work
);
9478 if (!netif_running(bp
->dev
)) {
9483 /* if stop on error is defined no recovery flows should be executed */
9484 #ifdef BNX2X_STOP_ON_ERROR
9485 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9486 "you will need to reboot when done\n");
9487 goto sp_rtnl_not_reset
;
9490 if (unlikely(bp
->recovery_state
!= BNX2X_RECOVERY_DONE
)) {
9492 * Clear all pending SP commands as we are going to reset the
9495 bp
->sp_rtnl_state
= 0;
9498 bnx2x_parity_recover(bp
);
9504 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT
, &bp
->sp_rtnl_state
)) {
9506 * Clear all pending SP commands as we are going to reset the
9509 bp
->sp_rtnl_state
= 0;
9512 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, true);
9513 bnx2x_nic_load(bp
, LOAD_NORMAL
);
9518 #ifdef BNX2X_STOP_ON_ERROR
9521 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC
, &bp
->sp_rtnl_state
))
9522 bnx2x_setup_tc(bp
->dev
, bp
->dcbx_port_params
.ets
.num_of_cos
);
9523 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE
, &bp
->sp_rtnl_state
))
9524 bnx2x_after_function_update(bp
);
9526 * in case of fan failure we need to reset id if the "stop on error"
9527 * debug flag is set, since we trying to prevent permanent overheating
9530 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
)) {
9531 DP(NETIF_MSG_HW
, "fan failure detected. Unloading driver\n");
9532 netif_device_detach(bp
->dev
);
9533 bnx2x_close(bp
->dev
);
9538 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST
, &bp
->sp_rtnl_state
)) {
9540 "sending set mcast vf pf channel message from rtnl sp-task\n");
9541 bnx2x_vfpf_set_mcast(bp
->dev
);
9544 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE
,
9545 &bp
->sp_rtnl_state
)) {
9547 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9548 bnx2x_vfpf_storm_rx_mode(bp
);
9551 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN
,
9552 &bp
->sp_rtnl_state
))
9553 bnx2x_pf_set_vfs_vlan(bp
);
9555 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9556 * can be called from other contexts as well)
9560 /* enable SR-IOV if applicable */
9561 if (IS_SRIOV(bp
) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV
,
9562 &bp
->sp_rtnl_state
)) {
9563 bnx2x_disable_sriov(bp
);
9564 bnx2x_enable_sriov(bp
);
9568 static void bnx2x_period_task(struct work_struct
*work
)
9570 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, period_task
.work
);
9572 if (!netif_running(bp
->dev
))
9573 goto period_task_exit
;
9575 if (CHIP_REV_IS_SLOW(bp
)) {
9576 BNX2X_ERR("period task called on emulation, ignoring\n");
9577 goto period_task_exit
;
9580 bnx2x_acquire_phy_lock(bp
);
9582 * The barrier is needed to ensure the ordering between the writing to
9583 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9588 bnx2x_period_func(&bp
->link_params
, &bp
->link_vars
);
9590 /* Re-queue task in 1 sec */
9591 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 1*HZ
);
9594 bnx2x_release_phy_lock(bp
);
9600 * Init service functions
9603 u32
bnx2x_get_pretend_reg(struct bnx2x
*bp
)
9605 u32 base
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
9606 u32 stride
= PXP2_REG_PGL_PRETEND_FUNC_F1
- base
;
9607 return base
+ (BP_ABS_FUNC(bp
)) * stride
;
9610 static void bnx2x_prev_unload_close_mac(struct bnx2x
*bp
,
9611 struct bnx2x_mac_vals
*vals
)
9613 u32 val
, base_addr
, offset
, mask
, reset_reg
;
9614 bool mac_stopped
= false;
9615 u8 port
= BP_PORT(bp
);
9617 /* reset addresses as they also mark which values were changed */
9618 vals
->bmac_addr
= 0;
9619 vals
->umac_addr
= 0;
9620 vals
->xmac_addr
= 0;
9621 vals
->emac_addr
= 0;
9623 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_2
);
9625 if (!CHIP_IS_E3(bp
)) {
9626 val
= REG_RD(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4);
9627 mask
= MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
;
9628 if ((mask
& reset_reg
) && val
) {
9630 BNX2X_DEV_INFO("Disable bmac Rx\n");
9631 base_addr
= BP_PORT(bp
) ? NIG_REG_INGRESS_BMAC1_MEM
9632 : NIG_REG_INGRESS_BMAC0_MEM
;
9633 offset
= CHIP_IS_E2(bp
) ? BIGMAC2_REGISTER_BMAC_CONTROL
9634 : BIGMAC_REGISTER_BMAC_CONTROL
;
9637 * use rd/wr since we cannot use dmae. This is safe
9638 * since MCP won't access the bus due to the request
9639 * to unload, and no function on the path can be
9640 * loaded at this time.
9642 wb_data
[0] = REG_RD(bp
, base_addr
+ offset
);
9643 wb_data
[1] = REG_RD(bp
, base_addr
+ offset
+ 0x4);
9644 vals
->bmac_addr
= base_addr
+ offset
;
9645 vals
->bmac_val
[0] = wb_data
[0];
9646 vals
->bmac_val
[1] = wb_data
[1];
9647 wb_data
[0] &= ~BMAC_CONTROL_RX_ENABLE
;
9648 REG_WR(bp
, vals
->bmac_addr
, wb_data
[0]);
9649 REG_WR(bp
, vals
->bmac_addr
+ 0x4, wb_data
[1]);
9652 BNX2X_DEV_INFO("Disable emac Rx\n");
9653 vals
->emac_addr
= NIG_REG_NIG_EMAC0_EN
+ BP_PORT(bp
)*4;
9654 vals
->emac_val
= REG_RD(bp
, vals
->emac_addr
);
9655 REG_WR(bp
, vals
->emac_addr
, 0);
9658 if (reset_reg
& MISC_REGISTERS_RESET_REG_2_XMAC
) {
9659 BNX2X_DEV_INFO("Disable xmac Rx\n");
9660 base_addr
= BP_PORT(bp
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
9661 val
= REG_RD(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
);
9662 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
9664 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
9666 vals
->xmac_addr
= base_addr
+ XMAC_REG_CTRL
;
9667 vals
->xmac_val
= REG_RD(bp
, vals
->xmac_addr
);
9668 REG_WR(bp
, vals
->xmac_addr
, 0);
9671 mask
= MISC_REGISTERS_RESET_REG_2_UMAC0
<< port
;
9672 if (mask
& reset_reg
) {
9673 BNX2X_DEV_INFO("Disable umac Rx\n");
9674 base_addr
= BP_PORT(bp
) ? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
9675 vals
->umac_addr
= base_addr
+ UMAC_REG_COMMAND_CONFIG
;
9676 vals
->umac_val
= REG_RD(bp
, vals
->umac_addr
);
9677 REG_WR(bp
, vals
->umac_addr
, 0);
9687 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9688 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9689 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9690 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9692 static void bnx2x_prev_unload_undi_inc(struct bnx2x
*bp
, u8 port
, u8 inc
)
9695 u32 tmp_reg
= REG_RD(bp
, BNX2X_PREV_UNDI_PROD_ADDR(port
));
9697 rcq
= BNX2X_PREV_UNDI_RCQ(tmp_reg
) + inc
;
9698 bd
= BNX2X_PREV_UNDI_BD(tmp_reg
) + inc
;
9700 tmp_reg
= BNX2X_PREV_UNDI_PROD(rcq
, bd
);
9701 REG_WR(bp
, BNX2X_PREV_UNDI_PROD_ADDR(port
), tmp_reg
);
9703 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9707 static int bnx2x_prev_mcp_done(struct bnx2x
*bp
)
9709 u32 rc
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
,
9710 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
);
9712 BNX2X_ERR("MCP response failure, aborting\n");
9719 static struct bnx2x_prev_path_list
*
9720 bnx2x_prev_path_get_entry(struct bnx2x
*bp
)
9722 struct bnx2x_prev_path_list
*tmp_list
;
9724 list_for_each_entry(tmp_list
, &bnx2x_prev_list
, list
)
9725 if (PCI_SLOT(bp
->pdev
->devfn
) == tmp_list
->slot
&&
9726 bp
->pdev
->bus
->number
== tmp_list
->bus
&&
9727 BP_PATH(bp
) == tmp_list
->path
)
9733 static int bnx2x_prev_path_mark_eeh(struct bnx2x
*bp
)
9735 struct bnx2x_prev_path_list
*tmp_list
;
9738 rc
= down_interruptible(&bnx2x_prev_sem
);
9740 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
9744 tmp_list
= bnx2x_prev_path_get_entry(bp
);
9749 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9753 up(&bnx2x_prev_sem
);
9758 static bool bnx2x_prev_is_path_marked(struct bnx2x
*bp
)
9760 struct bnx2x_prev_path_list
*tmp_list
;
9763 if (down_trylock(&bnx2x_prev_sem
))
9766 tmp_list
= bnx2x_prev_path_get_entry(bp
);
9768 if (tmp_list
->aer
) {
9769 DP(NETIF_MSG_HW
, "Path %d was marked by AER\n",
9773 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9778 up(&bnx2x_prev_sem
);
9783 bool bnx2x_port_after_undi(struct bnx2x
*bp
)
9785 struct bnx2x_prev_path_list
*entry
;
9788 down(&bnx2x_prev_sem
);
9790 entry
= bnx2x_prev_path_get_entry(bp
);
9791 val
= !!(entry
&& (entry
->undi
& (1 << BP_PORT(bp
))));
9793 up(&bnx2x_prev_sem
);
9798 static int bnx2x_prev_mark_path(struct bnx2x
*bp
, bool after_undi
)
9800 struct bnx2x_prev_path_list
*tmp_list
;
9803 rc
= down_interruptible(&bnx2x_prev_sem
);
9805 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
9809 /* Check whether the entry for this path already exists */
9810 tmp_list
= bnx2x_prev_path_get_entry(bp
);
9812 if (!tmp_list
->aer
) {
9813 BNX2X_ERR("Re-Marking the path.\n");
9815 DP(NETIF_MSG_HW
, "Removing AER indication from path %d\n",
9819 up(&bnx2x_prev_sem
);
9822 up(&bnx2x_prev_sem
);
9824 /* Create an entry for this path and add it */
9825 tmp_list
= kmalloc(sizeof(struct bnx2x_prev_path_list
), GFP_KERNEL
);
9827 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9831 tmp_list
->bus
= bp
->pdev
->bus
->number
;
9832 tmp_list
->slot
= PCI_SLOT(bp
->pdev
->devfn
);
9833 tmp_list
->path
= BP_PATH(bp
);
9835 tmp_list
->undi
= after_undi
? (1 << BP_PORT(bp
)) : 0;
9837 rc
= down_interruptible(&bnx2x_prev_sem
);
9839 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
9842 DP(NETIF_MSG_HW
, "Marked path [%d] - finished previous unload\n",
9844 list_add(&tmp_list
->list
, &bnx2x_prev_list
);
9845 up(&bnx2x_prev_sem
);
9851 static int bnx2x_do_flr(struct bnx2x
*bp
)
9855 struct pci_dev
*dev
= bp
->pdev
;
9858 if (CHIP_IS_E1x(bp
)) {
9859 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9863 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9864 if (bp
->common
.bc_ver
< REQ_BC_VER_4_INITIATE_FLR
) {
9865 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9870 /* Wait for Transaction Pending bit clean */
9871 for (i
= 0; i
< 4; i
++) {
9873 msleep((1 << (i
- 1)) * 100);
9875 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &status
);
9876 if (!(status
& PCI_EXP_DEVSTA_TRPND
))
9881 "transaction is not cleared; proceeding with reset anyway\n");
9885 BNX2X_DEV_INFO("Initiating FLR\n");
9886 bnx2x_fw_command(bp
, DRV_MSG_CODE_INITIATE_FLR
, 0);
9891 static int bnx2x_prev_unload_uncommon(struct bnx2x
*bp
)
9895 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9897 /* Test if previous unload process was already finished for this path */
9898 if (bnx2x_prev_is_path_marked(bp
))
9899 return bnx2x_prev_mcp_done(bp
);
9901 BNX2X_DEV_INFO("Path is unmarked\n");
9903 /* If function has FLR capabilities, and existing FW version matches
9904 * the one required, then FLR will be sufficient to clean any residue
9905 * left by previous driver
9907 rc
= bnx2x_nic_load_analyze_req(bp
, FW_MSG_CODE_DRV_LOAD_FUNCTION
);
9910 /* fw version is good */
9911 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9912 rc
= bnx2x_do_flr(bp
);
9916 /* FLR was performed */
9917 BNX2X_DEV_INFO("FLR successful\n");
9921 BNX2X_DEV_INFO("Could not FLR\n");
9923 /* Close the MCP request, return failure*/
9924 rc
= bnx2x_prev_mcp_done(bp
);
9926 rc
= BNX2X_PREV_WAIT_NEEDED
;
9931 static int bnx2x_prev_unload_common(struct bnx2x
*bp
)
9933 u32 reset_reg
, tmp_reg
= 0, rc
;
9934 bool prev_undi
= false;
9935 struct bnx2x_mac_vals mac_vals
;
9937 /* It is possible a previous function received 'common' answer,
9938 * but hasn't loaded yet, therefore creating a scenario of
9939 * multiple functions receiving 'common' on the same path.
9941 BNX2X_DEV_INFO("Common unload Flow\n");
9943 memset(&mac_vals
, 0, sizeof(mac_vals
));
9945 if (bnx2x_prev_is_path_marked(bp
))
9946 return bnx2x_prev_mcp_done(bp
);
9948 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_1
);
9950 /* Reset should be performed after BRB is emptied */
9951 if (reset_reg
& MISC_REGISTERS_RESET_REG_1_RST_BRB1
) {
9952 u32 timer_count
= 1000;
9954 /* Close the MAC Rx to prevent BRB from filling up */
9955 bnx2x_prev_unload_close_mac(bp
, &mac_vals
);
9957 /* close LLH filters towards the BRB */
9958 bnx2x_set_rx_filter(&bp
->link_params
, 0);
9960 /* Check if the UNDI driver was previously loaded
9961 * UNDI driver initializes CID offset for normal bell to 0x7
9963 if (reset_reg
& MISC_REGISTERS_RESET_REG_1_RST_DORQ
) {
9964 tmp_reg
= REG_RD(bp
, DORQ_REG_NORM_CID_OFST
);
9965 if (tmp_reg
== 0x7) {
9966 BNX2X_DEV_INFO("UNDI previously loaded\n");
9968 /* clear the UNDI indication */
9969 REG_WR(bp
, DORQ_REG_NORM_CID_OFST
, 0);
9970 /* clear possible idle check errors */
9971 REG_RD(bp
, NIG_REG_NIG_INT_STS_CLR_0
);
9974 if (!CHIP_IS_E1x(bp
))
9975 /* block FW from writing to host */
9976 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
9978 /* wait until BRB is empty */
9979 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
9980 while (timer_count
) {
9981 u32 prev_brb
= tmp_reg
;
9983 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
9987 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg
);
9989 /* reset timer as long as BRB actually gets emptied */
9990 if (prev_brb
> tmp_reg
)
9995 /* If UNDI resides in memory, manually increment it */
9997 bnx2x_prev_unload_undi_inc(bp
, BP_PORT(bp
), 1);
10003 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10007 /* No packets are in the pipeline, path is ready for reset */
10008 bnx2x_reset_common(bp
);
10010 if (mac_vals
.xmac_addr
)
10011 REG_WR(bp
, mac_vals
.xmac_addr
, mac_vals
.xmac_val
);
10012 if (mac_vals
.umac_addr
)
10013 REG_WR(bp
, mac_vals
.umac_addr
, mac_vals
.umac_val
);
10014 if (mac_vals
.emac_addr
)
10015 REG_WR(bp
, mac_vals
.emac_addr
, mac_vals
.emac_val
);
10016 if (mac_vals
.bmac_addr
) {
10017 REG_WR(bp
, mac_vals
.bmac_addr
, mac_vals
.bmac_val
[0]);
10018 REG_WR(bp
, mac_vals
.bmac_addr
+ 4, mac_vals
.bmac_val
[1]);
10021 rc
= bnx2x_prev_mark_path(bp
, prev_undi
);
10023 bnx2x_prev_mcp_done(bp
);
10027 return bnx2x_prev_mcp_done(bp
);
10030 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10031 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10032 * the addresses of the transaction, resulting in was-error bit set in the pci
10033 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10034 * to clear the interrupt which detected this from the pglueb and the was done
10037 static void bnx2x_prev_interrupted_dmae(struct bnx2x
*bp
)
10039 if (!CHIP_IS_E1x(bp
)) {
10040 u32 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS
);
10041 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
) {
10043 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10044 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
,
10050 static int bnx2x_prev_unload(struct bnx2x
*bp
)
10052 int time_counter
= 10;
10053 u32 rc
, fw
, hw_lock_reg
, hw_lock_val
;
10054 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10056 /* clear hw from errors which may have resulted from an interrupted
10057 * dmae transaction.
10059 bnx2x_prev_interrupted_dmae(bp
);
10061 /* Release previously held locks */
10062 hw_lock_reg
= (BP_FUNC(bp
) <= 5) ?
10063 (MISC_REG_DRIVER_CONTROL_1
+ BP_FUNC(bp
) * 8) :
10064 (MISC_REG_DRIVER_CONTROL_7
+ (BP_FUNC(bp
) - 6) * 8);
10066 hw_lock_val
= (REG_RD(bp
, hw_lock_reg
));
10068 if (hw_lock_val
& HW_LOCK_RESOURCE_NVRAM
) {
10069 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10070 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
10071 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1
<< BP_PORT(bp
)));
10074 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10075 REG_WR(bp
, hw_lock_reg
, 0xffffffff);
10077 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10079 if (MCPR_ACCESS_LOCK_LOCK
& REG_RD(bp
, MCP_REG_MCPR_ACCESS_LOCK
)) {
10080 BNX2X_DEV_INFO("Release previously held alr\n");
10081 REG_WR(bp
, MCP_REG_MCPR_ACCESS_LOCK
, 0);
10086 /* Lock MCP using an unload request */
10087 fw
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
, 0);
10089 BNX2X_ERR("MCP response failure, aborting\n");
10094 rc
= down_interruptible(&bnx2x_prev_sem
);
10096 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10099 /* If Path is marked by EEH, ignore unload status */
10100 aer
= !!(bnx2x_prev_path_get_entry(bp
) &&
10101 bnx2x_prev_path_get_entry(bp
)->aer
);
10102 up(&bnx2x_prev_sem
);
10105 if (fw
== FW_MSG_CODE_DRV_UNLOAD_COMMON
|| aer
) {
10106 rc
= bnx2x_prev_unload_common(bp
);
10110 /* non-common reply from MCP night require looping */
10111 rc
= bnx2x_prev_unload_uncommon(bp
);
10112 if (rc
!= BNX2X_PREV_WAIT_NEEDED
)
10116 } while (--time_counter
);
10118 if (!time_counter
|| rc
) {
10119 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10123 /* Mark function if its port was used to boot from SAN */
10124 if (bnx2x_port_after_undi(bp
))
10125 bp
->link_params
.feature_config_flags
|=
10126 FEATURE_CONFIG_BOOT_FROM_SAN
;
10128 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc
);
10133 static void bnx2x_get_common_hwinfo(struct bnx2x
*bp
)
10135 u32 val
, val2
, val3
, val4
, id
, boot_mode
;
10138 /* Get the chip revision id and number. */
10139 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10140 val
= REG_RD(bp
, MISC_REG_CHIP_NUM
);
10141 id
= ((val
& 0xffff) << 16);
10142 val
= REG_RD(bp
, MISC_REG_CHIP_REV
);
10143 id
|= ((val
& 0xf) << 12);
10145 /* Metal is read from PCI regs, but we can't access >=0x400 from
10146 * the configuration space (so we need to reg_rd)
10148 val
= REG_RD(bp
, PCICFG_OFFSET
+ PCI_ID_VAL3
);
10149 id
|= (((val
>> 24) & 0xf) << 4);
10150 val
= REG_RD(bp
, MISC_REG_BOND_ID
);
10152 bp
->common
.chip_id
= id
;
10154 /* force 57811 according to MISC register */
10155 if (REG_RD(bp
, MISC_REG_CHIP_TYPE
) & MISC_REG_CHIP_TYPE_57811_MASK
) {
10156 if (CHIP_IS_57810(bp
))
10157 bp
->common
.chip_id
= (CHIP_NUM_57811
<< 16) |
10158 (bp
->common
.chip_id
& 0x0000FFFF);
10159 else if (CHIP_IS_57810_MF(bp
))
10160 bp
->common
.chip_id
= (CHIP_NUM_57811_MF
<< 16) |
10161 (bp
->common
.chip_id
& 0x0000FFFF);
10162 bp
->common
.chip_id
|= 0x1;
10165 /* Set doorbell size */
10166 bp
->db_size
= (1 << BNX2X_DB_SHIFT
);
10168 if (!CHIP_IS_E1x(bp
)) {
10169 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
);
10170 if ((val
& 1) == 0)
10171 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN
);
10173 val
= (val
>> 1) & 1;
10174 BNX2X_DEV_INFO("chip is in %s\n", val
? "4_PORT_MODE" :
10176 bp
->common
.chip_port_mode
= val
? CHIP_4_PORT_MODE
:
10179 if (CHIP_MODE_IS_4_PORT(bp
))
10180 bp
->pfid
= (bp
->pf_num
>> 1); /* 0..3 */
10182 bp
->pfid
= (bp
->pf_num
& 0x6); /* 0, 2, 4, 6 */
10184 bp
->common
.chip_port_mode
= CHIP_PORT_MODE_NONE
; /* N/A */
10185 bp
->pfid
= bp
->pf_num
; /* 0..7 */
10188 BNX2X_DEV_INFO("pf_id: %x", bp
->pfid
);
10190 bp
->link_params
.chip_id
= bp
->common
.chip_id
;
10191 BNX2X_DEV_INFO("chip ID is 0x%x\n", id
);
10193 val
= (REG_RD(bp
, 0x2874) & 0x55);
10194 if ((bp
->common
.chip_id
& 0x1) ||
10195 (CHIP_IS_E1(bp
) && val
) || (CHIP_IS_E1H(bp
) && (val
== 0x55))) {
10196 bp
->flags
|= ONE_PORT_FLAG
;
10197 BNX2X_DEV_INFO("single port device\n");
10200 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_CFG4
);
10201 bp
->common
.flash_size
= (BNX2X_NVRAM_1MB_SIZE
<<
10202 (val
& MCPR_NVM_CFG4_FLASH_SIZE
));
10203 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10204 bp
->common
.flash_size
, bp
->common
.flash_size
);
10206 bnx2x_init_shmem(bp
);
10210 bp
->common
.shmem2_base
= REG_RD(bp
, (BP_PATH(bp
) ?
10211 MISC_REG_GENERIC_CR_1
:
10212 MISC_REG_GENERIC_CR_0
));
10214 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
10215 bp
->link_params
.shmem2_base
= bp
->common
.shmem2_base
;
10216 if (SHMEM2_RD(bp
, size
) >
10217 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
10218 bp
->link_params
.lfa_base
=
10219 REG_RD(bp
, bp
->common
.shmem2_base
+
10220 (u32
)offsetof(struct shmem2_region
,
10221 lfa_host_addr
[BP_PORT(bp
)]));
10223 bp
->link_params
.lfa_base
= 0;
10224 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10225 bp
->common
.shmem_base
, bp
->common
.shmem2_base
);
10227 if (!bp
->common
.shmem_base
) {
10228 BNX2X_DEV_INFO("MCP not active\n");
10229 bp
->flags
|= NO_MCP_FLAG
;
10233 bp
->common
.hw_config
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config
);
10234 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp
->common
.hw_config
);
10236 bp
->link_params
.hw_led_mode
= ((bp
->common
.hw_config
&
10237 SHARED_HW_CFG_LED_MODE_MASK
) >>
10238 SHARED_HW_CFG_LED_MODE_SHIFT
);
10240 bp
->link_params
.feature_config_flags
= 0;
10241 val
= SHMEM_RD(bp
, dev_info
.shared_feature_config
.config
);
10242 if (val
& SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED
)
10243 bp
->link_params
.feature_config_flags
|=
10244 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
10246 bp
->link_params
.feature_config_flags
&=
10247 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
10249 val
= SHMEM_RD(bp
, dev_info
.bc_rev
) >> 8;
10250 bp
->common
.bc_ver
= val
;
10251 BNX2X_DEV_INFO("bc_ver %X\n", val
);
10252 if (val
< BNX2X_BC_VER
) {
10253 /* for now only warn
10254 * later we might need to enforce this */
10255 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10256 BNX2X_BC_VER
, val
);
10258 bp
->link_params
.feature_config_flags
|=
10259 (val
>= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL
) ?
10260 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
: 0;
10262 bp
->link_params
.feature_config_flags
|=
10263 (val
>= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL
) ?
10264 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
: 0;
10265 bp
->link_params
.feature_config_flags
|=
10266 (val
>= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED
) ?
10267 FEATURE_CONFIG_BC_SUPPORTS_AFEX
: 0;
10268 bp
->link_params
.feature_config_flags
|=
10269 (val
>= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED
) ?
10270 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
: 0;
10272 bp
->link_params
.feature_config_flags
|=
10273 (val
>= REQ_BC_VER_4_MT_SUPPORTED
) ?
10274 FEATURE_CONFIG_MT_SUPPORT
: 0;
10276 bp
->flags
|= (val
>= REQ_BC_VER_4_PFC_STATS_SUPPORTED
) ?
10277 BC_SUPPORTS_PFC_STATS
: 0;
10279 bp
->flags
|= (val
>= REQ_BC_VER_4_FCOE_FEATURES
) ?
10280 BC_SUPPORTS_FCOE_FEATURES
: 0;
10282 bp
->flags
|= (val
>= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF
) ?
10283 BC_SUPPORTS_DCBX_MSG_NON_PMF
: 0;
10284 boot_mode
= SHMEM_RD(bp
,
10285 dev_info
.port_feature_config
[BP_PORT(bp
)].mba_config
) &
10286 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK
;
10287 switch (boot_mode
) {
10288 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE
:
10289 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_PXE
;
10291 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB
:
10292 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_ISCSI
;
10294 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT
:
10295 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_FCOE
;
10297 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE
:
10298 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_NONE
;
10302 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_PMC
, &pmc
);
10303 bp
->flags
|= (pmc
& PCI_PM_CAP_PME_D3cold
) ? 0 : NO_WOL_FLAG
;
10305 BNX2X_DEV_INFO("%sWoL capable\n",
10306 (bp
->flags
& NO_WOL_FLAG
) ? "not " : "");
10308 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
);
10309 val2
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[4]);
10310 val3
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[8]);
10311 val4
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[12]);
10313 dev_info(&bp
->pdev
->dev
, "part number %X-%X-%X-%X\n",
10314 val
, val2
, val3
, val4
);
10317 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10318 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10320 static int bnx2x_get_igu_cam_info(struct bnx2x
*bp
)
10322 int pfid
= BP_FUNC(bp
);
10325 u8 fid
, igu_sb_cnt
= 0;
10327 bp
->igu_base_sb
= 0xff;
10328 if (CHIP_INT_MODE_IS_BC(bp
)) {
10329 int vn
= BP_VN(bp
);
10330 igu_sb_cnt
= bp
->igu_sb_cnt
;
10331 bp
->igu_base_sb
= (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
) *
10334 bp
->igu_dsb_id
= E1HVN_MAX
* FP_SB_MAX_E1x
+
10335 (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
);
10340 /* IGU in normal mode - read CAM */
10341 for (igu_sb_id
= 0; igu_sb_id
< IGU_REG_MAPPING_MEMORY_SIZE
;
10343 val
= REG_RD(bp
, IGU_REG_MAPPING_MEMORY
+ igu_sb_id
* 4);
10344 if (!(val
& IGU_REG_MAPPING_MEMORY_VALID
))
10346 fid
= IGU_FID(val
);
10347 if ((fid
& IGU_FID_ENCODE_IS_PF
)) {
10348 if ((fid
& IGU_FID_PF_NUM_MASK
) != pfid
)
10350 if (IGU_VEC(val
) == 0)
10351 /* default status block */
10352 bp
->igu_dsb_id
= igu_sb_id
;
10354 if (bp
->igu_base_sb
== 0xff)
10355 bp
->igu_base_sb
= igu_sb_id
;
10361 #ifdef CONFIG_PCI_MSI
10362 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10363 * optional that number of CAM entries will not be equal to the value
10364 * advertised in PCI.
10365 * Driver should use the minimal value of both as the actual status
10368 bp
->igu_sb_cnt
= min_t(int, bp
->igu_sb_cnt
, igu_sb_cnt
);
10371 if (igu_sb_cnt
== 0) {
10372 BNX2X_ERR("CAM configuration error\n");
10379 static void bnx2x_link_settings_supported(struct bnx2x
*bp
, u32 switch_cfg
)
10381 int cfg_size
= 0, idx
, port
= BP_PORT(bp
);
10383 /* Aggregation of supported attributes of all external phys */
10384 bp
->port
.supported
[0] = 0;
10385 bp
->port
.supported
[1] = 0;
10386 switch (bp
->link_params
.num_phys
) {
10388 bp
->port
.supported
[0] = bp
->link_params
.phy
[INT_PHY
].supported
;
10392 bp
->port
.supported
[0] = bp
->link_params
.phy
[EXT_PHY1
].supported
;
10396 if (bp
->link_params
.multi_phy_config
&
10397 PORT_HW_CFG_PHY_SWAPPED_ENABLED
) {
10398 bp
->port
.supported
[1] =
10399 bp
->link_params
.phy
[EXT_PHY1
].supported
;
10400 bp
->port
.supported
[0] =
10401 bp
->link_params
.phy
[EXT_PHY2
].supported
;
10403 bp
->port
.supported
[0] =
10404 bp
->link_params
.phy
[EXT_PHY1
].supported
;
10405 bp
->port
.supported
[1] =
10406 bp
->link_params
.phy
[EXT_PHY2
].supported
;
10412 if (!(bp
->port
.supported
[0] || bp
->port
.supported
[1])) {
10413 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10415 dev_info
.port_hw_config
[port
].external_phy_config
),
10417 dev_info
.port_hw_config
[port
].external_phy_config2
));
10421 if (CHIP_IS_E3(bp
))
10422 bp
->port
.phy_addr
= REG_RD(bp
, MISC_REG_WC0_CTRL_PHY_ADDR
);
10424 switch (switch_cfg
) {
10425 case SWITCH_CFG_1G
:
10426 bp
->port
.phy_addr
= REG_RD(
10427 bp
, NIG_REG_SERDES0_CTRL_PHY_ADDR
+ port
*0x10);
10429 case SWITCH_CFG_10G
:
10430 bp
->port
.phy_addr
= REG_RD(
10431 bp
, NIG_REG_XGXS0_CTRL_PHY_ADDR
+ port
*0x18);
10434 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10435 bp
->port
.link_config
[0]);
10439 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
10440 /* mask what we support according to speed_cap_mask per configuration */
10441 for (idx
= 0; idx
< cfg_size
; idx
++) {
10442 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10443 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
))
10444 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Half
;
10446 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10447 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
))
10448 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Full
;
10450 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10451 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))
10452 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Half
;
10454 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10455 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
))
10456 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Full
;
10458 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10459 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))
10460 bp
->port
.supported
[idx
] &= ~(SUPPORTED_1000baseT_Half
|
10461 SUPPORTED_1000baseT_Full
);
10463 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10464 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
10465 bp
->port
.supported
[idx
] &= ~SUPPORTED_2500baseX_Full
;
10467 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
10468 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
))
10469 bp
->port
.supported
[idx
] &= ~SUPPORTED_10000baseT_Full
;
10473 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp
->port
.supported
[0],
10474 bp
->port
.supported
[1]);
10477 static void bnx2x_link_settings_requested(struct bnx2x
*bp
)
10479 u32 link_config
, idx
, cfg_size
= 0;
10480 bp
->port
.advertising
[0] = 0;
10481 bp
->port
.advertising
[1] = 0;
10482 switch (bp
->link_params
.num_phys
) {
10491 for (idx
= 0; idx
< cfg_size
; idx
++) {
10492 bp
->link_params
.req_duplex
[idx
] = DUPLEX_FULL
;
10493 link_config
= bp
->port
.link_config
[idx
];
10494 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
10495 case PORT_FEATURE_LINK_SPEED_AUTO
:
10496 if (bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
) {
10497 bp
->link_params
.req_line_speed
[idx
] =
10499 bp
->port
.advertising
[idx
] |=
10500 bp
->port
.supported
[idx
];
10501 if (bp
->link_params
.phy
[EXT_PHY1
].type
==
10502 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
)
10503 bp
->port
.advertising
[idx
] |=
10504 (SUPPORTED_100baseT_Half
|
10505 SUPPORTED_100baseT_Full
);
10507 /* force 10G, no AN */
10508 bp
->link_params
.req_line_speed
[idx
] =
10510 bp
->port
.advertising
[idx
] |=
10511 (ADVERTISED_10000baseT_Full
|
10517 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
10518 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Full
) {
10519 bp
->link_params
.req_line_speed
[idx
] =
10521 bp
->port
.advertising
[idx
] |=
10522 (ADVERTISED_10baseT_Full
|
10525 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10527 bp
->link_params
.speed_cap_mask
[idx
]);
10532 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
10533 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Half
) {
10534 bp
->link_params
.req_line_speed
[idx
] =
10536 bp
->link_params
.req_duplex
[idx
] =
10538 bp
->port
.advertising
[idx
] |=
10539 (ADVERTISED_10baseT_Half
|
10542 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10544 bp
->link_params
.speed_cap_mask
[idx
]);
10549 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
10550 if (bp
->port
.supported
[idx
] &
10551 SUPPORTED_100baseT_Full
) {
10552 bp
->link_params
.req_line_speed
[idx
] =
10554 bp
->port
.advertising
[idx
] |=
10555 (ADVERTISED_100baseT_Full
|
10558 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10560 bp
->link_params
.speed_cap_mask
[idx
]);
10565 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
10566 if (bp
->port
.supported
[idx
] &
10567 SUPPORTED_100baseT_Half
) {
10568 bp
->link_params
.req_line_speed
[idx
] =
10570 bp
->link_params
.req_duplex
[idx
] =
10572 bp
->port
.advertising
[idx
] |=
10573 (ADVERTISED_100baseT_Half
|
10576 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10578 bp
->link_params
.speed_cap_mask
[idx
]);
10583 case PORT_FEATURE_LINK_SPEED_1G
:
10584 if (bp
->port
.supported
[idx
] &
10585 SUPPORTED_1000baseT_Full
) {
10586 bp
->link_params
.req_line_speed
[idx
] =
10588 bp
->port
.advertising
[idx
] |=
10589 (ADVERTISED_1000baseT_Full
|
10592 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10594 bp
->link_params
.speed_cap_mask
[idx
]);
10599 case PORT_FEATURE_LINK_SPEED_2_5G
:
10600 if (bp
->port
.supported
[idx
] &
10601 SUPPORTED_2500baseX_Full
) {
10602 bp
->link_params
.req_line_speed
[idx
] =
10604 bp
->port
.advertising
[idx
] |=
10605 (ADVERTISED_2500baseX_Full
|
10608 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10610 bp
->link_params
.speed_cap_mask
[idx
]);
10615 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
10616 if (bp
->port
.supported
[idx
] &
10617 SUPPORTED_10000baseT_Full
) {
10618 bp
->link_params
.req_line_speed
[idx
] =
10620 bp
->port
.advertising
[idx
] |=
10621 (ADVERTISED_10000baseT_Full
|
10624 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10626 bp
->link_params
.speed_cap_mask
[idx
]);
10630 case PORT_FEATURE_LINK_SPEED_20G
:
10631 bp
->link_params
.req_line_speed
[idx
] = SPEED_20000
;
10635 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10637 bp
->link_params
.req_line_speed
[idx
] =
10639 bp
->port
.advertising
[idx
] =
10640 bp
->port
.supported
[idx
];
10644 bp
->link_params
.req_flow_ctrl
[idx
] = (link_config
&
10645 PORT_FEATURE_FLOW_CONTROL_MASK
);
10646 if (bp
->link_params
.req_flow_ctrl
[idx
] ==
10647 BNX2X_FLOW_CTRL_AUTO
) {
10648 if (!(bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
))
10649 bp
->link_params
.req_flow_ctrl
[idx
] =
10650 BNX2X_FLOW_CTRL_NONE
;
10652 bnx2x_set_requested_fc(bp
);
10655 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10656 bp
->link_params
.req_line_speed
[idx
],
10657 bp
->link_params
.req_duplex
[idx
],
10658 bp
->link_params
.req_flow_ctrl
[idx
],
10659 bp
->port
.advertising
[idx
]);
10663 static void bnx2x_set_mac_buf(u8
*mac_buf
, u32 mac_lo
, u16 mac_hi
)
10665 __be16 mac_hi_be
= cpu_to_be16(mac_hi
);
10666 __be32 mac_lo_be
= cpu_to_be32(mac_lo
);
10667 memcpy(mac_buf
, &mac_hi_be
, sizeof(mac_hi_be
));
10668 memcpy(mac_buf
+ sizeof(mac_hi_be
), &mac_lo_be
, sizeof(mac_lo_be
));
10671 static void bnx2x_get_port_hwinfo(struct bnx2x
*bp
)
10673 int port
= BP_PORT(bp
);
10675 u32 ext_phy_type
, ext_phy_config
, eee_mode
;
10677 bp
->link_params
.bp
= bp
;
10678 bp
->link_params
.port
= port
;
10680 bp
->link_params
.lane_config
=
10681 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].lane_config
);
10683 bp
->link_params
.speed_cap_mask
[0] =
10685 dev_info
.port_hw_config
[port
].speed_capability_mask
) &
10686 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK
;
10687 bp
->link_params
.speed_cap_mask
[1] =
10689 dev_info
.port_hw_config
[port
].speed_capability_mask2
) &
10690 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK
;
10691 bp
->port
.link_config
[0] =
10692 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config
);
10694 bp
->port
.link_config
[1] =
10695 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config2
);
10697 bp
->link_params
.multi_phy_config
=
10698 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].multi_phy_config
);
10699 /* If the device is capable of WoL, set the default state according
10702 config
= SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].config
);
10703 bp
->wol
= (!(bp
->flags
& NO_WOL_FLAG
) &&
10704 (config
& PORT_FEATURE_WOL_ENABLED
));
10706 if ((config
& PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK
) ==
10707 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE
&& !IS_MF(bp
))
10708 bp
->flags
|= NO_ISCSI_FLAG
;
10709 if ((config
& PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK
) ==
10710 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI
&& !(IS_MF(bp
)))
10711 bp
->flags
|= NO_FCOE_FLAG
;
10713 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10714 bp
->link_params
.lane_config
,
10715 bp
->link_params
.speed_cap_mask
[0],
10716 bp
->port
.link_config
[0]);
10718 bp
->link_params
.switch_cfg
= (bp
->port
.link_config
[0] &
10719 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
10720 bnx2x_phy_probe(&bp
->link_params
);
10721 bnx2x_link_settings_supported(bp
, bp
->link_params
.switch_cfg
);
10723 bnx2x_link_settings_requested(bp
);
10726 * If connected directly, work with the internal PHY, otherwise, work
10727 * with the external PHY
10731 dev_info
.port_hw_config
[port
].external_phy_config
);
10732 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
10733 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
10734 bp
->mdio
.prtad
= bp
->port
.phy_addr
;
10736 else if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
10737 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
10739 XGXS_EXT_PHY_ADDR(ext_phy_config
);
10741 /* Configure link feature according to nvram value */
10742 eee_mode
= (((SHMEM_RD(bp
, dev_info
.
10743 port_feature_config
[port
].eee_power_mode
)) &
10744 PORT_FEAT_CFG_EEE_POWER_MODE_MASK
) >>
10745 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
);
10746 if (eee_mode
!= PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
) {
10747 bp
->link_params
.eee_mode
= EEE_MODE_ADV_LPI
|
10748 EEE_MODE_ENABLE_LPI
|
10749 EEE_MODE_OUTPUT_TIME
;
10751 bp
->link_params
.eee_mode
= 0;
10755 void bnx2x_get_iscsi_info(struct bnx2x
*bp
)
10757 u32 no_flags
= NO_ISCSI_FLAG
;
10758 int port
= BP_PORT(bp
);
10759 u32 max_iscsi_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
10760 drv_lic_key
[port
].max_iscsi_conn
);
10762 if (!CNIC_SUPPORT(bp
)) {
10763 bp
->flags
|= no_flags
;
10767 /* Get the number of maximum allowed iSCSI connections */
10768 bp
->cnic_eth_dev
.max_iscsi_conn
=
10769 (max_iscsi_conn
& BNX2X_MAX_ISCSI_INIT_CONN_MASK
) >>
10770 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT
;
10772 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10773 bp
->cnic_eth_dev
.max_iscsi_conn
);
10776 * If maximum allowed number of connections is zero -
10777 * disable the feature.
10779 if (!bp
->cnic_eth_dev
.max_iscsi_conn
)
10780 bp
->flags
|= no_flags
;
10784 static void bnx2x_get_ext_wwn_info(struct bnx2x
*bp
, int func
)
10787 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
10788 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_upper
);
10789 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
10790 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_lower
);
10793 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
10794 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_upper
);
10795 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
10796 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_lower
);
10799 static int bnx2x_shared_fcoe_funcs(struct bnx2x
*bp
)
10806 /* iterate over absolute function ids for this path: */
10807 for (fid
= BP_PATH(bp
); fid
< E2_FUNC_MAX
* 2; fid
+= 2) {
10808 if (IS_MF_SD(bp
)) {
10809 u32 cfg
= MF_CFG_RD(bp
,
10810 func_mf_config
[fid
].config
);
10812 if (!(cfg
& FUNC_MF_CFG_FUNC_HIDE
) &&
10813 ((cfg
& FUNC_MF_CFG_PROTOCOL_MASK
) ==
10814 FUNC_MF_CFG_PROTOCOL_FCOE
))
10817 u32 cfg
= MF_CFG_RD(bp
,
10818 func_ext_config
[fid
].
10821 if ((cfg
& MACP_FUNC_CFG_FLAGS_ENABLED
) &&
10822 (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
))
10827 int port
, port_cnt
= CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1;
10829 for (port
= 0; port
< port_cnt
; port
++) {
10830 u32 lic
= SHMEM_RD(bp
,
10831 drv_lic_key
[port
].max_fcoe_conn
) ^
10832 FW_ENCODE_32BIT_PATTERN
;
10841 static void bnx2x_get_fcoe_info(struct bnx2x
*bp
)
10843 int port
= BP_PORT(bp
);
10844 int func
= BP_ABS_FUNC(bp
);
10845 u32 max_fcoe_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
10846 drv_lic_key
[port
].max_fcoe_conn
);
10847 u8 num_fcoe_func
= bnx2x_shared_fcoe_funcs(bp
);
10849 if (!CNIC_SUPPORT(bp
)) {
10850 bp
->flags
|= NO_FCOE_FLAG
;
10854 /* Get the number of maximum allowed FCoE connections */
10855 bp
->cnic_eth_dev
.max_fcoe_conn
=
10856 (max_fcoe_conn
& BNX2X_MAX_FCOE_INIT_CONN_MASK
) >>
10857 BNX2X_MAX_FCOE_INIT_CONN_SHIFT
;
10859 /* Calculate the number of maximum allowed FCoE tasks */
10860 bp
->cnic_eth_dev
.max_fcoe_exchanges
= MAX_NUM_FCOE_TASKS_PER_ENGINE
;
10862 /* check if FCoE resources must be shared between different functions */
10864 bp
->cnic_eth_dev
.max_fcoe_exchanges
/= num_fcoe_func
;
10866 /* Read the WWN: */
10869 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
10871 dev_info
.port_hw_config
[port
].
10872 fcoe_wwn_port_name_upper
);
10873 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
10875 dev_info
.port_hw_config
[port
].
10876 fcoe_wwn_port_name_lower
);
10879 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
10881 dev_info
.port_hw_config
[port
].
10882 fcoe_wwn_node_name_upper
);
10883 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
10885 dev_info
.port_hw_config
[port
].
10886 fcoe_wwn_node_name_lower
);
10887 } else if (!IS_MF_SD(bp
)) {
10889 * Read the WWN info only if the FCoE feature is enabled for
10892 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp
) && !CHIP_IS_E1x(bp
))
10893 bnx2x_get_ext_wwn_info(bp
, func
);
10895 } else if (IS_MF_FCOE_SD(bp
) && !CHIP_IS_E1x(bp
)) {
10896 bnx2x_get_ext_wwn_info(bp
, func
);
10899 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp
->cnic_eth_dev
.max_fcoe_conn
);
10902 * If maximum allowed number of connections is zero -
10903 * disable the feature.
10905 if (!bp
->cnic_eth_dev
.max_fcoe_conn
)
10906 bp
->flags
|= NO_FCOE_FLAG
;
10909 static void bnx2x_get_cnic_info(struct bnx2x
*bp
)
10912 * iSCSI may be dynamically disabled but reading
10913 * info here we will decrease memory usage by driver
10914 * if the feature is disabled for good
10916 bnx2x_get_iscsi_info(bp
);
10917 bnx2x_get_fcoe_info(bp
);
10920 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x
*bp
)
10923 int func
= BP_ABS_FUNC(bp
);
10924 int port
= BP_PORT(bp
);
10925 u8
*iscsi_mac
= bp
->cnic_eth_dev
.iscsi_mac
;
10926 u8
*fip_mac
= bp
->fip_mac
;
10929 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10930 * FCoE MAC then the appropriate feature should be disabled.
10931 * In non SD mode features configuration comes from struct
10934 if (!IS_MF_SD(bp
) && !CHIP_IS_E1x(bp
)) {
10935 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
10936 if (cfg
& MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD
) {
10937 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
10938 iscsi_mac_addr_upper
);
10939 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
10940 iscsi_mac_addr_lower
);
10941 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
10943 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
10945 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
10948 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
10949 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
10950 fcoe_mac_addr_upper
);
10951 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
10952 fcoe_mac_addr_lower
);
10953 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
10955 ("Read FCoE L2 MAC: %pM\n", fip_mac
);
10957 bp
->flags
|= NO_FCOE_FLAG
;
10960 bp
->mf_ext_config
= cfg
;
10962 } else { /* SD MODE */
10963 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp
)) {
10964 /* use primary mac as iscsi mac */
10965 memcpy(iscsi_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
10967 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10969 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
10970 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
)) {
10971 /* use primary mac as fip mac */
10972 memcpy(fip_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
10973 BNX2X_DEV_INFO("SD FCoE MODE\n");
10975 ("Read FIP MAC: %pM\n", fip_mac
);
10979 /* If this is a storage-only interface, use SAN mac as
10980 * primary MAC. Notice that for SD this is already the case,
10981 * as the SAN mac was copied from the primary MAC.
10983 if (IS_MF_FCOE_AFEX(bp
))
10984 memcpy(bp
->dev
->dev_addr
, fip_mac
, ETH_ALEN
);
10986 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
10988 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
10990 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
10992 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
10993 fcoe_fip_mac_upper
);
10994 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
10995 fcoe_fip_mac_lower
);
10996 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
10999 /* Disable iSCSI OOO if MAC configuration is invalid. */
11000 if (!is_valid_ether_addr(iscsi_mac
)) {
11001 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
11002 memset(iscsi_mac
, 0, ETH_ALEN
);
11005 /* Disable FCoE if MAC configuration is invalid. */
11006 if (!is_valid_ether_addr(fip_mac
)) {
11007 bp
->flags
|= NO_FCOE_FLAG
;
11008 memset(bp
->fip_mac
, 0, ETH_ALEN
);
11012 static void bnx2x_get_mac_hwinfo(struct bnx2x
*bp
)
11015 int func
= BP_ABS_FUNC(bp
);
11016 int port
= BP_PORT(bp
);
11018 /* Zero primary MAC configuration */
11019 memset(bp
->dev
->dev_addr
, 0, ETH_ALEN
);
11021 if (BP_NOMCP(bp
)) {
11022 BNX2X_ERROR("warning: random MAC workaround active\n");
11023 eth_hw_addr_random(bp
->dev
);
11024 } else if (IS_MF(bp
)) {
11025 val2
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
11026 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_lower
);
11027 if ((val2
!= FUNC_MF_CFG_UPPERMAC_DEFAULT
) &&
11028 (val
!= FUNC_MF_CFG_LOWERMAC_DEFAULT
))
11029 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
11031 if (CNIC_SUPPORT(bp
))
11032 bnx2x_get_cnic_mac_hwinfo(bp
);
11034 /* in SF read MACs from port configuration */
11035 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
11036 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
11037 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
11039 if (CNIC_SUPPORT(bp
))
11040 bnx2x_get_cnic_mac_hwinfo(bp
);
11043 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
11045 if (!bnx2x_is_valid_ether_addr(bp
, bp
->dev
->dev_addr
))
11046 dev_err(&bp
->pdev
->dev
,
11047 "bad Ethernet MAC address configuration: %pM\n"
11048 "change it manually before bringing up the appropriate network interface\n",
11049 bp
->dev
->dev_addr
);
11052 static bool bnx2x_get_dropless_info(struct bnx2x
*bp
)
11057 if (IS_MF(bp
) && !CHIP_IS_E1x(bp
)) {
11058 /* Take function: tmp = func */
11059 tmp
= BP_ABS_FUNC(bp
);
11060 cfg
= MF_CFG_RD(bp
, func_ext_config
[tmp
].func_cfg
);
11061 cfg
= !!(cfg
& MACP_FUNC_CFG_PAUSE_ON_HOST_RING
);
11063 /* Take port: tmp = port */
11066 dev_info
.port_hw_config
[tmp
].generic_features
);
11067 cfg
= !!(cfg
& PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED
);
11072 static int bnx2x_get_hwinfo(struct bnx2x
*bp
)
11074 int /*abs*/func
= BP_ABS_FUNC(bp
);
11079 bnx2x_get_common_hwinfo(bp
);
11082 * initialize IGU parameters
11084 if (CHIP_IS_E1x(bp
)) {
11085 bp
->common
.int_block
= INT_BLOCK_HC
;
11087 bp
->igu_dsb_id
= DEF_SB_IGU_ID
;
11088 bp
->igu_base_sb
= 0;
11090 bp
->common
.int_block
= INT_BLOCK_IGU
;
11092 /* do not allow device reset during IGU info preocessing */
11093 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
11095 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
11097 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
11100 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11102 val
&= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
);
11103 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
, val
);
11104 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x7f);
11106 while (tout
&& REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
11108 usleep_range(1000, 2000);
11111 if (REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
11112 dev_err(&bp
->pdev
->dev
,
11113 "FORCING Normal Mode failed!!!\n");
11114 bnx2x_release_hw_lock(bp
,
11115 HW_LOCK_RESOURCE_RESET
);
11120 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
11121 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11122 bp
->common
.int_block
|= INT_BLOCK_MODE_BW_COMP
;
11124 BNX2X_DEV_INFO("IGU Normal Mode\n");
11126 rc
= bnx2x_get_igu_cam_info(bp
);
11127 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
11133 * set base FW non-default (fast path) status block id, this value is
11134 * used to initialize the fw_sb_id saved on the fp/queue structure to
11135 * determine the id used by the FW.
11137 if (CHIP_IS_E1x(bp
))
11138 bp
->base_fw_ndsb
= BP_PORT(bp
) * FP_SB_MAX_E1x
+ BP_L_ID(bp
);
11140 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11141 * the same queue are indicated on the same IGU SB). So we prefer
11142 * FW and IGU SBs to be the same value.
11144 bp
->base_fw_ndsb
= bp
->igu_base_sb
;
11146 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11147 "base_fw_ndsb %d\n", bp
->igu_dsb_id
, bp
->igu_base_sb
,
11148 bp
->igu_sb_cnt
, bp
->base_fw_ndsb
);
11151 * Initialize MF configuration
11158 if (!CHIP_IS_E1(bp
) && !BP_NOMCP(bp
)) {
11159 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11160 bp
->common
.shmem2_base
, SHMEM2_RD(bp
, size
),
11161 (u32
)offsetof(struct shmem2_region
, mf_cfg_addr
));
11163 if (SHMEM2_HAS(bp
, mf_cfg_addr
))
11164 bp
->common
.mf_cfg_base
= SHMEM2_RD(bp
, mf_cfg_addr
);
11166 bp
->common
.mf_cfg_base
= bp
->common
.shmem_base
+
11167 offsetof(struct shmem_region
, func_mb
) +
11168 E1H_FUNC_MAX
* sizeof(struct drv_func_mb
);
11170 * get mf configuration:
11171 * 1. existence of MF configuration
11172 * 2. MAC address must be legal (check only upper bytes)
11173 * for Switch-Independent mode;
11174 * OVLAN must be legal for Switch-Dependent mode
11175 * 3. SF_MODE configures specific MF mode
11177 if (bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
11178 /* get mf configuration */
11180 dev_info
.shared_feature_config
.config
);
11181 val
&= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK
;
11184 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT
:
11185 val
= MF_CFG_RD(bp
, func_mf_config
[func
].
11187 /* check for legal mac (upper bytes)*/
11188 if (val
!= 0xffff) {
11189 bp
->mf_mode
= MULTI_FUNCTION_SI
;
11190 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
11191 func_mf_config
[func
].config
);
11193 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11195 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE
:
11196 if ((!CHIP_IS_E1x(bp
)) &&
11197 (MF_CFG_RD(bp
, func_mf_config
[func
].
11198 mac_upper
) != 0xffff) &&
11200 afex_driver_support
))) {
11201 bp
->mf_mode
= MULTI_FUNCTION_AFEX
;
11202 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
11203 func_mf_config
[func
].config
);
11205 BNX2X_DEV_INFO("can not configure afex mode\n");
11208 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED
:
11209 /* get OV configuration */
11210 val
= MF_CFG_RD(bp
,
11211 func_mf_config
[FUNC_0
].e1hov_tag
);
11212 val
&= FUNC_MF_CFG_E1HOV_TAG_MASK
;
11214 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
11215 bp
->mf_mode
= MULTI_FUNCTION_SD
;
11216 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
11217 func_mf_config
[func
].config
);
11219 BNX2X_DEV_INFO("illegal OV for SD\n");
11221 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF
:
11222 bp
->mf_config
[vn
] = 0;
11225 /* Unknown configuration: reset mf_config */
11226 bp
->mf_config
[vn
] = 0;
11227 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val
);
11231 BNX2X_DEV_INFO("%s function mode\n",
11232 IS_MF(bp
) ? "multi" : "single");
11234 switch (bp
->mf_mode
) {
11235 case MULTI_FUNCTION_SD
:
11236 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
11237 FUNC_MF_CFG_E1HOV_TAG_MASK
;
11238 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
11240 bp
->path_has_ovlan
= true;
11242 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11243 func
, bp
->mf_ov
, bp
->mf_ov
);
11245 dev_err(&bp
->pdev
->dev
,
11246 "No valid MF OV for func %d, aborting\n",
11251 case MULTI_FUNCTION_AFEX
:
11252 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func
);
11254 case MULTI_FUNCTION_SI
:
11255 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11260 dev_err(&bp
->pdev
->dev
,
11261 "VN %d is in a single function mode, aborting\n",
11268 /* check if other port on the path needs ovlan:
11269 * Since MF configuration is shared between ports
11270 * Possible mixed modes are only
11271 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11273 if (CHIP_MODE_IS_4_PORT(bp
) &&
11274 !bp
->path_has_ovlan
&&
11276 bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
11277 u8 other_port
= !BP_PORT(bp
);
11278 u8 other_func
= BP_PATH(bp
) + 2*other_port
;
11279 val
= MF_CFG_RD(bp
,
11280 func_mf_config
[other_func
].e1hov_tag
);
11281 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
)
11282 bp
->path_has_ovlan
= true;
11286 /* adjust igu_sb_cnt to MF for E1x */
11287 if (CHIP_IS_E1x(bp
) && IS_MF(bp
))
11288 bp
->igu_sb_cnt
/= E1HVN_MAX
;
11291 bnx2x_get_port_hwinfo(bp
);
11293 /* Get MAC addresses */
11294 bnx2x_get_mac_hwinfo(bp
);
11296 bnx2x_get_cnic_info(bp
);
11301 static void bnx2x_read_fwinfo(struct bnx2x
*bp
)
11303 int cnt
, i
, block_end
, rodi
;
11304 char vpd_start
[BNX2X_VPD_LEN
+1];
11305 char str_id_reg
[VENDOR_ID_LEN
+1];
11306 char str_id_cap
[VENDOR_ID_LEN
+1];
11308 char *vpd_extended_data
= NULL
;
11311 cnt
= pci_read_vpd(bp
->pdev
, 0, BNX2X_VPD_LEN
, vpd_start
);
11312 memset(bp
->fw_ver
, 0, sizeof(bp
->fw_ver
));
11314 if (cnt
< BNX2X_VPD_LEN
)
11315 goto out_not_found
;
11317 /* VPD RO tag should be first tag after identifier string, hence
11318 * we should be able to find it in first BNX2X_VPD_LEN chars
11320 i
= pci_vpd_find_tag(vpd_start
, 0, BNX2X_VPD_LEN
,
11321 PCI_VPD_LRDT_RO_DATA
);
11323 goto out_not_found
;
11325 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+
11326 pci_vpd_lrdt_size(&vpd_start
[i
]);
11328 i
+= PCI_VPD_LRDT_TAG_SIZE
;
11330 if (block_end
> BNX2X_VPD_LEN
) {
11331 vpd_extended_data
= kmalloc(block_end
, GFP_KERNEL
);
11332 if (vpd_extended_data
== NULL
)
11333 goto out_not_found
;
11335 /* read rest of vpd image into vpd_extended_data */
11336 memcpy(vpd_extended_data
, vpd_start
, BNX2X_VPD_LEN
);
11337 cnt
= pci_read_vpd(bp
->pdev
, BNX2X_VPD_LEN
,
11338 block_end
- BNX2X_VPD_LEN
,
11339 vpd_extended_data
+ BNX2X_VPD_LEN
);
11340 if (cnt
< (block_end
- BNX2X_VPD_LEN
))
11341 goto out_not_found
;
11342 vpd_data
= vpd_extended_data
;
11344 vpd_data
= vpd_start
;
11346 /* now vpd_data holds full vpd content in both cases */
11348 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
11349 PCI_VPD_RO_KEYWORD_MFR_ID
);
11351 goto out_not_found
;
11353 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
11355 if (len
!= VENDOR_ID_LEN
)
11356 goto out_not_found
;
11358 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
11360 /* vendor specific info */
11361 snprintf(str_id_reg
, VENDOR_ID_LEN
+ 1, "%04x", PCI_VENDOR_ID_DELL
);
11362 snprintf(str_id_cap
, VENDOR_ID_LEN
+ 1, "%04X", PCI_VENDOR_ID_DELL
);
11363 if (!strncmp(str_id_reg
, &vpd_data
[rodi
], VENDOR_ID_LEN
) ||
11364 !strncmp(str_id_cap
, &vpd_data
[rodi
], VENDOR_ID_LEN
)) {
11366 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
11367 PCI_VPD_RO_KEYWORD_VENDOR0
);
11369 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
11371 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
11373 if (len
< 32 && (len
+ rodi
) <= BNX2X_VPD_LEN
) {
11374 memcpy(bp
->fw_ver
, &vpd_data
[rodi
], len
);
11375 bp
->fw_ver
[len
] = ' ';
11378 kfree(vpd_extended_data
);
11382 kfree(vpd_extended_data
);
11386 static void bnx2x_set_modes_bitmap(struct bnx2x
*bp
)
11390 if (CHIP_REV_IS_FPGA(bp
))
11391 SET_FLAGS(flags
, MODE_FPGA
);
11392 else if (CHIP_REV_IS_EMUL(bp
))
11393 SET_FLAGS(flags
, MODE_EMUL
);
11395 SET_FLAGS(flags
, MODE_ASIC
);
11397 if (CHIP_MODE_IS_4_PORT(bp
))
11398 SET_FLAGS(flags
, MODE_PORT4
);
11400 SET_FLAGS(flags
, MODE_PORT2
);
11402 if (CHIP_IS_E2(bp
))
11403 SET_FLAGS(flags
, MODE_E2
);
11404 else if (CHIP_IS_E3(bp
)) {
11405 SET_FLAGS(flags
, MODE_E3
);
11406 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
11407 SET_FLAGS(flags
, MODE_E3_A0
);
11408 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11409 SET_FLAGS(flags
, MODE_E3_B0
| MODE_COS3
);
11413 SET_FLAGS(flags
, MODE_MF
);
11414 switch (bp
->mf_mode
) {
11415 case MULTI_FUNCTION_SD
:
11416 SET_FLAGS(flags
, MODE_MF_SD
);
11418 case MULTI_FUNCTION_SI
:
11419 SET_FLAGS(flags
, MODE_MF_SI
);
11421 case MULTI_FUNCTION_AFEX
:
11422 SET_FLAGS(flags
, MODE_MF_AFEX
);
11426 SET_FLAGS(flags
, MODE_SF
);
11428 #if defined(__LITTLE_ENDIAN)
11429 SET_FLAGS(flags
, MODE_LITTLE_ENDIAN
);
11430 #else /*(__BIG_ENDIAN)*/
11431 SET_FLAGS(flags
, MODE_BIG_ENDIAN
);
11433 INIT_MODE_FLAGS(bp
) = flags
;
11436 static int bnx2x_init_bp(struct bnx2x
*bp
)
11441 mutex_init(&bp
->port
.phy_mutex
);
11442 mutex_init(&bp
->fw_mb_mutex
);
11443 spin_lock_init(&bp
->stats_lock
);
11446 INIT_DELAYED_WORK(&bp
->sp_task
, bnx2x_sp_task
);
11447 INIT_DELAYED_WORK(&bp
->sp_rtnl_task
, bnx2x_sp_rtnl_task
);
11448 INIT_DELAYED_WORK(&bp
->period_task
, bnx2x_period_task
);
11450 rc
= bnx2x_get_hwinfo(bp
);
11454 eth_zero_addr(bp
->dev
->dev_addr
);
11457 bnx2x_set_modes_bitmap(bp
);
11459 rc
= bnx2x_alloc_mem_bp(bp
);
11463 bnx2x_read_fwinfo(bp
);
11465 func
= BP_FUNC(bp
);
11467 /* need to reset chip if undi was active */
11468 if (IS_PF(bp
) && !BP_NOMCP(bp
)) {
11471 SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
11472 DRV_MSG_SEQ_NUMBER_MASK
;
11473 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp
->fw_seq
);
11475 bnx2x_prev_unload(bp
);
11479 if (CHIP_REV_IS_FPGA(bp
))
11480 dev_err(&bp
->pdev
->dev
, "FPGA detected\n");
11482 if (BP_NOMCP(bp
) && (func
== 0))
11483 dev_err(&bp
->pdev
->dev
, "MCP disabled, must load devices in order!\n");
11485 bp
->disable_tpa
= disable_tpa
;
11486 bp
->disable_tpa
|= IS_MF_STORAGE_SD(bp
) || IS_MF_FCOE_AFEX(bp
);
11488 /* Set TPA flags */
11489 if (bp
->disable_tpa
) {
11490 bp
->flags
&= ~(TPA_ENABLE_FLAG
| GRO_ENABLE_FLAG
);
11491 bp
->dev
->features
&= ~NETIF_F_LRO
;
11493 bp
->flags
|= (TPA_ENABLE_FLAG
| GRO_ENABLE_FLAG
);
11494 bp
->dev
->features
|= NETIF_F_LRO
;
11497 if (CHIP_IS_E1(bp
))
11498 bp
->dropless_fc
= 0;
11500 bp
->dropless_fc
= dropless_fc
| bnx2x_get_dropless_info(bp
);
11504 bp
->tx_ring_size
= IS_MF_FCOE_AFEX(bp
) ? 0 : MAX_TX_AVAIL
;
11506 bp
->rx_ring_size
= MAX_RX_AVAIL
;
11508 /* make sure that the numbers are in the right granularity */
11509 bp
->tx_ticks
= (50 / BNX2X_BTR
) * BNX2X_BTR
;
11510 bp
->rx_ticks
= (25 / BNX2X_BTR
) * BNX2X_BTR
;
11512 bp
->current_interval
= CHIP_REV_IS_SLOW(bp
) ? 5*HZ
: HZ
;
11514 init_timer(&bp
->timer
);
11515 bp
->timer
.expires
= jiffies
+ bp
->current_interval
;
11516 bp
->timer
.data
= (unsigned long) bp
;
11517 bp
->timer
.function
= bnx2x_timer
;
11519 if (SHMEM2_HAS(bp
, dcbx_lldp_params_offset
) &&
11520 SHMEM2_HAS(bp
, dcbx_lldp_dcbx_stat_offset
) &&
11521 SHMEM2_RD(bp
, dcbx_lldp_params_offset
) &&
11522 SHMEM2_RD(bp
, dcbx_lldp_dcbx_stat_offset
)) {
11523 bnx2x_dcbx_set_state(bp
, true, BNX2X_DCBX_ENABLED_ON_NEG_ON
);
11524 bnx2x_dcbx_init_params(bp
);
11526 bnx2x_dcbx_set_state(bp
, false, BNX2X_DCBX_ENABLED_OFF
);
11529 if (CHIP_IS_E1x(bp
))
11530 bp
->cnic_base_cl_id
= FP_SB_MAX_E1x
;
11532 bp
->cnic_base_cl_id
= FP_SB_MAX_E2
;
11534 /* multiple tx priority */
11537 else if (CHIP_IS_E1x(bp
))
11538 bp
->max_cos
= BNX2X_MULTI_TX_COS_E1X
;
11539 else if (CHIP_IS_E2(bp
) || CHIP_IS_E3A0(bp
))
11540 bp
->max_cos
= BNX2X_MULTI_TX_COS_E2_E3A0
;
11541 else if (CHIP_IS_E3B0(bp
))
11542 bp
->max_cos
= BNX2X_MULTI_TX_COS_E3B0
;
11544 BNX2X_ERR("unknown chip %x revision %x\n",
11545 CHIP_NUM(bp
), CHIP_REV(bp
));
11546 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp
->max_cos
);
11548 /* We need at least one default status block for slow-path events,
11549 * second status block for the L2 queue, and a third status block for
11550 * CNIC if supproted.
11552 if (CNIC_SUPPORT(bp
))
11553 bp
->min_msix_vec_cnt
= 3;
11555 bp
->min_msix_vec_cnt
= 2;
11556 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp
->min_msix_vec_cnt
);
11562 /****************************************************************************
11563 * General service functions
11564 ****************************************************************************/
11567 * net_device service functions
11570 /* called with rtnl_lock */
11571 static int bnx2x_open(struct net_device
*dev
)
11573 struct bnx2x
*bp
= netdev_priv(dev
);
11574 bool global
= false;
11575 int other_engine
= BP_PATH(bp
) ? 0 : 1;
11576 bool other_load_status
, load_status
;
11579 bp
->stats_init
= true;
11581 netif_carrier_off(dev
);
11583 bnx2x_set_power_state(bp
, PCI_D0
);
11585 /* If parity had happen during the unload, then attentions
11586 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11587 * want the first function loaded on the current engine to
11588 * complete the recovery.
11589 * Parity recovery is only relevant for PF driver.
11592 other_load_status
= bnx2x_get_load_status(bp
, other_engine
);
11593 load_status
= bnx2x_get_load_status(bp
, BP_PATH(bp
));
11594 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
)) ||
11595 bnx2x_chk_parity_attn(bp
, &global
, true)) {
11597 /* If there are attentions and they are in a
11598 * global blocks, set the GLOBAL_RESET bit
11599 * regardless whether it will be this function
11600 * that will complete the recovery or not.
11603 bnx2x_set_reset_global(bp
);
11605 /* Only the first function on the current
11606 * engine should try to recover in open. In case
11607 * of attentions in global blocks only the first
11608 * in the chip should try to recover.
11610 if ((!load_status
&&
11611 (!global
|| !other_load_status
)) &&
11612 bnx2x_trylock_leader_lock(bp
) &&
11613 !bnx2x_leader_reset(bp
)) {
11614 netdev_info(bp
->dev
,
11615 "Recovered in open\n");
11619 /* recovery has failed... */
11620 bnx2x_set_power_state(bp
, PCI_D3hot
);
11621 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
11623 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11624 "If you still see this message after a few retries then power cycle is required.\n");
11631 bp
->recovery_state
= BNX2X_RECOVERY_DONE
;
11632 rc
= bnx2x_nic_load(bp
, LOAD_OPEN
);
11635 return bnx2x_open_epilog(bp
);
11638 /* called with rtnl_lock */
11639 static int bnx2x_close(struct net_device
*dev
)
11641 struct bnx2x
*bp
= netdev_priv(dev
);
11643 /* Unload the driver, release IRQs */
11644 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
, false);
11647 bnx2x_set_power_state(bp
, PCI_D3hot
);
11652 static int bnx2x_init_mcast_macs_list(struct bnx2x
*bp
,
11653 struct bnx2x_mcast_ramrod_params
*p
)
11655 int mc_count
= netdev_mc_count(bp
->dev
);
11656 struct bnx2x_mcast_list_elem
*mc_mac
=
11657 kzalloc(sizeof(*mc_mac
) * mc_count
, GFP_ATOMIC
);
11658 struct netdev_hw_addr
*ha
;
11663 INIT_LIST_HEAD(&p
->mcast_list
);
11665 netdev_for_each_mc_addr(ha
, bp
->dev
) {
11666 mc_mac
->mac
= bnx2x_mc_addr(ha
);
11667 list_add_tail(&mc_mac
->link
, &p
->mcast_list
);
11671 p
->mcast_list_len
= mc_count
;
11676 static void bnx2x_free_mcast_macs_list(
11677 struct bnx2x_mcast_ramrod_params
*p
)
11679 struct bnx2x_mcast_list_elem
*mc_mac
=
11680 list_first_entry(&p
->mcast_list
, struct bnx2x_mcast_list_elem
,
11688 * bnx2x_set_uc_list - configure a new unicast MACs list.
11690 * @bp: driver handle
11692 * We will use zero (0) as a MAC type for these MACs.
11694 static int bnx2x_set_uc_list(struct bnx2x
*bp
)
11697 struct net_device
*dev
= bp
->dev
;
11698 struct netdev_hw_addr
*ha
;
11699 struct bnx2x_vlan_mac_obj
*mac_obj
= &bp
->sp_objs
->mac_obj
;
11700 unsigned long ramrod_flags
= 0;
11702 /* First schedule a cleanup up of old configuration */
11703 rc
= bnx2x_del_all_macs(bp
, mac_obj
, BNX2X_UC_LIST_MAC
, false);
11705 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc
);
11709 netdev_for_each_uc_addr(ha
, dev
) {
11710 rc
= bnx2x_set_mac_one(bp
, bnx2x_uc_addr(ha
), mac_obj
, true,
11711 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
11712 if (rc
== -EEXIST
) {
11714 "Failed to schedule ADD operations: %d\n", rc
);
11715 /* do not treat adding same MAC as error */
11718 } else if (rc
< 0) {
11720 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11726 /* Execute the pending commands */
11727 __set_bit(RAMROD_CONT
, &ramrod_flags
);
11728 return bnx2x_set_mac_one(bp
, NULL
, mac_obj
, false /* don't care */,
11729 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
11732 static int bnx2x_set_mc_list(struct bnx2x
*bp
)
11734 struct net_device
*dev
= bp
->dev
;
11735 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
11738 rparam
.mcast_obj
= &bp
->mcast_obj
;
11740 /* first, clear all configured multicast MACs */
11741 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
11743 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc
);
11747 /* then, configure a new MACs list */
11748 if (netdev_mc_count(dev
)) {
11749 rc
= bnx2x_init_mcast_macs_list(bp
, &rparam
);
11751 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11756 /* Now add the new MACs */
11757 rc
= bnx2x_config_mcast(bp
, &rparam
,
11758 BNX2X_MCAST_CMD_ADD
);
11760 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11763 bnx2x_free_mcast_macs_list(&rparam
);
11769 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11770 void bnx2x_set_rx_mode(struct net_device
*dev
)
11772 struct bnx2x
*bp
= netdev_priv(dev
);
11773 u32 rx_mode
= BNX2X_RX_MODE_NORMAL
;
11775 if (bp
->state
!= BNX2X_STATE_OPEN
) {
11776 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
11780 DP(NETIF_MSG_IFUP
, "dev->flags = %x\n", bp
->dev
->flags
);
11782 if (dev
->flags
& IFF_PROMISC
)
11783 rx_mode
= BNX2X_RX_MODE_PROMISC
;
11784 else if ((dev
->flags
& IFF_ALLMULTI
) ||
11785 ((netdev_mc_count(dev
) > BNX2X_MAX_MULTICAST
) &&
11787 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
11790 /* some multicasts */
11791 if (bnx2x_set_mc_list(bp
) < 0)
11792 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
11794 if (bnx2x_set_uc_list(bp
) < 0)
11795 rx_mode
= BNX2X_RX_MODE_PROMISC
;
11797 /* configuring mcast to a vf involves sleeping (when we
11798 * wait for the pf's response). Since this function is
11799 * called from non sleepable context we must schedule
11800 * a work item for this purpose
11802 smp_mb__before_clear_bit();
11803 set_bit(BNX2X_SP_RTNL_VFPF_MCAST
,
11804 &bp
->sp_rtnl_state
);
11805 smp_mb__after_clear_bit();
11806 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
11810 bp
->rx_mode
= rx_mode
;
11811 /* handle ISCSI SD mode */
11812 if (IS_MF_ISCSI_SD(bp
))
11813 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
11815 /* Schedule the rx_mode command */
11816 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
)) {
11817 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
11822 bnx2x_set_storm_rx_mode(bp
);
11824 /* configuring rx mode to storms in a vf involves sleeping (when
11825 * we wait for the pf's response). Since this function is
11826 * called from non sleepable context we must schedule
11827 * a work item for this purpose
11829 smp_mb__before_clear_bit();
11830 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE
,
11831 &bp
->sp_rtnl_state
);
11832 smp_mb__after_clear_bit();
11833 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
11837 /* called with rtnl_lock */
11838 static int bnx2x_mdio_read(struct net_device
*netdev
, int prtad
,
11839 int devad
, u16 addr
)
11841 struct bnx2x
*bp
= netdev_priv(netdev
);
11845 DP(NETIF_MSG_LINK
, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11846 prtad
, devad
, addr
);
11848 /* The HW expects different devad if CL22 is used */
11849 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
11851 bnx2x_acquire_phy_lock(bp
);
11852 rc
= bnx2x_phy_read(&bp
->link_params
, prtad
, devad
, addr
, &value
);
11853 bnx2x_release_phy_lock(bp
);
11854 DP(NETIF_MSG_LINK
, "mdio_read_val 0x%x rc = 0x%x\n", value
, rc
);
11861 /* called with rtnl_lock */
11862 static int bnx2x_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
11863 u16 addr
, u16 value
)
11865 struct bnx2x
*bp
= netdev_priv(netdev
);
11869 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11870 prtad
, devad
, addr
, value
);
11872 /* The HW expects different devad if CL22 is used */
11873 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
11875 bnx2x_acquire_phy_lock(bp
);
11876 rc
= bnx2x_phy_write(&bp
->link_params
, prtad
, devad
, addr
, value
);
11877 bnx2x_release_phy_lock(bp
);
11881 /* called with rtnl_lock */
11882 static int bnx2x_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
11884 struct bnx2x
*bp
= netdev_priv(dev
);
11885 struct mii_ioctl_data
*mdio
= if_mii(ifr
);
11887 DP(NETIF_MSG_LINK
, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11888 mdio
->phy_id
, mdio
->reg_num
, mdio
->val_in
);
11890 if (!netif_running(dev
))
11893 return mdio_mii_ioctl(&bp
->mdio
, mdio
, cmd
);
11896 #ifdef CONFIG_NET_POLL_CONTROLLER
11897 static void poll_bnx2x(struct net_device
*dev
)
11899 struct bnx2x
*bp
= netdev_priv(dev
);
11902 for_each_eth_queue(bp
, i
) {
11903 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
11904 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
11909 static int bnx2x_validate_addr(struct net_device
*dev
)
11911 struct bnx2x
*bp
= netdev_priv(dev
);
11913 /* query the bulletin board for mac address configured by the PF */
11915 bnx2x_sample_bulletin(bp
);
11917 if (!bnx2x_is_valid_ether_addr(bp
, dev
->dev_addr
)) {
11918 BNX2X_ERR("Non-valid Ethernet address\n");
11919 return -EADDRNOTAVAIL
;
11924 static const struct net_device_ops bnx2x_netdev_ops
= {
11925 .ndo_open
= bnx2x_open
,
11926 .ndo_stop
= bnx2x_close
,
11927 .ndo_start_xmit
= bnx2x_start_xmit
,
11928 .ndo_select_queue
= bnx2x_select_queue
,
11929 .ndo_set_rx_mode
= bnx2x_set_rx_mode
,
11930 .ndo_set_mac_address
= bnx2x_change_mac_addr
,
11931 .ndo_validate_addr
= bnx2x_validate_addr
,
11932 .ndo_do_ioctl
= bnx2x_ioctl
,
11933 .ndo_change_mtu
= bnx2x_change_mtu
,
11934 .ndo_fix_features
= bnx2x_fix_features
,
11935 .ndo_set_features
= bnx2x_set_features
,
11936 .ndo_tx_timeout
= bnx2x_tx_timeout
,
11937 #ifdef CONFIG_NET_POLL_CONTROLLER
11938 .ndo_poll_controller
= poll_bnx2x
,
11940 .ndo_setup_tc
= bnx2x_setup_tc
,
11941 #ifdef CONFIG_BNX2X_SRIOV
11942 .ndo_set_vf_mac
= bnx2x_set_vf_mac
,
11943 .ndo_set_vf_vlan
= bnx2x_set_vf_vlan
,
11944 .ndo_get_vf_config
= bnx2x_get_vf_config
,
11946 #ifdef NETDEV_FCOE_WWNN
11947 .ndo_fcoe_get_wwn
= bnx2x_fcoe_get_wwn
,
11951 static int bnx2x_set_coherency_mask(struct bnx2x
*bp
)
11953 struct device
*dev
= &bp
->pdev
->dev
;
11955 if (dma_set_mask(dev
, DMA_BIT_MASK(64)) == 0) {
11956 bp
->flags
|= USING_DAC_FLAG
;
11957 if (dma_set_coherent_mask(dev
, DMA_BIT_MASK(64)) != 0) {
11958 dev_err(dev
, "dma_set_coherent_mask failed, aborting\n");
11961 } else if (dma_set_mask(dev
, DMA_BIT_MASK(32)) != 0) {
11962 dev_err(dev
, "System does not support DMA, aborting\n");
11969 static int bnx2x_init_dev(struct bnx2x
*bp
, struct pci_dev
*pdev
,
11970 struct net_device
*dev
, unsigned long board_type
)
11974 bool chip_is_e1x
= (board_type
== BCM57710
||
11975 board_type
== BCM57711
||
11976 board_type
== BCM57711E
);
11978 SET_NETDEV_DEV(dev
, &pdev
->dev
);
11983 rc
= pci_enable_device(pdev
);
11985 dev_err(&bp
->pdev
->dev
,
11986 "Cannot enable PCI device, aborting\n");
11990 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
11991 dev_err(&bp
->pdev
->dev
,
11992 "Cannot find PCI device base address, aborting\n");
11994 goto err_out_disable
;
11997 if (IS_PF(bp
) && !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
11998 dev_err(&bp
->pdev
->dev
, "Cannot find second PCI device base address, aborting\n");
12000 goto err_out_disable
;
12003 pci_read_config_dword(pdev
, PCICFG_REVISION_ID_OFFSET
, &pci_cfg_dword
);
12004 if ((pci_cfg_dword
& PCICFG_REVESION_ID_MASK
) ==
12005 PCICFG_REVESION_ID_ERROR_VAL
) {
12006 pr_err("PCI device error, probably due to fan failure, aborting\n");
12008 goto err_out_disable
;
12011 if (atomic_read(&pdev
->enable_cnt
) == 1) {
12012 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
12014 dev_err(&bp
->pdev
->dev
,
12015 "Cannot obtain PCI resources, aborting\n");
12016 goto err_out_disable
;
12019 pci_set_master(pdev
);
12020 pci_save_state(pdev
);
12024 bp
->pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
12025 if (bp
->pm_cap
== 0) {
12026 dev_err(&bp
->pdev
->dev
,
12027 "Cannot find power management capability, aborting\n");
12029 goto err_out_release
;
12033 if (!pci_is_pcie(pdev
)) {
12034 dev_err(&bp
->pdev
->dev
, "Not PCI Express, aborting\n");
12036 goto err_out_release
;
12039 rc
= bnx2x_set_coherency_mask(bp
);
12041 goto err_out_release
;
12043 dev
->mem_start
= pci_resource_start(pdev
, 0);
12044 dev
->base_addr
= dev
->mem_start
;
12045 dev
->mem_end
= pci_resource_end(pdev
, 0);
12047 dev
->irq
= pdev
->irq
;
12049 bp
->regview
= pci_ioremap_bar(pdev
, 0);
12050 if (!bp
->regview
) {
12051 dev_err(&bp
->pdev
->dev
,
12052 "Cannot map register space, aborting\n");
12054 goto err_out_release
;
12057 /* In E1/E1H use pci device function given by kernel.
12058 * In E2/E3 read physical function from ME register since these chips
12059 * support Physical Device Assignment where kernel BDF maybe arbitrary
12060 * (depending on hypervisor).
12063 bp
->pf_num
= PCI_FUNC(pdev
->devfn
);
12066 pci_read_config_dword(bp
->pdev
,
12067 PCICFG_ME_REGISTER
, &pci_cfg_dword
);
12068 bp
->pf_num
= (u8
)((pci_cfg_dword
& ME_REG_ABS_PF_NUM
) >>
12069 ME_REG_ABS_PF_NUM_SHIFT
);
12071 BNX2X_DEV_INFO("me reg PF num: %d\n", bp
->pf_num
);
12073 bnx2x_set_power_state(bp
, PCI_D0
);
12075 /* clean indirect addresses */
12076 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
12077 PCICFG_VENDOR_ID_OFFSET
);
12079 * Clean the following indirect addresses for all functions since it
12080 * is not used by the driver.
12083 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F0
, 0);
12084 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F0
, 0);
12085 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F0
, 0);
12086 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F0
, 0);
12089 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F1
, 0);
12090 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F1
, 0);
12091 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F1
, 0);
12092 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F1
, 0);
12095 /* Enable internal target-read (in case we are probed after PF
12096 * FLR). Must be done prior to any BAR read access. Only for
12101 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
12104 dev
->watchdog_timeo
= TX_TIMEOUT
;
12106 dev
->netdev_ops
= &bnx2x_netdev_ops
;
12107 bnx2x_set_ethtool_ops(bp
, dev
);
12109 dev
->priv_flags
|= IFF_UNICAST_FLT
;
12111 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
12112 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
12113 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
|
12114 NETIF_F_RXHASH
| NETIF_F_HW_VLAN_CTAG_TX
;
12115 if (!CHIP_IS_E1x(bp
)) {
12116 dev
->hw_features
|= NETIF_F_GSO_GRE
| NETIF_F_GSO_UDP_TUNNEL
;
12117 dev
->hw_enc_features
=
12118 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
12119 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
12120 NETIF_F_GSO_GRE
| NETIF_F_GSO_UDP_TUNNEL
;
12123 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
12124 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_HIGHDMA
;
12126 dev
->features
|= dev
->hw_features
| NETIF_F_HW_VLAN_CTAG_RX
;
12127 if (bp
->flags
& USING_DAC_FLAG
)
12128 dev
->features
|= NETIF_F_HIGHDMA
;
12130 /* Add Loopback capability to the device */
12131 dev
->hw_features
|= NETIF_F_LOOPBACK
;
12134 dev
->dcbnl_ops
= &bnx2x_dcbnl_ops
;
12137 /* get_port_hwinfo() will set prtad and mmds properly */
12138 bp
->mdio
.prtad
= MDIO_PRTAD_NONE
;
12140 bp
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
12141 bp
->mdio
.dev
= dev
;
12142 bp
->mdio
.mdio_read
= bnx2x_mdio_read
;
12143 bp
->mdio
.mdio_write
= bnx2x_mdio_write
;
12148 if (atomic_read(&pdev
->enable_cnt
) == 1)
12149 pci_release_regions(pdev
);
12152 pci_disable_device(pdev
);
12153 pci_set_drvdata(pdev
, NULL
);
12159 static void bnx2x_get_pcie_width_speed(struct bnx2x
*bp
, int *width
,
12160 enum bnx2x_pci_bus_speed
*speed
)
12162 u32 link_speed
, val
= 0;
12164 pci_read_config_dword(bp
->pdev
, PCICFG_LINK_CONTROL
, &val
);
12165 *width
= (val
& PCICFG_LINK_WIDTH
) >> PCICFG_LINK_WIDTH_SHIFT
;
12167 link_speed
= (val
& PCICFG_LINK_SPEED
) >> PCICFG_LINK_SPEED_SHIFT
;
12169 switch (link_speed
) {
12171 *speed
= BNX2X_PCI_LINK_SPEED_8000
;
12174 *speed
= BNX2X_PCI_LINK_SPEED_5000
;
12177 *speed
= BNX2X_PCI_LINK_SPEED_2500
;
12181 static int bnx2x_check_firmware(struct bnx2x
*bp
)
12183 const struct firmware
*firmware
= bp
->firmware
;
12184 struct bnx2x_fw_file_hdr
*fw_hdr
;
12185 struct bnx2x_fw_file_section
*sections
;
12186 u32 offset
, len
, num_ops
;
12187 __be16
*ops_offsets
;
12191 if (firmware
->size
< sizeof(struct bnx2x_fw_file_hdr
)) {
12192 BNX2X_ERR("Wrong FW size\n");
12196 fw_hdr
= (struct bnx2x_fw_file_hdr
*)firmware
->data
;
12197 sections
= (struct bnx2x_fw_file_section
*)fw_hdr
;
12199 /* Make sure none of the offsets and sizes make us read beyond
12200 * the end of the firmware data */
12201 for (i
= 0; i
< sizeof(*fw_hdr
) / sizeof(*sections
); i
++) {
12202 offset
= be32_to_cpu(sections
[i
].offset
);
12203 len
= be32_to_cpu(sections
[i
].len
);
12204 if (offset
+ len
> firmware
->size
) {
12205 BNX2X_ERR("Section %d length is out of bounds\n", i
);
12210 /* Likewise for the init_ops offsets */
12211 offset
= be32_to_cpu(fw_hdr
->init_ops_offsets
.offset
);
12212 ops_offsets
= (__force __be16
*)(firmware
->data
+ offset
);
12213 num_ops
= be32_to_cpu(fw_hdr
->init_ops
.len
) / sizeof(struct raw_op
);
12215 for (i
= 0; i
< be32_to_cpu(fw_hdr
->init_ops_offsets
.len
) / 2; i
++) {
12216 if (be16_to_cpu(ops_offsets
[i
]) > num_ops
) {
12217 BNX2X_ERR("Section offset %d is out of bounds\n", i
);
12222 /* Check FW version */
12223 offset
= be32_to_cpu(fw_hdr
->fw_version
.offset
);
12224 fw_ver
= firmware
->data
+ offset
;
12225 if ((fw_ver
[0] != BCM_5710_FW_MAJOR_VERSION
) ||
12226 (fw_ver
[1] != BCM_5710_FW_MINOR_VERSION
) ||
12227 (fw_ver
[2] != BCM_5710_FW_REVISION_VERSION
) ||
12228 (fw_ver
[3] != BCM_5710_FW_ENGINEERING_VERSION
)) {
12229 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12230 fw_ver
[0], fw_ver
[1], fw_ver
[2], fw_ver
[3],
12231 BCM_5710_FW_MAJOR_VERSION
,
12232 BCM_5710_FW_MINOR_VERSION
,
12233 BCM_5710_FW_REVISION_VERSION
,
12234 BCM_5710_FW_ENGINEERING_VERSION
);
12241 static void be32_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
12243 const __be32
*source
= (const __be32
*)_source
;
12244 u32
*target
= (u32
*)_target
;
12247 for (i
= 0; i
< n
/4; i
++)
12248 target
[i
] = be32_to_cpu(source
[i
]);
12252 Ops array is stored in the following format:
12253 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12255 static void bnx2x_prep_ops(const u8
*_source
, u8
*_target
, u32 n
)
12257 const __be32
*source
= (const __be32
*)_source
;
12258 struct raw_op
*target
= (struct raw_op
*)_target
;
12261 for (i
= 0, j
= 0; i
< n
/8; i
++, j
+= 2) {
12262 tmp
= be32_to_cpu(source
[j
]);
12263 target
[i
].op
= (tmp
>> 24) & 0xff;
12264 target
[i
].offset
= tmp
& 0xffffff;
12265 target
[i
].raw_data
= be32_to_cpu(source
[j
+ 1]);
12269 /* IRO array is stored in the following format:
12270 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12272 static void bnx2x_prep_iro(const u8
*_source
, u8
*_target
, u32 n
)
12274 const __be32
*source
= (const __be32
*)_source
;
12275 struct iro
*target
= (struct iro
*)_target
;
12278 for (i
= 0, j
= 0; i
< n
/sizeof(struct iro
); i
++) {
12279 target
[i
].base
= be32_to_cpu(source
[j
]);
12281 tmp
= be32_to_cpu(source
[j
]);
12282 target
[i
].m1
= (tmp
>> 16) & 0xffff;
12283 target
[i
].m2
= tmp
& 0xffff;
12285 tmp
= be32_to_cpu(source
[j
]);
12286 target
[i
].m3
= (tmp
>> 16) & 0xffff;
12287 target
[i
].size
= tmp
& 0xffff;
12292 static void be16_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
12294 const __be16
*source
= (const __be16
*)_source
;
12295 u16
*target
= (u16
*)_target
;
12298 for (i
= 0; i
< n
/2; i
++)
12299 target
[i
] = be16_to_cpu(source
[i
]);
12302 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12304 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12305 bp->arr = kmalloc(len, GFP_KERNEL); \
12308 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12309 (u8 *)bp->arr, len); \
12312 static int bnx2x_init_firmware(struct bnx2x
*bp
)
12314 const char *fw_file_name
;
12315 struct bnx2x_fw_file_hdr
*fw_hdr
;
12321 if (CHIP_IS_E1(bp
))
12322 fw_file_name
= FW_FILE_NAME_E1
;
12323 else if (CHIP_IS_E1H(bp
))
12324 fw_file_name
= FW_FILE_NAME_E1H
;
12325 else if (!CHIP_IS_E1x(bp
))
12326 fw_file_name
= FW_FILE_NAME_E2
;
12328 BNX2X_ERR("Unsupported chip revision\n");
12331 BNX2X_DEV_INFO("Loading %s\n", fw_file_name
);
12333 rc
= request_firmware(&bp
->firmware
, fw_file_name
, &bp
->pdev
->dev
);
12335 BNX2X_ERR("Can't load firmware file %s\n",
12337 goto request_firmware_exit
;
12340 rc
= bnx2x_check_firmware(bp
);
12342 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name
);
12343 goto request_firmware_exit
;
12346 fw_hdr
= (struct bnx2x_fw_file_hdr
*)bp
->firmware
->data
;
12348 /* Initialize the pointers to the init arrays */
12350 BNX2X_ALLOC_AND_SET(init_data
, request_firmware_exit
, be32_to_cpu_n
);
12353 BNX2X_ALLOC_AND_SET(init_ops
, init_ops_alloc_err
, bnx2x_prep_ops
);
12356 BNX2X_ALLOC_AND_SET(init_ops_offsets
, init_offsets_alloc_err
,
12359 /* STORMs firmware */
12360 INIT_TSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
12361 be32_to_cpu(fw_hdr
->tsem_int_table_data
.offset
);
12362 INIT_TSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
12363 be32_to_cpu(fw_hdr
->tsem_pram_data
.offset
);
12364 INIT_USEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
12365 be32_to_cpu(fw_hdr
->usem_int_table_data
.offset
);
12366 INIT_USEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
12367 be32_to_cpu(fw_hdr
->usem_pram_data
.offset
);
12368 INIT_XSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
12369 be32_to_cpu(fw_hdr
->xsem_int_table_data
.offset
);
12370 INIT_XSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
12371 be32_to_cpu(fw_hdr
->xsem_pram_data
.offset
);
12372 INIT_CSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
12373 be32_to_cpu(fw_hdr
->csem_int_table_data
.offset
);
12374 INIT_CSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
12375 be32_to_cpu(fw_hdr
->csem_pram_data
.offset
);
12377 BNX2X_ALLOC_AND_SET(iro_arr
, iro_alloc_err
, bnx2x_prep_iro
);
12382 kfree(bp
->init_ops_offsets
);
12383 init_offsets_alloc_err
:
12384 kfree(bp
->init_ops
);
12385 init_ops_alloc_err
:
12386 kfree(bp
->init_data
);
12387 request_firmware_exit
:
12388 release_firmware(bp
->firmware
);
12389 bp
->firmware
= NULL
;
12394 static void bnx2x_release_firmware(struct bnx2x
*bp
)
12396 kfree(bp
->init_ops_offsets
);
12397 kfree(bp
->init_ops
);
12398 kfree(bp
->init_data
);
12399 release_firmware(bp
->firmware
);
12400 bp
->firmware
= NULL
;
12404 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv
= {
12405 .init_hw_cmn_chip
= bnx2x_init_hw_common_chip
,
12406 .init_hw_cmn
= bnx2x_init_hw_common
,
12407 .init_hw_port
= bnx2x_init_hw_port
,
12408 .init_hw_func
= bnx2x_init_hw_func
,
12410 .reset_hw_cmn
= bnx2x_reset_common
,
12411 .reset_hw_port
= bnx2x_reset_port
,
12412 .reset_hw_func
= bnx2x_reset_func
,
12414 .gunzip_init
= bnx2x_gunzip_init
,
12415 .gunzip_end
= bnx2x_gunzip_end
,
12417 .init_fw
= bnx2x_init_firmware
,
12418 .release_fw
= bnx2x_release_firmware
,
12421 void bnx2x__init_func_obj(struct bnx2x
*bp
)
12423 /* Prepare DMAE related driver resources */
12424 bnx2x_setup_dmae(bp
);
12426 bnx2x_init_func_obj(bp
, &bp
->func_obj
,
12427 bnx2x_sp(bp
, func_rdata
),
12428 bnx2x_sp_mapping(bp
, func_rdata
),
12429 bnx2x_sp(bp
, func_afex_rdata
),
12430 bnx2x_sp_mapping(bp
, func_afex_rdata
),
12431 &bnx2x_func_sp_drv
);
12434 /* must be called after sriov-enable */
12435 static int bnx2x_set_qm_cid_count(struct bnx2x
*bp
)
12437 int cid_count
= BNX2X_L2_MAX_CID(bp
);
12440 cid_count
+= BNX2X_VF_CIDS
;
12442 if (CNIC_SUPPORT(bp
))
12443 cid_count
+= CNIC_CID_MAX
;
12445 return roundup(cid_count
, QM_CID_ROUND
);
12449 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12454 static int bnx2x_get_num_non_def_sbs(struct pci_dev
*pdev
,
12455 int cnic_cnt
, bool is_vf
)
12460 pos
= pci_find_capability(pdev
, PCI_CAP_ID_MSIX
);
12463 * If MSI-X is not supported - return number of SBs needed to support
12464 * one fast path queue: one FP queue + SB for CNIC
12467 dev_info(&pdev
->dev
, "no msix capability found\n");
12468 return 1 + cnic_cnt
;
12470 dev_info(&pdev
->dev
, "msix capability found\n");
12473 * The value in the PCI configuration space is the index of the last
12474 * entry, namely one less than the actual size of the table, which is
12475 * exactly what we want to return from this function: number of all SBs
12476 * without the default SB.
12477 * For VFs there is no default SB, then we return (index+1).
12479 pci_read_config_word(pdev
, pos
+ PCI_MSI_FLAGS
, &control
);
12481 index
= control
& PCI_MSIX_FLAGS_QSIZE
;
12483 return is_vf
? index
+ 1 : index
;
12486 static int set_max_cos_est(int chip_id
)
12492 return BNX2X_MULTI_TX_COS_E1X
;
12496 return BNX2X_MULTI_TX_COS_E2_E3A0
;
12502 case BCM57840_4_10
:
12503 case BCM57840_2_20
:
12512 return BNX2X_MULTI_TX_COS_E3B0
;
12515 pr_err("Unknown board_type (%d), aborting\n", chip_id
);
12520 static int set_is_vf(int chip_id
)
12534 struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
);
12536 static int bnx2x_init_one(struct pci_dev
*pdev
,
12537 const struct pci_device_id
*ent
)
12539 struct net_device
*dev
= NULL
;
12542 enum bnx2x_pci_bus_speed pcie_speed
;
12543 int rc
, max_non_def_sbs
;
12544 int rx_count
, tx_count
, rss_count
, doorbell_size
;
12549 /* An estimated maximum supported CoS number according to the chip
12551 * We will try to roughly estimate the maximum number of CoSes this chip
12552 * may support in order to minimize the memory allocated for Tx
12553 * netdev_queue's. This number will be accurately calculated during the
12554 * initialization of bp->max_cos based on the chip versions AND chip
12555 * revision in the bnx2x_init_bp().
12557 max_cos_est
= set_max_cos_est(ent
->driver_data
);
12558 if (max_cos_est
< 0)
12559 return max_cos_est
;
12560 is_vf
= set_is_vf(ent
->driver_data
);
12561 cnic_cnt
= is_vf
? 0 : 1;
12563 max_non_def_sbs
= bnx2x_get_num_non_def_sbs(pdev
, cnic_cnt
, is_vf
);
12565 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12566 rss_count
= is_vf
? 1 : max_non_def_sbs
- cnic_cnt
;
12571 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12572 rx_count
= rss_count
+ cnic_cnt
;
12574 /* Maximum number of netdev Tx queues:
12575 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12577 tx_count
= rss_count
* max_cos_est
+ cnic_cnt
;
12579 /* dev zeroed in init_etherdev */
12580 dev
= alloc_etherdev_mqs(sizeof(*bp
), tx_count
, rx_count
);
12584 bp
= netdev_priv(dev
);
12588 bp
->flags
|= IS_VF_FLAG
;
12590 bp
->igu_sb_cnt
= max_non_def_sbs
;
12591 bp
->igu_base_addr
= IS_VF(bp
) ? PXP_VF_ADDR_IGU_START
: BAR_IGU_INTMEM
;
12592 bp
->msg_enable
= debug
;
12593 bp
->cnic_support
= cnic_cnt
;
12594 bp
->cnic_probe
= bnx2x_cnic_probe
;
12596 pci_set_drvdata(pdev
, dev
);
12598 rc
= bnx2x_init_dev(bp
, pdev
, dev
, ent
->driver_data
);
12604 BNX2X_DEV_INFO("This is a %s function\n",
12605 IS_PF(bp
) ? "physical" : "virtual");
12606 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp
) ? "on" : "off");
12607 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs
);
12608 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12609 tx_count
, rx_count
);
12611 rc
= bnx2x_init_bp(bp
);
12613 goto init_one_exit
;
12615 /* Map doorbells here as we need the real value of bp->max_cos which
12616 * is initialized in bnx2x_init_bp() to determine the number of
12620 bp
->doorbells
= bnx2x_vf_doorbells(bp
);
12621 rc
= bnx2x_vf_pci_alloc(bp
);
12623 goto init_one_exit
;
12625 doorbell_size
= BNX2X_L2_MAX_CID(bp
) * (1 << BNX2X_DB_SHIFT
);
12626 if (doorbell_size
> pci_resource_len(pdev
, 2)) {
12627 dev_err(&bp
->pdev
->dev
,
12628 "Cannot map doorbells, bar size too small, aborting\n");
12630 goto init_one_exit
;
12632 bp
->doorbells
= ioremap_nocache(pci_resource_start(pdev
, 2),
12635 if (!bp
->doorbells
) {
12636 dev_err(&bp
->pdev
->dev
,
12637 "Cannot map doorbell space, aborting\n");
12639 goto init_one_exit
;
12643 rc
= bnx2x_vfpf_acquire(bp
, tx_count
, rx_count
);
12645 goto init_one_exit
;
12648 /* Enable SRIOV if capability found in configuration space */
12649 rc
= bnx2x_iov_init_one(bp
, int_mode
, BNX2X_MAX_NUM_OF_VFS
);
12651 goto init_one_exit
;
12653 /* calc qm_cid_count */
12654 bp
->qm_cid_count
= bnx2x_set_qm_cid_count(bp
);
12655 BNX2X_DEV_INFO("qm_cid_count %d\n", bp
->qm_cid_count
);
12657 /* disable FCOE L2 queue for E1x*/
12658 if (CHIP_IS_E1x(bp
))
12659 bp
->flags
|= NO_FCOE_FLAG
;
12661 /* Set bp->num_queues for MSI-X mode*/
12662 bnx2x_set_num_queues(bp
);
12664 /* Configure interrupt mode: try to enable MSI-X/MSI if
12667 rc
= bnx2x_set_int_mode(bp
);
12669 dev_err(&pdev
->dev
, "Cannot set interrupts\n");
12670 goto init_one_exit
;
12672 BNX2X_DEV_INFO("set interrupts successfully\n");
12674 /* register the net device */
12675 rc
= register_netdev(dev
);
12677 dev_err(&pdev
->dev
, "Cannot register net device\n");
12678 goto init_one_exit
;
12680 BNX2X_DEV_INFO("device name after netdev register %s\n", dev
->name
);
12683 if (!NO_FCOE(bp
)) {
12684 /* Add storage MAC address */
12686 dev_addr_add(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
12690 bnx2x_get_pcie_width_speed(bp
, &pcie_width
, &pcie_speed
);
12691 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12692 pcie_width
, pcie_speed
);
12694 BNX2X_DEV_INFO("%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12695 board_info
[ent
->driver_data
].name
,
12696 (CHIP_REV(bp
) >> 12) + 'A', (CHIP_METAL(bp
) >> 4),
12698 pcie_speed
== BNX2X_PCI_LINK_SPEED_2500
? "2.5GHz" :
12699 pcie_speed
== BNX2X_PCI_LINK_SPEED_5000
? "5.0GHz" :
12700 pcie_speed
== BNX2X_PCI_LINK_SPEED_8000
? "8.0GHz" :
12702 dev
->base_addr
, bp
->pdev
->irq
, dev
->dev_addr
);
12708 iounmap(bp
->regview
);
12710 if (IS_PF(bp
) && bp
->doorbells
)
12711 iounmap(bp
->doorbells
);
12715 if (atomic_read(&pdev
->enable_cnt
) == 1)
12716 pci_release_regions(pdev
);
12718 pci_disable_device(pdev
);
12719 pci_set_drvdata(pdev
, NULL
);
12724 static void __bnx2x_remove(struct pci_dev
*pdev
,
12725 struct net_device
*dev
,
12727 bool remove_netdev
)
12729 /* Delete storage MAC address */
12730 if (!NO_FCOE(bp
)) {
12732 dev_addr_del(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
12737 /* Delete app tlvs from dcbnl */
12738 bnx2x_dcbnl_update_applist(bp
, true);
12741 /* Close the interface - either directly or implicitly */
12742 if (remove_netdev
) {
12743 unregister_netdev(dev
);
12746 if (netif_running(dev
))
12751 /* Power on: we can't let PCI layer write to us while we are in D3 */
12753 bnx2x_set_power_state(bp
, PCI_D0
);
12755 /* Disable MSI/MSI-X */
12756 bnx2x_disable_msi(bp
);
12760 bnx2x_set_power_state(bp
, PCI_D3hot
);
12762 /* Make sure RESET task is not scheduled before continuing */
12763 cancel_delayed_work_sync(&bp
->sp_rtnl_task
);
12765 bnx2x_iov_remove_one(bp
);
12767 /* send message via vfpf channel to release the resources of this vf */
12769 bnx2x_vfpf_release(bp
);
12771 /* Assumes no further PCIe PM changes will occur */
12772 if (system_state
== SYSTEM_POWER_OFF
) {
12773 pci_wake_from_d3(pdev
, bp
->wol
);
12774 pci_set_power_state(pdev
, PCI_D3hot
);
12778 iounmap(bp
->regview
);
12780 /* for vf doorbells are part of the regview and were unmapped along with
12781 * it. FW is only loaded by PF.
12785 iounmap(bp
->doorbells
);
12787 bnx2x_release_firmware(bp
);
12789 bnx2x_free_mem_bp(bp
);
12794 if (atomic_read(&pdev
->enable_cnt
) == 1)
12795 pci_release_regions(pdev
);
12797 pci_disable_device(pdev
);
12798 pci_set_drvdata(pdev
, NULL
);
12801 static void bnx2x_remove_one(struct pci_dev
*pdev
)
12803 struct net_device
*dev
= pci_get_drvdata(pdev
);
12807 dev_err(&pdev
->dev
, "BAD net device from bnx2x_init_one\n");
12810 bp
= netdev_priv(dev
);
12812 __bnx2x_remove(pdev
, dev
, bp
, true);
12815 static int bnx2x_eeh_nic_unload(struct bnx2x
*bp
)
12817 bp
->state
= BNX2X_STATE_CLOSING_WAIT4_HALT
;
12819 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
12821 if (CNIC_LOADED(bp
))
12822 bnx2x_cnic_notify(bp
, CNIC_CTL_STOP_CMD
);
12825 bnx2x_tx_disable(bp
);
12826 /* Delete all NAPI objects */
12827 bnx2x_del_all_napi(bp
);
12828 if (CNIC_LOADED(bp
))
12829 bnx2x_del_all_napi_cnic(bp
);
12830 netdev_reset_tc(bp
->dev
);
12832 del_timer_sync(&bp
->timer
);
12833 cancel_delayed_work(&bp
->sp_task
);
12834 cancel_delayed_work(&bp
->period_task
);
12836 spin_lock_bh(&bp
->stats_lock
);
12837 bp
->stats_state
= STATS_STATE_DISABLED
;
12838 spin_unlock_bh(&bp
->stats_lock
);
12840 bnx2x_save_statistics(bp
);
12842 netif_carrier_off(bp
->dev
);
12848 * bnx2x_io_error_detected - called when PCI error is detected
12849 * @pdev: Pointer to PCI device
12850 * @state: The current pci connection state
12852 * This function is called after a PCI bus error affecting
12853 * this device has been detected.
12855 static pci_ers_result_t
bnx2x_io_error_detected(struct pci_dev
*pdev
,
12856 pci_channel_state_t state
)
12858 struct net_device
*dev
= pci_get_drvdata(pdev
);
12859 struct bnx2x
*bp
= netdev_priv(dev
);
12863 BNX2X_ERR("IO error detected\n");
12865 netif_device_detach(dev
);
12867 if (state
== pci_channel_io_perm_failure
) {
12869 return PCI_ERS_RESULT_DISCONNECT
;
12872 if (netif_running(dev
))
12873 bnx2x_eeh_nic_unload(bp
);
12875 bnx2x_prev_path_mark_eeh(bp
);
12877 pci_disable_device(pdev
);
12881 /* Request a slot reset */
12882 return PCI_ERS_RESULT_NEED_RESET
;
12886 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12887 * @pdev: Pointer to PCI device
12889 * Restart the card from scratch, as if from a cold-boot.
12891 static pci_ers_result_t
bnx2x_io_slot_reset(struct pci_dev
*pdev
)
12893 struct net_device
*dev
= pci_get_drvdata(pdev
);
12894 struct bnx2x
*bp
= netdev_priv(dev
);
12898 BNX2X_ERR("IO slot reset initializing...\n");
12899 if (pci_enable_device(pdev
)) {
12900 dev_err(&pdev
->dev
,
12901 "Cannot re-enable PCI device after reset\n");
12903 return PCI_ERS_RESULT_DISCONNECT
;
12906 pci_set_master(pdev
);
12907 pci_restore_state(pdev
);
12908 pci_save_state(pdev
);
12910 if (netif_running(dev
))
12911 bnx2x_set_power_state(bp
, PCI_D0
);
12913 if (netif_running(dev
)) {
12914 BNX2X_ERR("IO slot reset --> driver unload\n");
12916 /* MCP should have been reset; Need to wait for validity */
12917 bnx2x_init_shmem(bp
);
12919 if (IS_PF(bp
) && SHMEM2_HAS(bp
, drv_capabilities_flag
)) {
12923 drv_capabilities_flag
[BP_FW_MB_IDX(bp
)]);
12924 SHMEM2_WR(bp
, drv_capabilities_flag
[BP_FW_MB_IDX(bp
)],
12925 v
& ~DRV_FLAGS_CAPABILITIES_LOADED_L2
);
12927 bnx2x_drain_tx_queues(bp
);
12928 bnx2x_send_unload_req(bp
, UNLOAD_RECOVERY
);
12929 bnx2x_netif_stop(bp
, 1);
12930 bnx2x_free_irq(bp
);
12932 /* Report UNLOAD_DONE to MCP */
12933 bnx2x_send_unload_done(bp
, true);
12938 bnx2x_prev_unload(bp
);
12940 /* We should have resetted the engine, so It's fair to
12941 * assume the FW will no longer write to the bnx2x driver.
12943 bnx2x_squeeze_objects(bp
);
12944 bnx2x_free_skbs(bp
);
12945 for_each_rx_queue(bp
, i
)
12946 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
12947 bnx2x_free_fp_mem(bp
);
12948 bnx2x_free_mem(bp
);
12950 bp
->state
= BNX2X_STATE_CLOSED
;
12955 return PCI_ERS_RESULT_RECOVERED
;
12959 * bnx2x_io_resume - called when traffic can start flowing again
12960 * @pdev: Pointer to PCI device
12962 * This callback is called when the error recovery driver tells us that
12963 * its OK to resume normal operation.
12965 static void bnx2x_io_resume(struct pci_dev
*pdev
)
12967 struct net_device
*dev
= pci_get_drvdata(pdev
);
12968 struct bnx2x
*bp
= netdev_priv(dev
);
12970 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
12971 netdev_err(bp
->dev
, "Handling parity error recovery. Try again later\n");
12977 bp
->fw_seq
= SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
12978 DRV_MSG_SEQ_NUMBER_MASK
;
12980 if (netif_running(dev
))
12981 bnx2x_nic_load(bp
, LOAD_NORMAL
);
12983 netif_device_attach(dev
);
12988 static const struct pci_error_handlers bnx2x_err_handler
= {
12989 .error_detected
= bnx2x_io_error_detected
,
12990 .slot_reset
= bnx2x_io_slot_reset
,
12991 .resume
= bnx2x_io_resume
,
12994 static void bnx2x_shutdown(struct pci_dev
*pdev
)
12996 struct net_device
*dev
= pci_get_drvdata(pdev
);
13002 bp
= netdev_priv(dev
);
13007 netif_device_detach(dev
);
13010 /* Don't remove the netdevice, as there are scenarios which will cause
13011 * the kernel to hang, e.g., when trying to remove bnx2i while the
13012 * rootfs is mounted from SAN.
13014 __bnx2x_remove(pdev
, dev
, bp
, false);
13017 static struct pci_driver bnx2x_pci_driver
= {
13018 .name
= DRV_MODULE_NAME
,
13019 .id_table
= bnx2x_pci_tbl
,
13020 .probe
= bnx2x_init_one
,
13021 .remove
= bnx2x_remove_one
,
13022 .suspend
= bnx2x_suspend
,
13023 .resume
= bnx2x_resume
,
13024 .err_handler
= &bnx2x_err_handler
,
13025 #ifdef CONFIG_BNX2X_SRIOV
13026 .sriov_configure
= bnx2x_sriov_configure
,
13028 .shutdown
= bnx2x_shutdown
,
13031 static int __init
bnx2x_init(void)
13035 pr_info("%s", version
);
13037 bnx2x_wq
= create_singlethread_workqueue("bnx2x");
13038 if (bnx2x_wq
== NULL
) {
13039 pr_err("Cannot create workqueue\n");
13043 ret
= pci_register_driver(&bnx2x_pci_driver
);
13045 pr_err("Cannot register driver\n");
13046 destroy_workqueue(bnx2x_wq
);
13051 static void __exit
bnx2x_cleanup(void)
13053 struct list_head
*pos
, *q
;
13054 pci_unregister_driver(&bnx2x_pci_driver
);
13056 destroy_workqueue(bnx2x_wq
);
13058 /* Free globablly allocated resources */
13059 list_for_each_safe(pos
, q
, &bnx2x_prev_list
) {
13060 struct bnx2x_prev_path_list
*tmp
=
13061 list_entry(pos
, struct bnx2x_prev_path_list
, list
);
13067 void bnx2x_notify_link_changed(struct bnx2x
*bp
)
13069 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ BP_FUNC(bp
)*sizeof(u32
), 1);
13072 module_init(bnx2x_init
);
13073 module_exit(bnx2x_cleanup
);
13076 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
13078 * @bp: driver handle
13079 * @set: set or clear the CAM entry
13081 * This function will wait until the ramdord completion returns.
13082 * Return 0 if success, -ENODEV if ramrod doesn't return.
13084 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x
*bp
)
13086 unsigned long ramrod_flags
= 0;
13088 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
13089 return bnx2x_set_mac_one(bp
, bp
->cnic_eth_dev
.iscsi_mac
,
13090 &bp
->iscsi_l2_mac_obj
, true,
13091 BNX2X_ISCSI_ETH_MAC
, &ramrod_flags
);
13094 /* count denotes the number of new completions we have seen */
13095 static void bnx2x_cnic_sp_post(struct bnx2x
*bp
, int count
)
13097 struct eth_spe
*spe
;
13098 int cxt_index
, cxt_offset
;
13100 #ifdef BNX2X_STOP_ON_ERROR
13101 if (unlikely(bp
->panic
))
13105 spin_lock_bh(&bp
->spq_lock
);
13106 BUG_ON(bp
->cnic_spq_pending
< count
);
13107 bp
->cnic_spq_pending
-= count
;
13110 for (; bp
->cnic_kwq_pending
; bp
->cnic_kwq_pending
--) {
13111 u16 type
= (le16_to_cpu(bp
->cnic_kwq_cons
->hdr
.type
)
13112 & SPE_HDR_CONN_TYPE
) >>
13113 SPE_HDR_CONN_TYPE_SHIFT
;
13114 u8 cmd
= (le32_to_cpu(bp
->cnic_kwq_cons
->hdr
.conn_and_cmd_data
)
13115 >> SPE_HDR_CMD_ID_SHIFT
) & 0xff;
13117 /* Set validation for iSCSI L2 client before sending SETUP
13120 if (type
== ETH_CONNECTION_TYPE
) {
13121 if (cmd
== RAMROD_CMD_ID_ETH_CLIENT_SETUP
) {
13122 cxt_index
= BNX2X_ISCSI_ETH_CID(bp
) /
13124 cxt_offset
= BNX2X_ISCSI_ETH_CID(bp
) -
13125 (cxt_index
* ILT_PAGE_CIDS
);
13126 bnx2x_set_ctx_validation(bp
,
13127 &bp
->context
[cxt_index
].
13128 vcxt
[cxt_offset
].eth
,
13129 BNX2X_ISCSI_ETH_CID(bp
));
13134 * There may be not more than 8 L2, not more than 8 L5 SPEs
13135 * and in the air. We also check that number of outstanding
13136 * COMMON ramrods is not more than the EQ and SPQ can
13139 if (type
== ETH_CONNECTION_TYPE
) {
13140 if (!atomic_read(&bp
->cq_spq_left
))
13143 atomic_dec(&bp
->cq_spq_left
);
13144 } else if (type
== NONE_CONNECTION_TYPE
) {
13145 if (!atomic_read(&bp
->eq_spq_left
))
13148 atomic_dec(&bp
->eq_spq_left
);
13149 } else if ((type
== ISCSI_CONNECTION_TYPE
) ||
13150 (type
== FCOE_CONNECTION_TYPE
)) {
13151 if (bp
->cnic_spq_pending
>=
13152 bp
->cnic_eth_dev
.max_kwqe_pending
)
13155 bp
->cnic_spq_pending
++;
13157 BNX2X_ERR("Unknown SPE type: %d\n", type
);
13162 spe
= bnx2x_sp_get_next(bp
);
13163 *spe
= *bp
->cnic_kwq_cons
;
13165 DP(BNX2X_MSG_SP
, "pending on SPQ %d, on KWQ %d count %d\n",
13166 bp
->cnic_spq_pending
, bp
->cnic_kwq_pending
, count
);
13168 if (bp
->cnic_kwq_cons
== bp
->cnic_kwq_last
)
13169 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
13171 bp
->cnic_kwq_cons
++;
13173 bnx2x_sp_prod_update(bp
);
13174 spin_unlock_bh(&bp
->spq_lock
);
13177 static int bnx2x_cnic_sp_queue(struct net_device
*dev
,
13178 struct kwqe_16
*kwqes
[], u32 count
)
13180 struct bnx2x
*bp
= netdev_priv(dev
);
13183 #ifdef BNX2X_STOP_ON_ERROR
13184 if (unlikely(bp
->panic
)) {
13185 BNX2X_ERR("Can't post to SP queue while panic\n");
13190 if ((bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) &&
13191 (bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
13192 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13196 spin_lock_bh(&bp
->spq_lock
);
13198 for (i
= 0; i
< count
; i
++) {
13199 struct eth_spe
*spe
= (struct eth_spe
*)kwqes
[i
];
13201 if (bp
->cnic_kwq_pending
== MAX_SP_DESC_CNT
)
13204 *bp
->cnic_kwq_prod
= *spe
;
13206 bp
->cnic_kwq_pending
++;
13208 DP(BNX2X_MSG_SP
, "L5 SPQE %x %x %x:%x pos %d\n",
13209 spe
->hdr
.conn_and_cmd_data
, spe
->hdr
.type
,
13210 spe
->data
.update_data_addr
.hi
,
13211 spe
->data
.update_data_addr
.lo
,
13212 bp
->cnic_kwq_pending
);
13214 if (bp
->cnic_kwq_prod
== bp
->cnic_kwq_last
)
13215 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
13217 bp
->cnic_kwq_prod
++;
13220 spin_unlock_bh(&bp
->spq_lock
);
13222 if (bp
->cnic_spq_pending
< bp
->cnic_eth_dev
.max_kwqe_pending
)
13223 bnx2x_cnic_sp_post(bp
, 0);
13228 static int bnx2x_cnic_ctl_send(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
13230 struct cnic_ops
*c_ops
;
13233 mutex_lock(&bp
->cnic_mutex
);
13234 c_ops
= rcu_dereference_protected(bp
->cnic_ops
,
13235 lockdep_is_held(&bp
->cnic_mutex
));
13237 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
13238 mutex_unlock(&bp
->cnic_mutex
);
13243 static int bnx2x_cnic_ctl_send_bh(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
13245 struct cnic_ops
*c_ops
;
13249 c_ops
= rcu_dereference(bp
->cnic_ops
);
13251 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
13258 * for commands that have no data
13260 int bnx2x_cnic_notify(struct bnx2x
*bp
, int cmd
)
13262 struct cnic_ctl_info ctl
= {0};
13266 return bnx2x_cnic_ctl_send(bp
, &ctl
);
13269 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
)
13271 struct cnic_ctl_info ctl
= {0};
13273 /* first we tell CNIC and only then we count this as a completion */
13274 ctl
.cmd
= CNIC_CTL_COMPLETION_CMD
;
13275 ctl
.data
.comp
.cid
= cid
;
13276 ctl
.data
.comp
.error
= err
;
13278 bnx2x_cnic_ctl_send_bh(bp
, &ctl
);
13279 bnx2x_cnic_sp_post(bp
, 0);
13283 /* Called with netif_addr_lock_bh() taken.
13284 * Sets an rx_mode config for an iSCSI ETH client.
13286 * Completion should be checked outside.
13288 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
)
13290 unsigned long accept_flags
= 0, ramrod_flags
= 0;
13291 u8 cl_id
= bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
13292 int sched_state
= BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
;
13295 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13296 * because it's the only way for UIO Queue to accept
13297 * multicasts (in non-promiscuous mode only one Queue per
13298 * function will receive multicast packets (leading in our
13301 __set_bit(BNX2X_ACCEPT_UNICAST
, &accept_flags
);
13302 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &accept_flags
);
13303 __set_bit(BNX2X_ACCEPT_BROADCAST
, &accept_flags
);
13304 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &accept_flags
);
13306 /* Clear STOP_PENDING bit if START is requested */
13307 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &bp
->sp_state
);
13309 sched_state
= BNX2X_FILTER_ISCSI_ETH_START_SCHED
;
13311 /* Clear START_PENDING bit if STOP is requested */
13312 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &bp
->sp_state
);
13314 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
13315 set_bit(sched_state
, &bp
->sp_state
);
13317 __set_bit(RAMROD_RX
, &ramrod_flags
);
13318 bnx2x_set_q_rx_mode(bp
, cl_id
, 0, accept_flags
, 0,
13324 static int bnx2x_drv_ctl(struct net_device
*dev
, struct drv_ctl_info
*ctl
)
13326 struct bnx2x
*bp
= netdev_priv(dev
);
13329 switch (ctl
->cmd
) {
13330 case DRV_CTL_CTXTBL_WR_CMD
: {
13331 u32 index
= ctl
->data
.io
.offset
;
13332 dma_addr_t addr
= ctl
->data
.io
.dma_addr
;
13334 bnx2x_ilt_wr(bp
, index
, addr
);
13338 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD
: {
13339 int count
= ctl
->data
.credit
.credit_count
;
13341 bnx2x_cnic_sp_post(bp
, count
);
13345 /* rtnl_lock is held. */
13346 case DRV_CTL_START_L2_CMD
: {
13347 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13348 unsigned long sp_bits
= 0;
13350 /* Configure the iSCSI classification object */
13351 bnx2x_init_mac_obj(bp
, &bp
->iscsi_l2_mac_obj
,
13352 cp
->iscsi_l2_client_id
,
13353 cp
->iscsi_l2_cid
, BP_FUNC(bp
),
13354 bnx2x_sp(bp
, mac_rdata
),
13355 bnx2x_sp_mapping(bp
, mac_rdata
),
13356 BNX2X_FILTER_MAC_PENDING
,
13357 &bp
->sp_state
, BNX2X_OBJ_TYPE_RX
,
13360 /* Set iSCSI MAC address */
13361 rc
= bnx2x_set_iscsi_eth_mac_addr(bp
);
13368 /* Start accepting on iSCSI L2 ring */
13370 netif_addr_lock_bh(dev
);
13371 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
13372 netif_addr_unlock_bh(dev
);
13374 /* bits to wait on */
13375 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
13376 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &sp_bits
);
13378 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
13379 BNX2X_ERR("rx_mode completion timed out!\n");
13384 /* rtnl_lock is held. */
13385 case DRV_CTL_STOP_L2_CMD
: {
13386 unsigned long sp_bits
= 0;
13388 /* Stop accepting on iSCSI L2 ring */
13389 netif_addr_lock_bh(dev
);
13390 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
13391 netif_addr_unlock_bh(dev
);
13393 /* bits to wait on */
13394 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
13395 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &sp_bits
);
13397 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
13398 BNX2X_ERR("rx_mode completion timed out!\n");
13403 /* Unset iSCSI L2 MAC */
13404 rc
= bnx2x_del_all_macs(bp
, &bp
->iscsi_l2_mac_obj
,
13405 BNX2X_ISCSI_ETH_MAC
, true);
13408 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD
: {
13409 int count
= ctl
->data
.credit
.credit_count
;
13411 smp_mb__before_atomic_inc();
13412 atomic_add(count
, &bp
->cq_spq_left
);
13413 smp_mb__after_atomic_inc();
13416 case DRV_CTL_ULP_REGISTER_CMD
: {
13417 int ulp_type
= ctl
->data
.register_data
.ulp_type
;
13419 if (CHIP_IS_E3(bp
)) {
13420 int idx
= BP_FW_MB_IDX(bp
);
13421 u32 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
13422 int path
= BP_PATH(bp
);
13423 int port
= BP_PORT(bp
);
13425 u32 scratch_offset
;
13428 /* first write capability to shmem2 */
13429 if (ulp_type
== CNIC_ULP_ISCSI
)
13430 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
13431 else if (ulp_type
== CNIC_ULP_FCOE
)
13432 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
13433 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
13435 if ((ulp_type
!= CNIC_ULP_FCOE
) ||
13436 (!SHMEM2_HAS(bp
, ncsi_oem_data_addr
)) ||
13437 (!(bp
->flags
& BC_SUPPORTS_FCOE_FEATURES
)))
13440 /* if reached here - should write fcoe capabilities */
13441 scratch_offset
= SHMEM2_RD(bp
, ncsi_oem_data_addr
);
13442 if (!scratch_offset
)
13444 scratch_offset
+= offsetof(struct glob_ncsi_oem_data
,
13445 fcoe_features
[path
][port
]);
13446 host_addr
= (u32
*) &(ctl
->data
.register_data
.
13448 for (i
= 0; i
< sizeof(struct fcoe_capabilities
);
13450 REG_WR(bp
, scratch_offset
+ i
,
13451 *(host_addr
+ i
/4));
13456 case DRV_CTL_ULP_UNREGISTER_CMD
: {
13457 int ulp_type
= ctl
->data
.ulp_type
;
13459 if (CHIP_IS_E3(bp
)) {
13460 int idx
= BP_FW_MB_IDX(bp
);
13463 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
13464 if (ulp_type
== CNIC_ULP_ISCSI
)
13465 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
13466 else if (ulp_type
== CNIC_ULP_FCOE
)
13467 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
13468 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
13474 BNX2X_ERR("unknown command %x\n", ctl
->cmd
);
13481 void bnx2x_setup_cnic_irq_info(struct bnx2x
*bp
)
13483 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13485 if (bp
->flags
& USING_MSIX_FLAG
) {
13486 cp
->drv_state
|= CNIC_DRV_STATE_USING_MSIX
;
13487 cp
->irq_arr
[0].irq_flags
|= CNIC_IRQ_FL_MSIX
;
13488 cp
->irq_arr
[0].vector
= bp
->msix_table
[1].vector
;
13490 cp
->drv_state
&= ~CNIC_DRV_STATE_USING_MSIX
;
13491 cp
->irq_arr
[0].irq_flags
&= ~CNIC_IRQ_FL_MSIX
;
13493 if (!CHIP_IS_E1x(bp
))
13494 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e2_sb
;
13496 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e1x_sb
;
13498 cp
->irq_arr
[0].status_blk_num
= bnx2x_cnic_fw_sb_id(bp
);
13499 cp
->irq_arr
[0].status_blk_num2
= bnx2x_cnic_igu_sb_id(bp
);
13500 cp
->irq_arr
[1].status_blk
= bp
->def_status_blk
;
13501 cp
->irq_arr
[1].status_blk_num
= DEF_SB_ID
;
13502 cp
->irq_arr
[1].status_blk_num2
= DEF_SB_IGU_ID
;
13507 void bnx2x_setup_cnic_info(struct bnx2x
*bp
)
13509 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13512 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
13513 bnx2x_cid_ilt_lines(bp
);
13514 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
13515 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
13516 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
13518 if (NO_ISCSI_OOO(bp
))
13519 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
13522 static int bnx2x_register_cnic(struct net_device
*dev
, struct cnic_ops
*ops
,
13525 struct bnx2x
*bp
= netdev_priv(dev
);
13526 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13529 DP(NETIF_MSG_IFUP
, "Register_cnic called\n");
13532 BNX2X_ERR("NULL ops received\n");
13536 if (!CNIC_SUPPORT(bp
)) {
13537 BNX2X_ERR("Can't register CNIC when not supported\n");
13538 return -EOPNOTSUPP
;
13541 if (!CNIC_LOADED(bp
)) {
13542 rc
= bnx2x_load_cnic(bp
);
13544 BNX2X_ERR("CNIC-related load failed\n");
13550 bp
->cnic_enabled
= true;
13552 bp
->cnic_kwq
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
13556 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
13557 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
13558 bp
->cnic_kwq_last
= bp
->cnic_kwq
+ MAX_SP_DESC_CNT
;
13560 bp
->cnic_spq_pending
= 0;
13561 bp
->cnic_kwq_pending
= 0;
13563 bp
->cnic_data
= data
;
13566 cp
->drv_state
|= CNIC_DRV_STATE_REGD
;
13567 cp
->iro_arr
= bp
->iro_arr
;
13569 bnx2x_setup_cnic_irq_info(bp
);
13571 rcu_assign_pointer(bp
->cnic_ops
, ops
);
13576 static int bnx2x_unregister_cnic(struct net_device
*dev
)
13578 struct bnx2x
*bp
= netdev_priv(dev
);
13579 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13581 mutex_lock(&bp
->cnic_mutex
);
13583 RCU_INIT_POINTER(bp
->cnic_ops
, NULL
);
13584 mutex_unlock(&bp
->cnic_mutex
);
13586 bp
->cnic_enabled
= false;
13587 kfree(bp
->cnic_kwq
);
13588 bp
->cnic_kwq
= NULL
;
13593 struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
)
13595 struct bnx2x
*bp
= netdev_priv(dev
);
13596 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
13598 /* If both iSCSI and FCoE are disabled - return NULL in
13599 * order to indicate CNIC that it should not try to work
13600 * with this device.
13602 if (NO_ISCSI(bp
) && NO_FCOE(bp
))
13605 cp
->drv_owner
= THIS_MODULE
;
13606 cp
->chip_id
= CHIP_ID(bp
);
13607 cp
->pdev
= bp
->pdev
;
13608 cp
->io_base
= bp
->regview
;
13609 cp
->io_base2
= bp
->doorbells
;
13610 cp
->max_kwqe_pending
= 8;
13611 cp
->ctx_blk_size
= CDU_ILT_PAGE_SZ
;
13612 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
13613 bnx2x_cid_ilt_lines(bp
);
13614 cp
->ctx_tbl_len
= CNIC_ILT_LINES
;
13615 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
13616 cp
->drv_submit_kwqes_16
= bnx2x_cnic_sp_queue
;
13617 cp
->drv_ctl
= bnx2x_drv_ctl
;
13618 cp
->drv_register_cnic
= bnx2x_register_cnic
;
13619 cp
->drv_unregister_cnic
= bnx2x_unregister_cnic
;
13620 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
13621 cp
->iscsi_l2_client_id
=
13622 bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
13623 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
13625 if (NO_ISCSI_OOO(bp
))
13626 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
13629 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI
;
13632 cp
->drv_state
|= CNIC_DRV_STATE_NO_FCOE
;
13635 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13637 cp
->ctx_tbl_offset
,
13643 u32
bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath
*fp
)
13645 struct bnx2x
*bp
= fp
->bp
;
13646 u32 offset
= BAR_USTRORM_INTMEM
;
13649 return bnx2x_vf_ustorm_prods_offset(bp
, fp
);
13650 else if (!CHIP_IS_E1x(bp
))
13651 offset
+= USTORM_RX_PRODS_E2_OFFSET(fp
->cl_qzone_id
);
13653 offset
+= USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp
), fp
->cl_id
);
13658 /* called only on E1H or E2.
13659 * When pretending to be PF, the pretend value is the function number 0...7
13660 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13663 int bnx2x_pretend_func(struct bnx2x
*bp
, u16 pretend_func_val
)
13667 if (CHIP_IS_E1H(bp
) && pretend_func_val
>= E1H_FUNC_MAX
)
13670 /* get my own pretend register */
13671 pretend_reg
= bnx2x_get_pretend_reg(bp
);
13672 REG_WR(bp
, pretend_reg
, pretend_func_val
);
13673 REG_RD(bp
, pretend_reg
);