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net: vlan: rename NETIF_F_HW_VLAN_* feature flags to NETIF_F_HW_VLAN_CTAG_*
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <net/ip.h>
44 #include <net/ipv6.h>
45 #include <net/tcp.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
53 #include <linux/io.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_vfpf.h"
63 #include "bnx2x_dcb.h"
64 #include "bnx2x_sp.h"
65
66 #include <linux/firmware.h>
67 #include "bnx2x_fw_file_hdr.h"
68 /* FW files */
69 #define FW_FILE_VERSION \
70 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
71 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
72 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
73 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
74 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
76 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
77
78 /* Time in jiffies before concluding the transmitter is hung */
79 #define TX_TIMEOUT (5*HZ)
80
81 static char version[] =
82 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
83 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
84
85 MODULE_AUTHOR("Eliezer Tamir");
86 MODULE_DESCRIPTION("Broadcom NetXtreme II "
87 "BCM57710/57711/57711E/"
88 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
89 "57840/57840_MF Driver");
90 MODULE_LICENSE("GPL");
91 MODULE_VERSION(DRV_MODULE_VERSION);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
94 MODULE_FIRMWARE(FW_FILE_NAME_E2);
95
96
97 int num_queues;
98 module_param(num_queues, int, 0);
99 MODULE_PARM_DESC(num_queues,
100 " Set number of queues (default is as a number of CPUs)");
101
102 static int disable_tpa;
103 module_param(disable_tpa, int, 0);
104 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
105
106 #define INT_MODE_INTx 1
107 #define INT_MODE_MSI 2
108 int int_mode;
109 module_param(int_mode, int, 0);
110 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
111 "(1 INT#x; 2 MSI)");
112
113 static int dropless_fc;
114 module_param(dropless_fc, int, 0);
115 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
116
117 static int mrrs = -1;
118 module_param(mrrs, int, 0);
119 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
120
121 static int debug;
122 module_param(debug, int, 0);
123 MODULE_PARM_DESC(debug, " Default debug msglevel");
124
125
126
127 struct workqueue_struct *bnx2x_wq;
128
129 struct bnx2x_mac_vals {
130 u32 xmac_addr;
131 u32 xmac_val;
132 u32 emac_addr;
133 u32 emac_val;
134 u32 umac_addr;
135 u32 umac_val;
136 u32 bmac_addr;
137 u32 bmac_val[2];
138 };
139
140 enum bnx2x_board_type {
141 BCM57710 = 0,
142 BCM57711,
143 BCM57711E,
144 BCM57712,
145 BCM57712_MF,
146 BCM57712_VF,
147 BCM57800,
148 BCM57800_MF,
149 BCM57800_VF,
150 BCM57810,
151 BCM57810_MF,
152 BCM57810_VF,
153 BCM57840_4_10,
154 BCM57840_2_20,
155 BCM57840_MF,
156 BCM57840_VF,
157 BCM57811,
158 BCM57811_MF,
159 BCM57840_O,
160 BCM57840_MFO,
161 BCM57811_VF
162 };
163
164 /* indexed by board_type, above */
165 static struct {
166 char *name;
167 } board_info[] = {
168 [BCM57710] = { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
169 [BCM57711] = { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
170 [BCM57711E] = { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
171 [BCM57712] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
172 [BCM57712_MF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
173 [BCM57712_VF] = { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Virtual Function" },
174 [BCM57800] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
175 [BCM57800_MF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
176 [BCM57800_VF] = { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Virtual Function" },
177 [BCM57810] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
178 [BCM57810_MF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
179 [BCM57810_VF] = { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Virtual Function" },
180 [BCM57840_4_10] = { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
181 [BCM57840_2_20] = { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
182 [BCM57840_MF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
183 [BCM57840_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" },
184 [BCM57811] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet" },
185 [BCM57811_MF] = { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function" },
186 [BCM57840_O] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
187 [BCM57840_MFO] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function" },
188 [BCM57811_VF] = { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Virtual Function" }
189 };
190
191 #ifndef PCI_DEVICE_ID_NX2_57710
192 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
193 #endif
194 #ifndef PCI_DEVICE_ID_NX2_57711
195 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
196 #endif
197 #ifndef PCI_DEVICE_ID_NX2_57711E
198 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
199 #endif
200 #ifndef PCI_DEVICE_ID_NX2_57712
201 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
202 #endif
203 #ifndef PCI_DEVICE_ID_NX2_57712_MF
204 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
205 #endif
206 #ifndef PCI_DEVICE_ID_NX2_57712_VF
207 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
208 #endif
209 #ifndef PCI_DEVICE_ID_NX2_57800
210 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
211 #endif
212 #ifndef PCI_DEVICE_ID_NX2_57800_MF
213 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
214 #endif
215 #ifndef PCI_DEVICE_ID_NX2_57800_VF
216 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
217 #endif
218 #ifndef PCI_DEVICE_ID_NX2_57810
219 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
220 #endif
221 #ifndef PCI_DEVICE_ID_NX2_57810_MF
222 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
223 #endif
224 #ifndef PCI_DEVICE_ID_NX2_57840_O
225 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
226 #endif
227 #ifndef PCI_DEVICE_ID_NX2_57810_VF
228 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
229 #endif
230 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
231 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
232 #endif
233 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
234 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
235 #endif
236 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
237 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
238 #endif
239 #ifndef PCI_DEVICE_ID_NX2_57840_MF
240 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
241 #endif
242 #ifndef PCI_DEVICE_ID_NX2_57840_VF
243 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
244 #endif
245 #ifndef PCI_DEVICE_ID_NX2_57811
246 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
247 #endif
248 #ifndef PCI_DEVICE_ID_NX2_57811_MF
249 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
250 #endif
251 #ifndef PCI_DEVICE_ID_NX2_57811_VF
252 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
253 #endif
254
255 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
256 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
257 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
258 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
259 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
260 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
261 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_VF), BCM57712_VF },
262 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
263 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
264 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_VF), BCM57800_VF },
265 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
266 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
267 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
268 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
269 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
270 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_VF), BCM57810_VF },
271 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
272 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
273 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_VF), BCM57840_VF },
274 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
275 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
276 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_VF), BCM57811_VF },
277 { 0 }
278 };
279
280 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
281
282 /* Global resources for unloading a previously loaded device */
283 #define BNX2X_PREV_WAIT_NEEDED 1
284 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
285 static LIST_HEAD(bnx2x_prev_list);
286 /****************************************************************************
287 * General service functions
288 ****************************************************************************/
289
290 static void __storm_memset_dma_mapping(struct bnx2x *bp,
291 u32 addr, dma_addr_t mapping)
292 {
293 REG_WR(bp, addr, U64_LO(mapping));
294 REG_WR(bp, addr + 4, U64_HI(mapping));
295 }
296
297 static void storm_memset_spq_addr(struct bnx2x *bp,
298 dma_addr_t mapping, u16 abs_fid)
299 {
300 u32 addr = XSEM_REG_FAST_MEMORY +
301 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
302
303 __storm_memset_dma_mapping(bp, addr, mapping);
304 }
305
306 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
307 u16 pf_id)
308 {
309 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
310 pf_id);
311 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
312 pf_id);
313 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
314 pf_id);
315 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
316 pf_id);
317 }
318
319 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
320 u8 enable)
321 {
322 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
323 enable);
324 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
325 enable);
326 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
327 enable);
328 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
329 enable);
330 }
331
332 static void storm_memset_eq_data(struct bnx2x *bp,
333 struct event_ring_data *eq_data,
334 u16 pfid)
335 {
336 size_t size = sizeof(struct event_ring_data);
337
338 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
339
340 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
341 }
342
343 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
344 u16 pfid)
345 {
346 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
347 REG_WR16(bp, addr, eq_prod);
348 }
349
350 /* used only at init
351 * locking is done by mcp
352 */
353 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
354 {
355 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
356 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
357 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
358 PCICFG_VENDOR_ID_OFFSET);
359 }
360
361 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
362 {
363 u32 val;
364
365 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
366 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
367 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
368 PCICFG_VENDOR_ID_OFFSET);
369
370 return val;
371 }
372
373 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
374 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
375 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
376 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
377 #define DMAE_DP_DST_NONE "dst_addr [none]"
378
379 void bnx2x_dp_dmae(struct bnx2x *bp, struct dmae_command *dmae, int msglvl)
380 {
381 u32 src_type = dmae->opcode & DMAE_COMMAND_SRC;
382
383 switch (dmae->opcode & DMAE_COMMAND_DST) {
384 case DMAE_CMD_DST_PCI:
385 if (src_type == DMAE_CMD_SRC_PCI)
386 DP(msglvl, "DMAE: opcode 0x%08x\n"
387 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
388 "comp_addr [%x:%08x], comp_val 0x%08x\n",
389 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
390 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
391 dmae->comp_addr_hi, dmae->comp_addr_lo,
392 dmae->comp_val);
393 else
394 DP(msglvl, "DMAE: opcode 0x%08x\n"
395 "src [%08x], len [%d*4], dst [%x:%08x]\n"
396 "comp_addr [%x:%08x], comp_val 0x%08x\n",
397 dmae->opcode, dmae->src_addr_lo >> 2,
398 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo,
399 dmae->comp_addr_hi, dmae->comp_addr_lo,
400 dmae->comp_val);
401 break;
402 case DMAE_CMD_DST_GRC:
403 if (src_type == DMAE_CMD_SRC_PCI)
404 DP(msglvl, "DMAE: opcode 0x%08x\n"
405 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
406 "comp_addr [%x:%08x], comp_val 0x%08x\n",
407 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
408 dmae->len, dmae->dst_addr_lo >> 2,
409 dmae->comp_addr_hi, dmae->comp_addr_lo,
410 dmae->comp_val);
411 else
412 DP(msglvl, "DMAE: opcode 0x%08x\n"
413 "src [%08x], len [%d*4], dst [%08x]\n"
414 "comp_addr [%x:%08x], comp_val 0x%08x\n",
415 dmae->opcode, dmae->src_addr_lo >> 2,
416 dmae->len, dmae->dst_addr_lo >> 2,
417 dmae->comp_addr_hi, dmae->comp_addr_lo,
418 dmae->comp_val);
419 break;
420 default:
421 if (src_type == DMAE_CMD_SRC_PCI)
422 DP(msglvl, "DMAE: opcode 0x%08x\n"
423 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
424 "comp_addr [%x:%08x] comp_val 0x%08x\n",
425 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo,
426 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
427 dmae->comp_val);
428 else
429 DP(msglvl, "DMAE: opcode 0x%08x\n"
430 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
431 "comp_addr [%x:%08x] comp_val 0x%08x\n",
432 dmae->opcode, dmae->src_addr_lo >> 2,
433 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo,
434 dmae->comp_val);
435 break;
436 }
437 }
438
439 /* copy command into DMAE command memory and set DMAE command go */
440 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
441 {
442 u32 cmd_offset;
443 int i;
444
445 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
446 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
447 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
448 }
449 REG_WR(bp, dmae_reg_go_c[idx], 1);
450 }
451
452 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
453 {
454 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
455 DMAE_CMD_C_ENABLE);
456 }
457
458 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
459 {
460 return opcode & ~DMAE_CMD_SRC_RESET;
461 }
462
463 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
464 bool with_comp, u8 comp_type)
465 {
466 u32 opcode = 0;
467
468 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
469 (dst_type << DMAE_COMMAND_DST_SHIFT));
470
471 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
472
473 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
474 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
475 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
476 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
477
478 #ifdef __BIG_ENDIAN
479 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
480 #else
481 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
482 #endif
483 if (with_comp)
484 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
485 return opcode;
486 }
487
488 void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
489 struct dmae_command *dmae,
490 u8 src_type, u8 dst_type)
491 {
492 memset(dmae, 0, sizeof(struct dmae_command));
493
494 /* set the opcode */
495 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
496 true, DMAE_COMP_PCI);
497
498 /* fill in the completion parameters */
499 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
500 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
501 dmae->comp_val = DMAE_COMP_VAL;
502 }
503
504 /* issue a dmae command over the init-channel and wait for completion */
505 int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae)
506 {
507 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
508 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
509 int rc = 0;
510
511 /*
512 * Lock the dmae channel. Disable BHs to prevent a dead-lock
513 * as long as this code is called both from syscall context and
514 * from ndo_set_rx_mode() flow that may be called from BH.
515 */
516 spin_lock_bh(&bp->dmae_lock);
517
518 /* reset completion */
519 *wb_comp = 0;
520
521 /* post the command on the channel used for initializations */
522 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
523
524 /* wait for completion */
525 udelay(5);
526 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
527
528 if (!cnt ||
529 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
530 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
531 BNX2X_ERR("DMAE timeout!\n");
532 rc = DMAE_TIMEOUT;
533 goto unlock;
534 }
535 cnt--;
536 udelay(50);
537 }
538 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
539 BNX2X_ERR("DMAE PCI error!\n");
540 rc = DMAE_PCI_ERROR;
541 }
542
543 unlock:
544 spin_unlock_bh(&bp->dmae_lock);
545 return rc;
546 }
547
548 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
549 u32 len32)
550 {
551 struct dmae_command dmae;
552
553 if (!bp->dmae_ready) {
554 u32 *data = bnx2x_sp(bp, wb_data[0]);
555
556 if (CHIP_IS_E1(bp))
557 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
558 else
559 bnx2x_init_str_wr(bp, dst_addr, data, len32);
560 return;
561 }
562
563 /* set opcode and fixed command fields */
564 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
565
566 /* fill in addresses and len */
567 dmae.src_addr_lo = U64_LO(dma_addr);
568 dmae.src_addr_hi = U64_HI(dma_addr);
569 dmae.dst_addr_lo = dst_addr >> 2;
570 dmae.dst_addr_hi = 0;
571 dmae.len = len32;
572
573 /* issue the command and wait for completion */
574 bnx2x_issue_dmae_with_comp(bp, &dmae);
575 }
576
577 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
578 {
579 struct dmae_command dmae;
580
581 if (!bp->dmae_ready) {
582 u32 *data = bnx2x_sp(bp, wb_data[0]);
583 int i;
584
585 if (CHIP_IS_E1(bp))
586 for (i = 0; i < len32; i++)
587 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
588 else
589 for (i = 0; i < len32; i++)
590 data[i] = REG_RD(bp, src_addr + i*4);
591
592 return;
593 }
594
595 /* set opcode and fixed command fields */
596 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
597
598 /* fill in addresses and len */
599 dmae.src_addr_lo = src_addr >> 2;
600 dmae.src_addr_hi = 0;
601 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
602 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
603 dmae.len = len32;
604
605 /* issue the command and wait for completion */
606 bnx2x_issue_dmae_with_comp(bp, &dmae);
607 }
608
609 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
610 u32 addr, u32 len)
611 {
612 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
613 int offset = 0;
614
615 while (len > dmae_wr_max) {
616 bnx2x_write_dmae(bp, phys_addr + offset,
617 addr + offset, dmae_wr_max);
618 offset += dmae_wr_max * 4;
619 len -= dmae_wr_max;
620 }
621
622 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
623 }
624
625 static int bnx2x_mc_assert(struct bnx2x *bp)
626 {
627 char last_idx;
628 int i, rc = 0;
629 u32 row0, row1, row2, row3;
630
631 /* XSTORM */
632 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
633 XSTORM_ASSERT_LIST_INDEX_OFFSET);
634 if (last_idx)
635 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
636
637 /* print the asserts */
638 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
639
640 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
641 XSTORM_ASSERT_LIST_OFFSET(i));
642 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
643 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
644 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
645 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
646 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
647 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
648
649 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
650 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
651 i, row3, row2, row1, row0);
652 rc++;
653 } else {
654 break;
655 }
656 }
657
658 /* TSTORM */
659 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
660 TSTORM_ASSERT_LIST_INDEX_OFFSET);
661 if (last_idx)
662 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
663
664 /* print the asserts */
665 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
666
667 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
668 TSTORM_ASSERT_LIST_OFFSET(i));
669 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
670 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
671 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
672 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
673 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
674 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
675
676 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
677 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
678 i, row3, row2, row1, row0);
679 rc++;
680 } else {
681 break;
682 }
683 }
684
685 /* CSTORM */
686 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
687 CSTORM_ASSERT_LIST_INDEX_OFFSET);
688 if (last_idx)
689 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
690
691 /* print the asserts */
692 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
693
694 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
695 CSTORM_ASSERT_LIST_OFFSET(i));
696 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
697 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
698 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
699 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
700 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
701 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
702
703 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
704 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
705 i, row3, row2, row1, row0);
706 rc++;
707 } else {
708 break;
709 }
710 }
711
712 /* USTORM */
713 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
714 USTORM_ASSERT_LIST_INDEX_OFFSET);
715 if (last_idx)
716 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
717
718 /* print the asserts */
719 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
720
721 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
722 USTORM_ASSERT_LIST_OFFSET(i));
723 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
724 USTORM_ASSERT_LIST_OFFSET(i) + 4);
725 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
726 USTORM_ASSERT_LIST_OFFSET(i) + 8);
727 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
728 USTORM_ASSERT_LIST_OFFSET(i) + 12);
729
730 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
731 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
732 i, row3, row2, row1, row0);
733 rc++;
734 } else {
735 break;
736 }
737 }
738
739 return rc;
740 }
741
742 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
743 {
744 u32 addr, val;
745 u32 mark, offset;
746 __be32 data[9];
747 int word;
748 u32 trace_shmem_base;
749 if (BP_NOMCP(bp)) {
750 BNX2X_ERR("NO MCP - can not dump\n");
751 return;
752 }
753 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
754 (bp->common.bc_ver & 0xff0000) >> 16,
755 (bp->common.bc_ver & 0xff00) >> 8,
756 (bp->common.bc_ver & 0xff));
757
758 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
759 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
760 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
761
762 if (BP_PATH(bp) == 0)
763 trace_shmem_base = bp->common.shmem_base;
764 else
765 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
766 addr = trace_shmem_base - 0x800;
767
768 /* validate TRCB signature */
769 mark = REG_RD(bp, addr);
770 if (mark != MFW_TRACE_SIGNATURE) {
771 BNX2X_ERR("Trace buffer signature is missing.");
772 return ;
773 }
774
775 /* read cyclic buffer pointer */
776 addr += 4;
777 mark = REG_RD(bp, addr);
778 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
779 + ((mark + 0x3) & ~0x3) - 0x08000000;
780 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
781
782 printk("%s", lvl);
783
784 /* dump buffer after the mark */
785 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
786 for (word = 0; word < 8; word++)
787 data[word] = htonl(REG_RD(bp, offset + 4*word));
788 data[8] = 0x0;
789 pr_cont("%s", (char *)data);
790 }
791
792 /* dump buffer before the mark */
793 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
794 for (word = 0; word < 8; word++)
795 data[word] = htonl(REG_RD(bp, offset + 4*word));
796 data[8] = 0x0;
797 pr_cont("%s", (char *)data);
798 }
799 printk("%s" "end of fw dump\n", lvl);
800 }
801
802 static void bnx2x_fw_dump(struct bnx2x *bp)
803 {
804 bnx2x_fw_dump_lvl(bp, KERN_ERR);
805 }
806
807 static void bnx2x_hc_int_disable(struct bnx2x *bp)
808 {
809 int port = BP_PORT(bp);
810 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
811 u32 val = REG_RD(bp, addr);
812
813 /* in E1 we must use only PCI configuration space to disable
814 * MSI/MSIX capablility
815 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
816 */
817 if (CHIP_IS_E1(bp)) {
818 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
819 * Use mask register to prevent from HC sending interrupts
820 * after we exit the function
821 */
822 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
823
824 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
825 HC_CONFIG_0_REG_INT_LINE_EN_0 |
826 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
827 } else
828 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
829 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
830 HC_CONFIG_0_REG_INT_LINE_EN_0 |
831 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
832
833 DP(NETIF_MSG_IFDOWN,
834 "write %x to HC %d (addr 0x%x)\n",
835 val, port, addr);
836
837 /* flush all outstanding writes */
838 mmiowb();
839
840 REG_WR(bp, addr, val);
841 if (REG_RD(bp, addr) != val)
842 BNX2X_ERR("BUG! proper val not read from IGU!\n");
843 }
844
845 static void bnx2x_igu_int_disable(struct bnx2x *bp)
846 {
847 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
848
849 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
850 IGU_PF_CONF_INT_LINE_EN |
851 IGU_PF_CONF_ATTN_BIT_EN);
852
853 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
854
855 /* flush all outstanding writes */
856 mmiowb();
857
858 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
859 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
860 BNX2X_ERR("BUG! proper val not read from IGU!\n");
861 }
862
863 static void bnx2x_int_disable(struct bnx2x *bp)
864 {
865 if (bp->common.int_block == INT_BLOCK_HC)
866 bnx2x_hc_int_disable(bp);
867 else
868 bnx2x_igu_int_disable(bp);
869 }
870
871 void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
872 {
873 int i;
874 u16 j;
875 struct hc_sp_status_block_data sp_sb_data;
876 int func = BP_FUNC(bp);
877 #ifdef BNX2X_STOP_ON_ERROR
878 u16 start = 0, end = 0;
879 u8 cos;
880 #endif
881 if (disable_int)
882 bnx2x_int_disable(bp);
883
884 bp->stats_state = STATS_STATE_DISABLED;
885 bp->eth_stats.unrecoverable_error++;
886 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
887
888 BNX2X_ERR("begin crash dump -----------------\n");
889
890 /* Indices */
891 /* Common */
892 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
893 bp->def_idx, bp->def_att_idx, bp->attn_state,
894 bp->spq_prod_idx, bp->stats_counter);
895 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
896 bp->def_status_blk->atten_status_block.attn_bits,
897 bp->def_status_blk->atten_status_block.attn_bits_ack,
898 bp->def_status_blk->atten_status_block.status_block_id,
899 bp->def_status_blk->atten_status_block.attn_bits_index);
900 BNX2X_ERR(" def (");
901 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
902 pr_cont("0x%x%s",
903 bp->def_status_blk->sp_sb.index_values[i],
904 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
905
906 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
907 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
908 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
909 i*sizeof(u32));
910
911 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
912 sp_sb_data.igu_sb_id,
913 sp_sb_data.igu_seg_id,
914 sp_sb_data.p_func.pf_id,
915 sp_sb_data.p_func.vnic_id,
916 sp_sb_data.p_func.vf_id,
917 sp_sb_data.p_func.vf_valid,
918 sp_sb_data.state);
919
920
921 for_each_eth_queue(bp, i) {
922 struct bnx2x_fastpath *fp = &bp->fp[i];
923 int loop;
924 struct hc_status_block_data_e2 sb_data_e2;
925 struct hc_status_block_data_e1x sb_data_e1x;
926 struct hc_status_block_sm *hc_sm_p =
927 CHIP_IS_E1x(bp) ?
928 sb_data_e1x.common.state_machine :
929 sb_data_e2.common.state_machine;
930 struct hc_index_data *hc_index_p =
931 CHIP_IS_E1x(bp) ?
932 sb_data_e1x.index_data :
933 sb_data_e2.index_data;
934 u8 data_size, cos;
935 u32 *sb_data_p;
936 struct bnx2x_fp_txdata txdata;
937
938 /* Rx */
939 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
940 i, fp->rx_bd_prod, fp->rx_bd_cons,
941 fp->rx_comp_prod,
942 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
943 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
944 fp->rx_sge_prod, fp->last_max_sge,
945 le16_to_cpu(fp->fp_hc_idx));
946
947 /* Tx */
948 for_each_cos_in_tx_queue(fp, cos)
949 {
950 txdata = *fp->txdata_ptr[cos];
951 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
952 i, txdata.tx_pkt_prod,
953 txdata.tx_pkt_cons, txdata.tx_bd_prod,
954 txdata.tx_bd_cons,
955 le16_to_cpu(*txdata.tx_cons_sb));
956 }
957
958 loop = CHIP_IS_E1x(bp) ?
959 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
960
961 /* host sb data */
962
963 if (IS_FCOE_FP(fp))
964 continue;
965
966 BNX2X_ERR(" run indexes (");
967 for (j = 0; j < HC_SB_MAX_SM; j++)
968 pr_cont("0x%x%s",
969 fp->sb_running_index[j],
970 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
971
972 BNX2X_ERR(" indexes (");
973 for (j = 0; j < loop; j++)
974 pr_cont("0x%x%s",
975 fp->sb_index_values[j],
976 (j == loop - 1) ? ")" : " ");
977 /* fw sb data */
978 data_size = CHIP_IS_E1x(bp) ?
979 sizeof(struct hc_status_block_data_e1x) :
980 sizeof(struct hc_status_block_data_e2);
981 data_size /= sizeof(u32);
982 sb_data_p = CHIP_IS_E1x(bp) ?
983 (u32 *)&sb_data_e1x :
984 (u32 *)&sb_data_e2;
985 /* copy sb data in here */
986 for (j = 0; j < data_size; j++)
987 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
988 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
989 j * sizeof(u32));
990
991 if (!CHIP_IS_E1x(bp)) {
992 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
993 sb_data_e2.common.p_func.pf_id,
994 sb_data_e2.common.p_func.vf_id,
995 sb_data_e2.common.p_func.vf_valid,
996 sb_data_e2.common.p_func.vnic_id,
997 sb_data_e2.common.same_igu_sb_1b,
998 sb_data_e2.common.state);
999 } else {
1000 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1001 sb_data_e1x.common.p_func.pf_id,
1002 sb_data_e1x.common.p_func.vf_id,
1003 sb_data_e1x.common.p_func.vf_valid,
1004 sb_data_e1x.common.p_func.vnic_id,
1005 sb_data_e1x.common.same_igu_sb_1b,
1006 sb_data_e1x.common.state);
1007 }
1008
1009 /* SB_SMs data */
1010 for (j = 0; j < HC_SB_MAX_SM; j++) {
1011 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1012 j, hc_sm_p[j].__flags,
1013 hc_sm_p[j].igu_sb_id,
1014 hc_sm_p[j].igu_seg_id,
1015 hc_sm_p[j].time_to_expire,
1016 hc_sm_p[j].timer_value);
1017 }
1018
1019 /* Indecies data */
1020 for (j = 0; j < loop; j++) {
1021 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
1022 hc_index_p[j].flags,
1023 hc_index_p[j].timeout);
1024 }
1025 }
1026
1027 #ifdef BNX2X_STOP_ON_ERROR
1028
1029 /* event queue */
1030 for (i = 0; i < NUM_EQ_DESC; i++) {
1031 u32 *data = (u32 *)&bp->eq_ring[i].message.data;
1032
1033 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1034 i, bp->eq_ring[i].message.opcode,
1035 bp->eq_ring[i].message.error);
1036 BNX2X_ERR("data: %x %x %x\n", data[0], data[1], data[2]);
1037 }
1038
1039 /* Rings */
1040 /* Rx */
1041 for_each_valid_rx_queue(bp, i) {
1042 struct bnx2x_fastpath *fp = &bp->fp[i];
1043
1044 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
1045 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
1046 for (j = start; j != end; j = RX_BD(j + 1)) {
1047 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
1048 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
1049
1050 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1051 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
1052 }
1053
1054 start = RX_SGE(fp->rx_sge_prod);
1055 end = RX_SGE(fp->last_max_sge);
1056 for (j = start; j != end; j = RX_SGE(j + 1)) {
1057 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
1058 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
1059
1060 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1061 i, j, rx_sge[1], rx_sge[0], sw_page->page);
1062 }
1063
1064 start = RCQ_BD(fp->rx_comp_cons - 10);
1065 end = RCQ_BD(fp->rx_comp_cons + 503);
1066 for (j = start; j != end; j = RCQ_BD(j + 1)) {
1067 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
1068
1069 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1070 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
1071 }
1072 }
1073
1074 /* Tx */
1075 for_each_valid_tx_queue(bp, i) {
1076 struct bnx2x_fastpath *fp = &bp->fp[i];
1077 for_each_cos_in_tx_queue(fp, cos) {
1078 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
1079
1080 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
1081 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
1082 for (j = start; j != end; j = TX_BD(j + 1)) {
1083 struct sw_tx_bd *sw_bd =
1084 &txdata->tx_buf_ring[j];
1085
1086 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1087 i, cos, j, sw_bd->skb,
1088 sw_bd->first_bd);
1089 }
1090
1091 start = TX_BD(txdata->tx_bd_cons - 10);
1092 end = TX_BD(txdata->tx_bd_cons + 254);
1093 for (j = start; j != end; j = TX_BD(j + 1)) {
1094 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
1095
1096 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1097 i, cos, j, tx_bd[0], tx_bd[1],
1098 tx_bd[2], tx_bd[3]);
1099 }
1100 }
1101 }
1102 #endif
1103 bnx2x_fw_dump(bp);
1104 bnx2x_mc_assert(bp);
1105 BNX2X_ERR("end crash dump -----------------\n");
1106 }
1107
1108 /*
1109 * FLR Support for E2
1110 *
1111 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1112 * initialization.
1113 */
1114 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
1115 #define FLR_WAIT_INTERVAL 50 /* usec */
1116 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1117
1118 struct pbf_pN_buf_regs {
1119 int pN;
1120 u32 init_crd;
1121 u32 crd;
1122 u32 crd_freed;
1123 };
1124
1125 struct pbf_pN_cmd_regs {
1126 int pN;
1127 u32 lines_occup;
1128 u32 lines_freed;
1129 };
1130
1131 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
1132 struct pbf_pN_buf_regs *regs,
1133 u32 poll_count)
1134 {
1135 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
1136 u32 cur_cnt = poll_count;
1137
1138 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
1139 crd = crd_start = REG_RD(bp, regs->crd);
1140 init_crd = REG_RD(bp, regs->init_crd);
1141
1142 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
1143 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
1144 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
1145
1146 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
1147 (init_crd - crd_start))) {
1148 if (cur_cnt--) {
1149 udelay(FLR_WAIT_INTERVAL);
1150 crd = REG_RD(bp, regs->crd);
1151 crd_freed = REG_RD(bp, regs->crd_freed);
1152 } else {
1153 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
1154 regs->pN);
1155 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
1156 regs->pN, crd);
1157 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
1158 regs->pN, crd_freed);
1159 break;
1160 }
1161 }
1162 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1163 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1164 }
1165
1166 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
1167 struct pbf_pN_cmd_regs *regs,
1168 u32 poll_count)
1169 {
1170 u32 occup, to_free, freed, freed_start;
1171 u32 cur_cnt = poll_count;
1172
1173 occup = to_free = REG_RD(bp, regs->lines_occup);
1174 freed = freed_start = REG_RD(bp, regs->lines_freed);
1175
1176 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
1177 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
1178
1179 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1180 if (cur_cnt--) {
1181 udelay(FLR_WAIT_INTERVAL);
1182 occup = REG_RD(bp, regs->lines_occup);
1183 freed = REG_RD(bp, regs->lines_freed);
1184 } else {
1185 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1186 regs->pN);
1187 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1188 regs->pN, occup);
1189 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1190 regs->pN, freed);
1191 break;
1192 }
1193 }
1194 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1195 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1196 }
1197
1198 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1199 u32 expected, u32 poll_count)
1200 {
1201 u32 cur_cnt = poll_count;
1202 u32 val;
1203
1204 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1205 udelay(FLR_WAIT_INTERVAL);
1206
1207 return val;
1208 }
1209
1210 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1211 char *msg, u32 poll_cnt)
1212 {
1213 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1214 if (val != 0) {
1215 BNX2X_ERR("%s usage count=%d\n", msg, val);
1216 return 1;
1217 }
1218 return 0;
1219 }
1220
1221 /* Common routines with VF FLR cleanup */
1222 u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1223 {
1224 /* adjust polling timeout */
1225 if (CHIP_REV_IS_EMUL(bp))
1226 return FLR_POLL_CNT * 2000;
1227
1228 if (CHIP_REV_IS_FPGA(bp))
1229 return FLR_POLL_CNT * 120;
1230
1231 return FLR_POLL_CNT;
1232 }
1233
1234 void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1235 {
1236 struct pbf_pN_cmd_regs cmd_regs[] = {
1237 {0, (CHIP_IS_E3B0(bp)) ?
1238 PBF_REG_TQ_OCCUPANCY_Q0 :
1239 PBF_REG_P0_TQ_OCCUPANCY,
1240 (CHIP_IS_E3B0(bp)) ?
1241 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1242 PBF_REG_P0_TQ_LINES_FREED_CNT},
1243 {1, (CHIP_IS_E3B0(bp)) ?
1244 PBF_REG_TQ_OCCUPANCY_Q1 :
1245 PBF_REG_P1_TQ_OCCUPANCY,
1246 (CHIP_IS_E3B0(bp)) ?
1247 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1248 PBF_REG_P1_TQ_LINES_FREED_CNT},
1249 {4, (CHIP_IS_E3B0(bp)) ?
1250 PBF_REG_TQ_OCCUPANCY_LB_Q :
1251 PBF_REG_P4_TQ_OCCUPANCY,
1252 (CHIP_IS_E3B0(bp)) ?
1253 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1254 PBF_REG_P4_TQ_LINES_FREED_CNT}
1255 };
1256
1257 struct pbf_pN_buf_regs buf_regs[] = {
1258 {0, (CHIP_IS_E3B0(bp)) ?
1259 PBF_REG_INIT_CRD_Q0 :
1260 PBF_REG_P0_INIT_CRD ,
1261 (CHIP_IS_E3B0(bp)) ?
1262 PBF_REG_CREDIT_Q0 :
1263 PBF_REG_P0_CREDIT,
1264 (CHIP_IS_E3B0(bp)) ?
1265 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1266 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1267 {1, (CHIP_IS_E3B0(bp)) ?
1268 PBF_REG_INIT_CRD_Q1 :
1269 PBF_REG_P1_INIT_CRD,
1270 (CHIP_IS_E3B0(bp)) ?
1271 PBF_REG_CREDIT_Q1 :
1272 PBF_REG_P1_CREDIT,
1273 (CHIP_IS_E3B0(bp)) ?
1274 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1275 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1276 {4, (CHIP_IS_E3B0(bp)) ?
1277 PBF_REG_INIT_CRD_LB_Q :
1278 PBF_REG_P4_INIT_CRD,
1279 (CHIP_IS_E3B0(bp)) ?
1280 PBF_REG_CREDIT_LB_Q :
1281 PBF_REG_P4_CREDIT,
1282 (CHIP_IS_E3B0(bp)) ?
1283 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1284 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1285 };
1286
1287 int i;
1288
1289 /* Verify the command queues are flushed P0, P1, P4 */
1290 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1291 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1292
1293
1294 /* Verify the transmission buffers are flushed P0, P1, P4 */
1295 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1296 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1297 }
1298
1299 #define OP_GEN_PARAM(param) \
1300 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1301
1302 #define OP_GEN_TYPE(type) \
1303 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1304
1305 #define OP_GEN_AGG_VECT(index) \
1306 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1307
1308
1309 int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func, u32 poll_cnt)
1310 {
1311 u32 op_gen_command = 0;
1312
1313 u32 comp_addr = BAR_CSTRORM_INTMEM +
1314 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1315 int ret = 0;
1316
1317 if (REG_RD(bp, comp_addr)) {
1318 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1319 return 1;
1320 }
1321
1322 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1323 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1324 op_gen_command |= OP_GEN_AGG_VECT(clnup_func);
1325 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1326
1327 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1328 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen_command);
1329
1330 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1331 BNX2X_ERR("FW final cleanup did not succeed\n");
1332 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1333 (REG_RD(bp, comp_addr)));
1334 bnx2x_panic();
1335 return 1;
1336 }
1337 /* Zero completion for nxt FLR */
1338 REG_WR(bp, comp_addr, 0);
1339
1340 return ret;
1341 }
1342
1343 u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1344 {
1345 u16 status;
1346
1347 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
1348 return status & PCI_EXP_DEVSTA_TRPND;
1349 }
1350
1351 /* PF FLR specific routines
1352 */
1353 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1354 {
1355
1356 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1357 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1358 CFC_REG_NUM_LCIDS_INSIDE_PF,
1359 "CFC PF usage counter timed out",
1360 poll_cnt))
1361 return 1;
1362
1363
1364 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1365 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1366 DORQ_REG_PF_USAGE_CNT,
1367 "DQ PF usage counter timed out",
1368 poll_cnt))
1369 return 1;
1370
1371 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1372 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1373 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1374 "QM PF usage counter timed out",
1375 poll_cnt))
1376 return 1;
1377
1378 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1379 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1380 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1381 "Timers VNIC usage counter timed out",
1382 poll_cnt))
1383 return 1;
1384 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1385 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1386 "Timers NUM_SCANS usage counter timed out",
1387 poll_cnt))
1388 return 1;
1389
1390 /* Wait DMAE PF usage counter to zero */
1391 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1392 dmae_reg_go_c[INIT_DMAE_C(bp)],
1393 "DMAE dommand register timed out",
1394 poll_cnt))
1395 return 1;
1396
1397 return 0;
1398 }
1399
1400 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1401 {
1402 u32 val;
1403
1404 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1405 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1406
1407 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1408 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1409
1410 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1411 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1412
1413 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1414 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1415
1416 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1417 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1418
1419 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1420 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1421
1422 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1423 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1424
1425 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1426 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1427 val);
1428 }
1429
1430 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1431 {
1432 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1433
1434 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1435
1436 /* Re-enable PF target read access */
1437 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1438
1439 /* Poll HW usage counters */
1440 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1441 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1442 return -EBUSY;
1443
1444 /* Zero the igu 'trailing edge' and 'leading edge' */
1445
1446 /* Send the FW cleanup command */
1447 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1448 return -EBUSY;
1449
1450 /* ATC cleanup */
1451
1452 /* Verify TX hw is flushed */
1453 bnx2x_tx_hw_flushed(bp, poll_cnt);
1454
1455 /* Wait 100ms (not adjusted according to platform) */
1456 msleep(100);
1457
1458 /* Verify no pending pci transactions */
1459 if (bnx2x_is_pcie_pending(bp->pdev))
1460 BNX2X_ERR("PCIE Transactions still pending\n");
1461
1462 /* Debug */
1463 bnx2x_hw_enable_status(bp);
1464
1465 /*
1466 * Master enable - Due to WB DMAE writes performed before this
1467 * register is re-initialized as part of the regular function init
1468 */
1469 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1470
1471 return 0;
1472 }
1473
1474 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1475 {
1476 int port = BP_PORT(bp);
1477 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1478 u32 val = REG_RD(bp, addr);
1479 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1480 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1481 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1482
1483 if (msix) {
1484 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1485 HC_CONFIG_0_REG_INT_LINE_EN_0);
1486 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1487 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1488 if (single_msix)
1489 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1490 } else if (msi) {
1491 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1492 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1493 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1494 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1495 } else {
1496 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1497 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1498 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1499 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1500
1501 if (!CHIP_IS_E1(bp)) {
1502 DP(NETIF_MSG_IFUP,
1503 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1504
1505 REG_WR(bp, addr, val);
1506
1507 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1508 }
1509 }
1510
1511 if (CHIP_IS_E1(bp))
1512 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1513
1514 DP(NETIF_MSG_IFUP,
1515 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1516 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1517
1518 REG_WR(bp, addr, val);
1519 /*
1520 * Ensure that HC_CONFIG is written before leading/trailing edge config
1521 */
1522 mmiowb();
1523 barrier();
1524
1525 if (!CHIP_IS_E1(bp)) {
1526 /* init leading/trailing edge */
1527 if (IS_MF(bp)) {
1528 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1529 if (bp->port.pmf)
1530 /* enable nig and gpio3 attention */
1531 val |= 0x1100;
1532 } else
1533 val = 0xffff;
1534
1535 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1536 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1537 }
1538
1539 /* Make sure that interrupts are indeed enabled from here on */
1540 mmiowb();
1541 }
1542
1543 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1544 {
1545 u32 val;
1546 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1547 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1548 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1549
1550 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1551
1552 if (msix) {
1553 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1554 IGU_PF_CONF_SINGLE_ISR_EN);
1555 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1556 IGU_PF_CONF_ATTN_BIT_EN);
1557
1558 if (single_msix)
1559 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1560 } else if (msi) {
1561 val &= ~IGU_PF_CONF_INT_LINE_EN;
1562 val |= (IGU_PF_CONF_MSI_MSIX_EN |
1563 IGU_PF_CONF_ATTN_BIT_EN |
1564 IGU_PF_CONF_SINGLE_ISR_EN);
1565 } else {
1566 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1567 val |= (IGU_PF_CONF_INT_LINE_EN |
1568 IGU_PF_CONF_ATTN_BIT_EN |
1569 IGU_PF_CONF_SINGLE_ISR_EN);
1570 }
1571
1572 /* Clean previous status - need to configure igu prior to ack*/
1573 if ((!msix) || single_msix) {
1574 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1575 bnx2x_ack_int(bp);
1576 }
1577
1578 val |= IGU_PF_CONF_FUNC_EN;
1579
1580 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1581 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1582
1583 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1584
1585 if (val & IGU_PF_CONF_INT_LINE_EN)
1586 pci_intx(bp->pdev, true);
1587
1588 barrier();
1589
1590 /* init leading/trailing edge */
1591 if (IS_MF(bp)) {
1592 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1593 if (bp->port.pmf)
1594 /* enable nig and gpio3 attention */
1595 val |= 0x1100;
1596 } else
1597 val = 0xffff;
1598
1599 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1600 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1601
1602 /* Make sure that interrupts are indeed enabled from here on */
1603 mmiowb();
1604 }
1605
1606 void bnx2x_int_enable(struct bnx2x *bp)
1607 {
1608 if (bp->common.int_block == INT_BLOCK_HC)
1609 bnx2x_hc_int_enable(bp);
1610 else
1611 bnx2x_igu_int_enable(bp);
1612 }
1613
1614 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1615 {
1616 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1617 int i, offset;
1618
1619 if (disable_hw)
1620 /* prevent the HW from sending interrupts */
1621 bnx2x_int_disable(bp);
1622
1623 /* make sure all ISRs are done */
1624 if (msix) {
1625 synchronize_irq(bp->msix_table[0].vector);
1626 offset = 1;
1627 if (CNIC_SUPPORT(bp))
1628 offset++;
1629 for_each_eth_queue(bp, i)
1630 synchronize_irq(bp->msix_table[offset++].vector);
1631 } else
1632 synchronize_irq(bp->pdev->irq);
1633
1634 /* make sure sp_task is not running */
1635 cancel_delayed_work(&bp->sp_task);
1636 cancel_delayed_work(&bp->period_task);
1637 flush_workqueue(bnx2x_wq);
1638 }
1639
1640 /* fast path */
1641
1642 /*
1643 * General service functions
1644 */
1645
1646 /* Return true if succeeded to acquire the lock */
1647 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1648 {
1649 u32 lock_status;
1650 u32 resource_bit = (1 << resource);
1651 int func = BP_FUNC(bp);
1652 u32 hw_lock_control_reg;
1653
1654 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1655 "Trying to take a lock on resource %d\n", resource);
1656
1657 /* Validating that the resource is within range */
1658 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1659 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1660 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1661 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1662 return false;
1663 }
1664
1665 if (func <= 5)
1666 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1667 else
1668 hw_lock_control_reg =
1669 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1670
1671 /* Try to acquire the lock */
1672 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1673 lock_status = REG_RD(bp, hw_lock_control_reg);
1674 if (lock_status & resource_bit)
1675 return true;
1676
1677 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1678 "Failed to get a lock on resource %d\n", resource);
1679 return false;
1680 }
1681
1682 /**
1683 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1684 *
1685 * @bp: driver handle
1686 *
1687 * Returns the recovery leader resource id according to the engine this function
1688 * belongs to. Currently only only 2 engines is supported.
1689 */
1690 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1691 {
1692 if (BP_PATH(bp))
1693 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1694 else
1695 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1696 }
1697
1698 /**
1699 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1700 *
1701 * @bp: driver handle
1702 *
1703 * Tries to acquire a leader lock for current engine.
1704 */
1705 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1706 {
1707 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1708 }
1709
1710 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1711
1712 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1713 static int bnx2x_schedule_sp_task(struct bnx2x *bp)
1714 {
1715 /* Set the interrupt occurred bit for the sp-task to recognize it
1716 * must ack the interrupt and transition according to the IGU
1717 * state machine.
1718 */
1719 atomic_set(&bp->interrupt_occurred, 1);
1720
1721 /* The sp_task must execute only after this bit
1722 * is set, otherwise we will get out of sync and miss all
1723 * further interrupts. Hence, the barrier.
1724 */
1725 smp_wmb();
1726
1727 /* schedule sp_task to workqueue */
1728 return queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1729 }
1730
1731 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1732 {
1733 struct bnx2x *bp = fp->bp;
1734 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1735 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1736 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1737 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1738
1739 DP(BNX2X_MSG_SP,
1740 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1741 fp->index, cid, command, bp->state,
1742 rr_cqe->ramrod_cqe.ramrod_type);
1743
1744 /* If cid is within VF range, replace the slowpath object with the
1745 * one corresponding to this VF
1746 */
1747 if (cid >= BNX2X_FIRST_VF_CID &&
1748 cid < BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)
1749 bnx2x_iov_set_queue_sp_obj(bp, cid, &q_obj);
1750
1751 switch (command) {
1752 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1753 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1754 drv_cmd = BNX2X_Q_CMD_UPDATE;
1755 break;
1756
1757 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1758 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1759 drv_cmd = BNX2X_Q_CMD_SETUP;
1760 break;
1761
1762 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1763 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1764 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1765 break;
1766
1767 case (RAMROD_CMD_ID_ETH_HALT):
1768 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1769 drv_cmd = BNX2X_Q_CMD_HALT;
1770 break;
1771
1772 case (RAMROD_CMD_ID_ETH_TERMINATE):
1773 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1774 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1775 break;
1776
1777 case (RAMROD_CMD_ID_ETH_EMPTY):
1778 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1779 drv_cmd = BNX2X_Q_CMD_EMPTY;
1780 break;
1781
1782 default:
1783 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1784 command, fp->index);
1785 return;
1786 }
1787
1788 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1789 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1790 /* q_obj->complete_cmd() failure means that this was
1791 * an unexpected completion.
1792 *
1793 * In this case we don't want to increase the bp->spq_left
1794 * because apparently we haven't sent this command the first
1795 * place.
1796 */
1797 #ifdef BNX2X_STOP_ON_ERROR
1798 bnx2x_panic();
1799 #else
1800 return;
1801 #endif
1802 /* SRIOV: reschedule any 'in_progress' operations */
1803 bnx2x_iov_sp_event(bp, cid, true);
1804
1805 smp_mb__before_atomic_inc();
1806 atomic_inc(&bp->cq_spq_left);
1807 /* push the change in bp->spq_left and towards the memory */
1808 smp_mb__after_atomic_inc();
1809
1810 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1811
1812 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1813 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1814 /* if Q update ramrod is completed for last Q in AFEX vif set
1815 * flow, then ACK MCP at the end
1816 *
1817 * mark pending ACK to MCP bit.
1818 * prevent case that both bits are cleared.
1819 * At the end of load/unload driver checks that
1820 * sp_state is cleared, and this order prevents
1821 * races
1822 */
1823 smp_mb__before_clear_bit();
1824 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1825 wmb();
1826 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1827 smp_mb__after_clear_bit();
1828
1829 /* schedule the sp task as mcp ack is required */
1830 bnx2x_schedule_sp_task(bp);
1831 }
1832
1833 return;
1834 }
1835
1836 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1837 {
1838 struct bnx2x *bp = netdev_priv(dev_instance);
1839 u16 status = bnx2x_ack_int(bp);
1840 u16 mask;
1841 int i;
1842 u8 cos;
1843
1844 /* Return here if interrupt is shared and it's not for us */
1845 if (unlikely(status == 0)) {
1846 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1847 return IRQ_NONE;
1848 }
1849 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1850
1851 #ifdef BNX2X_STOP_ON_ERROR
1852 if (unlikely(bp->panic))
1853 return IRQ_HANDLED;
1854 #endif
1855
1856 for_each_eth_queue(bp, i) {
1857 struct bnx2x_fastpath *fp = &bp->fp[i];
1858
1859 mask = 0x2 << (fp->index + CNIC_SUPPORT(bp));
1860 if (status & mask) {
1861 /* Handle Rx or Tx according to SB id */
1862 prefetch(fp->rx_cons_sb);
1863 for_each_cos_in_tx_queue(fp, cos)
1864 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1865 prefetch(&fp->sb_running_index[SM_RX_ID]);
1866 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1867 status &= ~mask;
1868 }
1869 }
1870
1871 if (CNIC_SUPPORT(bp)) {
1872 mask = 0x2;
1873 if (status & (mask | 0x1)) {
1874 struct cnic_ops *c_ops = NULL;
1875
1876 rcu_read_lock();
1877 c_ops = rcu_dereference(bp->cnic_ops);
1878 if (c_ops && (bp->cnic_eth_dev.drv_state &
1879 CNIC_DRV_STATE_HANDLES_IRQ))
1880 c_ops->cnic_handler(bp->cnic_data, NULL);
1881 rcu_read_unlock();
1882
1883 status &= ~mask;
1884 }
1885 }
1886
1887 if (unlikely(status & 0x1)) {
1888
1889 /* schedule sp task to perform default status block work, ack
1890 * attentions and enable interrupts.
1891 */
1892 bnx2x_schedule_sp_task(bp);
1893
1894 status &= ~0x1;
1895 if (!status)
1896 return IRQ_HANDLED;
1897 }
1898
1899 if (unlikely(status))
1900 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1901 status);
1902
1903 return IRQ_HANDLED;
1904 }
1905
1906 /* Link */
1907
1908 /*
1909 * General service functions
1910 */
1911
1912 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1913 {
1914 u32 lock_status;
1915 u32 resource_bit = (1 << resource);
1916 int func = BP_FUNC(bp);
1917 u32 hw_lock_control_reg;
1918 int cnt;
1919
1920 /* Validating that the resource is within range */
1921 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1922 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1923 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1924 return -EINVAL;
1925 }
1926
1927 if (func <= 5) {
1928 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1929 } else {
1930 hw_lock_control_reg =
1931 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1932 }
1933
1934 /* Validating that the resource is not already taken */
1935 lock_status = REG_RD(bp, hw_lock_control_reg);
1936 if (lock_status & resource_bit) {
1937 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1938 lock_status, resource_bit);
1939 return -EEXIST;
1940 }
1941
1942 /* Try for 5 second every 5ms */
1943 for (cnt = 0; cnt < 1000; cnt++) {
1944 /* Try to acquire the lock */
1945 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1946 lock_status = REG_RD(bp, hw_lock_control_reg);
1947 if (lock_status & resource_bit)
1948 return 0;
1949
1950 msleep(5);
1951 }
1952 BNX2X_ERR("Timeout\n");
1953 return -EAGAIN;
1954 }
1955
1956 int bnx2x_release_leader_lock(struct bnx2x *bp)
1957 {
1958 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1959 }
1960
1961 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1962 {
1963 u32 lock_status;
1964 u32 resource_bit = (1 << resource);
1965 int func = BP_FUNC(bp);
1966 u32 hw_lock_control_reg;
1967
1968 /* Validating that the resource is within range */
1969 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1970 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1971 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1972 return -EINVAL;
1973 }
1974
1975 if (func <= 5) {
1976 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1977 } else {
1978 hw_lock_control_reg =
1979 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1980 }
1981
1982 /* Validating that the resource is currently taken */
1983 lock_status = REG_RD(bp, hw_lock_control_reg);
1984 if (!(lock_status & resource_bit)) {
1985 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1986 lock_status, resource_bit);
1987 return -EFAULT;
1988 }
1989
1990 REG_WR(bp, hw_lock_control_reg, resource_bit);
1991 return 0;
1992 }
1993
1994
1995 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1996 {
1997 /* The GPIO should be swapped if swap register is set and active */
1998 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1999 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2000 int gpio_shift = gpio_num +
2001 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2002 u32 gpio_mask = (1 << gpio_shift);
2003 u32 gpio_reg;
2004 int value;
2005
2006 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2007 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2008 return -EINVAL;
2009 }
2010
2011 /* read GPIO value */
2012 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2013
2014 /* get the requested pin value */
2015 if ((gpio_reg & gpio_mask) == gpio_mask)
2016 value = 1;
2017 else
2018 value = 0;
2019
2020 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
2021
2022 return value;
2023 }
2024
2025 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2026 {
2027 /* The GPIO should be swapped if swap register is set and active */
2028 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2029 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2030 int gpio_shift = gpio_num +
2031 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2032 u32 gpio_mask = (1 << gpio_shift);
2033 u32 gpio_reg;
2034
2035 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2036 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2037 return -EINVAL;
2038 }
2039
2040 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2041 /* read GPIO and mask except the float bits */
2042 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
2043
2044 switch (mode) {
2045 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2046 DP(NETIF_MSG_LINK,
2047 "Set GPIO %d (shift %d) -> output low\n",
2048 gpio_num, gpio_shift);
2049 /* clear FLOAT and set CLR */
2050 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2051 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
2052 break;
2053
2054 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2055 DP(NETIF_MSG_LINK,
2056 "Set GPIO %d (shift %d) -> output high\n",
2057 gpio_num, gpio_shift);
2058 /* clear FLOAT and set SET */
2059 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2060 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
2061 break;
2062
2063 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2064 DP(NETIF_MSG_LINK,
2065 "Set GPIO %d (shift %d) -> input\n",
2066 gpio_num, gpio_shift);
2067 /* set FLOAT */
2068 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
2069 break;
2070
2071 default:
2072 break;
2073 }
2074
2075 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2076 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2077
2078 return 0;
2079 }
2080
2081 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
2082 {
2083 u32 gpio_reg = 0;
2084 int rc = 0;
2085
2086 /* Any port swapping should be handled by caller. */
2087
2088 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2089 /* read GPIO and mask except the float bits */
2090 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
2091 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2092 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
2093 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
2094
2095 switch (mode) {
2096 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
2097 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
2098 /* set CLR */
2099 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
2100 break;
2101
2102 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
2103 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
2104 /* set SET */
2105 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
2106 break;
2107
2108 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
2109 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
2110 /* set FLOAT */
2111 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
2112 break;
2113
2114 default:
2115 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
2116 rc = -EINVAL;
2117 break;
2118 }
2119
2120 if (rc == 0)
2121 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
2122
2123 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2124
2125 return rc;
2126 }
2127
2128 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
2129 {
2130 /* The GPIO should be swapped if swap register is set and active */
2131 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
2132 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
2133 int gpio_shift = gpio_num +
2134 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2135 u32 gpio_mask = (1 << gpio_shift);
2136 u32 gpio_reg;
2137
2138 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2139 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2140 return -EINVAL;
2141 }
2142
2143 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2144 /* read GPIO int */
2145 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2146
2147 switch (mode) {
2148 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2149 DP(NETIF_MSG_LINK,
2150 "Clear GPIO INT %d (shift %d) -> output low\n",
2151 gpio_num, gpio_shift);
2152 /* clear SET and set CLR */
2153 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2154 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2155 break;
2156
2157 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2158 DP(NETIF_MSG_LINK,
2159 "Set GPIO INT %d (shift %d) -> output high\n",
2160 gpio_num, gpio_shift);
2161 /* clear CLR and set SET */
2162 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2163 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2164 break;
2165
2166 default:
2167 break;
2168 }
2169
2170 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2171 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2172
2173 return 0;
2174 }
2175
2176 static int bnx2x_set_spio(struct bnx2x *bp, int spio, u32 mode)
2177 {
2178 u32 spio_reg;
2179
2180 /* Only 2 SPIOs are configurable */
2181 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) {
2182 BNX2X_ERR("Invalid SPIO 0x%x\n", spio);
2183 return -EINVAL;
2184 }
2185
2186 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2187 /* read SPIO and mask except the float bits */
2188 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_SPIO_FLOAT);
2189
2190 switch (mode) {
2191 case MISC_SPIO_OUTPUT_LOW:
2192 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output low\n", spio);
2193 /* clear FLOAT and set CLR */
2194 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2195 spio_reg |= (spio << MISC_SPIO_CLR_POS);
2196 break;
2197
2198 case MISC_SPIO_OUTPUT_HIGH:
2199 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> output high\n", spio);
2200 /* clear FLOAT and set SET */
2201 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS);
2202 spio_reg |= (spio << MISC_SPIO_SET_POS);
2203 break;
2204
2205 case MISC_SPIO_INPUT_HI_Z:
2206 DP(NETIF_MSG_HW, "Set SPIO 0x%x -> input\n", spio);
2207 /* set FLOAT */
2208 spio_reg |= (spio << MISC_SPIO_FLOAT_POS);
2209 break;
2210
2211 default:
2212 break;
2213 }
2214
2215 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2216 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2217
2218 return 0;
2219 }
2220
2221 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2222 {
2223 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2224 switch (bp->link_vars.ieee_fc &
2225 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2226 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2227 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2228 ADVERTISED_Pause);
2229 break;
2230
2231 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2232 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2233 ADVERTISED_Pause);
2234 break;
2235
2236 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2237 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2238 break;
2239
2240 default:
2241 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2242 ADVERTISED_Pause);
2243 break;
2244 }
2245 }
2246
2247 static void bnx2x_set_requested_fc(struct bnx2x *bp)
2248 {
2249 /* Initialize link parameters structure variables
2250 * It is recommended to turn off RX FC for jumbo frames
2251 * for better performance
2252 */
2253 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2254 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2255 else
2256 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2257 }
2258
2259 int bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2260 {
2261 int rc, cfx_idx = bnx2x_get_link_cfg_idx(bp);
2262 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2263
2264 if (!BP_NOMCP(bp)) {
2265 bnx2x_set_requested_fc(bp);
2266 bnx2x_acquire_phy_lock(bp);
2267
2268 if (load_mode == LOAD_DIAG) {
2269 struct link_params *lp = &bp->link_params;
2270 lp->loopback_mode = LOOPBACK_XGXS;
2271 /* do PHY loopback at 10G speed, if possible */
2272 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2273 if (lp->speed_cap_mask[cfx_idx] &
2274 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2275 lp->req_line_speed[cfx_idx] =
2276 SPEED_10000;
2277 else
2278 lp->req_line_speed[cfx_idx] =
2279 SPEED_1000;
2280 }
2281 }
2282
2283 if (load_mode == LOAD_LOOPBACK_EXT) {
2284 struct link_params *lp = &bp->link_params;
2285 lp->loopback_mode = LOOPBACK_EXT;
2286 }
2287
2288 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2289
2290 bnx2x_release_phy_lock(bp);
2291
2292 bnx2x_calc_fc_adv(bp);
2293
2294 if (bp->link_vars.link_up) {
2295 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2296 bnx2x_link_report(bp);
2297 }
2298 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2299 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2300 return rc;
2301 }
2302 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2303 return -EINVAL;
2304 }
2305
2306 void bnx2x_link_set(struct bnx2x *bp)
2307 {
2308 if (!BP_NOMCP(bp)) {
2309 bnx2x_acquire_phy_lock(bp);
2310 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2311 bnx2x_release_phy_lock(bp);
2312
2313 bnx2x_calc_fc_adv(bp);
2314 } else
2315 BNX2X_ERR("Bootcode is missing - can not set link\n");
2316 }
2317
2318 static void bnx2x__link_reset(struct bnx2x *bp)
2319 {
2320 if (!BP_NOMCP(bp)) {
2321 bnx2x_acquire_phy_lock(bp);
2322 bnx2x_lfa_reset(&bp->link_params, &bp->link_vars);
2323 bnx2x_release_phy_lock(bp);
2324 } else
2325 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2326 }
2327
2328 void bnx2x_force_link_reset(struct bnx2x *bp)
2329 {
2330 bnx2x_acquire_phy_lock(bp);
2331 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2332 bnx2x_release_phy_lock(bp);
2333 }
2334
2335 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2336 {
2337 u8 rc = 0;
2338
2339 if (!BP_NOMCP(bp)) {
2340 bnx2x_acquire_phy_lock(bp);
2341 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2342 is_serdes);
2343 bnx2x_release_phy_lock(bp);
2344 } else
2345 BNX2X_ERR("Bootcode is missing - can not test link\n");
2346
2347 return rc;
2348 }
2349
2350
2351 /* Calculates the sum of vn_min_rates.
2352 It's needed for further normalizing of the min_rates.
2353 Returns:
2354 sum of vn_min_rates.
2355 or
2356 0 - if all the min_rates are 0.
2357 In the later case fainess algorithm should be deactivated.
2358 If not all min_rates are zero then those that are zeroes will be set to 1.
2359 */
2360 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2361 struct cmng_init_input *input)
2362 {
2363 int all_zero = 1;
2364 int vn;
2365
2366 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2367 u32 vn_cfg = bp->mf_config[vn];
2368 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2369 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2370
2371 /* Skip hidden vns */
2372 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2373 vn_min_rate = 0;
2374 /* If min rate is zero - set it to 1 */
2375 else if (!vn_min_rate)
2376 vn_min_rate = DEF_MIN_RATE;
2377 else
2378 all_zero = 0;
2379
2380 input->vnic_min_rate[vn] = vn_min_rate;
2381 }
2382
2383 /* if ETS or all min rates are zeros - disable fairness */
2384 if (BNX2X_IS_ETS_ENABLED(bp)) {
2385 input->flags.cmng_enables &=
2386 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2387 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2388 } else if (all_zero) {
2389 input->flags.cmng_enables &=
2390 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2391 DP(NETIF_MSG_IFUP,
2392 "All MIN values are zeroes fairness will be disabled\n");
2393 } else
2394 input->flags.cmng_enables |=
2395 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2396 }
2397
2398 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2399 struct cmng_init_input *input)
2400 {
2401 u16 vn_max_rate;
2402 u32 vn_cfg = bp->mf_config[vn];
2403
2404 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2405 vn_max_rate = 0;
2406 else {
2407 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2408
2409 if (IS_MF_SI(bp)) {
2410 /* maxCfg in percents of linkspeed */
2411 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2412 } else /* SD modes */
2413 /* maxCfg is absolute in 100Mb units */
2414 vn_max_rate = maxCfg * 100;
2415 }
2416
2417 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2418
2419 input->vnic_max_rate[vn] = vn_max_rate;
2420 }
2421
2422
2423 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2424 {
2425 if (CHIP_REV_IS_SLOW(bp))
2426 return CMNG_FNS_NONE;
2427 if (IS_MF(bp))
2428 return CMNG_FNS_MINMAX;
2429
2430 return CMNG_FNS_NONE;
2431 }
2432
2433 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2434 {
2435 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2436
2437 if (BP_NOMCP(bp))
2438 return; /* what should be the default bvalue in this case */
2439
2440 /* For 2 port configuration the absolute function number formula
2441 * is:
2442 * abs_func = 2 * vn + BP_PORT + BP_PATH
2443 *
2444 * and there are 4 functions per port
2445 *
2446 * For 4 port configuration it is
2447 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2448 *
2449 * and there are 2 functions per port
2450 */
2451 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2452 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2453
2454 if (func >= E1H_FUNC_MAX)
2455 break;
2456
2457 bp->mf_config[vn] =
2458 MF_CFG_RD(bp, func_mf_config[func].config);
2459 }
2460 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2461 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2462 bp->flags |= MF_FUNC_DIS;
2463 } else {
2464 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2465 bp->flags &= ~MF_FUNC_DIS;
2466 }
2467 }
2468
2469 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2470 {
2471 struct cmng_init_input input;
2472 memset(&input, 0, sizeof(struct cmng_init_input));
2473
2474 input.port_rate = bp->link_vars.line_speed;
2475
2476 if (cmng_type == CMNG_FNS_MINMAX) {
2477 int vn;
2478
2479 /* read mf conf from shmem */
2480 if (read_cfg)
2481 bnx2x_read_mf_cfg(bp);
2482
2483 /* vn_weight_sum and enable fairness if not 0 */
2484 bnx2x_calc_vn_min(bp, &input);
2485
2486 /* calculate and set min-max rate for each vn */
2487 if (bp->port.pmf)
2488 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2489 bnx2x_calc_vn_max(bp, vn, &input);
2490
2491 /* always enable rate shaping and fairness */
2492 input.flags.cmng_enables |=
2493 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2494
2495 bnx2x_init_cmng(&input, &bp->cmng);
2496 return;
2497 }
2498
2499 /* rate shaping and fairness are disabled */
2500 DP(NETIF_MSG_IFUP,
2501 "rate shaping and fairness are disabled\n");
2502 }
2503
2504 static void storm_memset_cmng(struct bnx2x *bp,
2505 struct cmng_init *cmng,
2506 u8 port)
2507 {
2508 int vn;
2509 size_t size = sizeof(struct cmng_struct_per_port);
2510
2511 u32 addr = BAR_XSTRORM_INTMEM +
2512 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2513
2514 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2515
2516 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2517 int func = func_by_vn(bp, vn);
2518
2519 addr = BAR_XSTRORM_INTMEM +
2520 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2521 size = sizeof(struct rate_shaping_vars_per_vn);
2522 __storm_memset_struct(bp, addr, size,
2523 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2524
2525 addr = BAR_XSTRORM_INTMEM +
2526 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2527 size = sizeof(struct fairness_vars_per_vn);
2528 __storm_memset_struct(bp, addr, size,
2529 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2530 }
2531 }
2532
2533 /* This function is called upon link interrupt */
2534 static void bnx2x_link_attn(struct bnx2x *bp)
2535 {
2536 /* Make sure that we are synced with the current statistics */
2537 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2538
2539 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2540
2541 if (bp->link_vars.link_up) {
2542
2543 /* dropless flow control */
2544 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2545 int port = BP_PORT(bp);
2546 u32 pause_enabled = 0;
2547
2548 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2549 pause_enabled = 1;
2550
2551 REG_WR(bp, BAR_USTRORM_INTMEM +
2552 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2553 pause_enabled);
2554 }
2555
2556 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2557 struct host_port_stats *pstats;
2558
2559 pstats = bnx2x_sp(bp, port_stats);
2560 /* reset old mac stats */
2561 memset(&(pstats->mac_stx[0]), 0,
2562 sizeof(struct mac_stx));
2563 }
2564 if (bp->state == BNX2X_STATE_OPEN)
2565 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2566 }
2567
2568 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2569 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2570
2571 if (cmng_fns != CMNG_FNS_NONE) {
2572 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2573 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2574 } else
2575 /* rate shaping and fairness are disabled */
2576 DP(NETIF_MSG_IFUP,
2577 "single function mode without fairness\n");
2578 }
2579
2580 __bnx2x_link_report(bp);
2581
2582 if (IS_MF(bp))
2583 bnx2x_link_sync_notify(bp);
2584 }
2585
2586 void bnx2x__link_status_update(struct bnx2x *bp)
2587 {
2588 if (bp->state != BNX2X_STATE_OPEN)
2589 return;
2590
2591 /* read updated dcb configuration */
2592 if (IS_PF(bp)) {
2593 bnx2x_dcbx_pmf_update(bp);
2594 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2595 if (bp->link_vars.link_up)
2596 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2597 else
2598 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2599 /* indicate link status */
2600 bnx2x_link_report(bp);
2601
2602 } else { /* VF */
2603 bp->port.supported[0] |= (SUPPORTED_10baseT_Half |
2604 SUPPORTED_10baseT_Full |
2605 SUPPORTED_100baseT_Half |
2606 SUPPORTED_100baseT_Full |
2607 SUPPORTED_1000baseT_Full |
2608 SUPPORTED_2500baseX_Full |
2609 SUPPORTED_10000baseT_Full |
2610 SUPPORTED_TP |
2611 SUPPORTED_FIBRE |
2612 SUPPORTED_Autoneg |
2613 SUPPORTED_Pause |
2614 SUPPORTED_Asym_Pause);
2615 bp->port.advertising[0] = bp->port.supported[0];
2616
2617 bp->link_params.bp = bp;
2618 bp->link_params.port = BP_PORT(bp);
2619 bp->link_params.req_duplex[0] = DUPLEX_FULL;
2620 bp->link_params.req_flow_ctrl[0] = BNX2X_FLOW_CTRL_NONE;
2621 bp->link_params.req_line_speed[0] = SPEED_10000;
2622 bp->link_params.speed_cap_mask[0] = 0x7f0000;
2623 bp->link_params.switch_cfg = SWITCH_CFG_10G;
2624 bp->link_vars.mac_type = MAC_TYPE_BMAC;
2625 bp->link_vars.line_speed = SPEED_10000;
2626 bp->link_vars.link_status =
2627 (LINK_STATUS_LINK_UP |
2628 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD);
2629 bp->link_vars.link_up = 1;
2630 bp->link_vars.duplex = DUPLEX_FULL;
2631 bp->link_vars.flow_ctrl = BNX2X_FLOW_CTRL_NONE;
2632 __bnx2x_link_report(bp);
2633 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2634 }
2635 }
2636
2637 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2638 u16 vlan_val, u8 allowed_prio)
2639 {
2640 struct bnx2x_func_state_params func_params = {NULL};
2641 struct bnx2x_func_afex_update_params *f_update_params =
2642 &func_params.params.afex_update;
2643
2644 func_params.f_obj = &bp->func_obj;
2645 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2646
2647 /* no need to wait for RAMROD completion, so don't
2648 * set RAMROD_COMP_WAIT flag
2649 */
2650
2651 f_update_params->vif_id = vifid;
2652 f_update_params->afex_default_vlan = vlan_val;
2653 f_update_params->allowed_priorities = allowed_prio;
2654
2655 /* if ramrod can not be sent, response to MCP immediately */
2656 if (bnx2x_func_state_change(bp, &func_params) < 0)
2657 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2658
2659 return 0;
2660 }
2661
2662 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2663 u16 vif_index, u8 func_bit_map)
2664 {
2665 struct bnx2x_func_state_params func_params = {NULL};
2666 struct bnx2x_func_afex_viflists_params *update_params =
2667 &func_params.params.afex_viflists;
2668 int rc;
2669 u32 drv_msg_code;
2670
2671 /* validate only LIST_SET and LIST_GET are received from switch */
2672 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2673 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2674 cmd_type);
2675
2676 func_params.f_obj = &bp->func_obj;
2677 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2678
2679 /* set parameters according to cmd_type */
2680 update_params->afex_vif_list_command = cmd_type;
2681 update_params->vif_list_index = vif_index;
2682 update_params->func_bit_map =
2683 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2684 update_params->func_to_clear = 0;
2685 drv_msg_code =
2686 (cmd_type == VIF_LIST_RULE_GET) ?
2687 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2688 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2689
2690 /* if ramrod can not be sent, respond to MCP immediately for
2691 * SET and GET requests (other are not triggered from MCP)
2692 */
2693 rc = bnx2x_func_state_change(bp, &func_params);
2694 if (rc < 0)
2695 bnx2x_fw_command(bp, drv_msg_code, 0);
2696
2697 return 0;
2698 }
2699
2700 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2701 {
2702 struct afex_stats afex_stats;
2703 u32 func = BP_ABS_FUNC(bp);
2704 u32 mf_config;
2705 u16 vlan_val;
2706 u32 vlan_prio;
2707 u16 vif_id;
2708 u8 allowed_prio;
2709 u8 vlan_mode;
2710 u32 addr_to_write, vifid, addrs, stats_type, i;
2711
2712 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2713 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2714 DP(BNX2X_MSG_MCP,
2715 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2716 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2717 }
2718
2719 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2720 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2721 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2722 DP(BNX2X_MSG_MCP,
2723 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2724 vifid, addrs);
2725 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2726 addrs);
2727 }
2728
2729 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2730 addr_to_write = SHMEM2_RD(bp,
2731 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2732 stats_type = SHMEM2_RD(bp,
2733 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2734
2735 DP(BNX2X_MSG_MCP,
2736 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2737 addr_to_write);
2738
2739 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2740
2741 /* write response to scratchpad, for MCP */
2742 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2743 REG_WR(bp, addr_to_write + i*sizeof(u32),
2744 *(((u32 *)(&afex_stats))+i));
2745
2746 /* send ack message to MCP */
2747 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2748 }
2749
2750 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2751 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2752 bp->mf_config[BP_VN(bp)] = mf_config;
2753 DP(BNX2X_MSG_MCP,
2754 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2755 mf_config);
2756
2757 /* if VIF_SET is "enabled" */
2758 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2759 /* set rate limit directly to internal RAM */
2760 struct cmng_init_input cmng_input;
2761 struct rate_shaping_vars_per_vn m_rs_vn;
2762 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2763 u32 addr = BAR_XSTRORM_INTMEM +
2764 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2765
2766 bp->mf_config[BP_VN(bp)] = mf_config;
2767
2768 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2769 m_rs_vn.vn_counter.rate =
2770 cmng_input.vnic_max_rate[BP_VN(bp)];
2771 m_rs_vn.vn_counter.quota =
2772 (m_rs_vn.vn_counter.rate *
2773 RS_PERIODIC_TIMEOUT_USEC) / 8;
2774
2775 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2776
2777 /* read relevant values from mf_cfg struct in shmem */
2778 vif_id =
2779 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2780 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2781 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2782 vlan_val =
2783 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2784 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2785 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2786 vlan_prio = (mf_config &
2787 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2788 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2789 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2790 vlan_mode =
2791 (MF_CFG_RD(bp,
2792 func_mf_config[func].afex_config) &
2793 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2794 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2795 allowed_prio =
2796 (MF_CFG_RD(bp,
2797 func_mf_config[func].afex_config) &
2798 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2799 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2800
2801 /* send ramrod to FW, return in case of failure */
2802 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2803 allowed_prio))
2804 return;
2805
2806 bp->afex_def_vlan_tag = vlan_val;
2807 bp->afex_vlan_mode = vlan_mode;
2808 } else {
2809 /* notify link down because BP->flags is disabled */
2810 bnx2x_link_report(bp);
2811
2812 /* send INVALID VIF ramrod to FW */
2813 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2814
2815 /* Reset the default afex VLAN */
2816 bp->afex_def_vlan_tag = -1;
2817 }
2818 }
2819 }
2820
2821 static void bnx2x_pmf_update(struct bnx2x *bp)
2822 {
2823 int port = BP_PORT(bp);
2824 u32 val;
2825
2826 bp->port.pmf = 1;
2827 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2828
2829 /*
2830 * We need the mb() to ensure the ordering between the writing to
2831 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2832 */
2833 smp_mb();
2834
2835 /* queue a periodic task */
2836 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2837
2838 bnx2x_dcbx_pmf_update(bp);
2839
2840 /* enable nig attention */
2841 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2842 if (bp->common.int_block == INT_BLOCK_HC) {
2843 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2844 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2845 } else if (!CHIP_IS_E1x(bp)) {
2846 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2847 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2848 }
2849
2850 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2851 }
2852
2853 /* end of Link */
2854
2855 /* slow path */
2856
2857 /*
2858 * General service functions
2859 */
2860
2861 /* send the MCP a request, block until there is a reply */
2862 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2863 {
2864 int mb_idx = BP_FW_MB_IDX(bp);
2865 u32 seq;
2866 u32 rc = 0;
2867 u32 cnt = 1;
2868 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2869
2870 mutex_lock(&bp->fw_mb_mutex);
2871 seq = ++bp->fw_seq;
2872 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2873 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2874
2875 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2876 (command | seq), param);
2877
2878 do {
2879 /* let the FW do it's magic ... */
2880 msleep(delay);
2881
2882 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2883
2884 /* Give the FW up to 5 second (500*10ms) */
2885 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2886
2887 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2888 cnt*delay, rc, seq);
2889
2890 /* is this a reply to our command? */
2891 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2892 rc &= FW_MSG_CODE_MASK;
2893 else {
2894 /* FW BUG! */
2895 BNX2X_ERR("FW failed to respond!\n");
2896 bnx2x_fw_dump(bp);
2897 rc = 0;
2898 }
2899 mutex_unlock(&bp->fw_mb_mutex);
2900
2901 return rc;
2902 }
2903
2904
2905 static void storm_memset_func_cfg(struct bnx2x *bp,
2906 struct tstorm_eth_function_common_config *tcfg,
2907 u16 abs_fid)
2908 {
2909 size_t size = sizeof(struct tstorm_eth_function_common_config);
2910
2911 u32 addr = BAR_TSTRORM_INTMEM +
2912 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2913
2914 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2915 }
2916
2917 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2918 {
2919 if (CHIP_IS_E1x(bp)) {
2920 struct tstorm_eth_function_common_config tcfg = {0};
2921
2922 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2923 }
2924
2925 /* Enable the function in the FW */
2926 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2927 storm_memset_func_en(bp, p->func_id, 1);
2928
2929 /* spq */
2930 if (p->func_flgs & FUNC_FLG_SPQ) {
2931 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2932 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2933 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2934 }
2935 }
2936
2937 /**
2938 * bnx2x_get_tx_only_flags - Return common flags
2939 *
2940 * @bp device handle
2941 * @fp queue handle
2942 * @zero_stats TRUE if statistics zeroing is needed
2943 *
2944 * Return the flags that are common for the Tx-only and not normal connections.
2945 */
2946 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2947 struct bnx2x_fastpath *fp,
2948 bool zero_stats)
2949 {
2950 unsigned long flags = 0;
2951
2952 /* PF driver will always initialize the Queue to an ACTIVE state */
2953 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2954
2955 /* tx only connections collect statistics (on the same index as the
2956 * parent connection). The statistics are zeroed when the parent
2957 * connection is initialized.
2958 */
2959
2960 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2961 if (zero_stats)
2962 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2963
2964 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, &flags);
2965 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, &flags);
2966
2967 #ifdef BNX2X_STOP_ON_ERROR
2968 __set_bit(BNX2X_Q_FLG_TX_SEC, &flags);
2969 #endif
2970
2971 return flags;
2972 }
2973
2974 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2975 struct bnx2x_fastpath *fp,
2976 bool leading)
2977 {
2978 unsigned long flags = 0;
2979
2980 /* calculate other queue flags */
2981 if (IS_MF_SD(bp))
2982 __set_bit(BNX2X_Q_FLG_OV, &flags);
2983
2984 if (IS_FCOE_FP(fp)) {
2985 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2986 /* For FCoE - force usage of default priority (for afex) */
2987 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2988 }
2989
2990 if (!fp->disable_tpa) {
2991 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2992 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2993 if (fp->mode == TPA_MODE_GRO)
2994 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2995 }
2996
2997 if (leading) {
2998 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2999 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
3000 }
3001
3002 /* Always set HW VLAN stripping */
3003 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
3004
3005 /* configure silent vlan removal */
3006 if (IS_MF_AFEX(bp))
3007 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
3008
3009
3010 return flags | bnx2x_get_common_flags(bp, fp, true);
3011 }
3012
3013 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
3014 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
3015 u8 cos)
3016 {
3017 gen_init->stat_id = bnx2x_stats_id(fp);
3018 gen_init->spcl_id = fp->cl_id;
3019
3020 /* Always use mini-jumbo MTU for FCoE L2 ring */
3021 if (IS_FCOE_FP(fp))
3022 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
3023 else
3024 gen_init->mtu = bp->dev->mtu;
3025
3026 gen_init->cos = cos;
3027 }
3028
3029 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
3030 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
3031 struct bnx2x_rxq_setup_params *rxq_init)
3032 {
3033 u8 max_sge = 0;
3034 u16 sge_sz = 0;
3035 u16 tpa_agg_size = 0;
3036
3037 if (!fp->disable_tpa) {
3038 pause->sge_th_lo = SGE_TH_LO(bp);
3039 pause->sge_th_hi = SGE_TH_HI(bp);
3040
3041 /* validate SGE ring has enough to cross high threshold */
3042 WARN_ON(bp->dropless_fc &&
3043 pause->sge_th_hi + FW_PREFETCH_CNT >
3044 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
3045
3046 tpa_agg_size = TPA_AGG_SIZE;
3047 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
3048 SGE_PAGE_SHIFT;
3049 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
3050 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
3051 sge_sz = (u16)min_t(u32, SGE_PAGES, 0xffff);
3052 }
3053
3054 /* pause - not for e1 */
3055 if (!CHIP_IS_E1(bp)) {
3056 pause->bd_th_lo = BD_TH_LO(bp);
3057 pause->bd_th_hi = BD_TH_HI(bp);
3058
3059 pause->rcq_th_lo = RCQ_TH_LO(bp);
3060 pause->rcq_th_hi = RCQ_TH_HI(bp);
3061 /*
3062 * validate that rings have enough entries to cross
3063 * high thresholds
3064 */
3065 WARN_ON(bp->dropless_fc &&
3066 pause->bd_th_hi + FW_PREFETCH_CNT >
3067 bp->rx_ring_size);
3068 WARN_ON(bp->dropless_fc &&
3069 pause->rcq_th_hi + FW_PREFETCH_CNT >
3070 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
3071
3072 pause->pri_map = 1;
3073 }
3074
3075 /* rxq setup */
3076 rxq_init->dscr_map = fp->rx_desc_mapping;
3077 rxq_init->sge_map = fp->rx_sge_mapping;
3078 rxq_init->rcq_map = fp->rx_comp_mapping;
3079 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
3080
3081 /* This should be a maximum number of data bytes that may be
3082 * placed on the BD (not including paddings).
3083 */
3084 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
3085 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
3086
3087 rxq_init->cl_qzone_id = fp->cl_qzone_id;
3088 rxq_init->tpa_agg_sz = tpa_agg_size;
3089 rxq_init->sge_buf_sz = sge_sz;
3090 rxq_init->max_sges_pkt = max_sge;
3091 rxq_init->rss_engine_id = BP_FUNC(bp);
3092 rxq_init->mcast_engine_id = BP_FUNC(bp);
3093
3094 /* Maximum number or simultaneous TPA aggregation for this Queue.
3095 *
3096 * For PF Clients it should be the maximum available number.
3097 * VF driver(s) may want to define it to a smaller value.
3098 */
3099 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
3100
3101 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
3102 rxq_init->fw_sb_id = fp->fw_sb_id;
3103
3104 if (IS_FCOE_FP(fp))
3105 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
3106 else
3107 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
3108 /* configure silent vlan removal
3109 * if multi function mode is afex, then mask default vlan
3110 */
3111 if (IS_MF_AFEX(bp)) {
3112 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
3113 rxq_init->silent_removal_mask = VLAN_VID_MASK;
3114 }
3115 }
3116
3117 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
3118 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
3119 u8 cos)
3120 {
3121 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
3122 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
3123 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
3124 txq_init->fw_sb_id = fp->fw_sb_id;
3125
3126 /*
3127 * set the tss leading client id for TX classfication ==
3128 * leading RSS client id
3129 */
3130 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
3131
3132 if (IS_FCOE_FP(fp)) {
3133 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
3134 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
3135 }
3136 }
3137
3138 static void bnx2x_pf_init(struct bnx2x *bp)
3139 {
3140 struct bnx2x_func_init_params func_init = {0};
3141 struct event_ring_data eq_data = { {0} };
3142 u16 flags;
3143
3144 if (!CHIP_IS_E1x(bp)) {
3145 /* reset IGU PF statistics: MSIX + ATTN */
3146 /* PF */
3147 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3148 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3149 (CHIP_MODE_IS_4_PORT(bp) ?
3150 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3151 /* ATTN */
3152 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
3153 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
3154 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
3155 (CHIP_MODE_IS_4_PORT(bp) ?
3156 BP_FUNC(bp) : BP_VN(bp))*4, 0);
3157 }
3158
3159 /* function setup flags */
3160 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
3161
3162 /* This flag is relevant for E1x only.
3163 * E2 doesn't have a TPA configuration in a function level.
3164 */
3165 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
3166
3167 func_init.func_flgs = flags;
3168 func_init.pf_id = BP_FUNC(bp);
3169 func_init.func_id = BP_FUNC(bp);
3170 func_init.spq_map = bp->spq_mapping;
3171 func_init.spq_prod = bp->spq_prod_idx;
3172
3173 bnx2x_func_init(bp, &func_init);
3174
3175 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
3176
3177 /*
3178 * Congestion management values depend on the link rate
3179 * There is no active link so initial link rate is set to 10 Gbps.
3180 * When the link comes up The congestion management values are
3181 * re-calculated according to the actual link rate.
3182 */
3183 bp->link_vars.line_speed = SPEED_10000;
3184 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3185
3186 /* Only the PMF sets the HW */
3187 if (bp->port.pmf)
3188 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3189
3190 /* init Event Queue - PCI bus guarantees correct endianity*/
3191 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3192 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3193 eq_data.producer = bp->eq_prod;
3194 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3195 eq_data.sb_id = DEF_SB_ID;
3196 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3197 }
3198
3199
3200 static void bnx2x_e1h_disable(struct bnx2x *bp)
3201 {
3202 int port = BP_PORT(bp);
3203
3204 bnx2x_tx_disable(bp);
3205
3206 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3207 }
3208
3209 static void bnx2x_e1h_enable(struct bnx2x *bp)
3210 {
3211 int port = BP_PORT(bp);
3212
3213 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3214
3215 /* Tx queue should be only reenabled */
3216 netif_tx_wake_all_queues(bp->dev);
3217
3218 /*
3219 * Should not call netif_carrier_on since it will be called if the link
3220 * is up when checking for link state
3221 */
3222 }
3223
3224 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3225
3226 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3227 {
3228 struct eth_stats_info *ether_stat =
3229 &bp->slowpath->drv_info_to_mcp.ether_stat;
3230 struct bnx2x_vlan_mac_obj *mac_obj =
3231 &bp->sp_objs->mac_obj;
3232 int i;
3233
3234 strlcpy(ether_stat->version, DRV_MODULE_VERSION,
3235 ETH_STAT_INFO_VERSION_LEN);
3236
3237 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3238 * mac_local field in ether_stat struct. The base address is offset by 2
3239 * bytes to account for the field being 8 bytes but a mac address is
3240 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3241 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3242 * allocated by the ether_stat struct, so the macs will land in their
3243 * proper positions.
3244 */
3245 for (i = 0; i < DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED; i++)
3246 memset(ether_stat->mac_local + i, 0,
3247 sizeof(ether_stat->mac_local[0]));
3248 mac_obj->get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3249 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3250 ether_stat->mac_local + MAC_PAD, MAC_PAD,
3251 ETH_ALEN);
3252 ether_stat->mtu_size = bp->dev->mtu;
3253 if (bp->dev->features & NETIF_F_RXCSUM)
3254 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3255 if (bp->dev->features & NETIF_F_TSO)
3256 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3257 ether_stat->feature_flags |= bp->common.boot_mode;
3258
3259 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3260
3261 ether_stat->txq_size = bp->tx_ring_size;
3262 ether_stat->rxq_size = bp->rx_ring_size;
3263 }
3264
3265 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3266 {
3267 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3268 struct fcoe_stats_info *fcoe_stat =
3269 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3270
3271 if (!CNIC_LOADED(bp))
3272 return;
3273
3274 memcpy(fcoe_stat->mac_local + MAC_PAD, bp->fip_mac, ETH_ALEN);
3275
3276 fcoe_stat->qos_priority =
3277 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3278
3279 /* insert FCoE stats from ramrod response */
3280 if (!NO_FCOE(bp)) {
3281 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3282 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3283 tstorm_queue_statistics;
3284
3285 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3286 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3287 xstorm_queue_statistics;
3288
3289 struct fcoe_statistics_params *fw_fcoe_stat =
3290 &bp->fw_stats_data->fcoe;
3291
3292 ADD_64_LE(fcoe_stat->rx_bytes_hi, LE32_0,
3293 fcoe_stat->rx_bytes_lo,
3294 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3295
3296 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3297 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3298 fcoe_stat->rx_bytes_lo,
3299 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3300
3301 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3302 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3303 fcoe_stat->rx_bytes_lo,
3304 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3305
3306 ADD_64_LE(fcoe_stat->rx_bytes_hi,
3307 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3308 fcoe_stat->rx_bytes_lo,
3309 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3310
3311 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3312 fcoe_stat->rx_frames_lo,
3313 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3314
3315 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3316 fcoe_stat->rx_frames_lo,
3317 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3318
3319 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3320 fcoe_stat->rx_frames_lo,
3321 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3322
3323 ADD_64_LE(fcoe_stat->rx_frames_hi, LE32_0,
3324 fcoe_stat->rx_frames_lo,
3325 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3326
3327 ADD_64_LE(fcoe_stat->tx_bytes_hi, LE32_0,
3328 fcoe_stat->tx_bytes_lo,
3329 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3330
3331 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3332 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3333 fcoe_stat->tx_bytes_lo,
3334 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3335
3336 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3337 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3338 fcoe_stat->tx_bytes_lo,
3339 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3340
3341 ADD_64_LE(fcoe_stat->tx_bytes_hi,
3342 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3343 fcoe_stat->tx_bytes_lo,
3344 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3345
3346 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3347 fcoe_stat->tx_frames_lo,
3348 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3349
3350 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3351 fcoe_stat->tx_frames_lo,
3352 fcoe_q_xstorm_stats->ucast_pkts_sent);
3353
3354 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3355 fcoe_stat->tx_frames_lo,
3356 fcoe_q_xstorm_stats->bcast_pkts_sent);
3357
3358 ADD_64_LE(fcoe_stat->tx_frames_hi, LE32_0,
3359 fcoe_stat->tx_frames_lo,
3360 fcoe_q_xstorm_stats->mcast_pkts_sent);
3361 }
3362
3363 /* ask L5 driver to add data to the struct */
3364 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3365 }
3366
3367 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3368 {
3369 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3370 struct iscsi_stats_info *iscsi_stat =
3371 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3372
3373 if (!CNIC_LOADED(bp))
3374 return;
3375
3376 memcpy(iscsi_stat->mac_local + MAC_PAD, bp->cnic_eth_dev.iscsi_mac,
3377 ETH_ALEN);
3378
3379 iscsi_stat->qos_priority =
3380 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3381
3382 /* ask L5 driver to add data to the struct */
3383 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3384 }
3385
3386 /* called due to MCP event (on pmf):
3387 * reread new bandwidth configuration
3388 * configure FW
3389 * notify others function about the change
3390 */
3391 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3392 {
3393 if (bp->link_vars.link_up) {
3394 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3395 bnx2x_link_sync_notify(bp);
3396 }
3397 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3398 }
3399
3400 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3401 {
3402 bnx2x_config_mf_bw(bp);
3403 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3404 }
3405
3406 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3407 {
3408 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3409 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3410 }
3411
3412 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3413 {
3414 enum drv_info_opcode op_code;
3415 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3416
3417 /* if drv_info version supported by MFW doesn't match - send NACK */
3418 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3419 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3420 return;
3421 }
3422
3423 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3424 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3425
3426 memset(&bp->slowpath->drv_info_to_mcp, 0,
3427 sizeof(union drv_info_to_mcp));
3428
3429 switch (op_code) {
3430 case ETH_STATS_OPCODE:
3431 bnx2x_drv_info_ether_stat(bp);
3432 break;
3433 case FCOE_STATS_OPCODE:
3434 bnx2x_drv_info_fcoe_stat(bp);
3435 break;
3436 case ISCSI_STATS_OPCODE:
3437 bnx2x_drv_info_iscsi_stat(bp);
3438 break;
3439 default:
3440 /* if op code isn't supported - send NACK */
3441 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3442 return;
3443 }
3444
3445 /* if we got drv_info attn from MFW then these fields are defined in
3446 * shmem2 for sure
3447 */
3448 SHMEM2_WR(bp, drv_info_host_addr_lo,
3449 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3450 SHMEM2_WR(bp, drv_info_host_addr_hi,
3451 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3452
3453 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3454 }
3455
3456 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3457 {
3458 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3459
3460 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3461
3462 /*
3463 * This is the only place besides the function initialization
3464 * where the bp->flags can change so it is done without any
3465 * locks
3466 */
3467 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3468 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3469 bp->flags |= MF_FUNC_DIS;
3470
3471 bnx2x_e1h_disable(bp);
3472 } else {
3473 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3474 bp->flags &= ~MF_FUNC_DIS;
3475
3476 bnx2x_e1h_enable(bp);
3477 }
3478 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3479 }
3480 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3481 bnx2x_config_mf_bw(bp);
3482 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3483 }
3484
3485 /* Report results to MCP */
3486 if (dcc_event)
3487 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3488 else
3489 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3490 }
3491
3492 /* must be called under the spq lock */
3493 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3494 {
3495 struct eth_spe *next_spe = bp->spq_prod_bd;
3496
3497 if (bp->spq_prod_bd == bp->spq_last_bd) {
3498 bp->spq_prod_bd = bp->spq;
3499 bp->spq_prod_idx = 0;
3500 DP(BNX2X_MSG_SP, "end of spq\n");
3501 } else {
3502 bp->spq_prod_bd++;
3503 bp->spq_prod_idx++;
3504 }
3505 return next_spe;
3506 }
3507
3508 /* must be called under the spq lock */
3509 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3510 {
3511 int func = BP_FUNC(bp);
3512
3513 /*
3514 * Make sure that BD data is updated before writing the producer:
3515 * BD data is written to the memory, the producer is read from the
3516 * memory, thus we need a full memory barrier to ensure the ordering.
3517 */
3518 mb();
3519
3520 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3521 bp->spq_prod_idx);
3522 mmiowb();
3523 }
3524
3525 /**
3526 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3527 *
3528 * @cmd: command to check
3529 * @cmd_type: command type
3530 */
3531 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3532 {
3533 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3534 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3535 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3536 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3537 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3538 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3539 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3540 return true;
3541 else
3542 return false;
3543
3544 }
3545
3546
3547 /**
3548 * bnx2x_sp_post - place a single command on an SP ring
3549 *
3550 * @bp: driver handle
3551 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3552 * @cid: SW CID the command is related to
3553 * @data_hi: command private data address (high 32 bits)
3554 * @data_lo: command private data address (low 32 bits)
3555 * @cmd_type: command type (e.g. NONE, ETH)
3556 *
3557 * SP data is handled as if it's always an address pair, thus data fields are
3558 * not swapped to little endian in upper functions. Instead this function swaps
3559 * data as if it's two u32 fields.
3560 */
3561 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3562 u32 data_hi, u32 data_lo, int cmd_type)
3563 {
3564 struct eth_spe *spe;
3565 u16 type;
3566 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3567
3568 #ifdef BNX2X_STOP_ON_ERROR
3569 if (unlikely(bp->panic)) {
3570 BNX2X_ERR("Can't post SP when there is panic\n");
3571 return -EIO;
3572 }
3573 #endif
3574
3575 spin_lock_bh(&bp->spq_lock);
3576
3577 if (common) {
3578 if (!atomic_read(&bp->eq_spq_left)) {
3579 BNX2X_ERR("BUG! EQ ring full!\n");
3580 spin_unlock_bh(&bp->spq_lock);
3581 bnx2x_panic();
3582 return -EBUSY;
3583 }
3584 } else if (!atomic_read(&bp->cq_spq_left)) {
3585 BNX2X_ERR("BUG! SPQ ring full!\n");
3586 spin_unlock_bh(&bp->spq_lock);
3587 bnx2x_panic();
3588 return -EBUSY;
3589 }
3590
3591 spe = bnx2x_sp_get_next(bp);
3592
3593 /* CID needs port number to be encoded int it */
3594 spe->hdr.conn_and_cmd_data =
3595 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3596 HW_CID(bp, cid));
3597
3598 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3599
3600 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3601 SPE_HDR_FUNCTION_ID);
3602
3603 spe->hdr.type = cpu_to_le16(type);
3604
3605 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3606 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3607
3608 /*
3609 * It's ok if the actual decrement is issued towards the memory
3610 * somewhere between the spin_lock and spin_unlock. Thus no
3611 * more explict memory barrier is needed.
3612 */
3613 if (common)
3614 atomic_dec(&bp->eq_spq_left);
3615 else
3616 atomic_dec(&bp->cq_spq_left);
3617
3618
3619 DP(BNX2X_MSG_SP,
3620 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3621 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3622 (u32)(U64_LO(bp->spq_mapping) +
3623 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3624 HW_CID(bp, cid), data_hi, data_lo, type,
3625 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3626
3627 bnx2x_sp_prod_update(bp);
3628 spin_unlock_bh(&bp->spq_lock);
3629 return 0;
3630 }
3631
3632 /* acquire split MCP access lock register */
3633 static int bnx2x_acquire_alr(struct bnx2x *bp)
3634 {
3635 u32 j, val;
3636 int rc = 0;
3637
3638 might_sleep();
3639 for (j = 0; j < 1000; j++) {
3640 val = (1UL << 31);
3641 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3642 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3643 if (val & (1L << 31))
3644 break;
3645
3646 msleep(5);
3647 }
3648 if (!(val & (1L << 31))) {
3649 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3650 rc = -EBUSY;
3651 }
3652
3653 return rc;
3654 }
3655
3656 /* release split MCP access lock register */
3657 static void bnx2x_release_alr(struct bnx2x *bp)
3658 {
3659 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3660 }
3661
3662 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3663 #define BNX2X_DEF_SB_IDX 0x0002
3664
3665 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3666 {
3667 struct host_sp_status_block *def_sb = bp->def_status_blk;
3668 u16 rc = 0;
3669
3670 barrier(); /* status block is written to by the chip */
3671 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3672 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3673 rc |= BNX2X_DEF_SB_ATT_IDX;
3674 }
3675
3676 if (bp->def_idx != def_sb->sp_sb.running_index) {
3677 bp->def_idx = def_sb->sp_sb.running_index;
3678 rc |= BNX2X_DEF_SB_IDX;
3679 }
3680
3681 /* Do not reorder: indecies reading should complete before handling */
3682 barrier();
3683 return rc;
3684 }
3685
3686 /*
3687 * slow path service functions
3688 */
3689
3690 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3691 {
3692 int port = BP_PORT(bp);
3693 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3694 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3695 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3696 NIG_REG_MASK_INTERRUPT_PORT0;
3697 u32 aeu_mask;
3698 u32 nig_mask = 0;
3699 u32 reg_addr;
3700
3701 if (bp->attn_state & asserted)
3702 BNX2X_ERR("IGU ERROR\n");
3703
3704 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3705 aeu_mask = REG_RD(bp, aeu_addr);
3706
3707 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3708 aeu_mask, asserted);
3709 aeu_mask &= ~(asserted & 0x3ff);
3710 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3711
3712 REG_WR(bp, aeu_addr, aeu_mask);
3713 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3714
3715 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3716 bp->attn_state |= asserted;
3717 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3718
3719 if (asserted & ATTN_HARD_WIRED_MASK) {
3720 if (asserted & ATTN_NIG_FOR_FUNC) {
3721
3722 bnx2x_acquire_phy_lock(bp);
3723
3724 /* save nig interrupt mask */
3725 nig_mask = REG_RD(bp, nig_int_mask_addr);
3726
3727 /* If nig_mask is not set, no need to call the update
3728 * function.
3729 */
3730 if (nig_mask) {
3731 REG_WR(bp, nig_int_mask_addr, 0);
3732
3733 bnx2x_link_attn(bp);
3734 }
3735
3736 /* handle unicore attn? */
3737 }
3738 if (asserted & ATTN_SW_TIMER_4_FUNC)
3739 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3740
3741 if (asserted & GPIO_2_FUNC)
3742 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3743
3744 if (asserted & GPIO_3_FUNC)
3745 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3746
3747 if (asserted & GPIO_4_FUNC)
3748 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3749
3750 if (port == 0) {
3751 if (asserted & ATTN_GENERAL_ATTN_1) {
3752 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3753 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3754 }
3755 if (asserted & ATTN_GENERAL_ATTN_2) {
3756 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3757 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3758 }
3759 if (asserted & ATTN_GENERAL_ATTN_3) {
3760 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3761 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3762 }
3763 } else {
3764 if (asserted & ATTN_GENERAL_ATTN_4) {
3765 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3766 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3767 }
3768 if (asserted & ATTN_GENERAL_ATTN_5) {
3769 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3770 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3771 }
3772 if (asserted & ATTN_GENERAL_ATTN_6) {
3773 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3774 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3775 }
3776 }
3777
3778 } /* if hardwired */
3779
3780 if (bp->common.int_block == INT_BLOCK_HC)
3781 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3782 COMMAND_REG_ATTN_BITS_SET);
3783 else
3784 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3785
3786 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3787 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3788 REG_WR(bp, reg_addr, asserted);
3789
3790 /* now set back the mask */
3791 if (asserted & ATTN_NIG_FOR_FUNC) {
3792 /* Verify that IGU ack through BAR was written before restoring
3793 * NIG mask. This loop should exit after 2-3 iterations max.
3794 */
3795 if (bp->common.int_block != INT_BLOCK_HC) {
3796 u32 cnt = 0, igu_acked;
3797 do {
3798 igu_acked = REG_RD(bp,
3799 IGU_REG_ATTENTION_ACK_BITS);
3800 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) &&
3801 (++cnt < MAX_IGU_ATTN_ACK_TO));
3802 if (!igu_acked)
3803 DP(NETIF_MSG_HW,
3804 "Failed to verify IGU ack on time\n");
3805 barrier();
3806 }
3807 REG_WR(bp, nig_int_mask_addr, nig_mask);
3808 bnx2x_release_phy_lock(bp);
3809 }
3810 }
3811
3812 static void bnx2x_fan_failure(struct bnx2x *bp)
3813 {
3814 int port = BP_PORT(bp);
3815 u32 ext_phy_config;
3816 /* mark the failure */
3817 ext_phy_config =
3818 SHMEM_RD(bp,
3819 dev_info.port_hw_config[port].external_phy_config);
3820
3821 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3822 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3823 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3824 ext_phy_config);
3825
3826 /* log the failure */
3827 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3828 "Please contact OEM Support for assistance\n");
3829
3830 /*
3831 * Schedule device reset (unload)
3832 * This is due to some boards consuming sufficient power when driver is
3833 * up to overheat if fan fails.
3834 */
3835 smp_mb__before_clear_bit();
3836 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3837 smp_mb__after_clear_bit();
3838 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3839
3840 }
3841
3842 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3843 {
3844 int port = BP_PORT(bp);
3845 int reg_offset;
3846 u32 val;
3847
3848 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3849 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3850
3851 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3852
3853 val = REG_RD(bp, reg_offset);
3854 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3855 REG_WR(bp, reg_offset, val);
3856
3857 BNX2X_ERR("SPIO5 hw attention\n");
3858
3859 /* Fan failure attention */
3860 bnx2x_hw_reset_phy(&bp->link_params);
3861 bnx2x_fan_failure(bp);
3862 }
3863
3864 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3865 bnx2x_acquire_phy_lock(bp);
3866 bnx2x_handle_module_detect_int(&bp->link_params);
3867 bnx2x_release_phy_lock(bp);
3868 }
3869
3870 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3871
3872 val = REG_RD(bp, reg_offset);
3873 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3874 REG_WR(bp, reg_offset, val);
3875
3876 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3877 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3878 bnx2x_panic();
3879 }
3880 }
3881
3882 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3883 {
3884 u32 val;
3885
3886 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3887
3888 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3889 BNX2X_ERR("DB hw attention 0x%x\n", val);
3890 /* DORQ discard attention */
3891 if (val & 0x2)
3892 BNX2X_ERR("FATAL error from DORQ\n");
3893 }
3894
3895 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3896
3897 int port = BP_PORT(bp);
3898 int reg_offset;
3899
3900 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3901 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3902
3903 val = REG_RD(bp, reg_offset);
3904 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3905 REG_WR(bp, reg_offset, val);
3906
3907 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3908 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3909 bnx2x_panic();
3910 }
3911 }
3912
3913 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3914 {
3915 u32 val;
3916
3917 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3918
3919 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3920 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3921 /* CFC error attention */
3922 if (val & 0x2)
3923 BNX2X_ERR("FATAL error from CFC\n");
3924 }
3925
3926 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3927 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3928 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3929 /* RQ_USDMDP_FIFO_OVERFLOW */
3930 if (val & 0x18000)
3931 BNX2X_ERR("FATAL error from PXP\n");
3932
3933 if (!CHIP_IS_E1x(bp)) {
3934 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3935 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3936 }
3937 }
3938
3939 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3940
3941 int port = BP_PORT(bp);
3942 int reg_offset;
3943
3944 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3945 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3946
3947 val = REG_RD(bp, reg_offset);
3948 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3949 REG_WR(bp, reg_offset, val);
3950
3951 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3952 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3953 bnx2x_panic();
3954 }
3955 }
3956
3957 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3958 {
3959 u32 val;
3960
3961 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3962
3963 if (attn & BNX2X_PMF_LINK_ASSERT) {
3964 int func = BP_FUNC(bp);
3965
3966 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3967 bnx2x_read_mf_cfg(bp);
3968 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3969 func_mf_config[BP_ABS_FUNC(bp)].config);
3970 val = SHMEM_RD(bp,
3971 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3972 if (val & DRV_STATUS_DCC_EVENT_MASK)
3973 bnx2x_dcc_event(bp,
3974 (val & DRV_STATUS_DCC_EVENT_MASK));
3975
3976 if (val & DRV_STATUS_SET_MF_BW)
3977 bnx2x_set_mf_bw(bp);
3978
3979 if (val & DRV_STATUS_DRV_INFO_REQ)
3980 bnx2x_handle_drv_info_req(bp);
3981
3982 if (val & DRV_STATUS_VF_DISABLED)
3983 bnx2x_vf_handle_flr_event(bp);
3984
3985 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3986 bnx2x_pmf_update(bp);
3987
3988 if (bp->port.pmf &&
3989 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3990 bp->dcbx_enabled > 0)
3991 /* start dcbx state machine */
3992 bnx2x_dcbx_set_params(bp,
3993 BNX2X_DCBX_STATE_NEG_RECEIVED);
3994 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3995 bnx2x_handle_afex_cmd(bp,
3996 val & DRV_STATUS_AFEX_EVENT_MASK);
3997 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3998 bnx2x_handle_eee_event(bp);
3999 if (bp->link_vars.periodic_flags &
4000 PERIODIC_FLAGS_LINK_EVENT) {
4001 /* sync with link */
4002 bnx2x_acquire_phy_lock(bp);
4003 bp->link_vars.periodic_flags &=
4004 ~PERIODIC_FLAGS_LINK_EVENT;
4005 bnx2x_release_phy_lock(bp);
4006 if (IS_MF(bp))
4007 bnx2x_link_sync_notify(bp);
4008 bnx2x_link_report(bp);
4009 }
4010 /* Always call it here: bnx2x_link_report() will
4011 * prevent the link indication duplication.
4012 */
4013 bnx2x__link_status_update(bp);
4014 } else if (attn & BNX2X_MC_ASSERT_BITS) {
4015
4016 BNX2X_ERR("MC assert!\n");
4017 bnx2x_mc_assert(bp);
4018 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
4019 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
4020 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
4021 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
4022 bnx2x_panic();
4023
4024 } else if (attn & BNX2X_MCP_ASSERT) {
4025
4026 BNX2X_ERR("MCP assert!\n");
4027 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
4028 bnx2x_fw_dump(bp);
4029
4030 } else
4031 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
4032 }
4033
4034 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
4035 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
4036 if (attn & BNX2X_GRC_TIMEOUT) {
4037 val = CHIP_IS_E1(bp) ? 0 :
4038 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
4039 BNX2X_ERR("GRC time-out 0x%08x\n", val);
4040 }
4041 if (attn & BNX2X_GRC_RSV) {
4042 val = CHIP_IS_E1(bp) ? 0 :
4043 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
4044 BNX2X_ERR("GRC reserved 0x%08x\n", val);
4045 }
4046 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
4047 }
4048 }
4049
4050 /*
4051 * Bits map:
4052 * 0-7 - Engine0 load counter.
4053 * 8-15 - Engine1 load counter.
4054 * 16 - Engine0 RESET_IN_PROGRESS bit.
4055 * 17 - Engine1 RESET_IN_PROGRESS bit.
4056 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4057 * on the engine
4058 * 19 - Engine1 ONE_IS_LOADED.
4059 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4060 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4061 * just the one belonging to its engine).
4062 *
4063 */
4064 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4065
4066 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4067 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4068 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4069 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4070 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4071 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4072 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4073
4074 /*
4075 * Set the GLOBAL_RESET bit.
4076 *
4077 * Should be run under rtnl lock
4078 */
4079 void bnx2x_set_reset_global(struct bnx2x *bp)
4080 {
4081 u32 val;
4082 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4083 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4084 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
4085 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4086 }
4087
4088 /*
4089 * Clear the GLOBAL_RESET bit.
4090 *
4091 * Should be run under rtnl lock
4092 */
4093 static void bnx2x_clear_reset_global(struct bnx2x *bp)
4094 {
4095 u32 val;
4096 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4097 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4098 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
4099 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4100 }
4101
4102 /*
4103 * Checks the GLOBAL_RESET bit.
4104 *
4105 * should be run under rtnl lock
4106 */
4107 static bool bnx2x_reset_is_global(struct bnx2x *bp)
4108 {
4109 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4110
4111 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
4112 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
4113 }
4114
4115 /*
4116 * Clear RESET_IN_PROGRESS bit for the current engine.
4117 *
4118 * Should be run under rtnl lock
4119 */
4120 static void bnx2x_set_reset_done(struct bnx2x *bp)
4121 {
4122 u32 val;
4123 u32 bit = BP_PATH(bp) ?
4124 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4125 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4126 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4127
4128 /* Clear the bit */
4129 val &= ~bit;
4130 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4131
4132 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4133 }
4134
4135 /*
4136 * Set RESET_IN_PROGRESS for the current engine.
4137 *
4138 * should be run under rtnl lock
4139 */
4140 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
4141 {
4142 u32 val;
4143 u32 bit = BP_PATH(bp) ?
4144 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4145 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4146 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4147
4148 /* Set the bit */
4149 val |= bit;
4150 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4151 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4152 }
4153
4154 /*
4155 * Checks the RESET_IN_PROGRESS bit for the given engine.
4156 * should be run under rtnl lock
4157 */
4158 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
4159 {
4160 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4161 u32 bit = engine ?
4162 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
4163
4164 /* return false if bit is set */
4165 return (val & bit) ? false : true;
4166 }
4167
4168 /*
4169 * set pf load for the current pf.
4170 *
4171 * should be run under rtnl lock
4172 */
4173 void bnx2x_set_pf_load(struct bnx2x *bp)
4174 {
4175 u32 val1, val;
4176 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4177 BNX2X_PATH0_LOAD_CNT_MASK;
4178 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4179 BNX2X_PATH0_LOAD_CNT_SHIFT;
4180
4181 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4182 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4183
4184 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
4185
4186 /* get the current counter value */
4187 val1 = (val & mask) >> shift;
4188
4189 /* set bit of that PF */
4190 val1 |= (1 << bp->pf_num);
4191
4192 /* clear the old value */
4193 val &= ~mask;
4194
4195 /* set the new one */
4196 val |= ((val1 << shift) & mask);
4197
4198 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4199 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4200 }
4201
4202 /**
4203 * bnx2x_clear_pf_load - clear pf load mark
4204 *
4205 * @bp: driver handle
4206 *
4207 * Should be run under rtnl lock.
4208 * Decrements the load counter for the current engine. Returns
4209 * whether other functions are still loaded
4210 */
4211 bool bnx2x_clear_pf_load(struct bnx2x *bp)
4212 {
4213 u32 val1, val;
4214 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
4215 BNX2X_PATH0_LOAD_CNT_MASK;
4216 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4217 BNX2X_PATH0_LOAD_CNT_SHIFT;
4218
4219 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4220 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4221 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4222
4223 /* get the current counter value */
4224 val1 = (val & mask) >> shift;
4225
4226 /* clear bit of that PF */
4227 val1 &= ~(1 << bp->pf_num);
4228
4229 /* clear the old value */
4230 val &= ~mask;
4231
4232 /* set the new one */
4233 val |= ((val1 << shift) & mask);
4234
4235 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4236 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4237 return val1 != 0;
4238 }
4239
4240 /*
4241 * Read the load status for the current engine.
4242 *
4243 * should be run under rtnl lock
4244 */
4245 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4246 {
4247 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4248 BNX2X_PATH0_LOAD_CNT_MASK);
4249 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4250 BNX2X_PATH0_LOAD_CNT_SHIFT);
4251 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4252
4253 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4254
4255 val = (val & mask) >> shift;
4256
4257 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4258 engine, val);
4259
4260 return val != 0;
4261 }
4262
4263 static void _print_next_block(int idx, const char *blk)
4264 {
4265 pr_cont("%s%s", idx ? ", " : "", blk);
4266 }
4267
4268 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4269 bool print)
4270 {
4271 int i = 0;
4272 u32 cur_bit = 0;
4273 for (i = 0; sig; i++) {
4274 cur_bit = ((u32)0x1 << i);
4275 if (sig & cur_bit) {
4276 switch (cur_bit) {
4277 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4278 if (print)
4279 _print_next_block(par_num++, "BRB");
4280 break;
4281 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4282 if (print)
4283 _print_next_block(par_num++, "PARSER");
4284 break;
4285 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4286 if (print)
4287 _print_next_block(par_num++, "TSDM");
4288 break;
4289 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4290 if (print)
4291 _print_next_block(par_num++,
4292 "SEARCHER");
4293 break;
4294 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4295 if (print)
4296 _print_next_block(par_num++, "TCM");
4297 break;
4298 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4299 if (print)
4300 _print_next_block(par_num++, "TSEMI");
4301 break;
4302 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4303 if (print)
4304 _print_next_block(par_num++, "XPB");
4305 break;
4306 }
4307
4308 /* Clear the bit */
4309 sig &= ~cur_bit;
4310 }
4311 }
4312
4313 return par_num;
4314 }
4315
4316 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4317 bool *global, bool print)
4318 {
4319 int i = 0;
4320 u32 cur_bit = 0;
4321 for (i = 0; sig; i++) {
4322 cur_bit = ((u32)0x1 << i);
4323 if (sig & cur_bit) {
4324 switch (cur_bit) {
4325 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4326 if (print)
4327 _print_next_block(par_num++, "PBF");
4328 break;
4329 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4330 if (print)
4331 _print_next_block(par_num++, "QM");
4332 break;
4333 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4334 if (print)
4335 _print_next_block(par_num++, "TM");
4336 break;
4337 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4338 if (print)
4339 _print_next_block(par_num++, "XSDM");
4340 break;
4341 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4342 if (print)
4343 _print_next_block(par_num++, "XCM");
4344 break;
4345 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4346 if (print)
4347 _print_next_block(par_num++, "XSEMI");
4348 break;
4349 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4350 if (print)
4351 _print_next_block(par_num++,
4352 "DOORBELLQ");
4353 break;
4354 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4355 if (print)
4356 _print_next_block(par_num++, "NIG");
4357 break;
4358 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4359 if (print)
4360 _print_next_block(par_num++,
4361 "VAUX PCI CORE");
4362 *global = true;
4363 break;
4364 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4365 if (print)
4366 _print_next_block(par_num++, "DEBUG");
4367 break;
4368 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4369 if (print)
4370 _print_next_block(par_num++, "USDM");
4371 break;
4372 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4373 if (print)
4374 _print_next_block(par_num++, "UCM");
4375 break;
4376 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4377 if (print)
4378 _print_next_block(par_num++, "USEMI");
4379 break;
4380 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4381 if (print)
4382 _print_next_block(par_num++, "UPB");
4383 break;
4384 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4385 if (print)
4386 _print_next_block(par_num++, "CSDM");
4387 break;
4388 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4389 if (print)
4390 _print_next_block(par_num++, "CCM");
4391 break;
4392 }
4393
4394 /* Clear the bit */
4395 sig &= ~cur_bit;
4396 }
4397 }
4398
4399 return par_num;
4400 }
4401
4402 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4403 bool print)
4404 {
4405 int i = 0;
4406 u32 cur_bit = 0;
4407 for (i = 0; sig; i++) {
4408 cur_bit = ((u32)0x1 << i);
4409 if (sig & cur_bit) {
4410 switch (cur_bit) {
4411 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4412 if (print)
4413 _print_next_block(par_num++, "CSEMI");
4414 break;
4415 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4416 if (print)
4417 _print_next_block(par_num++, "PXP");
4418 break;
4419 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4420 if (print)
4421 _print_next_block(par_num++,
4422 "PXPPCICLOCKCLIENT");
4423 break;
4424 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4425 if (print)
4426 _print_next_block(par_num++, "CFC");
4427 break;
4428 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4429 if (print)
4430 _print_next_block(par_num++, "CDU");
4431 break;
4432 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4433 if (print)
4434 _print_next_block(par_num++, "DMAE");
4435 break;
4436 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4437 if (print)
4438 _print_next_block(par_num++, "IGU");
4439 break;
4440 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4441 if (print)
4442 _print_next_block(par_num++, "MISC");
4443 break;
4444 }
4445
4446 /* Clear the bit */
4447 sig &= ~cur_bit;
4448 }
4449 }
4450
4451 return par_num;
4452 }
4453
4454 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4455 bool *global, bool print)
4456 {
4457 int i = 0;
4458 u32 cur_bit = 0;
4459 for (i = 0; sig; i++) {
4460 cur_bit = ((u32)0x1 << i);
4461 if (sig & cur_bit) {
4462 switch (cur_bit) {
4463 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4464 if (print)
4465 _print_next_block(par_num++, "MCP ROM");
4466 *global = true;
4467 break;
4468 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4469 if (print)
4470 _print_next_block(par_num++,
4471 "MCP UMP RX");
4472 *global = true;
4473 break;
4474 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4475 if (print)
4476 _print_next_block(par_num++,
4477 "MCP UMP TX");
4478 *global = true;
4479 break;
4480 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4481 if (print)
4482 _print_next_block(par_num++,
4483 "MCP SCPAD");
4484 *global = true;
4485 break;
4486 }
4487
4488 /* Clear the bit */
4489 sig &= ~cur_bit;
4490 }
4491 }
4492
4493 return par_num;
4494 }
4495
4496 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4497 bool print)
4498 {
4499 int i = 0;
4500 u32 cur_bit = 0;
4501 for (i = 0; sig; i++) {
4502 cur_bit = ((u32)0x1 << i);
4503 if (sig & cur_bit) {
4504 switch (cur_bit) {
4505 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4506 if (print)
4507 _print_next_block(par_num++, "PGLUE_B");
4508 break;
4509 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4510 if (print)
4511 _print_next_block(par_num++, "ATC");
4512 break;
4513 }
4514
4515 /* Clear the bit */
4516 sig &= ~cur_bit;
4517 }
4518 }
4519
4520 return par_num;
4521 }
4522
4523 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4524 u32 *sig)
4525 {
4526 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4527 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4528 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4529 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4530 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4531 int par_num = 0;
4532 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4533 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4534 sig[0] & HW_PRTY_ASSERT_SET_0,
4535 sig[1] & HW_PRTY_ASSERT_SET_1,
4536 sig[2] & HW_PRTY_ASSERT_SET_2,
4537 sig[3] & HW_PRTY_ASSERT_SET_3,
4538 sig[4] & HW_PRTY_ASSERT_SET_4);
4539 if (print)
4540 netdev_err(bp->dev,
4541 "Parity errors detected in blocks: ");
4542 par_num = bnx2x_check_blocks_with_parity0(
4543 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4544 par_num = bnx2x_check_blocks_with_parity1(
4545 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4546 par_num = bnx2x_check_blocks_with_parity2(
4547 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4548 par_num = bnx2x_check_blocks_with_parity3(
4549 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4550 par_num = bnx2x_check_blocks_with_parity4(
4551 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4552
4553 if (print)
4554 pr_cont("\n");
4555
4556 return true;
4557 } else
4558 return false;
4559 }
4560
4561 /**
4562 * bnx2x_chk_parity_attn - checks for parity attentions.
4563 *
4564 * @bp: driver handle
4565 * @global: true if there was a global attention
4566 * @print: show parity attention in syslog
4567 */
4568 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4569 {
4570 struct attn_route attn = { {0} };
4571 int port = BP_PORT(bp);
4572
4573 attn.sig[0] = REG_RD(bp,
4574 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4575 port*4);
4576 attn.sig[1] = REG_RD(bp,
4577 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4578 port*4);
4579 attn.sig[2] = REG_RD(bp,
4580 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4581 port*4);
4582 attn.sig[3] = REG_RD(bp,
4583 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4584 port*4);
4585
4586 if (!CHIP_IS_E1x(bp))
4587 attn.sig[4] = REG_RD(bp,
4588 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4589 port*4);
4590
4591 return bnx2x_parity_attn(bp, global, print, attn.sig);
4592 }
4593
4594
4595 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4596 {
4597 u32 val;
4598 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4599
4600 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4601 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4602 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4603 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4604 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4605 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4606 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4607 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4608 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4609 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4610 if (val &
4611 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4612 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4613 if (val &
4614 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4615 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4616 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4617 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4618 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4619 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4620 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4621 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4622 }
4623 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4624 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4625 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4626 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4627 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4628 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4629 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4630 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4631 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4632 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4633 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4634 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4635 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4636 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4637 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4638 }
4639
4640 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4641 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4642 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4643 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4644 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4645 }
4646
4647 }
4648
4649 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4650 {
4651 struct attn_route attn, *group_mask;
4652 int port = BP_PORT(bp);
4653 int index;
4654 u32 reg_addr;
4655 u32 val;
4656 u32 aeu_mask;
4657 bool global = false;
4658
4659 /* need to take HW lock because MCP or other port might also
4660 try to handle this event */
4661 bnx2x_acquire_alr(bp);
4662
4663 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4664 #ifndef BNX2X_STOP_ON_ERROR
4665 bp->recovery_state = BNX2X_RECOVERY_INIT;
4666 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4667 /* Disable HW interrupts */
4668 bnx2x_int_disable(bp);
4669 /* In case of parity errors don't handle attentions so that
4670 * other function would "see" parity errors.
4671 */
4672 #else
4673 bnx2x_panic();
4674 #endif
4675 bnx2x_release_alr(bp);
4676 return;
4677 }
4678
4679 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4680 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4681 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4682 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4683 if (!CHIP_IS_E1x(bp))
4684 attn.sig[4] =
4685 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4686 else
4687 attn.sig[4] = 0;
4688
4689 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4690 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4691
4692 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4693 if (deasserted & (1 << index)) {
4694 group_mask = &bp->attn_group[index];
4695
4696 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4697 index,
4698 group_mask->sig[0], group_mask->sig[1],
4699 group_mask->sig[2], group_mask->sig[3],
4700 group_mask->sig[4]);
4701
4702 bnx2x_attn_int_deasserted4(bp,
4703 attn.sig[4] & group_mask->sig[4]);
4704 bnx2x_attn_int_deasserted3(bp,
4705 attn.sig[3] & group_mask->sig[3]);
4706 bnx2x_attn_int_deasserted1(bp,
4707 attn.sig[1] & group_mask->sig[1]);
4708 bnx2x_attn_int_deasserted2(bp,
4709 attn.sig[2] & group_mask->sig[2]);
4710 bnx2x_attn_int_deasserted0(bp,
4711 attn.sig[0] & group_mask->sig[0]);
4712 }
4713 }
4714
4715 bnx2x_release_alr(bp);
4716
4717 if (bp->common.int_block == INT_BLOCK_HC)
4718 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4719 COMMAND_REG_ATTN_BITS_CLR);
4720 else
4721 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4722
4723 val = ~deasserted;
4724 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4725 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4726 REG_WR(bp, reg_addr, val);
4727
4728 if (~bp->attn_state & deasserted)
4729 BNX2X_ERR("IGU ERROR\n");
4730
4731 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4732 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4733
4734 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4735 aeu_mask = REG_RD(bp, reg_addr);
4736
4737 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4738 aeu_mask, deasserted);
4739 aeu_mask |= (deasserted & 0x3ff);
4740 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4741
4742 REG_WR(bp, reg_addr, aeu_mask);
4743 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4744
4745 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4746 bp->attn_state &= ~deasserted;
4747 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4748 }
4749
4750 static void bnx2x_attn_int(struct bnx2x *bp)
4751 {
4752 /* read local copy of bits */
4753 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4754 attn_bits);
4755 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4756 attn_bits_ack);
4757 u32 attn_state = bp->attn_state;
4758
4759 /* look for changed bits */
4760 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4761 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4762
4763 DP(NETIF_MSG_HW,
4764 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4765 attn_bits, attn_ack, asserted, deasserted);
4766
4767 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4768 BNX2X_ERR("BAD attention state\n");
4769
4770 /* handle bits that were raised */
4771 if (asserted)
4772 bnx2x_attn_int_asserted(bp, asserted);
4773
4774 if (deasserted)
4775 bnx2x_attn_int_deasserted(bp, deasserted);
4776 }
4777
4778 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4779 u16 index, u8 op, u8 update)
4780 {
4781 u32 igu_addr = bp->igu_base_addr;
4782 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4783 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4784 igu_addr);
4785 }
4786
4787 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4788 {
4789 /* No memory barriers */
4790 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4791 mmiowb(); /* keep prod updates ordered */
4792 }
4793
4794 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4795 union event_ring_elem *elem)
4796 {
4797 u8 err = elem->message.error;
4798
4799 if (!bp->cnic_eth_dev.starting_cid ||
4800 (cid < bp->cnic_eth_dev.starting_cid &&
4801 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4802 return 1;
4803
4804 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4805
4806 if (unlikely(err)) {
4807
4808 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4809 cid);
4810 bnx2x_panic_dump(bp, false);
4811 }
4812 bnx2x_cnic_cfc_comp(bp, cid, err);
4813 return 0;
4814 }
4815
4816 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4817 {
4818 struct bnx2x_mcast_ramrod_params rparam;
4819 int rc;
4820
4821 memset(&rparam, 0, sizeof(rparam));
4822
4823 rparam.mcast_obj = &bp->mcast_obj;
4824
4825 netif_addr_lock_bh(bp->dev);
4826
4827 /* Clear pending state for the last command */
4828 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4829
4830 /* If there are pending mcast commands - send them */
4831 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4832 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4833 if (rc < 0)
4834 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4835 rc);
4836 }
4837
4838 netif_addr_unlock_bh(bp->dev);
4839 }
4840
4841 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4842 union event_ring_elem *elem)
4843 {
4844 unsigned long ramrod_flags = 0;
4845 int rc = 0;
4846 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4847 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4848
4849 /* Always push next commands out, don't wait here */
4850 __set_bit(RAMROD_CONT, &ramrod_flags);
4851
4852 switch (le32_to_cpu((__force __le32)elem->message.data.eth_event.echo)
4853 >> BNX2X_SWCID_SHIFT) {
4854 case BNX2X_FILTER_MAC_PENDING:
4855 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4856 if (CNIC_LOADED(bp) && (cid == BNX2X_ISCSI_ETH_CID(bp)))
4857 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4858 else
4859 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4860
4861 break;
4862 case BNX2X_FILTER_MCAST_PENDING:
4863 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4864 /* This is only relevant for 57710 where multicast MACs are
4865 * configured as unicast MACs using the same ramrod.
4866 */
4867 bnx2x_handle_mcast_eqe(bp);
4868 return;
4869 default:
4870 BNX2X_ERR("Unsupported classification command: %d\n",
4871 elem->message.data.eth_event.echo);
4872 return;
4873 }
4874
4875 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4876
4877 if (rc < 0)
4878 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4879 else if (rc > 0)
4880 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4881
4882 }
4883
4884 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4885
4886 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4887 {
4888 netif_addr_lock_bh(bp->dev);
4889
4890 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4891
4892 /* Send rx_mode command again if was requested */
4893 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4894 bnx2x_set_storm_rx_mode(bp);
4895 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4896 &bp->sp_state))
4897 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4898 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4899 &bp->sp_state))
4900 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4901
4902 netif_addr_unlock_bh(bp->dev);
4903 }
4904
4905 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4906 union event_ring_elem *elem)
4907 {
4908 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4909 DP(BNX2X_MSG_SP,
4910 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4911 elem->message.data.vif_list_event.func_bit_map);
4912 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4913 elem->message.data.vif_list_event.func_bit_map);
4914 } else if (elem->message.data.vif_list_event.echo ==
4915 VIF_LIST_RULE_SET) {
4916 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4917 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4918 }
4919 }
4920
4921 /* called with rtnl_lock */
4922 static void bnx2x_after_function_update(struct bnx2x *bp)
4923 {
4924 int q, rc;
4925 struct bnx2x_fastpath *fp;
4926 struct bnx2x_queue_state_params queue_params = {NULL};
4927 struct bnx2x_queue_update_params *q_update_params =
4928 &queue_params.params.update;
4929
4930 /* Send Q update command with afex vlan removal values for all Qs */
4931 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4932
4933 /* set silent vlan removal values according to vlan mode */
4934 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4935 &q_update_params->update_flags);
4936 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4937 &q_update_params->update_flags);
4938 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4939
4940 /* in access mode mark mask and value are 0 to strip all vlans */
4941 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4942 q_update_params->silent_removal_value = 0;
4943 q_update_params->silent_removal_mask = 0;
4944 } else {
4945 q_update_params->silent_removal_value =
4946 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4947 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4948 }
4949
4950 for_each_eth_queue(bp, q) {
4951 /* Set the appropriate Queue object */
4952 fp = &bp->fp[q];
4953 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4954
4955 /* send the ramrod */
4956 rc = bnx2x_queue_state_change(bp, &queue_params);
4957 if (rc < 0)
4958 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4959 q);
4960 }
4961
4962 if (!NO_FCOE(bp)) {
4963 fp = &bp->fp[FCOE_IDX(bp)];
4964 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4965
4966 /* clear pending completion bit */
4967 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4968
4969 /* mark latest Q bit */
4970 smp_mb__before_clear_bit();
4971 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4972 smp_mb__after_clear_bit();
4973
4974 /* send Q update ramrod for FCoE Q */
4975 rc = bnx2x_queue_state_change(bp, &queue_params);
4976 if (rc < 0)
4977 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4978 q);
4979 } else {
4980 /* If no FCoE ring - ACK MCP now */
4981 bnx2x_link_report(bp);
4982 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4983 }
4984 }
4985
4986 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4987 struct bnx2x *bp, u32 cid)
4988 {
4989 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4990
4991 if (CNIC_LOADED(bp) && (cid == BNX2X_FCOE_ETH_CID(bp)))
4992 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4993 else
4994 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4995 }
4996
4997 static void bnx2x_eq_int(struct bnx2x *bp)
4998 {
4999 u16 hw_cons, sw_cons, sw_prod;
5000 union event_ring_elem *elem;
5001 u8 echo;
5002 u32 cid;
5003 u8 opcode;
5004 int rc, spqe_cnt = 0;
5005 struct bnx2x_queue_sp_obj *q_obj;
5006 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
5007 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
5008
5009 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
5010
5011 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5012 * when we get the the next-page we nned to adjust so the loop
5013 * condition below will be met. The next element is the size of a
5014 * regular element and hence incrementing by 1
5015 */
5016 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
5017 hw_cons++;
5018
5019 /* This function may never run in parallel with itself for a
5020 * specific bp, thus there is no need in "paired" read memory
5021 * barrier here.
5022 */
5023 sw_cons = bp->eq_cons;
5024 sw_prod = bp->eq_prod;
5025
5026 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5027 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
5028
5029 for (; sw_cons != hw_cons;
5030 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
5031
5032 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
5033
5034 rc = bnx2x_iov_eq_sp_event(bp, elem);
5035 if (!rc) {
5036 DP(BNX2X_MSG_IOV, "bnx2x_iov_eq_sp_event returned %d\n",
5037 rc);
5038 goto next_spqe;
5039 }
5040
5041 /* elem CID originates from FW; actually LE */
5042 cid = SW_CID((__force __le32)
5043 elem->message.data.cfc_del_event.cid);
5044 opcode = elem->message.opcode;
5045
5046 /* handle eq element */
5047 switch (opcode) {
5048 case EVENT_RING_OPCODE_VF_PF_CHANNEL:
5049 DP(BNX2X_MSG_IOV, "vf pf channel element on eq\n");
5050 bnx2x_vf_mbx(bp, &elem->message.data.vf_pf_event);
5051 continue;
5052
5053 case EVENT_RING_OPCODE_STAT_QUERY:
5054 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
5055 "got statistics comp event %d\n",
5056 bp->stats_comp++);
5057 /* nothing to do with stats comp */
5058 goto next_spqe;
5059
5060 case EVENT_RING_OPCODE_CFC_DEL:
5061 /* handle according to cid range */
5062 /*
5063 * we may want to verify here that the bp state is
5064 * HALTING
5065 */
5066 DP(BNX2X_MSG_SP,
5067 "got delete ramrod for MULTI[%d]\n", cid);
5068
5069 if (CNIC_LOADED(bp) &&
5070 !bnx2x_cnic_handle_cfc_del(bp, cid, elem))
5071 goto next_spqe;
5072
5073 q_obj = bnx2x_cid_to_q_obj(bp, cid);
5074
5075 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
5076 break;
5077
5078
5079
5080 goto next_spqe;
5081
5082 case EVENT_RING_OPCODE_STOP_TRAFFIC:
5083 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
5084 if (f_obj->complete_cmd(bp, f_obj,
5085 BNX2X_F_CMD_TX_STOP))
5086 break;
5087 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
5088 goto next_spqe;
5089
5090 case EVENT_RING_OPCODE_START_TRAFFIC:
5091 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
5092 if (f_obj->complete_cmd(bp, f_obj,
5093 BNX2X_F_CMD_TX_START))
5094 break;
5095 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
5096 goto next_spqe;
5097
5098 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
5099 echo = elem->message.data.function_update_event.echo;
5100 if (echo == SWITCH_UPDATE) {
5101 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5102 "got FUNC_SWITCH_UPDATE ramrod\n");
5103 if (f_obj->complete_cmd(
5104 bp, f_obj, BNX2X_F_CMD_SWITCH_UPDATE))
5105 break;
5106
5107 } else {
5108 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
5109 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5110 f_obj->complete_cmd(bp, f_obj,
5111 BNX2X_F_CMD_AFEX_UPDATE);
5112
5113 /* We will perform the Queues update from
5114 * sp_rtnl task as all Queue SP operations
5115 * should run under rtnl_lock.
5116 */
5117 smp_mb__before_clear_bit();
5118 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
5119 &bp->sp_rtnl_state);
5120 smp_mb__after_clear_bit();
5121
5122 schedule_delayed_work(&bp->sp_rtnl_task, 0);
5123 }
5124
5125 goto next_spqe;
5126
5127 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
5128 f_obj->complete_cmd(bp, f_obj,
5129 BNX2X_F_CMD_AFEX_VIFLISTS);
5130 bnx2x_after_afex_vif_lists(bp, elem);
5131 goto next_spqe;
5132 case EVENT_RING_OPCODE_FUNCTION_START:
5133 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5134 "got FUNC_START ramrod\n");
5135 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
5136 break;
5137
5138 goto next_spqe;
5139
5140 case EVENT_RING_OPCODE_FUNCTION_STOP:
5141 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
5142 "got FUNC_STOP ramrod\n");
5143 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
5144 break;
5145
5146 goto next_spqe;
5147 }
5148
5149 switch (opcode | bp->state) {
5150 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5151 BNX2X_STATE_OPEN):
5152 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
5153 BNX2X_STATE_OPENING_WAIT4_PORT):
5154 cid = elem->message.data.eth_event.echo &
5155 BNX2X_SWCID_MASK;
5156 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
5157 cid);
5158 rss_raw->clear_pending(rss_raw);
5159 break;
5160
5161 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
5162 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
5163 case (EVENT_RING_OPCODE_SET_MAC |
5164 BNX2X_STATE_CLOSING_WAIT4_HALT):
5165 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5166 BNX2X_STATE_OPEN):
5167 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5168 BNX2X_STATE_DIAG):
5169 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
5170 BNX2X_STATE_CLOSING_WAIT4_HALT):
5171 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
5172 bnx2x_handle_classification_eqe(bp, elem);
5173 break;
5174
5175 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5176 BNX2X_STATE_OPEN):
5177 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5178 BNX2X_STATE_DIAG):
5179 case (EVENT_RING_OPCODE_MULTICAST_RULES |
5180 BNX2X_STATE_CLOSING_WAIT4_HALT):
5181 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
5182 bnx2x_handle_mcast_eqe(bp);
5183 break;
5184
5185 case (EVENT_RING_OPCODE_FILTERS_RULES |
5186 BNX2X_STATE_OPEN):
5187 case (EVENT_RING_OPCODE_FILTERS_RULES |
5188 BNX2X_STATE_DIAG):
5189 case (EVENT_RING_OPCODE_FILTERS_RULES |
5190 BNX2X_STATE_CLOSING_WAIT4_HALT):
5191 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
5192 bnx2x_handle_rx_mode_eqe(bp);
5193 break;
5194 default:
5195 /* unknown event log error and continue */
5196 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5197 elem->message.opcode, bp->state);
5198 }
5199 next_spqe:
5200 spqe_cnt++;
5201 } /* for */
5202
5203 smp_mb__before_atomic_inc();
5204 atomic_add(spqe_cnt, &bp->eq_spq_left);
5205
5206 bp->eq_cons = sw_cons;
5207 bp->eq_prod = sw_prod;
5208 /* Make sure that above mem writes were issued towards the memory */
5209 smp_wmb();
5210
5211 /* update producer */
5212 bnx2x_update_eq_prod(bp, bp->eq_prod);
5213 }
5214
5215 static void bnx2x_sp_task(struct work_struct *work)
5216 {
5217 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
5218
5219 DP(BNX2X_MSG_SP, "sp task invoked\n");
5220
5221 /* make sure the atomic interupt_occurred has been written */
5222 smp_rmb();
5223 if (atomic_read(&bp->interrupt_occurred)) {
5224
5225 /* what work needs to be performed? */
5226 u16 status = bnx2x_update_dsb_idx(bp);
5227
5228 DP(BNX2X_MSG_SP, "status %x\n", status);
5229 DP(BNX2X_MSG_SP, "setting interrupt_occurred to 0\n");
5230 atomic_set(&bp->interrupt_occurred, 0);
5231
5232 /* HW attentions */
5233 if (status & BNX2X_DEF_SB_ATT_IDX) {
5234 bnx2x_attn_int(bp);
5235 status &= ~BNX2X_DEF_SB_ATT_IDX;
5236 }
5237
5238 /* SP events: STAT_QUERY and others */
5239 if (status & BNX2X_DEF_SB_IDX) {
5240 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5241
5242 if (FCOE_INIT(bp) &&
5243 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5244 /* Prevent local bottom-halves from running as
5245 * we are going to change the local NAPI list.
5246 */
5247 local_bh_disable();
5248 napi_schedule(&bnx2x_fcoe(bp, napi));
5249 local_bh_enable();
5250 }
5251
5252 /* Handle EQ completions */
5253 bnx2x_eq_int(bp);
5254 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5255 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5256
5257 status &= ~BNX2X_DEF_SB_IDX;
5258 }
5259
5260 /* if status is non zero then perhaps something went wrong */
5261 if (unlikely(status))
5262 DP(BNX2X_MSG_SP,
5263 "got an unknown interrupt! (status 0x%x)\n", status);
5264
5265 /* ack status block only if something was actually handled */
5266 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5267 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5268
5269 }
5270
5271 /* must be called after the EQ processing (since eq leads to sriov
5272 * ramrod completion flows).
5273 * This flow may have been scheduled by the arrival of a ramrod
5274 * completion, or by the sriov code rescheduling itself.
5275 */
5276 bnx2x_iov_sp_task(bp);
5277
5278 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5279 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5280 &bp->sp_state)) {
5281 bnx2x_link_report(bp);
5282 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5283 }
5284 }
5285
5286 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5287 {
5288 struct net_device *dev = dev_instance;
5289 struct bnx2x *bp = netdev_priv(dev);
5290
5291 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5292 IGU_INT_DISABLE, 0);
5293
5294 #ifdef BNX2X_STOP_ON_ERROR
5295 if (unlikely(bp->panic))
5296 return IRQ_HANDLED;
5297 #endif
5298
5299 if (CNIC_LOADED(bp)) {
5300 struct cnic_ops *c_ops;
5301
5302 rcu_read_lock();
5303 c_ops = rcu_dereference(bp->cnic_ops);
5304 if (c_ops)
5305 c_ops->cnic_handler(bp->cnic_data, NULL);
5306 rcu_read_unlock();
5307 }
5308
5309 /* schedule sp task to perform default status block work, ack
5310 * attentions and enable interrupts.
5311 */
5312 bnx2x_schedule_sp_task(bp);
5313
5314 return IRQ_HANDLED;
5315 }
5316
5317 /* end of slow path */
5318
5319
5320 void bnx2x_drv_pulse(struct bnx2x *bp)
5321 {
5322 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5323 bp->fw_drv_pulse_wr_seq);
5324 }
5325
5326 static void bnx2x_timer(unsigned long data)
5327 {
5328 struct bnx2x *bp = (struct bnx2x *) data;
5329
5330 if (!netif_running(bp->dev))
5331 return;
5332
5333 if (IS_PF(bp) &&
5334 !BP_NOMCP(bp)) {
5335 int mb_idx = BP_FW_MB_IDX(bp);
5336 u32 drv_pulse;
5337 u32 mcp_pulse;
5338
5339 ++bp->fw_drv_pulse_wr_seq;
5340 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5341 /* TBD - add SYSTEM_TIME */
5342 drv_pulse = bp->fw_drv_pulse_wr_seq;
5343 bnx2x_drv_pulse(bp);
5344
5345 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5346 MCP_PULSE_SEQ_MASK);
5347 /* The delta between driver pulse and mcp response
5348 * should be 1 (before mcp response) or 0 (after mcp response)
5349 */
5350 if ((drv_pulse != mcp_pulse) &&
5351 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5352 /* someone lost a heartbeat... */
5353 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5354 drv_pulse, mcp_pulse);
5355 }
5356 }
5357
5358 if (bp->state == BNX2X_STATE_OPEN)
5359 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5360
5361 /* sample pf vf bulletin board for new posts from pf */
5362 if (IS_VF(bp))
5363 bnx2x_sample_bulletin(bp);
5364
5365 mod_timer(&bp->timer, jiffies + bp->current_interval);
5366 }
5367
5368 /* end of Statistics */
5369
5370 /* nic init */
5371
5372 /*
5373 * nic init service functions
5374 */
5375
5376 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5377 {
5378 u32 i;
5379 if (!(len%4) && !(addr%4))
5380 for (i = 0; i < len; i += 4)
5381 REG_WR(bp, addr + i, fill);
5382 else
5383 for (i = 0; i < len; i++)
5384 REG_WR8(bp, addr + i, fill);
5385
5386 }
5387
5388 /* helper: writes FP SP data to FW - data_size in dwords */
5389 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5390 int fw_sb_id,
5391 u32 *sb_data_p,
5392 u32 data_size)
5393 {
5394 int index;
5395 for (index = 0; index < data_size; index++)
5396 REG_WR(bp, BAR_CSTRORM_INTMEM +
5397 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5398 sizeof(u32)*index,
5399 *(sb_data_p + index));
5400 }
5401
5402 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5403 {
5404 u32 *sb_data_p;
5405 u32 data_size = 0;
5406 struct hc_status_block_data_e2 sb_data_e2;
5407 struct hc_status_block_data_e1x sb_data_e1x;
5408
5409 /* disable the function first */
5410 if (!CHIP_IS_E1x(bp)) {
5411 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5412 sb_data_e2.common.state = SB_DISABLED;
5413 sb_data_e2.common.p_func.vf_valid = false;
5414 sb_data_p = (u32 *)&sb_data_e2;
5415 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5416 } else {
5417 memset(&sb_data_e1x, 0,
5418 sizeof(struct hc_status_block_data_e1x));
5419 sb_data_e1x.common.state = SB_DISABLED;
5420 sb_data_e1x.common.p_func.vf_valid = false;
5421 sb_data_p = (u32 *)&sb_data_e1x;
5422 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5423 }
5424 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5425
5426 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5427 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5428 CSTORM_STATUS_BLOCK_SIZE);
5429 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5430 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5431 CSTORM_SYNC_BLOCK_SIZE);
5432 }
5433
5434 /* helper: writes SP SB data to FW */
5435 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5436 struct hc_sp_status_block_data *sp_sb_data)
5437 {
5438 int func = BP_FUNC(bp);
5439 int i;
5440 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5441 REG_WR(bp, BAR_CSTRORM_INTMEM +
5442 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5443 i*sizeof(u32),
5444 *((u32 *)sp_sb_data + i));
5445 }
5446
5447 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5448 {
5449 int func = BP_FUNC(bp);
5450 struct hc_sp_status_block_data sp_sb_data;
5451 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5452
5453 sp_sb_data.state = SB_DISABLED;
5454 sp_sb_data.p_func.vf_valid = false;
5455
5456 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5457
5458 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5459 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5460 CSTORM_SP_STATUS_BLOCK_SIZE);
5461 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5462 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5463 CSTORM_SP_SYNC_BLOCK_SIZE);
5464
5465 }
5466
5467
5468 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5469 int igu_sb_id, int igu_seg_id)
5470 {
5471 hc_sm->igu_sb_id = igu_sb_id;
5472 hc_sm->igu_seg_id = igu_seg_id;
5473 hc_sm->timer_value = 0xFF;
5474 hc_sm->time_to_expire = 0xFFFFFFFF;
5475 }
5476
5477
5478 /* allocates state machine ids. */
5479 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5480 {
5481 /* zero out state machine indices */
5482 /* rx indices */
5483 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5484
5485 /* tx indices */
5486 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5487 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5488 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5489 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5490
5491 /* map indices */
5492 /* rx indices */
5493 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5494 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5495
5496 /* tx indices */
5497 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5498 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5499 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5500 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5501 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5502 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5503 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5504 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5505 }
5506
5507 void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5508 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5509 {
5510 int igu_seg_id;
5511
5512 struct hc_status_block_data_e2 sb_data_e2;
5513 struct hc_status_block_data_e1x sb_data_e1x;
5514 struct hc_status_block_sm *hc_sm_p;
5515 int data_size;
5516 u32 *sb_data_p;
5517
5518 if (CHIP_INT_MODE_IS_BC(bp))
5519 igu_seg_id = HC_SEG_ACCESS_NORM;
5520 else
5521 igu_seg_id = IGU_SEG_ACCESS_NORM;
5522
5523 bnx2x_zero_fp_sb(bp, fw_sb_id);
5524
5525 if (!CHIP_IS_E1x(bp)) {
5526 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5527 sb_data_e2.common.state = SB_ENABLED;
5528 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5529 sb_data_e2.common.p_func.vf_id = vfid;
5530 sb_data_e2.common.p_func.vf_valid = vf_valid;
5531 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5532 sb_data_e2.common.same_igu_sb_1b = true;
5533 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5534 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5535 hc_sm_p = sb_data_e2.common.state_machine;
5536 sb_data_p = (u32 *)&sb_data_e2;
5537 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5538 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5539 } else {
5540 memset(&sb_data_e1x, 0,
5541 sizeof(struct hc_status_block_data_e1x));
5542 sb_data_e1x.common.state = SB_ENABLED;
5543 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5544 sb_data_e1x.common.p_func.vf_id = 0xff;
5545 sb_data_e1x.common.p_func.vf_valid = false;
5546 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5547 sb_data_e1x.common.same_igu_sb_1b = true;
5548 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5549 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5550 hc_sm_p = sb_data_e1x.common.state_machine;
5551 sb_data_p = (u32 *)&sb_data_e1x;
5552 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5553 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5554 }
5555
5556 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5557 igu_sb_id, igu_seg_id);
5558 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5559 igu_sb_id, igu_seg_id);
5560
5561 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5562
5563 /* write indices to HW - PCI guarantees endianity of regpairs */
5564 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5565 }
5566
5567 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5568 u16 tx_usec, u16 rx_usec)
5569 {
5570 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5571 false, rx_usec);
5572 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5573 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5574 tx_usec);
5575 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5576 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5577 tx_usec);
5578 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5579 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5580 tx_usec);
5581 }
5582
5583 static void bnx2x_init_def_sb(struct bnx2x *bp)
5584 {
5585 struct host_sp_status_block *def_sb = bp->def_status_blk;
5586 dma_addr_t mapping = bp->def_status_blk_mapping;
5587 int igu_sp_sb_index;
5588 int igu_seg_id;
5589 int port = BP_PORT(bp);
5590 int func = BP_FUNC(bp);
5591 int reg_offset, reg_offset_en5;
5592 u64 section;
5593 int index;
5594 struct hc_sp_status_block_data sp_sb_data;
5595 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5596
5597 if (CHIP_INT_MODE_IS_BC(bp)) {
5598 igu_sp_sb_index = DEF_SB_IGU_ID;
5599 igu_seg_id = HC_SEG_ACCESS_DEF;
5600 } else {
5601 igu_sp_sb_index = bp->igu_dsb_id;
5602 igu_seg_id = IGU_SEG_ACCESS_DEF;
5603 }
5604
5605 /* ATTN */
5606 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5607 atten_status_block);
5608 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5609
5610 bp->attn_state = 0;
5611
5612 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5613 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5614 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5615 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5616 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5617 int sindex;
5618 /* take care of sig[0]..sig[4] */
5619 for (sindex = 0; sindex < 4; sindex++)
5620 bp->attn_group[index].sig[sindex] =
5621 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5622
5623 if (!CHIP_IS_E1x(bp))
5624 /*
5625 * enable5 is separate from the rest of the registers,
5626 * and therefore the address skip is 4
5627 * and not 16 between the different groups
5628 */
5629 bp->attn_group[index].sig[4] = REG_RD(bp,
5630 reg_offset_en5 + 0x4*index);
5631 else
5632 bp->attn_group[index].sig[4] = 0;
5633 }
5634
5635 if (bp->common.int_block == INT_BLOCK_HC) {
5636 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5637 HC_REG_ATTN_MSG0_ADDR_L);
5638
5639 REG_WR(bp, reg_offset, U64_LO(section));
5640 REG_WR(bp, reg_offset + 4, U64_HI(section));
5641 } else if (!CHIP_IS_E1x(bp)) {
5642 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5643 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5644 }
5645
5646 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5647 sp_sb);
5648
5649 bnx2x_zero_sp_sb(bp);
5650
5651 /* PCI guarantees endianity of regpairs */
5652 sp_sb_data.state = SB_ENABLED;
5653 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5654 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5655 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5656 sp_sb_data.igu_seg_id = igu_seg_id;
5657 sp_sb_data.p_func.pf_id = func;
5658 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5659 sp_sb_data.p_func.vf_id = 0xff;
5660
5661 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5662
5663 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5664 }
5665
5666 void bnx2x_update_coalesce(struct bnx2x *bp)
5667 {
5668 int i;
5669
5670 for_each_eth_queue(bp, i)
5671 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5672 bp->tx_ticks, bp->rx_ticks);
5673 }
5674
5675 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5676 {
5677 spin_lock_init(&bp->spq_lock);
5678 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5679
5680 bp->spq_prod_idx = 0;
5681 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5682 bp->spq_prod_bd = bp->spq;
5683 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5684 }
5685
5686 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5687 {
5688 int i;
5689 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5690 union event_ring_elem *elem =
5691 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5692
5693 elem->next_page.addr.hi =
5694 cpu_to_le32(U64_HI(bp->eq_mapping +
5695 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5696 elem->next_page.addr.lo =
5697 cpu_to_le32(U64_LO(bp->eq_mapping +
5698 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5699 }
5700 bp->eq_cons = 0;
5701 bp->eq_prod = NUM_EQ_DESC;
5702 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5703 /* we want a warning message before it gets rought... */
5704 atomic_set(&bp->eq_spq_left,
5705 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5706 }
5707
5708 /* called with netif_addr_lock_bh() */
5709 int bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5710 unsigned long rx_mode_flags,
5711 unsigned long rx_accept_flags,
5712 unsigned long tx_accept_flags,
5713 unsigned long ramrod_flags)
5714 {
5715 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5716 int rc;
5717
5718 memset(&ramrod_param, 0, sizeof(ramrod_param));
5719
5720 /* Prepare ramrod parameters */
5721 ramrod_param.cid = 0;
5722 ramrod_param.cl_id = cl_id;
5723 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5724 ramrod_param.func_id = BP_FUNC(bp);
5725
5726 ramrod_param.pstate = &bp->sp_state;
5727 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5728
5729 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5730 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5731
5732 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5733
5734 ramrod_param.ramrod_flags = ramrod_flags;
5735 ramrod_param.rx_mode_flags = rx_mode_flags;
5736
5737 ramrod_param.rx_accept_flags = rx_accept_flags;
5738 ramrod_param.tx_accept_flags = tx_accept_flags;
5739
5740 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5741 if (rc < 0) {
5742 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5743 return rc;
5744 }
5745
5746 return 0;
5747 }
5748
5749 static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
5750 unsigned long *rx_accept_flags,
5751 unsigned long *tx_accept_flags)
5752 {
5753 /* Clear the flags first */
5754 *rx_accept_flags = 0;
5755 *tx_accept_flags = 0;
5756
5757 switch (rx_mode) {
5758 case BNX2X_RX_MODE_NONE:
5759 /*
5760 * 'drop all' supersedes any accept flags that may have been
5761 * passed to the function.
5762 */
5763 break;
5764 case BNX2X_RX_MODE_NORMAL:
5765 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5766 __set_bit(BNX2X_ACCEPT_MULTICAST, rx_accept_flags);
5767 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5768
5769 /* internal switching mode */
5770 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5771 __set_bit(BNX2X_ACCEPT_MULTICAST, tx_accept_flags);
5772 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5773
5774 break;
5775 case BNX2X_RX_MODE_ALLMULTI:
5776 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5777 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5778 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5779
5780 /* internal switching mode */
5781 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5782 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5783 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5784
5785 break;
5786 case BNX2X_RX_MODE_PROMISC:
5787 /* According to deffinition of SI mode, iface in promisc mode
5788 * should receive matched and unmatched (in resolution of port)
5789 * unicast packets.
5790 */
5791 __set_bit(BNX2X_ACCEPT_UNMATCHED, rx_accept_flags);
5792 __set_bit(BNX2X_ACCEPT_UNICAST, rx_accept_flags);
5793 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, rx_accept_flags);
5794 __set_bit(BNX2X_ACCEPT_BROADCAST, rx_accept_flags);
5795
5796 /* internal switching mode */
5797 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, tx_accept_flags);
5798 __set_bit(BNX2X_ACCEPT_BROADCAST, tx_accept_flags);
5799
5800 if (IS_MF_SI(bp))
5801 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, tx_accept_flags);
5802 else
5803 __set_bit(BNX2X_ACCEPT_UNICAST, tx_accept_flags);
5804
5805 break;
5806 default:
5807 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode);
5808 return -EINVAL;
5809 }
5810
5811 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
5812 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5813 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
5814 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
5815 }
5816
5817 return 0;
5818 }
5819
5820 /* called with netif_addr_lock_bh() */
5821 int bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5822 {
5823 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5824 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5825 int rc;
5826
5827 if (!NO_FCOE(bp))
5828 /* Configure rx_mode of FCoE Queue */
5829 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5830
5831 rc = bnx2x_fill_accept_flags(bp, bp->rx_mode, &rx_accept_flags,
5832 &tx_accept_flags);
5833 if (rc)
5834 return rc;
5835
5836 __set_bit(RAMROD_RX, &ramrod_flags);
5837 __set_bit(RAMROD_TX, &ramrod_flags);
5838
5839 return bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags,
5840 rx_accept_flags, tx_accept_flags,
5841 ramrod_flags);
5842 }
5843
5844 static void bnx2x_init_internal_common(struct bnx2x *bp)
5845 {
5846 int i;
5847
5848 if (IS_MF_SI(bp))
5849 /*
5850 * In switch independent mode, the TSTORM needs to accept
5851 * packets that failed classification, since approximate match
5852 * mac addresses aren't written to NIG LLH
5853 */
5854 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5855 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5856 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5857 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5858 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5859
5860 /* Zero this manually as its initialization is
5861 currently missing in the initTool */
5862 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5863 REG_WR(bp, BAR_USTRORM_INTMEM +
5864 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5865 if (!CHIP_IS_E1x(bp)) {
5866 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5867 CHIP_INT_MODE_IS_BC(bp) ?
5868 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5869 }
5870 }
5871
5872 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5873 {
5874 switch (load_code) {
5875 case FW_MSG_CODE_DRV_LOAD_COMMON:
5876 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5877 bnx2x_init_internal_common(bp);
5878 /* no break */
5879
5880 case FW_MSG_CODE_DRV_LOAD_PORT:
5881 /* nothing to do */
5882 /* no break */
5883
5884 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5885 /* internal memory per function is
5886 initialized inside bnx2x_pf_init */
5887 break;
5888
5889 default:
5890 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5891 break;
5892 }
5893 }
5894
5895 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5896 {
5897 return fp->bp->igu_base_sb + fp->index + CNIC_SUPPORT(fp->bp);
5898 }
5899
5900 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5901 {
5902 return fp->bp->base_fw_ndsb + fp->index + CNIC_SUPPORT(fp->bp);
5903 }
5904
5905 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5906 {
5907 if (CHIP_IS_E1x(fp->bp))
5908 return BP_L_ID(fp->bp) + fp->index;
5909 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5910 return bnx2x_fp_igu_sb_id(fp);
5911 }
5912
5913 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5914 {
5915 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5916 u8 cos;
5917 unsigned long q_type = 0;
5918 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5919 fp->rx_queue = fp_idx;
5920 fp->cid = fp_idx;
5921 fp->cl_id = bnx2x_fp_cl_id(fp);
5922 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5923 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5924 /* qZone id equals to FW (per path) client id */
5925 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5926
5927 /* init shortcut */
5928 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5929
5930 /* Setup SB indicies */
5931 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5932
5933 /* Configure Queue State object */
5934 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5935 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5936
5937 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5938
5939 /* init tx data */
5940 for_each_cos_in_tx_queue(fp, cos) {
5941 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5942 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5943 FP_COS_TO_TXQ(fp, cos, bp),
5944 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5945 cids[cos] = fp->txdata_ptr[cos]->cid;
5946 }
5947
5948 /* nothing more for vf to do here */
5949 if (IS_VF(bp))
5950 return;
5951
5952 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5953 fp->fw_sb_id, fp->igu_sb_id);
5954 bnx2x_update_fpsb_idx(fp);
5955 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5956 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5957 bnx2x_sp_mapping(bp, q_rdata), q_type);
5958
5959 /**
5960 * Configure classification DBs: Always enable Tx switching
5961 */
5962 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5963
5964 DP(NETIF_MSG_IFUP,
5965 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5966 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5967 fp->igu_sb_id);
5968 }
5969
5970 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5971 {
5972 int i;
5973
5974 for (i = 1; i <= NUM_TX_RINGS; i++) {
5975 struct eth_tx_next_bd *tx_next_bd =
5976 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5977
5978 tx_next_bd->addr_hi =
5979 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5980 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5981 tx_next_bd->addr_lo =
5982 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5983 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5984 }
5985
5986 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5987 txdata->tx_db.data.zero_fill1 = 0;
5988 txdata->tx_db.data.prod = 0;
5989
5990 txdata->tx_pkt_prod = 0;
5991 txdata->tx_pkt_cons = 0;
5992 txdata->tx_bd_prod = 0;
5993 txdata->tx_bd_cons = 0;
5994 txdata->tx_pkt = 0;
5995 }
5996
5997 static void bnx2x_init_tx_rings_cnic(struct bnx2x *bp)
5998 {
5999 int i;
6000
6001 for_each_tx_queue_cnic(bp, i)
6002 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[0]);
6003 }
6004 static void bnx2x_init_tx_rings(struct bnx2x *bp)
6005 {
6006 int i;
6007 u8 cos;
6008
6009 for_each_eth_queue(bp, i)
6010 for_each_cos_in_tx_queue(&bp->fp[i], cos)
6011 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
6012 }
6013
6014 void bnx2x_nic_init_cnic(struct bnx2x *bp)
6015 {
6016 if (!NO_FCOE(bp))
6017 bnx2x_init_fcoe_fp(bp);
6018
6019 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
6020 BNX2X_VF_ID_INVALID, false,
6021 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
6022
6023 /* ensure status block indices were read */
6024 rmb();
6025 bnx2x_init_rx_rings_cnic(bp);
6026 bnx2x_init_tx_rings_cnic(bp);
6027
6028 /* flush all */
6029 mb();
6030 mmiowb();
6031 }
6032
6033 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
6034 {
6035 int i;
6036
6037 for_each_eth_queue(bp, i)
6038 bnx2x_init_eth_fp(bp, i);
6039
6040 /* ensure status block indices were read */
6041 rmb();
6042 bnx2x_init_rx_rings(bp);
6043 bnx2x_init_tx_rings(bp);
6044 if (IS_VF(bp)) {
6045 bnx2x_memset_stats(bp);
6046 return;
6047 }
6048
6049 /* Initialize MOD_ABS interrupts */
6050 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
6051 bp->common.shmem_base, bp->common.shmem2_base,
6052 BP_PORT(bp));
6053
6054 bnx2x_init_def_sb(bp);
6055 bnx2x_update_dsb_idx(bp);
6056 bnx2x_init_sp_ring(bp);
6057 bnx2x_init_eq_ring(bp);
6058 bnx2x_init_internal(bp, load_code);
6059 bnx2x_pf_init(bp);
6060 bnx2x_stats_init(bp);
6061
6062 /* flush all before enabling interrupts */
6063 mb();
6064 mmiowb();
6065
6066 bnx2x_int_enable(bp);
6067
6068 /* Check for SPIO5 */
6069 bnx2x_attn_int_deasserted0(bp,
6070 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
6071 AEU_INPUTS_ATTN_BITS_SPIO5);
6072 }
6073
6074 /* end of nic init */
6075
6076 /*
6077 * gzip service functions
6078 */
6079
6080 static int bnx2x_gunzip_init(struct bnx2x *bp)
6081 {
6082 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
6083 &bp->gunzip_mapping, GFP_KERNEL);
6084 if (bp->gunzip_buf == NULL)
6085 goto gunzip_nomem1;
6086
6087 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
6088 if (bp->strm == NULL)
6089 goto gunzip_nomem2;
6090
6091 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
6092 if (bp->strm->workspace == NULL)
6093 goto gunzip_nomem3;
6094
6095 return 0;
6096
6097 gunzip_nomem3:
6098 kfree(bp->strm);
6099 bp->strm = NULL;
6100
6101 gunzip_nomem2:
6102 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6103 bp->gunzip_mapping);
6104 bp->gunzip_buf = NULL;
6105
6106 gunzip_nomem1:
6107 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6108 return -ENOMEM;
6109 }
6110
6111 static void bnx2x_gunzip_end(struct bnx2x *bp)
6112 {
6113 if (bp->strm) {
6114 vfree(bp->strm->workspace);
6115 kfree(bp->strm);
6116 bp->strm = NULL;
6117 }
6118
6119 if (bp->gunzip_buf) {
6120 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
6121 bp->gunzip_mapping);
6122 bp->gunzip_buf = NULL;
6123 }
6124 }
6125
6126 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
6127 {
6128 int n, rc;
6129
6130 /* check gzip header */
6131 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
6132 BNX2X_ERR("Bad gzip header\n");
6133 return -EINVAL;
6134 }
6135
6136 n = 10;
6137
6138 #define FNAME 0x8
6139
6140 if (zbuf[3] & FNAME)
6141 while ((zbuf[n++] != 0) && (n < len));
6142
6143 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
6144 bp->strm->avail_in = len - n;
6145 bp->strm->next_out = bp->gunzip_buf;
6146 bp->strm->avail_out = FW_BUF_SIZE;
6147
6148 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
6149 if (rc != Z_OK)
6150 return rc;
6151
6152 rc = zlib_inflate(bp->strm, Z_FINISH);
6153 if ((rc != Z_OK) && (rc != Z_STREAM_END))
6154 netdev_err(bp->dev, "Firmware decompression error: %s\n",
6155 bp->strm->msg);
6156
6157 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
6158 if (bp->gunzip_outlen & 0x3)
6159 netdev_err(bp->dev,
6160 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6161 bp->gunzip_outlen);
6162 bp->gunzip_outlen >>= 2;
6163
6164 zlib_inflateEnd(bp->strm);
6165
6166 if (rc == Z_STREAM_END)
6167 return 0;
6168
6169 return rc;
6170 }
6171
6172 /* nic load/unload */
6173
6174 /*
6175 * General service functions
6176 */
6177
6178 /* send a NIG loopback debug packet */
6179 static void bnx2x_lb_pckt(struct bnx2x *bp)
6180 {
6181 u32 wb_write[3];
6182
6183 /* Ethernet source and destination addresses */
6184 wb_write[0] = 0x55555555;
6185 wb_write[1] = 0x55555555;
6186 wb_write[2] = 0x20; /* SOP */
6187 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6188
6189 /* NON-IP protocol */
6190 wb_write[0] = 0x09000000;
6191 wb_write[1] = 0x55555555;
6192 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
6193 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
6194 }
6195
6196 /* some of the internal memories
6197 * are not directly readable from the driver
6198 * to test them we send debug packets
6199 */
6200 static int bnx2x_int_mem_test(struct bnx2x *bp)
6201 {
6202 int factor;
6203 int count, i;
6204 u32 val = 0;
6205
6206 if (CHIP_REV_IS_FPGA(bp))
6207 factor = 120;
6208 else if (CHIP_REV_IS_EMUL(bp))
6209 factor = 200;
6210 else
6211 factor = 1;
6212
6213 /* Disable inputs of parser neighbor blocks */
6214 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6215 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6216 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6217 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6218
6219 /* Write 0 to parser credits for CFC search request */
6220 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6221
6222 /* send Ethernet packet */
6223 bnx2x_lb_pckt(bp);
6224
6225 /* TODO do i reset NIG statistic? */
6226 /* Wait until NIG register shows 1 packet of size 0x10 */
6227 count = 1000 * factor;
6228 while (count) {
6229
6230 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6231 val = *bnx2x_sp(bp, wb_data[0]);
6232 if (val == 0x10)
6233 break;
6234
6235 msleep(10);
6236 count--;
6237 }
6238 if (val != 0x10) {
6239 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6240 return -1;
6241 }
6242
6243 /* Wait until PRS register shows 1 packet */
6244 count = 1000 * factor;
6245 while (count) {
6246 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6247 if (val == 1)
6248 break;
6249
6250 msleep(10);
6251 count--;
6252 }
6253 if (val != 0x1) {
6254 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6255 return -2;
6256 }
6257
6258 /* Reset and init BRB, PRS */
6259 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6260 msleep(50);
6261 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6262 msleep(50);
6263 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6264 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6265
6266 DP(NETIF_MSG_HW, "part2\n");
6267
6268 /* Disable inputs of parser neighbor blocks */
6269 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
6270 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
6271 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
6272 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
6273
6274 /* Write 0 to parser credits for CFC search request */
6275 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
6276
6277 /* send 10 Ethernet packets */
6278 for (i = 0; i < 10; i++)
6279 bnx2x_lb_pckt(bp);
6280
6281 /* Wait until NIG register shows 10 + 1
6282 packets of size 11*0x10 = 0xb0 */
6283 count = 1000 * factor;
6284 while (count) {
6285
6286 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6287 val = *bnx2x_sp(bp, wb_data[0]);
6288 if (val == 0xb0)
6289 break;
6290
6291 msleep(10);
6292 count--;
6293 }
6294 if (val != 0xb0) {
6295 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6296 return -3;
6297 }
6298
6299 /* Wait until PRS register shows 2 packets */
6300 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6301 if (val != 2)
6302 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6303
6304 /* Write 1 to parser credits for CFC search request */
6305 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6306
6307 /* Wait until PRS register shows 3 packets */
6308 msleep(10 * factor);
6309 /* Wait until NIG register shows 1 packet of size 0x10 */
6310 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6311 if (val != 3)
6312 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6313
6314 /* clear NIG EOP FIFO */
6315 for (i = 0; i < 11; i++)
6316 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6317 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6318 if (val != 1) {
6319 BNX2X_ERR("clear of NIG failed\n");
6320 return -4;
6321 }
6322
6323 /* Reset and init BRB, PRS, NIG */
6324 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6325 msleep(50);
6326 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6327 msleep(50);
6328 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6329 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6330 if (!CNIC_SUPPORT(bp))
6331 /* set NIC mode */
6332 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6333
6334 /* Enable inputs of parser neighbor blocks */
6335 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6336 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6337 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6338 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6339
6340 DP(NETIF_MSG_HW, "done\n");
6341
6342 return 0; /* OK */
6343 }
6344
6345 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6346 {
6347 u32 val;
6348
6349 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6350 if (!CHIP_IS_E1x(bp))
6351 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6352 else
6353 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6354 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6355 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6356 /*
6357 * mask read length error interrupts in brb for parser
6358 * (parsing unit and 'checksum and crc' unit)
6359 * these errors are legal (PU reads fixed length and CAC can cause
6360 * read length error on truncated packets)
6361 */
6362 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6363 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6364 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6365 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6366 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6367 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6368 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6369 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6370 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6371 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6372 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6373 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6374 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6375 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6376 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6377 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6378 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6379 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6380 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6381
6382 val = PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT |
6383 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF |
6384 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN;
6385 if (!CHIP_IS_E1x(bp))
6386 val |= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED |
6387 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED;
6388 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, val);
6389
6390 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6391 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6392 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6393 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6394
6395 if (!CHIP_IS_E1x(bp))
6396 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6397 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6398
6399 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6400 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6401 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6402 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6403 }
6404
6405 static void bnx2x_reset_common(struct bnx2x *bp)
6406 {
6407 u32 val = 0x1400;
6408
6409 /* reset_common */
6410 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6411 0xd3ffff7f);
6412
6413 if (CHIP_IS_E3(bp)) {
6414 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6415 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6416 }
6417
6418 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6419 }
6420
6421 static void bnx2x_setup_dmae(struct bnx2x *bp)
6422 {
6423 bp->dmae_ready = 0;
6424 spin_lock_init(&bp->dmae_lock);
6425 }
6426
6427 static void bnx2x_init_pxp(struct bnx2x *bp)
6428 {
6429 u16 devctl;
6430 int r_order, w_order;
6431
6432 pcie_capability_read_word(bp->pdev, PCI_EXP_DEVCTL, &devctl);
6433 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6434 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6435 if (bp->mrrs == -1)
6436 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6437 else {
6438 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6439 r_order = bp->mrrs;
6440 }
6441
6442 bnx2x_init_pxp_arb(bp, r_order, w_order);
6443 }
6444
6445 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6446 {
6447 int is_required;
6448 u32 val;
6449 int port;
6450
6451 if (BP_NOMCP(bp))
6452 return;
6453
6454 is_required = 0;
6455 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6456 SHARED_HW_CFG_FAN_FAILURE_MASK;
6457
6458 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6459 is_required = 1;
6460
6461 /*
6462 * The fan failure mechanism is usually related to the PHY type since
6463 * the power consumption of the board is affected by the PHY. Currently,
6464 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6465 */
6466 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6467 for (port = PORT_0; port < PORT_MAX; port++) {
6468 is_required |=
6469 bnx2x_fan_failure_det_req(
6470 bp,
6471 bp->common.shmem_base,
6472 bp->common.shmem2_base,
6473 port);
6474 }
6475
6476 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6477
6478 if (is_required == 0)
6479 return;
6480
6481 /* Fan failure is indicated by SPIO 5 */
6482 bnx2x_set_spio(bp, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z);
6483
6484 /* set to active low mode */
6485 val = REG_RD(bp, MISC_REG_SPIO_INT);
6486 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS);
6487 REG_WR(bp, MISC_REG_SPIO_INT, val);
6488
6489 /* enable interrupt to signal the IGU */
6490 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6491 val |= MISC_SPIO_SPIO5;
6492 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6493 }
6494
6495 void bnx2x_pf_disable(struct bnx2x *bp)
6496 {
6497 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6498 val &= ~IGU_PF_CONF_FUNC_EN;
6499
6500 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6501 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6502 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6503 }
6504
6505 static void bnx2x__common_init_phy(struct bnx2x *bp)
6506 {
6507 u32 shmem_base[2], shmem2_base[2];
6508 /* Avoid common init in case MFW supports LFA */
6509 if (SHMEM2_RD(bp, size) >
6510 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
6511 return;
6512 shmem_base[0] = bp->common.shmem_base;
6513 shmem2_base[0] = bp->common.shmem2_base;
6514 if (!CHIP_IS_E1x(bp)) {
6515 shmem_base[1] =
6516 SHMEM2_RD(bp, other_shmem_base_addr);
6517 shmem2_base[1] =
6518 SHMEM2_RD(bp, other_shmem2_base_addr);
6519 }
6520 bnx2x_acquire_phy_lock(bp);
6521 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6522 bp->common.chip_id);
6523 bnx2x_release_phy_lock(bp);
6524 }
6525
6526 /**
6527 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6528 *
6529 * @bp: driver handle
6530 */
6531 static int bnx2x_init_hw_common(struct bnx2x *bp)
6532 {
6533 u32 val;
6534
6535 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6536
6537 /*
6538 * take the RESET lock to protect undi_unload flow from accessing
6539 * registers while we're resetting the chip
6540 */
6541 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6542
6543 bnx2x_reset_common(bp);
6544 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6545
6546 val = 0xfffc;
6547 if (CHIP_IS_E3(bp)) {
6548 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6549 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6550 }
6551 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6552
6553 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6554
6555 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6556
6557 if (!CHIP_IS_E1x(bp)) {
6558 u8 abs_func_id;
6559
6560 /**
6561 * 4-port mode or 2-port mode we need to turn of master-enable
6562 * for everyone, after that, turn it back on for self.
6563 * so, we disregard multi-function or not, and always disable
6564 * for all functions on the given path, this means 0,2,4,6 for
6565 * path 0 and 1,3,5,7 for path 1
6566 */
6567 for (abs_func_id = BP_PATH(bp);
6568 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6569 if (abs_func_id == BP_ABS_FUNC(bp)) {
6570 REG_WR(bp,
6571 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6572 1);
6573 continue;
6574 }
6575
6576 bnx2x_pretend_func(bp, abs_func_id);
6577 /* clear pf enable */
6578 bnx2x_pf_disable(bp);
6579 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6580 }
6581 }
6582
6583 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6584 if (CHIP_IS_E1(bp)) {
6585 /* enable HW interrupt from PXP on USDM overflow
6586 bit 16 on INT_MASK_0 */
6587 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6588 }
6589
6590 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6591 bnx2x_init_pxp(bp);
6592
6593 #ifdef __BIG_ENDIAN
6594 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6595 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6596 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6597 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6598 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6599 /* make sure this value is 0 */
6600 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6601
6602 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6603 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6604 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6605 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6606 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6607 #endif
6608
6609 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6610
6611 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6612 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6613
6614 /* let the HW do it's magic ... */
6615 msleep(100);
6616 /* finish PXP init */
6617 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6618 if (val != 1) {
6619 BNX2X_ERR("PXP2 CFG failed\n");
6620 return -EBUSY;
6621 }
6622 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6623 if (val != 1) {
6624 BNX2X_ERR("PXP2 RD_INIT failed\n");
6625 return -EBUSY;
6626 }
6627
6628 /* Timers bug workaround E2 only. We need to set the entire ILT to
6629 * have entries with value "0" and valid bit on.
6630 * This needs to be done by the first PF that is loaded in a path
6631 * (i.e. common phase)
6632 */
6633 if (!CHIP_IS_E1x(bp)) {
6634 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6635 * (i.e. vnic3) to start even if it is marked as "scan-off".
6636 * This occurs when a different function (func2,3) is being marked
6637 * as "scan-off". Real-life scenario for example: if a driver is being
6638 * load-unloaded while func6,7 are down. This will cause the timer to access
6639 * the ilt, translate to a logical address and send a request to read/write.
6640 * Since the ilt for the function that is down is not valid, this will cause
6641 * a translation error which is unrecoverable.
6642 * The Workaround is intended to make sure that when this happens nothing fatal
6643 * will occur. The workaround:
6644 * 1. First PF driver which loads on a path will:
6645 * a. After taking the chip out of reset, by using pretend,
6646 * it will write "0" to the following registers of
6647 * the other vnics.
6648 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6649 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6650 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6651 * And for itself it will write '1' to
6652 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6653 * dmae-operations (writing to pram for example.)
6654 * note: can be done for only function 6,7 but cleaner this
6655 * way.
6656 * b. Write zero+valid to the entire ILT.
6657 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6658 * VNIC3 (of that port). The range allocated will be the
6659 * entire ILT. This is needed to prevent ILT range error.
6660 * 2. Any PF driver load flow:
6661 * a. ILT update with the physical addresses of the allocated
6662 * logical pages.
6663 * b. Wait 20msec. - note that this timeout is needed to make
6664 * sure there are no requests in one of the PXP internal
6665 * queues with "old" ILT addresses.
6666 * c. PF enable in the PGLC.
6667 * d. Clear the was_error of the PF in the PGLC. (could have
6668 * occurred while driver was down)
6669 * e. PF enable in the CFC (WEAK + STRONG)
6670 * f. Timers scan enable
6671 * 3. PF driver unload flow:
6672 * a. Clear the Timers scan_en.
6673 * b. Polling for scan_on=0 for that PF.
6674 * c. Clear the PF enable bit in the PXP.
6675 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6676 * e. Write zero+valid to all ILT entries (The valid bit must
6677 * stay set)
6678 * f. If this is VNIC 3 of a port then also init
6679 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6680 * to the last enrty in the ILT.
6681 *
6682 * Notes:
6683 * Currently the PF error in the PGLC is non recoverable.
6684 * In the future the there will be a recovery routine for this error.
6685 * Currently attention is masked.
6686 * Having an MCP lock on the load/unload process does not guarantee that
6687 * there is no Timer disable during Func6/7 enable. This is because the
6688 * Timers scan is currently being cleared by the MCP on FLR.
6689 * Step 2.d can be done only for PF6/7 and the driver can also check if
6690 * there is error before clearing it. But the flow above is simpler and
6691 * more general.
6692 * All ILT entries are written by zero+valid and not just PF6/7
6693 * ILT entries since in the future the ILT entries allocation for
6694 * PF-s might be dynamic.
6695 */
6696 struct ilt_client_info ilt_cli;
6697 struct bnx2x_ilt ilt;
6698 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6699 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6700
6701 /* initialize dummy TM client */
6702 ilt_cli.start = 0;
6703 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6704 ilt_cli.client_num = ILT_CLIENT_TM;
6705
6706 /* Step 1: set zeroes to all ilt page entries with valid bit on
6707 * Step 2: set the timers first/last ilt entry to point
6708 * to the entire range to prevent ILT range error for 3rd/4th
6709 * vnic (this code assumes existence of the vnic)
6710 *
6711 * both steps performed by call to bnx2x_ilt_client_init_op()
6712 * with dummy TM client
6713 *
6714 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6715 * and his brother are split registers
6716 */
6717 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6718 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6719 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6720
6721 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6722 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6723 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6724 }
6725
6726 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6727 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6728
6729 if (!CHIP_IS_E1x(bp)) {
6730 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6731 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6732 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6733
6734 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6735
6736 /* let the HW do it's magic ... */
6737 do {
6738 msleep(200);
6739 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6740 } while (factor-- && (val != 1));
6741
6742 if (val != 1) {
6743 BNX2X_ERR("ATC_INIT failed\n");
6744 return -EBUSY;
6745 }
6746 }
6747
6748 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6749
6750 bnx2x_iov_init_dmae(bp);
6751
6752 /* clean the DMAE memory */
6753 bp->dmae_ready = 1;
6754 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6755
6756 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6757
6758 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6759
6760 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6761
6762 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6763
6764 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6765 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6766 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6767 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6768
6769 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6770
6771
6772 /* QM queues pointers table */
6773 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6774
6775 /* soft reset pulse */
6776 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6777 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6778
6779 if (CNIC_SUPPORT(bp))
6780 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6781
6782 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6783 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6784 if (!CHIP_REV_IS_SLOW(bp))
6785 /* enable hw interrupt from doorbell Q */
6786 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6787
6788 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6789
6790 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6791 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6792
6793 if (!CHIP_IS_E1(bp))
6794 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6795
6796 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6797 if (IS_MF_AFEX(bp)) {
6798 /* configure that VNTag and VLAN headers must be
6799 * received in afex mode
6800 */
6801 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6802 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6803 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6804 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6805 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6806 } else {
6807 /* Bit-map indicating which L2 hdrs may appear
6808 * after the basic Ethernet header
6809 */
6810 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6811 bp->path_has_ovlan ? 7 : 6);
6812 }
6813 }
6814
6815 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6816 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6817 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6818 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6819
6820 if (!CHIP_IS_E1x(bp)) {
6821 /* reset VFC memories */
6822 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6823 VFC_MEMORIES_RST_REG_CAM_RST |
6824 VFC_MEMORIES_RST_REG_RAM_RST);
6825 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6826 VFC_MEMORIES_RST_REG_CAM_RST |
6827 VFC_MEMORIES_RST_REG_RAM_RST);
6828
6829 msleep(20);
6830 }
6831
6832 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6833 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6834 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6835 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6836
6837 /* sync semi rtc */
6838 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6839 0x80000000);
6840 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6841 0x80000000);
6842
6843 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6844 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6845 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6846
6847 if (!CHIP_IS_E1x(bp)) {
6848 if (IS_MF_AFEX(bp)) {
6849 /* configure that VNTag and VLAN headers must be
6850 * sent in afex mode
6851 */
6852 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6853 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6854 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6855 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6856 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6857 } else {
6858 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6859 bp->path_has_ovlan ? 7 : 6);
6860 }
6861 }
6862
6863 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6864
6865 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6866
6867 if (CNIC_SUPPORT(bp)) {
6868 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6869 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6870 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6871 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6872 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6873 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6874 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6875 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6876 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6877 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6878 }
6879 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6880
6881 if (sizeof(union cdu_context) != 1024)
6882 /* we currently assume that a context is 1024 bytes */
6883 dev_alert(&bp->pdev->dev,
6884 "please adjust the size of cdu_context(%ld)\n",
6885 (long)sizeof(union cdu_context));
6886
6887 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6888 val = (4 << 24) + (0 << 12) + 1024;
6889 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6890
6891 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6892 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6893 /* enable context validation interrupt from CFC */
6894 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6895
6896 /* set the thresholds to prevent CFC/CDU race */
6897 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6898
6899 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6900
6901 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6902 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6903
6904 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6905 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6906
6907 /* Reset PCIE errors for debug */
6908 REG_WR(bp, 0x2814, 0xffffffff);
6909 REG_WR(bp, 0x3820, 0xffffffff);
6910
6911 if (!CHIP_IS_E1x(bp)) {
6912 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6913 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6914 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6915 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6916 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6917 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6918 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6919 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6920 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6921 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6922 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6923 }
6924
6925 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6926 if (!CHIP_IS_E1(bp)) {
6927 /* in E3 this done in per-port section */
6928 if (!CHIP_IS_E3(bp))
6929 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6930 }
6931 if (CHIP_IS_E1H(bp))
6932 /* not applicable for E2 (and above ...) */
6933 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6934
6935 if (CHIP_REV_IS_SLOW(bp))
6936 msleep(200);
6937
6938 /* finish CFC init */
6939 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6940 if (val != 1) {
6941 BNX2X_ERR("CFC LL_INIT failed\n");
6942 return -EBUSY;
6943 }
6944 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6945 if (val != 1) {
6946 BNX2X_ERR("CFC AC_INIT failed\n");
6947 return -EBUSY;
6948 }
6949 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6950 if (val != 1) {
6951 BNX2X_ERR("CFC CAM_INIT failed\n");
6952 return -EBUSY;
6953 }
6954 REG_WR(bp, CFC_REG_DEBUG0, 0);
6955
6956 if (CHIP_IS_E1(bp)) {
6957 /* read NIG statistic
6958 to see if this is our first up since powerup */
6959 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6960 val = *bnx2x_sp(bp, wb_data[0]);
6961
6962 /* do internal memory self test */
6963 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6964 BNX2X_ERR("internal mem self test failed\n");
6965 return -EBUSY;
6966 }
6967 }
6968
6969 bnx2x_setup_fan_failure_detection(bp);
6970
6971 /* clear PXP2 attentions */
6972 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6973
6974 bnx2x_enable_blocks_attention(bp);
6975 bnx2x_enable_blocks_parity(bp);
6976
6977 if (!BP_NOMCP(bp)) {
6978 if (CHIP_IS_E1x(bp))
6979 bnx2x__common_init_phy(bp);
6980 } else
6981 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6982
6983 return 0;
6984 }
6985
6986 /**
6987 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6988 *
6989 * @bp: driver handle
6990 */
6991 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6992 {
6993 int rc = bnx2x_init_hw_common(bp);
6994
6995 if (rc)
6996 return rc;
6997
6998 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6999 if (!BP_NOMCP(bp))
7000 bnx2x__common_init_phy(bp);
7001
7002 return 0;
7003 }
7004
7005 static int bnx2x_init_hw_port(struct bnx2x *bp)
7006 {
7007 int port = BP_PORT(bp);
7008 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
7009 u32 low, high;
7010 u32 val;
7011
7012
7013 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
7014
7015 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
7016
7017 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7018 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7019 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7020
7021 /* Timers bug workaround: disables the pf_master bit in pglue at
7022 * common phase, we need to enable it here before any dmae access are
7023 * attempted. Therefore we manually added the enable-master to the
7024 * port phase (it also happens in the function phase)
7025 */
7026 if (!CHIP_IS_E1x(bp))
7027 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7028
7029 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7030 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7031 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7032 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7033
7034 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7035 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7036 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7037 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7038
7039 /* QM cid (connection) count */
7040 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
7041
7042 if (CNIC_SUPPORT(bp)) {
7043 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7044 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
7045 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
7046 }
7047
7048 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7049
7050 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7051
7052 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
7053
7054 if (IS_MF(bp))
7055 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
7056 else if (bp->dev->mtu > 4096) {
7057 if (bp->flags & ONE_PORT_FLAG)
7058 low = 160;
7059 else {
7060 val = bp->dev->mtu;
7061 /* (24*1024 + val*4)/256 */
7062 low = 96 + (val/64) +
7063 ((val % 64) ? 1 : 0);
7064 }
7065 } else
7066 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
7067 high = low + 56; /* 14*1024/256 */
7068 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
7069 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
7070 }
7071
7072 if (CHIP_MODE_IS_4_PORT(bp))
7073 REG_WR(bp, (BP_PORT(bp) ?
7074 BRB1_REG_MAC_GUARANTIED_1 :
7075 BRB1_REG_MAC_GUARANTIED_0), 40);
7076
7077
7078 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7079 if (CHIP_IS_E3B0(bp)) {
7080 if (IS_MF_AFEX(bp)) {
7081 /* configure headers for AFEX mode */
7082 REG_WR(bp, BP_PORT(bp) ?
7083 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7084 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
7085 REG_WR(bp, BP_PORT(bp) ?
7086 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
7087 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
7088 REG_WR(bp, BP_PORT(bp) ?
7089 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
7090 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
7091 } else {
7092 /* Ovlan exists only if we are in multi-function +
7093 * switch-dependent mode, in switch-independent there
7094 * is no ovlan headers
7095 */
7096 REG_WR(bp, BP_PORT(bp) ?
7097 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
7098 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
7099 (bp->path_has_ovlan ? 7 : 6));
7100 }
7101 }
7102
7103 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7104 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7105 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7106 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7107
7108 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7109 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7110 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7111 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7112
7113 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7114 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7115
7116 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7117
7118 if (CHIP_IS_E1x(bp)) {
7119 /* configure PBF to work without PAUSE mtu 9000 */
7120 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
7121
7122 /* update threshold */
7123 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
7124 /* update init credit */
7125 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
7126
7127 /* probe changes */
7128 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
7129 udelay(50);
7130 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
7131 }
7132
7133 if (CNIC_SUPPORT(bp))
7134 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7135
7136 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7137 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7138
7139 if (CHIP_IS_E1(bp)) {
7140 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7141 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7142 }
7143 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7144
7145 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7146
7147 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7148 /* init aeu_mask_attn_func_0/1:
7149 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
7150 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
7151 * bits 4-7 are used for "per vn group attention" */
7152 val = IS_MF(bp) ? 0xF7 : 0x7;
7153 /* Enable DCBX attention for all but E1 */
7154 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
7155 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
7156
7157 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7158
7159 if (!CHIP_IS_E1x(bp)) {
7160 /* Bit-map indicating which L2 hdrs may appear after the
7161 * basic Ethernet header
7162 */
7163 if (IS_MF_AFEX(bp))
7164 REG_WR(bp, BP_PORT(bp) ?
7165 NIG_REG_P1_HDRS_AFTER_BASIC :
7166 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
7167 else
7168 REG_WR(bp, BP_PORT(bp) ?
7169 NIG_REG_P1_HDRS_AFTER_BASIC :
7170 NIG_REG_P0_HDRS_AFTER_BASIC,
7171 IS_MF_SD(bp) ? 7 : 6);
7172
7173 if (CHIP_IS_E3(bp))
7174 REG_WR(bp, BP_PORT(bp) ?
7175 NIG_REG_LLH1_MF_MODE :
7176 NIG_REG_LLH_MF_MODE, IS_MF(bp));
7177 }
7178 if (!CHIP_IS_E3(bp))
7179 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
7180
7181 if (!CHIP_IS_E1(bp)) {
7182 /* 0x2 disable mf_ov, 0x1 enable */
7183 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
7184 (IS_MF_SD(bp) ? 0x1 : 0x2));
7185
7186 if (!CHIP_IS_E1x(bp)) {
7187 val = 0;
7188 switch (bp->mf_mode) {
7189 case MULTI_FUNCTION_SD:
7190 val = 1;
7191 break;
7192 case MULTI_FUNCTION_SI:
7193 case MULTI_FUNCTION_AFEX:
7194 val = 2;
7195 break;
7196 }
7197
7198 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
7199 NIG_REG_LLH0_CLS_TYPE), val);
7200 }
7201 {
7202 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
7203 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
7204 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
7205 }
7206 }
7207
7208 /* If SPIO5 is set to generate interrupts, enable it for this port */
7209 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
7210 if (val & MISC_SPIO_SPIO5) {
7211 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
7212 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
7213 val = REG_RD(bp, reg_addr);
7214 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
7215 REG_WR(bp, reg_addr, val);
7216 }
7217
7218 return 0;
7219 }
7220
7221 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
7222 {
7223 int reg;
7224 u32 wb_write[2];
7225
7226 if (CHIP_IS_E1(bp))
7227 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
7228 else
7229 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
7230
7231 wb_write[0] = ONCHIP_ADDR1(addr);
7232 wb_write[1] = ONCHIP_ADDR2(addr);
7233 REG_WR_DMAE(bp, reg, wb_write, 2);
7234 }
7235
7236 void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func, u8 idu_sb_id, bool is_pf)
7237 {
7238 u32 data, ctl, cnt = 100;
7239 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
7240 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
7241 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
7242 u32 sb_bit = 1 << (idu_sb_id%32);
7243 u32 func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
7244 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
7245
7246 /* Not supported in BC mode */
7247 if (CHIP_INT_MODE_IS_BC(bp))
7248 return;
7249
7250 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7251 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7252 IGU_REGULAR_CLEANUP_SET |
7253 IGU_REGULAR_BCLEANUP;
7254
7255 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7256 func_encode << IGU_CTRL_REG_FID_SHIFT |
7257 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7258
7259 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7260 data, igu_addr_data);
7261 REG_WR(bp, igu_addr_data, data);
7262 mmiowb();
7263 barrier();
7264 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7265 ctl, igu_addr_ctl);
7266 REG_WR(bp, igu_addr_ctl, ctl);
7267 mmiowb();
7268 barrier();
7269
7270 /* wait for clean up to finish */
7271 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7272 msleep(20);
7273
7274
7275 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7276 DP(NETIF_MSG_HW,
7277 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7278 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7279 }
7280 }
7281
7282 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7283 {
7284 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7285 }
7286
7287 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7288 {
7289 u32 i, base = FUNC_ILT_BASE(func);
7290 for (i = base; i < base + ILT_PER_FUNC; i++)
7291 bnx2x_ilt_wr(bp, i, 0);
7292 }
7293
7294
7295 static void bnx2x_init_searcher(struct bnx2x *bp)
7296 {
7297 int port = BP_PORT(bp);
7298 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7299 /* T1 hash bits value determines the T1 number of entries */
7300 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7301 }
7302
7303 static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
7304 {
7305 int rc;
7306 struct bnx2x_func_state_params func_params = {NULL};
7307 struct bnx2x_func_switch_update_params *switch_update_params =
7308 &func_params.params.switch_update;
7309
7310 /* Prepare parameters for function state transitions */
7311 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
7312 __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
7313
7314 func_params.f_obj = &bp->func_obj;
7315 func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
7316
7317 /* Function parameters */
7318 switch_update_params->suspend = suspend;
7319
7320 rc = bnx2x_func_state_change(bp, &func_params);
7321
7322 return rc;
7323 }
7324
7325 static int bnx2x_reset_nic_mode(struct bnx2x *bp)
7326 {
7327 int rc, i, port = BP_PORT(bp);
7328 int vlan_en = 0, mac_en[NUM_MACS];
7329
7330
7331 /* Close input from network */
7332 if (bp->mf_mode == SINGLE_FUNCTION) {
7333 bnx2x_set_rx_filter(&bp->link_params, 0);
7334 } else {
7335 vlan_en = REG_RD(bp, port ? NIG_REG_LLH1_FUNC_EN :
7336 NIG_REG_LLH0_FUNC_EN);
7337 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7338 NIG_REG_LLH0_FUNC_EN, 0);
7339 for (i = 0; i < NUM_MACS; i++) {
7340 mac_en[i] = REG_RD(bp, port ?
7341 (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7342 4 * i) :
7343 (NIG_REG_LLH0_FUNC_MEM_ENABLE +
7344 4 * i));
7345 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7346 4 * i) :
7347 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i), 0);
7348 }
7349 }
7350
7351 /* Close BMC to host */
7352 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7353 NIG_REG_P1_TX_MNG_HOST_ENABLE, 0);
7354
7355 /* Suspend Tx switching to the PF. Completion of this ramrod
7356 * further guarantees that all the packets of that PF / child
7357 * VFs in BRB were processed by the Parser, so it is safe to
7358 * change the NIC_MODE register.
7359 */
7360 rc = bnx2x_func_switch_update(bp, 1);
7361 if (rc) {
7362 BNX2X_ERR("Can't suspend tx-switching!\n");
7363 return rc;
7364 }
7365
7366 /* Change NIC_MODE register */
7367 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7368
7369 /* Open input from network */
7370 if (bp->mf_mode == SINGLE_FUNCTION) {
7371 bnx2x_set_rx_filter(&bp->link_params, 1);
7372 } else {
7373 REG_WR(bp, port ? NIG_REG_LLH1_FUNC_EN :
7374 NIG_REG_LLH0_FUNC_EN, vlan_en);
7375 for (i = 0; i < NUM_MACS; i++) {
7376 REG_WR(bp, port ? (NIG_REG_LLH1_FUNC_MEM_ENABLE +
7377 4 * i) :
7378 (NIG_REG_LLH0_FUNC_MEM_ENABLE + 4 * i),
7379 mac_en[i]);
7380 }
7381 }
7382
7383 /* Enable BMC to host */
7384 REG_WR(bp, port ? NIG_REG_P0_TX_MNG_HOST_ENABLE :
7385 NIG_REG_P1_TX_MNG_HOST_ENABLE, 1);
7386
7387 /* Resume Tx switching to the PF */
7388 rc = bnx2x_func_switch_update(bp, 0);
7389 if (rc) {
7390 BNX2X_ERR("Can't resume tx-switching!\n");
7391 return rc;
7392 }
7393
7394 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7395 return 0;
7396 }
7397
7398 int bnx2x_init_hw_func_cnic(struct bnx2x *bp)
7399 {
7400 int rc;
7401
7402 bnx2x_ilt_init_op_cnic(bp, INITOP_SET);
7403
7404 if (CONFIGURE_NIC_MODE(bp)) {
7405 /* Configrue searcher as part of function hw init */
7406 bnx2x_init_searcher(bp);
7407
7408 /* Reset NIC mode */
7409 rc = bnx2x_reset_nic_mode(bp);
7410 if (rc)
7411 BNX2X_ERR("Can't change NIC mode!\n");
7412 return rc;
7413 }
7414
7415 return 0;
7416 }
7417
7418 static int bnx2x_init_hw_func(struct bnx2x *bp)
7419 {
7420 int port = BP_PORT(bp);
7421 int func = BP_FUNC(bp);
7422 int init_phase = PHASE_PF0 + func;
7423 struct bnx2x_ilt *ilt = BP_ILT(bp);
7424 u16 cdu_ilt_start;
7425 u32 addr, val;
7426 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7427 int i, main_mem_width, rc;
7428
7429 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7430
7431 /* FLR cleanup - hmmm */
7432 if (!CHIP_IS_E1x(bp)) {
7433 rc = bnx2x_pf_flr_clnup(bp);
7434 if (rc) {
7435 bnx2x_fw_dump(bp);
7436 return rc;
7437 }
7438 }
7439
7440 /* set MSI reconfigure capability */
7441 if (bp->common.int_block == INT_BLOCK_HC) {
7442 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7443 val = REG_RD(bp, addr);
7444 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7445 REG_WR(bp, addr, val);
7446 }
7447
7448 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7449 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7450
7451 ilt = BP_ILT(bp);
7452 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7453
7454 if (IS_SRIOV(bp))
7455 cdu_ilt_start += BNX2X_FIRST_VF_CID/ILT_PAGE_CIDS;
7456 cdu_ilt_start = bnx2x_iov_init_ilt(bp, cdu_ilt_start);
7457
7458 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7459 * those of the VFs, so start line should be reset
7460 */
7461 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7462 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7463 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7464 ilt->lines[cdu_ilt_start + i].page_mapping =
7465 bp->context[i].cxt_mapping;
7466 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7467 }
7468
7469 bnx2x_ilt_init_op(bp, INITOP_SET);
7470
7471 if (!CONFIGURE_NIC_MODE(bp)) {
7472 bnx2x_init_searcher(bp);
7473 REG_WR(bp, PRS_REG_NIC_MODE, 0);
7474 DP(NETIF_MSG_IFUP, "NIC MODE disabled\n");
7475 } else {
7476 /* Set NIC mode */
7477 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7478 DP(NETIF_MSG_IFUP, "NIC MODE configrued\n");
7479
7480 }
7481
7482 if (!CHIP_IS_E1x(bp)) {
7483 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7484
7485 /* Turn on a single ISR mode in IGU if driver is going to use
7486 * INT#x or MSI
7487 */
7488 if (!(bp->flags & USING_MSIX_FLAG))
7489 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7490 /*
7491 * Timers workaround bug: function init part.
7492 * Need to wait 20msec after initializing ILT,
7493 * needed to make sure there are no requests in
7494 * one of the PXP internal queues with "old" ILT addresses
7495 */
7496 msleep(20);
7497 /*
7498 * Master enable - Due to WB DMAE writes performed before this
7499 * register is re-initialized as part of the regular function
7500 * init
7501 */
7502 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7503 /* Enable the function in IGU */
7504 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7505 }
7506
7507 bp->dmae_ready = 1;
7508
7509 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7510
7511 if (!CHIP_IS_E1x(bp))
7512 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7513
7514 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7515 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7516 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7517 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7518 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7519 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7520 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7521 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7522 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7523 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7524 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7525 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7526 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7527
7528 if (!CHIP_IS_E1x(bp))
7529 REG_WR(bp, QM_REG_PF_EN, 1);
7530
7531 if (!CHIP_IS_E1x(bp)) {
7532 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7533 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7534 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7535 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7536 }
7537 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7538
7539 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7540 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7541
7542 bnx2x_iov_init_dq(bp);
7543
7544 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7545 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7546 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7547 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7548 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7549 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7550 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7551 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7552 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7553 if (!CHIP_IS_E1x(bp))
7554 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7555
7556 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7557
7558 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7559
7560 if (!CHIP_IS_E1x(bp))
7561 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7562
7563 if (IS_MF(bp)) {
7564 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7565 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7566 }
7567
7568 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7569
7570 /* HC init per function */
7571 if (bp->common.int_block == INT_BLOCK_HC) {
7572 if (CHIP_IS_E1H(bp)) {
7573 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7574
7575 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7576 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7577 }
7578 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7579
7580 } else {
7581 int num_segs, sb_idx, prod_offset;
7582
7583 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7584
7585 if (!CHIP_IS_E1x(bp)) {
7586 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7587 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7588 }
7589
7590 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7591
7592 if (!CHIP_IS_E1x(bp)) {
7593 int dsb_idx = 0;
7594 /**
7595 * Producer memory:
7596 * E2 mode: address 0-135 match to the mapping memory;
7597 * 136 - PF0 default prod; 137 - PF1 default prod;
7598 * 138 - PF2 default prod; 139 - PF3 default prod;
7599 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7600 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7601 * 144-147 reserved.
7602 *
7603 * E1.5 mode - In backward compatible mode;
7604 * for non default SB; each even line in the memory
7605 * holds the U producer and each odd line hold
7606 * the C producer. The first 128 producers are for
7607 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7608 * producers are for the DSB for each PF.
7609 * Each PF has five segments: (the order inside each
7610 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7611 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7612 * 144-147 attn prods;
7613 */
7614 /* non-default-status-blocks */
7615 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7616 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7617 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7618 prod_offset = (bp->igu_base_sb + sb_idx) *
7619 num_segs;
7620
7621 for (i = 0; i < num_segs; i++) {
7622 addr = IGU_REG_PROD_CONS_MEMORY +
7623 (prod_offset + i) * 4;
7624 REG_WR(bp, addr, 0);
7625 }
7626 /* send consumer update with value 0 */
7627 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7628 USTORM_ID, 0, IGU_INT_NOP, 1);
7629 bnx2x_igu_clear_sb(bp,
7630 bp->igu_base_sb + sb_idx);
7631 }
7632
7633 /* default-status-blocks */
7634 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7635 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7636
7637 if (CHIP_MODE_IS_4_PORT(bp))
7638 dsb_idx = BP_FUNC(bp);
7639 else
7640 dsb_idx = BP_VN(bp);
7641
7642 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7643 IGU_BC_BASE_DSB_PROD + dsb_idx :
7644 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7645
7646 /*
7647 * igu prods come in chunks of E1HVN_MAX (4) -
7648 * does not matters what is the current chip mode
7649 */
7650 for (i = 0; i < (num_segs * E1HVN_MAX);
7651 i += E1HVN_MAX) {
7652 addr = IGU_REG_PROD_CONS_MEMORY +
7653 (prod_offset + i)*4;
7654 REG_WR(bp, addr, 0);
7655 }
7656 /* send consumer update with 0 */
7657 if (CHIP_INT_MODE_IS_BC(bp)) {
7658 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7659 USTORM_ID, 0, IGU_INT_NOP, 1);
7660 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7661 CSTORM_ID, 0, IGU_INT_NOP, 1);
7662 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7663 XSTORM_ID, 0, IGU_INT_NOP, 1);
7664 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7665 TSTORM_ID, 0, IGU_INT_NOP, 1);
7666 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7667 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7668 } else {
7669 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7670 USTORM_ID, 0, IGU_INT_NOP, 1);
7671 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7672 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7673 }
7674 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7675
7676 /* !!! these should become driver const once
7677 rf-tool supports split-68 const */
7678 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7679 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7680 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7681 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7682 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7683 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7684 }
7685 }
7686
7687 /* Reset PCIE errors for debug */
7688 REG_WR(bp, 0x2114, 0xffffffff);
7689 REG_WR(bp, 0x2120, 0xffffffff);
7690
7691 if (CHIP_IS_E1x(bp)) {
7692 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7693 main_mem_base = HC_REG_MAIN_MEMORY +
7694 BP_PORT(bp) * (main_mem_size * 4);
7695 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7696 main_mem_width = 8;
7697
7698 val = REG_RD(bp, main_mem_prty_clr);
7699 if (val)
7700 DP(NETIF_MSG_HW,
7701 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7702 val);
7703
7704 /* Clear "false" parity errors in MSI-X table */
7705 for (i = main_mem_base;
7706 i < main_mem_base + main_mem_size * 4;
7707 i += main_mem_width) {
7708 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7709 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7710 i, main_mem_width / 4);
7711 }
7712 /* Clear HC parity attention */
7713 REG_RD(bp, main_mem_prty_clr);
7714 }
7715
7716 #ifdef BNX2X_STOP_ON_ERROR
7717 /* Enable STORMs SP logging */
7718 REG_WR8(bp, BAR_USTRORM_INTMEM +
7719 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7720 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7721 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7722 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7723 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7724 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7725 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7726 #endif
7727
7728 bnx2x_phy_probe(&bp->link_params);
7729
7730 return 0;
7731 }
7732
7733
7734 void bnx2x_free_mem_cnic(struct bnx2x *bp)
7735 {
7736 bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_FREE);
7737
7738 if (!CHIP_IS_E1x(bp))
7739 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7740 sizeof(struct host_hc_status_block_e2));
7741 else
7742 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7743 sizeof(struct host_hc_status_block_e1x));
7744
7745 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7746 }
7747
7748 void bnx2x_free_mem(struct bnx2x *bp)
7749 {
7750 int i;
7751
7752 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7753 sizeof(struct host_sp_status_block));
7754
7755 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7756 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7757
7758 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7759 sizeof(struct bnx2x_slowpath));
7760
7761 for (i = 0; i < L2_ILT_LINES(bp); i++)
7762 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7763 bp->context[i].size);
7764 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7765
7766 BNX2X_FREE(bp->ilt->lines);
7767
7768 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7769
7770 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7771 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7772
7773 bnx2x_iov_free_mem(bp);
7774 }
7775
7776
7777 int bnx2x_alloc_mem_cnic(struct bnx2x *bp)
7778 {
7779 if (!CHIP_IS_E1x(bp))
7780 /* size = the status block + ramrod buffers */
7781 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7782 sizeof(struct host_hc_status_block_e2));
7783 else
7784 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb,
7785 &bp->cnic_sb_mapping,
7786 sizeof(struct
7787 host_hc_status_block_e1x));
7788
7789 if (CONFIGURE_NIC_MODE(bp))
7790 /* allocate searcher T2 table, as it wan't allocated before */
7791 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7792
7793 /* write address to which L5 should insert its values */
7794 bp->cnic_eth_dev.addr_drv_info_to_mcp =
7795 &bp->slowpath->drv_info_to_mcp;
7796
7797 if (bnx2x_ilt_mem_op_cnic(bp, ILT_MEMOP_ALLOC))
7798 goto alloc_mem_err;
7799
7800 return 0;
7801
7802 alloc_mem_err:
7803 bnx2x_free_mem_cnic(bp);
7804 BNX2X_ERR("Can't allocate memory\n");
7805 return -ENOMEM;
7806 }
7807
7808 int bnx2x_alloc_mem(struct bnx2x *bp)
7809 {
7810 int i, allocated, context_size;
7811
7812 if (!CONFIGURE_NIC_MODE(bp))
7813 /* allocate searcher T2 table */
7814 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7815
7816 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7817 sizeof(struct host_sp_status_block));
7818
7819 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7820 sizeof(struct bnx2x_slowpath));
7821
7822 /* Allocate memory for CDU context:
7823 * This memory is allocated separately and not in the generic ILT
7824 * functions because CDU differs in few aspects:
7825 * 1. There are multiple entities allocating memory for context -
7826 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7827 * its own ILT lines.
7828 * 2. Since CDU page-size is not a single 4KB page (which is the case
7829 * for the other ILT clients), to be efficient we want to support
7830 * allocation of sub-page-size in the last entry.
7831 * 3. Context pointers are used by the driver to pass to FW / update
7832 * the context (for the other ILT clients the pointers are used just to
7833 * free the memory during unload).
7834 */
7835 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7836
7837 for (i = 0, allocated = 0; allocated < context_size; i++) {
7838 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7839 (context_size - allocated));
7840 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7841 &bp->context[i].cxt_mapping,
7842 bp->context[i].size);
7843 allocated += bp->context[i].size;
7844 }
7845 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7846
7847 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7848 goto alloc_mem_err;
7849
7850 if (bnx2x_iov_alloc_mem(bp))
7851 goto alloc_mem_err;
7852
7853 /* Slow path ring */
7854 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7855
7856 /* EQ */
7857 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7858 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7859
7860 return 0;
7861
7862 alloc_mem_err:
7863 bnx2x_free_mem(bp);
7864 BNX2X_ERR("Can't allocate memory\n");
7865 return -ENOMEM;
7866 }
7867
7868 /*
7869 * Init service functions
7870 */
7871
7872 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7873 struct bnx2x_vlan_mac_obj *obj, bool set,
7874 int mac_type, unsigned long *ramrod_flags)
7875 {
7876 int rc;
7877 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7878
7879 memset(&ramrod_param, 0, sizeof(ramrod_param));
7880
7881 /* Fill general parameters */
7882 ramrod_param.vlan_mac_obj = obj;
7883 ramrod_param.ramrod_flags = *ramrod_flags;
7884
7885 /* Fill a user request section if needed */
7886 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7887 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7888
7889 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7890
7891 /* Set the command: ADD or DEL */
7892 if (set)
7893 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7894 else
7895 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7896 }
7897
7898 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7899
7900 if (rc == -EEXIST) {
7901 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7902 /* do not treat adding same MAC as error */
7903 rc = 0;
7904 } else if (rc < 0)
7905 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7906
7907 return rc;
7908 }
7909
7910 int bnx2x_del_all_macs(struct bnx2x *bp,
7911 struct bnx2x_vlan_mac_obj *mac_obj,
7912 int mac_type, bool wait_for_comp)
7913 {
7914 int rc;
7915 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7916
7917 /* Wait for completion of requested */
7918 if (wait_for_comp)
7919 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7920
7921 /* Set the mac type of addresses we want to clear */
7922 __set_bit(mac_type, &vlan_mac_flags);
7923
7924 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7925 if (rc < 0)
7926 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7927
7928 return rc;
7929 }
7930
7931 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7932 {
7933 unsigned long ramrod_flags = 0;
7934
7935 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7936 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7937 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7938 "Ignoring Zero MAC for STORAGE SD mode\n");
7939 return 0;
7940 }
7941
7942 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7943
7944 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7945 /* Eth MAC is set on RSS leading client (fp[0]) */
7946 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7947 set, BNX2X_ETH_MAC, &ramrod_flags);
7948 }
7949
7950 int bnx2x_setup_leading(struct bnx2x *bp)
7951 {
7952 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7953 }
7954
7955 /**
7956 * bnx2x_set_int_mode - configure interrupt mode
7957 *
7958 * @bp: driver handle
7959 *
7960 * In case of MSI-X it will also try to enable MSI-X.
7961 */
7962 int bnx2x_set_int_mode(struct bnx2x *bp)
7963 {
7964 int rc = 0;
7965
7966 if (IS_VF(bp) && int_mode != BNX2X_INT_MODE_MSIX)
7967 return -EINVAL;
7968
7969 switch (int_mode) {
7970 case BNX2X_INT_MODE_MSIX:
7971 /* attempt to enable msix */
7972 rc = bnx2x_enable_msix(bp);
7973
7974 /* msix attained */
7975 if (!rc)
7976 return 0;
7977
7978 /* vfs use only msix */
7979 if (rc && IS_VF(bp))
7980 return rc;
7981
7982 /* failed to enable multiple MSI-X */
7983 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7984 bp->num_queues,
7985 1 + bp->num_cnic_queues);
7986
7987 /* falling through... */
7988 case BNX2X_INT_MODE_MSI:
7989 bnx2x_enable_msi(bp);
7990
7991 /* falling through... */
7992 case BNX2X_INT_MODE_INTX:
7993 bp->num_ethernet_queues = 1;
7994 bp->num_queues = bp->num_ethernet_queues + bp->num_cnic_queues;
7995 BNX2X_DEV_INFO("set number of queues to 1\n");
7996 break;
7997 default:
7998 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
7999 return -EINVAL;
8000 }
8001 return 0;
8002 }
8003
8004 /* must be called prior to any HW initializations */
8005 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
8006 {
8007 if (IS_SRIOV(bp))
8008 return (BNX2X_FIRST_VF_CID + BNX2X_VF_CIDS)/ILT_PAGE_CIDS;
8009 return L2_ILT_LINES(bp);
8010 }
8011
8012 void bnx2x_ilt_set_info(struct bnx2x *bp)
8013 {
8014 struct ilt_client_info *ilt_client;
8015 struct bnx2x_ilt *ilt = BP_ILT(bp);
8016 u16 line = 0;
8017
8018 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
8019 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
8020
8021 /* CDU */
8022 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
8023 ilt_client->client_num = ILT_CLIENT_CDU;
8024 ilt_client->page_size = CDU_ILT_PAGE_SZ;
8025 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
8026 ilt_client->start = line;
8027 line += bnx2x_cid_ilt_lines(bp);
8028
8029 if (CNIC_SUPPORT(bp))
8030 line += CNIC_ILT_LINES;
8031 ilt_client->end = line - 1;
8032
8033 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8034 ilt_client->start,
8035 ilt_client->end,
8036 ilt_client->page_size,
8037 ilt_client->flags,
8038 ilog2(ilt_client->page_size >> 12));
8039
8040 /* QM */
8041 if (QM_INIT(bp->qm_cid_count)) {
8042 ilt_client = &ilt->clients[ILT_CLIENT_QM];
8043 ilt_client->client_num = ILT_CLIENT_QM;
8044 ilt_client->page_size = QM_ILT_PAGE_SZ;
8045 ilt_client->flags = 0;
8046 ilt_client->start = line;
8047
8048 /* 4 bytes for each cid */
8049 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
8050 QM_ILT_PAGE_SZ);
8051
8052 ilt_client->end = line - 1;
8053
8054 DP(NETIF_MSG_IFUP,
8055 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8056 ilt_client->start,
8057 ilt_client->end,
8058 ilt_client->page_size,
8059 ilt_client->flags,
8060 ilog2(ilt_client->page_size >> 12));
8061
8062 }
8063
8064 if (CNIC_SUPPORT(bp)) {
8065 /* SRC */
8066 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
8067 ilt_client->client_num = ILT_CLIENT_SRC;
8068 ilt_client->page_size = SRC_ILT_PAGE_SZ;
8069 ilt_client->flags = 0;
8070 ilt_client->start = line;
8071 line += SRC_ILT_LINES;
8072 ilt_client->end = line - 1;
8073
8074 DP(NETIF_MSG_IFUP,
8075 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8076 ilt_client->start,
8077 ilt_client->end,
8078 ilt_client->page_size,
8079 ilt_client->flags,
8080 ilog2(ilt_client->page_size >> 12));
8081
8082 /* TM */
8083 ilt_client = &ilt->clients[ILT_CLIENT_TM];
8084 ilt_client->client_num = ILT_CLIENT_TM;
8085 ilt_client->page_size = TM_ILT_PAGE_SZ;
8086 ilt_client->flags = 0;
8087 ilt_client->start = line;
8088 line += TM_ILT_LINES;
8089 ilt_client->end = line - 1;
8090
8091 DP(NETIF_MSG_IFUP,
8092 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8093 ilt_client->start,
8094 ilt_client->end,
8095 ilt_client->page_size,
8096 ilt_client->flags,
8097 ilog2(ilt_client->page_size >> 12));
8098 }
8099
8100 BUG_ON(line > ILT_MAX_LINES);
8101 }
8102
8103 /**
8104 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8105 *
8106 * @bp: driver handle
8107 * @fp: pointer to fastpath
8108 * @init_params: pointer to parameters structure
8109 *
8110 * parameters configured:
8111 * - HC configuration
8112 * - Queue's CDU context
8113 */
8114 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
8115 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
8116 {
8117
8118 u8 cos;
8119 int cxt_index, cxt_offset;
8120
8121 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8122 if (!IS_FCOE_FP(fp)) {
8123 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
8124 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
8125
8126 /* If HC is supporterd, enable host coalescing in the transition
8127 * to INIT state.
8128 */
8129 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
8130 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
8131
8132 /* HC rate */
8133 init_params->rx.hc_rate = bp->rx_ticks ?
8134 (1000000 / bp->rx_ticks) : 0;
8135 init_params->tx.hc_rate = bp->tx_ticks ?
8136 (1000000 / bp->tx_ticks) : 0;
8137
8138 /* FW SB ID */
8139 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
8140 fp->fw_sb_id;
8141
8142 /*
8143 * CQ index among the SB indices: FCoE clients uses the default
8144 * SB, therefore it's different.
8145 */
8146 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
8147 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
8148 }
8149
8150 /* set maximum number of COSs supported by this queue */
8151 init_params->max_cos = fp->max_cos;
8152
8153 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
8154 fp->index, init_params->max_cos);
8155
8156 /* set the context pointers queue object */
8157 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
8158 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
8159 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
8160 ILT_PAGE_CIDS);
8161 init_params->cxts[cos] =
8162 &bp->context[cxt_index].vcxt[cxt_offset].eth;
8163 }
8164 }
8165
8166 static int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8167 struct bnx2x_queue_state_params *q_params,
8168 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
8169 int tx_index, bool leading)
8170 {
8171 memset(tx_only_params, 0, sizeof(*tx_only_params));
8172
8173 /* Set the command */
8174 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
8175
8176 /* Set tx-only QUEUE flags: don't zero statistics */
8177 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
8178
8179 /* choose the index of the cid to send the slow path on */
8180 tx_only_params->cid_index = tx_index;
8181
8182 /* Set general TX_ONLY_SETUP parameters */
8183 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
8184
8185 /* Set Tx TX_ONLY_SETUP parameters */
8186 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
8187
8188 DP(NETIF_MSG_IFUP,
8189 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8190 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
8191 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
8192 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
8193
8194 /* send the ramrod */
8195 return bnx2x_queue_state_change(bp, q_params);
8196 }
8197
8198
8199 /**
8200 * bnx2x_setup_queue - setup queue
8201 *
8202 * @bp: driver handle
8203 * @fp: pointer to fastpath
8204 * @leading: is leading
8205 *
8206 * This function performs 2 steps in a Queue state machine
8207 * actually: 1) RESET->INIT 2) INIT->SETUP
8208 */
8209
8210 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
8211 bool leading)
8212 {
8213 struct bnx2x_queue_state_params q_params = {NULL};
8214 struct bnx2x_queue_setup_params *setup_params =
8215 &q_params.params.setup;
8216 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
8217 &q_params.params.tx_only;
8218 int rc;
8219 u8 tx_index;
8220
8221 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
8222
8223 /* reset IGU state skip FCoE L2 queue */
8224 if (!IS_FCOE_FP(fp))
8225 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
8226 IGU_INT_ENABLE, 0);
8227
8228 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8229 /* We want to wait for completion in this context */
8230 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8231
8232 /* Prepare the INIT parameters */
8233 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
8234
8235 /* Set the command */
8236 q_params.cmd = BNX2X_Q_CMD_INIT;
8237
8238 /* Change the state to INIT */
8239 rc = bnx2x_queue_state_change(bp, &q_params);
8240 if (rc) {
8241 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
8242 return rc;
8243 }
8244
8245 DP(NETIF_MSG_IFUP, "init complete\n");
8246
8247
8248 /* Now move the Queue to the SETUP state... */
8249 memset(setup_params, 0, sizeof(*setup_params));
8250
8251 /* Set QUEUE flags */
8252 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
8253
8254 /* Set general SETUP parameters */
8255 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
8256 FIRST_TX_COS_INDEX);
8257
8258 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
8259 &setup_params->rxq_params);
8260
8261 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
8262 FIRST_TX_COS_INDEX);
8263
8264 /* Set the command */
8265 q_params.cmd = BNX2X_Q_CMD_SETUP;
8266
8267 if (IS_FCOE_FP(fp))
8268 bp->fcoe_init = true;
8269
8270 /* Change the state to SETUP */
8271 rc = bnx2x_queue_state_change(bp, &q_params);
8272 if (rc) {
8273 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
8274 return rc;
8275 }
8276
8277 /* loop through the relevant tx-only indices */
8278 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8279 tx_index < fp->max_cos;
8280 tx_index++) {
8281
8282 /* prepare and send tx-only ramrod*/
8283 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
8284 tx_only_params, tx_index, leading);
8285 if (rc) {
8286 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8287 fp->index, tx_index);
8288 return rc;
8289 }
8290 }
8291
8292 return rc;
8293 }
8294
8295 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
8296 {
8297 struct bnx2x_fastpath *fp = &bp->fp[index];
8298 struct bnx2x_fp_txdata *txdata;
8299 struct bnx2x_queue_state_params q_params = {NULL};
8300 int rc, tx_index;
8301
8302 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
8303
8304 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
8305 /* We want to wait for completion in this context */
8306 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
8307
8308
8309 /* close tx-only connections */
8310 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
8311 tx_index < fp->max_cos;
8312 tx_index++){
8313
8314 /* ascertain this is a normal queue*/
8315 txdata = fp->txdata_ptr[tx_index];
8316
8317 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
8318 txdata->txq_index);
8319
8320 /* send halt terminate on tx-only connection */
8321 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8322 memset(&q_params.params.terminate, 0,
8323 sizeof(q_params.params.terminate));
8324 q_params.params.terminate.cid_index = tx_index;
8325
8326 rc = bnx2x_queue_state_change(bp, &q_params);
8327 if (rc)
8328 return rc;
8329
8330 /* send halt terminate on tx-only connection */
8331 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8332 memset(&q_params.params.cfc_del, 0,
8333 sizeof(q_params.params.cfc_del));
8334 q_params.params.cfc_del.cid_index = tx_index;
8335 rc = bnx2x_queue_state_change(bp, &q_params);
8336 if (rc)
8337 return rc;
8338 }
8339 /* Stop the primary connection: */
8340 /* ...halt the connection */
8341 q_params.cmd = BNX2X_Q_CMD_HALT;
8342 rc = bnx2x_queue_state_change(bp, &q_params);
8343 if (rc)
8344 return rc;
8345
8346 /* ...terminate the connection */
8347 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8348 memset(&q_params.params.terminate, 0,
8349 sizeof(q_params.params.terminate));
8350 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8351 rc = bnx2x_queue_state_change(bp, &q_params);
8352 if (rc)
8353 return rc;
8354 /* ...delete cfc entry */
8355 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8356 memset(&q_params.params.cfc_del, 0,
8357 sizeof(q_params.params.cfc_del));
8358 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8359 return bnx2x_queue_state_change(bp, &q_params);
8360 }
8361
8362
8363 static void bnx2x_reset_func(struct bnx2x *bp)
8364 {
8365 int port = BP_PORT(bp);
8366 int func = BP_FUNC(bp);
8367 int i;
8368
8369 /* Disable the function in the FW */
8370 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8371 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8372 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8373 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8374
8375 /* FP SBs */
8376 for_each_eth_queue(bp, i) {
8377 struct bnx2x_fastpath *fp = &bp->fp[i];
8378 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8379 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8380 SB_DISABLED);
8381 }
8382
8383 if (CNIC_LOADED(bp))
8384 /* CNIC SB */
8385 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8386 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8387 (bnx2x_cnic_fw_sb_id(bp)), SB_DISABLED);
8388
8389 /* SP SB */
8390 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8391 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8392 SB_DISABLED);
8393
8394 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8395 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8396 0);
8397
8398 /* Configure IGU */
8399 if (bp->common.int_block == INT_BLOCK_HC) {
8400 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8401 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8402 } else {
8403 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8404 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8405 }
8406
8407 if (CNIC_LOADED(bp)) {
8408 /* Disable Timer scan */
8409 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8410 /*
8411 * Wait for at least 10ms and up to 2 second for the timers
8412 * scan to complete
8413 */
8414 for (i = 0; i < 200; i++) {
8415 msleep(10);
8416 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8417 break;
8418 }
8419 }
8420 /* Clear ILT */
8421 bnx2x_clear_func_ilt(bp, func);
8422
8423 /* Timers workaround bug for E2: if this is vnic-3,
8424 * we need to set the entire ilt range for this timers.
8425 */
8426 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8427 struct ilt_client_info ilt_cli;
8428 /* use dummy TM client */
8429 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8430 ilt_cli.start = 0;
8431 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8432 ilt_cli.client_num = ILT_CLIENT_TM;
8433
8434 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8435 }
8436
8437 /* this assumes that reset_port() called before reset_func()*/
8438 if (!CHIP_IS_E1x(bp))
8439 bnx2x_pf_disable(bp);
8440
8441 bp->dmae_ready = 0;
8442 }
8443
8444 static void bnx2x_reset_port(struct bnx2x *bp)
8445 {
8446 int port = BP_PORT(bp);
8447 u32 val;
8448
8449 /* Reset physical Link */
8450 bnx2x__link_reset(bp);
8451
8452 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8453
8454 /* Do not rcv packets to BRB */
8455 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8456 /* Do not direct rcv packets that are not for MCP to the BRB */
8457 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8458 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8459
8460 /* Configure AEU */
8461 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8462
8463 msleep(100);
8464 /* Check for BRB port occupancy */
8465 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8466 if (val)
8467 DP(NETIF_MSG_IFDOWN,
8468 "BRB1 is not empty %d blocks are occupied\n", val);
8469
8470 /* TODO: Close Doorbell port? */
8471 }
8472
8473 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8474 {
8475 struct bnx2x_func_state_params func_params = {NULL};
8476
8477 /* Prepare parameters for function state transitions */
8478 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8479
8480 func_params.f_obj = &bp->func_obj;
8481 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8482
8483 func_params.params.hw_init.load_phase = load_code;
8484
8485 return bnx2x_func_state_change(bp, &func_params);
8486 }
8487
8488 static int bnx2x_func_stop(struct bnx2x *bp)
8489 {
8490 struct bnx2x_func_state_params func_params = {NULL};
8491 int rc;
8492
8493 /* Prepare parameters for function state transitions */
8494 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8495 func_params.f_obj = &bp->func_obj;
8496 func_params.cmd = BNX2X_F_CMD_STOP;
8497
8498 /*
8499 * Try to stop the function the 'good way'. If fails (in case
8500 * of a parity error during bnx2x_chip_cleanup()) and we are
8501 * not in a debug mode, perform a state transaction in order to
8502 * enable further HW_RESET transaction.
8503 */
8504 rc = bnx2x_func_state_change(bp, &func_params);
8505 if (rc) {
8506 #ifdef BNX2X_STOP_ON_ERROR
8507 return rc;
8508 #else
8509 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8510 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8511 return bnx2x_func_state_change(bp, &func_params);
8512 #endif
8513 }
8514
8515 return 0;
8516 }
8517
8518 /**
8519 * bnx2x_send_unload_req - request unload mode from the MCP.
8520 *
8521 * @bp: driver handle
8522 * @unload_mode: requested function's unload mode
8523 *
8524 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8525 */
8526 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8527 {
8528 u32 reset_code = 0;
8529 int port = BP_PORT(bp);
8530
8531 /* Select the UNLOAD request mode */
8532 if (unload_mode == UNLOAD_NORMAL)
8533 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8534
8535 else if (bp->flags & NO_WOL_FLAG)
8536 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8537
8538 else if (bp->wol) {
8539 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8540 u8 *mac_addr = bp->dev->dev_addr;
8541 u32 val;
8542 u16 pmc;
8543
8544 /* The mac address is written to entries 1-4 to
8545 * preserve entry 0 which is used by the PMF
8546 */
8547 u8 entry = (BP_VN(bp) + 1)*8;
8548
8549 val = (mac_addr[0] << 8) | mac_addr[1];
8550 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8551
8552 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8553 (mac_addr[4] << 8) | mac_addr[5];
8554 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8555
8556 /* Enable the PME and clear the status */
8557 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8558 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8559 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8560
8561 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8562
8563 } else
8564 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8565
8566 /* Send the request to the MCP */
8567 if (!BP_NOMCP(bp))
8568 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8569 else {
8570 int path = BP_PATH(bp);
8571
8572 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8573 path, load_count[path][0], load_count[path][1],
8574 load_count[path][2]);
8575 load_count[path][0]--;
8576 load_count[path][1 + port]--;
8577 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8578 path, load_count[path][0], load_count[path][1],
8579 load_count[path][2]);
8580 if (load_count[path][0] == 0)
8581 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8582 else if (load_count[path][1 + port] == 0)
8583 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8584 else
8585 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8586 }
8587
8588 return reset_code;
8589 }
8590
8591 /**
8592 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8593 *
8594 * @bp: driver handle
8595 * @keep_link: true iff link should be kept up
8596 */
8597 void bnx2x_send_unload_done(struct bnx2x *bp, bool keep_link)
8598 {
8599 u32 reset_param = keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0;
8600
8601 /* Report UNLOAD_DONE to MCP */
8602 if (!BP_NOMCP(bp))
8603 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, reset_param);
8604 }
8605
8606 static int bnx2x_func_wait_started(struct bnx2x *bp)
8607 {
8608 int tout = 50;
8609 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8610
8611 if (!bp->port.pmf)
8612 return 0;
8613
8614 /*
8615 * (assumption: No Attention from MCP at this stage)
8616 * PMF probably in the middle of TXdisable/enable transaction
8617 * 1. Sync IRS for default SB
8618 * 2. Sync SP queue - this guarantes us that attention handling started
8619 * 3. Wait, that TXdisable/enable transaction completes
8620 *
8621 * 1+2 guranty that if DCBx attention was scheduled it already changed
8622 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8623 * received complettion for the transaction the state is TX_STOPPED.
8624 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8625 * transaction.
8626 */
8627
8628 /* make sure default SB ISR is done */
8629 if (msix)
8630 synchronize_irq(bp->msix_table[0].vector);
8631 else
8632 synchronize_irq(bp->pdev->irq);
8633
8634 flush_workqueue(bnx2x_wq);
8635
8636 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8637 BNX2X_F_STATE_STARTED && tout--)
8638 msleep(20);
8639
8640 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8641 BNX2X_F_STATE_STARTED) {
8642 #ifdef BNX2X_STOP_ON_ERROR
8643 BNX2X_ERR("Wrong function state\n");
8644 return -EBUSY;
8645 #else
8646 /*
8647 * Failed to complete the transaction in a "good way"
8648 * Force both transactions with CLR bit
8649 */
8650 struct bnx2x_func_state_params func_params = {NULL};
8651
8652 DP(NETIF_MSG_IFDOWN,
8653 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8654
8655 func_params.f_obj = &bp->func_obj;
8656 __set_bit(RAMROD_DRV_CLR_ONLY,
8657 &func_params.ramrod_flags);
8658
8659 /* STARTED-->TX_ST0PPED */
8660 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8661 bnx2x_func_state_change(bp, &func_params);
8662
8663 /* TX_ST0PPED-->STARTED */
8664 func_params.cmd = BNX2X_F_CMD_TX_START;
8665 return bnx2x_func_state_change(bp, &func_params);
8666 #endif
8667 }
8668
8669 return 0;
8670 }
8671
8672 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
8673 {
8674 int port = BP_PORT(bp);
8675 int i, rc = 0;
8676 u8 cos;
8677 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8678 u32 reset_code;
8679
8680 /* Wait until tx fastpath tasks complete */
8681 for_each_tx_queue(bp, i) {
8682 struct bnx2x_fastpath *fp = &bp->fp[i];
8683
8684 for_each_cos_in_tx_queue(fp, cos)
8685 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8686 #ifdef BNX2X_STOP_ON_ERROR
8687 if (rc)
8688 return;
8689 #endif
8690 }
8691
8692 /* Give HW time to discard old tx messages */
8693 usleep_range(1000, 2000);
8694
8695 /* Clean all ETH MACs */
8696 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8697 false);
8698 if (rc < 0)
8699 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8700
8701 /* Clean up UC list */
8702 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8703 true);
8704 if (rc < 0)
8705 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8706 rc);
8707
8708 /* Disable LLH */
8709 if (!CHIP_IS_E1(bp))
8710 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8711
8712 /* Set "drop all" (stop Rx).
8713 * We need to take a netif_addr_lock() here in order to prevent
8714 * a race between the completion code and this code.
8715 */
8716 netif_addr_lock_bh(bp->dev);
8717 /* Schedule the rx_mode command */
8718 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8719 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8720 else
8721 bnx2x_set_storm_rx_mode(bp);
8722
8723 /* Cleanup multicast configuration */
8724 rparam.mcast_obj = &bp->mcast_obj;
8725 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8726 if (rc < 0)
8727 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8728
8729 netif_addr_unlock_bh(bp->dev);
8730
8731 bnx2x_iov_chip_cleanup(bp);
8732
8733
8734 /*
8735 * Send the UNLOAD_REQUEST to the MCP. This will return if
8736 * this function should perform FUNC, PORT or COMMON HW
8737 * reset.
8738 */
8739 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8740
8741 /*
8742 * (assumption: No Attention from MCP at this stage)
8743 * PMF probably in the middle of TXdisable/enable transaction
8744 */
8745 rc = bnx2x_func_wait_started(bp);
8746 if (rc) {
8747 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8748 #ifdef BNX2X_STOP_ON_ERROR
8749 return;
8750 #endif
8751 }
8752
8753 /* Close multi and leading connections
8754 * Completions for ramrods are collected in a synchronous way
8755 */
8756 for_each_eth_queue(bp, i)
8757 if (bnx2x_stop_queue(bp, i))
8758 #ifdef BNX2X_STOP_ON_ERROR
8759 return;
8760 #else
8761 goto unload_error;
8762 #endif
8763
8764 if (CNIC_LOADED(bp)) {
8765 for_each_cnic_queue(bp, i)
8766 if (bnx2x_stop_queue(bp, i))
8767 #ifdef BNX2X_STOP_ON_ERROR
8768 return;
8769 #else
8770 goto unload_error;
8771 #endif
8772 }
8773
8774 /* If SP settings didn't get completed so far - something
8775 * very wrong has happen.
8776 */
8777 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8778 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8779
8780 #ifndef BNX2X_STOP_ON_ERROR
8781 unload_error:
8782 #endif
8783 rc = bnx2x_func_stop(bp);
8784 if (rc) {
8785 BNX2X_ERR("Function stop failed!\n");
8786 #ifdef BNX2X_STOP_ON_ERROR
8787 return;
8788 #endif
8789 }
8790
8791 /* Disable HW interrupts, NAPI */
8792 bnx2x_netif_stop(bp, 1);
8793 /* Delete all NAPI objects */
8794 bnx2x_del_all_napi(bp);
8795 if (CNIC_LOADED(bp))
8796 bnx2x_del_all_napi_cnic(bp);
8797
8798 /* Release IRQs */
8799 bnx2x_free_irq(bp);
8800
8801 /* Reset the chip */
8802 rc = bnx2x_reset_hw(bp, reset_code);
8803 if (rc)
8804 BNX2X_ERR("HW_RESET failed\n");
8805
8806
8807 /* Report UNLOAD_DONE to MCP */
8808 bnx2x_send_unload_done(bp, keep_link);
8809 }
8810
8811 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8812 {
8813 u32 val;
8814
8815 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8816
8817 if (CHIP_IS_E1(bp)) {
8818 int port = BP_PORT(bp);
8819 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8820 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8821
8822 val = REG_RD(bp, addr);
8823 val &= ~(0x300);
8824 REG_WR(bp, addr, val);
8825 } else {
8826 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8827 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8828 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8829 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8830 }
8831 }
8832
8833 /* Close gates #2, #3 and #4: */
8834 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8835 {
8836 u32 val;
8837
8838 /* Gates #2 and #4a are closed/opened for "not E1" only */
8839 if (!CHIP_IS_E1(bp)) {
8840 /* #4 */
8841 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8842 /* #2 */
8843 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8844 }
8845
8846 /* #3 */
8847 if (CHIP_IS_E1x(bp)) {
8848 /* Prevent interrupts from HC on both ports */
8849 val = REG_RD(bp, HC_REG_CONFIG_1);
8850 REG_WR(bp, HC_REG_CONFIG_1,
8851 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8852 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8853
8854 val = REG_RD(bp, HC_REG_CONFIG_0);
8855 REG_WR(bp, HC_REG_CONFIG_0,
8856 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8857 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8858 } else {
8859 /* Prevent incoming interrupts in IGU */
8860 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8861
8862 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8863 (!close) ?
8864 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8865 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8866 }
8867
8868 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8869 close ? "closing" : "opening");
8870 mmiowb();
8871 }
8872
8873 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8874
8875 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8876 {
8877 /* Do some magic... */
8878 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8879 *magic_val = val & SHARED_MF_CLP_MAGIC;
8880 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8881 }
8882
8883 /**
8884 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8885 *
8886 * @bp: driver handle
8887 * @magic_val: old value of the `magic' bit.
8888 */
8889 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8890 {
8891 /* Restore the `magic' bit value... */
8892 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8893 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8894 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8895 }
8896
8897 /**
8898 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8899 *
8900 * @bp: driver handle
8901 * @magic_val: old value of 'magic' bit.
8902 *
8903 * Takes care of CLP configurations.
8904 */
8905 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8906 {
8907 u32 shmem;
8908 u32 validity_offset;
8909
8910 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8911
8912 /* Set `magic' bit in order to save MF config */
8913 if (!CHIP_IS_E1(bp))
8914 bnx2x_clp_reset_prep(bp, magic_val);
8915
8916 /* Get shmem offset */
8917 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8918 validity_offset =
8919 offsetof(struct shmem_region, validity_map[BP_PORT(bp)]);
8920
8921 /* Clear validity map flags */
8922 if (shmem > 0)
8923 REG_WR(bp, shmem + validity_offset, 0);
8924 }
8925
8926 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8927 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8928
8929 /**
8930 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8931 *
8932 * @bp: driver handle
8933 */
8934 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8935 {
8936 /* special handling for emulation and FPGA,
8937 wait 10 times longer */
8938 if (CHIP_REV_IS_SLOW(bp))
8939 msleep(MCP_ONE_TIMEOUT*10);
8940 else
8941 msleep(MCP_ONE_TIMEOUT);
8942 }
8943
8944 /*
8945 * initializes bp->common.shmem_base and waits for validity signature to appear
8946 */
8947 static int bnx2x_init_shmem(struct bnx2x *bp)
8948 {
8949 int cnt = 0;
8950 u32 val = 0;
8951
8952 do {
8953 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8954 if (bp->common.shmem_base) {
8955 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8956 if (val & SHR_MEM_VALIDITY_MB)
8957 return 0;
8958 }
8959
8960 bnx2x_mcp_wait_one(bp);
8961
8962 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8963
8964 BNX2X_ERR("BAD MCP validity signature\n");
8965
8966 return -ENODEV;
8967 }
8968
8969 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8970 {
8971 int rc = bnx2x_init_shmem(bp);
8972
8973 /* Restore the `magic' bit value */
8974 if (!CHIP_IS_E1(bp))
8975 bnx2x_clp_reset_done(bp, magic_val);
8976
8977 return rc;
8978 }
8979
8980 static void bnx2x_pxp_prep(struct bnx2x *bp)
8981 {
8982 if (!CHIP_IS_E1(bp)) {
8983 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8984 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8985 mmiowb();
8986 }
8987 }
8988
8989 /*
8990 * Reset the whole chip except for:
8991 * - PCIE core
8992 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8993 * one reset bit)
8994 * - IGU
8995 * - MISC (including AEU)
8996 * - GRC
8997 * - RBCN, RBCP
8998 */
8999 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
9000 {
9001 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
9002 u32 global_bits2, stay_reset2;
9003
9004 /*
9005 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9006 * (per chip) blocks.
9007 */
9008 global_bits2 =
9009 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
9010 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
9011
9012 /* Don't reset the following blocks.
9013 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9014 * reset, as in 4 port device they might still be owned
9015 * by the MCP (there is only one leader per path).
9016 */
9017 not_reset_mask1 =
9018 MISC_REGISTERS_RESET_REG_1_RST_HC |
9019 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
9020 MISC_REGISTERS_RESET_REG_1_RST_PXP;
9021
9022 not_reset_mask2 =
9023 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
9024 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
9025 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
9026 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
9027 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
9028 MISC_REGISTERS_RESET_REG_2_RST_GRC |
9029 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
9030 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
9031 MISC_REGISTERS_RESET_REG_2_RST_ATC |
9032 MISC_REGISTERS_RESET_REG_2_PGLC |
9033 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
9034 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
9035 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
9036 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
9037 MISC_REGISTERS_RESET_REG_2_UMAC0 |
9038 MISC_REGISTERS_RESET_REG_2_UMAC1;
9039
9040 /*
9041 * Keep the following blocks in reset:
9042 * - all xxMACs are handled by the bnx2x_link code.
9043 */
9044 stay_reset2 =
9045 MISC_REGISTERS_RESET_REG_2_XMAC |
9046 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
9047
9048 /* Full reset masks according to the chip */
9049 reset_mask1 = 0xffffffff;
9050
9051 if (CHIP_IS_E1(bp))
9052 reset_mask2 = 0xffff;
9053 else if (CHIP_IS_E1H(bp))
9054 reset_mask2 = 0x1ffff;
9055 else if (CHIP_IS_E2(bp))
9056 reset_mask2 = 0xfffff;
9057 else /* CHIP_IS_E3 */
9058 reset_mask2 = 0x3ffffff;
9059
9060 /* Don't reset global blocks unless we need to */
9061 if (!global)
9062 reset_mask2 &= ~global_bits2;
9063
9064 /*
9065 * In case of attention in the QM, we need to reset PXP
9066 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9067 * because otherwise QM reset would release 'close the gates' shortly
9068 * before resetting the PXP, then the PSWRQ would send a write
9069 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9070 * read the payload data from PSWWR, but PSWWR would not
9071 * respond. The write queue in PGLUE would stuck, dmae commands
9072 * would not return. Therefore it's important to reset the second
9073 * reset register (containing the
9074 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9075 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9076 * bit).
9077 */
9078 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
9079 reset_mask2 & (~not_reset_mask2));
9080
9081 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
9082 reset_mask1 & (~not_reset_mask1));
9083
9084 barrier();
9085 mmiowb();
9086
9087 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
9088 reset_mask2 & (~stay_reset2));
9089
9090 barrier();
9091 mmiowb();
9092
9093 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
9094 mmiowb();
9095 }
9096
9097 /**
9098 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9099 * It should get cleared in no more than 1s.
9100 *
9101 * @bp: driver handle
9102 *
9103 * It should get cleared in no more than 1s. Returns 0 if
9104 * pending writes bit gets cleared.
9105 */
9106 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
9107 {
9108 u32 cnt = 1000;
9109 u32 pend_bits = 0;
9110
9111 do {
9112 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
9113
9114 if (pend_bits == 0)
9115 break;
9116
9117 usleep_range(1000, 2000);
9118 } while (cnt-- > 0);
9119
9120 if (cnt <= 0) {
9121 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9122 pend_bits);
9123 return -EBUSY;
9124 }
9125
9126 return 0;
9127 }
9128
9129 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
9130 {
9131 int cnt = 1000;
9132 u32 val = 0;
9133 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
9134 u32 tags_63_32 = 0;
9135
9136 /* Empty the Tetris buffer, wait for 1s */
9137 do {
9138 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
9139 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
9140 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
9141 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
9142 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
9143 if (CHIP_IS_E3(bp))
9144 tags_63_32 = REG_RD(bp, PGLUE_B_REG_TAGS_63_32);
9145
9146 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
9147 ((port_is_idle_0 & 0x1) == 0x1) &&
9148 ((port_is_idle_1 & 0x1) == 0x1) &&
9149 (pgl_exp_rom2 == 0xffffffff) &&
9150 (!CHIP_IS_E3(bp) || (tags_63_32 == 0xffffffff)))
9151 break;
9152 usleep_range(1000, 2000);
9153 } while (cnt-- > 0);
9154
9155 if (cnt <= 0) {
9156 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9157 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9158 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
9159 pgl_exp_rom2);
9160 return -EAGAIN;
9161 }
9162
9163 barrier();
9164
9165 /* Close gates #2, #3 and #4 */
9166 bnx2x_set_234_gates(bp, true);
9167
9168 /* Poll for IGU VQs for 57712 and newer chips */
9169 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
9170 return -EAGAIN;
9171
9172
9173 /* TBD: Indicate that "process kill" is in progress to MCP */
9174
9175 /* Clear "unprepared" bit */
9176 REG_WR(bp, MISC_REG_UNPREPARED, 0);
9177 barrier();
9178
9179 /* Make sure all is written to the chip before the reset */
9180 mmiowb();
9181
9182 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9183 * PSWHST, GRC and PSWRD Tetris buffer.
9184 */
9185 usleep_range(1000, 2000);
9186
9187 /* Prepare to chip reset: */
9188 /* MCP */
9189 if (global)
9190 bnx2x_reset_mcp_prep(bp, &val);
9191
9192 /* PXP */
9193 bnx2x_pxp_prep(bp);
9194 barrier();
9195
9196 /* reset the chip */
9197 bnx2x_process_kill_chip_reset(bp, global);
9198 barrier();
9199
9200 /* Recover after reset: */
9201 /* MCP */
9202 if (global && bnx2x_reset_mcp_comp(bp, val))
9203 return -EAGAIN;
9204
9205 /* TBD: Add resetting the NO_MCP mode DB here */
9206
9207 /* Open the gates #2, #3 and #4 */
9208 bnx2x_set_234_gates(bp, false);
9209
9210 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9211 * reset state, re-enable attentions. */
9212
9213 return 0;
9214 }
9215
9216 static int bnx2x_leader_reset(struct bnx2x *bp)
9217 {
9218 int rc = 0;
9219 bool global = bnx2x_reset_is_global(bp);
9220 u32 load_code;
9221
9222 /* if not going to reset MCP - load "fake" driver to reset HW while
9223 * driver is owner of the HW
9224 */
9225 if (!global && !BP_NOMCP(bp)) {
9226 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ,
9227 DRV_MSG_CODE_LOAD_REQ_WITH_LFA);
9228 if (!load_code) {
9229 BNX2X_ERR("MCP response failure, aborting\n");
9230 rc = -EAGAIN;
9231 goto exit_leader_reset;
9232 }
9233 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
9234 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
9235 BNX2X_ERR("MCP unexpected resp, aborting\n");
9236 rc = -EAGAIN;
9237 goto exit_leader_reset2;
9238 }
9239 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
9240 if (!load_code) {
9241 BNX2X_ERR("MCP response failure, aborting\n");
9242 rc = -EAGAIN;
9243 goto exit_leader_reset2;
9244 }
9245 }
9246
9247 /* Try to recover after the failure */
9248 if (bnx2x_process_kill(bp, global)) {
9249 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9250 BP_PATH(bp));
9251 rc = -EAGAIN;
9252 goto exit_leader_reset2;
9253 }
9254
9255 /*
9256 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9257 * state.
9258 */
9259 bnx2x_set_reset_done(bp);
9260 if (global)
9261 bnx2x_clear_reset_global(bp);
9262
9263 exit_leader_reset2:
9264 /* unload "fake driver" if it was loaded */
9265 if (!global && !BP_NOMCP(bp)) {
9266 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
9267 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9268 }
9269 exit_leader_reset:
9270 bp->is_leader = 0;
9271 bnx2x_release_leader_lock(bp);
9272 smp_mb();
9273 return rc;
9274 }
9275
9276 static void bnx2x_recovery_failed(struct bnx2x *bp)
9277 {
9278 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
9279
9280 /* Disconnect this device */
9281 netif_device_detach(bp->dev);
9282
9283 /*
9284 * Block ifup for all function on this engine until "process kill"
9285 * or power cycle.
9286 */
9287 bnx2x_set_reset_in_progress(bp);
9288
9289 /* Shut down the power */
9290 bnx2x_set_power_state(bp, PCI_D3hot);
9291
9292 bp->recovery_state = BNX2X_RECOVERY_FAILED;
9293
9294 smp_mb();
9295 }
9296
9297 /*
9298 * Assumption: runs under rtnl lock. This together with the fact
9299 * that it's called only from bnx2x_sp_rtnl() ensure that it
9300 * will never be called when netif_running(bp->dev) is false.
9301 */
9302 static void bnx2x_parity_recover(struct bnx2x *bp)
9303 {
9304 bool global = false;
9305 u32 error_recovered, error_unrecovered;
9306 bool is_parity;
9307
9308 DP(NETIF_MSG_HW, "Handling parity\n");
9309 while (1) {
9310 switch (bp->recovery_state) {
9311 case BNX2X_RECOVERY_INIT:
9312 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
9313 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
9314 WARN_ON(!is_parity);
9315
9316 /* Try to get a LEADER_LOCK HW lock */
9317 if (bnx2x_trylock_leader_lock(bp)) {
9318 bnx2x_set_reset_in_progress(bp);
9319 /*
9320 * Check if there is a global attention and if
9321 * there was a global attention, set the global
9322 * reset bit.
9323 */
9324
9325 if (global)
9326 bnx2x_set_reset_global(bp);
9327
9328 bp->is_leader = 1;
9329 }
9330
9331 /* Stop the driver */
9332 /* If interface has been removed - break */
9333 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY, false))
9334 return;
9335
9336 bp->recovery_state = BNX2X_RECOVERY_WAIT;
9337
9338 /* Ensure "is_leader", MCP command sequence and
9339 * "recovery_state" update values are seen on other
9340 * CPUs.
9341 */
9342 smp_mb();
9343 break;
9344
9345 case BNX2X_RECOVERY_WAIT:
9346 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
9347 if (bp->is_leader) {
9348 int other_engine = BP_PATH(bp) ? 0 : 1;
9349 bool other_load_status =
9350 bnx2x_get_load_status(bp, other_engine);
9351 bool load_status =
9352 bnx2x_get_load_status(bp, BP_PATH(bp));
9353 global = bnx2x_reset_is_global(bp);
9354
9355 /*
9356 * In case of a parity in a global block, let
9357 * the first leader that performs a
9358 * leader_reset() reset the global blocks in
9359 * order to clear global attentions. Otherwise
9360 * the the gates will remain closed for that
9361 * engine.
9362 */
9363 if (load_status ||
9364 (global && other_load_status)) {
9365 /* Wait until all other functions get
9366 * down.
9367 */
9368 schedule_delayed_work(&bp->sp_rtnl_task,
9369 HZ/10);
9370 return;
9371 } else {
9372 /* If all other functions got down -
9373 * try to bring the chip back to
9374 * normal. In any case it's an exit
9375 * point for a leader.
9376 */
9377 if (bnx2x_leader_reset(bp)) {
9378 bnx2x_recovery_failed(bp);
9379 return;
9380 }
9381
9382 /* If we are here, means that the
9383 * leader has succeeded and doesn't
9384 * want to be a leader any more. Try
9385 * to continue as a none-leader.
9386 */
9387 break;
9388 }
9389 } else { /* non-leader */
9390 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9391 /* Try to get a LEADER_LOCK HW lock as
9392 * long as a former leader may have
9393 * been unloaded by the user or
9394 * released a leadership by another
9395 * reason.
9396 */
9397 if (bnx2x_trylock_leader_lock(bp)) {
9398 /* I'm a leader now! Restart a
9399 * switch case.
9400 */
9401 bp->is_leader = 1;
9402 break;
9403 }
9404
9405 schedule_delayed_work(&bp->sp_rtnl_task,
9406 HZ/10);
9407 return;
9408
9409 } else {
9410 /*
9411 * If there was a global attention, wait
9412 * for it to be cleared.
9413 */
9414 if (bnx2x_reset_is_global(bp)) {
9415 schedule_delayed_work(
9416 &bp->sp_rtnl_task,
9417 HZ/10);
9418 return;
9419 }
9420
9421 error_recovered =
9422 bp->eth_stats.recoverable_error;
9423 error_unrecovered =
9424 bp->eth_stats.unrecoverable_error;
9425 bp->recovery_state =
9426 BNX2X_RECOVERY_NIC_LOADING;
9427 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9428 error_unrecovered++;
9429 netdev_err(bp->dev,
9430 "Recovery failed. Power cycle needed\n");
9431 /* Disconnect this device */
9432 netif_device_detach(bp->dev);
9433 /* Shut down the power */
9434 bnx2x_set_power_state(
9435 bp, PCI_D3hot);
9436 smp_mb();
9437 } else {
9438 bp->recovery_state =
9439 BNX2X_RECOVERY_DONE;
9440 error_recovered++;
9441 smp_mb();
9442 }
9443 bp->eth_stats.recoverable_error =
9444 error_recovered;
9445 bp->eth_stats.unrecoverable_error =
9446 error_unrecovered;
9447
9448 return;
9449 }
9450 }
9451 default:
9452 return;
9453 }
9454 }
9455 }
9456
9457 static int bnx2x_close(struct net_device *dev);
9458
9459 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9460 * scheduled on a general queue in order to prevent a dead lock.
9461 */
9462 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9463 {
9464 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9465
9466 rtnl_lock();
9467
9468 if (!netif_running(bp->dev)) {
9469 rtnl_unlock();
9470 return;
9471 }
9472
9473 /* if stop on error is defined no recovery flows should be executed */
9474 #ifdef BNX2X_STOP_ON_ERROR
9475 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9476 "you will need to reboot when done\n");
9477 goto sp_rtnl_not_reset;
9478 #endif
9479
9480 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9481 /*
9482 * Clear all pending SP commands as we are going to reset the
9483 * function anyway.
9484 */
9485 bp->sp_rtnl_state = 0;
9486 smp_mb();
9487
9488 bnx2x_parity_recover(bp);
9489
9490 rtnl_unlock();
9491 return;
9492 }
9493
9494 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9495 /*
9496 * Clear all pending SP commands as we are going to reset the
9497 * function anyway.
9498 */
9499 bp->sp_rtnl_state = 0;
9500 smp_mb();
9501
9502 bnx2x_nic_unload(bp, UNLOAD_NORMAL, true);
9503 bnx2x_nic_load(bp, LOAD_NORMAL);
9504
9505 rtnl_unlock();
9506 return;
9507 }
9508 #ifdef BNX2X_STOP_ON_ERROR
9509 sp_rtnl_not_reset:
9510 #endif
9511 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9512 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9513 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9514 bnx2x_after_function_update(bp);
9515 /*
9516 * in case of fan failure we need to reset id if the "stop on error"
9517 * debug flag is set, since we trying to prevent permanent overheating
9518 * damage
9519 */
9520 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9521 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9522 netif_device_detach(bp->dev);
9523 bnx2x_close(bp->dev);
9524 rtnl_unlock();
9525 return;
9526 }
9527
9528 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST, &bp->sp_rtnl_state)) {
9529 DP(BNX2X_MSG_SP,
9530 "sending set mcast vf pf channel message from rtnl sp-task\n");
9531 bnx2x_vfpf_set_mcast(bp->dev);
9532 }
9533
9534 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
9535 &bp->sp_rtnl_state)) {
9536 DP(BNX2X_MSG_SP,
9537 "sending set storm rx mode vf pf channel message from rtnl sp-task\n");
9538 bnx2x_vfpf_storm_rx_mode(bp);
9539 }
9540
9541 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN,
9542 &bp->sp_rtnl_state))
9543 bnx2x_pf_set_vfs_vlan(bp);
9544
9545 /* work which needs rtnl lock not-taken (as it takes the lock itself and
9546 * can be called from other contexts as well)
9547 */
9548 rtnl_unlock();
9549
9550 /* enable SR-IOV if applicable */
9551 if (IS_SRIOV(bp) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV,
9552 &bp->sp_rtnl_state)) {
9553 bnx2x_disable_sriov(bp);
9554 bnx2x_enable_sriov(bp);
9555 }
9556 }
9557
9558 static void bnx2x_period_task(struct work_struct *work)
9559 {
9560 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9561
9562 if (!netif_running(bp->dev))
9563 goto period_task_exit;
9564
9565 if (CHIP_REV_IS_SLOW(bp)) {
9566 BNX2X_ERR("period task called on emulation, ignoring\n");
9567 goto period_task_exit;
9568 }
9569
9570 bnx2x_acquire_phy_lock(bp);
9571 /*
9572 * The barrier is needed to ensure the ordering between the writing to
9573 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9574 * the reading here.
9575 */
9576 smp_mb();
9577 if (bp->port.pmf) {
9578 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9579
9580 /* Re-queue task in 1 sec */
9581 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9582 }
9583
9584 bnx2x_release_phy_lock(bp);
9585 period_task_exit:
9586 return;
9587 }
9588
9589 /*
9590 * Init service functions
9591 */
9592
9593 u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9594 {
9595 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9596 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9597 return base + (BP_ABS_FUNC(bp)) * stride;
9598 }
9599
9600 static void bnx2x_prev_unload_close_mac(struct bnx2x *bp,
9601 struct bnx2x_mac_vals *vals)
9602 {
9603 u32 val, base_addr, offset, mask, reset_reg;
9604 bool mac_stopped = false;
9605 u8 port = BP_PORT(bp);
9606
9607 /* reset addresses as they also mark which values were changed */
9608 vals->bmac_addr = 0;
9609 vals->umac_addr = 0;
9610 vals->xmac_addr = 0;
9611 vals->emac_addr = 0;
9612
9613 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9614
9615 if (!CHIP_IS_E3(bp)) {
9616 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9617 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9618 if ((mask & reset_reg) && val) {
9619 u32 wb_data[2];
9620 BNX2X_DEV_INFO("Disable bmac Rx\n");
9621 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9622 : NIG_REG_INGRESS_BMAC0_MEM;
9623 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9624 : BIGMAC_REGISTER_BMAC_CONTROL;
9625
9626 /*
9627 * use rd/wr since we cannot use dmae. This is safe
9628 * since MCP won't access the bus due to the request
9629 * to unload, and no function on the path can be
9630 * loaded at this time.
9631 */
9632 wb_data[0] = REG_RD(bp, base_addr + offset);
9633 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9634 vals->bmac_addr = base_addr + offset;
9635 vals->bmac_val[0] = wb_data[0];
9636 vals->bmac_val[1] = wb_data[1];
9637 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9638 REG_WR(bp, vals->bmac_addr, wb_data[0]);
9639 REG_WR(bp, vals->bmac_addr + 0x4, wb_data[1]);
9640
9641 }
9642 BNX2X_DEV_INFO("Disable emac Rx\n");
9643 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4;
9644 vals->emac_val = REG_RD(bp, vals->emac_addr);
9645 REG_WR(bp, vals->emac_addr, 0);
9646 mac_stopped = true;
9647 } else {
9648 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9649 BNX2X_DEV_INFO("Disable xmac Rx\n");
9650 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9651 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9652 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9653 val & ~(1 << 1));
9654 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9655 val | (1 << 1));
9656 vals->xmac_addr = base_addr + XMAC_REG_CTRL;
9657 vals->xmac_val = REG_RD(bp, vals->xmac_addr);
9658 REG_WR(bp, vals->xmac_addr, 0);
9659 mac_stopped = true;
9660 }
9661 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9662 if (mask & reset_reg) {
9663 BNX2X_DEV_INFO("Disable umac Rx\n");
9664 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9665 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG;
9666 vals->umac_val = REG_RD(bp, vals->umac_addr);
9667 REG_WR(bp, vals->umac_addr, 0);
9668 mac_stopped = true;
9669 }
9670 }
9671
9672 if (mac_stopped)
9673 msleep(20);
9674
9675 }
9676
9677 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9678 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9679 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9680 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9681
9682 static void bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port, u8 inc)
9683 {
9684 u16 rcq, bd;
9685 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9686
9687 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9688 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9689
9690 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9691 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9692
9693 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9694 port, bd, rcq);
9695 }
9696
9697 static int bnx2x_prev_mcp_done(struct bnx2x *bp)
9698 {
9699 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE,
9700 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET);
9701 if (!rc) {
9702 BNX2X_ERR("MCP response failure, aborting\n");
9703 return -EBUSY;
9704 }
9705
9706 return 0;
9707 }
9708
9709 static struct bnx2x_prev_path_list *
9710 bnx2x_prev_path_get_entry(struct bnx2x *bp)
9711 {
9712 struct bnx2x_prev_path_list *tmp_list;
9713
9714 list_for_each_entry(tmp_list, &bnx2x_prev_list, list)
9715 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9716 bp->pdev->bus->number == tmp_list->bus &&
9717 BP_PATH(bp) == tmp_list->path)
9718 return tmp_list;
9719
9720 return NULL;
9721 }
9722
9723 static int bnx2x_prev_path_mark_eeh(struct bnx2x *bp)
9724 {
9725 struct bnx2x_prev_path_list *tmp_list;
9726 int rc;
9727
9728 rc = down_interruptible(&bnx2x_prev_sem);
9729 if (rc) {
9730 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9731 return rc;
9732 }
9733
9734 tmp_list = bnx2x_prev_path_get_entry(bp);
9735 if (tmp_list) {
9736 tmp_list->aer = 1;
9737 rc = 0;
9738 } else {
9739 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
9740 BP_PATH(bp));
9741 }
9742
9743 up(&bnx2x_prev_sem);
9744
9745 return rc;
9746 }
9747
9748 static bool bnx2x_prev_is_path_marked(struct bnx2x *bp)
9749 {
9750 struct bnx2x_prev_path_list *tmp_list;
9751 int rc = false;
9752
9753 if (down_trylock(&bnx2x_prev_sem))
9754 return false;
9755
9756 tmp_list = bnx2x_prev_path_get_entry(bp);
9757 if (tmp_list) {
9758 if (tmp_list->aer) {
9759 DP(NETIF_MSG_HW, "Path %d was marked by AER\n",
9760 BP_PATH(bp));
9761 } else {
9762 rc = true;
9763 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9764 BP_PATH(bp));
9765 }
9766 }
9767
9768 up(&bnx2x_prev_sem);
9769
9770 return rc;
9771 }
9772
9773 static int bnx2x_prev_mark_path(struct bnx2x *bp, bool after_undi)
9774 {
9775 struct bnx2x_prev_path_list *tmp_list;
9776 int rc;
9777
9778 rc = down_interruptible(&bnx2x_prev_sem);
9779 if (rc) {
9780 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9781 return rc;
9782 }
9783
9784 /* Check whether the entry for this path already exists */
9785 tmp_list = bnx2x_prev_path_get_entry(bp);
9786 if (tmp_list) {
9787 if (!tmp_list->aer) {
9788 BNX2X_ERR("Re-Marking the path.\n");
9789 } else {
9790 DP(NETIF_MSG_HW, "Removing AER indication from path %d\n",
9791 BP_PATH(bp));
9792 tmp_list->aer = 0;
9793 }
9794 up(&bnx2x_prev_sem);
9795 return 0;
9796 }
9797 up(&bnx2x_prev_sem);
9798
9799 /* Create an entry for this path and add it */
9800 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9801 if (!tmp_list) {
9802 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9803 return -ENOMEM;
9804 }
9805
9806 tmp_list->bus = bp->pdev->bus->number;
9807 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9808 tmp_list->path = BP_PATH(bp);
9809 tmp_list->aer = 0;
9810 tmp_list->undi = after_undi ? (1 << BP_PORT(bp)) : 0;
9811
9812 rc = down_interruptible(&bnx2x_prev_sem);
9813 if (rc) {
9814 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9815 kfree(tmp_list);
9816 } else {
9817 DP(NETIF_MSG_HW, "Marked path [%d] - finished previous unload\n",
9818 BP_PATH(bp));
9819 list_add(&tmp_list->list, &bnx2x_prev_list);
9820 up(&bnx2x_prev_sem);
9821 }
9822
9823 return rc;
9824 }
9825
9826 static int bnx2x_do_flr(struct bnx2x *bp)
9827 {
9828 int i;
9829 u16 status;
9830 struct pci_dev *dev = bp->pdev;
9831
9832
9833 if (CHIP_IS_E1x(bp)) {
9834 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9835 return -EINVAL;
9836 }
9837
9838 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9839 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9840 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9841 bp->common.bc_ver);
9842 return -EINVAL;
9843 }
9844
9845 /* Wait for Transaction Pending bit clean */
9846 for (i = 0; i < 4; i++) {
9847 if (i)
9848 msleep((1 << (i - 1)) * 100);
9849
9850 pcie_capability_read_word(dev, PCI_EXP_DEVSTA, &status);
9851 if (!(status & PCI_EXP_DEVSTA_TRPND))
9852 goto clear;
9853 }
9854
9855 dev_err(&dev->dev,
9856 "transaction is not cleared; proceeding with reset anyway\n");
9857
9858 clear:
9859
9860 BNX2X_DEV_INFO("Initiating FLR\n");
9861 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9862
9863 return 0;
9864 }
9865
9866 static int bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9867 {
9868 int rc;
9869
9870 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9871
9872 /* Test if previous unload process was already finished for this path */
9873 if (bnx2x_prev_is_path_marked(bp))
9874 return bnx2x_prev_mcp_done(bp);
9875
9876 BNX2X_DEV_INFO("Path is unmarked\n");
9877
9878 /* If function has FLR capabilities, and existing FW version matches
9879 * the one required, then FLR will be sufficient to clean any residue
9880 * left by previous driver
9881 */
9882 rc = bnx2x_nic_load_analyze_req(bp, FW_MSG_CODE_DRV_LOAD_FUNCTION);
9883
9884 if (!rc) {
9885 /* fw version is good */
9886 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9887 rc = bnx2x_do_flr(bp);
9888 }
9889
9890 if (!rc) {
9891 /* FLR was performed */
9892 BNX2X_DEV_INFO("FLR successful\n");
9893 return 0;
9894 }
9895
9896 BNX2X_DEV_INFO("Could not FLR\n");
9897
9898 /* Close the MCP request, return failure*/
9899 rc = bnx2x_prev_mcp_done(bp);
9900 if (!rc)
9901 rc = BNX2X_PREV_WAIT_NEEDED;
9902
9903 return rc;
9904 }
9905
9906 static int bnx2x_prev_unload_common(struct bnx2x *bp)
9907 {
9908 u32 reset_reg, tmp_reg = 0, rc;
9909 bool prev_undi = false;
9910 struct bnx2x_mac_vals mac_vals;
9911
9912 /* It is possible a previous function received 'common' answer,
9913 * but hasn't loaded yet, therefore creating a scenario of
9914 * multiple functions receiving 'common' on the same path.
9915 */
9916 BNX2X_DEV_INFO("Common unload Flow\n");
9917
9918 memset(&mac_vals, 0, sizeof(mac_vals));
9919
9920 if (bnx2x_prev_is_path_marked(bp))
9921 return bnx2x_prev_mcp_done(bp);
9922
9923 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9924
9925 /* Reset should be performed after BRB is emptied */
9926 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9927 u32 timer_count = 1000;
9928
9929 /* Close the MAC Rx to prevent BRB from filling up */
9930 bnx2x_prev_unload_close_mac(bp, &mac_vals);
9931
9932 /* close LLH filters towards the BRB */
9933 bnx2x_set_rx_filter(&bp->link_params, 0);
9934
9935 /* Check if the UNDI driver was previously loaded
9936 * UNDI driver initializes CID offset for normal bell to 0x7
9937 */
9938 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9939 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9940 if (tmp_reg == 0x7) {
9941 BNX2X_DEV_INFO("UNDI previously loaded\n");
9942 prev_undi = true;
9943 /* clear the UNDI indication */
9944 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9945 /* clear possible idle check errors */
9946 REG_RD(bp, NIG_REG_NIG_INT_STS_CLR_0);
9947 }
9948 }
9949 /* wait until BRB is empty */
9950 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9951 while (timer_count) {
9952 u32 prev_brb = tmp_reg;
9953
9954 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9955 if (!tmp_reg)
9956 break;
9957
9958 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9959
9960 /* reset timer as long as BRB actually gets emptied */
9961 if (prev_brb > tmp_reg)
9962 timer_count = 1000;
9963 else
9964 timer_count--;
9965
9966 /* If UNDI resides in memory, manually increment it */
9967 if (prev_undi)
9968 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9969
9970 udelay(10);
9971 }
9972
9973 if (!timer_count)
9974 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9975
9976 }
9977
9978 /* No packets are in the pipeline, path is ready for reset */
9979 bnx2x_reset_common(bp);
9980
9981 if (mac_vals.xmac_addr)
9982 REG_WR(bp, mac_vals.xmac_addr, mac_vals.xmac_val);
9983 if (mac_vals.umac_addr)
9984 REG_WR(bp, mac_vals.umac_addr, mac_vals.umac_val);
9985 if (mac_vals.emac_addr)
9986 REG_WR(bp, mac_vals.emac_addr, mac_vals.emac_val);
9987 if (mac_vals.bmac_addr) {
9988 REG_WR(bp, mac_vals.bmac_addr, mac_vals.bmac_val[0]);
9989 REG_WR(bp, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]);
9990 }
9991
9992 rc = bnx2x_prev_mark_path(bp, prev_undi);
9993 if (rc) {
9994 bnx2x_prev_mcp_done(bp);
9995 return rc;
9996 }
9997
9998 return bnx2x_prev_mcp_done(bp);
9999 }
10000
10001 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
10002 * and boot began, or when kdump kernel was loaded. Either case would invalidate
10003 * the addresses of the transaction, resulting in was-error bit set in the pci
10004 * causing all hw-to-host pcie transactions to timeout. If this happened we want
10005 * to clear the interrupt which detected this from the pglueb and the was done
10006 * bit
10007 */
10008 static void bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
10009 {
10010 if (!CHIP_IS_E1x(bp)) {
10011 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
10012 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
10013 DP(BNX2X_MSG_SP,
10014 "'was error' bit was found to be set in pglueb upon startup. Clearing\n");
10015 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR,
10016 1 << BP_FUNC(bp));
10017 }
10018 }
10019 }
10020
10021 static int bnx2x_prev_unload(struct bnx2x *bp)
10022 {
10023 int time_counter = 10;
10024 u32 rc, fw, hw_lock_reg, hw_lock_val;
10025 struct bnx2x_prev_path_list *prev_list;
10026 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10027
10028 /* clear hw from errors which may have resulted from an interrupted
10029 * dmae transaction.
10030 */
10031 bnx2x_prev_interrupted_dmae(bp);
10032
10033 /* Release previously held locks */
10034 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
10035 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
10036 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
10037
10038 hw_lock_val = (REG_RD(bp, hw_lock_reg));
10039 if (hw_lock_val) {
10040 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
10041 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10042 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
10043 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
10044 }
10045
10046 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10047 REG_WR(bp, hw_lock_reg, 0xffffffff);
10048 } else
10049 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10050
10051 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
10052 BNX2X_DEV_INFO("Release previously held alr\n");
10053 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
10054 }
10055
10056 do {
10057 int aer = 0;
10058 /* Lock MCP using an unload request */
10059 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
10060 if (!fw) {
10061 BNX2X_ERR("MCP response failure, aborting\n");
10062 rc = -EBUSY;
10063 break;
10064 }
10065
10066 rc = down_interruptible(&bnx2x_prev_sem);
10067 if (rc) {
10068 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10069 rc);
10070 } else {
10071 /* If Path is marked by EEH, ignore unload status */
10072 aer = !!(bnx2x_prev_path_get_entry(bp) &&
10073 bnx2x_prev_path_get_entry(bp)->aer);
10074 up(&bnx2x_prev_sem);
10075 }
10076
10077 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON || aer) {
10078 rc = bnx2x_prev_unload_common(bp);
10079 break;
10080 }
10081
10082 /* non-common reply from MCP night require looping */
10083 rc = bnx2x_prev_unload_uncommon(bp);
10084 if (rc != BNX2X_PREV_WAIT_NEEDED)
10085 break;
10086
10087 msleep(20);
10088 } while (--time_counter);
10089
10090 if (!time_counter || rc) {
10091 BNX2X_ERR("Failed unloading previous driver, aborting\n");
10092 rc = -EBUSY;
10093 }
10094
10095 /* Mark function if its port was used to boot from SAN */
10096 prev_list = bnx2x_prev_path_get_entry(bp);
10097 if (prev_list && (prev_list->undi & (1 << BP_PORT(bp))))
10098 bp->link_params.feature_config_flags |=
10099 FEATURE_CONFIG_BOOT_FROM_SAN;
10100
10101 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
10102
10103 return rc;
10104 }
10105
10106 static void bnx2x_get_common_hwinfo(struct bnx2x *bp)
10107 {
10108 u32 val, val2, val3, val4, id, boot_mode;
10109 u16 pmc;
10110
10111 /* Get the chip revision id and number. */
10112 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10113 val = REG_RD(bp, MISC_REG_CHIP_NUM);
10114 id = ((val & 0xffff) << 16);
10115 val = REG_RD(bp, MISC_REG_CHIP_REV);
10116 id |= ((val & 0xf) << 12);
10117
10118 /* Metal is read from PCI regs, but we can't access >=0x400 from
10119 * the configuration space (so we need to reg_rd)
10120 */
10121 val = REG_RD(bp, PCICFG_OFFSET + PCI_ID_VAL3);
10122 id |= (((val >> 24) & 0xf) << 4);
10123 val = REG_RD(bp, MISC_REG_BOND_ID);
10124 id |= (val & 0xf);
10125 bp->common.chip_id = id;
10126
10127 /* force 57811 according to MISC register */
10128 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
10129 if (CHIP_IS_57810(bp))
10130 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
10131 (bp->common.chip_id & 0x0000FFFF);
10132 else if (CHIP_IS_57810_MF(bp))
10133 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
10134 (bp->common.chip_id & 0x0000FFFF);
10135 bp->common.chip_id |= 0x1;
10136 }
10137
10138 /* Set doorbell size */
10139 bp->db_size = (1 << BNX2X_DB_SHIFT);
10140
10141 if (!CHIP_IS_E1x(bp)) {
10142 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
10143 if ((val & 1) == 0)
10144 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
10145 else
10146 val = (val >> 1) & 1;
10147 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
10148 "2_PORT_MODE");
10149 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
10150 CHIP_2_PORT_MODE;
10151
10152 if (CHIP_MODE_IS_4_PORT(bp))
10153 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
10154 else
10155 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
10156 } else {
10157 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
10158 bp->pfid = bp->pf_num; /* 0..7 */
10159 }
10160
10161 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
10162
10163 bp->link_params.chip_id = bp->common.chip_id;
10164 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
10165
10166 val = (REG_RD(bp, 0x2874) & 0x55);
10167 if ((bp->common.chip_id & 0x1) ||
10168 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
10169 bp->flags |= ONE_PORT_FLAG;
10170 BNX2X_DEV_INFO("single port device\n");
10171 }
10172
10173 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
10174 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
10175 (val & MCPR_NVM_CFG4_FLASH_SIZE));
10176 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
10177 bp->common.flash_size, bp->common.flash_size);
10178
10179 bnx2x_init_shmem(bp);
10180
10181
10182
10183 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
10184 MISC_REG_GENERIC_CR_1 :
10185 MISC_REG_GENERIC_CR_0));
10186
10187 bp->link_params.shmem_base = bp->common.shmem_base;
10188 bp->link_params.shmem2_base = bp->common.shmem2_base;
10189 if (SHMEM2_RD(bp, size) >
10190 (u32)offsetof(struct shmem2_region, lfa_host_addr[BP_PORT(bp)]))
10191 bp->link_params.lfa_base =
10192 REG_RD(bp, bp->common.shmem2_base +
10193 (u32)offsetof(struct shmem2_region,
10194 lfa_host_addr[BP_PORT(bp)]));
10195 else
10196 bp->link_params.lfa_base = 0;
10197 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
10198 bp->common.shmem_base, bp->common.shmem2_base);
10199
10200 if (!bp->common.shmem_base) {
10201 BNX2X_DEV_INFO("MCP not active\n");
10202 bp->flags |= NO_MCP_FLAG;
10203 return;
10204 }
10205
10206 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
10207 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
10208
10209 bp->link_params.hw_led_mode = ((bp->common.hw_config &
10210 SHARED_HW_CFG_LED_MODE_MASK) >>
10211 SHARED_HW_CFG_LED_MODE_SHIFT);
10212
10213 bp->link_params.feature_config_flags = 0;
10214 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
10215 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
10216 bp->link_params.feature_config_flags |=
10217 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10218 else
10219 bp->link_params.feature_config_flags &=
10220 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
10221
10222 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
10223 bp->common.bc_ver = val;
10224 BNX2X_DEV_INFO("bc_ver %X\n", val);
10225 if (val < BNX2X_BC_VER) {
10226 /* for now only warn
10227 * later we might need to enforce this */
10228 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
10229 BNX2X_BC_VER, val);
10230 }
10231 bp->link_params.feature_config_flags |=
10232 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
10233 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
10234
10235 bp->link_params.feature_config_flags |=
10236 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
10237 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
10238 bp->link_params.feature_config_flags |=
10239 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
10240 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
10241 bp->link_params.feature_config_flags |=
10242 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
10243 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
10244
10245 bp->link_params.feature_config_flags |=
10246 (val >= REQ_BC_VER_4_MT_SUPPORTED) ?
10247 FEATURE_CONFIG_MT_SUPPORT : 0;
10248
10249 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
10250 BC_SUPPORTS_PFC_STATS : 0;
10251
10252 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
10253 BC_SUPPORTS_FCOE_FEATURES : 0;
10254
10255 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
10256 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
10257 boot_mode = SHMEM_RD(bp,
10258 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
10259 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
10260 switch (boot_mode) {
10261 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
10262 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
10263 break;
10264 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
10265 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
10266 break;
10267 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
10268 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
10269 break;
10270 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
10271 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
10272 break;
10273 }
10274
10275 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
10276 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
10277
10278 BNX2X_DEV_INFO("%sWoL capable\n",
10279 (bp->flags & NO_WOL_FLAG) ? "not " : "");
10280
10281 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
10282 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
10283 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
10284 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
10285
10286 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
10287 val, val2, val3, val4);
10288 }
10289
10290 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
10291 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
10292
10293 static int bnx2x_get_igu_cam_info(struct bnx2x *bp)
10294 {
10295 int pfid = BP_FUNC(bp);
10296 int igu_sb_id;
10297 u32 val;
10298 u8 fid, igu_sb_cnt = 0;
10299
10300 bp->igu_base_sb = 0xff;
10301 if (CHIP_INT_MODE_IS_BC(bp)) {
10302 int vn = BP_VN(bp);
10303 igu_sb_cnt = bp->igu_sb_cnt;
10304 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
10305 FP_SB_MAX_E1x;
10306
10307 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
10308 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
10309
10310 return 0;
10311 }
10312
10313 /* IGU in normal mode - read CAM */
10314 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
10315 igu_sb_id++) {
10316 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
10317 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
10318 continue;
10319 fid = IGU_FID(val);
10320 if ((fid & IGU_FID_ENCODE_IS_PF)) {
10321 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
10322 continue;
10323 if (IGU_VEC(val) == 0)
10324 /* default status block */
10325 bp->igu_dsb_id = igu_sb_id;
10326 else {
10327 if (bp->igu_base_sb == 0xff)
10328 bp->igu_base_sb = igu_sb_id;
10329 igu_sb_cnt++;
10330 }
10331 }
10332 }
10333
10334 #ifdef CONFIG_PCI_MSI
10335 /* Due to new PF resource allocation by MFW T7.4 and above, it's
10336 * optional that number of CAM entries will not be equal to the value
10337 * advertised in PCI.
10338 * Driver should use the minimal value of both as the actual status
10339 * block count
10340 */
10341 bp->igu_sb_cnt = min_t(int, bp->igu_sb_cnt, igu_sb_cnt);
10342 #endif
10343
10344 if (igu_sb_cnt == 0) {
10345 BNX2X_ERR("CAM configuration error\n");
10346 return -EINVAL;
10347 }
10348
10349 return 0;
10350 }
10351
10352 static void bnx2x_link_settings_supported(struct bnx2x *bp, u32 switch_cfg)
10353 {
10354 int cfg_size = 0, idx, port = BP_PORT(bp);
10355
10356 /* Aggregation of supported attributes of all external phys */
10357 bp->port.supported[0] = 0;
10358 bp->port.supported[1] = 0;
10359 switch (bp->link_params.num_phys) {
10360 case 1:
10361 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
10362 cfg_size = 1;
10363 break;
10364 case 2:
10365 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
10366 cfg_size = 1;
10367 break;
10368 case 3:
10369 if (bp->link_params.multi_phy_config &
10370 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
10371 bp->port.supported[1] =
10372 bp->link_params.phy[EXT_PHY1].supported;
10373 bp->port.supported[0] =
10374 bp->link_params.phy[EXT_PHY2].supported;
10375 } else {
10376 bp->port.supported[0] =
10377 bp->link_params.phy[EXT_PHY1].supported;
10378 bp->port.supported[1] =
10379 bp->link_params.phy[EXT_PHY2].supported;
10380 }
10381 cfg_size = 2;
10382 break;
10383 }
10384
10385 if (!(bp->port.supported[0] || bp->port.supported[1])) {
10386 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
10387 SHMEM_RD(bp,
10388 dev_info.port_hw_config[port].external_phy_config),
10389 SHMEM_RD(bp,
10390 dev_info.port_hw_config[port].external_phy_config2));
10391 return;
10392 }
10393
10394 if (CHIP_IS_E3(bp))
10395 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
10396 else {
10397 switch (switch_cfg) {
10398 case SWITCH_CFG_1G:
10399 bp->port.phy_addr = REG_RD(
10400 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
10401 break;
10402 case SWITCH_CFG_10G:
10403 bp->port.phy_addr = REG_RD(
10404 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
10405 break;
10406 default:
10407 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
10408 bp->port.link_config[0]);
10409 return;
10410 }
10411 }
10412 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
10413 /* mask what we support according to speed_cap_mask per configuration */
10414 for (idx = 0; idx < cfg_size; idx++) {
10415 if (!(bp->link_params.speed_cap_mask[idx] &
10416 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
10417 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
10418
10419 if (!(bp->link_params.speed_cap_mask[idx] &
10420 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
10421 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
10422
10423 if (!(bp->link_params.speed_cap_mask[idx] &
10424 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
10425 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
10426
10427 if (!(bp->link_params.speed_cap_mask[idx] &
10428 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
10429 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
10430
10431 if (!(bp->link_params.speed_cap_mask[idx] &
10432 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
10433 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
10434 SUPPORTED_1000baseT_Full);
10435
10436 if (!(bp->link_params.speed_cap_mask[idx] &
10437 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
10438 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
10439
10440 if (!(bp->link_params.speed_cap_mask[idx] &
10441 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
10442 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
10443
10444 }
10445
10446 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
10447 bp->port.supported[1]);
10448 }
10449
10450 static void bnx2x_link_settings_requested(struct bnx2x *bp)
10451 {
10452 u32 link_config, idx, cfg_size = 0;
10453 bp->port.advertising[0] = 0;
10454 bp->port.advertising[1] = 0;
10455 switch (bp->link_params.num_phys) {
10456 case 1:
10457 case 2:
10458 cfg_size = 1;
10459 break;
10460 case 3:
10461 cfg_size = 2;
10462 break;
10463 }
10464 for (idx = 0; idx < cfg_size; idx++) {
10465 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
10466 link_config = bp->port.link_config[idx];
10467 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
10468 case PORT_FEATURE_LINK_SPEED_AUTO:
10469 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
10470 bp->link_params.req_line_speed[idx] =
10471 SPEED_AUTO_NEG;
10472 bp->port.advertising[idx] |=
10473 bp->port.supported[idx];
10474 if (bp->link_params.phy[EXT_PHY1].type ==
10475 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
10476 bp->port.advertising[idx] |=
10477 (SUPPORTED_100baseT_Half |
10478 SUPPORTED_100baseT_Full);
10479 } else {
10480 /* force 10G, no AN */
10481 bp->link_params.req_line_speed[idx] =
10482 SPEED_10000;
10483 bp->port.advertising[idx] |=
10484 (ADVERTISED_10000baseT_Full |
10485 ADVERTISED_FIBRE);
10486 continue;
10487 }
10488 break;
10489
10490 case PORT_FEATURE_LINK_SPEED_10M_FULL:
10491 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
10492 bp->link_params.req_line_speed[idx] =
10493 SPEED_10;
10494 bp->port.advertising[idx] |=
10495 (ADVERTISED_10baseT_Full |
10496 ADVERTISED_TP);
10497 } else {
10498 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10499 link_config,
10500 bp->link_params.speed_cap_mask[idx]);
10501 return;
10502 }
10503 break;
10504
10505 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10506 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10507 bp->link_params.req_line_speed[idx] =
10508 SPEED_10;
10509 bp->link_params.req_duplex[idx] =
10510 DUPLEX_HALF;
10511 bp->port.advertising[idx] |=
10512 (ADVERTISED_10baseT_Half |
10513 ADVERTISED_TP);
10514 } else {
10515 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10516 link_config,
10517 bp->link_params.speed_cap_mask[idx]);
10518 return;
10519 }
10520 break;
10521
10522 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10523 if (bp->port.supported[idx] &
10524 SUPPORTED_100baseT_Full) {
10525 bp->link_params.req_line_speed[idx] =
10526 SPEED_100;
10527 bp->port.advertising[idx] |=
10528 (ADVERTISED_100baseT_Full |
10529 ADVERTISED_TP);
10530 } else {
10531 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10532 link_config,
10533 bp->link_params.speed_cap_mask[idx]);
10534 return;
10535 }
10536 break;
10537
10538 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10539 if (bp->port.supported[idx] &
10540 SUPPORTED_100baseT_Half) {
10541 bp->link_params.req_line_speed[idx] =
10542 SPEED_100;
10543 bp->link_params.req_duplex[idx] =
10544 DUPLEX_HALF;
10545 bp->port.advertising[idx] |=
10546 (ADVERTISED_100baseT_Half |
10547 ADVERTISED_TP);
10548 } else {
10549 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10550 link_config,
10551 bp->link_params.speed_cap_mask[idx]);
10552 return;
10553 }
10554 break;
10555
10556 case PORT_FEATURE_LINK_SPEED_1G:
10557 if (bp->port.supported[idx] &
10558 SUPPORTED_1000baseT_Full) {
10559 bp->link_params.req_line_speed[idx] =
10560 SPEED_1000;
10561 bp->port.advertising[idx] |=
10562 (ADVERTISED_1000baseT_Full |
10563 ADVERTISED_TP);
10564 } else {
10565 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10566 link_config,
10567 bp->link_params.speed_cap_mask[idx]);
10568 return;
10569 }
10570 break;
10571
10572 case PORT_FEATURE_LINK_SPEED_2_5G:
10573 if (bp->port.supported[idx] &
10574 SUPPORTED_2500baseX_Full) {
10575 bp->link_params.req_line_speed[idx] =
10576 SPEED_2500;
10577 bp->port.advertising[idx] |=
10578 (ADVERTISED_2500baseX_Full |
10579 ADVERTISED_TP);
10580 } else {
10581 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10582 link_config,
10583 bp->link_params.speed_cap_mask[idx]);
10584 return;
10585 }
10586 break;
10587
10588 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10589 if (bp->port.supported[idx] &
10590 SUPPORTED_10000baseT_Full) {
10591 bp->link_params.req_line_speed[idx] =
10592 SPEED_10000;
10593 bp->port.advertising[idx] |=
10594 (ADVERTISED_10000baseT_Full |
10595 ADVERTISED_FIBRE);
10596 } else {
10597 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10598 link_config,
10599 bp->link_params.speed_cap_mask[idx]);
10600 return;
10601 }
10602 break;
10603 case PORT_FEATURE_LINK_SPEED_20G:
10604 bp->link_params.req_line_speed[idx] = SPEED_20000;
10605
10606 break;
10607 default:
10608 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10609 link_config);
10610 bp->link_params.req_line_speed[idx] =
10611 SPEED_AUTO_NEG;
10612 bp->port.advertising[idx] =
10613 bp->port.supported[idx];
10614 break;
10615 }
10616
10617 bp->link_params.req_flow_ctrl[idx] = (link_config &
10618 PORT_FEATURE_FLOW_CONTROL_MASK);
10619 if (bp->link_params.req_flow_ctrl[idx] ==
10620 BNX2X_FLOW_CTRL_AUTO) {
10621 if (!(bp->port.supported[idx] & SUPPORTED_Autoneg))
10622 bp->link_params.req_flow_ctrl[idx] =
10623 BNX2X_FLOW_CTRL_NONE;
10624 else
10625 bnx2x_set_requested_fc(bp);
10626 }
10627
10628 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10629 bp->link_params.req_line_speed[idx],
10630 bp->link_params.req_duplex[idx],
10631 bp->link_params.req_flow_ctrl[idx],
10632 bp->port.advertising[idx]);
10633 }
10634 }
10635
10636 static void bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10637 {
10638 __be16 mac_hi_be = cpu_to_be16(mac_hi);
10639 __be32 mac_lo_be = cpu_to_be32(mac_lo);
10640 memcpy(mac_buf, &mac_hi_be, sizeof(mac_hi_be));
10641 memcpy(mac_buf + sizeof(mac_hi_be), &mac_lo_be, sizeof(mac_lo_be));
10642 }
10643
10644 static void bnx2x_get_port_hwinfo(struct bnx2x *bp)
10645 {
10646 int port = BP_PORT(bp);
10647 u32 config;
10648 u32 ext_phy_type, ext_phy_config, eee_mode;
10649
10650 bp->link_params.bp = bp;
10651 bp->link_params.port = port;
10652
10653 bp->link_params.lane_config =
10654 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10655
10656 bp->link_params.speed_cap_mask[0] =
10657 SHMEM_RD(bp,
10658 dev_info.port_hw_config[port].speed_capability_mask);
10659 bp->link_params.speed_cap_mask[1] =
10660 SHMEM_RD(bp,
10661 dev_info.port_hw_config[port].speed_capability_mask2);
10662 bp->port.link_config[0] =
10663 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10664
10665 bp->port.link_config[1] =
10666 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10667
10668 bp->link_params.multi_phy_config =
10669 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10670 /* If the device is capable of WoL, set the default state according
10671 * to the HW
10672 */
10673 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10674 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10675 (config & PORT_FEATURE_WOL_ENABLED));
10676
10677 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10678 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE && !IS_MF(bp))
10679 bp->flags |= NO_ISCSI_FLAG;
10680 if ((config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) ==
10681 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI && !(IS_MF(bp)))
10682 bp->flags |= NO_FCOE_FLAG;
10683
10684 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10685 bp->link_params.lane_config,
10686 bp->link_params.speed_cap_mask[0],
10687 bp->port.link_config[0]);
10688
10689 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10690 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10691 bnx2x_phy_probe(&bp->link_params);
10692 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10693
10694 bnx2x_link_settings_requested(bp);
10695
10696 /*
10697 * If connected directly, work with the internal PHY, otherwise, work
10698 * with the external PHY
10699 */
10700 ext_phy_config =
10701 SHMEM_RD(bp,
10702 dev_info.port_hw_config[port].external_phy_config);
10703 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10704 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10705 bp->mdio.prtad = bp->port.phy_addr;
10706
10707 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10708 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10709 bp->mdio.prtad =
10710 XGXS_EXT_PHY_ADDR(ext_phy_config);
10711
10712 /* Configure link feature according to nvram value */
10713 eee_mode = (((SHMEM_RD(bp, dev_info.
10714 port_feature_config[port].eee_power_mode)) &
10715 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10716 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10717 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10718 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10719 EEE_MODE_ENABLE_LPI |
10720 EEE_MODE_OUTPUT_TIME;
10721 } else {
10722 bp->link_params.eee_mode = 0;
10723 }
10724 }
10725
10726 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10727 {
10728 u32 no_flags = NO_ISCSI_FLAG;
10729 int port = BP_PORT(bp);
10730 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10731 drv_lic_key[port].max_iscsi_conn);
10732
10733 if (!CNIC_SUPPORT(bp)) {
10734 bp->flags |= no_flags;
10735 return;
10736 }
10737
10738 /* Get the number of maximum allowed iSCSI connections */
10739 bp->cnic_eth_dev.max_iscsi_conn =
10740 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10741 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10742
10743 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10744 bp->cnic_eth_dev.max_iscsi_conn);
10745
10746 /*
10747 * If maximum allowed number of connections is zero -
10748 * disable the feature.
10749 */
10750 if (!bp->cnic_eth_dev.max_iscsi_conn)
10751 bp->flags |= no_flags;
10752
10753 }
10754
10755 static void bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10756 {
10757 /* Port info */
10758 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10759 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10760 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10761 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10762
10763 /* Node info */
10764 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10765 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10766 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10767 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10768 }
10769 static void bnx2x_get_fcoe_info(struct bnx2x *bp)
10770 {
10771 int port = BP_PORT(bp);
10772 int func = BP_ABS_FUNC(bp);
10773 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10774 drv_lic_key[port].max_fcoe_conn);
10775
10776 if (!CNIC_SUPPORT(bp)) {
10777 bp->flags |= NO_FCOE_FLAG;
10778 return;
10779 }
10780
10781 /* Get the number of maximum allowed FCoE connections */
10782 bp->cnic_eth_dev.max_fcoe_conn =
10783 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10784 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10785
10786 /* Read the WWN: */
10787 if (!IS_MF(bp)) {
10788 /* Port info */
10789 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10790 SHMEM_RD(bp,
10791 dev_info.port_hw_config[port].
10792 fcoe_wwn_port_name_upper);
10793 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10794 SHMEM_RD(bp,
10795 dev_info.port_hw_config[port].
10796 fcoe_wwn_port_name_lower);
10797
10798 /* Node info */
10799 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10800 SHMEM_RD(bp,
10801 dev_info.port_hw_config[port].
10802 fcoe_wwn_node_name_upper);
10803 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10804 SHMEM_RD(bp,
10805 dev_info.port_hw_config[port].
10806 fcoe_wwn_node_name_lower);
10807 } else if (!IS_MF_SD(bp)) {
10808 /*
10809 * Read the WWN info only if the FCoE feature is enabled for
10810 * this function.
10811 */
10812 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10813 bnx2x_get_ext_wwn_info(bp, func);
10814
10815 } else if (IS_MF_FCOE_SD(bp) && !CHIP_IS_E1x(bp)) {
10816 bnx2x_get_ext_wwn_info(bp, func);
10817 }
10818
10819 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10820
10821 /*
10822 * If maximum allowed number of connections is zero -
10823 * disable the feature.
10824 */
10825 if (!bp->cnic_eth_dev.max_fcoe_conn)
10826 bp->flags |= NO_FCOE_FLAG;
10827 }
10828
10829 static void bnx2x_get_cnic_info(struct bnx2x *bp)
10830 {
10831 /*
10832 * iSCSI may be dynamically disabled but reading
10833 * info here we will decrease memory usage by driver
10834 * if the feature is disabled for good
10835 */
10836 bnx2x_get_iscsi_info(bp);
10837 bnx2x_get_fcoe_info(bp);
10838 }
10839
10840 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x *bp)
10841 {
10842 u32 val, val2;
10843 int func = BP_ABS_FUNC(bp);
10844 int port = BP_PORT(bp);
10845 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10846 u8 *fip_mac = bp->fip_mac;
10847
10848 if (IS_MF(bp)) {
10849 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10850 * FCoE MAC then the appropriate feature should be disabled.
10851 * In non SD mode features configuration comes from struct
10852 * func_ext_config.
10853 */
10854 if (!IS_MF_SD(bp) && !CHIP_IS_E1x(bp)) {
10855 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10856 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10857 val2 = MF_CFG_RD(bp, func_ext_config[func].
10858 iscsi_mac_addr_upper);
10859 val = MF_CFG_RD(bp, func_ext_config[func].
10860 iscsi_mac_addr_lower);
10861 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10862 BNX2X_DEV_INFO
10863 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10864 } else {
10865 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10866 }
10867
10868 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10869 val2 = MF_CFG_RD(bp, func_ext_config[func].
10870 fcoe_mac_addr_upper);
10871 val = MF_CFG_RD(bp, func_ext_config[func].
10872 fcoe_mac_addr_lower);
10873 bnx2x_set_mac_buf(fip_mac, val, val2);
10874 BNX2X_DEV_INFO
10875 ("Read FCoE L2 MAC: %pM\n", fip_mac);
10876 } else {
10877 bp->flags |= NO_FCOE_FLAG;
10878 }
10879
10880 bp->mf_ext_config = cfg;
10881
10882 } else { /* SD MODE */
10883 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10884 /* use primary mac as iscsi mac */
10885 memcpy(iscsi_mac, bp->dev->dev_addr, ETH_ALEN);
10886
10887 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10888 BNX2X_DEV_INFO
10889 ("Read iSCSI MAC: %pM\n", iscsi_mac);
10890 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp)) {
10891 /* use primary mac as fip mac */
10892 memcpy(fip_mac, bp->dev->dev_addr, ETH_ALEN);
10893 BNX2X_DEV_INFO("SD FCoE MODE\n");
10894 BNX2X_DEV_INFO
10895 ("Read FIP MAC: %pM\n", fip_mac);
10896 }
10897 }
10898
10899 /* If this is a storage-only interface, use SAN mac as
10900 * primary MAC. Notice that for SD this is already the case,
10901 * as the SAN mac was copied from the primary MAC.
10902 */
10903 if (IS_MF_FCOE_AFEX(bp))
10904 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10905 } else {
10906 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10907 iscsi_mac_upper);
10908 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10909 iscsi_mac_lower);
10910 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10911
10912 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10913 fcoe_fip_mac_upper);
10914 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10915 fcoe_fip_mac_lower);
10916 bnx2x_set_mac_buf(fip_mac, val, val2);
10917 }
10918
10919 /* Disable iSCSI OOO if MAC configuration is invalid. */
10920 if (!is_valid_ether_addr(iscsi_mac)) {
10921 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10922 memset(iscsi_mac, 0, ETH_ALEN);
10923 }
10924
10925 /* Disable FCoE if MAC configuration is invalid. */
10926 if (!is_valid_ether_addr(fip_mac)) {
10927 bp->flags |= NO_FCOE_FLAG;
10928 memset(bp->fip_mac, 0, ETH_ALEN);
10929 }
10930 }
10931
10932 static void bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10933 {
10934 u32 val, val2;
10935 int func = BP_ABS_FUNC(bp);
10936 int port = BP_PORT(bp);
10937
10938 /* Zero primary MAC configuration */
10939 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10940
10941 if (BP_NOMCP(bp)) {
10942 BNX2X_ERROR("warning: random MAC workaround active\n");
10943 eth_hw_addr_random(bp->dev);
10944 } else if (IS_MF(bp)) {
10945 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10946 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10947 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10948 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10949 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10950
10951 if (CNIC_SUPPORT(bp))
10952 bnx2x_get_cnic_mac_hwinfo(bp);
10953 } else {
10954 /* in SF read MACs from port configuration */
10955 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10956 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10957 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10958
10959 if (CNIC_SUPPORT(bp))
10960 bnx2x_get_cnic_mac_hwinfo(bp);
10961 }
10962
10963 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10964
10965 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10966 dev_err(&bp->pdev->dev,
10967 "bad Ethernet MAC address configuration: %pM\n"
10968 "change it manually before bringing up the appropriate network interface\n",
10969 bp->dev->dev_addr);
10970 }
10971
10972 static bool bnx2x_get_dropless_info(struct bnx2x *bp)
10973 {
10974 int tmp;
10975 u32 cfg;
10976
10977 if (IS_MF(bp) && !CHIP_IS_E1x(bp)) {
10978 /* Take function: tmp = func */
10979 tmp = BP_ABS_FUNC(bp);
10980 cfg = MF_CFG_RD(bp, func_ext_config[tmp].func_cfg);
10981 cfg = !!(cfg & MACP_FUNC_CFG_PAUSE_ON_HOST_RING);
10982 } else {
10983 /* Take port: tmp = port */
10984 tmp = BP_PORT(bp);
10985 cfg = SHMEM_RD(bp,
10986 dev_info.port_hw_config[tmp].generic_features);
10987 cfg = !!(cfg & PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED);
10988 }
10989 return cfg;
10990 }
10991
10992 static int bnx2x_get_hwinfo(struct bnx2x *bp)
10993 {
10994 int /*abs*/func = BP_ABS_FUNC(bp);
10995 int vn;
10996 u32 val = 0;
10997 int rc = 0;
10998
10999 bnx2x_get_common_hwinfo(bp);
11000
11001 /*
11002 * initialize IGU parameters
11003 */
11004 if (CHIP_IS_E1x(bp)) {
11005 bp->common.int_block = INT_BLOCK_HC;
11006
11007 bp->igu_dsb_id = DEF_SB_IGU_ID;
11008 bp->igu_base_sb = 0;
11009 } else {
11010 bp->common.int_block = INT_BLOCK_IGU;
11011
11012 /* do not allow device reset during IGU info preocessing */
11013 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11014
11015 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
11016
11017 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11018 int tout = 5000;
11019
11020 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11021
11022 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
11023 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
11024 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
11025
11026 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11027 tout--;
11028 usleep_range(1000, 2000);
11029 }
11030
11031 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
11032 dev_err(&bp->pdev->dev,
11033 "FORCING Normal Mode failed!!!\n");
11034 bnx2x_release_hw_lock(bp,
11035 HW_LOCK_RESOURCE_RESET);
11036 return -EPERM;
11037 }
11038 }
11039
11040 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
11041 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11042 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
11043 } else
11044 BNX2X_DEV_INFO("IGU Normal Mode\n");
11045
11046 rc = bnx2x_get_igu_cam_info(bp);
11047 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
11048 if (rc)
11049 return rc;
11050 }
11051
11052 /*
11053 * set base FW non-default (fast path) status block id, this value is
11054 * used to initialize the fw_sb_id saved on the fp/queue structure to
11055 * determine the id used by the FW.
11056 */
11057 if (CHIP_IS_E1x(bp))
11058 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
11059 else /*
11060 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11061 * the same queue are indicated on the same IGU SB). So we prefer
11062 * FW and IGU SBs to be the same value.
11063 */
11064 bp->base_fw_ndsb = bp->igu_base_sb;
11065
11066 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
11067 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
11068 bp->igu_sb_cnt, bp->base_fw_ndsb);
11069
11070 /*
11071 * Initialize MF configuration
11072 */
11073
11074 bp->mf_ov = 0;
11075 bp->mf_mode = 0;
11076 vn = BP_VN(bp);
11077
11078 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
11079 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
11080 bp->common.shmem2_base, SHMEM2_RD(bp, size),
11081 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
11082
11083 if (SHMEM2_HAS(bp, mf_cfg_addr))
11084 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
11085 else
11086 bp->common.mf_cfg_base = bp->common.shmem_base +
11087 offsetof(struct shmem_region, func_mb) +
11088 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
11089 /*
11090 * get mf configuration:
11091 * 1. existence of MF configuration
11092 * 2. MAC address must be legal (check only upper bytes)
11093 * for Switch-Independent mode;
11094 * OVLAN must be legal for Switch-Dependent mode
11095 * 3. SF_MODE configures specific MF mode
11096 */
11097 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11098 /* get mf configuration */
11099 val = SHMEM_RD(bp,
11100 dev_info.shared_feature_config.config);
11101 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
11102
11103 switch (val) {
11104 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
11105 val = MF_CFG_RD(bp, func_mf_config[func].
11106 mac_upper);
11107 /* check for legal mac (upper bytes)*/
11108 if (val != 0xffff) {
11109 bp->mf_mode = MULTI_FUNCTION_SI;
11110 bp->mf_config[vn] = MF_CFG_RD(bp,
11111 func_mf_config[func].config);
11112 } else
11113 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11114 break;
11115 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
11116 if ((!CHIP_IS_E1x(bp)) &&
11117 (MF_CFG_RD(bp, func_mf_config[func].
11118 mac_upper) != 0xffff) &&
11119 (SHMEM2_HAS(bp,
11120 afex_driver_support))) {
11121 bp->mf_mode = MULTI_FUNCTION_AFEX;
11122 bp->mf_config[vn] = MF_CFG_RD(bp,
11123 func_mf_config[func].config);
11124 } else {
11125 BNX2X_DEV_INFO("can not configure afex mode\n");
11126 }
11127 break;
11128 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
11129 /* get OV configuration */
11130 val = MF_CFG_RD(bp,
11131 func_mf_config[FUNC_0].e1hov_tag);
11132 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
11133
11134 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11135 bp->mf_mode = MULTI_FUNCTION_SD;
11136 bp->mf_config[vn] = MF_CFG_RD(bp,
11137 func_mf_config[func].config);
11138 } else
11139 BNX2X_DEV_INFO("illegal OV for SD\n");
11140 break;
11141 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF:
11142 bp->mf_config[vn] = 0;
11143 break;
11144 default:
11145 /* Unknown configuration: reset mf_config */
11146 bp->mf_config[vn] = 0;
11147 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
11148 }
11149 }
11150
11151 BNX2X_DEV_INFO("%s function mode\n",
11152 IS_MF(bp) ? "multi" : "single");
11153
11154 switch (bp->mf_mode) {
11155 case MULTI_FUNCTION_SD:
11156 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
11157 FUNC_MF_CFG_E1HOV_TAG_MASK;
11158 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
11159 bp->mf_ov = val;
11160 bp->path_has_ovlan = true;
11161
11162 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
11163 func, bp->mf_ov, bp->mf_ov);
11164 } else {
11165 dev_err(&bp->pdev->dev,
11166 "No valid MF OV for func %d, aborting\n",
11167 func);
11168 return -EPERM;
11169 }
11170 break;
11171 case MULTI_FUNCTION_AFEX:
11172 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
11173 break;
11174 case MULTI_FUNCTION_SI:
11175 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
11176 func);
11177 break;
11178 default:
11179 if (vn) {
11180 dev_err(&bp->pdev->dev,
11181 "VN %d is in a single function mode, aborting\n",
11182 vn);
11183 return -EPERM;
11184 }
11185 break;
11186 }
11187
11188 /* check if other port on the path needs ovlan:
11189 * Since MF configuration is shared between ports
11190 * Possible mixed modes are only
11191 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
11192 */
11193 if (CHIP_MODE_IS_4_PORT(bp) &&
11194 !bp->path_has_ovlan &&
11195 !IS_MF(bp) &&
11196 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
11197 u8 other_port = !BP_PORT(bp);
11198 u8 other_func = BP_PATH(bp) + 2*other_port;
11199 val = MF_CFG_RD(bp,
11200 func_mf_config[other_func].e1hov_tag);
11201 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
11202 bp->path_has_ovlan = true;
11203 }
11204 }
11205
11206 /* adjust igu_sb_cnt to MF for E1x */
11207 if (CHIP_IS_E1x(bp) && IS_MF(bp))
11208 bp->igu_sb_cnt /= E1HVN_MAX;
11209
11210 /* port info */
11211 bnx2x_get_port_hwinfo(bp);
11212
11213 /* Get MAC addresses */
11214 bnx2x_get_mac_hwinfo(bp);
11215
11216 bnx2x_get_cnic_info(bp);
11217
11218 return rc;
11219 }
11220
11221 static void bnx2x_read_fwinfo(struct bnx2x *bp)
11222 {
11223 int cnt, i, block_end, rodi;
11224 char vpd_start[BNX2X_VPD_LEN+1];
11225 char str_id_reg[VENDOR_ID_LEN+1];
11226 char str_id_cap[VENDOR_ID_LEN+1];
11227 char *vpd_data;
11228 char *vpd_extended_data = NULL;
11229 u8 len;
11230
11231 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
11232 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
11233
11234 if (cnt < BNX2X_VPD_LEN)
11235 goto out_not_found;
11236
11237 /* VPD RO tag should be first tag after identifier string, hence
11238 * we should be able to find it in first BNX2X_VPD_LEN chars
11239 */
11240 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
11241 PCI_VPD_LRDT_RO_DATA);
11242 if (i < 0)
11243 goto out_not_found;
11244
11245 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
11246 pci_vpd_lrdt_size(&vpd_start[i]);
11247
11248 i += PCI_VPD_LRDT_TAG_SIZE;
11249
11250 if (block_end > BNX2X_VPD_LEN) {
11251 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
11252 if (vpd_extended_data == NULL)
11253 goto out_not_found;
11254
11255 /* read rest of vpd image into vpd_extended_data */
11256 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
11257 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
11258 block_end - BNX2X_VPD_LEN,
11259 vpd_extended_data + BNX2X_VPD_LEN);
11260 if (cnt < (block_end - BNX2X_VPD_LEN))
11261 goto out_not_found;
11262 vpd_data = vpd_extended_data;
11263 } else
11264 vpd_data = vpd_start;
11265
11266 /* now vpd_data holds full vpd content in both cases */
11267
11268 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11269 PCI_VPD_RO_KEYWORD_MFR_ID);
11270 if (rodi < 0)
11271 goto out_not_found;
11272
11273 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11274
11275 if (len != VENDOR_ID_LEN)
11276 goto out_not_found;
11277
11278 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11279
11280 /* vendor specific info */
11281 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
11282 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
11283 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
11284 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
11285
11286 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
11287 PCI_VPD_RO_KEYWORD_VENDOR0);
11288 if (rodi >= 0) {
11289 len = pci_vpd_info_field_size(&vpd_data[rodi]);
11290
11291 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
11292
11293 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
11294 memcpy(bp->fw_ver, &vpd_data[rodi], len);
11295 bp->fw_ver[len] = ' ';
11296 }
11297 }
11298 kfree(vpd_extended_data);
11299 return;
11300 }
11301 out_not_found:
11302 kfree(vpd_extended_data);
11303 return;
11304 }
11305
11306 static void bnx2x_set_modes_bitmap(struct bnx2x *bp)
11307 {
11308 u32 flags = 0;
11309
11310 if (CHIP_REV_IS_FPGA(bp))
11311 SET_FLAGS(flags, MODE_FPGA);
11312 else if (CHIP_REV_IS_EMUL(bp))
11313 SET_FLAGS(flags, MODE_EMUL);
11314 else
11315 SET_FLAGS(flags, MODE_ASIC);
11316
11317 if (CHIP_MODE_IS_4_PORT(bp))
11318 SET_FLAGS(flags, MODE_PORT4);
11319 else
11320 SET_FLAGS(flags, MODE_PORT2);
11321
11322 if (CHIP_IS_E2(bp))
11323 SET_FLAGS(flags, MODE_E2);
11324 else if (CHIP_IS_E3(bp)) {
11325 SET_FLAGS(flags, MODE_E3);
11326 if (CHIP_REV(bp) == CHIP_REV_Ax)
11327 SET_FLAGS(flags, MODE_E3_A0);
11328 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
11329 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
11330 }
11331
11332 if (IS_MF(bp)) {
11333 SET_FLAGS(flags, MODE_MF);
11334 switch (bp->mf_mode) {
11335 case MULTI_FUNCTION_SD:
11336 SET_FLAGS(flags, MODE_MF_SD);
11337 break;
11338 case MULTI_FUNCTION_SI:
11339 SET_FLAGS(flags, MODE_MF_SI);
11340 break;
11341 case MULTI_FUNCTION_AFEX:
11342 SET_FLAGS(flags, MODE_MF_AFEX);
11343 break;
11344 }
11345 } else
11346 SET_FLAGS(flags, MODE_SF);
11347
11348 #if defined(__LITTLE_ENDIAN)
11349 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
11350 #else /*(__BIG_ENDIAN)*/
11351 SET_FLAGS(flags, MODE_BIG_ENDIAN);
11352 #endif
11353 INIT_MODE_FLAGS(bp) = flags;
11354 }
11355
11356 static int bnx2x_init_bp(struct bnx2x *bp)
11357 {
11358 int func;
11359 int rc;
11360
11361 mutex_init(&bp->port.phy_mutex);
11362 mutex_init(&bp->fw_mb_mutex);
11363 spin_lock_init(&bp->stats_lock);
11364
11365
11366 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
11367 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
11368 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
11369 if (IS_PF(bp)) {
11370 rc = bnx2x_get_hwinfo(bp);
11371 if (rc)
11372 return rc;
11373 } else {
11374 random_ether_addr(bp->dev->dev_addr);
11375 }
11376
11377 bnx2x_set_modes_bitmap(bp);
11378
11379 rc = bnx2x_alloc_mem_bp(bp);
11380 if (rc)
11381 return rc;
11382
11383 bnx2x_read_fwinfo(bp);
11384
11385 func = BP_FUNC(bp);
11386
11387 /* need to reset chip if undi was active */
11388 if (IS_PF(bp) && !BP_NOMCP(bp)) {
11389 /* init fw_seq */
11390 bp->fw_seq =
11391 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
11392 DRV_MSG_SEQ_NUMBER_MASK;
11393 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
11394
11395 bnx2x_prev_unload(bp);
11396 }
11397
11398
11399 if (CHIP_REV_IS_FPGA(bp))
11400 dev_err(&bp->pdev->dev, "FPGA detected\n");
11401
11402 if (BP_NOMCP(bp) && (func == 0))
11403 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
11404
11405 bp->disable_tpa = disable_tpa;
11406 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
11407
11408 /* Set TPA flags */
11409 if (bp->disable_tpa) {
11410 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11411 bp->dev->features &= ~NETIF_F_LRO;
11412 } else {
11413 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
11414 bp->dev->features |= NETIF_F_LRO;
11415 }
11416
11417 if (CHIP_IS_E1(bp))
11418 bp->dropless_fc = 0;
11419 else
11420 bp->dropless_fc = dropless_fc | bnx2x_get_dropless_info(bp);
11421
11422 bp->mrrs = mrrs;
11423
11424 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
11425 if (IS_VF(bp))
11426 bp->rx_ring_size = MAX_RX_AVAIL;
11427
11428 /* make sure that the numbers are in the right granularity */
11429 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
11430 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
11431
11432 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
11433
11434 init_timer(&bp->timer);
11435 bp->timer.expires = jiffies + bp->current_interval;
11436 bp->timer.data = (unsigned long) bp;
11437 bp->timer.function = bnx2x_timer;
11438
11439 if (SHMEM2_HAS(bp, dcbx_lldp_params_offset) &&
11440 SHMEM2_HAS(bp, dcbx_lldp_dcbx_stat_offset) &&
11441 SHMEM2_RD(bp, dcbx_lldp_params_offset) &&
11442 SHMEM2_RD(bp, dcbx_lldp_dcbx_stat_offset)) {
11443 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
11444 bnx2x_dcbx_init_params(bp);
11445 } else {
11446 bnx2x_dcbx_set_state(bp, false, BNX2X_DCBX_ENABLED_OFF);
11447 }
11448
11449 if (CHIP_IS_E1x(bp))
11450 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
11451 else
11452 bp->cnic_base_cl_id = FP_SB_MAX_E2;
11453
11454 /* multiple tx priority */
11455 if (IS_VF(bp))
11456 bp->max_cos = 1;
11457 else if (CHIP_IS_E1x(bp))
11458 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
11459 else if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
11460 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
11461 else if (CHIP_IS_E3B0(bp))
11462 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
11463 else
11464 BNX2X_ERR("unknown chip %x revision %x\n",
11465 CHIP_NUM(bp), CHIP_REV(bp));
11466 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp->max_cos);
11467
11468 /* We need at least one default status block for slow-path events,
11469 * second status block for the L2 queue, and a third status block for
11470 * CNIC if supproted.
11471 */
11472 if (CNIC_SUPPORT(bp))
11473 bp->min_msix_vec_cnt = 3;
11474 else
11475 bp->min_msix_vec_cnt = 2;
11476 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp->min_msix_vec_cnt);
11477
11478 return rc;
11479 }
11480
11481
11482 /****************************************************************************
11483 * General service functions
11484 ****************************************************************************/
11485
11486 /*
11487 * net_device service functions
11488 */
11489
11490 /* called with rtnl_lock */
11491 static int bnx2x_open(struct net_device *dev)
11492 {
11493 struct bnx2x *bp = netdev_priv(dev);
11494 bool global = false;
11495 int other_engine = BP_PATH(bp) ? 0 : 1;
11496 bool other_load_status, load_status;
11497 int rc;
11498
11499 bp->stats_init = true;
11500
11501 netif_carrier_off(dev);
11502
11503 bnx2x_set_power_state(bp, PCI_D0);
11504
11505 /* If parity had happen during the unload, then attentions
11506 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
11507 * want the first function loaded on the current engine to
11508 * complete the recovery.
11509 * Parity recovery is only relevant for PF driver.
11510 */
11511 if (IS_PF(bp)) {
11512 other_load_status = bnx2x_get_load_status(bp, other_engine);
11513 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
11514 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
11515 bnx2x_chk_parity_attn(bp, &global, true)) {
11516 do {
11517 /* If there are attentions and they are in a
11518 * global blocks, set the GLOBAL_RESET bit
11519 * regardless whether it will be this function
11520 * that will complete the recovery or not.
11521 */
11522 if (global)
11523 bnx2x_set_reset_global(bp);
11524
11525 /* Only the first function on the current
11526 * engine should try to recover in open. In case
11527 * of attentions in global blocks only the first
11528 * in the chip should try to recover.
11529 */
11530 if ((!load_status &&
11531 (!global || !other_load_status)) &&
11532 bnx2x_trylock_leader_lock(bp) &&
11533 !bnx2x_leader_reset(bp)) {
11534 netdev_info(bp->dev,
11535 "Recovered in open\n");
11536 break;
11537 }
11538
11539 /* recovery has failed... */
11540 bnx2x_set_power_state(bp, PCI_D3hot);
11541 bp->recovery_state = BNX2X_RECOVERY_FAILED;
11542
11543 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
11544 "If you still see this message after a few retries then power cycle is required.\n");
11545
11546 return -EAGAIN;
11547 } while (0);
11548 }
11549 }
11550
11551 bp->recovery_state = BNX2X_RECOVERY_DONE;
11552 rc = bnx2x_nic_load(bp, LOAD_OPEN);
11553 if (rc)
11554 return rc;
11555 return bnx2x_open_epilog(bp);
11556 }
11557
11558 /* called with rtnl_lock */
11559 static int bnx2x_close(struct net_device *dev)
11560 {
11561 struct bnx2x *bp = netdev_priv(dev);
11562
11563 /* Unload the driver, release IRQs */
11564 bnx2x_nic_unload(bp, UNLOAD_CLOSE, false);
11565
11566 /* Power off */
11567 bnx2x_set_power_state(bp, PCI_D3hot);
11568
11569 return 0;
11570 }
11571
11572 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11573 struct bnx2x_mcast_ramrod_params *p)
11574 {
11575 int mc_count = netdev_mc_count(bp->dev);
11576 struct bnx2x_mcast_list_elem *mc_mac =
11577 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11578 struct netdev_hw_addr *ha;
11579
11580 if (!mc_mac)
11581 return -ENOMEM;
11582
11583 INIT_LIST_HEAD(&p->mcast_list);
11584
11585 netdev_for_each_mc_addr(ha, bp->dev) {
11586 mc_mac->mac = bnx2x_mc_addr(ha);
11587 list_add_tail(&mc_mac->link, &p->mcast_list);
11588 mc_mac++;
11589 }
11590
11591 p->mcast_list_len = mc_count;
11592
11593 return 0;
11594 }
11595
11596 static void bnx2x_free_mcast_macs_list(
11597 struct bnx2x_mcast_ramrod_params *p)
11598 {
11599 struct bnx2x_mcast_list_elem *mc_mac =
11600 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11601 link);
11602
11603 WARN_ON(!mc_mac);
11604 kfree(mc_mac);
11605 }
11606
11607 /**
11608 * bnx2x_set_uc_list - configure a new unicast MACs list.
11609 *
11610 * @bp: driver handle
11611 *
11612 * We will use zero (0) as a MAC type for these MACs.
11613 */
11614 static int bnx2x_set_uc_list(struct bnx2x *bp)
11615 {
11616 int rc;
11617 struct net_device *dev = bp->dev;
11618 struct netdev_hw_addr *ha;
11619 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11620 unsigned long ramrod_flags = 0;
11621
11622 /* First schedule a cleanup up of old configuration */
11623 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11624 if (rc < 0) {
11625 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11626 return rc;
11627 }
11628
11629 netdev_for_each_uc_addr(ha, dev) {
11630 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11631 BNX2X_UC_LIST_MAC, &ramrod_flags);
11632 if (rc == -EEXIST) {
11633 DP(BNX2X_MSG_SP,
11634 "Failed to schedule ADD operations: %d\n", rc);
11635 /* do not treat adding same MAC as error */
11636 rc = 0;
11637
11638 } else if (rc < 0) {
11639
11640 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11641 rc);
11642 return rc;
11643 }
11644 }
11645
11646 /* Execute the pending commands */
11647 __set_bit(RAMROD_CONT, &ramrod_flags);
11648 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11649 BNX2X_UC_LIST_MAC, &ramrod_flags);
11650 }
11651
11652 static int bnx2x_set_mc_list(struct bnx2x *bp)
11653 {
11654 struct net_device *dev = bp->dev;
11655 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11656 int rc = 0;
11657
11658 rparam.mcast_obj = &bp->mcast_obj;
11659
11660 /* first, clear all configured multicast MACs */
11661 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11662 if (rc < 0) {
11663 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11664 return rc;
11665 }
11666
11667 /* then, configure a new MACs list */
11668 if (netdev_mc_count(dev)) {
11669 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11670 if (rc) {
11671 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11672 rc);
11673 return rc;
11674 }
11675
11676 /* Now add the new MACs */
11677 rc = bnx2x_config_mcast(bp, &rparam,
11678 BNX2X_MCAST_CMD_ADD);
11679 if (rc < 0)
11680 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11681 rc);
11682
11683 bnx2x_free_mcast_macs_list(&rparam);
11684 }
11685
11686 return rc;
11687 }
11688
11689 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11690 void bnx2x_set_rx_mode(struct net_device *dev)
11691 {
11692 struct bnx2x *bp = netdev_priv(dev);
11693 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11694
11695 if (bp->state != BNX2X_STATE_OPEN) {
11696 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11697 return;
11698 }
11699
11700 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11701
11702 if (dev->flags & IFF_PROMISC)
11703 rx_mode = BNX2X_RX_MODE_PROMISC;
11704 else if ((dev->flags & IFF_ALLMULTI) ||
11705 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11706 CHIP_IS_E1(bp)))
11707 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11708 else {
11709 if (IS_PF(bp)) {
11710 /* some multicasts */
11711 if (bnx2x_set_mc_list(bp) < 0)
11712 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11713
11714 if (bnx2x_set_uc_list(bp) < 0)
11715 rx_mode = BNX2X_RX_MODE_PROMISC;
11716 } else {
11717 /* configuring mcast to a vf involves sleeping (when we
11718 * wait for the pf's response). Since this function is
11719 * called from non sleepable context we must schedule
11720 * a work item for this purpose
11721 */
11722 smp_mb__before_clear_bit();
11723 set_bit(BNX2X_SP_RTNL_VFPF_MCAST,
11724 &bp->sp_rtnl_state);
11725 smp_mb__after_clear_bit();
11726 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11727 }
11728 }
11729
11730 bp->rx_mode = rx_mode;
11731 /* handle ISCSI SD mode */
11732 if (IS_MF_ISCSI_SD(bp))
11733 bp->rx_mode = BNX2X_RX_MODE_NONE;
11734
11735 /* Schedule the rx_mode command */
11736 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11737 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11738 return;
11739 }
11740
11741 if (IS_PF(bp)) {
11742 bnx2x_set_storm_rx_mode(bp);
11743 } else {
11744 /* configuring rx mode to storms in a vf involves sleeping (when
11745 * we wait for the pf's response). Since this function is
11746 * called from non sleepable context we must schedule
11747 * a work item for this purpose
11748 */
11749 smp_mb__before_clear_bit();
11750 set_bit(BNX2X_SP_RTNL_VFPF_STORM_RX_MODE,
11751 &bp->sp_rtnl_state);
11752 smp_mb__after_clear_bit();
11753 schedule_delayed_work(&bp->sp_rtnl_task, 0);
11754 }
11755 }
11756
11757 /* called with rtnl_lock */
11758 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11759 int devad, u16 addr)
11760 {
11761 struct bnx2x *bp = netdev_priv(netdev);
11762 u16 value;
11763 int rc;
11764
11765 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11766 prtad, devad, addr);
11767
11768 /* The HW expects different devad if CL22 is used */
11769 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11770
11771 bnx2x_acquire_phy_lock(bp);
11772 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11773 bnx2x_release_phy_lock(bp);
11774 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11775
11776 if (!rc)
11777 rc = value;
11778 return rc;
11779 }
11780
11781 /* called with rtnl_lock */
11782 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11783 u16 addr, u16 value)
11784 {
11785 struct bnx2x *bp = netdev_priv(netdev);
11786 int rc;
11787
11788 DP(NETIF_MSG_LINK,
11789 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11790 prtad, devad, addr, value);
11791
11792 /* The HW expects different devad if CL22 is used */
11793 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11794
11795 bnx2x_acquire_phy_lock(bp);
11796 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11797 bnx2x_release_phy_lock(bp);
11798 return rc;
11799 }
11800
11801 /* called with rtnl_lock */
11802 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11803 {
11804 struct bnx2x *bp = netdev_priv(dev);
11805 struct mii_ioctl_data *mdio = if_mii(ifr);
11806
11807 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11808 mdio->phy_id, mdio->reg_num, mdio->val_in);
11809
11810 if (!netif_running(dev))
11811 return -EAGAIN;
11812
11813 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11814 }
11815
11816 #ifdef CONFIG_NET_POLL_CONTROLLER
11817 static void poll_bnx2x(struct net_device *dev)
11818 {
11819 struct bnx2x *bp = netdev_priv(dev);
11820 int i;
11821
11822 for_each_eth_queue(bp, i) {
11823 struct bnx2x_fastpath *fp = &bp->fp[i];
11824 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11825 }
11826 }
11827 #endif
11828
11829 static int bnx2x_validate_addr(struct net_device *dev)
11830 {
11831 struct bnx2x *bp = netdev_priv(dev);
11832
11833 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11834 BNX2X_ERR("Non-valid Ethernet address\n");
11835 return -EADDRNOTAVAIL;
11836 }
11837 return 0;
11838 }
11839
11840 static const struct net_device_ops bnx2x_netdev_ops = {
11841 .ndo_open = bnx2x_open,
11842 .ndo_stop = bnx2x_close,
11843 .ndo_start_xmit = bnx2x_start_xmit,
11844 .ndo_select_queue = bnx2x_select_queue,
11845 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11846 .ndo_set_mac_address = bnx2x_change_mac_addr,
11847 .ndo_validate_addr = bnx2x_validate_addr,
11848 .ndo_do_ioctl = bnx2x_ioctl,
11849 .ndo_change_mtu = bnx2x_change_mtu,
11850 .ndo_fix_features = bnx2x_fix_features,
11851 .ndo_set_features = bnx2x_set_features,
11852 .ndo_tx_timeout = bnx2x_tx_timeout,
11853 #ifdef CONFIG_NET_POLL_CONTROLLER
11854 .ndo_poll_controller = poll_bnx2x,
11855 #endif
11856 .ndo_setup_tc = bnx2x_setup_tc,
11857 #ifdef CONFIG_BNX2X_SRIOV
11858 .ndo_set_vf_mac = bnx2x_set_vf_mac,
11859 .ndo_set_vf_vlan = bnx2x_set_vf_vlan,
11860 .ndo_get_vf_config = bnx2x_get_vf_config,
11861 #endif
11862 #ifdef NETDEV_FCOE_WWNN
11863 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11864 #endif
11865 };
11866
11867 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11868 {
11869 struct device *dev = &bp->pdev->dev;
11870
11871 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11872 bp->flags |= USING_DAC_FLAG;
11873 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11874 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11875 return -EIO;
11876 }
11877 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11878 dev_err(dev, "System does not support DMA, aborting\n");
11879 return -EIO;
11880 }
11881
11882 return 0;
11883 }
11884
11885 static int bnx2x_init_dev(struct bnx2x *bp, struct pci_dev *pdev,
11886 struct net_device *dev, unsigned long board_type)
11887 {
11888 int rc;
11889 u32 pci_cfg_dword;
11890 bool chip_is_e1x = (board_type == BCM57710 ||
11891 board_type == BCM57711 ||
11892 board_type == BCM57711E);
11893
11894 SET_NETDEV_DEV(dev, &pdev->dev);
11895
11896 bp->dev = dev;
11897 bp->pdev = pdev;
11898
11899 rc = pci_enable_device(pdev);
11900 if (rc) {
11901 dev_err(&bp->pdev->dev,
11902 "Cannot enable PCI device, aborting\n");
11903 goto err_out;
11904 }
11905
11906 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11907 dev_err(&bp->pdev->dev,
11908 "Cannot find PCI device base address, aborting\n");
11909 rc = -ENODEV;
11910 goto err_out_disable;
11911 }
11912
11913 if (IS_PF(bp) && !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11914 dev_err(&bp->pdev->dev, "Cannot find second PCI device base address, aborting\n");
11915 rc = -ENODEV;
11916 goto err_out_disable;
11917 }
11918
11919 pci_read_config_dword(pdev, PCICFG_REVISION_ID_OFFSET, &pci_cfg_dword);
11920 if ((pci_cfg_dword & PCICFG_REVESION_ID_MASK) ==
11921 PCICFG_REVESION_ID_ERROR_VAL) {
11922 pr_err("PCI device error, probably due to fan failure, aborting\n");
11923 rc = -ENODEV;
11924 goto err_out_disable;
11925 }
11926
11927 if (atomic_read(&pdev->enable_cnt) == 1) {
11928 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11929 if (rc) {
11930 dev_err(&bp->pdev->dev,
11931 "Cannot obtain PCI resources, aborting\n");
11932 goto err_out_disable;
11933 }
11934
11935 pci_set_master(pdev);
11936 pci_save_state(pdev);
11937 }
11938
11939 if (IS_PF(bp)) {
11940 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11941 if (bp->pm_cap == 0) {
11942 dev_err(&bp->pdev->dev,
11943 "Cannot find power management capability, aborting\n");
11944 rc = -EIO;
11945 goto err_out_release;
11946 }
11947 }
11948
11949 if (!pci_is_pcie(pdev)) {
11950 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11951 rc = -EIO;
11952 goto err_out_release;
11953 }
11954
11955 rc = bnx2x_set_coherency_mask(bp);
11956 if (rc)
11957 goto err_out_release;
11958
11959 dev->mem_start = pci_resource_start(pdev, 0);
11960 dev->base_addr = dev->mem_start;
11961 dev->mem_end = pci_resource_end(pdev, 0);
11962
11963 dev->irq = pdev->irq;
11964
11965 bp->regview = pci_ioremap_bar(pdev, 0);
11966 if (!bp->regview) {
11967 dev_err(&bp->pdev->dev,
11968 "Cannot map register space, aborting\n");
11969 rc = -ENOMEM;
11970 goto err_out_release;
11971 }
11972
11973 /* In E1/E1H use pci device function given by kernel.
11974 * In E2/E3 read physical function from ME register since these chips
11975 * support Physical Device Assignment where kernel BDF maybe arbitrary
11976 * (depending on hypervisor).
11977 */
11978 if (chip_is_e1x) {
11979 bp->pf_num = PCI_FUNC(pdev->devfn);
11980 } else {
11981 /* chip is E2/3*/
11982 pci_read_config_dword(bp->pdev,
11983 PCICFG_ME_REGISTER, &pci_cfg_dword);
11984 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11985 ME_REG_ABS_PF_NUM_SHIFT);
11986 }
11987 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11988
11989 bnx2x_set_power_state(bp, PCI_D0);
11990
11991 /* clean indirect addresses */
11992 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11993 PCICFG_VENDOR_ID_OFFSET);
11994 /*
11995 * Clean the following indirect addresses for all functions since it
11996 * is not used by the driver.
11997 */
11998 if (IS_PF(bp)) {
11999 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
12000 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
12001 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
12002 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
12003
12004 if (chip_is_e1x) {
12005 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
12006 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
12007 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
12008 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
12009 }
12010
12011 /* Enable internal target-read (in case we are probed after PF
12012 * FLR). Must be done prior to any BAR read access. Only for
12013 * 57712 and up
12014 */
12015 if (!chip_is_e1x)
12016 REG_WR(bp,
12017 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
12018 }
12019
12020 dev->watchdog_timeo = TX_TIMEOUT;
12021
12022 dev->netdev_ops = &bnx2x_netdev_ops;
12023 bnx2x_set_ethtool_ops(bp, dev);
12024
12025 dev->priv_flags |= IFF_UNICAST_FLT;
12026
12027 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12028 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12029 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
12030 NETIF_F_RXHASH | NETIF_F_HW_VLAN_CTAG_TX;
12031 if (!CHIP_IS_E1x(bp)) {
12032 dev->hw_features |= NETIF_F_GSO_GRE;
12033 dev->hw_enc_features =
12034 NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | NETIF_F_SG |
12035 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
12036 NETIF_F_GSO_GRE;
12037 }
12038
12039 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
12040 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
12041
12042 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_CTAG_RX;
12043 if (bp->flags & USING_DAC_FLAG)
12044 dev->features |= NETIF_F_HIGHDMA;
12045
12046 /* Add Loopback capability to the device */
12047 dev->hw_features |= NETIF_F_LOOPBACK;
12048
12049 #ifdef BCM_DCBNL
12050 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
12051 #endif
12052
12053 /* get_port_hwinfo() will set prtad and mmds properly */
12054 bp->mdio.prtad = MDIO_PRTAD_NONE;
12055 bp->mdio.mmds = 0;
12056 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
12057 bp->mdio.dev = dev;
12058 bp->mdio.mdio_read = bnx2x_mdio_read;
12059 bp->mdio.mdio_write = bnx2x_mdio_write;
12060
12061 return 0;
12062
12063 err_out_release:
12064 if (atomic_read(&pdev->enable_cnt) == 1)
12065 pci_release_regions(pdev);
12066
12067 err_out_disable:
12068 pci_disable_device(pdev);
12069 pci_set_drvdata(pdev, NULL);
12070
12071 err_out:
12072 return rc;
12073 }
12074
12075 static void bnx2x_get_pcie_width_speed(struct bnx2x *bp, int *width, int *speed)
12076 {
12077 u32 val = 0;
12078
12079 pci_read_config_dword(bp->pdev, PCICFG_LINK_CONTROL, &val);
12080 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
12081
12082 /* return value of 1=2.5GHz 2=5GHz */
12083 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
12084 }
12085
12086 static int bnx2x_check_firmware(struct bnx2x *bp)
12087 {
12088 const struct firmware *firmware = bp->firmware;
12089 struct bnx2x_fw_file_hdr *fw_hdr;
12090 struct bnx2x_fw_file_section *sections;
12091 u32 offset, len, num_ops;
12092 __be16 *ops_offsets;
12093 int i;
12094 const u8 *fw_ver;
12095
12096 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
12097 BNX2X_ERR("Wrong FW size\n");
12098 return -EINVAL;
12099 }
12100
12101 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
12102 sections = (struct bnx2x_fw_file_section *)fw_hdr;
12103
12104 /* Make sure none of the offsets and sizes make us read beyond
12105 * the end of the firmware data */
12106 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
12107 offset = be32_to_cpu(sections[i].offset);
12108 len = be32_to_cpu(sections[i].len);
12109 if (offset + len > firmware->size) {
12110 BNX2X_ERR("Section %d length is out of bounds\n", i);
12111 return -EINVAL;
12112 }
12113 }
12114
12115 /* Likewise for the init_ops offsets */
12116 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
12117 ops_offsets = (__force __be16 *)(firmware->data + offset);
12118 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
12119
12120 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
12121 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
12122 BNX2X_ERR("Section offset %d is out of bounds\n", i);
12123 return -EINVAL;
12124 }
12125 }
12126
12127 /* Check FW version */
12128 offset = be32_to_cpu(fw_hdr->fw_version.offset);
12129 fw_ver = firmware->data + offset;
12130 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
12131 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
12132 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
12133 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
12134 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
12135 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
12136 BCM_5710_FW_MAJOR_VERSION,
12137 BCM_5710_FW_MINOR_VERSION,
12138 BCM_5710_FW_REVISION_VERSION,
12139 BCM_5710_FW_ENGINEERING_VERSION);
12140 return -EINVAL;
12141 }
12142
12143 return 0;
12144 }
12145
12146 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12147 {
12148 const __be32 *source = (const __be32 *)_source;
12149 u32 *target = (u32 *)_target;
12150 u32 i;
12151
12152 for (i = 0; i < n/4; i++)
12153 target[i] = be32_to_cpu(source[i]);
12154 }
12155
12156 /*
12157 Ops array is stored in the following format:
12158 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
12159 */
12160 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
12161 {
12162 const __be32 *source = (const __be32 *)_source;
12163 struct raw_op *target = (struct raw_op *)_target;
12164 u32 i, j, tmp;
12165
12166 for (i = 0, j = 0; i < n/8; i++, j += 2) {
12167 tmp = be32_to_cpu(source[j]);
12168 target[i].op = (tmp >> 24) & 0xff;
12169 target[i].offset = tmp & 0xffffff;
12170 target[i].raw_data = be32_to_cpu(source[j + 1]);
12171 }
12172 }
12173
12174 /* IRO array is stored in the following format:
12175 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
12176 */
12177 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
12178 {
12179 const __be32 *source = (const __be32 *)_source;
12180 struct iro *target = (struct iro *)_target;
12181 u32 i, j, tmp;
12182
12183 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
12184 target[i].base = be32_to_cpu(source[j]);
12185 j++;
12186 tmp = be32_to_cpu(source[j]);
12187 target[i].m1 = (tmp >> 16) & 0xffff;
12188 target[i].m2 = tmp & 0xffff;
12189 j++;
12190 tmp = be32_to_cpu(source[j]);
12191 target[i].m3 = (tmp >> 16) & 0xffff;
12192 target[i].size = tmp & 0xffff;
12193 j++;
12194 }
12195 }
12196
12197 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
12198 {
12199 const __be16 *source = (const __be16 *)_source;
12200 u16 *target = (u16 *)_target;
12201 u32 i;
12202
12203 for (i = 0; i < n/2; i++)
12204 target[i] = be16_to_cpu(source[i]);
12205 }
12206
12207 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
12208 do { \
12209 u32 len = be32_to_cpu(fw_hdr->arr.len); \
12210 bp->arr = kmalloc(len, GFP_KERNEL); \
12211 if (!bp->arr) \
12212 goto lbl; \
12213 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
12214 (u8 *)bp->arr, len); \
12215 } while (0)
12216
12217 static int bnx2x_init_firmware(struct bnx2x *bp)
12218 {
12219 const char *fw_file_name;
12220 struct bnx2x_fw_file_hdr *fw_hdr;
12221 int rc;
12222
12223 if (bp->firmware)
12224 return 0;
12225
12226 if (CHIP_IS_E1(bp))
12227 fw_file_name = FW_FILE_NAME_E1;
12228 else if (CHIP_IS_E1H(bp))
12229 fw_file_name = FW_FILE_NAME_E1H;
12230 else if (!CHIP_IS_E1x(bp))
12231 fw_file_name = FW_FILE_NAME_E2;
12232 else {
12233 BNX2X_ERR("Unsupported chip revision\n");
12234 return -EINVAL;
12235 }
12236 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
12237
12238 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
12239 if (rc) {
12240 BNX2X_ERR("Can't load firmware file %s\n",
12241 fw_file_name);
12242 goto request_firmware_exit;
12243 }
12244
12245 rc = bnx2x_check_firmware(bp);
12246 if (rc) {
12247 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
12248 goto request_firmware_exit;
12249 }
12250
12251 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
12252
12253 /* Initialize the pointers to the init arrays */
12254 /* Blob */
12255 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
12256
12257 /* Opcodes */
12258 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
12259
12260 /* Offsets */
12261 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
12262 be16_to_cpu_n);
12263
12264 /* STORMs firmware */
12265 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12266 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
12267 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
12268 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
12269 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12270 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
12271 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
12272 be32_to_cpu(fw_hdr->usem_pram_data.offset);
12273 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12274 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
12275 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
12276 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
12277 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
12278 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
12279 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
12280 be32_to_cpu(fw_hdr->csem_pram_data.offset);
12281 /* IRO */
12282 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
12283
12284 return 0;
12285
12286 iro_alloc_err:
12287 kfree(bp->init_ops_offsets);
12288 init_offsets_alloc_err:
12289 kfree(bp->init_ops);
12290 init_ops_alloc_err:
12291 kfree(bp->init_data);
12292 request_firmware_exit:
12293 release_firmware(bp->firmware);
12294 bp->firmware = NULL;
12295
12296 return rc;
12297 }
12298
12299 static void bnx2x_release_firmware(struct bnx2x *bp)
12300 {
12301 kfree(bp->init_ops_offsets);
12302 kfree(bp->init_ops);
12303 kfree(bp->init_data);
12304 release_firmware(bp->firmware);
12305 bp->firmware = NULL;
12306 }
12307
12308
12309 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
12310 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
12311 .init_hw_cmn = bnx2x_init_hw_common,
12312 .init_hw_port = bnx2x_init_hw_port,
12313 .init_hw_func = bnx2x_init_hw_func,
12314
12315 .reset_hw_cmn = bnx2x_reset_common,
12316 .reset_hw_port = bnx2x_reset_port,
12317 .reset_hw_func = bnx2x_reset_func,
12318
12319 .gunzip_init = bnx2x_gunzip_init,
12320 .gunzip_end = bnx2x_gunzip_end,
12321
12322 .init_fw = bnx2x_init_firmware,
12323 .release_fw = bnx2x_release_firmware,
12324 };
12325
12326 void bnx2x__init_func_obj(struct bnx2x *bp)
12327 {
12328 /* Prepare DMAE related driver resources */
12329 bnx2x_setup_dmae(bp);
12330
12331 bnx2x_init_func_obj(bp, &bp->func_obj,
12332 bnx2x_sp(bp, func_rdata),
12333 bnx2x_sp_mapping(bp, func_rdata),
12334 bnx2x_sp(bp, func_afex_rdata),
12335 bnx2x_sp_mapping(bp, func_afex_rdata),
12336 &bnx2x_func_sp_drv);
12337 }
12338
12339 /* must be called after sriov-enable */
12340 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
12341 {
12342 int cid_count = BNX2X_L2_MAX_CID(bp);
12343
12344 if (IS_SRIOV(bp))
12345 cid_count += BNX2X_VF_CIDS;
12346
12347 if (CNIC_SUPPORT(bp))
12348 cid_count += CNIC_CID_MAX;
12349
12350 return roundup(cid_count, QM_CID_ROUND);
12351 }
12352
12353 /**
12354 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
12355 *
12356 * @dev: pci device
12357 *
12358 */
12359 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev,
12360 int cnic_cnt, bool is_vf)
12361 {
12362 int pos, index;
12363 u16 control = 0;
12364
12365 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
12366
12367 /*
12368 * If MSI-X is not supported - return number of SBs needed to support
12369 * one fast path queue: one FP queue + SB for CNIC
12370 */
12371 if (!pos) {
12372 dev_info(&pdev->dev, "no msix capability found\n");
12373 return 1 + cnic_cnt;
12374 }
12375 dev_info(&pdev->dev, "msix capability found\n");
12376
12377 /*
12378 * The value in the PCI configuration space is the index of the last
12379 * entry, namely one less than the actual size of the table, which is
12380 * exactly what we want to return from this function: number of all SBs
12381 * without the default SB.
12382 * For VFs there is no default SB, then we return (index+1).
12383 */
12384 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
12385
12386 index = control & PCI_MSIX_FLAGS_QSIZE;
12387
12388 return is_vf ? index + 1 : index;
12389 }
12390
12391 static int set_max_cos_est(int chip_id)
12392 {
12393 switch (chip_id) {
12394 case BCM57710:
12395 case BCM57711:
12396 case BCM57711E:
12397 return BNX2X_MULTI_TX_COS_E1X;
12398 case BCM57712:
12399 case BCM57712_MF:
12400 case BCM57712_VF:
12401 return BNX2X_MULTI_TX_COS_E2_E3A0;
12402 case BCM57800:
12403 case BCM57800_MF:
12404 case BCM57800_VF:
12405 case BCM57810:
12406 case BCM57810_MF:
12407 case BCM57840_4_10:
12408 case BCM57840_2_20:
12409 case BCM57840_O:
12410 case BCM57840_MFO:
12411 case BCM57810_VF:
12412 case BCM57840_MF:
12413 case BCM57840_VF:
12414 case BCM57811:
12415 case BCM57811_MF:
12416 case BCM57811_VF:
12417 return BNX2X_MULTI_TX_COS_E3B0;
12418 return 1;
12419 default:
12420 pr_err("Unknown board_type (%d), aborting\n", chip_id);
12421 return -ENODEV;
12422 }
12423 }
12424
12425 static int set_is_vf(int chip_id)
12426 {
12427 switch (chip_id) {
12428 case BCM57712_VF:
12429 case BCM57800_VF:
12430 case BCM57810_VF:
12431 case BCM57840_VF:
12432 case BCM57811_VF:
12433 return true;
12434 default:
12435 return false;
12436 }
12437 }
12438
12439 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev);
12440
12441 static int bnx2x_init_one(struct pci_dev *pdev,
12442 const struct pci_device_id *ent)
12443 {
12444 struct net_device *dev = NULL;
12445 struct bnx2x *bp;
12446 int pcie_width, pcie_speed;
12447 int rc, max_non_def_sbs;
12448 int rx_count, tx_count, rss_count, doorbell_size;
12449 int max_cos_est;
12450 bool is_vf;
12451 int cnic_cnt;
12452
12453 /* An estimated maximum supported CoS number according to the chip
12454 * version.
12455 * We will try to roughly estimate the maximum number of CoSes this chip
12456 * may support in order to minimize the memory allocated for Tx
12457 * netdev_queue's. This number will be accurately calculated during the
12458 * initialization of bp->max_cos based on the chip versions AND chip
12459 * revision in the bnx2x_init_bp().
12460 */
12461 max_cos_est = set_max_cos_est(ent->driver_data);
12462 if (max_cos_est < 0)
12463 return max_cos_est;
12464 is_vf = set_is_vf(ent->driver_data);
12465 cnic_cnt = is_vf ? 0 : 1;
12466
12467 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev, cnic_cnt, is_vf);
12468
12469 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
12470 rss_count = is_vf ? 1 : max_non_def_sbs - cnic_cnt;
12471
12472 if (rss_count < 1)
12473 return -EINVAL;
12474
12475 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
12476 rx_count = rss_count + cnic_cnt;
12477
12478 /* Maximum number of netdev Tx queues:
12479 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
12480 */
12481 tx_count = rss_count * max_cos_est + cnic_cnt;
12482
12483 /* dev zeroed in init_etherdev */
12484 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
12485 if (!dev)
12486 return -ENOMEM;
12487
12488 bp = netdev_priv(dev);
12489
12490 bp->flags = 0;
12491 if (is_vf)
12492 bp->flags |= IS_VF_FLAG;
12493
12494 bp->igu_sb_cnt = max_non_def_sbs;
12495 bp->igu_base_addr = IS_VF(bp) ? PXP_VF_ADDR_IGU_START : BAR_IGU_INTMEM;
12496 bp->msg_enable = debug;
12497 bp->cnic_support = cnic_cnt;
12498 bp->cnic_probe = bnx2x_cnic_probe;
12499
12500 pci_set_drvdata(pdev, dev);
12501
12502 rc = bnx2x_init_dev(bp, pdev, dev, ent->driver_data);
12503 if (rc < 0) {
12504 free_netdev(dev);
12505 return rc;
12506 }
12507
12508 BNX2X_DEV_INFO("This is a %s function\n",
12509 IS_PF(bp) ? "physical" : "virtual");
12510 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp) ? "on" : "off");
12511 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs);
12512 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
12513 tx_count, rx_count);
12514
12515 rc = bnx2x_init_bp(bp);
12516 if (rc)
12517 goto init_one_exit;
12518
12519 /* Map doorbells here as we need the real value of bp->max_cos which
12520 * is initialized in bnx2x_init_bp() to determine the number of
12521 * l2 connections.
12522 */
12523 if (IS_VF(bp)) {
12524 bp->doorbells = bnx2x_vf_doorbells(bp);
12525 rc = bnx2x_vf_pci_alloc(bp);
12526 if (rc)
12527 goto init_one_exit;
12528 } else {
12529 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
12530 if (doorbell_size > pci_resource_len(pdev, 2)) {
12531 dev_err(&bp->pdev->dev,
12532 "Cannot map doorbells, bar size too small, aborting\n");
12533 rc = -ENOMEM;
12534 goto init_one_exit;
12535 }
12536 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
12537 doorbell_size);
12538 }
12539 if (!bp->doorbells) {
12540 dev_err(&bp->pdev->dev,
12541 "Cannot map doorbell space, aborting\n");
12542 rc = -ENOMEM;
12543 goto init_one_exit;
12544 }
12545
12546 if (IS_VF(bp)) {
12547 rc = bnx2x_vfpf_acquire(bp, tx_count, rx_count);
12548 if (rc)
12549 goto init_one_exit;
12550 }
12551
12552 /* Enable SRIOV if capability found in configuration space */
12553 rc = bnx2x_iov_init_one(bp, int_mode, BNX2X_MAX_NUM_OF_VFS);
12554 if (rc)
12555 goto init_one_exit;
12556
12557 /* calc qm_cid_count */
12558 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
12559 BNX2X_DEV_INFO("qm_cid_count %d\n", bp->qm_cid_count);
12560
12561 /* disable FCOE L2 queue for E1x*/
12562 if (CHIP_IS_E1x(bp))
12563 bp->flags |= NO_FCOE_FLAG;
12564
12565 /* Set bp->num_queues for MSI-X mode*/
12566 bnx2x_set_num_queues(bp);
12567
12568 /* Configure interrupt mode: try to enable MSI-X/MSI if
12569 * needed.
12570 */
12571 rc = bnx2x_set_int_mode(bp);
12572 if (rc) {
12573 dev_err(&pdev->dev, "Cannot set interrupts\n");
12574 goto init_one_exit;
12575 }
12576 BNX2X_DEV_INFO("set interrupts successfully\n");
12577
12578 /* register the net device */
12579 rc = register_netdev(dev);
12580 if (rc) {
12581 dev_err(&pdev->dev, "Cannot register net device\n");
12582 goto init_one_exit;
12583 }
12584 BNX2X_DEV_INFO("device name after netdev register %s\n", dev->name);
12585
12586
12587 if (!NO_FCOE(bp)) {
12588 /* Add storage MAC address */
12589 rtnl_lock();
12590 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12591 rtnl_unlock();
12592 }
12593
12594 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
12595 BNX2X_DEV_INFO("got pcie width %d and speed %d\n",
12596 pcie_width, pcie_speed);
12597
12598 BNX2X_DEV_INFO(
12599 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
12600 board_info[ent->driver_data].name,
12601 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
12602 pcie_width,
12603 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
12604 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
12605 "5GHz (Gen2)" : "2.5GHz",
12606 dev->base_addr, bp->pdev->irq, dev->dev_addr);
12607
12608 return 0;
12609
12610 init_one_exit:
12611 if (bp->regview)
12612 iounmap(bp->regview);
12613
12614 if (IS_PF(bp) && bp->doorbells)
12615 iounmap(bp->doorbells);
12616
12617 free_netdev(dev);
12618
12619 if (atomic_read(&pdev->enable_cnt) == 1)
12620 pci_release_regions(pdev);
12621
12622 pci_disable_device(pdev);
12623 pci_set_drvdata(pdev, NULL);
12624
12625 return rc;
12626 }
12627
12628 static void bnx2x_remove_one(struct pci_dev *pdev)
12629 {
12630 struct net_device *dev = pci_get_drvdata(pdev);
12631 struct bnx2x *bp;
12632
12633 if (!dev) {
12634 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
12635 return;
12636 }
12637 bp = netdev_priv(dev);
12638
12639 /* Delete storage MAC address */
12640 if (!NO_FCOE(bp)) {
12641 rtnl_lock();
12642 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
12643 rtnl_unlock();
12644 }
12645
12646 #ifdef BCM_DCBNL
12647 /* Delete app tlvs from dcbnl */
12648 bnx2x_dcbnl_update_applist(bp, true);
12649 #endif
12650
12651 unregister_netdev(dev);
12652
12653 /* Power on: we can't let PCI layer write to us while we are in D3 */
12654 if (IS_PF(bp))
12655 bnx2x_set_power_state(bp, PCI_D0);
12656
12657 /* Disable MSI/MSI-X */
12658 bnx2x_disable_msi(bp);
12659
12660 /* Power off */
12661 if (IS_PF(bp))
12662 bnx2x_set_power_state(bp, PCI_D3hot);
12663
12664 /* Make sure RESET task is not scheduled before continuing */
12665 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12666
12667 bnx2x_iov_remove_one(bp);
12668
12669 /* send message via vfpf channel to release the resources of this vf */
12670 if (IS_VF(bp))
12671 bnx2x_vfpf_release(bp);
12672
12673 if (bp->regview)
12674 iounmap(bp->regview);
12675
12676 /* for vf doorbells are part of the regview and were unmapped along with
12677 * it. FW is only loaded by PF.
12678 */
12679 if (IS_PF(bp)) {
12680 if (bp->doorbells)
12681 iounmap(bp->doorbells);
12682
12683 bnx2x_release_firmware(bp);
12684 }
12685 bnx2x_free_mem_bp(bp);
12686
12687 free_netdev(dev);
12688
12689 if (atomic_read(&pdev->enable_cnt) == 1)
12690 pci_release_regions(pdev);
12691
12692 pci_disable_device(pdev);
12693 pci_set_drvdata(pdev, NULL);
12694 }
12695
12696 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12697 {
12698 bp->state = BNX2X_STATE_CLOSING_WAIT4_HALT;
12699
12700 bp->rx_mode = BNX2X_RX_MODE_NONE;
12701
12702 if (CNIC_LOADED(bp))
12703 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12704
12705 /* Stop Tx */
12706 bnx2x_tx_disable(bp);
12707 /* Delete all NAPI objects */
12708 bnx2x_del_all_napi(bp);
12709 if (CNIC_LOADED(bp))
12710 bnx2x_del_all_napi_cnic(bp);
12711 netdev_reset_tc(bp->dev);
12712
12713 del_timer_sync(&bp->timer);
12714 cancel_delayed_work(&bp->sp_task);
12715 cancel_delayed_work(&bp->period_task);
12716
12717 spin_lock_bh(&bp->stats_lock);
12718 bp->stats_state = STATS_STATE_DISABLED;
12719 spin_unlock_bh(&bp->stats_lock);
12720
12721 bnx2x_save_statistics(bp);
12722
12723 netif_carrier_off(bp->dev);
12724
12725 return 0;
12726 }
12727
12728 static void bnx2x_eeh_recover(struct bnx2x *bp)
12729 {
12730 u32 val;
12731
12732 mutex_init(&bp->port.phy_mutex);
12733
12734
12735 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12736 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12737 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12738 BNX2X_ERR("BAD MCP validity signature\n");
12739 }
12740
12741 /**
12742 * bnx2x_io_error_detected - called when PCI error is detected
12743 * @pdev: Pointer to PCI device
12744 * @state: The current pci connection state
12745 *
12746 * This function is called after a PCI bus error affecting
12747 * this device has been detected.
12748 */
12749 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12750 pci_channel_state_t state)
12751 {
12752 struct net_device *dev = pci_get_drvdata(pdev);
12753 struct bnx2x *bp = netdev_priv(dev);
12754
12755 rtnl_lock();
12756
12757 BNX2X_ERR("IO error detected\n");
12758
12759 netif_device_detach(dev);
12760
12761 if (state == pci_channel_io_perm_failure) {
12762 rtnl_unlock();
12763 return PCI_ERS_RESULT_DISCONNECT;
12764 }
12765
12766 if (netif_running(dev))
12767 bnx2x_eeh_nic_unload(bp);
12768
12769 bnx2x_prev_path_mark_eeh(bp);
12770
12771 pci_disable_device(pdev);
12772
12773 rtnl_unlock();
12774
12775 /* Request a slot reset */
12776 return PCI_ERS_RESULT_NEED_RESET;
12777 }
12778
12779 /**
12780 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12781 * @pdev: Pointer to PCI device
12782 *
12783 * Restart the card from scratch, as if from a cold-boot.
12784 */
12785 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12786 {
12787 struct net_device *dev = pci_get_drvdata(pdev);
12788 struct bnx2x *bp = netdev_priv(dev);
12789 int i;
12790
12791 rtnl_lock();
12792 BNX2X_ERR("IO slot reset initializing...\n");
12793 if (pci_enable_device(pdev)) {
12794 dev_err(&pdev->dev,
12795 "Cannot re-enable PCI device after reset\n");
12796 rtnl_unlock();
12797 return PCI_ERS_RESULT_DISCONNECT;
12798 }
12799
12800 pci_set_master(pdev);
12801 pci_restore_state(pdev);
12802
12803 if (netif_running(dev))
12804 bnx2x_set_power_state(bp, PCI_D0);
12805
12806 if (netif_running(dev)) {
12807 BNX2X_ERR("IO slot reset --> driver unload\n");
12808 if (IS_PF(bp) && SHMEM2_HAS(bp, drv_capabilities_flag)) {
12809 u32 v;
12810
12811 v = SHMEM2_RD(bp,
12812 drv_capabilities_flag[BP_FW_MB_IDX(bp)]);
12813 SHMEM2_WR(bp, drv_capabilities_flag[BP_FW_MB_IDX(bp)],
12814 v & ~DRV_FLAGS_CAPABILITIES_LOADED_L2);
12815 }
12816 bnx2x_drain_tx_queues(bp);
12817 bnx2x_send_unload_req(bp, UNLOAD_RECOVERY);
12818 bnx2x_netif_stop(bp, 1);
12819 bnx2x_free_irq(bp);
12820
12821 /* Report UNLOAD_DONE to MCP */
12822 bnx2x_send_unload_done(bp, true);
12823
12824 bp->sp_state = 0;
12825 bp->port.pmf = 0;
12826
12827 bnx2x_prev_unload(bp);
12828
12829 /* We should have resetted the engine, so It's fair to
12830 * assume the FW will no longer write to the bnx2x driver.
12831 */
12832 bnx2x_squeeze_objects(bp);
12833 bnx2x_free_skbs(bp);
12834 for_each_rx_queue(bp, i)
12835 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12836 bnx2x_free_fp_mem(bp);
12837 bnx2x_free_mem(bp);
12838
12839 bp->state = BNX2X_STATE_CLOSED;
12840 }
12841
12842 rtnl_unlock();
12843
12844 return PCI_ERS_RESULT_RECOVERED;
12845 }
12846
12847 /**
12848 * bnx2x_io_resume - called when traffic can start flowing again
12849 * @pdev: Pointer to PCI device
12850 *
12851 * This callback is called when the error recovery driver tells us that
12852 * its OK to resume normal operation.
12853 */
12854 static void bnx2x_io_resume(struct pci_dev *pdev)
12855 {
12856 struct net_device *dev = pci_get_drvdata(pdev);
12857 struct bnx2x *bp = netdev_priv(dev);
12858
12859 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12860 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12861 return;
12862 }
12863
12864 rtnl_lock();
12865
12866 bnx2x_eeh_recover(bp);
12867
12868 bp->fw_seq = SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
12869 DRV_MSG_SEQ_NUMBER_MASK;
12870
12871 if (netif_running(dev))
12872 bnx2x_nic_load(bp, LOAD_NORMAL);
12873
12874 netif_device_attach(dev);
12875
12876 rtnl_unlock();
12877 }
12878
12879 static const struct pci_error_handlers bnx2x_err_handler = {
12880 .error_detected = bnx2x_io_error_detected,
12881 .slot_reset = bnx2x_io_slot_reset,
12882 .resume = bnx2x_io_resume,
12883 };
12884
12885 static struct pci_driver bnx2x_pci_driver = {
12886 .name = DRV_MODULE_NAME,
12887 .id_table = bnx2x_pci_tbl,
12888 .probe = bnx2x_init_one,
12889 .remove = bnx2x_remove_one,
12890 .suspend = bnx2x_suspend,
12891 .resume = bnx2x_resume,
12892 .err_handler = &bnx2x_err_handler,
12893 #ifdef CONFIG_BNX2X_SRIOV
12894 .sriov_configure = bnx2x_sriov_configure,
12895 #endif
12896 };
12897
12898 static int __init bnx2x_init(void)
12899 {
12900 int ret;
12901
12902 pr_info("%s", version);
12903
12904 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12905 if (bnx2x_wq == NULL) {
12906 pr_err("Cannot create workqueue\n");
12907 return -ENOMEM;
12908 }
12909
12910 ret = pci_register_driver(&bnx2x_pci_driver);
12911 if (ret) {
12912 pr_err("Cannot register driver\n");
12913 destroy_workqueue(bnx2x_wq);
12914 }
12915 return ret;
12916 }
12917
12918 static void __exit bnx2x_cleanup(void)
12919 {
12920 struct list_head *pos, *q;
12921 pci_unregister_driver(&bnx2x_pci_driver);
12922
12923 destroy_workqueue(bnx2x_wq);
12924
12925 /* Free globablly allocated resources */
12926 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12927 struct bnx2x_prev_path_list *tmp =
12928 list_entry(pos, struct bnx2x_prev_path_list, list);
12929 list_del(pos);
12930 kfree(tmp);
12931 }
12932 }
12933
12934 void bnx2x_notify_link_changed(struct bnx2x *bp)
12935 {
12936 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12937 }
12938
12939 module_init(bnx2x_init);
12940 module_exit(bnx2x_cleanup);
12941
12942 /**
12943 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12944 *
12945 * @bp: driver handle
12946 * @set: set or clear the CAM entry
12947 *
12948 * This function will wait until the ramdord completion returns.
12949 * Return 0 if success, -ENODEV if ramrod doesn't return.
12950 */
12951 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12952 {
12953 unsigned long ramrod_flags = 0;
12954
12955 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12956 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12957 &bp->iscsi_l2_mac_obj, true,
12958 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12959 }
12960
12961 /* count denotes the number of new completions we have seen */
12962 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12963 {
12964 struct eth_spe *spe;
12965 int cxt_index, cxt_offset;
12966
12967 #ifdef BNX2X_STOP_ON_ERROR
12968 if (unlikely(bp->panic))
12969 return;
12970 #endif
12971
12972 spin_lock_bh(&bp->spq_lock);
12973 BUG_ON(bp->cnic_spq_pending < count);
12974 bp->cnic_spq_pending -= count;
12975
12976
12977 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12978 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12979 & SPE_HDR_CONN_TYPE) >>
12980 SPE_HDR_CONN_TYPE_SHIFT;
12981 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12982 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12983
12984 /* Set validation for iSCSI L2 client before sending SETUP
12985 * ramrod
12986 */
12987 if (type == ETH_CONNECTION_TYPE) {
12988 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12989 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12990 ILT_PAGE_CIDS;
12991 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12992 (cxt_index * ILT_PAGE_CIDS);
12993 bnx2x_set_ctx_validation(bp,
12994 &bp->context[cxt_index].
12995 vcxt[cxt_offset].eth,
12996 BNX2X_ISCSI_ETH_CID(bp));
12997 }
12998 }
12999
13000 /*
13001 * There may be not more than 8 L2, not more than 8 L5 SPEs
13002 * and in the air. We also check that number of outstanding
13003 * COMMON ramrods is not more than the EQ and SPQ can
13004 * accommodate.
13005 */
13006 if (type == ETH_CONNECTION_TYPE) {
13007 if (!atomic_read(&bp->cq_spq_left))
13008 break;
13009 else
13010 atomic_dec(&bp->cq_spq_left);
13011 } else if (type == NONE_CONNECTION_TYPE) {
13012 if (!atomic_read(&bp->eq_spq_left))
13013 break;
13014 else
13015 atomic_dec(&bp->eq_spq_left);
13016 } else if ((type == ISCSI_CONNECTION_TYPE) ||
13017 (type == FCOE_CONNECTION_TYPE)) {
13018 if (bp->cnic_spq_pending >=
13019 bp->cnic_eth_dev.max_kwqe_pending)
13020 break;
13021 else
13022 bp->cnic_spq_pending++;
13023 } else {
13024 BNX2X_ERR("Unknown SPE type: %d\n", type);
13025 bnx2x_panic();
13026 break;
13027 }
13028
13029 spe = bnx2x_sp_get_next(bp);
13030 *spe = *bp->cnic_kwq_cons;
13031
13032 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
13033 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
13034
13035 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
13036 bp->cnic_kwq_cons = bp->cnic_kwq;
13037 else
13038 bp->cnic_kwq_cons++;
13039 }
13040 bnx2x_sp_prod_update(bp);
13041 spin_unlock_bh(&bp->spq_lock);
13042 }
13043
13044 static int bnx2x_cnic_sp_queue(struct net_device *dev,
13045 struct kwqe_16 *kwqes[], u32 count)
13046 {
13047 struct bnx2x *bp = netdev_priv(dev);
13048 int i;
13049
13050 #ifdef BNX2X_STOP_ON_ERROR
13051 if (unlikely(bp->panic)) {
13052 BNX2X_ERR("Can't post to SP queue while panic\n");
13053 return -EIO;
13054 }
13055 #endif
13056
13057 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
13058 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
13059 BNX2X_ERR("Handling parity error recovery. Try again later\n");
13060 return -EAGAIN;
13061 }
13062
13063 spin_lock_bh(&bp->spq_lock);
13064
13065 for (i = 0; i < count; i++) {
13066 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
13067
13068 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
13069 break;
13070
13071 *bp->cnic_kwq_prod = *spe;
13072
13073 bp->cnic_kwq_pending++;
13074
13075 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
13076 spe->hdr.conn_and_cmd_data, spe->hdr.type,
13077 spe->data.update_data_addr.hi,
13078 spe->data.update_data_addr.lo,
13079 bp->cnic_kwq_pending);
13080
13081 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
13082 bp->cnic_kwq_prod = bp->cnic_kwq;
13083 else
13084 bp->cnic_kwq_prod++;
13085 }
13086
13087 spin_unlock_bh(&bp->spq_lock);
13088
13089 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
13090 bnx2x_cnic_sp_post(bp, 0);
13091
13092 return i;
13093 }
13094
13095 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13096 {
13097 struct cnic_ops *c_ops;
13098 int rc = 0;
13099
13100 mutex_lock(&bp->cnic_mutex);
13101 c_ops = rcu_dereference_protected(bp->cnic_ops,
13102 lockdep_is_held(&bp->cnic_mutex));
13103 if (c_ops)
13104 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13105 mutex_unlock(&bp->cnic_mutex);
13106
13107 return rc;
13108 }
13109
13110 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
13111 {
13112 struct cnic_ops *c_ops;
13113 int rc = 0;
13114
13115 rcu_read_lock();
13116 c_ops = rcu_dereference(bp->cnic_ops);
13117 if (c_ops)
13118 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
13119 rcu_read_unlock();
13120
13121 return rc;
13122 }
13123
13124 /*
13125 * for commands that have no data
13126 */
13127 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
13128 {
13129 struct cnic_ctl_info ctl = {0};
13130
13131 ctl.cmd = cmd;
13132
13133 return bnx2x_cnic_ctl_send(bp, &ctl);
13134 }
13135
13136 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
13137 {
13138 struct cnic_ctl_info ctl = {0};
13139
13140 /* first we tell CNIC and only then we count this as a completion */
13141 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
13142 ctl.data.comp.cid = cid;
13143 ctl.data.comp.error = err;
13144
13145 bnx2x_cnic_ctl_send_bh(bp, &ctl);
13146 bnx2x_cnic_sp_post(bp, 0);
13147 }
13148
13149
13150 /* Called with netif_addr_lock_bh() taken.
13151 * Sets an rx_mode config for an iSCSI ETH client.
13152 * Doesn't block.
13153 * Completion should be checked outside.
13154 */
13155 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
13156 {
13157 unsigned long accept_flags = 0, ramrod_flags = 0;
13158 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13159 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
13160
13161 if (start) {
13162 /* Start accepting on iSCSI L2 ring. Accept all multicasts
13163 * because it's the only way for UIO Queue to accept
13164 * multicasts (in non-promiscuous mode only one Queue per
13165 * function will receive multicast packets (leading in our
13166 * case).
13167 */
13168 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
13169 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
13170 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
13171 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
13172
13173 /* Clear STOP_PENDING bit if START is requested */
13174 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
13175
13176 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
13177 } else
13178 /* Clear START_PENDING bit if STOP is requested */
13179 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
13180
13181 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
13182 set_bit(sched_state, &bp->sp_state);
13183 else {
13184 __set_bit(RAMROD_RX, &ramrod_flags);
13185 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
13186 ramrod_flags);
13187 }
13188 }
13189
13190
13191 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
13192 {
13193 struct bnx2x *bp = netdev_priv(dev);
13194 int rc = 0;
13195
13196 switch (ctl->cmd) {
13197 case DRV_CTL_CTXTBL_WR_CMD: {
13198 u32 index = ctl->data.io.offset;
13199 dma_addr_t addr = ctl->data.io.dma_addr;
13200
13201 bnx2x_ilt_wr(bp, index, addr);
13202 break;
13203 }
13204
13205 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
13206 int count = ctl->data.credit.credit_count;
13207
13208 bnx2x_cnic_sp_post(bp, count);
13209 break;
13210 }
13211
13212 /* rtnl_lock is held. */
13213 case DRV_CTL_START_L2_CMD: {
13214 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13215 unsigned long sp_bits = 0;
13216
13217 /* Configure the iSCSI classification object */
13218 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
13219 cp->iscsi_l2_client_id,
13220 cp->iscsi_l2_cid, BP_FUNC(bp),
13221 bnx2x_sp(bp, mac_rdata),
13222 bnx2x_sp_mapping(bp, mac_rdata),
13223 BNX2X_FILTER_MAC_PENDING,
13224 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
13225 &bp->macs_pool);
13226
13227 /* Set iSCSI MAC address */
13228 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
13229 if (rc)
13230 break;
13231
13232 mmiowb();
13233 barrier();
13234
13235 /* Start accepting on iSCSI L2 ring */
13236
13237 netif_addr_lock_bh(dev);
13238 bnx2x_set_iscsi_eth_rx_mode(bp, true);
13239 netif_addr_unlock_bh(dev);
13240
13241 /* bits to wait on */
13242 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13243 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
13244
13245 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13246 BNX2X_ERR("rx_mode completion timed out!\n");
13247
13248 break;
13249 }
13250
13251 /* rtnl_lock is held. */
13252 case DRV_CTL_STOP_L2_CMD: {
13253 unsigned long sp_bits = 0;
13254
13255 /* Stop accepting on iSCSI L2 ring */
13256 netif_addr_lock_bh(dev);
13257 bnx2x_set_iscsi_eth_rx_mode(bp, false);
13258 netif_addr_unlock_bh(dev);
13259
13260 /* bits to wait on */
13261 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
13262 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
13263
13264 if (!bnx2x_wait_sp_comp(bp, sp_bits))
13265 BNX2X_ERR("rx_mode completion timed out!\n");
13266
13267 mmiowb();
13268 barrier();
13269
13270 /* Unset iSCSI L2 MAC */
13271 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
13272 BNX2X_ISCSI_ETH_MAC, true);
13273 break;
13274 }
13275 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
13276 int count = ctl->data.credit.credit_count;
13277
13278 smp_mb__before_atomic_inc();
13279 atomic_add(count, &bp->cq_spq_left);
13280 smp_mb__after_atomic_inc();
13281 break;
13282 }
13283 case DRV_CTL_ULP_REGISTER_CMD: {
13284 int ulp_type = ctl->data.register_data.ulp_type;
13285
13286 if (CHIP_IS_E3(bp)) {
13287 int idx = BP_FW_MB_IDX(bp);
13288 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13289 int path = BP_PATH(bp);
13290 int port = BP_PORT(bp);
13291 int i;
13292 u32 scratch_offset;
13293 u32 *host_addr;
13294
13295 /* first write capability to shmem2 */
13296 if (ulp_type == CNIC_ULP_ISCSI)
13297 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13298 else if (ulp_type == CNIC_ULP_FCOE)
13299 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13300 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13301
13302 if ((ulp_type != CNIC_ULP_FCOE) ||
13303 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
13304 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
13305 break;
13306
13307 /* if reached here - should write fcoe capabilities */
13308 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
13309 if (!scratch_offset)
13310 break;
13311 scratch_offset += offsetof(struct glob_ncsi_oem_data,
13312 fcoe_features[path][port]);
13313 host_addr = (u32 *) &(ctl->data.register_data.
13314 fcoe_features);
13315 for (i = 0; i < sizeof(struct fcoe_capabilities);
13316 i += 4)
13317 REG_WR(bp, scratch_offset + i,
13318 *(host_addr + i/4));
13319 }
13320 break;
13321 }
13322
13323 case DRV_CTL_ULP_UNREGISTER_CMD: {
13324 int ulp_type = ctl->data.ulp_type;
13325
13326 if (CHIP_IS_E3(bp)) {
13327 int idx = BP_FW_MB_IDX(bp);
13328 u32 cap;
13329
13330 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
13331 if (ulp_type == CNIC_ULP_ISCSI)
13332 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
13333 else if (ulp_type == CNIC_ULP_FCOE)
13334 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
13335 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
13336 }
13337 break;
13338 }
13339
13340 default:
13341 BNX2X_ERR("unknown command %x\n", ctl->cmd);
13342 rc = -EINVAL;
13343 }
13344
13345 return rc;
13346 }
13347
13348 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
13349 {
13350 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13351
13352 if (bp->flags & USING_MSIX_FLAG) {
13353 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
13354 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
13355 cp->irq_arr[0].vector = bp->msix_table[1].vector;
13356 } else {
13357 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
13358 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
13359 }
13360 if (!CHIP_IS_E1x(bp))
13361 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
13362 else
13363 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
13364
13365 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
13366 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
13367 cp->irq_arr[1].status_blk = bp->def_status_blk;
13368 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
13369 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
13370
13371 cp->num_irq = 2;
13372 }
13373
13374 void bnx2x_setup_cnic_info(struct bnx2x *bp)
13375 {
13376 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13377
13378
13379 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13380 bnx2x_cid_ilt_lines(bp);
13381 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13382 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13383 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13384
13385 if (NO_ISCSI_OOO(bp))
13386 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13387 }
13388
13389 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
13390 void *data)
13391 {
13392 struct bnx2x *bp = netdev_priv(dev);
13393 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13394 int rc;
13395
13396 DP(NETIF_MSG_IFUP, "Register_cnic called\n");
13397
13398 if (ops == NULL) {
13399 BNX2X_ERR("NULL ops received\n");
13400 return -EINVAL;
13401 }
13402
13403 if (!CNIC_SUPPORT(bp)) {
13404 BNX2X_ERR("Can't register CNIC when not supported\n");
13405 return -EOPNOTSUPP;
13406 }
13407
13408 if (!CNIC_LOADED(bp)) {
13409 rc = bnx2x_load_cnic(bp);
13410 if (rc) {
13411 BNX2X_ERR("CNIC-related load failed\n");
13412 return rc;
13413 }
13414
13415 }
13416
13417 bp->cnic_enabled = true;
13418
13419 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
13420 if (!bp->cnic_kwq)
13421 return -ENOMEM;
13422
13423 bp->cnic_kwq_cons = bp->cnic_kwq;
13424 bp->cnic_kwq_prod = bp->cnic_kwq;
13425 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
13426
13427 bp->cnic_spq_pending = 0;
13428 bp->cnic_kwq_pending = 0;
13429
13430 bp->cnic_data = data;
13431
13432 cp->num_irq = 0;
13433 cp->drv_state |= CNIC_DRV_STATE_REGD;
13434 cp->iro_arr = bp->iro_arr;
13435
13436 bnx2x_setup_cnic_irq_info(bp);
13437
13438 rcu_assign_pointer(bp->cnic_ops, ops);
13439
13440 return 0;
13441 }
13442
13443 static int bnx2x_unregister_cnic(struct net_device *dev)
13444 {
13445 struct bnx2x *bp = netdev_priv(dev);
13446 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13447
13448 mutex_lock(&bp->cnic_mutex);
13449 cp->drv_state = 0;
13450 RCU_INIT_POINTER(bp->cnic_ops, NULL);
13451 mutex_unlock(&bp->cnic_mutex);
13452 synchronize_rcu();
13453 kfree(bp->cnic_kwq);
13454 bp->cnic_kwq = NULL;
13455
13456 return 0;
13457 }
13458
13459 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
13460 {
13461 struct bnx2x *bp = netdev_priv(dev);
13462 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
13463
13464 /* If both iSCSI and FCoE are disabled - return NULL in
13465 * order to indicate CNIC that it should not try to work
13466 * with this device.
13467 */
13468 if (NO_ISCSI(bp) && NO_FCOE(bp))
13469 return NULL;
13470
13471 cp->drv_owner = THIS_MODULE;
13472 cp->chip_id = CHIP_ID(bp);
13473 cp->pdev = bp->pdev;
13474 cp->io_base = bp->regview;
13475 cp->io_base2 = bp->doorbells;
13476 cp->max_kwqe_pending = 8;
13477 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
13478 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
13479 bnx2x_cid_ilt_lines(bp);
13480 cp->ctx_tbl_len = CNIC_ILT_LINES;
13481 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
13482 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
13483 cp->drv_ctl = bnx2x_drv_ctl;
13484 cp->drv_register_cnic = bnx2x_register_cnic;
13485 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
13486 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
13487 cp->iscsi_l2_client_id =
13488 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
13489 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
13490
13491 if (NO_ISCSI_OOO(bp))
13492 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
13493
13494 if (NO_ISCSI(bp))
13495 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
13496
13497 if (NO_FCOE(bp))
13498 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
13499
13500 BNX2X_DEV_INFO(
13501 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
13502 cp->ctx_blk_size,
13503 cp->ctx_tbl_offset,
13504 cp->ctx_tbl_len,
13505 cp->starting_cid);
13506 return cp;
13507 }
13508
13509 u32 bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath *fp)
13510 {
13511 struct bnx2x *bp = fp->bp;
13512 u32 offset = BAR_USTRORM_INTMEM;
13513
13514 if (IS_VF(bp))
13515 return bnx2x_vf_ustorm_prods_offset(bp, fp);
13516 else if (!CHIP_IS_E1x(bp))
13517 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id);
13518 else
13519 offset += USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp), fp->cl_id);
13520
13521 return offset;
13522 }
13523
13524 /* called only on E1H or E2.
13525 * When pretending to be PF, the pretend value is the function number 0...7
13526 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
13527 * combination
13528 */
13529 int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
13530 {
13531 u32 pretend_reg;
13532
13533 if (CHIP_IS_E1H(bp) && pretend_func_val >= E1H_FUNC_MAX)
13534 return -1;
13535
13536 /* get my own pretend register */
13537 pretend_reg = bnx2x_get_pretend_reg(bp);
13538 REG_WR(bp, pretend_reg, pretend_func_val);
13539 REG_RD(bp, pretend_reg);
13540 return 0;
13541 }
Linux kernel - Deliverables
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