projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_main.c
1 /* bnx2x_main.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
42 #include <linux/if_vlan.h>
43 #include <net/ip.h>
44 #include <net/ipv6.h>
45 #include <net/tcp.h>
46 #include <net/checksum.h>
47 #include <net/ip6_checksum.h>
48 #include <linux/workqueue.h>
49 #include <linux/crc32.h>
50 #include <linux/crc32c.h>
51 #include <linux/prefetch.h>
52 #include <linux/zlib.h>
53 #include <linux/io.h>
54 #include <linux/semaphore.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
57
58 #include "bnx2x.h"
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
63 #include "bnx2x_sp.h"
64
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
67 /* FW files */
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
76
77 #define MAC_LEADING_ZERO_CNT (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
78
79 /* Time in jiffies before concluding the transmitter is hung */
80 #define TX_TIMEOUT (5*HZ)
81
82 static char version[] __devinitdata =
83 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
84 DRV_MODULE_NAME " " DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
85
86 MODULE_AUTHOR("Eliezer Tamir");
87 MODULE_DESCRIPTION("Broadcom NetXtreme II "
88 "BCM57710/57711/57711E/"
89 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
90 "57840/57840_MF Driver");
91 MODULE_LICENSE("GPL");
92 MODULE_VERSION(DRV_MODULE_VERSION);
93 MODULE_FIRMWARE(FW_FILE_NAME_E1);
94 MODULE_FIRMWARE(FW_FILE_NAME_E1H);
95 MODULE_FIRMWARE(FW_FILE_NAME_E2);
96
97
98 int num_queues;
99 module_param(num_queues, int, 0);
100 MODULE_PARM_DESC(num_queues,
101 " Set number of queues (default is as a number of CPUs)");
102
103 static int disable_tpa;
104 module_param(disable_tpa, int, 0);
105 MODULE_PARM_DESC(disable_tpa, " Disable the TPA (LRO) feature");
106
107 #define INT_MODE_INTx 1
108 #define INT_MODE_MSI 2
109 int int_mode;
110 module_param(int_mode, int, 0);
111 MODULE_PARM_DESC(int_mode, " Force interrupt mode other than MSI-X "
112 "(1 INT#x; 2 MSI)");
113
114 static int dropless_fc;
115 module_param(dropless_fc, int, 0);
116 MODULE_PARM_DESC(dropless_fc, " Pause on exhausted host ring");
117
118 static int mrrs = -1;
119 module_param(mrrs, int, 0);
120 MODULE_PARM_DESC(mrrs, " Force Max Read Req Size (0..3) (for debug)");
121
122 static int debug;
123 module_param(debug, int, 0);
124 MODULE_PARM_DESC(debug, " Default debug msglevel");
125
126
127
128 struct workqueue_struct *bnx2x_wq;
129
130 enum bnx2x_board_type {
131 BCM57710 = 0,
132 BCM57711,
133 BCM57711E,
134 BCM57712,
135 BCM57712_MF,
136 BCM57800,
137 BCM57800_MF,
138 BCM57810,
139 BCM57810_MF,
140 BCM57840_O,
141 BCM57840_4_10,
142 BCM57840_2_20,
143 BCM57840_MFO,
144 BCM57840_MF,
145 BCM57811,
146 BCM57811_MF
147 };
148
149 /* indexed by board_type, above */
150 static struct {
151 char *name;
152 } board_info[] __devinitdata = {
153 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
154 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
155 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
156 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
157 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
158 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
159 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
160 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
161 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
162 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
163 { "Broadcom NetXtreme II BCM57840 10 Gigabit Ethernet" },
164 { "Broadcom NetXtreme II BCM57840 20 Gigabit Ethernet" },
165 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
166 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet Multi Function"},
167 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet"},
168 { "Broadcom NetXtreme II BCM57811 10 Gigabit Ethernet Multi Function"},
169 };
170
171 #ifndef PCI_DEVICE_ID_NX2_57710
172 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
173 #endif
174 #ifndef PCI_DEVICE_ID_NX2_57711
175 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
176 #endif
177 #ifndef PCI_DEVICE_ID_NX2_57711E
178 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
179 #endif
180 #ifndef PCI_DEVICE_ID_NX2_57712
181 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
182 #endif
183 #ifndef PCI_DEVICE_ID_NX2_57712_MF
184 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
185 #endif
186 #ifndef PCI_DEVICE_ID_NX2_57800
187 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
188 #endif
189 #ifndef PCI_DEVICE_ID_NX2_57800_MF
190 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
191 #endif
192 #ifndef PCI_DEVICE_ID_NX2_57810
193 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
194 #endif
195 #ifndef PCI_DEVICE_ID_NX2_57810_MF
196 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
197 #endif
198 #ifndef PCI_DEVICE_ID_NX2_57840_O
199 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
200 #endif
201 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
202 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
203 #endif
204 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
205 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
206 #endif
207 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
208 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
209 #endif
210 #ifndef PCI_DEVICE_ID_NX2_57840_MF
211 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
212 #endif
213 #ifndef PCI_DEVICE_ID_NX2_57811
214 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
215 #endif
216 #ifndef PCI_DEVICE_ID_NX2_57811_MF
217 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
218 #endif
219 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl) = {
220 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57710), BCM57710 },
221 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711), BCM57711 },
222 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57711E), BCM57711E },
223 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712), BCM57712 },
224 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57712_MF), BCM57712_MF },
225 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800), BCM57800 },
226 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57800_MF), BCM57800_MF },
227 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810), BCM57810 },
228 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57810_MF), BCM57810_MF },
229 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_O), BCM57840_O },
230 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_4_10), BCM57840_4_10 },
231 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_2_20), BCM57840_2_20 },
232 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MFO), BCM57840_MFO },
233 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57840_MF), BCM57840_MF },
234 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811), BCM57811 },
235 { PCI_VDEVICE(BROADCOM, PCI_DEVICE_ID_NX2_57811_MF), BCM57811_MF },
236 { 0 }
237 };
238
239 MODULE_DEVICE_TABLE(pci, bnx2x_pci_tbl);
240
241 /* Global resources for unloading a previously loaded device */
242 #define BNX2X_PREV_WAIT_NEEDED 1
243 static DEFINE_SEMAPHORE(bnx2x_prev_sem);
244 static LIST_HEAD(bnx2x_prev_list);
245 /****************************************************************************
246 * General service functions
247 ****************************************************************************/
248
249 static void __storm_memset_dma_mapping(struct bnx2x *bp,
250 u32 addr, dma_addr_t mapping)
251 {
252 REG_WR(bp, addr, U64_LO(mapping));
253 REG_WR(bp, addr + 4, U64_HI(mapping));
254 }
255
256 static void storm_memset_spq_addr(struct bnx2x *bp,
257 dma_addr_t mapping, u16 abs_fid)
258 {
259 u32 addr = XSEM_REG_FAST_MEMORY +
260 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid);
261
262 __storm_memset_dma_mapping(bp, addr, mapping);
263 }
264
265 static void storm_memset_vf_to_pf(struct bnx2x *bp, u16 abs_fid,
266 u16 pf_id)
267 {
268 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid),
269 pf_id);
270 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid),
271 pf_id);
272 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid),
273 pf_id);
274 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid),
275 pf_id);
276 }
277
278 static void storm_memset_func_en(struct bnx2x *bp, u16 abs_fid,
279 u8 enable)
280 {
281 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid),
282 enable);
283 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid),
284 enable);
285 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid),
286 enable);
287 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid),
288 enable);
289 }
290
291 static void storm_memset_eq_data(struct bnx2x *bp,
292 struct event_ring_data *eq_data,
293 u16 pfid)
294 {
295 size_t size = sizeof(struct event_ring_data);
296
297 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid);
298
299 __storm_memset_struct(bp, addr, size, (u32 *)eq_data);
300 }
301
302 static void storm_memset_eq_prod(struct bnx2x *bp, u16 eq_prod,
303 u16 pfid)
304 {
305 u32 addr = BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_PROD_OFFSET(pfid);
306 REG_WR16(bp, addr, eq_prod);
307 }
308
309 /* used only at init
310 * locking is done by mcp
311 */
312 static void bnx2x_reg_wr_ind(struct bnx2x *bp, u32 addr, u32 val)
313 {
314 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
315 pci_write_config_dword(bp->pdev, PCICFG_GRC_DATA, val);
316 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
317 PCICFG_VENDOR_ID_OFFSET);
318 }
319
320 static u32 bnx2x_reg_rd_ind(struct bnx2x *bp, u32 addr)
321 {
322 u32 val;
323
324 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS, addr);
325 pci_read_config_dword(bp->pdev, PCICFG_GRC_DATA, &val);
326 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
327 PCICFG_VENDOR_ID_OFFSET);
328
329 return val;
330 }
331
332 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
333 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
334 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
335 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
336 #define DMAE_DP_DST_NONE "dst_addr [none]"
337
338
339 /* copy command into DMAE command memory and set DMAE command go */
340 void bnx2x_post_dmae(struct bnx2x *bp, struct dmae_command *dmae, int idx)
341 {
342 u32 cmd_offset;
343 int i;
344
345 cmd_offset = (DMAE_REG_CMD_MEM + sizeof(struct dmae_command) * idx);
346 for (i = 0; i < (sizeof(struct dmae_command)/4); i++) {
347 REG_WR(bp, cmd_offset + i*4, *(((u32 *)dmae) + i));
348 }
349 REG_WR(bp, dmae_reg_go_c[idx], 1);
350 }
351
352 u32 bnx2x_dmae_opcode_add_comp(u32 opcode, u8 comp_type)
353 {
354 return opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) |
355 DMAE_CMD_C_ENABLE);
356 }
357
358 u32 bnx2x_dmae_opcode_clr_src_reset(u32 opcode)
359 {
360 return opcode & ~DMAE_CMD_SRC_RESET;
361 }
362
363 u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
364 bool with_comp, u8 comp_type)
365 {
366 u32 opcode = 0;
367
368 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) |
369 (dst_type << DMAE_COMMAND_DST_SHIFT));
370
371 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
372
373 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
374 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
375 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
376 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
377
378 #ifdef __BIG_ENDIAN
379 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP;
380 #else
381 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP;
382 #endif
383 if (with_comp)
384 opcode = bnx2x_dmae_opcode_add_comp(opcode, comp_type);
385 return opcode;
386 }
387
388 static void bnx2x_prep_dmae_with_comp(struct bnx2x *bp,
389 struct dmae_command *dmae,
390 u8 src_type, u8 dst_type)
391 {
392 memset(dmae, 0, sizeof(struct dmae_command));
393
394 /* set the opcode */
395 dmae->opcode = bnx2x_dmae_opcode(bp, src_type, dst_type,
396 true, DMAE_COMP_PCI);
397
398 /* fill in the completion parameters */
399 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_comp));
400 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_comp));
401 dmae->comp_val = DMAE_COMP_VAL;
402 }
403
404 /* issue a dmae command over the init-channel and wailt for completion */
405 static int bnx2x_issue_dmae_with_comp(struct bnx2x *bp,
406 struct dmae_command *dmae)
407 {
408 u32 *wb_comp = bnx2x_sp(bp, wb_comp);
409 int cnt = CHIP_REV_IS_SLOW(bp) ? (400000) : 4000;
410 int rc = 0;
411
412 /*
413 * Lock the dmae channel. Disable BHs to prevent a dead-lock
414 * as long as this code is called both from syscall context and
415 * from ndo_set_rx_mode() flow that may be called from BH.
416 */
417 spin_lock_bh(&bp->dmae_lock);
418
419 /* reset completion */
420 *wb_comp = 0;
421
422 /* post the command on the channel used for initializations */
423 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
424
425 /* wait for completion */
426 udelay(5);
427 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) {
428
429 if (!cnt ||
430 (bp->recovery_state != BNX2X_RECOVERY_DONE &&
431 bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
432 BNX2X_ERR("DMAE timeout!\n");
433 rc = DMAE_TIMEOUT;
434 goto unlock;
435 }
436 cnt--;
437 udelay(50);
438 }
439 if (*wb_comp & DMAE_PCI_ERR_FLAG) {
440 BNX2X_ERR("DMAE PCI error!\n");
441 rc = DMAE_PCI_ERROR;
442 }
443
444 unlock:
445 spin_unlock_bh(&bp->dmae_lock);
446 return rc;
447 }
448
449 void bnx2x_write_dmae(struct bnx2x *bp, dma_addr_t dma_addr, u32 dst_addr,
450 u32 len32)
451 {
452 struct dmae_command dmae;
453
454 if (!bp->dmae_ready) {
455 u32 *data = bnx2x_sp(bp, wb_data[0]);
456
457 if (CHIP_IS_E1(bp))
458 bnx2x_init_ind_wr(bp, dst_addr, data, len32);
459 else
460 bnx2x_init_str_wr(bp, dst_addr, data, len32);
461 return;
462 }
463
464 /* set opcode and fixed command fields */
465 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC);
466
467 /* fill in addresses and len */
468 dmae.src_addr_lo = U64_LO(dma_addr);
469 dmae.src_addr_hi = U64_HI(dma_addr);
470 dmae.dst_addr_lo = dst_addr >> 2;
471 dmae.dst_addr_hi = 0;
472 dmae.len = len32;
473
474 /* issue the command and wait for completion */
475 bnx2x_issue_dmae_with_comp(bp, &dmae);
476 }
477
478 void bnx2x_read_dmae(struct bnx2x *bp, u32 src_addr, u32 len32)
479 {
480 struct dmae_command dmae;
481
482 if (!bp->dmae_ready) {
483 u32 *data = bnx2x_sp(bp, wb_data[0]);
484 int i;
485
486 if (CHIP_IS_E1(bp))
487 for (i = 0; i < len32; i++)
488 data[i] = bnx2x_reg_rd_ind(bp, src_addr + i*4);
489 else
490 for (i = 0; i < len32; i++)
491 data[i] = REG_RD(bp, src_addr + i*4);
492
493 return;
494 }
495
496 /* set opcode and fixed command fields */
497 bnx2x_prep_dmae_with_comp(bp, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI);
498
499 /* fill in addresses and len */
500 dmae.src_addr_lo = src_addr >> 2;
501 dmae.src_addr_hi = 0;
502 dmae.dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, wb_data));
503 dmae.dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, wb_data));
504 dmae.len = len32;
505
506 /* issue the command and wait for completion */
507 bnx2x_issue_dmae_with_comp(bp, &dmae);
508 }
509
510 static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
511 u32 addr, u32 len)
512 {
513 int dmae_wr_max = DMAE_LEN32_WR_MAX(bp);
514 int offset = 0;
515
516 while (len > dmae_wr_max) {
517 bnx2x_write_dmae(bp, phys_addr + offset,
518 addr + offset, dmae_wr_max);
519 offset += dmae_wr_max * 4;
520 len -= dmae_wr_max;
521 }
522
523 bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
524 }
525
526 static int bnx2x_mc_assert(struct bnx2x *bp)
527 {
528 char last_idx;
529 int i, rc = 0;
530 u32 row0, row1, row2, row3;
531
532 /* XSTORM */
533 last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
534 XSTORM_ASSERT_LIST_INDEX_OFFSET);
535 if (last_idx)
536 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
537
538 /* print the asserts */
539 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
540
541 row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
542 XSTORM_ASSERT_LIST_OFFSET(i));
543 row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
544 XSTORM_ASSERT_LIST_OFFSET(i) + 4);
545 row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
546 XSTORM_ASSERT_LIST_OFFSET(i) + 8);
547 row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
548 XSTORM_ASSERT_LIST_OFFSET(i) + 12);
549
550 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
551 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
552 i, row3, row2, row1, row0);
553 rc++;
554 } else {
555 break;
556 }
557 }
558
559 /* TSTORM */
560 last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
561 TSTORM_ASSERT_LIST_INDEX_OFFSET);
562 if (last_idx)
563 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
564
565 /* print the asserts */
566 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
567
568 row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
569 TSTORM_ASSERT_LIST_OFFSET(i));
570 row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
571 TSTORM_ASSERT_LIST_OFFSET(i) + 4);
572 row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
573 TSTORM_ASSERT_LIST_OFFSET(i) + 8);
574 row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
575 TSTORM_ASSERT_LIST_OFFSET(i) + 12);
576
577 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
578 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
579 i, row3, row2, row1, row0);
580 rc++;
581 } else {
582 break;
583 }
584 }
585
586 /* CSTORM */
587 last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
588 CSTORM_ASSERT_LIST_INDEX_OFFSET);
589 if (last_idx)
590 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
591
592 /* print the asserts */
593 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
594
595 row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
596 CSTORM_ASSERT_LIST_OFFSET(i));
597 row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
598 CSTORM_ASSERT_LIST_OFFSET(i) + 4);
599 row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
600 CSTORM_ASSERT_LIST_OFFSET(i) + 8);
601 row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
602 CSTORM_ASSERT_LIST_OFFSET(i) + 12);
603
604 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
605 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
606 i, row3, row2, row1, row0);
607 rc++;
608 } else {
609 break;
610 }
611 }
612
613 /* USTORM */
614 last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
615 USTORM_ASSERT_LIST_INDEX_OFFSET);
616 if (last_idx)
617 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
618
619 /* print the asserts */
620 for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
621
622 row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
623 USTORM_ASSERT_LIST_OFFSET(i));
624 row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
625 USTORM_ASSERT_LIST_OFFSET(i) + 4);
626 row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
627 USTORM_ASSERT_LIST_OFFSET(i) + 8);
628 row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
629 USTORM_ASSERT_LIST_OFFSET(i) + 12);
630
631 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
632 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
633 i, row3, row2, row1, row0);
634 rc++;
635 } else {
636 break;
637 }
638 }
639
640 return rc;
641 }
642
643 void bnx2x_fw_dump_lvl(struct bnx2x *bp, const char *lvl)
644 {
645 u32 addr, val;
646 u32 mark, offset;
647 __be32 data[9];
648 int word;
649 u32 trace_shmem_base;
650 if (BP_NOMCP(bp)) {
651 BNX2X_ERR("NO MCP - can not dump\n");
652 return;
653 }
654 netdev_printk(lvl, bp->dev, "bc %d.%d.%d\n",
655 (bp->common.bc_ver & 0xff0000) >> 16,
656 (bp->common.bc_ver & 0xff00) >> 8,
657 (bp->common.bc_ver & 0xff));
658
659 val = REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER);
660 if (val == REG_RD(bp, MCP_REG_MCPR_CPU_PROGRAM_COUNTER))
661 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl, val);
662
663 if (BP_PATH(bp) == 0)
664 trace_shmem_base = bp->common.shmem_base;
665 else
666 trace_shmem_base = SHMEM2_RD(bp, other_shmem_base_addr);
667 addr = trace_shmem_base - 0x800;
668
669 /* validate TRCB signature */
670 mark = REG_RD(bp, addr);
671 if (mark != MFW_TRACE_SIGNATURE) {
672 BNX2X_ERR("Trace buffer signature is missing.");
673 return ;
674 }
675
676 /* read cyclic buffer pointer */
677 addr += 4;
678 mark = REG_RD(bp, addr);
679 mark = (CHIP_IS_E1x(bp) ? MCP_REG_MCPR_SCRATCH : MCP_A_REG_MCPR_SCRATCH)
680 + ((mark + 0x3) & ~0x3) - 0x08000000;
681 printk("%s" "begin fw dump (mark 0x%x)\n", lvl, mark);
682
683 printk("%s", lvl);
684 for (offset = mark; offset <= trace_shmem_base; offset += 0x8*4) {
685 for (word = 0; word < 8; word++)
686 data[word] = htonl(REG_RD(bp, offset + 4*word));
687 data[8] = 0x0;
688 pr_cont("%s", (char *)data);
689 }
690 for (offset = addr + 4; offset <= mark; offset += 0x8*4) {
691 for (word = 0; word < 8; word++)
692 data[word] = htonl(REG_RD(bp, offset + 4*word));
693 data[8] = 0x0;
694 pr_cont("%s", (char *)data);
695 }
696 printk("%s" "end of fw dump\n", lvl);
697 }
698
699 static void bnx2x_fw_dump(struct bnx2x *bp)
700 {
701 bnx2x_fw_dump_lvl(bp, KERN_ERR);
702 }
703
704 void bnx2x_panic_dump(struct bnx2x *bp)
705 {
706 int i;
707 u16 j;
708 struct hc_sp_status_block_data sp_sb_data;
709 int func = BP_FUNC(bp);
710 #ifdef BNX2X_STOP_ON_ERROR
711 u16 start = 0, end = 0;
712 u8 cos;
713 #endif
714
715 bp->stats_state = STATS_STATE_DISABLED;
716 bp->eth_stats.unrecoverable_error++;
717 DP(BNX2X_MSG_STATS, "stats_state - DISABLED\n");
718
719 BNX2X_ERR("begin crash dump -----------------\n");
720
721 /* Indices */
722 /* Common */
723 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
724 bp->def_idx, bp->def_att_idx, bp->attn_state,
725 bp->spq_prod_idx, bp->stats_counter);
726 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
727 bp->def_status_blk->atten_status_block.attn_bits,
728 bp->def_status_blk->atten_status_block.attn_bits_ack,
729 bp->def_status_blk->atten_status_block.status_block_id,
730 bp->def_status_blk->atten_status_block.attn_bits_index);
731 BNX2X_ERR(" def (");
732 for (i = 0; i < HC_SP_SB_MAX_INDICES; i++)
733 pr_cont("0x%x%s",
734 bp->def_status_blk->sp_sb.index_values[i],
735 (i == HC_SP_SB_MAX_INDICES - 1) ? ") " : " ");
736
737 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
738 *((u32 *)&sp_sb_data + i) = REG_RD(bp, BAR_CSTRORM_INTMEM +
739 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
740 i*sizeof(u32));
741
742 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
743 sp_sb_data.igu_sb_id,
744 sp_sb_data.igu_seg_id,
745 sp_sb_data.p_func.pf_id,
746 sp_sb_data.p_func.vnic_id,
747 sp_sb_data.p_func.vf_id,
748 sp_sb_data.p_func.vf_valid,
749 sp_sb_data.state);
750
751
752 for_each_eth_queue(bp, i) {
753 struct bnx2x_fastpath *fp = &bp->fp[i];
754 int loop;
755 struct hc_status_block_data_e2 sb_data_e2;
756 struct hc_status_block_data_e1x sb_data_e1x;
757 struct hc_status_block_sm *hc_sm_p =
758 CHIP_IS_E1x(bp) ?
759 sb_data_e1x.common.state_machine :
760 sb_data_e2.common.state_machine;
761 struct hc_index_data *hc_index_p =
762 CHIP_IS_E1x(bp) ?
763 sb_data_e1x.index_data :
764 sb_data_e2.index_data;
765 u8 data_size, cos;
766 u32 *sb_data_p;
767 struct bnx2x_fp_txdata txdata;
768
769 /* Rx */
770 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
771 i, fp->rx_bd_prod, fp->rx_bd_cons,
772 fp->rx_comp_prod,
773 fp->rx_comp_cons, le16_to_cpu(*fp->rx_cons_sb));
774 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
775 fp->rx_sge_prod, fp->last_max_sge,
776 le16_to_cpu(fp->fp_hc_idx));
777
778 /* Tx */
779 for_each_cos_in_tx_queue(fp, cos)
780 {
781 txdata = *fp->txdata_ptr[cos];
782 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
783 i, txdata.tx_pkt_prod,
784 txdata.tx_pkt_cons, txdata.tx_bd_prod,
785 txdata.tx_bd_cons,
786 le16_to_cpu(*txdata.tx_cons_sb));
787 }
788
789 loop = CHIP_IS_E1x(bp) ?
790 HC_SB_MAX_INDICES_E1X : HC_SB_MAX_INDICES_E2;
791
792 /* host sb data */
793
794 #ifdef BCM_CNIC
795 if (IS_FCOE_FP(fp))
796 continue;
797 #endif
798 BNX2X_ERR(" run indexes (");
799 for (j = 0; j < HC_SB_MAX_SM; j++)
800 pr_cont("0x%x%s",
801 fp->sb_running_index[j],
802 (j == HC_SB_MAX_SM - 1) ? ")" : " ");
803
804 BNX2X_ERR(" indexes (");
805 for (j = 0; j < loop; j++)
806 pr_cont("0x%x%s",
807 fp->sb_index_values[j],
808 (j == loop - 1) ? ")" : " ");
809 /* fw sb data */
810 data_size = CHIP_IS_E1x(bp) ?
811 sizeof(struct hc_status_block_data_e1x) :
812 sizeof(struct hc_status_block_data_e2);
813 data_size /= sizeof(u32);
814 sb_data_p = CHIP_IS_E1x(bp) ?
815 (u32 *)&sb_data_e1x :
816 (u32 *)&sb_data_e2;
817 /* copy sb data in here */
818 for (j = 0; j < data_size; j++)
819 *(sb_data_p + j) = REG_RD(bp, BAR_CSTRORM_INTMEM +
820 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp->fw_sb_id) +
821 j * sizeof(u32));
822
823 if (!CHIP_IS_E1x(bp)) {
824 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
825 sb_data_e2.common.p_func.pf_id,
826 sb_data_e2.common.p_func.vf_id,
827 sb_data_e2.common.p_func.vf_valid,
828 sb_data_e2.common.p_func.vnic_id,
829 sb_data_e2.common.same_igu_sb_1b,
830 sb_data_e2.common.state);
831 } else {
832 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
833 sb_data_e1x.common.p_func.pf_id,
834 sb_data_e1x.common.p_func.vf_id,
835 sb_data_e1x.common.p_func.vf_valid,
836 sb_data_e1x.common.p_func.vnic_id,
837 sb_data_e1x.common.same_igu_sb_1b,
838 sb_data_e1x.common.state);
839 }
840
841 /* SB_SMs data */
842 for (j = 0; j < HC_SB_MAX_SM; j++) {
843 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
844 j, hc_sm_p[j].__flags,
845 hc_sm_p[j].igu_sb_id,
846 hc_sm_p[j].igu_seg_id,
847 hc_sm_p[j].time_to_expire,
848 hc_sm_p[j].timer_value);
849 }
850
851 /* Indecies data */
852 for (j = 0; j < loop; j++) {
853 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j,
854 hc_index_p[j].flags,
855 hc_index_p[j].timeout);
856 }
857 }
858
859 #ifdef BNX2X_STOP_ON_ERROR
860 /* Rings */
861 /* Rx */
862 for_each_rx_queue(bp, i) {
863 struct bnx2x_fastpath *fp = &bp->fp[i];
864
865 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
866 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
867 for (j = start; j != end; j = RX_BD(j + 1)) {
868 u32 *rx_bd = (u32 *)&fp->rx_desc_ring[j];
869 struct sw_rx_bd *sw_bd = &fp->rx_buf_ring[j];
870
871 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
872 i, j, rx_bd[1], rx_bd[0], sw_bd->data);
873 }
874
875 start = RX_SGE(fp->rx_sge_prod);
876 end = RX_SGE(fp->last_max_sge);
877 for (j = start; j != end; j = RX_SGE(j + 1)) {
878 u32 *rx_sge = (u32 *)&fp->rx_sge_ring[j];
879 struct sw_rx_page *sw_page = &fp->rx_page_ring[j];
880
881 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
882 i, j, rx_sge[1], rx_sge[0], sw_page->page);
883 }
884
885 start = RCQ_BD(fp->rx_comp_cons - 10);
886 end = RCQ_BD(fp->rx_comp_cons + 503);
887 for (j = start; j != end; j = RCQ_BD(j + 1)) {
888 u32 *cqe = (u32 *)&fp->rx_comp_ring[j];
889
890 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
891 i, j, cqe[0], cqe[1], cqe[2], cqe[3]);
892 }
893 }
894
895 /* Tx */
896 for_each_tx_queue(bp, i) {
897 struct bnx2x_fastpath *fp = &bp->fp[i];
898 for_each_cos_in_tx_queue(fp, cos) {
899 struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
900
901 start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
902 end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
903 for (j = start; j != end; j = TX_BD(j + 1)) {
904 struct sw_tx_bd *sw_bd =
905 &txdata->tx_buf_ring[j];
906
907 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
908 i, cos, j, sw_bd->skb,
909 sw_bd->first_bd);
910 }
911
912 start = TX_BD(txdata->tx_bd_cons - 10);
913 end = TX_BD(txdata->tx_bd_cons + 254);
914 for (j = start; j != end; j = TX_BD(j + 1)) {
915 u32 *tx_bd = (u32 *)&txdata->tx_desc_ring[j];
916
917 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
918 i, cos, j, tx_bd[0], tx_bd[1],
919 tx_bd[2], tx_bd[3]);
920 }
921 }
922 }
923 #endif
924 bnx2x_fw_dump(bp);
925 bnx2x_mc_assert(bp);
926 BNX2X_ERR("end crash dump -----------------\n");
927 }
928
929 /*
930 * FLR Support for E2
931 *
932 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
933 * initialization.
934 */
935 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
936 #define FLR_WAIT_INTERVAL 50 /* usec */
937 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
938
939 struct pbf_pN_buf_regs {
940 int pN;
941 u32 init_crd;
942 u32 crd;
943 u32 crd_freed;
944 };
945
946 struct pbf_pN_cmd_regs {
947 int pN;
948 u32 lines_occup;
949 u32 lines_freed;
950 };
951
952 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x *bp,
953 struct pbf_pN_buf_regs *regs,
954 u32 poll_count)
955 {
956 u32 init_crd, crd, crd_start, crd_freed, crd_freed_start;
957 u32 cur_cnt = poll_count;
958
959 crd_freed = crd_freed_start = REG_RD(bp, regs->crd_freed);
960 crd = crd_start = REG_RD(bp, regs->crd);
961 init_crd = REG_RD(bp, regs->init_crd);
962
963 DP(BNX2X_MSG_SP, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd);
964 DP(BNX2X_MSG_SP, "CREDIT[%d] : s:%x\n", regs->pN, crd);
965 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed);
966
967 while ((crd != init_crd) && ((u32)SUB_S32(crd_freed, crd_freed_start) <
968 (init_crd - crd_start))) {
969 if (cur_cnt--) {
970 udelay(FLR_WAIT_INTERVAL);
971 crd = REG_RD(bp, regs->crd);
972 crd_freed = REG_RD(bp, regs->crd_freed);
973 } else {
974 DP(BNX2X_MSG_SP, "PBF tx buffer[%d] timed out\n",
975 regs->pN);
976 DP(BNX2X_MSG_SP, "CREDIT[%d] : c:%x\n",
977 regs->pN, crd);
978 DP(BNX2X_MSG_SP, "CREDIT_FREED[%d]: c:%x\n",
979 regs->pN, crd_freed);
980 break;
981 }
982 }
983 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF tx buffer[%d]\n",
984 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
985 }
986
987 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x *bp,
988 struct pbf_pN_cmd_regs *regs,
989 u32 poll_count)
990 {
991 u32 occup, to_free, freed, freed_start;
992 u32 cur_cnt = poll_count;
993
994 occup = to_free = REG_RD(bp, regs->lines_occup);
995 freed = freed_start = REG_RD(bp, regs->lines_freed);
996
997 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup);
998 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n", regs->pN, freed);
999
1000 while (occup && ((u32)SUB_S32(freed, freed_start) < to_free)) {
1001 if (cur_cnt--) {
1002 udelay(FLR_WAIT_INTERVAL);
1003 occup = REG_RD(bp, regs->lines_occup);
1004 freed = REG_RD(bp, regs->lines_freed);
1005 } else {
1006 DP(BNX2X_MSG_SP, "PBF cmd queue[%d] timed out\n",
1007 regs->pN);
1008 DP(BNX2X_MSG_SP, "OCCUPANCY[%d] : s:%x\n",
1009 regs->pN, occup);
1010 DP(BNX2X_MSG_SP, "LINES_FREED[%d] : s:%x\n",
1011 regs->pN, freed);
1012 break;
1013 }
1014 }
1015 DP(BNX2X_MSG_SP, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1016 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN);
1017 }
1018
1019 static u32 bnx2x_flr_clnup_reg_poll(struct bnx2x *bp, u32 reg,
1020 u32 expected, u32 poll_count)
1021 {
1022 u32 cur_cnt = poll_count;
1023 u32 val;
1024
1025 while ((val = REG_RD(bp, reg)) != expected && cur_cnt--)
1026 udelay(FLR_WAIT_INTERVAL);
1027
1028 return val;
1029 }
1030
1031 static int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x *bp, u32 reg,
1032 char *msg, u32 poll_cnt)
1033 {
1034 u32 val = bnx2x_flr_clnup_reg_poll(bp, reg, 0, poll_cnt);
1035 if (val != 0) {
1036 BNX2X_ERR("%s usage count=%d\n", msg, val);
1037 return 1;
1038 }
1039 return 0;
1040 }
1041
1042 static u32 bnx2x_flr_clnup_poll_count(struct bnx2x *bp)
1043 {
1044 /* adjust polling timeout */
1045 if (CHIP_REV_IS_EMUL(bp))
1046 return FLR_POLL_CNT * 2000;
1047
1048 if (CHIP_REV_IS_FPGA(bp))
1049 return FLR_POLL_CNT * 120;
1050
1051 return FLR_POLL_CNT;
1052 }
1053
1054 static void bnx2x_tx_hw_flushed(struct bnx2x *bp, u32 poll_count)
1055 {
1056 struct pbf_pN_cmd_regs cmd_regs[] = {
1057 {0, (CHIP_IS_E3B0(bp)) ?
1058 PBF_REG_TQ_OCCUPANCY_Q0 :
1059 PBF_REG_P0_TQ_OCCUPANCY,
1060 (CHIP_IS_E3B0(bp)) ?
1061 PBF_REG_TQ_LINES_FREED_CNT_Q0 :
1062 PBF_REG_P0_TQ_LINES_FREED_CNT},
1063 {1, (CHIP_IS_E3B0(bp)) ?
1064 PBF_REG_TQ_OCCUPANCY_Q1 :
1065 PBF_REG_P1_TQ_OCCUPANCY,
1066 (CHIP_IS_E3B0(bp)) ?
1067 PBF_REG_TQ_LINES_FREED_CNT_Q1 :
1068 PBF_REG_P1_TQ_LINES_FREED_CNT},
1069 {4, (CHIP_IS_E3B0(bp)) ?
1070 PBF_REG_TQ_OCCUPANCY_LB_Q :
1071 PBF_REG_P4_TQ_OCCUPANCY,
1072 (CHIP_IS_E3B0(bp)) ?
1073 PBF_REG_TQ_LINES_FREED_CNT_LB_Q :
1074 PBF_REG_P4_TQ_LINES_FREED_CNT}
1075 };
1076
1077 struct pbf_pN_buf_regs buf_regs[] = {
1078 {0, (CHIP_IS_E3B0(bp)) ?
1079 PBF_REG_INIT_CRD_Q0 :
1080 PBF_REG_P0_INIT_CRD ,
1081 (CHIP_IS_E3B0(bp)) ?
1082 PBF_REG_CREDIT_Q0 :
1083 PBF_REG_P0_CREDIT,
1084 (CHIP_IS_E3B0(bp)) ?
1085 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 :
1086 PBF_REG_P0_INTERNAL_CRD_FREED_CNT},
1087 {1, (CHIP_IS_E3B0(bp)) ?
1088 PBF_REG_INIT_CRD_Q1 :
1089 PBF_REG_P1_INIT_CRD,
1090 (CHIP_IS_E3B0(bp)) ?
1091 PBF_REG_CREDIT_Q1 :
1092 PBF_REG_P1_CREDIT,
1093 (CHIP_IS_E3B0(bp)) ?
1094 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 :
1095 PBF_REG_P1_INTERNAL_CRD_FREED_CNT},
1096 {4, (CHIP_IS_E3B0(bp)) ?
1097 PBF_REG_INIT_CRD_LB_Q :
1098 PBF_REG_P4_INIT_CRD,
1099 (CHIP_IS_E3B0(bp)) ?
1100 PBF_REG_CREDIT_LB_Q :
1101 PBF_REG_P4_CREDIT,
1102 (CHIP_IS_E3B0(bp)) ?
1103 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q :
1104 PBF_REG_P4_INTERNAL_CRD_FREED_CNT},
1105 };
1106
1107 int i;
1108
1109 /* Verify the command queues are flushed P0, P1, P4 */
1110 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++)
1111 bnx2x_pbf_pN_cmd_flushed(bp, &cmd_regs[i], poll_count);
1112
1113
1114 /* Verify the transmission buffers are flushed P0, P1, P4 */
1115 for (i = 0; i < ARRAY_SIZE(buf_regs); i++)
1116 bnx2x_pbf_pN_buf_flushed(bp, &buf_regs[i], poll_count);
1117 }
1118
1119 #define OP_GEN_PARAM(param) \
1120 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1121
1122 #define OP_GEN_TYPE(type) \
1123 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1124
1125 #define OP_GEN_AGG_VECT(index) \
1126 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1127
1128
1129 static int bnx2x_send_final_clnup(struct bnx2x *bp, u8 clnup_func,
1130 u32 poll_cnt)
1131 {
1132 struct sdm_op_gen op_gen = {0};
1133
1134 u32 comp_addr = BAR_CSTRORM_INTMEM +
1135 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func);
1136 int ret = 0;
1137
1138 if (REG_RD(bp, comp_addr)) {
1139 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1140 return 1;
1141 }
1142
1143 op_gen.command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX);
1144 op_gen.command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE);
1145 op_gen.command |= OP_GEN_AGG_VECT(clnup_func);
1146 op_gen.command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT;
1147
1148 DP(BNX2X_MSG_SP, "sending FW Final cleanup\n");
1149 REG_WR(bp, XSDM_REG_OPERATION_GEN, op_gen.command);
1150
1151 if (bnx2x_flr_clnup_reg_poll(bp, comp_addr, 1, poll_cnt) != 1) {
1152 BNX2X_ERR("FW final cleanup did not succeed\n");
1153 DP(BNX2X_MSG_SP, "At timeout completion address contained %x\n",
1154 (REG_RD(bp, comp_addr)));
1155 ret = 1;
1156 }
1157 /* Zero completion for nxt FLR */
1158 REG_WR(bp, comp_addr, 0);
1159
1160 return ret;
1161 }
1162
1163 static u8 bnx2x_is_pcie_pending(struct pci_dev *dev)
1164 {
1165 int pos;
1166 u16 status;
1167
1168 pos = pci_pcie_cap(dev);
1169 if (!pos)
1170 return false;
1171
1172 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
1173 return status & PCI_EXP_DEVSTA_TRPND;
1174 }
1175
1176 /* PF FLR specific routines
1177 */
1178 static int bnx2x_poll_hw_usage_counters(struct bnx2x *bp, u32 poll_cnt)
1179 {
1180
1181 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1182 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1183 CFC_REG_NUM_LCIDS_INSIDE_PF,
1184 "CFC PF usage counter timed out",
1185 poll_cnt))
1186 return 1;
1187
1188
1189 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1190 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1191 DORQ_REG_PF_USAGE_CNT,
1192 "DQ PF usage counter timed out",
1193 poll_cnt))
1194 return 1;
1195
1196 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1197 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1198 QM_REG_PF_USG_CNT_0 + 4*BP_FUNC(bp),
1199 "QM PF usage counter timed out",
1200 poll_cnt))
1201 return 1;
1202
1203 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1204 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1205 TM_REG_LIN0_VNIC_UC + 4*BP_PORT(bp),
1206 "Timers VNIC usage counter timed out",
1207 poll_cnt))
1208 return 1;
1209 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1210 TM_REG_LIN0_NUM_SCANS + 4*BP_PORT(bp),
1211 "Timers NUM_SCANS usage counter timed out",
1212 poll_cnt))
1213 return 1;
1214
1215 /* Wait DMAE PF usage counter to zero */
1216 if (bnx2x_flr_clnup_poll_hw_counter(bp,
1217 dmae_reg_go_c[INIT_DMAE_C(bp)],
1218 "DMAE dommand register timed out",
1219 poll_cnt))
1220 return 1;
1221
1222 return 0;
1223 }
1224
1225 static void bnx2x_hw_enable_status(struct bnx2x *bp)
1226 {
1227 u32 val;
1228
1229 val = REG_RD(bp, CFC_REG_WEAK_ENABLE_PF);
1230 DP(BNX2X_MSG_SP, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val);
1231
1232 val = REG_RD(bp, PBF_REG_DISABLE_PF);
1233 DP(BNX2X_MSG_SP, "PBF_REG_DISABLE_PF is 0x%x\n", val);
1234
1235 val = REG_RD(bp, IGU_REG_PCI_PF_MSI_EN);
1236 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val);
1237
1238 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_EN);
1239 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val);
1240
1241 val = REG_RD(bp, IGU_REG_PCI_PF_MSIX_FUNC_MASK);
1242 DP(BNX2X_MSG_SP, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val);
1243
1244 val = REG_RD(bp, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR);
1245 DP(BNX2X_MSG_SP, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val);
1246
1247 val = REG_RD(bp, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR);
1248 DP(BNX2X_MSG_SP, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val);
1249
1250 val = REG_RD(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER);
1251 DP(BNX2X_MSG_SP, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1252 val);
1253 }
1254
1255 static int bnx2x_pf_flr_clnup(struct bnx2x *bp)
1256 {
1257 u32 poll_cnt = bnx2x_flr_clnup_poll_count(bp);
1258
1259 DP(BNX2X_MSG_SP, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp));
1260
1261 /* Re-enable PF target read access */
1262 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
1263
1264 /* Poll HW usage counters */
1265 DP(BNX2X_MSG_SP, "Polling usage counters\n");
1266 if (bnx2x_poll_hw_usage_counters(bp, poll_cnt))
1267 return -EBUSY;
1268
1269 /* Zero the igu 'trailing edge' and 'leading edge' */
1270
1271 /* Send the FW cleanup command */
1272 if (bnx2x_send_final_clnup(bp, (u8)BP_FUNC(bp), poll_cnt))
1273 return -EBUSY;
1274
1275 /* ATC cleanup */
1276
1277 /* Verify TX hw is flushed */
1278 bnx2x_tx_hw_flushed(bp, poll_cnt);
1279
1280 /* Wait 100ms (not adjusted according to platform) */
1281 msleep(100);
1282
1283 /* Verify no pending pci transactions */
1284 if (bnx2x_is_pcie_pending(bp->pdev))
1285 BNX2X_ERR("PCIE Transactions still pending\n");
1286
1287 /* Debug */
1288 bnx2x_hw_enable_status(bp);
1289
1290 /*
1291 * Master enable - Due to WB DMAE writes performed before this
1292 * register is re-initialized as part of the regular function init
1293 */
1294 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
1295
1296 return 0;
1297 }
1298
1299 static void bnx2x_hc_int_enable(struct bnx2x *bp)
1300 {
1301 int port = BP_PORT(bp);
1302 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1303 u32 val = REG_RD(bp, addr);
1304 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1305 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1306 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1307
1308 if (msix) {
1309 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1310 HC_CONFIG_0_REG_INT_LINE_EN_0);
1311 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1312 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1313 if (single_msix)
1314 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0;
1315 } else if (msi) {
1316 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0;
1317 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1318 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1319 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1320 } else {
1321 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1322 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1323 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1324 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1325
1326 if (!CHIP_IS_E1(bp)) {
1327 DP(NETIF_MSG_IFUP,
1328 "write %x to HC %d (addr 0x%x)\n", val, port, addr);
1329
1330 REG_WR(bp, addr, val);
1331
1332 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0;
1333 }
1334 }
1335
1336 if (CHIP_IS_E1(bp))
1337 REG_WR(bp, HC_REG_INT_MASK + port*4, 0x1FFFF);
1338
1339 DP(NETIF_MSG_IFUP,
1340 "write %x to HC %d (addr 0x%x) mode %s\n", val, port, addr,
1341 (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1342
1343 REG_WR(bp, addr, val);
1344 /*
1345 * Ensure that HC_CONFIG is written before leading/trailing edge config
1346 */
1347 mmiowb();
1348 barrier();
1349
1350 if (!CHIP_IS_E1(bp)) {
1351 /* init leading/trailing edge */
1352 if (IS_MF(bp)) {
1353 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1354 if (bp->port.pmf)
1355 /* enable nig and gpio3 attention */
1356 val |= 0x1100;
1357 } else
1358 val = 0xffff;
1359
1360 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
1361 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
1362 }
1363
1364 /* Make sure that interrupts are indeed enabled from here on */
1365 mmiowb();
1366 }
1367
1368 static void bnx2x_igu_int_enable(struct bnx2x *bp)
1369 {
1370 u32 val;
1371 bool msix = (bp->flags & USING_MSIX_FLAG) ? true : false;
1372 bool single_msix = (bp->flags & USING_SINGLE_MSIX_FLAG) ? true : false;
1373 bool msi = (bp->flags & USING_MSI_FLAG) ? true : false;
1374
1375 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1376
1377 if (msix) {
1378 val &= ~(IGU_PF_CONF_INT_LINE_EN |
1379 IGU_PF_CONF_SINGLE_ISR_EN);
1380 val |= (IGU_PF_CONF_FUNC_EN |
1381 IGU_PF_CONF_MSI_MSIX_EN |
1382 IGU_PF_CONF_ATTN_BIT_EN);
1383
1384 if (single_msix)
1385 val |= IGU_PF_CONF_SINGLE_ISR_EN;
1386 } else if (msi) {
1387 val &= ~IGU_PF_CONF_INT_LINE_EN;
1388 val |= (IGU_PF_CONF_FUNC_EN |
1389 IGU_PF_CONF_MSI_MSIX_EN |
1390 IGU_PF_CONF_ATTN_BIT_EN |
1391 IGU_PF_CONF_SINGLE_ISR_EN);
1392 } else {
1393 val &= ~IGU_PF_CONF_MSI_MSIX_EN;
1394 val |= (IGU_PF_CONF_FUNC_EN |
1395 IGU_PF_CONF_INT_LINE_EN |
1396 IGU_PF_CONF_ATTN_BIT_EN |
1397 IGU_PF_CONF_SINGLE_ISR_EN);
1398 }
1399
1400 DP(NETIF_MSG_IFUP, "write 0x%x to IGU mode %s\n",
1401 val, (msix ? "MSI-X" : (msi ? "MSI" : "INTx")));
1402
1403 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1404
1405 if (val & IGU_PF_CONF_INT_LINE_EN)
1406 pci_intx(bp->pdev, true);
1407
1408 barrier();
1409
1410 /* init leading/trailing edge */
1411 if (IS_MF(bp)) {
1412 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1413 if (bp->port.pmf)
1414 /* enable nig and gpio3 attention */
1415 val |= 0x1100;
1416 } else
1417 val = 0xffff;
1418
1419 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
1420 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
1421
1422 /* Make sure that interrupts are indeed enabled from here on */
1423 mmiowb();
1424 }
1425
1426 void bnx2x_int_enable(struct bnx2x *bp)
1427 {
1428 if (bp->common.int_block == INT_BLOCK_HC)
1429 bnx2x_hc_int_enable(bp);
1430 else
1431 bnx2x_igu_int_enable(bp);
1432 }
1433
1434 static void bnx2x_hc_int_disable(struct bnx2x *bp)
1435 {
1436 int port = BP_PORT(bp);
1437 u32 addr = port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0;
1438 u32 val = REG_RD(bp, addr);
1439
1440 /*
1441 * in E1 we must use only PCI configuration space to disable
1442 * MSI/MSIX capablility
1443 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1444 */
1445 if (CHIP_IS_E1(bp)) {
1446 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1447 * Use mask register to prevent from HC sending interrupts
1448 * after we exit the function
1449 */
1450 REG_WR(bp, HC_REG_INT_MASK + port*4, 0);
1451
1452 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1453 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1454 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1455 } else
1456 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 |
1457 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 |
1458 HC_CONFIG_0_REG_INT_LINE_EN_0 |
1459 HC_CONFIG_0_REG_ATTN_BIT_EN_0);
1460
1461 DP(NETIF_MSG_IFDOWN,
1462 "write %x to HC %d (addr 0x%x)\n",
1463 val, port, addr);
1464
1465 /* flush all outstanding writes */
1466 mmiowb();
1467
1468 REG_WR(bp, addr, val);
1469 if (REG_RD(bp, addr) != val)
1470 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1471 }
1472
1473 static void bnx2x_igu_int_disable(struct bnx2x *bp)
1474 {
1475 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
1476
1477 val &= ~(IGU_PF_CONF_MSI_MSIX_EN |
1478 IGU_PF_CONF_INT_LINE_EN |
1479 IGU_PF_CONF_ATTN_BIT_EN);
1480
1481 DP(NETIF_MSG_IFDOWN, "write %x to IGU\n", val);
1482
1483 /* flush all outstanding writes */
1484 mmiowb();
1485
1486 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
1487 if (REG_RD(bp, IGU_REG_PF_CONFIGURATION) != val)
1488 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1489 }
1490
1491 void bnx2x_int_disable(struct bnx2x *bp)
1492 {
1493 if (bp->common.int_block == INT_BLOCK_HC)
1494 bnx2x_hc_int_disable(bp);
1495 else
1496 bnx2x_igu_int_disable(bp);
1497 }
1498
1499 void bnx2x_int_disable_sync(struct bnx2x *bp, int disable_hw)
1500 {
1501 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
1502 int i, offset;
1503
1504 if (disable_hw)
1505 /* prevent the HW from sending interrupts */
1506 bnx2x_int_disable(bp);
1507
1508 /* make sure all ISRs are done */
1509 if (msix) {
1510 synchronize_irq(bp->msix_table[0].vector);
1511 offset = 1;
1512 #ifdef BCM_CNIC
1513 offset++;
1514 #endif
1515 for_each_eth_queue(bp, i)
1516 synchronize_irq(bp->msix_table[offset++].vector);
1517 } else
1518 synchronize_irq(bp->pdev->irq);
1519
1520 /* make sure sp_task is not running */
1521 cancel_delayed_work(&bp->sp_task);
1522 cancel_delayed_work(&bp->period_task);
1523 flush_workqueue(bnx2x_wq);
1524 }
1525
1526 /* fast path */
1527
1528 /*
1529 * General service functions
1530 */
1531
1532 /* Return true if succeeded to acquire the lock */
1533 static bool bnx2x_trylock_hw_lock(struct bnx2x *bp, u32 resource)
1534 {
1535 u32 lock_status;
1536 u32 resource_bit = (1 << resource);
1537 int func = BP_FUNC(bp);
1538 u32 hw_lock_control_reg;
1539
1540 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1541 "Trying to take a lock on resource %d\n", resource);
1542
1543 /* Validating that the resource is within range */
1544 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1545 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1546 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1547 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1548 return false;
1549 }
1550
1551 if (func <= 5)
1552 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1553 else
1554 hw_lock_control_reg =
1555 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1556
1557 /* Try to acquire the lock */
1558 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1559 lock_status = REG_RD(bp, hw_lock_control_reg);
1560 if (lock_status & resource_bit)
1561 return true;
1562
1563 DP(NETIF_MSG_HW | NETIF_MSG_IFUP,
1564 "Failed to get a lock on resource %d\n", resource);
1565 return false;
1566 }
1567
1568 /**
1569 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1570 *
1571 * @bp: driver handle
1572 *
1573 * Returns the recovery leader resource id according to the engine this function
1574 * belongs to. Currently only only 2 engines is supported.
1575 */
1576 static int bnx2x_get_leader_lock_resource(struct bnx2x *bp)
1577 {
1578 if (BP_PATH(bp))
1579 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1;
1580 else
1581 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0;
1582 }
1583
1584 /**
1585 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1586 *
1587 * @bp: driver handle
1588 *
1589 * Tries to aquire a leader lock for current engine.
1590 */
1591 static bool bnx2x_trylock_leader_lock(struct bnx2x *bp)
1592 {
1593 return bnx2x_trylock_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1594 }
1595
1596 #ifdef BCM_CNIC
1597 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err);
1598 #endif
1599
1600 void bnx2x_sp_event(struct bnx2x_fastpath *fp, union eth_rx_cqe *rr_cqe)
1601 {
1602 struct bnx2x *bp = fp->bp;
1603 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1604 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data);
1605 enum bnx2x_queue_cmd drv_cmd = BNX2X_Q_CMD_MAX;
1606 struct bnx2x_queue_sp_obj *q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
1607
1608 DP(BNX2X_MSG_SP,
1609 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1610 fp->index, cid, command, bp->state,
1611 rr_cqe->ramrod_cqe.ramrod_type);
1612
1613 switch (command) {
1614 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE):
1615 DP(BNX2X_MSG_SP, "got UPDATE ramrod. CID %d\n", cid);
1616 drv_cmd = BNX2X_Q_CMD_UPDATE;
1617 break;
1618
1619 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP):
1620 DP(BNX2X_MSG_SP, "got MULTI[%d] setup ramrod\n", cid);
1621 drv_cmd = BNX2X_Q_CMD_SETUP;
1622 break;
1623
1624 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP):
1625 DP(BNX2X_MSG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid);
1626 drv_cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
1627 break;
1628
1629 case (RAMROD_CMD_ID_ETH_HALT):
1630 DP(BNX2X_MSG_SP, "got MULTI[%d] halt ramrod\n", cid);
1631 drv_cmd = BNX2X_Q_CMD_HALT;
1632 break;
1633
1634 case (RAMROD_CMD_ID_ETH_TERMINATE):
1635 DP(BNX2X_MSG_SP, "got MULTI[%d] teminate ramrod\n", cid);
1636 drv_cmd = BNX2X_Q_CMD_TERMINATE;
1637 break;
1638
1639 case (RAMROD_CMD_ID_ETH_EMPTY):
1640 DP(BNX2X_MSG_SP, "got MULTI[%d] empty ramrod\n", cid);
1641 drv_cmd = BNX2X_Q_CMD_EMPTY;
1642 break;
1643
1644 default:
1645 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1646 command, fp->index);
1647 return;
1648 }
1649
1650 if ((drv_cmd != BNX2X_Q_CMD_MAX) &&
1651 q_obj->complete_cmd(bp, q_obj, drv_cmd))
1652 /* q_obj->complete_cmd() failure means that this was
1653 * an unexpected completion.
1654 *
1655 * In this case we don't want to increase the bp->spq_left
1656 * because apparently we haven't sent this command the first
1657 * place.
1658 */
1659 #ifdef BNX2X_STOP_ON_ERROR
1660 bnx2x_panic();
1661 #else
1662 return;
1663 #endif
1664
1665 smp_mb__before_atomic_inc();
1666 atomic_inc(&bp->cq_spq_left);
1667 /* push the change in bp->spq_left and towards the memory */
1668 smp_mb__after_atomic_inc();
1669
1670 DP(BNX2X_MSG_SP, "bp->cq_spq_left %x\n", atomic_read(&bp->cq_spq_left));
1671
1672 if ((drv_cmd == BNX2X_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) &&
1673 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state))) {
1674 /* if Q update ramrod is completed for last Q in AFEX vif set
1675 * flow, then ACK MCP at the end
1676 *
1677 * mark pending ACK to MCP bit.
1678 * prevent case that both bits are cleared.
1679 * At the end of load/unload driver checks that
1680 * sp_state is cleaerd, and this order prevents
1681 * races
1682 */
1683 smp_mb__before_clear_bit();
1684 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK, &bp->sp_state);
1685 wmb();
1686 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
1687 smp_mb__after_clear_bit();
1688
1689 /* schedule workqueue to send ack to MCP */
1690 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1691 }
1692
1693 return;
1694 }
1695
1696 void bnx2x_update_rx_prod(struct bnx2x *bp, struct bnx2x_fastpath *fp,
1697 u16 bd_prod, u16 rx_comp_prod, u16 rx_sge_prod)
1698 {
1699 u32 start = BAR_USTRORM_INTMEM + fp->ustorm_rx_prods_offset;
1700
1701 bnx2x_update_rx_prod_gen(bp, fp, bd_prod, rx_comp_prod, rx_sge_prod,
1702 start);
1703 }
1704
1705 irqreturn_t bnx2x_interrupt(int irq, void *dev_instance)
1706 {
1707 struct bnx2x *bp = netdev_priv(dev_instance);
1708 u16 status = bnx2x_ack_int(bp);
1709 u16 mask;
1710 int i;
1711 u8 cos;
1712
1713 /* Return here if interrupt is shared and it's not for us */
1714 if (unlikely(status == 0)) {
1715 DP(NETIF_MSG_INTR, "not our interrupt!\n");
1716 return IRQ_NONE;
1717 }
1718 DP(NETIF_MSG_INTR, "got an interrupt status 0x%x\n", status);
1719
1720 #ifdef BNX2X_STOP_ON_ERROR
1721 if (unlikely(bp->panic))
1722 return IRQ_HANDLED;
1723 #endif
1724
1725 for_each_eth_queue(bp, i) {
1726 struct bnx2x_fastpath *fp = &bp->fp[i];
1727
1728 mask = 0x2 << (fp->index + CNIC_PRESENT);
1729 if (status & mask) {
1730 /* Handle Rx or Tx according to SB id */
1731 prefetch(fp->rx_cons_sb);
1732 for_each_cos_in_tx_queue(fp, cos)
1733 prefetch(fp->txdata_ptr[cos]->tx_cons_sb);
1734 prefetch(&fp->sb_running_index[SM_RX_ID]);
1735 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
1736 status &= ~mask;
1737 }
1738 }
1739
1740 #ifdef BCM_CNIC
1741 mask = 0x2;
1742 if (status & (mask | 0x1)) {
1743 struct cnic_ops *c_ops = NULL;
1744
1745 if (likely(bp->state == BNX2X_STATE_OPEN)) {
1746 rcu_read_lock();
1747 c_ops = rcu_dereference(bp->cnic_ops);
1748 if (c_ops)
1749 c_ops->cnic_handler(bp->cnic_data, NULL);
1750 rcu_read_unlock();
1751 }
1752
1753 status &= ~mask;
1754 }
1755 #endif
1756
1757 if (unlikely(status & 0x1)) {
1758 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
1759
1760 status &= ~0x1;
1761 if (!status)
1762 return IRQ_HANDLED;
1763 }
1764
1765 if (unlikely(status))
1766 DP(NETIF_MSG_INTR, "got an unknown interrupt! (status 0x%x)\n",
1767 status);
1768
1769 return IRQ_HANDLED;
1770 }
1771
1772 /* Link */
1773
1774 /*
1775 * General service functions
1776 */
1777
1778 int bnx2x_acquire_hw_lock(struct bnx2x *bp, u32 resource)
1779 {
1780 u32 lock_status;
1781 u32 resource_bit = (1 << resource);
1782 int func = BP_FUNC(bp);
1783 u32 hw_lock_control_reg;
1784 int cnt;
1785
1786 /* Validating that the resource is within range */
1787 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1788 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1789 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1790 return -EINVAL;
1791 }
1792
1793 if (func <= 5) {
1794 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1795 } else {
1796 hw_lock_control_reg =
1797 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1798 }
1799
1800 /* Validating that the resource is not already taken */
1801 lock_status = REG_RD(bp, hw_lock_control_reg);
1802 if (lock_status & resource_bit) {
1803 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1804 lock_status, resource_bit);
1805 return -EEXIST;
1806 }
1807
1808 /* Try for 5 second every 5ms */
1809 for (cnt = 0; cnt < 1000; cnt++) {
1810 /* Try to acquire the lock */
1811 REG_WR(bp, hw_lock_control_reg + 4, resource_bit);
1812 lock_status = REG_RD(bp, hw_lock_control_reg);
1813 if (lock_status & resource_bit)
1814 return 0;
1815
1816 msleep(5);
1817 }
1818 BNX2X_ERR("Timeout\n");
1819 return -EAGAIN;
1820 }
1821
1822 int bnx2x_release_leader_lock(struct bnx2x *bp)
1823 {
1824 return bnx2x_release_hw_lock(bp, bnx2x_get_leader_lock_resource(bp));
1825 }
1826
1827 int bnx2x_release_hw_lock(struct bnx2x *bp, u32 resource)
1828 {
1829 u32 lock_status;
1830 u32 resource_bit = (1 << resource);
1831 int func = BP_FUNC(bp);
1832 u32 hw_lock_control_reg;
1833
1834 /* Validating that the resource is within range */
1835 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) {
1836 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1837 resource, HW_LOCK_MAX_RESOURCE_VALUE);
1838 return -EINVAL;
1839 }
1840
1841 if (func <= 5) {
1842 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8);
1843 } else {
1844 hw_lock_control_reg =
1845 (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8);
1846 }
1847
1848 /* Validating that the resource is currently taken */
1849 lock_status = REG_RD(bp, hw_lock_control_reg);
1850 if (!(lock_status & resource_bit)) {
1851 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1852 lock_status, resource_bit);
1853 return -EFAULT;
1854 }
1855
1856 REG_WR(bp, hw_lock_control_reg, resource_bit);
1857 return 0;
1858 }
1859
1860
1861 int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
1862 {
1863 /* The GPIO should be swapped if swap register is set and active */
1864 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1865 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1866 int gpio_shift = gpio_num +
1867 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1868 u32 gpio_mask = (1 << gpio_shift);
1869 u32 gpio_reg;
1870 int value;
1871
1872 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1873 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1874 return -EINVAL;
1875 }
1876
1877 /* read GPIO value */
1878 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1879
1880 /* get the requested pin value */
1881 if ((gpio_reg & gpio_mask) == gpio_mask)
1882 value = 1;
1883 else
1884 value = 0;
1885
1886 DP(NETIF_MSG_LINK, "pin %d value 0x%x\n", gpio_num, value);
1887
1888 return value;
1889 }
1890
1891 int bnx2x_set_gpio(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1892 {
1893 /* The GPIO should be swapped if swap register is set and active */
1894 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1895 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1896 int gpio_shift = gpio_num +
1897 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
1898 u32 gpio_mask = (1 << gpio_shift);
1899 u32 gpio_reg;
1900
1901 if (gpio_num > MISC_REGISTERS_GPIO_3) {
1902 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
1903 return -EINVAL;
1904 }
1905
1906 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1907 /* read GPIO and mask except the float bits */
1908 gpio_reg = (REG_RD(bp, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT);
1909
1910 switch (mode) {
1911 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1912 DP(NETIF_MSG_LINK,
1913 "Set GPIO %d (shift %d) -> output low\n",
1914 gpio_num, gpio_shift);
1915 /* clear FLOAT and set CLR */
1916 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1917 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS);
1918 break;
1919
1920 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1921 DP(NETIF_MSG_LINK,
1922 "Set GPIO %d (shift %d) -> output high\n",
1923 gpio_num, gpio_shift);
1924 /* clear FLOAT and set SET */
1925 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1926 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS);
1927 break;
1928
1929 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1930 DP(NETIF_MSG_LINK,
1931 "Set GPIO %d (shift %d) -> input\n",
1932 gpio_num, gpio_shift);
1933 /* set FLOAT */
1934 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS);
1935 break;
1936
1937 default:
1938 break;
1939 }
1940
1941 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1942 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1943
1944 return 0;
1945 }
1946
1947 int bnx2x_set_mult_gpio(struct bnx2x *bp, u8 pins, u32 mode)
1948 {
1949 u32 gpio_reg = 0;
1950 int rc = 0;
1951
1952 /* Any port swapping should be handled by caller. */
1953
1954 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1955 /* read GPIO and mask except the float bits */
1956 gpio_reg = REG_RD(bp, MISC_REG_GPIO);
1957 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1958 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS);
1959 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS);
1960
1961 switch (mode) {
1962 case MISC_REGISTERS_GPIO_OUTPUT_LOW:
1963 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output low\n", pins);
1964 /* set CLR */
1965 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS);
1966 break;
1967
1968 case MISC_REGISTERS_GPIO_OUTPUT_HIGH:
1969 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> output high\n", pins);
1970 /* set SET */
1971 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS);
1972 break;
1973
1974 case MISC_REGISTERS_GPIO_INPUT_HI_Z:
1975 DP(NETIF_MSG_LINK, "Set GPIO 0x%x -> input\n", pins);
1976 /* set FLOAT */
1977 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS);
1978 break;
1979
1980 default:
1981 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode);
1982 rc = -EINVAL;
1983 break;
1984 }
1985
1986 if (rc == 0)
1987 REG_WR(bp, MISC_REG_GPIO, gpio_reg);
1988
1989 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
1990
1991 return rc;
1992 }
1993
1994 int bnx2x_set_gpio_int(struct bnx2x *bp, int gpio_num, u32 mode, u8 port)
1995 {
1996 /* The GPIO should be swapped if swap register is set and active */
1997 int gpio_port = (REG_RD(bp, NIG_REG_PORT_SWAP) &&
1998 REG_RD(bp, NIG_REG_STRAP_OVERRIDE)) ^ port;
1999 int gpio_shift = gpio_num +
2000 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0);
2001 u32 gpio_mask = (1 << gpio_shift);
2002 u32 gpio_reg;
2003
2004 if (gpio_num > MISC_REGISTERS_GPIO_3) {
2005 BNX2X_ERR("Invalid GPIO %d\n", gpio_num);
2006 return -EINVAL;
2007 }
2008
2009 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2010 /* read GPIO int */
2011 gpio_reg = REG_RD(bp, MISC_REG_GPIO_INT);
2012
2013 switch (mode) {
2014 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR:
2015 DP(NETIF_MSG_LINK,
2016 "Clear GPIO INT %d (shift %d) -> output low\n",
2017 gpio_num, gpio_shift);
2018 /* clear SET and set CLR */
2019 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2020 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2021 break;
2022
2023 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET:
2024 DP(NETIF_MSG_LINK,
2025 "Set GPIO INT %d (shift %d) -> output high\n",
2026 gpio_num, gpio_shift);
2027 /* clear CLR and set SET */
2028 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS);
2029 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS);
2030 break;
2031
2032 default:
2033 break;
2034 }
2035
2036 REG_WR(bp, MISC_REG_GPIO_INT, gpio_reg);
2037 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_GPIO);
2038
2039 return 0;
2040 }
2041
2042 static int bnx2x_set_spio(struct bnx2x *bp, int spio_num, u32 mode)
2043 {
2044 u32 spio_mask = (1 << spio_num);
2045 u32 spio_reg;
2046
2047 if ((spio_num < MISC_REGISTERS_SPIO_4) ||
2048 (spio_num > MISC_REGISTERS_SPIO_7)) {
2049 BNX2X_ERR("Invalid SPIO %d\n", spio_num);
2050 return -EINVAL;
2051 }
2052
2053 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2054 /* read SPIO and mask except the float bits */
2055 spio_reg = (REG_RD(bp, MISC_REG_SPIO) & MISC_REGISTERS_SPIO_FLOAT);
2056
2057 switch (mode) {
2058 case MISC_REGISTERS_SPIO_OUTPUT_LOW:
2059 DP(NETIF_MSG_HW, "Set SPIO %d -> output low\n", spio_num);
2060 /* clear FLOAT and set CLR */
2061 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2062 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_CLR_POS);
2063 break;
2064
2065 case MISC_REGISTERS_SPIO_OUTPUT_HIGH:
2066 DP(NETIF_MSG_HW, "Set SPIO %d -> output high\n", spio_num);
2067 /* clear FLOAT and set SET */
2068 spio_reg &= ~(spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2069 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_SET_POS);
2070 break;
2071
2072 case MISC_REGISTERS_SPIO_INPUT_HI_Z:
2073 DP(NETIF_MSG_HW, "Set SPIO %d -> input\n", spio_num);
2074 /* set FLOAT */
2075 spio_reg |= (spio_mask << MISC_REGISTERS_SPIO_FLOAT_POS);
2076 break;
2077
2078 default:
2079 break;
2080 }
2081
2082 REG_WR(bp, MISC_REG_SPIO, spio_reg);
2083 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_SPIO);
2084
2085 return 0;
2086 }
2087
2088 void bnx2x_calc_fc_adv(struct bnx2x *bp)
2089 {
2090 u8 cfg_idx = bnx2x_get_link_cfg_idx(bp);
2091 switch (bp->link_vars.ieee_fc &
2092 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) {
2093 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE:
2094 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2095 ADVERTISED_Pause);
2096 break;
2097
2098 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH:
2099 bp->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause |
2100 ADVERTISED_Pause);
2101 break;
2102
2103 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC:
2104 bp->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause;
2105 break;
2106
2107 default:
2108 bp->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause |
2109 ADVERTISED_Pause);
2110 break;
2111 }
2112 }
2113
2114 u8 bnx2x_initial_phy_init(struct bnx2x *bp, int load_mode)
2115 {
2116 if (!BP_NOMCP(bp)) {
2117 u8 rc;
2118 int cfx_idx = bnx2x_get_link_cfg_idx(bp);
2119 u16 req_line_speed = bp->link_params.req_line_speed[cfx_idx];
2120 /*
2121 * Initialize link parameters structure variables
2122 * It is recommended to turn off RX FC for jumbo frames
2123 * for better performance
2124 */
2125 if (CHIP_IS_E1x(bp) && (bp->dev->mtu > 5000))
2126 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_TX;
2127 else
2128 bp->link_params.req_fc_auto_adv = BNX2X_FLOW_CTRL_BOTH;
2129
2130 bnx2x_acquire_phy_lock(bp);
2131
2132 if (load_mode == LOAD_DIAG) {
2133 struct link_params *lp = &bp->link_params;
2134 lp->loopback_mode = LOOPBACK_XGXS;
2135 /* do PHY loopback at 10G speed, if possible */
2136 if (lp->req_line_speed[cfx_idx] < SPEED_10000) {
2137 if (lp->speed_cap_mask[cfx_idx] &
2138 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
2139 lp->req_line_speed[cfx_idx] =
2140 SPEED_10000;
2141 else
2142 lp->req_line_speed[cfx_idx] =
2143 SPEED_1000;
2144 }
2145 }
2146
2147 if (load_mode == LOAD_LOOPBACK_EXT) {
2148 struct link_params *lp = &bp->link_params;
2149 lp->loopback_mode = LOOPBACK_EXT;
2150 }
2151
2152 rc = bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2153
2154 bnx2x_release_phy_lock(bp);
2155
2156 bnx2x_calc_fc_adv(bp);
2157
2158 if (CHIP_REV_IS_SLOW(bp) && bp->link_vars.link_up) {
2159 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2160 bnx2x_link_report(bp);
2161 } else
2162 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2163 bp->link_params.req_line_speed[cfx_idx] = req_line_speed;
2164 return rc;
2165 }
2166 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2167 return -EINVAL;
2168 }
2169
2170 void bnx2x_link_set(struct bnx2x *bp)
2171 {
2172 if (!BP_NOMCP(bp)) {
2173 bnx2x_acquire_phy_lock(bp);
2174 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2175 bnx2x_phy_init(&bp->link_params, &bp->link_vars);
2176 bnx2x_release_phy_lock(bp);
2177
2178 bnx2x_calc_fc_adv(bp);
2179 } else
2180 BNX2X_ERR("Bootcode is missing - can not set link\n");
2181 }
2182
2183 static void bnx2x__link_reset(struct bnx2x *bp)
2184 {
2185 if (!BP_NOMCP(bp)) {
2186 bnx2x_acquire_phy_lock(bp);
2187 bnx2x_link_reset(&bp->link_params, &bp->link_vars, 1);
2188 bnx2x_release_phy_lock(bp);
2189 } else
2190 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2191 }
2192
2193 u8 bnx2x_link_test(struct bnx2x *bp, u8 is_serdes)
2194 {
2195 u8 rc = 0;
2196
2197 if (!BP_NOMCP(bp)) {
2198 bnx2x_acquire_phy_lock(bp);
2199 rc = bnx2x_test_link(&bp->link_params, &bp->link_vars,
2200 is_serdes);
2201 bnx2x_release_phy_lock(bp);
2202 } else
2203 BNX2X_ERR("Bootcode is missing - can not test link\n");
2204
2205 return rc;
2206 }
2207
2208
2209 /* Calculates the sum of vn_min_rates.
2210 It's needed for further normalizing of the min_rates.
2211 Returns:
2212 sum of vn_min_rates.
2213 or
2214 0 - if all the min_rates are 0.
2215 In the later case fainess algorithm should be deactivated.
2216 If not all min_rates are zero then those that are zeroes will be set to 1.
2217 */
2218 static void bnx2x_calc_vn_min(struct bnx2x *bp,
2219 struct cmng_init_input *input)
2220 {
2221 int all_zero = 1;
2222 int vn;
2223
2224 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2225 u32 vn_cfg = bp->mf_config[vn];
2226 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2227 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
2228
2229 /* Skip hidden vns */
2230 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2231 vn_min_rate = 0;
2232 /* If min rate is zero - set it to 1 */
2233 else if (!vn_min_rate)
2234 vn_min_rate = DEF_MIN_RATE;
2235 else
2236 all_zero = 0;
2237
2238 input->vnic_min_rate[vn] = vn_min_rate;
2239 }
2240
2241 /* if ETS or all min rates are zeros - disable fairness */
2242 if (BNX2X_IS_ETS_ENABLED(bp)) {
2243 input->flags.cmng_enables &=
2244 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2245 DP(NETIF_MSG_IFUP, "Fairness will be disabled due to ETS\n");
2246 } else if (all_zero) {
2247 input->flags.cmng_enables &=
2248 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2249 DP(NETIF_MSG_IFUP,
2250 "All MIN values are zeroes fairness will be disabled\n");
2251 } else
2252 input->flags.cmng_enables |=
2253 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2254 }
2255
2256 static void bnx2x_calc_vn_max(struct bnx2x *bp, int vn,
2257 struct cmng_init_input *input)
2258 {
2259 u16 vn_max_rate;
2260 u32 vn_cfg = bp->mf_config[vn];
2261
2262 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE)
2263 vn_max_rate = 0;
2264 else {
2265 u32 maxCfg = bnx2x_extract_max_cfg(bp, vn_cfg);
2266
2267 if (IS_MF_SI(bp)) {
2268 /* maxCfg in percents of linkspeed */
2269 vn_max_rate = (bp->link_vars.line_speed * maxCfg) / 100;
2270 } else /* SD modes */
2271 /* maxCfg is absolute in 100Mb units */
2272 vn_max_rate = maxCfg * 100;
2273 }
2274
2275 DP(NETIF_MSG_IFUP, "vn %d: vn_max_rate %d\n", vn, vn_max_rate);
2276
2277 input->vnic_max_rate[vn] = vn_max_rate;
2278 }
2279
2280
2281 static int bnx2x_get_cmng_fns_mode(struct bnx2x *bp)
2282 {
2283 if (CHIP_REV_IS_SLOW(bp))
2284 return CMNG_FNS_NONE;
2285 if (IS_MF(bp))
2286 return CMNG_FNS_MINMAX;
2287
2288 return CMNG_FNS_NONE;
2289 }
2290
2291 void bnx2x_read_mf_cfg(struct bnx2x *bp)
2292 {
2293 int vn, n = (CHIP_MODE_IS_4_PORT(bp) ? 2 : 1);
2294
2295 if (BP_NOMCP(bp))
2296 return; /* what should be the default bvalue in this case */
2297
2298 /* For 2 port configuration the absolute function number formula
2299 * is:
2300 * abs_func = 2 * vn + BP_PORT + BP_PATH
2301 *
2302 * and there are 4 functions per port
2303 *
2304 * For 4 port configuration it is
2305 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2306 *
2307 * and there are 2 functions per port
2308 */
2309 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2310 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2311
2312 if (func >= E1H_FUNC_MAX)
2313 break;
2314
2315 bp->mf_config[vn] =
2316 MF_CFG_RD(bp, func_mf_config[func].config);
2317 }
2318 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
2319 DP(NETIF_MSG_IFUP, "mf_cfg function disabled\n");
2320 bp->flags |= MF_FUNC_DIS;
2321 } else {
2322 DP(NETIF_MSG_IFUP, "mf_cfg function enabled\n");
2323 bp->flags &= ~MF_FUNC_DIS;
2324 }
2325 }
2326
2327 static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2328 {
2329 struct cmng_init_input input;
2330 memset(&input, 0, sizeof(struct cmng_init_input));
2331
2332 input.port_rate = bp->link_vars.line_speed;
2333
2334 if (cmng_type == CMNG_FNS_MINMAX) {
2335 int vn;
2336
2337 /* read mf conf from shmem */
2338 if (read_cfg)
2339 bnx2x_read_mf_cfg(bp);
2340
2341 /* vn_weight_sum and enable fairness if not 0 */
2342 bnx2x_calc_vn_min(bp, &input);
2343
2344 /* calculate and set min-max rate for each vn */
2345 if (bp->port.pmf)
2346 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2347 bnx2x_calc_vn_max(bp, vn, &input);
2348
2349 /* always enable rate shaping and fairness */
2350 input.flags.cmng_enables |=
2351 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN;
2352
2353 bnx2x_init_cmng(&input, &bp->cmng);
2354 return;
2355 }
2356
2357 /* rate shaping and fairness are disabled */
2358 DP(NETIF_MSG_IFUP,
2359 "rate shaping and fairness are disabled\n");
2360 }
2361
2362 static void storm_memset_cmng(struct bnx2x *bp,
2363 struct cmng_init *cmng,
2364 u8 port)
2365 {
2366 int vn;
2367 size_t size = sizeof(struct cmng_struct_per_port);
2368
2369 u32 addr = BAR_XSTRORM_INTMEM +
2370 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port);
2371
2372 __storm_memset_struct(bp, addr, size, (u32 *)&cmng->port);
2373
2374 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2375 int func = func_by_vn(bp, vn);
2376
2377 addr = BAR_XSTRORM_INTMEM +
2378 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func);
2379 size = sizeof(struct rate_shaping_vars_per_vn);
2380 __storm_memset_struct(bp, addr, size,
2381 (u32 *)&cmng->vnic.vnic_max_rate[vn]);
2382
2383 addr = BAR_XSTRORM_INTMEM +
2384 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func);
2385 size = sizeof(struct fairness_vars_per_vn);
2386 __storm_memset_struct(bp, addr, size,
2387 (u32 *)&cmng->vnic.vnic_min_rate[vn]);
2388 }
2389 }
2390
2391 /* This function is called upon link interrupt */
2392 static void bnx2x_link_attn(struct bnx2x *bp)
2393 {
2394 /* Make sure that we are synced with the current statistics */
2395 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2396
2397 bnx2x_link_update(&bp->link_params, &bp->link_vars);
2398
2399 if (bp->link_vars.link_up) {
2400
2401 /* dropless flow control */
2402 if (!CHIP_IS_E1(bp) && bp->dropless_fc) {
2403 int port = BP_PORT(bp);
2404 u32 pause_enabled = 0;
2405
2406 if (bp->link_vars.flow_ctrl & BNX2X_FLOW_CTRL_TX)
2407 pause_enabled = 1;
2408
2409 REG_WR(bp, BAR_USTRORM_INTMEM +
2410 USTORM_ETH_PAUSE_ENABLED_OFFSET(port),
2411 pause_enabled);
2412 }
2413
2414 if (bp->link_vars.mac_type != MAC_TYPE_EMAC) {
2415 struct host_port_stats *pstats;
2416
2417 pstats = bnx2x_sp(bp, port_stats);
2418 /* reset old mac stats */
2419 memset(&(pstats->mac_stx[0]), 0,
2420 sizeof(struct mac_stx));
2421 }
2422 if (bp->state == BNX2X_STATE_OPEN)
2423 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2424 }
2425
2426 if (bp->link_vars.link_up && bp->link_vars.line_speed) {
2427 int cmng_fns = bnx2x_get_cmng_fns_mode(bp);
2428
2429 if (cmng_fns != CMNG_FNS_NONE) {
2430 bnx2x_cmng_fns_init(bp, false, cmng_fns);
2431 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
2432 } else
2433 /* rate shaping and fairness are disabled */
2434 DP(NETIF_MSG_IFUP,
2435 "single function mode without fairness\n");
2436 }
2437
2438 __bnx2x_link_report(bp);
2439
2440 if (IS_MF(bp))
2441 bnx2x_link_sync_notify(bp);
2442 }
2443
2444 void bnx2x__link_status_update(struct bnx2x *bp)
2445 {
2446 if (bp->state != BNX2X_STATE_OPEN)
2447 return;
2448
2449 /* read updated dcb configuration */
2450 bnx2x_dcbx_pmf_update(bp);
2451
2452 bnx2x_link_status_update(&bp->link_params, &bp->link_vars);
2453
2454 if (bp->link_vars.link_up)
2455 bnx2x_stats_handle(bp, STATS_EVENT_LINK_UP);
2456 else
2457 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
2458
2459 /* indicate link status */
2460 bnx2x_link_report(bp);
2461 }
2462
2463 static int bnx2x_afex_func_update(struct bnx2x *bp, u16 vifid,
2464 u16 vlan_val, u8 allowed_prio)
2465 {
2466 struct bnx2x_func_state_params func_params = {0};
2467 struct bnx2x_func_afex_update_params *f_update_params =
2468 &func_params.params.afex_update;
2469
2470 func_params.f_obj = &bp->func_obj;
2471 func_params.cmd = BNX2X_F_CMD_AFEX_UPDATE;
2472
2473 /* no need to wait for RAMROD completion, so don't
2474 * set RAMROD_COMP_WAIT flag
2475 */
2476
2477 f_update_params->vif_id = vifid;
2478 f_update_params->afex_default_vlan = vlan_val;
2479 f_update_params->allowed_priorities = allowed_prio;
2480
2481 /* if ramrod can not be sent, response to MCP immediately */
2482 if (bnx2x_func_state_change(bp, &func_params) < 0)
2483 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
2484
2485 return 0;
2486 }
2487
2488 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x *bp, u8 cmd_type,
2489 u16 vif_index, u8 func_bit_map)
2490 {
2491 struct bnx2x_func_state_params func_params = {0};
2492 struct bnx2x_func_afex_viflists_params *update_params =
2493 &func_params.params.afex_viflists;
2494 int rc;
2495 u32 drv_msg_code;
2496
2497 /* validate only LIST_SET and LIST_GET are received from switch */
2498 if ((cmd_type != VIF_LIST_RULE_GET) && (cmd_type != VIF_LIST_RULE_SET))
2499 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2500 cmd_type);
2501
2502 func_params.f_obj = &bp->func_obj;
2503 func_params.cmd = BNX2X_F_CMD_AFEX_VIFLISTS;
2504
2505 /* set parameters according to cmd_type */
2506 update_params->afex_vif_list_command = cmd_type;
2507 update_params->vif_list_index = cpu_to_le16(vif_index);
2508 update_params->func_bit_map =
2509 (cmd_type == VIF_LIST_RULE_GET) ? 0 : func_bit_map;
2510 update_params->func_to_clear = 0;
2511 drv_msg_code =
2512 (cmd_type == VIF_LIST_RULE_GET) ?
2513 DRV_MSG_CODE_AFEX_LISTGET_ACK :
2514 DRV_MSG_CODE_AFEX_LISTSET_ACK;
2515
2516 /* if ramrod can not be sent, respond to MCP immediately for
2517 * SET and GET requests (other are not triggered from MCP)
2518 */
2519 rc = bnx2x_func_state_change(bp, &func_params);
2520 if (rc < 0)
2521 bnx2x_fw_command(bp, drv_msg_code, 0);
2522
2523 return 0;
2524 }
2525
2526 static void bnx2x_handle_afex_cmd(struct bnx2x *bp, u32 cmd)
2527 {
2528 struct afex_stats afex_stats;
2529 u32 func = BP_ABS_FUNC(bp);
2530 u32 mf_config;
2531 u16 vlan_val;
2532 u32 vlan_prio;
2533 u16 vif_id;
2534 u8 allowed_prio;
2535 u8 vlan_mode;
2536 u32 addr_to_write, vifid, addrs, stats_type, i;
2537
2538 if (cmd & DRV_STATUS_AFEX_LISTGET_REQ) {
2539 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2540 DP(BNX2X_MSG_MCP,
2541 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid);
2542 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_GET, vifid, 0);
2543 }
2544
2545 if (cmd & DRV_STATUS_AFEX_LISTSET_REQ) {
2546 vifid = SHMEM2_RD(bp, afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2547 addrs = SHMEM2_RD(bp, afex_param2_to_driver[BP_FW_MB_IDX(bp)]);
2548 DP(BNX2X_MSG_MCP,
2549 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2550 vifid, addrs);
2551 bnx2x_afex_handle_vif_list_cmd(bp, VIF_LIST_RULE_SET, vifid,
2552 addrs);
2553 }
2554
2555 if (cmd & DRV_STATUS_AFEX_STATSGET_REQ) {
2556 addr_to_write = SHMEM2_RD(bp,
2557 afex_scratchpad_addr_to_write[BP_FW_MB_IDX(bp)]);
2558 stats_type = SHMEM2_RD(bp,
2559 afex_param1_to_driver[BP_FW_MB_IDX(bp)]);
2560
2561 DP(BNX2X_MSG_MCP,
2562 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2563 addr_to_write);
2564
2565 bnx2x_afex_collect_stats(bp, (void *)&afex_stats, stats_type);
2566
2567 /* write response to scratchpad, for MCP */
2568 for (i = 0; i < (sizeof(struct afex_stats)/sizeof(u32)); i++)
2569 REG_WR(bp, addr_to_write + i*sizeof(u32),
2570 *(((u32 *)(&afex_stats))+i));
2571
2572 /* send ack message to MCP */
2573 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_STATSGET_ACK, 0);
2574 }
2575
2576 if (cmd & DRV_STATUS_AFEX_VIFSET_REQ) {
2577 mf_config = MF_CFG_RD(bp, func_mf_config[func].config);
2578 bp->mf_config[BP_VN(bp)] = mf_config;
2579 DP(BNX2X_MSG_MCP,
2580 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2581 mf_config);
2582
2583 /* if VIF_SET is "enabled" */
2584 if (!(mf_config & FUNC_MF_CFG_FUNC_DISABLED)) {
2585 /* set rate limit directly to internal RAM */
2586 struct cmng_init_input cmng_input;
2587 struct rate_shaping_vars_per_vn m_rs_vn;
2588 size_t size = sizeof(struct rate_shaping_vars_per_vn);
2589 u32 addr = BAR_XSTRORM_INTMEM +
2590 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp));
2591
2592 bp->mf_config[BP_VN(bp)] = mf_config;
2593
2594 bnx2x_calc_vn_max(bp, BP_VN(bp), &cmng_input);
2595 m_rs_vn.vn_counter.rate =
2596 cmng_input.vnic_max_rate[BP_VN(bp)];
2597 m_rs_vn.vn_counter.quota =
2598 (m_rs_vn.vn_counter.rate *
2599 RS_PERIODIC_TIMEOUT_USEC) / 8;
2600
2601 __storm_memset_struct(bp, addr, size, (u32 *)&m_rs_vn);
2602
2603 /* read relevant values from mf_cfg struct in shmem */
2604 vif_id =
2605 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2606 FUNC_MF_CFG_E1HOV_TAG_MASK) >>
2607 FUNC_MF_CFG_E1HOV_TAG_SHIFT;
2608 vlan_val =
2609 (MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
2610 FUNC_MF_CFG_AFEX_VLAN_MASK) >>
2611 FUNC_MF_CFG_AFEX_VLAN_SHIFT;
2612 vlan_prio = (mf_config &
2613 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >>
2614 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT;
2615 vlan_val |= (vlan_prio << VLAN_PRIO_SHIFT);
2616 vlan_mode =
2617 (MF_CFG_RD(bp,
2618 func_mf_config[func].afex_config) &
2619 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >>
2620 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT;
2621 allowed_prio =
2622 (MF_CFG_RD(bp,
2623 func_mf_config[func].afex_config) &
2624 FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >>
2625 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT;
2626
2627 /* send ramrod to FW, return in case of failure */
2628 if (bnx2x_afex_func_update(bp, vif_id, vlan_val,
2629 allowed_prio))
2630 return;
2631
2632 bp->afex_def_vlan_tag = vlan_val;
2633 bp->afex_vlan_mode = vlan_mode;
2634 } else {
2635 /* notify link down because BP->flags is disabled */
2636 bnx2x_link_report(bp);
2637
2638 /* send INVALID VIF ramrod to FW */
2639 bnx2x_afex_func_update(bp, 0xFFFF, 0, 0);
2640
2641 /* Reset the default afex VLAN */
2642 bp->afex_def_vlan_tag = -1;
2643 }
2644 }
2645 }
2646
2647 static void bnx2x_pmf_update(struct bnx2x *bp)
2648 {
2649 int port = BP_PORT(bp);
2650 u32 val;
2651
2652 bp->port.pmf = 1;
2653 DP(BNX2X_MSG_MCP, "pmf %d\n", bp->port.pmf);
2654
2655 /*
2656 * We need the mb() to ensure the ordering between the writing to
2657 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2658 */
2659 smp_mb();
2660
2661 /* queue a periodic task */
2662 queue_delayed_work(bnx2x_wq, &bp->period_task, 0);
2663
2664 bnx2x_dcbx_pmf_update(bp);
2665
2666 /* enable nig attention */
2667 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2668 if (bp->common.int_block == INT_BLOCK_HC) {
2669 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2670 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
2671 } else if (!CHIP_IS_E1x(bp)) {
2672 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, val);
2673 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, val);
2674 }
2675
2676 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
2677 }
2678
2679 /* end of Link */
2680
2681 /* slow path */
2682
2683 /*
2684 * General service functions
2685 */
2686
2687 /* send the MCP a request, block until there is a reply */
2688 u32 bnx2x_fw_command(struct bnx2x *bp, u32 command, u32 param)
2689 {
2690 int mb_idx = BP_FW_MB_IDX(bp);
2691 u32 seq;
2692 u32 rc = 0;
2693 u32 cnt = 1;
2694 u8 delay = CHIP_REV_IS_SLOW(bp) ? 100 : 10;
2695
2696 mutex_lock(&bp->fw_mb_mutex);
2697 seq = ++bp->fw_seq;
2698 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_param, param);
2699 SHMEM_WR(bp, func_mb[mb_idx].drv_mb_header, (command | seq));
2700
2701 DP(BNX2X_MSG_MCP, "wrote command (%x) to FW MB param 0x%08x\n",
2702 (command | seq), param);
2703
2704 do {
2705 /* let the FW do it's magic ... */
2706 msleep(delay);
2707
2708 rc = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_header);
2709
2710 /* Give the FW up to 5 second (500*10ms) */
2711 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500));
2712
2713 DP(BNX2X_MSG_MCP, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2714 cnt*delay, rc, seq);
2715
2716 /* is this a reply to our command? */
2717 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK))
2718 rc &= FW_MSG_CODE_MASK;
2719 else {
2720 /* FW BUG! */
2721 BNX2X_ERR("FW failed to respond!\n");
2722 bnx2x_fw_dump(bp);
2723 rc = 0;
2724 }
2725 mutex_unlock(&bp->fw_mb_mutex);
2726
2727 return rc;
2728 }
2729
2730
2731 static void storm_memset_func_cfg(struct bnx2x *bp,
2732 struct tstorm_eth_function_common_config *tcfg,
2733 u16 abs_fid)
2734 {
2735 size_t size = sizeof(struct tstorm_eth_function_common_config);
2736
2737 u32 addr = BAR_TSTRORM_INTMEM +
2738 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid);
2739
2740 __storm_memset_struct(bp, addr, size, (u32 *)tcfg);
2741 }
2742
2743 void bnx2x_func_init(struct bnx2x *bp, struct bnx2x_func_init_params *p)
2744 {
2745 if (CHIP_IS_E1x(bp)) {
2746 struct tstorm_eth_function_common_config tcfg = {0};
2747
2748 storm_memset_func_cfg(bp, &tcfg, p->func_id);
2749 }
2750
2751 /* Enable the function in the FW */
2752 storm_memset_vf_to_pf(bp, p->func_id, p->pf_id);
2753 storm_memset_func_en(bp, p->func_id, 1);
2754
2755 /* spq */
2756 if (p->func_flgs & FUNC_FLG_SPQ) {
2757 storm_memset_spq_addr(bp, p->spq_map, p->func_id);
2758 REG_WR(bp, XSEM_REG_FAST_MEMORY +
2759 XSTORM_SPQ_PROD_OFFSET(p->func_id), p->spq_prod);
2760 }
2761 }
2762
2763 /**
2764 * bnx2x_get_tx_only_flags - Return common flags
2765 *
2766 * @bp device handle
2767 * @fp queue handle
2768 * @zero_stats TRUE if statistics zeroing is needed
2769 *
2770 * Return the flags that are common for the Tx-only and not normal connections.
2771 */
2772 static unsigned long bnx2x_get_common_flags(struct bnx2x *bp,
2773 struct bnx2x_fastpath *fp,
2774 bool zero_stats)
2775 {
2776 unsigned long flags = 0;
2777
2778 /* PF driver will always initialize the Queue to an ACTIVE state */
2779 __set_bit(BNX2X_Q_FLG_ACTIVE, &flags);
2780
2781 /* tx only connections collect statistics (on the same index as the
2782 * parent connection). The statistics are zeroed when the parent
2783 * connection is initialized.
2784 */
2785
2786 __set_bit(BNX2X_Q_FLG_STATS, &flags);
2787 if (zero_stats)
2788 __set_bit(BNX2X_Q_FLG_ZERO_STATS, &flags);
2789
2790
2791 return flags;
2792 }
2793
2794 static unsigned long bnx2x_get_q_flags(struct bnx2x *bp,
2795 struct bnx2x_fastpath *fp,
2796 bool leading)
2797 {
2798 unsigned long flags = 0;
2799
2800 /* calculate other queue flags */
2801 if (IS_MF_SD(bp))
2802 __set_bit(BNX2X_Q_FLG_OV, &flags);
2803
2804 if (IS_FCOE_FP(fp)) {
2805 __set_bit(BNX2X_Q_FLG_FCOE, &flags);
2806 /* For FCoE - force usage of default priority (for afex) */
2807 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, &flags);
2808 }
2809
2810 if (!fp->disable_tpa) {
2811 __set_bit(BNX2X_Q_FLG_TPA, &flags);
2812 __set_bit(BNX2X_Q_FLG_TPA_IPV6, &flags);
2813 if (fp->mode == TPA_MODE_GRO)
2814 __set_bit(BNX2X_Q_FLG_TPA_GRO, &flags);
2815 }
2816
2817 if (leading) {
2818 __set_bit(BNX2X_Q_FLG_LEADING_RSS, &flags);
2819 __set_bit(BNX2X_Q_FLG_MCAST, &flags);
2820 }
2821
2822 /* Always set HW VLAN stripping */
2823 __set_bit(BNX2X_Q_FLG_VLAN, &flags);
2824
2825 /* configure silent vlan removal */
2826 if (IS_MF_AFEX(bp))
2827 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM, &flags);
2828
2829
2830 return flags | bnx2x_get_common_flags(bp, fp, true);
2831 }
2832
2833 static void bnx2x_pf_q_prep_general(struct bnx2x *bp,
2834 struct bnx2x_fastpath *fp, struct bnx2x_general_setup_params *gen_init,
2835 u8 cos)
2836 {
2837 gen_init->stat_id = bnx2x_stats_id(fp);
2838 gen_init->spcl_id = fp->cl_id;
2839
2840 /* Always use mini-jumbo MTU for FCoE L2 ring */
2841 if (IS_FCOE_FP(fp))
2842 gen_init->mtu = BNX2X_FCOE_MINI_JUMBO_MTU;
2843 else
2844 gen_init->mtu = bp->dev->mtu;
2845
2846 gen_init->cos = cos;
2847 }
2848
2849 static void bnx2x_pf_rx_q_prep(struct bnx2x *bp,
2850 struct bnx2x_fastpath *fp, struct rxq_pause_params *pause,
2851 struct bnx2x_rxq_setup_params *rxq_init)
2852 {
2853 u8 max_sge = 0;
2854 u16 sge_sz = 0;
2855 u16 tpa_agg_size = 0;
2856
2857 if (!fp->disable_tpa) {
2858 pause->sge_th_lo = SGE_TH_LO(bp);
2859 pause->sge_th_hi = SGE_TH_HI(bp);
2860
2861 /* validate SGE ring has enough to cross high threshold */
2862 WARN_ON(bp->dropless_fc &&
2863 pause->sge_th_hi + FW_PREFETCH_CNT >
2864 MAX_RX_SGE_CNT * NUM_RX_SGE_PAGES);
2865
2866 tpa_agg_size = min_t(u32,
2867 (min_t(u32, 8, MAX_SKB_FRAGS) *
2868 SGE_PAGE_SIZE * PAGES_PER_SGE), 0xffff);
2869 max_sge = SGE_PAGE_ALIGN(bp->dev->mtu) >>
2870 SGE_PAGE_SHIFT;
2871 max_sge = ((max_sge + PAGES_PER_SGE - 1) &
2872 (~(PAGES_PER_SGE-1))) >> PAGES_PER_SGE_SHIFT;
2873 sge_sz = (u16)min_t(u32, SGE_PAGE_SIZE * PAGES_PER_SGE,
2874 0xffff);
2875 }
2876
2877 /* pause - not for e1 */
2878 if (!CHIP_IS_E1(bp)) {
2879 pause->bd_th_lo = BD_TH_LO(bp);
2880 pause->bd_th_hi = BD_TH_HI(bp);
2881
2882 pause->rcq_th_lo = RCQ_TH_LO(bp);
2883 pause->rcq_th_hi = RCQ_TH_HI(bp);
2884 /*
2885 * validate that rings have enough entries to cross
2886 * high thresholds
2887 */
2888 WARN_ON(bp->dropless_fc &&
2889 pause->bd_th_hi + FW_PREFETCH_CNT >
2890 bp->rx_ring_size);
2891 WARN_ON(bp->dropless_fc &&
2892 pause->rcq_th_hi + FW_PREFETCH_CNT >
2893 NUM_RCQ_RINGS * MAX_RCQ_DESC_CNT);
2894
2895 pause->pri_map = 1;
2896 }
2897
2898 /* rxq setup */
2899 rxq_init->dscr_map = fp->rx_desc_mapping;
2900 rxq_init->sge_map = fp->rx_sge_mapping;
2901 rxq_init->rcq_map = fp->rx_comp_mapping;
2902 rxq_init->rcq_np_map = fp->rx_comp_mapping + BCM_PAGE_SIZE;
2903
2904 /* This should be a maximum number of data bytes that may be
2905 * placed on the BD (not including paddings).
2906 */
2907 rxq_init->buf_sz = fp->rx_buf_size - BNX2X_FW_RX_ALIGN_START -
2908 BNX2X_FW_RX_ALIGN_END - IP_HEADER_ALIGNMENT_PADDING;
2909
2910 rxq_init->cl_qzone_id = fp->cl_qzone_id;
2911 rxq_init->tpa_agg_sz = tpa_agg_size;
2912 rxq_init->sge_buf_sz = sge_sz;
2913 rxq_init->max_sges_pkt = max_sge;
2914 rxq_init->rss_engine_id = BP_FUNC(bp);
2915 rxq_init->mcast_engine_id = BP_FUNC(bp);
2916
2917 /* Maximum number or simultaneous TPA aggregation for this Queue.
2918 *
2919 * For PF Clients it should be the maximum avaliable number.
2920 * VF driver(s) may want to define it to a smaller value.
2921 */
2922 rxq_init->max_tpa_queues = MAX_AGG_QS(bp);
2923
2924 rxq_init->cache_line_log = BNX2X_RX_ALIGN_SHIFT;
2925 rxq_init->fw_sb_id = fp->fw_sb_id;
2926
2927 if (IS_FCOE_FP(fp))
2928 rxq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS;
2929 else
2930 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
2931 /* configure silent vlan removal
2932 * if multi function mode is afex, then mask default vlan
2933 */
2934 if (IS_MF_AFEX(bp)) {
2935 rxq_init->silent_removal_value = bp->afex_def_vlan_tag;
2936 rxq_init->silent_removal_mask = VLAN_VID_MASK;
2937 }
2938 }
2939
2940 static void bnx2x_pf_tx_q_prep(struct bnx2x *bp,
2941 struct bnx2x_fastpath *fp, struct bnx2x_txq_setup_params *txq_init,
2942 u8 cos)
2943 {
2944 txq_init->dscr_map = fp->txdata_ptr[cos]->tx_desc_mapping;
2945 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos;
2946 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW;
2947 txq_init->fw_sb_id = fp->fw_sb_id;
2948
2949 /*
2950 * set the tss leading client id for TX classfication ==
2951 * leading RSS client id
2952 */
2953 txq_init->tss_leading_cl_id = bnx2x_fp(bp, 0, cl_id);
2954
2955 if (IS_FCOE_FP(fp)) {
2956 txq_init->sb_cq_index = HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS;
2957 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_FCOE;
2958 }
2959 }
2960
2961 static void bnx2x_pf_init(struct bnx2x *bp)
2962 {
2963 struct bnx2x_func_init_params func_init = {0};
2964 struct event_ring_data eq_data = { {0} };
2965 u16 flags;
2966
2967 if (!CHIP_IS_E1x(bp)) {
2968 /* reset IGU PF statistics: MSIX + ATTN */
2969 /* PF */
2970 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2971 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2972 (CHIP_MODE_IS_4_PORT(bp) ?
2973 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2974 /* ATTN */
2975 REG_WR(bp, IGU_REG_STATISTIC_NUM_MESSAGE_SENT +
2976 BNX2X_IGU_STAS_MSG_VF_CNT*4 +
2977 BNX2X_IGU_STAS_MSG_PF_CNT*4 +
2978 (CHIP_MODE_IS_4_PORT(bp) ?
2979 BP_FUNC(bp) : BP_VN(bp))*4, 0);
2980 }
2981
2982 /* function setup flags */
2983 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ);
2984
2985 /* This flag is relevant for E1x only.
2986 * E2 doesn't have a TPA configuration in a function level.
2987 */
2988 flags |= (bp->flags & TPA_ENABLE_FLAG) ? FUNC_FLG_TPA : 0;
2989
2990 func_init.func_flgs = flags;
2991 func_init.pf_id = BP_FUNC(bp);
2992 func_init.func_id = BP_FUNC(bp);
2993 func_init.spq_map = bp->spq_mapping;
2994 func_init.spq_prod = bp->spq_prod_idx;
2995
2996 bnx2x_func_init(bp, &func_init);
2997
2998 memset(&(bp->cmng), 0, sizeof(struct cmng_struct_per_port));
2999
3000 /*
3001 * Congestion management values depend on the link rate
3002 * There is no active link so initial link rate is set to 10 Gbps.
3003 * When the link comes up The congestion management values are
3004 * re-calculated according to the actual link rate.
3005 */
3006 bp->link_vars.line_speed = SPEED_10000;
3007 bnx2x_cmng_fns_init(bp, true, bnx2x_get_cmng_fns_mode(bp));
3008
3009 /* Only the PMF sets the HW */
3010 if (bp->port.pmf)
3011 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3012
3013 /* init Event Queue */
3014 eq_data.base_addr.hi = U64_HI(bp->eq_mapping);
3015 eq_data.base_addr.lo = U64_LO(bp->eq_mapping);
3016 eq_data.producer = bp->eq_prod;
3017 eq_data.index_id = HC_SP_INDEX_EQ_CONS;
3018 eq_data.sb_id = DEF_SB_ID;
3019 storm_memset_eq_data(bp, &eq_data, BP_FUNC(bp));
3020 }
3021
3022
3023 static void bnx2x_e1h_disable(struct bnx2x *bp)
3024 {
3025 int port = BP_PORT(bp);
3026
3027 bnx2x_tx_disable(bp);
3028
3029 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
3030 }
3031
3032 static void bnx2x_e1h_enable(struct bnx2x *bp)
3033 {
3034 int port = BP_PORT(bp);
3035
3036 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
3037
3038 /* Tx queue should be only reenabled */
3039 netif_tx_wake_all_queues(bp->dev);
3040
3041 /*
3042 * Should not call netif_carrier_on since it will be called if the link
3043 * is up when checking for link state
3044 */
3045 }
3046
3047 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3048
3049 static void bnx2x_drv_info_ether_stat(struct bnx2x *bp)
3050 {
3051 struct eth_stats_info *ether_stat =
3052 &bp->slowpath->drv_info_to_mcp.ether_stat;
3053
3054 /* leave last char as NULL */
3055 memcpy(ether_stat->version, DRV_MODULE_VERSION,
3056 ETH_STAT_INFO_VERSION_LEN - 1);
3057
3058 bp->sp_objs[0].mac_obj.get_n_elements(bp, &bp->sp_objs[0].mac_obj,
3059 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED,
3060 ether_stat->mac_local);
3061
3062 ether_stat->mtu_size = bp->dev->mtu;
3063
3064 if (bp->dev->features & NETIF_F_RXCSUM)
3065 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK;
3066 if (bp->dev->features & NETIF_F_TSO)
3067 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK;
3068 ether_stat->feature_flags |= bp->common.boot_mode;
3069
3070 ether_stat->promiscuous_mode = (bp->dev->flags & IFF_PROMISC) ? 1 : 0;
3071
3072 ether_stat->txq_size = bp->tx_ring_size;
3073 ether_stat->rxq_size = bp->rx_ring_size;
3074 }
3075
3076 static void bnx2x_drv_info_fcoe_stat(struct bnx2x *bp)
3077 {
3078 #ifdef BCM_CNIC
3079 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3080 struct fcoe_stats_info *fcoe_stat =
3081 &bp->slowpath->drv_info_to_mcp.fcoe_stat;
3082
3083 memcpy(fcoe_stat->mac_local + MAC_LEADING_ZERO_CNT,
3084 bp->fip_mac, ETH_ALEN);
3085
3086 fcoe_stat->qos_priority =
3087 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_FCOE];
3088
3089 /* insert FCoE stats from ramrod response */
3090 if (!NO_FCOE(bp)) {
3091 struct tstorm_per_queue_stats *fcoe_q_tstorm_stats =
3092 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3093 tstorm_queue_statistics;
3094
3095 struct xstorm_per_queue_stats *fcoe_q_xstorm_stats =
3096 &bp->fw_stats_data->queue_stats[FCOE_IDX(bp)].
3097 xstorm_queue_statistics;
3098
3099 struct fcoe_statistics_params *fw_fcoe_stat =
3100 &bp->fw_stats_data->fcoe;
3101
3102 ADD_64(fcoe_stat->rx_bytes_hi, 0, fcoe_stat->rx_bytes_lo,
3103 fw_fcoe_stat->rx_stat0.fcoe_rx_byte_cnt);
3104
3105 ADD_64(fcoe_stat->rx_bytes_hi,
3106 fcoe_q_tstorm_stats->rcv_ucast_bytes.hi,
3107 fcoe_stat->rx_bytes_lo,
3108 fcoe_q_tstorm_stats->rcv_ucast_bytes.lo);
3109
3110 ADD_64(fcoe_stat->rx_bytes_hi,
3111 fcoe_q_tstorm_stats->rcv_bcast_bytes.hi,
3112 fcoe_stat->rx_bytes_lo,
3113 fcoe_q_tstorm_stats->rcv_bcast_bytes.lo);
3114
3115 ADD_64(fcoe_stat->rx_bytes_hi,
3116 fcoe_q_tstorm_stats->rcv_mcast_bytes.hi,
3117 fcoe_stat->rx_bytes_lo,
3118 fcoe_q_tstorm_stats->rcv_mcast_bytes.lo);
3119
3120 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3121 fw_fcoe_stat->rx_stat0.fcoe_rx_pkt_cnt);
3122
3123 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3124 fcoe_q_tstorm_stats->rcv_ucast_pkts);
3125
3126 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3127 fcoe_q_tstorm_stats->rcv_bcast_pkts);
3128
3129 ADD_64(fcoe_stat->rx_frames_hi, 0, fcoe_stat->rx_frames_lo,
3130 fcoe_q_tstorm_stats->rcv_mcast_pkts);
3131
3132 ADD_64(fcoe_stat->tx_bytes_hi, 0, fcoe_stat->tx_bytes_lo,
3133 fw_fcoe_stat->tx_stat.fcoe_tx_byte_cnt);
3134
3135 ADD_64(fcoe_stat->tx_bytes_hi,
3136 fcoe_q_xstorm_stats->ucast_bytes_sent.hi,
3137 fcoe_stat->tx_bytes_lo,
3138 fcoe_q_xstorm_stats->ucast_bytes_sent.lo);
3139
3140 ADD_64(fcoe_stat->tx_bytes_hi,
3141 fcoe_q_xstorm_stats->bcast_bytes_sent.hi,
3142 fcoe_stat->tx_bytes_lo,
3143 fcoe_q_xstorm_stats->bcast_bytes_sent.lo);
3144
3145 ADD_64(fcoe_stat->tx_bytes_hi,
3146 fcoe_q_xstorm_stats->mcast_bytes_sent.hi,
3147 fcoe_stat->tx_bytes_lo,
3148 fcoe_q_xstorm_stats->mcast_bytes_sent.lo);
3149
3150 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3151 fw_fcoe_stat->tx_stat.fcoe_tx_pkt_cnt);
3152
3153 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3154 fcoe_q_xstorm_stats->ucast_pkts_sent);
3155
3156 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3157 fcoe_q_xstorm_stats->bcast_pkts_sent);
3158
3159 ADD_64(fcoe_stat->tx_frames_hi, 0, fcoe_stat->tx_frames_lo,
3160 fcoe_q_xstorm_stats->mcast_pkts_sent);
3161 }
3162
3163 /* ask L5 driver to add data to the struct */
3164 bnx2x_cnic_notify(bp, CNIC_CTL_FCOE_STATS_GET_CMD);
3165 #endif
3166 }
3167
3168 static void bnx2x_drv_info_iscsi_stat(struct bnx2x *bp)
3169 {
3170 #ifdef BCM_CNIC
3171 struct bnx2x_dcbx_app_params *app = &bp->dcbx_port_params.app;
3172 struct iscsi_stats_info *iscsi_stat =
3173 &bp->slowpath->drv_info_to_mcp.iscsi_stat;
3174
3175 memcpy(iscsi_stat->mac_local + MAC_LEADING_ZERO_CNT,
3176 bp->cnic_eth_dev.iscsi_mac, ETH_ALEN);
3177
3178 iscsi_stat->qos_priority =
3179 app->traffic_type_priority[LLFC_TRAFFIC_TYPE_ISCSI];
3180
3181 /* ask L5 driver to add data to the struct */
3182 bnx2x_cnic_notify(bp, CNIC_CTL_ISCSI_STATS_GET_CMD);
3183 #endif
3184 }
3185
3186 /* called due to MCP event (on pmf):
3187 * reread new bandwidth configuration
3188 * configure FW
3189 * notify others function about the change
3190 */
3191 static void bnx2x_config_mf_bw(struct bnx2x *bp)
3192 {
3193 if (bp->link_vars.link_up) {
3194 bnx2x_cmng_fns_init(bp, true, CMNG_FNS_MINMAX);
3195 bnx2x_link_sync_notify(bp);
3196 }
3197 storm_memset_cmng(bp, &bp->cmng, BP_PORT(bp));
3198 }
3199
3200 static void bnx2x_set_mf_bw(struct bnx2x *bp)
3201 {
3202 bnx2x_config_mf_bw(bp);
3203 bnx2x_fw_command(bp, DRV_MSG_CODE_SET_MF_BW_ACK, 0);
3204 }
3205
3206 static void bnx2x_handle_eee_event(struct bnx2x *bp)
3207 {
3208 DP(BNX2X_MSG_MCP, "EEE - LLDP event\n");
3209 bnx2x_fw_command(bp, DRV_MSG_CODE_EEE_RESULTS_ACK, 0);
3210 }
3211
3212 static void bnx2x_handle_drv_info_req(struct bnx2x *bp)
3213 {
3214 enum drv_info_opcode op_code;
3215 u32 drv_info_ctl = SHMEM2_RD(bp, drv_info_control);
3216
3217 /* if drv_info version supported by MFW doesn't match - send NACK */
3218 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) {
3219 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3220 return;
3221 }
3222
3223 op_code = (drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >>
3224 DRV_INFO_CONTROL_OP_CODE_SHIFT;
3225
3226 memset(&bp->slowpath->drv_info_to_mcp, 0,
3227 sizeof(union drv_info_to_mcp));
3228
3229 switch (op_code) {
3230 case ETH_STATS_OPCODE:
3231 bnx2x_drv_info_ether_stat(bp);
3232 break;
3233 case FCOE_STATS_OPCODE:
3234 bnx2x_drv_info_fcoe_stat(bp);
3235 break;
3236 case ISCSI_STATS_OPCODE:
3237 bnx2x_drv_info_iscsi_stat(bp);
3238 break;
3239 default:
3240 /* if op code isn't supported - send NACK */
3241 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_NACK, 0);
3242 return;
3243 }
3244
3245 /* if we got drv_info attn from MFW then these fields are defined in
3246 * shmem2 for sure
3247 */
3248 SHMEM2_WR(bp, drv_info_host_addr_lo,
3249 U64_LO(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3250 SHMEM2_WR(bp, drv_info_host_addr_hi,
3251 U64_HI(bnx2x_sp_mapping(bp, drv_info_to_mcp)));
3252
3253 bnx2x_fw_command(bp, DRV_MSG_CODE_DRV_INFO_ACK, 0);
3254 }
3255
3256 static void bnx2x_dcc_event(struct bnx2x *bp, u32 dcc_event)
3257 {
3258 DP(BNX2X_MSG_MCP, "dcc_event 0x%x\n", dcc_event);
3259
3260 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) {
3261
3262 /*
3263 * This is the only place besides the function initialization
3264 * where the bp->flags can change so it is done without any
3265 * locks
3266 */
3267 if (bp->mf_config[BP_VN(bp)] & FUNC_MF_CFG_FUNC_DISABLED) {
3268 DP(BNX2X_MSG_MCP, "mf_cfg function disabled\n");
3269 bp->flags |= MF_FUNC_DIS;
3270
3271 bnx2x_e1h_disable(bp);
3272 } else {
3273 DP(BNX2X_MSG_MCP, "mf_cfg function enabled\n");
3274 bp->flags &= ~MF_FUNC_DIS;
3275
3276 bnx2x_e1h_enable(bp);
3277 }
3278 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF;
3279 }
3280 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) {
3281 bnx2x_config_mf_bw(bp);
3282 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION;
3283 }
3284
3285 /* Report results to MCP */
3286 if (dcc_event)
3287 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_FAILURE, 0);
3288 else
3289 bnx2x_fw_command(bp, DRV_MSG_CODE_DCC_OK, 0);
3290 }
3291
3292 /* must be called under the spq lock */
3293 static struct eth_spe *bnx2x_sp_get_next(struct bnx2x *bp)
3294 {
3295 struct eth_spe *next_spe = bp->spq_prod_bd;
3296
3297 if (bp->spq_prod_bd == bp->spq_last_bd) {
3298 bp->spq_prod_bd = bp->spq;
3299 bp->spq_prod_idx = 0;
3300 DP(BNX2X_MSG_SP, "end of spq\n");
3301 } else {
3302 bp->spq_prod_bd++;
3303 bp->spq_prod_idx++;
3304 }
3305 return next_spe;
3306 }
3307
3308 /* must be called under the spq lock */
3309 static void bnx2x_sp_prod_update(struct bnx2x *bp)
3310 {
3311 int func = BP_FUNC(bp);
3312
3313 /*
3314 * Make sure that BD data is updated before writing the producer:
3315 * BD data is written to the memory, the producer is read from the
3316 * memory, thus we need a full memory barrier to ensure the ordering.
3317 */
3318 mb();
3319
3320 REG_WR16(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func),
3321 bp->spq_prod_idx);
3322 mmiowb();
3323 }
3324
3325 /**
3326 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3327 *
3328 * @cmd: command to check
3329 * @cmd_type: command type
3330 */
3331 static bool bnx2x_is_contextless_ramrod(int cmd, int cmd_type)
3332 {
3333 if ((cmd_type == NONE_CONNECTION_TYPE) ||
3334 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) ||
3335 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) ||
3336 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) ||
3337 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) ||
3338 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) ||
3339 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE))
3340 return true;
3341 else
3342 return false;
3343
3344 }
3345
3346
3347 /**
3348 * bnx2x_sp_post - place a single command on an SP ring
3349 *
3350 * @bp: driver handle
3351 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3352 * @cid: SW CID the command is related to
3353 * @data_hi: command private data address (high 32 bits)
3354 * @data_lo: command private data address (low 32 bits)
3355 * @cmd_type: command type (e.g. NONE, ETH)
3356 *
3357 * SP data is handled as if it's always an address pair, thus data fields are
3358 * not swapped to little endian in upper functions. Instead this function swaps
3359 * data as if it's two u32 fields.
3360 */
3361 int bnx2x_sp_post(struct bnx2x *bp, int command, int cid,
3362 u32 data_hi, u32 data_lo, int cmd_type)
3363 {
3364 struct eth_spe *spe;
3365 u16 type;
3366 bool common = bnx2x_is_contextless_ramrod(command, cmd_type);
3367
3368 #ifdef BNX2X_STOP_ON_ERROR
3369 if (unlikely(bp->panic)) {
3370 BNX2X_ERR("Can't post SP when there is panic\n");
3371 return -EIO;
3372 }
3373 #endif
3374
3375 spin_lock_bh(&bp->spq_lock);
3376
3377 if (common) {
3378 if (!atomic_read(&bp->eq_spq_left)) {
3379 BNX2X_ERR("BUG! EQ ring full!\n");
3380 spin_unlock_bh(&bp->spq_lock);
3381 bnx2x_panic();
3382 return -EBUSY;
3383 }
3384 } else if (!atomic_read(&bp->cq_spq_left)) {
3385 BNX2X_ERR("BUG! SPQ ring full!\n");
3386 spin_unlock_bh(&bp->spq_lock);
3387 bnx2x_panic();
3388 return -EBUSY;
3389 }
3390
3391 spe = bnx2x_sp_get_next(bp);
3392
3393 /* CID needs port number to be encoded int it */
3394 spe->hdr.conn_and_cmd_data =
3395 cpu_to_le32((command << SPE_HDR_CMD_ID_SHIFT) |
3396 HW_CID(bp, cid));
3397
3398 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
3399
3400 type |= ((BP_FUNC(bp) << SPE_HDR_FUNCTION_ID_SHIFT) &
3401 SPE_HDR_FUNCTION_ID);
3402
3403 spe->hdr.type = cpu_to_le16(type);
3404
3405 spe->data.update_data_addr.hi = cpu_to_le32(data_hi);
3406 spe->data.update_data_addr.lo = cpu_to_le32(data_lo);
3407
3408 /*
3409 * It's ok if the actual decrement is issued towards the memory
3410 * somewhere between the spin_lock and spin_unlock. Thus no
3411 * more explict memory barrier is needed.
3412 */
3413 if (common)
3414 atomic_dec(&bp->eq_spq_left);
3415 else
3416 atomic_dec(&bp->cq_spq_left);
3417
3418
3419 DP(BNX2X_MSG_SP,
3420 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3421 bp->spq_prod_idx, (u32)U64_HI(bp->spq_mapping),
3422 (u32)(U64_LO(bp->spq_mapping) +
3423 (void *)bp->spq_prod_bd - (void *)bp->spq), command, common,
3424 HW_CID(bp, cid), data_hi, data_lo, type,
3425 atomic_read(&bp->cq_spq_left), atomic_read(&bp->eq_spq_left));
3426
3427 bnx2x_sp_prod_update(bp);
3428 spin_unlock_bh(&bp->spq_lock);
3429 return 0;
3430 }
3431
3432 /* acquire split MCP access lock register */
3433 static int bnx2x_acquire_alr(struct bnx2x *bp)
3434 {
3435 u32 j, val;
3436 int rc = 0;
3437
3438 might_sleep();
3439 for (j = 0; j < 1000; j++) {
3440 val = (1UL << 31);
3441 REG_WR(bp, GRCBASE_MCP + 0x9c, val);
3442 val = REG_RD(bp, GRCBASE_MCP + 0x9c);
3443 if (val & (1L << 31))
3444 break;
3445
3446 msleep(5);
3447 }
3448 if (!(val & (1L << 31))) {
3449 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3450 rc = -EBUSY;
3451 }
3452
3453 return rc;
3454 }
3455
3456 /* release split MCP access lock register */
3457 static void bnx2x_release_alr(struct bnx2x *bp)
3458 {
3459 REG_WR(bp, GRCBASE_MCP + 0x9c, 0);
3460 }
3461
3462 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3463 #define BNX2X_DEF_SB_IDX 0x0002
3464
3465 static u16 bnx2x_update_dsb_idx(struct bnx2x *bp)
3466 {
3467 struct host_sp_status_block *def_sb = bp->def_status_blk;
3468 u16 rc = 0;
3469
3470 barrier(); /* status block is written to by the chip */
3471 if (bp->def_att_idx != def_sb->atten_status_block.attn_bits_index) {
3472 bp->def_att_idx = def_sb->atten_status_block.attn_bits_index;
3473 rc |= BNX2X_DEF_SB_ATT_IDX;
3474 }
3475
3476 if (bp->def_idx != def_sb->sp_sb.running_index) {
3477 bp->def_idx = def_sb->sp_sb.running_index;
3478 rc |= BNX2X_DEF_SB_IDX;
3479 }
3480
3481 /* Do not reorder: indecies reading should complete before handling */
3482 barrier();
3483 return rc;
3484 }
3485
3486 /*
3487 * slow path service functions
3488 */
3489
3490 static void bnx2x_attn_int_asserted(struct bnx2x *bp, u32 asserted)
3491 {
3492 int port = BP_PORT(bp);
3493 u32 aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
3494 MISC_REG_AEU_MASK_ATTN_FUNC_0;
3495 u32 nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 :
3496 NIG_REG_MASK_INTERRUPT_PORT0;
3497 u32 aeu_mask;
3498 u32 nig_mask = 0;
3499 u32 reg_addr;
3500
3501 if (bp->attn_state & asserted)
3502 BNX2X_ERR("IGU ERROR\n");
3503
3504 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3505 aeu_mask = REG_RD(bp, aeu_addr);
3506
3507 DP(NETIF_MSG_HW, "aeu_mask %x newly asserted %x\n",
3508 aeu_mask, asserted);
3509 aeu_mask &= ~(asserted & 0x3ff);
3510 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
3511
3512 REG_WR(bp, aeu_addr, aeu_mask);
3513 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
3514
3515 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
3516 bp->attn_state |= asserted;
3517 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
3518
3519 if (asserted & ATTN_HARD_WIRED_MASK) {
3520 if (asserted & ATTN_NIG_FOR_FUNC) {
3521
3522 bnx2x_acquire_phy_lock(bp);
3523
3524 /* save nig interrupt mask */
3525 nig_mask = REG_RD(bp, nig_int_mask_addr);
3526
3527 /* If nig_mask is not set, no need to call the update
3528 * function.
3529 */
3530 if (nig_mask) {
3531 REG_WR(bp, nig_int_mask_addr, 0);
3532
3533 bnx2x_link_attn(bp);
3534 }
3535
3536 /* handle unicore attn? */
3537 }
3538 if (asserted & ATTN_SW_TIMER_4_FUNC)
3539 DP(NETIF_MSG_HW, "ATTN_SW_TIMER_4_FUNC!\n");
3540
3541 if (asserted & GPIO_2_FUNC)
3542 DP(NETIF_MSG_HW, "GPIO_2_FUNC!\n");
3543
3544 if (asserted & GPIO_3_FUNC)
3545 DP(NETIF_MSG_HW, "GPIO_3_FUNC!\n");
3546
3547 if (asserted & GPIO_4_FUNC)
3548 DP(NETIF_MSG_HW, "GPIO_4_FUNC!\n");
3549
3550 if (port == 0) {
3551 if (asserted & ATTN_GENERAL_ATTN_1) {
3552 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_1!\n");
3553 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_1, 0x0);
3554 }
3555 if (asserted & ATTN_GENERAL_ATTN_2) {
3556 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_2!\n");
3557 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_2, 0x0);
3558 }
3559 if (asserted & ATTN_GENERAL_ATTN_3) {
3560 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_3!\n");
3561 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_3, 0x0);
3562 }
3563 } else {
3564 if (asserted & ATTN_GENERAL_ATTN_4) {
3565 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_4!\n");
3566 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_4, 0x0);
3567 }
3568 if (asserted & ATTN_GENERAL_ATTN_5) {
3569 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_5!\n");
3570 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_5, 0x0);
3571 }
3572 if (asserted & ATTN_GENERAL_ATTN_6) {
3573 DP(NETIF_MSG_HW, "ATTN_GENERAL_ATTN_6!\n");
3574 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_6, 0x0);
3575 }
3576 }
3577
3578 } /* if hardwired */
3579
3580 if (bp->common.int_block == INT_BLOCK_HC)
3581 reg_addr = (HC_REG_COMMAND_REG + port*32 +
3582 COMMAND_REG_ATTN_BITS_SET);
3583 else
3584 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8);
3585
3586 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", asserted,
3587 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
3588 REG_WR(bp, reg_addr, asserted);
3589
3590 /* now set back the mask */
3591 if (asserted & ATTN_NIG_FOR_FUNC) {
3592 REG_WR(bp, nig_int_mask_addr, nig_mask);
3593 bnx2x_release_phy_lock(bp);
3594 }
3595 }
3596
3597 static void bnx2x_fan_failure(struct bnx2x *bp)
3598 {
3599 int port = BP_PORT(bp);
3600 u32 ext_phy_config;
3601 /* mark the failure */
3602 ext_phy_config =
3603 SHMEM_RD(bp,
3604 dev_info.port_hw_config[port].external_phy_config);
3605
3606 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK;
3607 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE;
3608 SHMEM_WR(bp, dev_info.port_hw_config[port].external_phy_config,
3609 ext_phy_config);
3610
3611 /* log the failure */
3612 netdev_err(bp->dev, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3613 "Please contact OEM Support for assistance\n");
3614
3615 /*
3616 * Scheudle device reset (unload)
3617 * This is due to some boards consuming sufficient power when driver is
3618 * up to overheat if fan fails.
3619 */
3620 smp_mb__before_clear_bit();
3621 set_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state);
3622 smp_mb__after_clear_bit();
3623 schedule_delayed_work(&bp->sp_rtnl_task, 0);
3624
3625 }
3626
3627 static void bnx2x_attn_int_deasserted0(struct bnx2x *bp, u32 attn)
3628 {
3629 int port = BP_PORT(bp);
3630 int reg_offset;
3631 u32 val;
3632
3633 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
3634 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
3635
3636 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) {
3637
3638 val = REG_RD(bp, reg_offset);
3639 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5;
3640 REG_WR(bp, reg_offset, val);
3641
3642 BNX2X_ERR("SPIO5 hw attention\n");
3643
3644 /* Fan failure attention */
3645 bnx2x_hw_reset_phy(&bp->link_params);
3646 bnx2x_fan_failure(bp);
3647 }
3648
3649 if ((attn & bp->link_vars.aeu_int_mask) && bp->port.pmf) {
3650 bnx2x_acquire_phy_lock(bp);
3651 bnx2x_handle_module_detect_int(&bp->link_params);
3652 bnx2x_release_phy_lock(bp);
3653 }
3654
3655 if (attn & HW_INTERRUT_ASSERT_SET_0) {
3656
3657 val = REG_RD(bp, reg_offset);
3658 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0);
3659 REG_WR(bp, reg_offset, val);
3660
3661 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3662 (u32)(attn & HW_INTERRUT_ASSERT_SET_0));
3663 bnx2x_panic();
3664 }
3665 }
3666
3667 static void bnx2x_attn_int_deasserted1(struct bnx2x *bp, u32 attn)
3668 {
3669 u32 val;
3670
3671 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) {
3672
3673 val = REG_RD(bp, DORQ_REG_DORQ_INT_STS_CLR);
3674 BNX2X_ERR("DB hw attention 0x%x\n", val);
3675 /* DORQ discard attention */
3676 if (val & 0x2)
3677 BNX2X_ERR("FATAL error from DORQ\n");
3678 }
3679
3680 if (attn & HW_INTERRUT_ASSERT_SET_1) {
3681
3682 int port = BP_PORT(bp);
3683 int reg_offset;
3684
3685 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 :
3686 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1);
3687
3688 val = REG_RD(bp, reg_offset);
3689 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1);
3690 REG_WR(bp, reg_offset, val);
3691
3692 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3693 (u32)(attn & HW_INTERRUT_ASSERT_SET_1));
3694 bnx2x_panic();
3695 }
3696 }
3697
3698 static void bnx2x_attn_int_deasserted2(struct bnx2x *bp, u32 attn)
3699 {
3700 u32 val;
3701
3702 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) {
3703
3704 val = REG_RD(bp, CFC_REG_CFC_INT_STS_CLR);
3705 BNX2X_ERR("CFC hw attention 0x%x\n", val);
3706 /* CFC error attention */
3707 if (val & 0x2)
3708 BNX2X_ERR("FATAL error from CFC\n");
3709 }
3710
3711 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) {
3712 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_0);
3713 BNX2X_ERR("PXP hw attention-0 0x%x\n", val);
3714 /* RQ_USDMDP_FIFO_OVERFLOW */
3715 if (val & 0x18000)
3716 BNX2X_ERR("FATAL error from PXP\n");
3717
3718 if (!CHIP_IS_E1x(bp)) {
3719 val = REG_RD(bp, PXP_REG_PXP_INT_STS_CLR_1);
3720 BNX2X_ERR("PXP hw attention-1 0x%x\n", val);
3721 }
3722 }
3723
3724 if (attn & HW_INTERRUT_ASSERT_SET_2) {
3725
3726 int port = BP_PORT(bp);
3727 int reg_offset;
3728
3729 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 :
3730 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2);
3731
3732 val = REG_RD(bp, reg_offset);
3733 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2);
3734 REG_WR(bp, reg_offset, val);
3735
3736 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3737 (u32)(attn & HW_INTERRUT_ASSERT_SET_2));
3738 bnx2x_panic();
3739 }
3740 }
3741
3742 static void bnx2x_attn_int_deasserted3(struct bnx2x *bp, u32 attn)
3743 {
3744 u32 val;
3745
3746 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) {
3747
3748 if (attn & BNX2X_PMF_LINK_ASSERT) {
3749 int func = BP_FUNC(bp);
3750
3751 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
3752 bnx2x_read_mf_cfg(bp);
3753 bp->mf_config[BP_VN(bp)] = MF_CFG_RD(bp,
3754 func_mf_config[BP_ABS_FUNC(bp)].config);
3755 val = SHMEM_RD(bp,
3756 func_mb[BP_FW_MB_IDX(bp)].drv_status);
3757 if (val & DRV_STATUS_DCC_EVENT_MASK)
3758 bnx2x_dcc_event(bp,
3759 (val & DRV_STATUS_DCC_EVENT_MASK));
3760
3761 if (val & DRV_STATUS_SET_MF_BW)
3762 bnx2x_set_mf_bw(bp);
3763
3764 if (val & DRV_STATUS_DRV_INFO_REQ)
3765 bnx2x_handle_drv_info_req(bp);
3766 if ((bp->port.pmf == 0) && (val & DRV_STATUS_PMF))
3767 bnx2x_pmf_update(bp);
3768
3769 if (bp->port.pmf &&
3770 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) &&
3771 bp->dcbx_enabled > 0)
3772 /* start dcbx state machine */
3773 bnx2x_dcbx_set_params(bp,
3774 BNX2X_DCBX_STATE_NEG_RECEIVED);
3775 if (val & DRV_STATUS_AFEX_EVENT_MASK)
3776 bnx2x_handle_afex_cmd(bp,
3777 val & DRV_STATUS_AFEX_EVENT_MASK);
3778 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS)
3779 bnx2x_handle_eee_event(bp);
3780 if (bp->link_vars.periodic_flags &
3781 PERIODIC_FLAGS_LINK_EVENT) {
3782 /* sync with link */
3783 bnx2x_acquire_phy_lock(bp);
3784 bp->link_vars.periodic_flags &=
3785 ~PERIODIC_FLAGS_LINK_EVENT;
3786 bnx2x_release_phy_lock(bp);
3787 if (IS_MF(bp))
3788 bnx2x_link_sync_notify(bp);
3789 bnx2x_link_report(bp);
3790 }
3791 /* Always call it here: bnx2x_link_report() will
3792 * prevent the link indication duplication.
3793 */
3794 bnx2x__link_status_update(bp);
3795 } else if (attn & BNX2X_MC_ASSERT_BITS) {
3796
3797 BNX2X_ERR("MC assert!\n");
3798 bnx2x_mc_assert(bp);
3799 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_10, 0);
3800 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_9, 0);
3801 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_8, 0);
3802 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_7, 0);
3803 bnx2x_panic();
3804
3805 } else if (attn & BNX2X_MCP_ASSERT) {
3806
3807 BNX2X_ERR("MCP assert!\n");
3808 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_11, 0);
3809 bnx2x_fw_dump(bp);
3810
3811 } else
3812 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn);
3813 }
3814
3815 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) {
3816 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn);
3817 if (attn & BNX2X_GRC_TIMEOUT) {
3818 val = CHIP_IS_E1(bp) ? 0 :
3819 REG_RD(bp, MISC_REG_GRC_TIMEOUT_ATTN);
3820 BNX2X_ERR("GRC time-out 0x%08x\n", val);
3821 }
3822 if (attn & BNX2X_GRC_RSV) {
3823 val = CHIP_IS_E1(bp) ? 0 :
3824 REG_RD(bp, MISC_REG_GRC_RSV_ATTN);
3825 BNX2X_ERR("GRC reserved 0x%08x\n", val);
3826 }
3827 REG_WR(bp, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff);
3828 }
3829 }
3830
3831 /*
3832 * Bits map:
3833 * 0-7 - Engine0 load counter.
3834 * 8-15 - Engine1 load counter.
3835 * 16 - Engine0 RESET_IN_PROGRESS bit.
3836 * 17 - Engine1 RESET_IN_PROGRESS bit.
3837 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3838 * on the engine
3839 * 19 - Engine1 ONE_IS_LOADED.
3840 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3841 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3842 * just the one belonging to its engine).
3843 *
3844 */
3845 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3846
3847 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3848 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3849 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3850 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3851 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3852 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3853 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3854
3855 /*
3856 * Set the GLOBAL_RESET bit.
3857 *
3858 * Should be run under rtnl lock
3859 */
3860 void bnx2x_set_reset_global(struct bnx2x *bp)
3861 {
3862 u32 val;
3863 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3864 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3865 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val | BNX2X_GLOBAL_RESET_BIT);
3866 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3867 }
3868
3869 /*
3870 * Clear the GLOBAL_RESET bit.
3871 *
3872 * Should be run under rtnl lock
3873 */
3874 static void bnx2x_clear_reset_global(struct bnx2x *bp)
3875 {
3876 u32 val;
3877 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3878 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3879 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val & (~BNX2X_GLOBAL_RESET_BIT));
3880 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3881 }
3882
3883 /*
3884 * Checks the GLOBAL_RESET bit.
3885 *
3886 * should be run under rtnl lock
3887 */
3888 static bool bnx2x_reset_is_global(struct bnx2x *bp)
3889 {
3890 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3891
3892 DP(NETIF_MSG_HW, "GEN_REG_VAL=0x%08x\n", val);
3893 return (val & BNX2X_GLOBAL_RESET_BIT) ? true : false;
3894 }
3895
3896 /*
3897 * Clear RESET_IN_PROGRESS bit for the current engine.
3898 *
3899 * Should be run under rtnl lock
3900 */
3901 static void bnx2x_set_reset_done(struct bnx2x *bp)
3902 {
3903 u32 val;
3904 u32 bit = BP_PATH(bp) ?
3905 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3906 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3907 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3908
3909 /* Clear the bit */
3910 val &= ~bit;
3911 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3912
3913 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3914 }
3915
3916 /*
3917 * Set RESET_IN_PROGRESS for the current engine.
3918 *
3919 * should be run under rtnl lock
3920 */
3921 void bnx2x_set_reset_in_progress(struct bnx2x *bp)
3922 {
3923 u32 val;
3924 u32 bit = BP_PATH(bp) ?
3925 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3926 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3927 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3928
3929 /* Set the bit */
3930 val |= bit;
3931 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3932 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3933 }
3934
3935 /*
3936 * Checks the RESET_IN_PROGRESS bit for the given engine.
3937 * should be run under rtnl lock
3938 */
3939 bool bnx2x_reset_is_done(struct bnx2x *bp, int engine)
3940 {
3941 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3942 u32 bit = engine ?
3943 BNX2X_PATH1_RST_IN_PROG_BIT : BNX2X_PATH0_RST_IN_PROG_BIT;
3944
3945 /* return false if bit is set */
3946 return (val & bit) ? false : true;
3947 }
3948
3949 /*
3950 * set pf load for the current pf.
3951 *
3952 * should be run under rtnl lock
3953 */
3954 void bnx2x_set_pf_load(struct bnx2x *bp)
3955 {
3956 u32 val1, val;
3957 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3958 BNX2X_PATH0_LOAD_CNT_MASK;
3959 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3960 BNX2X_PATH0_LOAD_CNT_SHIFT;
3961
3962 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3963 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
3964
3965 DP(NETIF_MSG_IFUP, "Old GEN_REG_VAL=0x%08x\n", val);
3966
3967 /* get the current counter value */
3968 val1 = (val & mask) >> shift;
3969
3970 /* set bit of that PF */
3971 val1 |= (1 << bp->pf_num);
3972
3973 /* clear the old value */
3974 val &= ~mask;
3975
3976 /* set the new one */
3977 val |= ((val1 << shift) & mask);
3978
3979 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
3980 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
3981 }
3982
3983 /**
3984 * bnx2x_clear_pf_load - clear pf load mark
3985 *
3986 * @bp: driver handle
3987 *
3988 * Should be run under rtnl lock.
3989 * Decrements the load counter for the current engine. Returns
3990 * whether other functions are still loaded
3991 */
3992 bool bnx2x_clear_pf_load(struct bnx2x *bp)
3993 {
3994 u32 val1, val;
3995 u32 mask = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_MASK :
3996 BNX2X_PATH0_LOAD_CNT_MASK;
3997 u32 shift = BP_PATH(bp) ? BNX2X_PATH1_LOAD_CNT_SHIFT :
3998 BNX2X_PATH0_LOAD_CNT_SHIFT;
3999
4000 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4001 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4002 DP(NETIF_MSG_IFDOWN, "Old GEN_REG_VAL=0x%08x\n", val);
4003
4004 /* get the current counter value */
4005 val1 = (val & mask) >> shift;
4006
4007 /* clear bit of that PF */
4008 val1 &= ~(1 << bp->pf_num);
4009
4010 /* clear the old value */
4011 val &= ~mask;
4012
4013 /* set the new one */
4014 val |= ((val1 << shift) & mask);
4015
4016 REG_WR(bp, BNX2X_RECOVERY_GLOB_REG, val);
4017 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RECOVERY_REG);
4018 return val1 != 0;
4019 }
4020
4021 /*
4022 * Read the load status for the current engine.
4023 *
4024 * should be run under rtnl lock
4025 */
4026 static bool bnx2x_get_load_status(struct bnx2x *bp, int engine)
4027 {
4028 u32 mask = (engine ? BNX2X_PATH1_LOAD_CNT_MASK :
4029 BNX2X_PATH0_LOAD_CNT_MASK);
4030 u32 shift = (engine ? BNX2X_PATH1_LOAD_CNT_SHIFT :
4031 BNX2X_PATH0_LOAD_CNT_SHIFT);
4032 u32 val = REG_RD(bp, BNX2X_RECOVERY_GLOB_REG);
4033
4034 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "GLOB_REG=0x%08x\n", val);
4035
4036 val = (val & mask) >> shift;
4037
4038 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "load mask for engine %d = 0x%x\n",
4039 engine, val);
4040
4041 return val != 0;
4042 }
4043
4044 static void _print_next_block(int idx, const char *blk)
4045 {
4046 pr_cont("%s%s", idx ? ", " : "", blk);
4047 }
4048
4049 static int bnx2x_check_blocks_with_parity0(u32 sig, int par_num,
4050 bool print)
4051 {
4052 int i = 0;
4053 u32 cur_bit = 0;
4054 for (i = 0; sig; i++) {
4055 cur_bit = ((u32)0x1 << i);
4056 if (sig & cur_bit) {
4057 switch (cur_bit) {
4058 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR:
4059 if (print)
4060 _print_next_block(par_num++, "BRB");
4061 break;
4062 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR:
4063 if (print)
4064 _print_next_block(par_num++, "PARSER");
4065 break;
4066 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR:
4067 if (print)
4068 _print_next_block(par_num++, "TSDM");
4069 break;
4070 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR:
4071 if (print)
4072 _print_next_block(par_num++,
4073 "SEARCHER");
4074 break;
4075 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR:
4076 if (print)
4077 _print_next_block(par_num++, "TCM");
4078 break;
4079 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR:
4080 if (print)
4081 _print_next_block(par_num++, "TSEMI");
4082 break;
4083 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR:
4084 if (print)
4085 _print_next_block(par_num++, "XPB");
4086 break;
4087 }
4088
4089 /* Clear the bit */
4090 sig &= ~cur_bit;
4091 }
4092 }
4093
4094 return par_num;
4095 }
4096
4097 static int bnx2x_check_blocks_with_parity1(u32 sig, int par_num,
4098 bool *global, bool print)
4099 {
4100 int i = 0;
4101 u32 cur_bit = 0;
4102 for (i = 0; sig; i++) {
4103 cur_bit = ((u32)0x1 << i);
4104 if (sig & cur_bit) {
4105 switch (cur_bit) {
4106 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR:
4107 if (print)
4108 _print_next_block(par_num++, "PBF");
4109 break;
4110 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR:
4111 if (print)
4112 _print_next_block(par_num++, "QM");
4113 break;
4114 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR:
4115 if (print)
4116 _print_next_block(par_num++, "TM");
4117 break;
4118 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR:
4119 if (print)
4120 _print_next_block(par_num++, "XSDM");
4121 break;
4122 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR:
4123 if (print)
4124 _print_next_block(par_num++, "XCM");
4125 break;
4126 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR:
4127 if (print)
4128 _print_next_block(par_num++, "XSEMI");
4129 break;
4130 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR:
4131 if (print)
4132 _print_next_block(par_num++,
4133 "DOORBELLQ");
4134 break;
4135 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR:
4136 if (print)
4137 _print_next_block(par_num++, "NIG");
4138 break;
4139 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR:
4140 if (print)
4141 _print_next_block(par_num++,
4142 "VAUX PCI CORE");
4143 *global = true;
4144 break;
4145 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR:
4146 if (print)
4147 _print_next_block(par_num++, "DEBUG");
4148 break;
4149 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR:
4150 if (print)
4151 _print_next_block(par_num++, "USDM");
4152 break;
4153 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR:
4154 if (print)
4155 _print_next_block(par_num++, "UCM");
4156 break;
4157 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR:
4158 if (print)
4159 _print_next_block(par_num++, "USEMI");
4160 break;
4161 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR:
4162 if (print)
4163 _print_next_block(par_num++, "UPB");
4164 break;
4165 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR:
4166 if (print)
4167 _print_next_block(par_num++, "CSDM");
4168 break;
4169 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR:
4170 if (print)
4171 _print_next_block(par_num++, "CCM");
4172 break;
4173 }
4174
4175 /* Clear the bit */
4176 sig &= ~cur_bit;
4177 }
4178 }
4179
4180 return par_num;
4181 }
4182
4183 static int bnx2x_check_blocks_with_parity2(u32 sig, int par_num,
4184 bool print)
4185 {
4186 int i = 0;
4187 u32 cur_bit = 0;
4188 for (i = 0; sig; i++) {
4189 cur_bit = ((u32)0x1 << i);
4190 if (sig & cur_bit) {
4191 switch (cur_bit) {
4192 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
4193 if (print)
4194 _print_next_block(par_num++, "CSEMI");
4195 break;
4196 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR:
4197 if (print)
4198 _print_next_block(par_num++, "PXP");
4199 break;
4200 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR:
4201 if (print)
4202 _print_next_block(par_num++,
4203 "PXPPCICLOCKCLIENT");
4204 break;
4205 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR:
4206 if (print)
4207 _print_next_block(par_num++, "CFC");
4208 break;
4209 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR:
4210 if (print)
4211 _print_next_block(par_num++, "CDU");
4212 break;
4213 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR:
4214 if (print)
4215 _print_next_block(par_num++, "DMAE");
4216 break;
4217 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR:
4218 if (print)
4219 _print_next_block(par_num++, "IGU");
4220 break;
4221 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR:
4222 if (print)
4223 _print_next_block(par_num++, "MISC");
4224 break;
4225 }
4226
4227 /* Clear the bit */
4228 sig &= ~cur_bit;
4229 }
4230 }
4231
4232 return par_num;
4233 }
4234
4235 static int bnx2x_check_blocks_with_parity3(u32 sig, int par_num,
4236 bool *global, bool print)
4237 {
4238 int i = 0;
4239 u32 cur_bit = 0;
4240 for (i = 0; sig; i++) {
4241 cur_bit = ((u32)0x1 << i);
4242 if (sig & cur_bit) {
4243 switch (cur_bit) {
4244 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY:
4245 if (print)
4246 _print_next_block(par_num++, "MCP ROM");
4247 *global = true;
4248 break;
4249 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
4250 if (print)
4251 _print_next_block(par_num++,
4252 "MCP UMP RX");
4253 *global = true;
4254 break;
4255 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
4256 if (print)
4257 _print_next_block(par_num++,
4258 "MCP UMP TX");
4259 *global = true;
4260 break;
4261 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
4262 if (print)
4263 _print_next_block(par_num++,
4264 "MCP SCPAD");
4265 *global = true;
4266 break;
4267 }
4268
4269 /* Clear the bit */
4270 sig &= ~cur_bit;
4271 }
4272 }
4273
4274 return par_num;
4275 }
4276
4277 static int bnx2x_check_blocks_with_parity4(u32 sig, int par_num,
4278 bool print)
4279 {
4280 int i = 0;
4281 u32 cur_bit = 0;
4282 for (i = 0; sig; i++) {
4283 cur_bit = ((u32)0x1 << i);
4284 if (sig & cur_bit) {
4285 switch (cur_bit) {
4286 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
4287 if (print)
4288 _print_next_block(par_num++, "PGLUE_B");
4289 break;
4290 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR:
4291 if (print)
4292 _print_next_block(par_num++, "ATC");
4293 break;
4294 }
4295
4296 /* Clear the bit */
4297 sig &= ~cur_bit;
4298 }
4299 }
4300
4301 return par_num;
4302 }
4303
4304 static bool bnx2x_parity_attn(struct bnx2x *bp, bool *global, bool print,
4305 u32 *sig)
4306 {
4307 if ((sig[0] & HW_PRTY_ASSERT_SET_0) ||
4308 (sig[1] & HW_PRTY_ASSERT_SET_1) ||
4309 (sig[2] & HW_PRTY_ASSERT_SET_2) ||
4310 (sig[3] & HW_PRTY_ASSERT_SET_3) ||
4311 (sig[4] & HW_PRTY_ASSERT_SET_4)) {
4312 int par_num = 0;
4313 DP(NETIF_MSG_HW, "Was parity error: HW block parity attention:\n"
4314 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4315 sig[0] & HW_PRTY_ASSERT_SET_0,
4316 sig[1] & HW_PRTY_ASSERT_SET_1,
4317 sig[2] & HW_PRTY_ASSERT_SET_2,
4318 sig[3] & HW_PRTY_ASSERT_SET_3,
4319 sig[4] & HW_PRTY_ASSERT_SET_4);
4320 if (print)
4321 netdev_err(bp->dev,
4322 "Parity errors detected in blocks: ");
4323 par_num = bnx2x_check_blocks_with_parity0(
4324 sig[0] & HW_PRTY_ASSERT_SET_0, par_num, print);
4325 par_num = bnx2x_check_blocks_with_parity1(
4326 sig[1] & HW_PRTY_ASSERT_SET_1, par_num, global, print);
4327 par_num = bnx2x_check_blocks_with_parity2(
4328 sig[2] & HW_PRTY_ASSERT_SET_2, par_num, print);
4329 par_num = bnx2x_check_blocks_with_parity3(
4330 sig[3] & HW_PRTY_ASSERT_SET_3, par_num, global, print);
4331 par_num = bnx2x_check_blocks_with_parity4(
4332 sig[4] & HW_PRTY_ASSERT_SET_4, par_num, print);
4333
4334 if (print)
4335 pr_cont("\n");
4336
4337 return true;
4338 } else
4339 return false;
4340 }
4341
4342 /**
4343 * bnx2x_chk_parity_attn - checks for parity attentions.
4344 *
4345 * @bp: driver handle
4346 * @global: true if there was a global attention
4347 * @print: show parity attention in syslog
4348 */
4349 bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
4350 {
4351 struct attn_route attn = { {0} };
4352 int port = BP_PORT(bp);
4353
4354 attn.sig[0] = REG_RD(bp,
4355 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 +
4356 port*4);
4357 attn.sig[1] = REG_RD(bp,
4358 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 +
4359 port*4);
4360 attn.sig[2] = REG_RD(bp,
4361 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 +
4362 port*4);
4363 attn.sig[3] = REG_RD(bp,
4364 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
4365 port*4);
4366
4367 if (!CHIP_IS_E1x(bp))
4368 attn.sig[4] = REG_RD(bp,
4369 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 +
4370 port*4);
4371
4372 return bnx2x_parity_attn(bp, global, print, attn.sig);
4373 }
4374
4375
4376 static void bnx2x_attn_int_deasserted4(struct bnx2x *bp, u32 attn)
4377 {
4378 u32 val;
4379 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) {
4380
4381 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS_CLR);
4382 BNX2X_ERR("PGLUE hw attention 0x%x\n", val);
4383 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR)
4384 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4385 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR)
4386 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4387 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN)
4388 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4389 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN)
4390 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4391 if (val &
4392 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN)
4393 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4394 if (val &
4395 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN)
4396 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4397 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN)
4398 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4399 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN)
4400 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4401 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW)
4402 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4403 }
4404 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) {
4405 val = REG_RD(bp, ATC_REG_ATC_INT_STS_CLR);
4406 BNX2X_ERR("ATC hw attention 0x%x\n", val);
4407 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR)
4408 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4409 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND)
4410 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4411 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS)
4412 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4413 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT)
4414 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4415 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR)
4416 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4417 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU)
4418 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4419 }
4420
4421 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4422 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) {
4423 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4424 (u32)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR |
4425 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)));
4426 }
4427
4428 }
4429
4430 static void bnx2x_attn_int_deasserted(struct bnx2x *bp, u32 deasserted)
4431 {
4432 struct attn_route attn, *group_mask;
4433 int port = BP_PORT(bp);
4434 int index;
4435 u32 reg_addr;
4436 u32 val;
4437 u32 aeu_mask;
4438 bool global = false;
4439
4440 /* need to take HW lock because MCP or other port might also
4441 try to handle this event */
4442 bnx2x_acquire_alr(bp);
4443
4444 if (bnx2x_chk_parity_attn(bp, &global, true)) {
4445 #ifndef BNX2X_STOP_ON_ERROR
4446 bp->recovery_state = BNX2X_RECOVERY_INIT;
4447 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4448 /* Disable HW interrupts */
4449 bnx2x_int_disable(bp);
4450 /* In case of parity errors don't handle attentions so that
4451 * other function would "see" parity errors.
4452 */
4453 #else
4454 bnx2x_panic();
4455 #endif
4456 bnx2x_release_alr(bp);
4457 return;
4458 }
4459
4460 attn.sig[0] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4);
4461 attn.sig[1] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4);
4462 attn.sig[2] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4);
4463 attn.sig[3] = REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4);
4464 if (!CHIP_IS_E1x(bp))
4465 attn.sig[4] =
4466 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4);
4467 else
4468 attn.sig[4] = 0;
4469
4470 DP(NETIF_MSG_HW, "attn: %08x %08x %08x %08x %08x\n",
4471 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]);
4472
4473 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
4474 if (deasserted & (1 << index)) {
4475 group_mask = &bp->attn_group[index];
4476
4477 DP(NETIF_MSG_HW, "group[%d]: %08x %08x %08x %08x %08x\n",
4478 index,
4479 group_mask->sig[0], group_mask->sig[1],
4480 group_mask->sig[2], group_mask->sig[3],
4481 group_mask->sig[4]);
4482
4483 bnx2x_attn_int_deasserted4(bp,
4484 attn.sig[4] & group_mask->sig[4]);
4485 bnx2x_attn_int_deasserted3(bp,
4486 attn.sig[3] & group_mask->sig[3]);
4487 bnx2x_attn_int_deasserted1(bp,
4488 attn.sig[1] & group_mask->sig[1]);
4489 bnx2x_attn_int_deasserted2(bp,
4490 attn.sig[2] & group_mask->sig[2]);
4491 bnx2x_attn_int_deasserted0(bp,
4492 attn.sig[0] & group_mask->sig[0]);
4493 }
4494 }
4495
4496 bnx2x_release_alr(bp);
4497
4498 if (bp->common.int_block == INT_BLOCK_HC)
4499 reg_addr = (HC_REG_COMMAND_REG + port*32 +
4500 COMMAND_REG_ATTN_BITS_CLR);
4501 else
4502 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8);
4503
4504 val = ~deasserted;
4505 DP(NETIF_MSG_HW, "about to mask 0x%08x at %s addr 0x%x\n", val,
4506 (bp->common.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr);
4507 REG_WR(bp, reg_addr, val);
4508
4509 if (~bp->attn_state & deasserted)
4510 BNX2X_ERR("IGU ERROR\n");
4511
4512 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
4513 MISC_REG_AEU_MASK_ATTN_FUNC_0;
4514
4515 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4516 aeu_mask = REG_RD(bp, reg_addr);
4517
4518 DP(NETIF_MSG_HW, "aeu_mask %x newly deasserted %x\n",
4519 aeu_mask, deasserted);
4520 aeu_mask |= (deasserted & 0x3ff);
4521 DP(NETIF_MSG_HW, "new mask %x\n", aeu_mask);
4522
4523 REG_WR(bp, reg_addr, aeu_mask);
4524 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port);
4525
4526 DP(NETIF_MSG_HW, "attn_state %x\n", bp->attn_state);
4527 bp->attn_state &= ~deasserted;
4528 DP(NETIF_MSG_HW, "new state %x\n", bp->attn_state);
4529 }
4530
4531 static void bnx2x_attn_int(struct bnx2x *bp)
4532 {
4533 /* read local copy of bits */
4534 u32 attn_bits = le32_to_cpu(bp->def_status_blk->atten_status_block.
4535 attn_bits);
4536 u32 attn_ack = le32_to_cpu(bp->def_status_blk->atten_status_block.
4537 attn_bits_ack);
4538 u32 attn_state = bp->attn_state;
4539
4540 /* look for changed bits */
4541 u32 asserted = attn_bits & ~attn_ack & ~attn_state;
4542 u32 deasserted = ~attn_bits & attn_ack & attn_state;
4543
4544 DP(NETIF_MSG_HW,
4545 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4546 attn_bits, attn_ack, asserted, deasserted);
4547
4548 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state))
4549 BNX2X_ERR("BAD attention state\n");
4550
4551 /* handle bits that were raised */
4552 if (asserted)
4553 bnx2x_attn_int_asserted(bp, asserted);
4554
4555 if (deasserted)
4556 bnx2x_attn_int_deasserted(bp, deasserted);
4557 }
4558
4559 void bnx2x_igu_ack_sb(struct bnx2x *bp, u8 igu_sb_id, u8 segment,
4560 u16 index, u8 op, u8 update)
4561 {
4562 u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8;
4563
4564 bnx2x_igu_ack_sb_gen(bp, igu_sb_id, segment, index, op, update,
4565 igu_addr);
4566 }
4567
4568 static void bnx2x_update_eq_prod(struct bnx2x *bp, u16 prod)
4569 {
4570 /* No memory barriers */
4571 storm_memset_eq_prod(bp, prod, BP_FUNC(bp));
4572 mmiowb(); /* keep prod updates ordered */
4573 }
4574
4575 #ifdef BCM_CNIC
4576 static int bnx2x_cnic_handle_cfc_del(struct bnx2x *bp, u32 cid,
4577 union event_ring_elem *elem)
4578 {
4579 u8 err = elem->message.error;
4580
4581 if (!bp->cnic_eth_dev.starting_cid ||
4582 (cid < bp->cnic_eth_dev.starting_cid &&
4583 cid != bp->cnic_eth_dev.iscsi_l2_cid))
4584 return 1;
4585
4586 DP(BNX2X_MSG_SP, "got delete ramrod for CNIC CID %d\n", cid);
4587
4588 if (unlikely(err)) {
4589
4590 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4591 cid);
4592 bnx2x_panic_dump(bp);
4593 }
4594 bnx2x_cnic_cfc_comp(bp, cid, err);
4595 return 0;
4596 }
4597 #endif
4598
4599 static void bnx2x_handle_mcast_eqe(struct bnx2x *bp)
4600 {
4601 struct bnx2x_mcast_ramrod_params rparam;
4602 int rc;
4603
4604 memset(&rparam, 0, sizeof(rparam));
4605
4606 rparam.mcast_obj = &bp->mcast_obj;
4607
4608 netif_addr_lock_bh(bp->dev);
4609
4610 /* Clear pending state for the last command */
4611 bp->mcast_obj.raw.clear_pending(&bp->mcast_obj.raw);
4612
4613 /* If there are pending mcast commands - send them */
4614 if (bp->mcast_obj.check_pending(&bp->mcast_obj)) {
4615 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_CONT);
4616 if (rc < 0)
4617 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4618 rc);
4619 }
4620
4621 netif_addr_unlock_bh(bp->dev);
4622 }
4623
4624 static void bnx2x_handle_classification_eqe(struct bnx2x *bp,
4625 union event_ring_elem *elem)
4626 {
4627 unsigned long ramrod_flags = 0;
4628 int rc = 0;
4629 u32 cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;
4630 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
4631
4632 /* Always push next commands out, don't wait here */
4633 __set_bit(RAMROD_CONT, &ramrod_flags);
4634
4635 switch (elem->message.data.eth_event.echo >> BNX2X_SWCID_SHIFT) {
4636 case BNX2X_FILTER_MAC_PENDING:
4637 DP(BNX2X_MSG_SP, "Got SETUP_MAC completions\n");
4638 #ifdef BCM_CNIC
4639 if (cid == BNX2X_ISCSI_ETH_CID(bp))
4640 vlan_mac_obj = &bp->iscsi_l2_mac_obj;
4641 else
4642 #endif
4643 vlan_mac_obj = &bp->sp_objs[cid].mac_obj;
4644
4645 break;
4646 case BNX2X_FILTER_MCAST_PENDING:
4647 DP(BNX2X_MSG_SP, "Got SETUP_MCAST completions\n");
4648 /* This is only relevant for 57710 where multicast MACs are
4649 * configured as unicast MACs using the same ramrod.
4650 */
4651 bnx2x_handle_mcast_eqe(bp);
4652 return;
4653 default:
4654 BNX2X_ERR("Unsupported classification command: %d\n",
4655 elem->message.data.eth_event.echo);
4656 return;
4657 }
4658
4659 rc = vlan_mac_obj->complete(bp, vlan_mac_obj, elem, &ramrod_flags);
4660
4661 if (rc < 0)
4662 BNX2X_ERR("Failed to schedule new commands: %d\n", rc);
4663 else if (rc > 0)
4664 DP(BNX2X_MSG_SP, "Scheduled next pending commands...\n");
4665
4666 }
4667
4668 #ifdef BCM_CNIC
4669 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start);
4670 #endif
4671
4672 static void bnx2x_handle_rx_mode_eqe(struct bnx2x *bp)
4673 {
4674 netif_addr_lock_bh(bp->dev);
4675
4676 clear_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
4677
4678 /* Send rx_mode command again if was requested */
4679 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state))
4680 bnx2x_set_storm_rx_mode(bp);
4681 #ifdef BCM_CNIC
4682 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED,
4683 &bp->sp_state))
4684 bnx2x_set_iscsi_eth_rx_mode(bp, true);
4685 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
4686 &bp->sp_state))
4687 bnx2x_set_iscsi_eth_rx_mode(bp, false);
4688 #endif
4689
4690 netif_addr_unlock_bh(bp->dev);
4691 }
4692
4693 static void bnx2x_after_afex_vif_lists(struct bnx2x *bp,
4694 union event_ring_elem *elem)
4695 {
4696 if (elem->message.data.vif_list_event.echo == VIF_LIST_RULE_GET) {
4697 DP(BNX2X_MSG_SP,
4698 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
4699 elem->message.data.vif_list_event.func_bit_map);
4700 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTGET_ACK,
4701 elem->message.data.vif_list_event.func_bit_map);
4702 } else if (elem->message.data.vif_list_event.echo ==
4703 VIF_LIST_RULE_SET) {
4704 DP(BNX2X_MSG_SP, "afex: ramrod completed VIF LIST_SET\n");
4705 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_LISTSET_ACK, 0);
4706 }
4707 }
4708
4709 /* called with rtnl_lock */
4710 static void bnx2x_after_function_update(struct bnx2x *bp)
4711 {
4712 int q, rc;
4713 struct bnx2x_fastpath *fp;
4714 struct bnx2x_queue_state_params queue_params = {NULL};
4715 struct bnx2x_queue_update_params *q_update_params =
4716 &queue_params.params.update;
4717
4718 /* Send Q update command with afex vlan removal values for all Qs */
4719 queue_params.cmd = BNX2X_Q_CMD_UPDATE;
4720
4721 /* set silent vlan removal values according to vlan mode */
4722 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
4723 &q_update_params->update_flags);
4724 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM,
4725 &q_update_params->update_flags);
4726 __set_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4727
4728 /* in access mode mark mask and value are 0 to strip all vlans */
4729 if (bp->afex_vlan_mode == FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE) {
4730 q_update_params->silent_removal_value = 0;
4731 q_update_params->silent_removal_mask = 0;
4732 } else {
4733 q_update_params->silent_removal_value =
4734 (bp->afex_def_vlan_tag & VLAN_VID_MASK);
4735 q_update_params->silent_removal_mask = VLAN_VID_MASK;
4736 }
4737
4738 for_each_eth_queue(bp, q) {
4739 /* Set the appropriate Queue object */
4740 fp = &bp->fp[q];
4741 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4742
4743 /* send the ramrod */
4744 rc = bnx2x_queue_state_change(bp, &queue_params);
4745 if (rc < 0)
4746 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4747 q);
4748 }
4749
4750 #ifdef BCM_CNIC
4751 if (!NO_FCOE(bp)) {
4752 fp = &bp->fp[FCOE_IDX(bp)];
4753 queue_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
4754
4755 /* clear pending completion bit */
4756 __clear_bit(RAMROD_COMP_WAIT, &queue_params.ramrod_flags);
4757
4758 /* mark latest Q bit */
4759 smp_mb__before_clear_bit();
4760 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING, &bp->sp_state);
4761 smp_mb__after_clear_bit();
4762
4763 /* send Q update ramrod for FCoE Q */
4764 rc = bnx2x_queue_state_change(bp, &queue_params);
4765 if (rc < 0)
4766 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
4767 q);
4768 } else {
4769 /* If no FCoE ring - ACK MCP now */
4770 bnx2x_link_report(bp);
4771 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4772 }
4773 #else
4774 /* If no FCoE ring - ACK MCP now */
4775 bnx2x_link_report(bp);
4776 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
4777 #endif /* BCM_CNIC */
4778 }
4779
4780 static struct bnx2x_queue_sp_obj *bnx2x_cid_to_q_obj(
4781 struct bnx2x *bp, u32 cid)
4782 {
4783 DP(BNX2X_MSG_SP, "retrieving fp from cid %d\n", cid);
4784 #ifdef BCM_CNIC
4785 if (cid == BNX2X_FCOE_ETH_CID(bp))
4786 return &bnx2x_fcoe_sp_obj(bp, q_obj);
4787 else
4788 #endif
4789 return &bp->sp_objs[CID_TO_FP(cid, bp)].q_obj;
4790 }
4791
4792 static void bnx2x_eq_int(struct bnx2x *bp)
4793 {
4794 u16 hw_cons, sw_cons, sw_prod;
4795 union event_ring_elem *elem;
4796 u32 cid;
4797 u8 opcode;
4798 int spqe_cnt = 0;
4799 struct bnx2x_queue_sp_obj *q_obj;
4800 struct bnx2x_func_sp_obj *f_obj = &bp->func_obj;
4801 struct bnx2x_raw_obj *rss_raw = &bp->rss_conf_obj.raw;
4802
4803 hw_cons = le16_to_cpu(*bp->eq_cons_sb);
4804
4805 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4806 * when we get the the next-page we nned to adjust so the loop
4807 * condition below will be met. The next element is the size of a
4808 * regular element and hence incrementing by 1
4809 */
4810 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE)
4811 hw_cons++;
4812
4813 /* This function may never run in parallel with itself for a
4814 * specific bp, thus there is no need in "paired" read memory
4815 * barrier here.
4816 */
4817 sw_cons = bp->eq_cons;
4818 sw_prod = bp->eq_prod;
4819
4820 DP(BNX2X_MSG_SP, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4821 hw_cons, sw_cons, atomic_read(&bp->eq_spq_left));
4822
4823 for (; sw_cons != hw_cons;
4824 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) {
4825
4826
4827 elem = &bp->eq_ring[EQ_DESC(sw_cons)];
4828
4829 cid = SW_CID(elem->message.data.cfc_del_event.cid);
4830 opcode = elem->message.opcode;
4831
4832
4833 /* handle eq element */
4834 switch (opcode) {
4835 case EVENT_RING_OPCODE_STAT_QUERY:
4836 DP(BNX2X_MSG_SP | BNX2X_MSG_STATS,
4837 "got statistics comp event %d\n",
4838 bp->stats_comp++);
4839 /* nothing to do with stats comp */
4840 goto next_spqe;
4841
4842 case EVENT_RING_OPCODE_CFC_DEL:
4843 /* handle according to cid range */
4844 /*
4845 * we may want to verify here that the bp state is
4846 * HALTING
4847 */
4848 DP(BNX2X_MSG_SP,
4849 "got delete ramrod for MULTI[%d]\n", cid);
4850 #ifdef BCM_CNIC
4851 if (!bnx2x_cnic_handle_cfc_del(bp, cid, elem))
4852 goto next_spqe;
4853 #endif
4854 q_obj = bnx2x_cid_to_q_obj(bp, cid);
4855
4856 if (q_obj->complete_cmd(bp, q_obj, BNX2X_Q_CMD_CFC_DEL))
4857 break;
4858
4859
4860
4861 goto next_spqe;
4862
4863 case EVENT_RING_OPCODE_STOP_TRAFFIC:
4864 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got STOP TRAFFIC\n");
4865 if (f_obj->complete_cmd(bp, f_obj,
4866 BNX2X_F_CMD_TX_STOP))
4867 break;
4868 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_PAUSED);
4869 goto next_spqe;
4870
4871 case EVENT_RING_OPCODE_START_TRAFFIC:
4872 DP(BNX2X_MSG_SP | BNX2X_MSG_DCB, "got START TRAFFIC\n");
4873 if (f_obj->complete_cmd(bp, f_obj,
4874 BNX2X_F_CMD_TX_START))
4875 break;
4876 bnx2x_dcbx_set_params(bp, BNX2X_DCBX_STATE_TX_RELEASED);
4877 goto next_spqe;
4878 case EVENT_RING_OPCODE_FUNCTION_UPDATE:
4879 DP(BNX2X_MSG_SP | BNX2X_MSG_MCP,
4880 "AFEX: ramrod completed FUNCTION_UPDATE\n");
4881 f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_AFEX_UPDATE);
4882
4883 /* We will perform the Queues update from sp_rtnl task
4884 * as all Queue SP operations should run under
4885 * rtnl_lock.
4886 */
4887 smp_mb__before_clear_bit();
4888 set_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE,
4889 &bp->sp_rtnl_state);
4890 smp_mb__after_clear_bit();
4891
4892 schedule_delayed_work(&bp->sp_rtnl_task, 0);
4893 goto next_spqe;
4894
4895 case EVENT_RING_OPCODE_AFEX_VIF_LISTS:
4896 f_obj->complete_cmd(bp, f_obj,
4897 BNX2X_F_CMD_AFEX_VIFLISTS);
4898 bnx2x_after_afex_vif_lists(bp, elem);
4899 goto next_spqe;
4900 case EVENT_RING_OPCODE_FUNCTION_START:
4901 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4902 "got FUNC_START ramrod\n");
4903 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_START))
4904 break;
4905
4906 goto next_spqe;
4907
4908 case EVENT_RING_OPCODE_FUNCTION_STOP:
4909 DP(BNX2X_MSG_SP | NETIF_MSG_IFUP,
4910 "got FUNC_STOP ramrod\n");
4911 if (f_obj->complete_cmd(bp, f_obj, BNX2X_F_CMD_STOP))
4912 break;
4913
4914 goto next_spqe;
4915 }
4916
4917 switch (opcode | bp->state) {
4918 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4919 BNX2X_STATE_OPEN):
4920 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES |
4921 BNX2X_STATE_OPENING_WAIT4_PORT):
4922 cid = elem->message.data.eth_event.echo &
4923 BNX2X_SWCID_MASK;
4924 DP(BNX2X_MSG_SP, "got RSS_UPDATE ramrod. CID %d\n",
4925 cid);
4926 rss_raw->clear_pending(rss_raw);
4927 break;
4928
4929 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_OPEN):
4930 case (EVENT_RING_OPCODE_SET_MAC | BNX2X_STATE_DIAG):
4931 case (EVENT_RING_OPCODE_SET_MAC |
4932 BNX2X_STATE_CLOSING_WAIT4_HALT):
4933 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4934 BNX2X_STATE_OPEN):
4935 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4936 BNX2X_STATE_DIAG):
4937 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES |
4938 BNX2X_STATE_CLOSING_WAIT4_HALT):
4939 DP(BNX2X_MSG_SP, "got (un)set mac ramrod\n");
4940 bnx2x_handle_classification_eqe(bp, elem);
4941 break;
4942
4943 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4944 BNX2X_STATE_OPEN):
4945 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4946 BNX2X_STATE_DIAG):
4947 case (EVENT_RING_OPCODE_MULTICAST_RULES |
4948 BNX2X_STATE_CLOSING_WAIT4_HALT):
4949 DP(BNX2X_MSG_SP, "got mcast ramrod\n");
4950 bnx2x_handle_mcast_eqe(bp);
4951 break;
4952
4953 case (EVENT_RING_OPCODE_FILTERS_RULES |
4954 BNX2X_STATE_OPEN):
4955 case (EVENT_RING_OPCODE_FILTERS_RULES |
4956 BNX2X_STATE_DIAG):
4957 case (EVENT_RING_OPCODE_FILTERS_RULES |
4958 BNX2X_STATE_CLOSING_WAIT4_HALT):
4959 DP(BNX2X_MSG_SP, "got rx_mode ramrod\n");
4960 bnx2x_handle_rx_mode_eqe(bp);
4961 break;
4962 default:
4963 /* unknown event log error and continue */
4964 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4965 elem->message.opcode, bp->state);
4966 }
4967 next_spqe:
4968 spqe_cnt++;
4969 } /* for */
4970
4971 smp_mb__before_atomic_inc();
4972 atomic_add(spqe_cnt, &bp->eq_spq_left);
4973
4974 bp->eq_cons = sw_cons;
4975 bp->eq_prod = sw_prod;
4976 /* Make sure that above mem writes were issued towards the memory */
4977 smp_wmb();
4978
4979 /* update producer */
4980 bnx2x_update_eq_prod(bp, bp->eq_prod);
4981 }
4982
4983 static void bnx2x_sp_task(struct work_struct *work)
4984 {
4985 struct bnx2x *bp = container_of(work, struct bnx2x, sp_task.work);
4986 u16 status;
4987
4988 status = bnx2x_update_dsb_idx(bp);
4989 /* if (status == 0) */
4990 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4991
4992 DP(BNX2X_MSG_SP, "got a slowpath interrupt (status 0x%x)\n", status);
4993
4994 /* HW attentions */
4995 if (status & BNX2X_DEF_SB_ATT_IDX) {
4996 bnx2x_attn_int(bp);
4997 status &= ~BNX2X_DEF_SB_ATT_IDX;
4998 }
4999
5000 /* SP events: STAT_QUERY and others */
5001 if (status & BNX2X_DEF_SB_IDX) {
5002 #ifdef BCM_CNIC
5003 struct bnx2x_fastpath *fp = bnx2x_fcoe_fp(bp);
5004
5005 if ((!NO_FCOE(bp)) &&
5006 (bnx2x_has_rx_work(fp) || bnx2x_has_tx_work(fp))) {
5007 /*
5008 * Prevent local bottom-halves from running as
5009 * we are going to change the local NAPI list.
5010 */
5011 local_bh_disable();
5012 napi_schedule(&bnx2x_fcoe(bp, napi));
5013 local_bh_enable();
5014 }
5015 #endif
5016 /* Handle EQ completions */
5017 bnx2x_eq_int(bp);
5018
5019 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID,
5020 le16_to_cpu(bp->def_idx), IGU_INT_NOP, 1);
5021
5022 status &= ~BNX2X_DEF_SB_IDX;
5023 }
5024
5025 if (unlikely(status))
5026 DP(BNX2X_MSG_SP, "got an unknown interrupt! (status 0x%x)\n",
5027 status);
5028
5029 bnx2x_ack_sb(bp, bp->igu_dsb_id, ATTENTION_ID,
5030 le16_to_cpu(bp->def_att_idx), IGU_INT_ENABLE, 1);
5031
5032 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5033 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK,
5034 &bp->sp_state)) {
5035 bnx2x_link_report(bp);
5036 bnx2x_fw_command(bp, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0);
5037 }
5038 }
5039
5040 irqreturn_t bnx2x_msix_sp_int(int irq, void *dev_instance)
5041 {
5042 struct net_device *dev = dev_instance;
5043 struct bnx2x *bp = netdev_priv(dev);
5044
5045 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0,
5046 IGU_INT_DISABLE, 0);
5047
5048 #ifdef BNX2X_STOP_ON_ERROR
5049 if (unlikely(bp->panic))
5050 return IRQ_HANDLED;
5051 #endif
5052
5053 #ifdef BCM_CNIC
5054 {
5055 struct cnic_ops *c_ops;
5056
5057 rcu_read_lock();
5058 c_ops = rcu_dereference(bp->cnic_ops);
5059 if (c_ops)
5060 c_ops->cnic_handler(bp->cnic_data, NULL);
5061 rcu_read_unlock();
5062 }
5063 #endif
5064 queue_delayed_work(bnx2x_wq, &bp->sp_task, 0);
5065
5066 return IRQ_HANDLED;
5067 }
5068
5069 /* end of slow path */
5070
5071
5072 void bnx2x_drv_pulse(struct bnx2x *bp)
5073 {
5074 SHMEM_WR(bp, func_mb[BP_FW_MB_IDX(bp)].drv_pulse_mb,
5075 bp->fw_drv_pulse_wr_seq);
5076 }
5077
5078
5079 static void bnx2x_timer(unsigned long data)
5080 {
5081 struct bnx2x *bp = (struct bnx2x *) data;
5082
5083 if (!netif_running(bp->dev))
5084 return;
5085
5086 if (!BP_NOMCP(bp)) {
5087 int mb_idx = BP_FW_MB_IDX(bp);
5088 u32 drv_pulse;
5089 u32 mcp_pulse;
5090
5091 ++bp->fw_drv_pulse_wr_seq;
5092 bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
5093 /* TBD - add SYSTEM_TIME */
5094 drv_pulse = bp->fw_drv_pulse_wr_seq;
5095 bnx2x_drv_pulse(bp);
5096
5097 mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
5098 MCP_PULSE_SEQ_MASK);
5099 /* The delta between driver pulse and mcp response
5100 * should be 1 (before mcp response) or 0 (after mcp response)
5101 */
5102 if ((drv_pulse != mcp_pulse) &&
5103 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
5104 /* someone lost a heartbeat... */
5105 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5106 drv_pulse, mcp_pulse);
5107 }
5108 }
5109
5110 if (bp->state == BNX2X_STATE_OPEN)
5111 bnx2x_stats_handle(bp, STATS_EVENT_UPDATE);
5112
5113 mod_timer(&bp->timer, jiffies + bp->current_interval);
5114 }
5115
5116 /* end of Statistics */
5117
5118 /* nic init */
5119
5120 /*
5121 * nic init service functions
5122 */
5123
5124 static void bnx2x_fill(struct bnx2x *bp, u32 addr, int fill, u32 len)
5125 {
5126 u32 i;
5127 if (!(len%4) && !(addr%4))
5128 for (i = 0; i < len; i += 4)
5129 REG_WR(bp, addr + i, fill);
5130 else
5131 for (i = 0; i < len; i++)
5132 REG_WR8(bp, addr + i, fill);
5133
5134 }
5135
5136 /* helper: writes FP SP data to FW - data_size in dwords */
5137 static void bnx2x_wr_fp_sb_data(struct bnx2x *bp,
5138 int fw_sb_id,
5139 u32 *sb_data_p,
5140 u32 data_size)
5141 {
5142 int index;
5143 for (index = 0; index < data_size; index++)
5144 REG_WR(bp, BAR_CSTRORM_INTMEM +
5145 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) +
5146 sizeof(u32)*index,
5147 *(sb_data_p + index));
5148 }
5149
5150 static void bnx2x_zero_fp_sb(struct bnx2x *bp, int fw_sb_id)
5151 {
5152 u32 *sb_data_p;
5153 u32 data_size = 0;
5154 struct hc_status_block_data_e2 sb_data_e2;
5155 struct hc_status_block_data_e1x sb_data_e1x;
5156
5157 /* disable the function first */
5158 if (!CHIP_IS_E1x(bp)) {
5159 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5160 sb_data_e2.common.state = SB_DISABLED;
5161 sb_data_e2.common.p_func.vf_valid = false;
5162 sb_data_p = (u32 *)&sb_data_e2;
5163 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5164 } else {
5165 memset(&sb_data_e1x, 0,
5166 sizeof(struct hc_status_block_data_e1x));
5167 sb_data_e1x.common.state = SB_DISABLED;
5168 sb_data_e1x.common.p_func.vf_valid = false;
5169 sb_data_p = (u32 *)&sb_data_e1x;
5170 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5171 }
5172 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5173
5174 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5175 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id), 0,
5176 CSTORM_STATUS_BLOCK_SIZE);
5177 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5178 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id), 0,
5179 CSTORM_SYNC_BLOCK_SIZE);
5180 }
5181
5182 /* helper: writes SP SB data to FW */
5183 static void bnx2x_wr_sp_sb_data(struct bnx2x *bp,
5184 struct hc_sp_status_block_data *sp_sb_data)
5185 {
5186 int func = BP_FUNC(bp);
5187 int i;
5188 for (i = 0; i < sizeof(struct hc_sp_status_block_data)/sizeof(u32); i++)
5189 REG_WR(bp, BAR_CSTRORM_INTMEM +
5190 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func) +
5191 i*sizeof(u32),
5192 *((u32 *)sp_sb_data + i));
5193 }
5194
5195 static void bnx2x_zero_sp_sb(struct bnx2x *bp)
5196 {
5197 int func = BP_FUNC(bp);
5198 struct hc_sp_status_block_data sp_sb_data;
5199 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5200
5201 sp_sb_data.state = SB_DISABLED;
5202 sp_sb_data.p_func.vf_valid = false;
5203
5204 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5205
5206 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5207 CSTORM_SP_STATUS_BLOCK_OFFSET(func), 0,
5208 CSTORM_SP_STATUS_BLOCK_SIZE);
5209 bnx2x_fill(bp, BAR_CSTRORM_INTMEM +
5210 CSTORM_SP_SYNC_BLOCK_OFFSET(func), 0,
5211 CSTORM_SP_SYNC_BLOCK_SIZE);
5212
5213 }
5214
5215
5216 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm,
5217 int igu_sb_id, int igu_seg_id)
5218 {
5219 hc_sm->igu_sb_id = igu_sb_id;
5220 hc_sm->igu_seg_id = igu_seg_id;
5221 hc_sm->timer_value = 0xFF;
5222 hc_sm->time_to_expire = 0xFFFFFFFF;
5223 }
5224
5225
5226 /* allocates state machine ids. */
5227 static void bnx2x_map_sb_state_machines(struct hc_index_data *index_data)
5228 {
5229 /* zero out state machine indices */
5230 /* rx indices */
5231 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5232
5233 /* tx indices */
5234 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID;
5235 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID;
5236 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID;
5237 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID;
5238
5239 /* map indices */
5240 /* rx indices */
5241 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |=
5242 SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5243
5244 /* tx indices */
5245 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |=
5246 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5247 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |=
5248 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5249 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |=
5250 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5251 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |=
5252 SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT;
5253 }
5254
5255 static void bnx2x_init_sb(struct bnx2x *bp, dma_addr_t mapping, int vfid,
5256 u8 vf_valid, int fw_sb_id, int igu_sb_id)
5257 {
5258 int igu_seg_id;
5259
5260 struct hc_status_block_data_e2 sb_data_e2;
5261 struct hc_status_block_data_e1x sb_data_e1x;
5262 struct hc_status_block_sm *hc_sm_p;
5263 int data_size;
5264 u32 *sb_data_p;
5265
5266 if (CHIP_INT_MODE_IS_BC(bp))
5267 igu_seg_id = HC_SEG_ACCESS_NORM;
5268 else
5269 igu_seg_id = IGU_SEG_ACCESS_NORM;
5270
5271 bnx2x_zero_fp_sb(bp, fw_sb_id);
5272
5273 if (!CHIP_IS_E1x(bp)) {
5274 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2));
5275 sb_data_e2.common.state = SB_ENABLED;
5276 sb_data_e2.common.p_func.pf_id = BP_FUNC(bp);
5277 sb_data_e2.common.p_func.vf_id = vfid;
5278 sb_data_e2.common.p_func.vf_valid = vf_valid;
5279 sb_data_e2.common.p_func.vnic_id = BP_VN(bp);
5280 sb_data_e2.common.same_igu_sb_1b = true;
5281 sb_data_e2.common.host_sb_addr.hi = U64_HI(mapping);
5282 sb_data_e2.common.host_sb_addr.lo = U64_LO(mapping);
5283 hc_sm_p = sb_data_e2.common.state_machine;
5284 sb_data_p = (u32 *)&sb_data_e2;
5285 data_size = sizeof(struct hc_status_block_data_e2)/sizeof(u32);
5286 bnx2x_map_sb_state_machines(sb_data_e2.index_data);
5287 } else {
5288 memset(&sb_data_e1x, 0,
5289 sizeof(struct hc_status_block_data_e1x));
5290 sb_data_e1x.common.state = SB_ENABLED;
5291 sb_data_e1x.common.p_func.pf_id = BP_FUNC(bp);
5292 sb_data_e1x.common.p_func.vf_id = 0xff;
5293 sb_data_e1x.common.p_func.vf_valid = false;
5294 sb_data_e1x.common.p_func.vnic_id = BP_VN(bp);
5295 sb_data_e1x.common.same_igu_sb_1b = true;
5296 sb_data_e1x.common.host_sb_addr.hi = U64_HI(mapping);
5297 sb_data_e1x.common.host_sb_addr.lo = U64_LO(mapping);
5298 hc_sm_p = sb_data_e1x.common.state_machine;
5299 sb_data_p = (u32 *)&sb_data_e1x;
5300 data_size = sizeof(struct hc_status_block_data_e1x)/sizeof(u32);
5301 bnx2x_map_sb_state_machines(sb_data_e1x.index_data);
5302 }
5303
5304 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID],
5305 igu_sb_id, igu_seg_id);
5306 bnx2x_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID],
5307 igu_sb_id, igu_seg_id);
5308
5309 DP(NETIF_MSG_IFUP, "Init FW SB %d\n", fw_sb_id);
5310
5311 /* write indecies to HW */
5312 bnx2x_wr_fp_sb_data(bp, fw_sb_id, sb_data_p, data_size);
5313 }
5314
5315 static void bnx2x_update_coalesce_sb(struct bnx2x *bp, u8 fw_sb_id,
5316 u16 tx_usec, u16 rx_usec)
5317 {
5318 bnx2x_update_coalesce_sb_index(bp, fw_sb_id, HC_INDEX_ETH_RX_CQ_CONS,
5319 false, rx_usec);
5320 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5321 HC_INDEX_ETH_TX_CQ_CONS_COS0, false,
5322 tx_usec);
5323 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5324 HC_INDEX_ETH_TX_CQ_CONS_COS1, false,
5325 tx_usec);
5326 bnx2x_update_coalesce_sb_index(bp, fw_sb_id,
5327 HC_INDEX_ETH_TX_CQ_CONS_COS2, false,
5328 tx_usec);
5329 }
5330
5331 static void bnx2x_init_def_sb(struct bnx2x *bp)
5332 {
5333 struct host_sp_status_block *def_sb = bp->def_status_blk;
5334 dma_addr_t mapping = bp->def_status_blk_mapping;
5335 int igu_sp_sb_index;
5336 int igu_seg_id;
5337 int port = BP_PORT(bp);
5338 int func = BP_FUNC(bp);
5339 int reg_offset, reg_offset_en5;
5340 u64 section;
5341 int index;
5342 struct hc_sp_status_block_data sp_sb_data;
5343 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data));
5344
5345 if (CHIP_INT_MODE_IS_BC(bp)) {
5346 igu_sp_sb_index = DEF_SB_IGU_ID;
5347 igu_seg_id = HC_SEG_ACCESS_DEF;
5348 } else {
5349 igu_sp_sb_index = bp->igu_dsb_id;
5350 igu_seg_id = IGU_SEG_ACCESS_DEF;
5351 }
5352
5353 /* ATTN */
5354 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5355 atten_status_block);
5356 def_sb->atten_status_block.status_block_id = igu_sp_sb_index;
5357
5358 bp->attn_state = 0;
5359
5360 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
5361 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
5362 reg_offset_en5 = (port ? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 :
5363 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0);
5364 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) {
5365 int sindex;
5366 /* take care of sig[0]..sig[4] */
5367 for (sindex = 0; sindex < 4; sindex++)
5368 bp->attn_group[index].sig[sindex] =
5369 REG_RD(bp, reg_offset + sindex*0x4 + 0x10*index);
5370
5371 if (!CHIP_IS_E1x(bp))
5372 /*
5373 * enable5 is separate from the rest of the registers,
5374 * and therefore the address skip is 4
5375 * and not 16 between the different groups
5376 */
5377 bp->attn_group[index].sig[4] = REG_RD(bp,
5378 reg_offset_en5 + 0x4*index);
5379 else
5380 bp->attn_group[index].sig[4] = 0;
5381 }
5382
5383 if (bp->common.int_block == INT_BLOCK_HC) {
5384 reg_offset = (port ? HC_REG_ATTN_MSG1_ADDR_L :
5385 HC_REG_ATTN_MSG0_ADDR_L);
5386
5387 REG_WR(bp, reg_offset, U64_LO(section));
5388 REG_WR(bp, reg_offset + 4, U64_HI(section));
5389 } else if (!CHIP_IS_E1x(bp)) {
5390 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section));
5391 REG_WR(bp, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section));
5392 }
5393
5394 section = ((u64)mapping) + offsetof(struct host_sp_status_block,
5395 sp_sb);
5396
5397 bnx2x_zero_sp_sb(bp);
5398
5399 sp_sb_data.state = SB_ENABLED;
5400 sp_sb_data.host_sb_addr.lo = U64_LO(section);
5401 sp_sb_data.host_sb_addr.hi = U64_HI(section);
5402 sp_sb_data.igu_sb_id = igu_sp_sb_index;
5403 sp_sb_data.igu_seg_id = igu_seg_id;
5404 sp_sb_data.p_func.pf_id = func;
5405 sp_sb_data.p_func.vnic_id = BP_VN(bp);
5406 sp_sb_data.p_func.vf_id = 0xff;
5407
5408 bnx2x_wr_sp_sb_data(bp, &sp_sb_data);
5409
5410 bnx2x_ack_sb(bp, bp->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0);
5411 }
5412
5413 void bnx2x_update_coalesce(struct bnx2x *bp)
5414 {
5415 int i;
5416
5417 for_each_eth_queue(bp, i)
5418 bnx2x_update_coalesce_sb(bp, bp->fp[i].fw_sb_id,
5419 bp->tx_ticks, bp->rx_ticks);
5420 }
5421
5422 static void bnx2x_init_sp_ring(struct bnx2x *bp)
5423 {
5424 spin_lock_init(&bp->spq_lock);
5425 atomic_set(&bp->cq_spq_left, MAX_SPQ_PENDING);
5426
5427 bp->spq_prod_idx = 0;
5428 bp->dsb_sp_prod = BNX2X_SP_DSB_INDEX;
5429 bp->spq_prod_bd = bp->spq;
5430 bp->spq_last_bd = bp->spq_prod_bd + MAX_SP_DESC_CNT;
5431 }
5432
5433 static void bnx2x_init_eq_ring(struct bnx2x *bp)
5434 {
5435 int i;
5436 for (i = 1; i <= NUM_EQ_PAGES; i++) {
5437 union event_ring_elem *elem =
5438 &bp->eq_ring[EQ_DESC_CNT_PAGE * i - 1];
5439
5440 elem->next_page.addr.hi =
5441 cpu_to_le32(U64_HI(bp->eq_mapping +
5442 BCM_PAGE_SIZE * (i % NUM_EQ_PAGES)));
5443 elem->next_page.addr.lo =
5444 cpu_to_le32(U64_LO(bp->eq_mapping +
5445 BCM_PAGE_SIZE*(i % NUM_EQ_PAGES)));
5446 }
5447 bp->eq_cons = 0;
5448 bp->eq_prod = NUM_EQ_DESC;
5449 bp->eq_cons_sb = BNX2X_EQ_INDEX;
5450 /* we want a warning message before it gets rought... */
5451 atomic_set(&bp->eq_spq_left,
5452 min_t(int, MAX_SP_DESC_CNT - MAX_SPQ_PENDING, NUM_EQ_DESC) - 1);
5453 }
5454
5455
5456 /* called with netif_addr_lock_bh() */
5457 void bnx2x_set_q_rx_mode(struct bnx2x *bp, u8 cl_id,
5458 unsigned long rx_mode_flags,
5459 unsigned long rx_accept_flags,
5460 unsigned long tx_accept_flags,
5461 unsigned long ramrod_flags)
5462 {
5463 struct bnx2x_rx_mode_ramrod_params ramrod_param;
5464 int rc;
5465
5466 memset(&ramrod_param, 0, sizeof(ramrod_param));
5467
5468 /* Prepare ramrod parameters */
5469 ramrod_param.cid = 0;
5470 ramrod_param.cl_id = cl_id;
5471 ramrod_param.rx_mode_obj = &bp->rx_mode_obj;
5472 ramrod_param.func_id = BP_FUNC(bp);
5473
5474 ramrod_param.pstate = &bp->sp_state;
5475 ramrod_param.state = BNX2X_FILTER_RX_MODE_PENDING;
5476
5477 ramrod_param.rdata = bnx2x_sp(bp, rx_mode_rdata);
5478 ramrod_param.rdata_mapping = bnx2x_sp_mapping(bp, rx_mode_rdata);
5479
5480 set_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state);
5481
5482 ramrod_param.ramrod_flags = ramrod_flags;
5483 ramrod_param.rx_mode_flags = rx_mode_flags;
5484
5485 ramrod_param.rx_accept_flags = rx_accept_flags;
5486 ramrod_param.tx_accept_flags = tx_accept_flags;
5487
5488 rc = bnx2x_config_rx_mode(bp, &ramrod_param);
5489 if (rc < 0) {
5490 BNX2X_ERR("Set rx_mode %d failed\n", bp->rx_mode);
5491 return;
5492 }
5493 }
5494
5495 /* called with netif_addr_lock_bh() */
5496 void bnx2x_set_storm_rx_mode(struct bnx2x *bp)
5497 {
5498 unsigned long rx_mode_flags = 0, ramrod_flags = 0;
5499 unsigned long rx_accept_flags = 0, tx_accept_flags = 0;
5500
5501 #ifdef BCM_CNIC
5502 if (!NO_FCOE(bp))
5503
5504 /* Configure rx_mode of FCoE Queue */
5505 __set_bit(BNX2X_RX_MODE_FCOE_ETH, &rx_mode_flags);
5506 #endif
5507
5508 switch (bp->rx_mode) {
5509 case BNX2X_RX_MODE_NONE:
5510 /*
5511 * 'drop all' supersedes any accept flags that may have been
5512 * passed to the function.
5513 */
5514 break;
5515 case BNX2X_RX_MODE_NORMAL:
5516 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5517 __set_bit(BNX2X_ACCEPT_MULTICAST, &rx_accept_flags);
5518 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5519
5520 /* internal switching mode */
5521 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5522 __set_bit(BNX2X_ACCEPT_MULTICAST, &tx_accept_flags);
5523 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5524
5525 break;
5526 case BNX2X_RX_MODE_ALLMULTI:
5527 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5528 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5529 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5530
5531 /* internal switching mode */
5532 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5533 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5534 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5535
5536 break;
5537 case BNX2X_RX_MODE_PROMISC:
5538 /* According to deffinition of SI mode, iface in promisc mode
5539 * should receive matched and unmatched (in resolution of port)
5540 * unicast packets.
5541 */
5542 __set_bit(BNX2X_ACCEPT_UNMATCHED, &rx_accept_flags);
5543 __set_bit(BNX2X_ACCEPT_UNICAST, &rx_accept_flags);
5544 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &rx_accept_flags);
5545 __set_bit(BNX2X_ACCEPT_BROADCAST, &rx_accept_flags);
5546
5547 /* internal switching mode */
5548 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &tx_accept_flags);
5549 __set_bit(BNX2X_ACCEPT_BROADCAST, &tx_accept_flags);
5550
5551 if (IS_MF_SI(bp))
5552 __set_bit(BNX2X_ACCEPT_ALL_UNICAST, &tx_accept_flags);
5553 else
5554 __set_bit(BNX2X_ACCEPT_UNICAST, &tx_accept_flags);
5555
5556 break;
5557 default:
5558 BNX2X_ERR("Unknown rx_mode: %d\n", bp->rx_mode);
5559 return;
5560 }
5561
5562 if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
5563 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &rx_accept_flags);
5564 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &tx_accept_flags);
5565 }
5566
5567 __set_bit(RAMROD_RX, &ramrod_flags);
5568 __set_bit(RAMROD_TX, &ramrod_flags);
5569
5570 bnx2x_set_q_rx_mode(bp, bp->fp->cl_id, rx_mode_flags, rx_accept_flags,
5571 tx_accept_flags, ramrod_flags);
5572 }
5573
5574 static void bnx2x_init_internal_common(struct bnx2x *bp)
5575 {
5576 int i;
5577
5578 if (IS_MF_SI(bp))
5579 /*
5580 * In switch independent mode, the TSTORM needs to accept
5581 * packets that failed classification, since approximate match
5582 * mac addresses aren't written to NIG LLH
5583 */
5584 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5585 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 2);
5586 else if (!CHIP_IS_E1(bp)) /* 57710 doesn't support MF */
5587 REG_WR8(bp, BAR_TSTRORM_INTMEM +
5588 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET, 0);
5589
5590 /* Zero this manually as its initialization is
5591 currently missing in the initTool */
5592 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++)
5593 REG_WR(bp, BAR_USTRORM_INTMEM +
5594 USTORM_AGG_DATA_OFFSET + i * 4, 0);
5595 if (!CHIP_IS_E1x(bp)) {
5596 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET,
5597 CHIP_INT_MODE_IS_BC(bp) ?
5598 HC_IGU_BC_MODE : HC_IGU_NBC_MODE);
5599 }
5600 }
5601
5602 static void bnx2x_init_internal(struct bnx2x *bp, u32 load_code)
5603 {
5604 switch (load_code) {
5605 case FW_MSG_CODE_DRV_LOAD_COMMON:
5606 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP:
5607 bnx2x_init_internal_common(bp);
5608 /* no break */
5609
5610 case FW_MSG_CODE_DRV_LOAD_PORT:
5611 /* nothing to do */
5612 /* no break */
5613
5614 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
5615 /* internal memory per function is
5616 initialized inside bnx2x_pf_init */
5617 break;
5618
5619 default:
5620 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code);
5621 break;
5622 }
5623 }
5624
5625 static inline u8 bnx2x_fp_igu_sb_id(struct bnx2x_fastpath *fp)
5626 {
5627 return fp->bp->igu_base_sb + fp->index + CNIC_PRESENT;
5628 }
5629
5630 static inline u8 bnx2x_fp_fw_sb_id(struct bnx2x_fastpath *fp)
5631 {
5632 return fp->bp->base_fw_ndsb + fp->index + CNIC_PRESENT;
5633 }
5634
5635 static u8 bnx2x_fp_cl_id(struct bnx2x_fastpath *fp)
5636 {
5637 if (CHIP_IS_E1x(fp->bp))
5638 return BP_L_ID(fp->bp) + fp->index;
5639 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5640 return bnx2x_fp_igu_sb_id(fp);
5641 }
5642
5643 static void bnx2x_init_eth_fp(struct bnx2x *bp, int fp_idx)
5644 {
5645 struct bnx2x_fastpath *fp = &bp->fp[fp_idx];
5646 u8 cos;
5647 unsigned long q_type = 0;
5648 u32 cids[BNX2X_MULTI_TX_COS] = { 0 };
5649 fp->rx_queue = fp_idx;
5650 fp->cid = fp_idx;
5651 fp->cl_id = bnx2x_fp_cl_id(fp);
5652 fp->fw_sb_id = bnx2x_fp_fw_sb_id(fp);
5653 fp->igu_sb_id = bnx2x_fp_igu_sb_id(fp);
5654 /* qZone id equals to FW (per path) client id */
5655 fp->cl_qzone_id = bnx2x_fp_qzone_id(fp);
5656
5657 /* init shortcut */
5658 fp->ustorm_rx_prods_offset = bnx2x_rx_ustorm_prods_offset(fp);
5659
5660 /* Setup SB indicies */
5661 fp->rx_cons_sb = BNX2X_RX_SB_INDEX;
5662
5663 /* Configure Queue State object */
5664 __set_bit(BNX2X_Q_TYPE_HAS_RX, &q_type);
5665 __set_bit(BNX2X_Q_TYPE_HAS_TX, &q_type);
5666
5667 BUG_ON(fp->max_cos > BNX2X_MULTI_TX_COS);
5668
5669 /* init tx data */
5670 for_each_cos_in_tx_queue(fp, cos) {
5671 bnx2x_init_txdata(bp, fp->txdata_ptr[cos],
5672 CID_COS_TO_TX_ONLY_CID(fp->cid, cos, bp),
5673 FP_COS_TO_TXQ(fp, cos, bp),
5674 BNX2X_TX_SB_INDEX_BASE + cos, fp);
5675 cids[cos] = fp->txdata_ptr[cos]->cid;
5676 }
5677
5678 bnx2x_init_queue_obj(bp, &bnx2x_sp_obj(bp, fp).q_obj, fp->cl_id, cids,
5679 fp->max_cos, BP_FUNC(bp), bnx2x_sp(bp, q_rdata),
5680 bnx2x_sp_mapping(bp, q_rdata), q_type);
5681
5682 /**
5683 * Configure classification DBs: Always enable Tx switching
5684 */
5685 bnx2x_init_vlan_mac_fp_objs(fp, BNX2X_OBJ_TYPE_RX_TX);
5686
5687 DP(NETIF_MSG_IFUP, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5688 fp_idx, bp, fp->status_blk.e2_sb, fp->cl_id, fp->fw_sb_id,
5689 fp->igu_sb_id);
5690 bnx2x_init_sb(bp, fp->status_blk_mapping, BNX2X_VF_ID_INVALID, false,
5691 fp->fw_sb_id, fp->igu_sb_id);
5692
5693 bnx2x_update_fpsb_idx(fp);
5694 }
5695
5696 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata *txdata)
5697 {
5698 int i;
5699
5700 for (i = 1; i <= NUM_TX_RINGS; i++) {
5701 struct eth_tx_next_bd *tx_next_bd =
5702 &txdata->tx_desc_ring[TX_DESC_CNT * i - 1].next_bd;
5703
5704 tx_next_bd->addr_hi =
5705 cpu_to_le32(U64_HI(txdata->tx_desc_mapping +
5706 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5707 tx_next_bd->addr_lo =
5708 cpu_to_le32(U64_LO(txdata->tx_desc_mapping +
5709 BCM_PAGE_SIZE*(i % NUM_TX_RINGS)));
5710 }
5711
5712 SET_FLAG(txdata->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1);
5713 txdata->tx_db.data.zero_fill1 = 0;
5714 txdata->tx_db.data.prod = 0;
5715
5716 txdata->tx_pkt_prod = 0;
5717 txdata->tx_pkt_cons = 0;
5718 txdata->tx_bd_prod = 0;
5719 txdata->tx_bd_cons = 0;
5720 txdata->tx_pkt = 0;
5721 }
5722
5723 static void bnx2x_init_tx_rings(struct bnx2x *bp)
5724 {
5725 int i;
5726 u8 cos;
5727
5728 for_each_tx_queue(bp, i)
5729 for_each_cos_in_tx_queue(&bp->fp[i], cos)
5730 bnx2x_init_tx_ring_one(bp->fp[i].txdata_ptr[cos]);
5731 }
5732
5733 void bnx2x_nic_init(struct bnx2x *bp, u32 load_code)
5734 {
5735 int i;
5736
5737 for_each_eth_queue(bp, i)
5738 bnx2x_init_eth_fp(bp, i);
5739 #ifdef BCM_CNIC
5740 if (!NO_FCOE(bp))
5741 bnx2x_init_fcoe_fp(bp);
5742
5743 bnx2x_init_sb(bp, bp->cnic_sb_mapping,
5744 BNX2X_VF_ID_INVALID, false,
5745 bnx2x_cnic_fw_sb_id(bp), bnx2x_cnic_igu_sb_id(bp));
5746
5747 #endif
5748
5749 /* Initialize MOD_ABS interrupts */
5750 bnx2x_init_mod_abs_int(bp, &bp->link_vars, bp->common.chip_id,
5751 bp->common.shmem_base, bp->common.shmem2_base,
5752 BP_PORT(bp));
5753 /* ensure status block indices were read */
5754 rmb();
5755
5756 bnx2x_init_def_sb(bp);
5757 bnx2x_update_dsb_idx(bp);
5758 bnx2x_init_rx_rings(bp);
5759 bnx2x_init_tx_rings(bp);
5760 bnx2x_init_sp_ring(bp);
5761 bnx2x_init_eq_ring(bp);
5762 bnx2x_init_internal(bp, load_code);
5763 bnx2x_pf_init(bp);
5764 bnx2x_stats_init(bp);
5765
5766 /* flush all before enabling interrupts */
5767 mb();
5768 mmiowb();
5769
5770 bnx2x_int_enable(bp);
5771
5772 /* Check for SPIO5 */
5773 bnx2x_attn_int_deasserted0(bp,
5774 REG_RD(bp, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + BP_PORT(bp)*4) &
5775 AEU_INPUTS_ATTN_BITS_SPIO5);
5776 }
5777
5778 /* end of nic init */
5779
5780 /*
5781 * gzip service functions
5782 */
5783
5784 static int bnx2x_gunzip_init(struct bnx2x *bp)
5785 {
5786 bp->gunzip_buf = dma_alloc_coherent(&bp->pdev->dev, FW_BUF_SIZE,
5787 &bp->gunzip_mapping, GFP_KERNEL);
5788 if (bp->gunzip_buf == NULL)
5789 goto gunzip_nomem1;
5790
5791 bp->strm = kmalloc(sizeof(*bp->strm), GFP_KERNEL);
5792 if (bp->strm == NULL)
5793 goto gunzip_nomem2;
5794
5795 bp->strm->workspace = vmalloc(zlib_inflate_workspacesize());
5796 if (bp->strm->workspace == NULL)
5797 goto gunzip_nomem3;
5798
5799 return 0;
5800
5801 gunzip_nomem3:
5802 kfree(bp->strm);
5803 bp->strm = NULL;
5804
5805 gunzip_nomem2:
5806 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5807 bp->gunzip_mapping);
5808 bp->gunzip_buf = NULL;
5809
5810 gunzip_nomem1:
5811 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5812 return -ENOMEM;
5813 }
5814
5815 static void bnx2x_gunzip_end(struct bnx2x *bp)
5816 {
5817 if (bp->strm) {
5818 vfree(bp->strm->workspace);
5819 kfree(bp->strm);
5820 bp->strm = NULL;
5821 }
5822
5823 if (bp->gunzip_buf) {
5824 dma_free_coherent(&bp->pdev->dev, FW_BUF_SIZE, bp->gunzip_buf,
5825 bp->gunzip_mapping);
5826 bp->gunzip_buf = NULL;
5827 }
5828 }
5829
5830 static int bnx2x_gunzip(struct bnx2x *bp, const u8 *zbuf, int len)
5831 {
5832 int n, rc;
5833
5834 /* check gzip header */
5835 if ((zbuf[0] != 0x1f) || (zbuf[1] != 0x8b) || (zbuf[2] != Z_DEFLATED)) {
5836 BNX2X_ERR("Bad gzip header\n");
5837 return -EINVAL;
5838 }
5839
5840 n = 10;
5841
5842 #define FNAME 0x8
5843
5844 if (zbuf[3] & FNAME)
5845 while ((zbuf[n++] != 0) && (n < len));
5846
5847 bp->strm->next_in = (typeof(bp->strm->next_in))zbuf + n;
5848 bp->strm->avail_in = len - n;
5849 bp->strm->next_out = bp->gunzip_buf;
5850 bp->strm->avail_out = FW_BUF_SIZE;
5851
5852 rc = zlib_inflateInit2(bp->strm, -MAX_WBITS);
5853 if (rc != Z_OK)
5854 return rc;
5855
5856 rc = zlib_inflate(bp->strm, Z_FINISH);
5857 if ((rc != Z_OK) && (rc != Z_STREAM_END))
5858 netdev_err(bp->dev, "Firmware decompression error: %s\n",
5859 bp->strm->msg);
5860
5861 bp->gunzip_outlen = (FW_BUF_SIZE - bp->strm->avail_out);
5862 if (bp->gunzip_outlen & 0x3)
5863 netdev_err(bp->dev,
5864 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5865 bp->gunzip_outlen);
5866 bp->gunzip_outlen >>= 2;
5867
5868 zlib_inflateEnd(bp->strm);
5869
5870 if (rc == Z_STREAM_END)
5871 return 0;
5872
5873 return rc;
5874 }
5875
5876 /* nic load/unload */
5877
5878 /*
5879 * General service functions
5880 */
5881
5882 /* send a NIG loopback debug packet */
5883 static void bnx2x_lb_pckt(struct bnx2x *bp)
5884 {
5885 u32 wb_write[3];
5886
5887 /* Ethernet source and destination addresses */
5888 wb_write[0] = 0x55555555;
5889 wb_write[1] = 0x55555555;
5890 wb_write[2] = 0x20; /* SOP */
5891 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5892
5893 /* NON-IP protocol */
5894 wb_write[0] = 0x09000000;
5895 wb_write[1] = 0x55555555;
5896 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */
5897 REG_WR_DMAE(bp, NIG_REG_DEBUG_PACKET_LB, wb_write, 3);
5898 }
5899
5900 /* some of the internal memories
5901 * are not directly readable from the driver
5902 * to test them we send debug packets
5903 */
5904 static int bnx2x_int_mem_test(struct bnx2x *bp)
5905 {
5906 int factor;
5907 int count, i;
5908 u32 val = 0;
5909
5910 if (CHIP_REV_IS_FPGA(bp))
5911 factor = 120;
5912 else if (CHIP_REV_IS_EMUL(bp))
5913 factor = 200;
5914 else
5915 factor = 1;
5916
5917 /* Disable inputs of parser neighbor blocks */
5918 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5919 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5920 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5921 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5922
5923 /* Write 0 to parser credits for CFC search request */
5924 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5925
5926 /* send Ethernet packet */
5927 bnx2x_lb_pckt(bp);
5928
5929 /* TODO do i reset NIG statistic? */
5930 /* Wait until NIG register shows 1 packet of size 0x10 */
5931 count = 1000 * factor;
5932 while (count) {
5933
5934 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5935 val = *bnx2x_sp(bp, wb_data[0]);
5936 if (val == 0x10)
5937 break;
5938
5939 msleep(10);
5940 count--;
5941 }
5942 if (val != 0x10) {
5943 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
5944 return -1;
5945 }
5946
5947 /* Wait until PRS register shows 1 packet */
5948 count = 1000 * factor;
5949 while (count) {
5950 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
5951 if (val == 1)
5952 break;
5953
5954 msleep(10);
5955 count--;
5956 }
5957 if (val != 0x1) {
5958 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
5959 return -2;
5960 }
5961
5962 /* Reset and init BRB, PRS */
5963 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
5964 msleep(50);
5965 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
5966 msleep(50);
5967 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
5968 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
5969
5970 DP(NETIF_MSG_HW, "part2\n");
5971
5972 /* Disable inputs of parser neighbor blocks */
5973 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x0);
5974 REG_WR(bp, TCM_REG_PRS_IFEN, 0x0);
5975 REG_WR(bp, CFC_REG_DEBUG0, 0x1);
5976 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x0);
5977
5978 /* Write 0 to parser credits for CFC search request */
5979 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0);
5980
5981 /* send 10 Ethernet packets */
5982 for (i = 0; i < 10; i++)
5983 bnx2x_lb_pckt(bp);
5984
5985 /* Wait until NIG register shows 10 + 1
5986 packets of size 11*0x10 = 0xb0 */
5987 count = 1000 * factor;
5988 while (count) {
5989
5990 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
5991 val = *bnx2x_sp(bp, wb_data[0]);
5992 if (val == 0xb0)
5993 break;
5994
5995 msleep(10);
5996 count--;
5997 }
5998 if (val != 0xb0) {
5999 BNX2X_ERR("NIG timeout val = 0x%x\n", val);
6000 return -3;
6001 }
6002
6003 /* Wait until PRS register shows 2 packets */
6004 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6005 if (val != 2)
6006 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6007
6008 /* Write 1 to parser credits for CFC search request */
6009 REG_WR(bp, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1);
6010
6011 /* Wait until PRS register shows 3 packets */
6012 msleep(10 * factor);
6013 /* Wait until NIG register shows 1 packet of size 0x10 */
6014 val = REG_RD(bp, PRS_REG_NUM_OF_PACKETS);
6015 if (val != 3)
6016 BNX2X_ERR("PRS timeout val = 0x%x\n", val);
6017
6018 /* clear NIG EOP FIFO */
6019 for (i = 0; i < 11; i++)
6020 REG_RD(bp, NIG_REG_INGRESS_EOP_LB_FIFO);
6021 val = REG_RD(bp, NIG_REG_INGRESS_EOP_LB_EMPTY);
6022 if (val != 1) {
6023 BNX2X_ERR("clear of NIG failed\n");
6024 return -4;
6025 }
6026
6027 /* Reset and init BRB, PRS, NIG */
6028 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03);
6029 msleep(50);
6030 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03);
6031 msleep(50);
6032 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6033 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6034 #ifndef BCM_CNIC
6035 /* set NIC mode */
6036 REG_WR(bp, PRS_REG_NIC_MODE, 1);
6037 #endif
6038
6039 /* Enable inputs of parser neighbor blocks */
6040 REG_WR(bp, TSDM_REG_ENABLE_IN1, 0x7fffffff);
6041 REG_WR(bp, TCM_REG_PRS_IFEN, 0x1);
6042 REG_WR(bp, CFC_REG_DEBUG0, 0x0);
6043 REG_WR(bp, NIG_REG_PRS_REQ_IN_EN, 0x1);
6044
6045 DP(NETIF_MSG_HW, "done\n");
6046
6047 return 0; /* OK */
6048 }
6049
6050 static void bnx2x_enable_blocks_attention(struct bnx2x *bp)
6051 {
6052 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6053 if (!CHIP_IS_E1x(bp))
6054 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0x40);
6055 else
6056 REG_WR(bp, PXP_REG_PXP_INT_MASK_1, 0);
6057 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6058 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6059 /*
6060 * mask read length error interrupts in brb for parser
6061 * (parsing unit and 'checksum and crc' unit)
6062 * these errors are legal (PU reads fixed length and CAC can cause
6063 * read length error on truncated packets)
6064 */
6065 REG_WR(bp, BRB1_REG_BRB1_INT_MASK, 0xFC00);
6066 REG_WR(bp, QM_REG_QM_INT_MASK, 0);
6067 REG_WR(bp, TM_REG_TM_INT_MASK, 0);
6068 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_0, 0);
6069 REG_WR(bp, XSDM_REG_XSDM_INT_MASK_1, 0);
6070 REG_WR(bp, XCM_REG_XCM_INT_MASK, 0);
6071 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6072 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6073 REG_WR(bp, USDM_REG_USDM_INT_MASK_0, 0);
6074 REG_WR(bp, USDM_REG_USDM_INT_MASK_1, 0);
6075 REG_WR(bp, UCM_REG_UCM_INT_MASK, 0);
6076 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6077 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6078 REG_WR(bp, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0);
6079 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_0, 0);
6080 REG_WR(bp, CSDM_REG_CSDM_INT_MASK_1, 0);
6081 REG_WR(bp, CCM_REG_CCM_INT_MASK, 0);
6082 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6083 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6084
6085 if (CHIP_REV_IS_FPGA(bp))
6086 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x580000);
6087 else if (!CHIP_IS_E1x(bp))
6088 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0,
6089 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
6090 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
6091 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
6092 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
6093 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED));
6094 else
6095 REG_WR(bp, PXP2_REG_PXP2_INT_MASK_0, 0x480000);
6096 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_0, 0);
6097 REG_WR(bp, TSDM_REG_TSDM_INT_MASK_1, 0);
6098 REG_WR(bp, TCM_REG_TCM_INT_MASK, 0);
6099 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6100
6101 if (!CHIP_IS_E1x(bp))
6102 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6103 REG_WR(bp, TSEM_REG_TSEM_INT_MASK_1, 0x07ff);
6104
6105 REG_WR(bp, CDU_REG_CDU_INT_MASK, 0);
6106 REG_WR(bp, DMAE_REG_DMAE_INT_MASK, 0);
6107 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6108 REG_WR(bp, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */
6109 }
6110
6111 static void bnx2x_reset_common(struct bnx2x *bp)
6112 {
6113 u32 val = 0x1400;
6114
6115 /* reset_common */
6116 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6117 0xd3ffff7f);
6118
6119 if (CHIP_IS_E3(bp)) {
6120 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6121 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6122 }
6123
6124 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, val);
6125 }
6126
6127 static void bnx2x_setup_dmae(struct bnx2x *bp)
6128 {
6129 bp->dmae_ready = 0;
6130 spin_lock_init(&bp->dmae_lock);
6131 }
6132
6133 static void bnx2x_init_pxp(struct bnx2x *bp)
6134 {
6135 u16 devctl;
6136 int r_order, w_order;
6137
6138 pci_read_config_word(bp->pdev,
6139 pci_pcie_cap(bp->pdev) + PCI_EXP_DEVCTL, &devctl);
6140 DP(NETIF_MSG_HW, "read 0x%x from devctl\n", devctl);
6141 w_order = ((devctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
6142 if (bp->mrrs == -1)
6143 r_order = ((devctl & PCI_EXP_DEVCTL_READRQ) >> 12);
6144 else {
6145 DP(NETIF_MSG_HW, "force read order to %d\n", bp->mrrs);
6146 r_order = bp->mrrs;
6147 }
6148
6149 bnx2x_init_pxp_arb(bp, r_order, w_order);
6150 }
6151
6152 static void bnx2x_setup_fan_failure_detection(struct bnx2x *bp)
6153 {
6154 int is_required;
6155 u32 val;
6156 int port;
6157
6158 if (BP_NOMCP(bp))
6159 return;
6160
6161 is_required = 0;
6162 val = SHMEM_RD(bp, dev_info.shared_hw_config.config2) &
6163 SHARED_HW_CFG_FAN_FAILURE_MASK;
6164
6165 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED)
6166 is_required = 1;
6167
6168 /*
6169 * The fan failure mechanism is usually related to the PHY type since
6170 * the power consumption of the board is affected by the PHY. Currently,
6171 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6172 */
6173 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE)
6174 for (port = PORT_0; port < PORT_MAX; port++) {
6175 is_required |=
6176 bnx2x_fan_failure_det_req(
6177 bp,
6178 bp->common.shmem_base,
6179 bp->common.shmem2_base,
6180 port);
6181 }
6182
6183 DP(NETIF_MSG_HW, "fan detection setting: %d\n", is_required);
6184
6185 if (is_required == 0)
6186 return;
6187
6188 /* Fan failure is indicated by SPIO 5 */
6189 bnx2x_set_spio(bp, MISC_REGISTERS_SPIO_5,
6190 MISC_REGISTERS_SPIO_INPUT_HI_Z);
6191
6192 /* set to active low mode */
6193 val = REG_RD(bp, MISC_REG_SPIO_INT);
6194 val |= ((1 << MISC_REGISTERS_SPIO_5) <<
6195 MISC_REGISTERS_SPIO_INT_OLD_SET_POS);
6196 REG_WR(bp, MISC_REG_SPIO_INT, val);
6197
6198 /* enable interrupt to signal the IGU */
6199 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6200 val |= (1 << MISC_REGISTERS_SPIO_5);
6201 REG_WR(bp, MISC_REG_SPIO_EVENT_EN, val);
6202 }
6203
6204 static void bnx2x_pretend_func(struct bnx2x *bp, u8 pretend_func_num)
6205 {
6206 u32 offset = 0;
6207
6208 if (CHIP_IS_E1(bp))
6209 return;
6210 if (CHIP_IS_E1H(bp) && (pretend_func_num >= E1H_FUNC_MAX))
6211 return;
6212
6213 switch (BP_ABS_FUNC(bp)) {
6214 case 0:
6215 offset = PXP2_REG_PGL_PRETEND_FUNC_F0;
6216 break;
6217 case 1:
6218 offset = PXP2_REG_PGL_PRETEND_FUNC_F1;
6219 break;
6220 case 2:
6221 offset = PXP2_REG_PGL_PRETEND_FUNC_F2;
6222 break;
6223 case 3:
6224 offset = PXP2_REG_PGL_PRETEND_FUNC_F3;
6225 break;
6226 case 4:
6227 offset = PXP2_REG_PGL_PRETEND_FUNC_F4;
6228 break;
6229 case 5:
6230 offset = PXP2_REG_PGL_PRETEND_FUNC_F5;
6231 break;
6232 case 6:
6233 offset = PXP2_REG_PGL_PRETEND_FUNC_F6;
6234 break;
6235 case 7:
6236 offset = PXP2_REG_PGL_PRETEND_FUNC_F7;
6237 break;
6238 default:
6239 return;
6240 }
6241
6242 REG_WR(bp, offset, pretend_func_num);
6243 REG_RD(bp, offset);
6244 DP(NETIF_MSG_HW, "Pretending to func %d\n", pretend_func_num);
6245 }
6246
6247 void bnx2x_pf_disable(struct bnx2x *bp)
6248 {
6249 u32 val = REG_RD(bp, IGU_REG_PF_CONFIGURATION);
6250 val &= ~IGU_PF_CONF_FUNC_EN;
6251
6252 REG_WR(bp, IGU_REG_PF_CONFIGURATION, val);
6253 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6254 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 0);
6255 }
6256
6257 static void bnx2x__common_init_phy(struct bnx2x *bp)
6258 {
6259 u32 shmem_base[2], shmem2_base[2];
6260 shmem_base[0] = bp->common.shmem_base;
6261 shmem2_base[0] = bp->common.shmem2_base;
6262 if (!CHIP_IS_E1x(bp)) {
6263 shmem_base[1] =
6264 SHMEM2_RD(bp, other_shmem_base_addr);
6265 shmem2_base[1] =
6266 SHMEM2_RD(bp, other_shmem2_base_addr);
6267 }
6268 bnx2x_acquire_phy_lock(bp);
6269 bnx2x_common_init_phy(bp, shmem_base, shmem2_base,
6270 bp->common.chip_id);
6271 bnx2x_release_phy_lock(bp);
6272 }
6273
6274 /**
6275 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
6276 *
6277 * @bp: driver handle
6278 */
6279 static int bnx2x_init_hw_common(struct bnx2x *bp)
6280 {
6281 u32 val;
6282
6283 DP(NETIF_MSG_HW, "starting common init func %d\n", BP_ABS_FUNC(bp));
6284
6285 /*
6286 * take the UNDI lock to protect undi_unload flow from accessing
6287 * registers while we're resetting the chip
6288 */
6289 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6290
6291 bnx2x_reset_common(bp);
6292 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0xffffffff);
6293
6294 val = 0xfffc;
6295 if (CHIP_IS_E3(bp)) {
6296 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0;
6297 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1;
6298 }
6299 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, val);
6300
6301 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
6302
6303 bnx2x_init_block(bp, BLOCK_MISC, PHASE_COMMON);
6304
6305 if (!CHIP_IS_E1x(bp)) {
6306 u8 abs_func_id;
6307
6308 /**
6309 * 4-port mode or 2-port mode we need to turn of master-enable
6310 * for everyone, after that, turn it back on for self.
6311 * so, we disregard multi-function or not, and always disable
6312 * for all functions on the given path, this means 0,2,4,6 for
6313 * path 0 and 1,3,5,7 for path 1
6314 */
6315 for (abs_func_id = BP_PATH(bp);
6316 abs_func_id < E2_FUNC_MAX*2; abs_func_id += 2) {
6317 if (abs_func_id == BP_ABS_FUNC(bp)) {
6318 REG_WR(bp,
6319 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER,
6320 1);
6321 continue;
6322 }
6323
6324 bnx2x_pretend_func(bp, abs_func_id);
6325 /* clear pf enable */
6326 bnx2x_pf_disable(bp);
6327 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6328 }
6329 }
6330
6331 bnx2x_init_block(bp, BLOCK_PXP, PHASE_COMMON);
6332 if (CHIP_IS_E1(bp)) {
6333 /* enable HW interrupt from PXP on USDM overflow
6334 bit 16 on INT_MASK_0 */
6335 REG_WR(bp, PXP_REG_PXP_INT_MASK_0, 0);
6336 }
6337
6338 bnx2x_init_block(bp, BLOCK_PXP2, PHASE_COMMON);
6339 bnx2x_init_pxp(bp);
6340
6341 #ifdef __BIG_ENDIAN
6342 REG_WR(bp, PXP2_REG_RQ_QM_ENDIAN_M, 1);
6343 REG_WR(bp, PXP2_REG_RQ_TM_ENDIAN_M, 1);
6344 REG_WR(bp, PXP2_REG_RQ_SRC_ENDIAN_M, 1);
6345 REG_WR(bp, PXP2_REG_RQ_CDU_ENDIAN_M, 1);
6346 REG_WR(bp, PXP2_REG_RQ_DBG_ENDIAN_M, 1);
6347 /* make sure this value is 0 */
6348 REG_WR(bp, PXP2_REG_RQ_HC_ENDIAN_M, 0);
6349
6350 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6351 REG_WR(bp, PXP2_REG_RD_QM_SWAP_MODE, 1);
6352 REG_WR(bp, PXP2_REG_RD_TM_SWAP_MODE, 1);
6353 REG_WR(bp, PXP2_REG_RD_SRC_SWAP_MODE, 1);
6354 REG_WR(bp, PXP2_REG_RD_CDURD_SWAP_MODE, 1);
6355 #endif
6356
6357 bnx2x_ilt_init_page_size(bp, INITOP_SET);
6358
6359 if (CHIP_REV_IS_FPGA(bp) && CHIP_IS_E1H(bp))
6360 REG_WR(bp, PXP2_REG_PGL_TAGS_LIMIT, 0x1);
6361
6362 /* let the HW do it's magic ... */
6363 msleep(100);
6364 /* finish PXP init */
6365 val = REG_RD(bp, PXP2_REG_RQ_CFG_DONE);
6366 if (val != 1) {
6367 BNX2X_ERR("PXP2 CFG failed\n");
6368 return -EBUSY;
6369 }
6370 val = REG_RD(bp, PXP2_REG_RD_INIT_DONE);
6371 if (val != 1) {
6372 BNX2X_ERR("PXP2 RD_INIT failed\n");
6373 return -EBUSY;
6374 }
6375
6376 /* Timers bug workaround E2 only. We need to set the entire ILT to
6377 * have entries with value "0" and valid bit on.
6378 * This needs to be done by the first PF that is loaded in a path
6379 * (i.e. common phase)
6380 */
6381 if (!CHIP_IS_E1x(bp)) {
6382 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6383 * (i.e. vnic3) to start even if it is marked as "scan-off".
6384 * This occurs when a different function (func2,3) is being marked
6385 * as "scan-off". Real-life scenario for example: if a driver is being
6386 * load-unloaded while func6,7 are down. This will cause the timer to access
6387 * the ilt, translate to a logical address and send a request to read/write.
6388 * Since the ilt for the function that is down is not valid, this will cause
6389 * a translation error which is unrecoverable.
6390 * The Workaround is intended to make sure that when this happens nothing fatal
6391 * will occur. The workaround:
6392 * 1. First PF driver which loads on a path will:
6393 * a. After taking the chip out of reset, by using pretend,
6394 * it will write "0" to the following registers of
6395 * the other vnics.
6396 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6397 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6398 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6399 * And for itself it will write '1' to
6400 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6401 * dmae-operations (writing to pram for example.)
6402 * note: can be done for only function 6,7 but cleaner this
6403 * way.
6404 * b. Write zero+valid to the entire ILT.
6405 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6406 * VNIC3 (of that port). The range allocated will be the
6407 * entire ILT. This is needed to prevent ILT range error.
6408 * 2. Any PF driver load flow:
6409 * a. ILT update with the physical addresses of the allocated
6410 * logical pages.
6411 * b. Wait 20msec. - note that this timeout is needed to make
6412 * sure there are no requests in one of the PXP internal
6413 * queues with "old" ILT addresses.
6414 * c. PF enable in the PGLC.
6415 * d. Clear the was_error of the PF in the PGLC. (could have
6416 * occured while driver was down)
6417 * e. PF enable in the CFC (WEAK + STRONG)
6418 * f. Timers scan enable
6419 * 3. PF driver unload flow:
6420 * a. Clear the Timers scan_en.
6421 * b. Polling for scan_on=0 for that PF.
6422 * c. Clear the PF enable bit in the PXP.
6423 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6424 * e. Write zero+valid to all ILT entries (The valid bit must
6425 * stay set)
6426 * f. If this is VNIC 3 of a port then also init
6427 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6428 * to the last enrty in the ILT.
6429 *
6430 * Notes:
6431 * Currently the PF error in the PGLC is non recoverable.
6432 * In the future the there will be a recovery routine for this error.
6433 * Currently attention is masked.
6434 * Having an MCP lock on the load/unload process does not guarantee that
6435 * there is no Timer disable during Func6/7 enable. This is because the
6436 * Timers scan is currently being cleared by the MCP on FLR.
6437 * Step 2.d can be done only for PF6/7 and the driver can also check if
6438 * there is error before clearing it. But the flow above is simpler and
6439 * more general.
6440 * All ILT entries are written by zero+valid and not just PF6/7
6441 * ILT entries since in the future the ILT entries allocation for
6442 * PF-s might be dynamic.
6443 */
6444 struct ilt_client_info ilt_cli;
6445 struct bnx2x_ilt ilt;
6446 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
6447 memset(&ilt, 0, sizeof(struct bnx2x_ilt));
6448
6449 /* initialize dummy TM client */
6450 ilt_cli.start = 0;
6451 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
6452 ilt_cli.client_num = ILT_CLIENT_TM;
6453
6454 /* Step 1: set zeroes to all ilt page entries with valid bit on
6455 * Step 2: set the timers first/last ilt entry to point
6456 * to the entire range to prevent ILT range error for 3rd/4th
6457 * vnic (this code assumes existance of the vnic)
6458 *
6459 * both steps performed by call to bnx2x_ilt_client_init_op()
6460 * with dummy TM client
6461 *
6462 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6463 * and his brother are split registers
6464 */
6465 bnx2x_pretend_func(bp, (BP_PATH(bp) + 6));
6466 bnx2x_ilt_client_init_op_ilt(bp, &ilt, &ilt_cli, INITOP_CLEAR);
6467 bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
6468
6469 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN, BNX2X_PXP_DRAM_ALIGN);
6470 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_RD, BNX2X_PXP_DRAM_ALIGN);
6471 REG_WR(bp, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1);
6472 }
6473
6474
6475 REG_WR(bp, PXP2_REG_RQ_DISABLE_INPUTS, 0);
6476 REG_WR(bp, PXP2_REG_RD_DISABLE_INPUTS, 0);
6477
6478 if (!CHIP_IS_E1x(bp)) {
6479 int factor = CHIP_REV_IS_EMUL(bp) ? 1000 :
6480 (CHIP_REV_IS_FPGA(bp) ? 400 : 0);
6481 bnx2x_init_block(bp, BLOCK_PGLUE_B, PHASE_COMMON);
6482
6483 bnx2x_init_block(bp, BLOCK_ATC, PHASE_COMMON);
6484
6485 /* let the HW do it's magic ... */
6486 do {
6487 msleep(200);
6488 val = REG_RD(bp, ATC_REG_ATC_INIT_DONE);
6489 } while (factor-- && (val != 1));
6490
6491 if (val != 1) {
6492 BNX2X_ERR("ATC_INIT failed\n");
6493 return -EBUSY;
6494 }
6495 }
6496
6497 bnx2x_init_block(bp, BLOCK_DMAE, PHASE_COMMON);
6498
6499 /* clean the DMAE memory */
6500 bp->dmae_ready = 1;
6501 bnx2x_init_fill(bp, TSEM_REG_PRAM, 0, 8, 1);
6502
6503 bnx2x_init_block(bp, BLOCK_TCM, PHASE_COMMON);
6504
6505 bnx2x_init_block(bp, BLOCK_UCM, PHASE_COMMON);
6506
6507 bnx2x_init_block(bp, BLOCK_CCM, PHASE_COMMON);
6508
6509 bnx2x_init_block(bp, BLOCK_XCM, PHASE_COMMON);
6510
6511 bnx2x_read_dmae(bp, XSEM_REG_PASSIVE_BUFFER, 3);
6512 bnx2x_read_dmae(bp, CSEM_REG_PASSIVE_BUFFER, 3);
6513 bnx2x_read_dmae(bp, TSEM_REG_PASSIVE_BUFFER, 3);
6514 bnx2x_read_dmae(bp, USEM_REG_PASSIVE_BUFFER, 3);
6515
6516 bnx2x_init_block(bp, BLOCK_QM, PHASE_COMMON);
6517
6518
6519 /* QM queues pointers table */
6520 bnx2x_qm_init_ptr_table(bp, bp->qm_cid_count, INITOP_SET);
6521
6522 /* soft reset pulse */
6523 REG_WR(bp, QM_REG_SOFT_RESET, 1);
6524 REG_WR(bp, QM_REG_SOFT_RESET, 0);
6525
6526 #ifdef BCM_CNIC
6527 bnx2x_init_block(bp, BLOCK_TM, PHASE_COMMON);
6528 #endif
6529
6530 bnx2x_init_block(bp, BLOCK_DORQ, PHASE_COMMON);
6531 REG_WR(bp, DORQ_REG_DPM_CID_OFST, BNX2X_DB_SHIFT);
6532 if (!CHIP_REV_IS_SLOW(bp))
6533 /* enable hw interrupt from doorbell Q */
6534 REG_WR(bp, DORQ_REG_DORQ_INT_MASK, 0);
6535
6536 bnx2x_init_block(bp, BLOCK_BRB1, PHASE_COMMON);
6537
6538 bnx2x_init_block(bp, BLOCK_PRS, PHASE_COMMON);
6539 REG_WR(bp, PRS_REG_A_PRSU_20, 0xf);
6540
6541 if (!CHIP_IS_E1(bp))
6542 REG_WR(bp, PRS_REG_E1HOV_MODE, bp->path_has_ovlan);
6543
6544 if (!CHIP_IS_E1x(bp) && !CHIP_IS_E3B0(bp)) {
6545 if (IS_MF_AFEX(bp)) {
6546 /* configure that VNTag and VLAN headers must be
6547 * received in afex mode
6548 */
6549 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC, 0xE);
6550 REG_WR(bp, PRS_REG_MUST_HAVE_HDRS, 0xA);
6551 REG_WR(bp, PRS_REG_HDRS_AFTER_TAG_0, 0x6);
6552 REG_WR(bp, PRS_REG_TAG_ETHERTYPE_0, 0x8926);
6553 REG_WR(bp, PRS_REG_TAG_LEN_0, 0x4);
6554 } else {
6555 /* Bit-map indicating which L2 hdrs may appear
6556 * after the basic Ethernet header
6557 */
6558 REG_WR(bp, PRS_REG_HDRS_AFTER_BASIC,
6559 bp->path_has_ovlan ? 7 : 6);
6560 }
6561 }
6562
6563 bnx2x_init_block(bp, BLOCK_TSDM, PHASE_COMMON);
6564 bnx2x_init_block(bp, BLOCK_CSDM, PHASE_COMMON);
6565 bnx2x_init_block(bp, BLOCK_USDM, PHASE_COMMON);
6566 bnx2x_init_block(bp, BLOCK_XSDM, PHASE_COMMON);
6567
6568 if (!CHIP_IS_E1x(bp)) {
6569 /* reset VFC memories */
6570 REG_WR(bp, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6571 VFC_MEMORIES_RST_REG_CAM_RST |
6572 VFC_MEMORIES_RST_REG_RAM_RST);
6573 REG_WR(bp, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST,
6574 VFC_MEMORIES_RST_REG_CAM_RST |
6575 VFC_MEMORIES_RST_REG_RAM_RST);
6576
6577 msleep(20);
6578 }
6579
6580 bnx2x_init_block(bp, BLOCK_TSEM, PHASE_COMMON);
6581 bnx2x_init_block(bp, BLOCK_USEM, PHASE_COMMON);
6582 bnx2x_init_block(bp, BLOCK_CSEM, PHASE_COMMON);
6583 bnx2x_init_block(bp, BLOCK_XSEM, PHASE_COMMON);
6584
6585 /* sync semi rtc */
6586 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
6587 0x80000000);
6588 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET,
6589 0x80000000);
6590
6591 bnx2x_init_block(bp, BLOCK_UPB, PHASE_COMMON);
6592 bnx2x_init_block(bp, BLOCK_XPB, PHASE_COMMON);
6593 bnx2x_init_block(bp, BLOCK_PBF, PHASE_COMMON);
6594
6595 if (!CHIP_IS_E1x(bp)) {
6596 if (IS_MF_AFEX(bp)) {
6597 /* configure that VNTag and VLAN headers must be
6598 * sent in afex mode
6599 */
6600 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC, 0xE);
6601 REG_WR(bp, PBF_REG_MUST_HAVE_HDRS, 0xA);
6602 REG_WR(bp, PBF_REG_HDRS_AFTER_TAG_0, 0x6);
6603 REG_WR(bp, PBF_REG_TAG_ETHERTYPE_0, 0x8926);
6604 REG_WR(bp, PBF_REG_TAG_LEN_0, 0x4);
6605 } else {
6606 REG_WR(bp, PBF_REG_HDRS_AFTER_BASIC,
6607 bp->path_has_ovlan ? 7 : 6);
6608 }
6609 }
6610
6611 REG_WR(bp, SRC_REG_SOFT_RST, 1);
6612
6613 bnx2x_init_block(bp, BLOCK_SRC, PHASE_COMMON);
6614
6615 #ifdef BCM_CNIC
6616 REG_WR(bp, SRC_REG_KEYSEARCH_0, 0x63285672);
6617 REG_WR(bp, SRC_REG_KEYSEARCH_1, 0x24b8f2cc);
6618 REG_WR(bp, SRC_REG_KEYSEARCH_2, 0x223aef9b);
6619 REG_WR(bp, SRC_REG_KEYSEARCH_3, 0x26001e3a);
6620 REG_WR(bp, SRC_REG_KEYSEARCH_4, 0x7ae91116);
6621 REG_WR(bp, SRC_REG_KEYSEARCH_5, 0x5ce5230b);
6622 REG_WR(bp, SRC_REG_KEYSEARCH_6, 0x298d8adf);
6623 REG_WR(bp, SRC_REG_KEYSEARCH_7, 0x6eb0ff09);
6624 REG_WR(bp, SRC_REG_KEYSEARCH_8, 0x1830f82f);
6625 REG_WR(bp, SRC_REG_KEYSEARCH_9, 0x01e46be7);
6626 #endif
6627 REG_WR(bp, SRC_REG_SOFT_RST, 0);
6628
6629 if (sizeof(union cdu_context) != 1024)
6630 /* we currently assume that a context is 1024 bytes */
6631 dev_alert(&bp->pdev->dev,
6632 "please adjust the size of cdu_context(%ld)\n",
6633 (long)sizeof(union cdu_context));
6634
6635 bnx2x_init_block(bp, BLOCK_CDU, PHASE_COMMON);
6636 val = (4 << 24) + (0 << 12) + 1024;
6637 REG_WR(bp, CDU_REG_CDU_GLOBAL_PARAMS, val);
6638
6639 bnx2x_init_block(bp, BLOCK_CFC, PHASE_COMMON);
6640 REG_WR(bp, CFC_REG_INIT_REG, 0x7FF);
6641 /* enable context validation interrupt from CFC */
6642 REG_WR(bp, CFC_REG_CFC_INT_MASK, 0);
6643
6644 /* set the thresholds to prevent CFC/CDU race */
6645 REG_WR(bp, CFC_REG_DEBUG0, 0x20020000);
6646
6647 bnx2x_init_block(bp, BLOCK_HC, PHASE_COMMON);
6648
6649 if (!CHIP_IS_E1x(bp) && BP_NOMCP(bp))
6650 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x36);
6651
6652 bnx2x_init_block(bp, BLOCK_IGU, PHASE_COMMON);
6653 bnx2x_init_block(bp, BLOCK_MISC_AEU, PHASE_COMMON);
6654
6655 /* Reset PCIE errors for debug */
6656 REG_WR(bp, 0x2814, 0xffffffff);
6657 REG_WR(bp, 0x3820, 0xffffffff);
6658
6659 if (!CHIP_IS_E1x(bp)) {
6660 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_CONTROL_5,
6661 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 |
6662 PXPCS_TL_CONTROL_5_ERR_UNSPPORT));
6663 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT,
6664 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 |
6665 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 |
6666 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2));
6667 REG_WR(bp, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT,
6668 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 |
6669 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 |
6670 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5));
6671 }
6672
6673 bnx2x_init_block(bp, BLOCK_NIG, PHASE_COMMON);
6674 if (!CHIP_IS_E1(bp)) {
6675 /* in E3 this done in per-port section */
6676 if (!CHIP_IS_E3(bp))
6677 REG_WR(bp, NIG_REG_LLH_MF_MODE, IS_MF(bp));
6678 }
6679 if (CHIP_IS_E1H(bp))
6680 /* not applicable for E2 (and above ...) */
6681 REG_WR(bp, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(bp));
6682
6683 if (CHIP_REV_IS_SLOW(bp))
6684 msleep(200);
6685
6686 /* finish CFC init */
6687 val = reg_poll(bp, CFC_REG_LL_INIT_DONE, 1, 100, 10);
6688 if (val != 1) {
6689 BNX2X_ERR("CFC LL_INIT failed\n");
6690 return -EBUSY;
6691 }
6692 val = reg_poll(bp, CFC_REG_AC_INIT_DONE, 1, 100, 10);
6693 if (val != 1) {
6694 BNX2X_ERR("CFC AC_INIT failed\n");
6695 return -EBUSY;
6696 }
6697 val = reg_poll(bp, CFC_REG_CAM_INIT_DONE, 1, 100, 10);
6698 if (val != 1) {
6699 BNX2X_ERR("CFC CAM_INIT failed\n");
6700 return -EBUSY;
6701 }
6702 REG_WR(bp, CFC_REG_DEBUG0, 0);
6703
6704 if (CHIP_IS_E1(bp)) {
6705 /* read NIG statistic
6706 to see if this is our first up since powerup */
6707 bnx2x_read_dmae(bp, NIG_REG_STAT2_BRB_OCTET, 2);
6708 val = *bnx2x_sp(bp, wb_data[0]);
6709
6710 /* do internal memory self test */
6711 if ((val == 0) && bnx2x_int_mem_test(bp)) {
6712 BNX2X_ERR("internal mem self test failed\n");
6713 return -EBUSY;
6714 }
6715 }
6716
6717 bnx2x_setup_fan_failure_detection(bp);
6718
6719 /* clear PXP2 attentions */
6720 REG_RD(bp, PXP2_REG_PXP2_INT_STS_CLR_0);
6721
6722 bnx2x_enable_blocks_attention(bp);
6723 bnx2x_enable_blocks_parity(bp);
6724
6725 if (!BP_NOMCP(bp)) {
6726 if (CHIP_IS_E1x(bp))
6727 bnx2x__common_init_phy(bp);
6728 } else
6729 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6730
6731 return 0;
6732 }
6733
6734 /**
6735 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6736 *
6737 * @bp: driver handle
6738 */
6739 static int bnx2x_init_hw_common_chip(struct bnx2x *bp)
6740 {
6741 int rc = bnx2x_init_hw_common(bp);
6742
6743 if (rc)
6744 return rc;
6745
6746 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6747 if (!BP_NOMCP(bp))
6748 bnx2x__common_init_phy(bp);
6749
6750 return 0;
6751 }
6752
6753 static int bnx2x_init_hw_port(struct bnx2x *bp)
6754 {
6755 int port = BP_PORT(bp);
6756 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0;
6757 u32 low, high;
6758 u32 val;
6759
6760 bnx2x__link_reset(bp);
6761
6762 DP(NETIF_MSG_HW, "starting port init port %d\n", port);
6763
6764 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
6765
6766 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
6767 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
6768 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
6769
6770 /* Timers bug workaround: disables the pf_master bit in pglue at
6771 * common phase, we need to enable it here before any dmae access are
6772 * attempted. Therefore we manually added the enable-master to the
6773 * port phase (it also happens in the function phase)
6774 */
6775 if (!CHIP_IS_E1x(bp))
6776 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
6777
6778 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
6779 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
6780 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
6781 bnx2x_init_block(bp, BLOCK_QM, init_phase);
6782
6783 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
6784 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
6785 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
6786 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
6787
6788 /* QM cid (connection) count */
6789 bnx2x_qm_init_cid_count(bp, bp->qm_cid_count, INITOP_SET);
6790
6791 #ifdef BCM_CNIC
6792 bnx2x_init_block(bp, BLOCK_TM, init_phase);
6793 REG_WR(bp, TM_REG_LIN0_SCAN_TIME + port*4, 20);
6794 REG_WR(bp, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31);
6795 #endif
6796
6797 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
6798
6799 if (CHIP_IS_E1(bp) || CHIP_IS_E1H(bp)) {
6800 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
6801
6802 if (IS_MF(bp))
6803 low = ((bp->flags & ONE_PORT_FLAG) ? 160 : 246);
6804 else if (bp->dev->mtu > 4096) {
6805 if (bp->flags & ONE_PORT_FLAG)
6806 low = 160;
6807 else {
6808 val = bp->dev->mtu;
6809 /* (24*1024 + val*4)/256 */
6810 low = 96 + (val/64) +
6811 ((val % 64) ? 1 : 0);
6812 }
6813 } else
6814 low = ((bp->flags & ONE_PORT_FLAG) ? 80 : 160);
6815 high = low + 56; /* 14*1024/256 */
6816 REG_WR(bp, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low);
6817 REG_WR(bp, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high);
6818 }
6819
6820 if (CHIP_MODE_IS_4_PORT(bp))
6821 REG_WR(bp, (BP_PORT(bp) ?
6822 BRB1_REG_MAC_GUARANTIED_1 :
6823 BRB1_REG_MAC_GUARANTIED_0), 40);
6824
6825
6826 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
6827 if (CHIP_IS_E3B0(bp)) {
6828 if (IS_MF_AFEX(bp)) {
6829 /* configure headers for AFEX mode */
6830 REG_WR(bp, BP_PORT(bp) ?
6831 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6832 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE);
6833 REG_WR(bp, BP_PORT(bp) ?
6834 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 :
6835 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6);
6836 REG_WR(bp, BP_PORT(bp) ?
6837 PRS_REG_MUST_HAVE_HDRS_PORT_1 :
6838 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA);
6839 } else {
6840 /* Ovlan exists only if we are in multi-function +
6841 * switch-dependent mode, in switch-independent there
6842 * is no ovlan headers
6843 */
6844 REG_WR(bp, BP_PORT(bp) ?
6845 PRS_REG_HDRS_AFTER_BASIC_PORT_1 :
6846 PRS_REG_HDRS_AFTER_BASIC_PORT_0,
6847 (bp->path_has_ovlan ? 7 : 6));
6848 }
6849 }
6850
6851 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
6852 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
6853 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
6854 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
6855
6856 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
6857 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
6858 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
6859 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
6860
6861 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
6862 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
6863
6864 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
6865
6866 if (CHIP_IS_E1x(bp)) {
6867 /* configure PBF to work without PAUSE mtu 9000 */
6868 REG_WR(bp, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
6869
6870 /* update threshold */
6871 REG_WR(bp, PBF_REG_P0_ARB_THRSH + port*4, (9040/16));
6872 /* update init credit */
6873 REG_WR(bp, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22);
6874
6875 /* probe changes */
6876 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 1);
6877 udelay(50);
6878 REG_WR(bp, PBF_REG_INIT_P0 + port*4, 0);
6879 }
6880
6881 #ifdef BCM_CNIC
6882 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
6883 #endif
6884 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
6885 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
6886
6887 if (CHIP_IS_E1(bp)) {
6888 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
6889 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
6890 }
6891 bnx2x_init_block(bp, BLOCK_HC, init_phase);
6892
6893 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
6894
6895 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
6896 /* init aeu_mask_attn_func_0/1:
6897 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6898 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6899 * bits 4-7 are used for "per vn group attention" */
6900 val = IS_MF(bp) ? 0xF7 : 0x7;
6901 /* Enable DCBX attention for all but E1 */
6902 val |= CHIP_IS_E1(bp) ? 0 : 0x10;
6903 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val);
6904
6905 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
6906
6907 if (!CHIP_IS_E1x(bp)) {
6908 /* Bit-map indicating which L2 hdrs may appear after the
6909 * basic Ethernet header
6910 */
6911 if (IS_MF_AFEX(bp))
6912 REG_WR(bp, BP_PORT(bp) ?
6913 NIG_REG_P1_HDRS_AFTER_BASIC :
6914 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE);
6915 else
6916 REG_WR(bp, BP_PORT(bp) ?
6917 NIG_REG_P1_HDRS_AFTER_BASIC :
6918 NIG_REG_P0_HDRS_AFTER_BASIC,
6919 IS_MF_SD(bp) ? 7 : 6);
6920
6921 if (CHIP_IS_E3(bp))
6922 REG_WR(bp, BP_PORT(bp) ?
6923 NIG_REG_LLH1_MF_MODE :
6924 NIG_REG_LLH_MF_MODE, IS_MF(bp));
6925 }
6926 if (!CHIP_IS_E3(bp))
6927 REG_WR(bp, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
6928
6929 if (!CHIP_IS_E1(bp)) {
6930 /* 0x2 disable mf_ov, 0x1 enable */
6931 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4,
6932 (IS_MF_SD(bp) ? 0x1 : 0x2));
6933
6934 if (!CHIP_IS_E1x(bp)) {
6935 val = 0;
6936 switch (bp->mf_mode) {
6937 case MULTI_FUNCTION_SD:
6938 val = 1;
6939 break;
6940 case MULTI_FUNCTION_SI:
6941 case MULTI_FUNCTION_AFEX:
6942 val = 2;
6943 break;
6944 }
6945
6946 REG_WR(bp, (BP_PORT(bp) ? NIG_REG_LLH1_CLS_TYPE :
6947 NIG_REG_LLH0_CLS_TYPE), val);
6948 }
6949 {
6950 REG_WR(bp, NIG_REG_LLFC_ENABLE_0 + port*4, 0);
6951 REG_WR(bp, NIG_REG_LLFC_OUT_EN_0 + port*4, 0);
6952 REG_WR(bp, NIG_REG_PAUSE_ENABLE_0 + port*4, 1);
6953 }
6954 }
6955
6956
6957 /* If SPIO5 is set to generate interrupts, enable it for this port */
6958 val = REG_RD(bp, MISC_REG_SPIO_EVENT_EN);
6959 if (val & (1 << MISC_REGISTERS_SPIO_5)) {
6960 u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
6961 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0);
6962 val = REG_RD(bp, reg_addr);
6963 val |= AEU_INPUTS_ATTN_BITS_SPIO5;
6964 REG_WR(bp, reg_addr, val);
6965 }
6966
6967 return 0;
6968 }
6969
6970 static void bnx2x_ilt_wr(struct bnx2x *bp, u32 index, dma_addr_t addr)
6971 {
6972 int reg;
6973 u32 wb_write[2];
6974
6975 if (CHIP_IS_E1(bp))
6976 reg = PXP2_REG_RQ_ONCHIP_AT + index*8;
6977 else
6978 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8;
6979
6980 wb_write[0] = ONCHIP_ADDR1(addr);
6981 wb_write[1] = ONCHIP_ADDR2(addr);
6982 REG_WR_DMAE(bp, reg, wb_write, 2);
6983 }
6984
6985 static void bnx2x_igu_clear_sb_gen(struct bnx2x *bp, u8 func,
6986 u8 idu_sb_id, bool is_Pf)
6987 {
6988 u32 data, ctl, cnt = 100;
6989 u32 igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA;
6990 u32 igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL;
6991 u32 igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4;
6992 u32 sb_bit = 1 << (idu_sb_id%32);
6993 u32 func_encode = func | (is_Pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT;
6994 u32 addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id;
6995
6996 /* Not supported in BC mode */
6997 if (CHIP_INT_MODE_IS_BC(bp))
6998 return;
6999
7000 data = (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7001 << IGU_REGULAR_CLEANUP_TYPE_SHIFT) |
7002 IGU_REGULAR_CLEANUP_SET |
7003 IGU_REGULAR_BCLEANUP;
7004
7005 ctl = addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT |
7006 func_encode << IGU_CTRL_REG_FID_SHIFT |
7007 IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT;
7008
7009 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7010 data, igu_addr_data);
7011 REG_WR(bp, igu_addr_data, data);
7012 mmiowb();
7013 barrier();
7014 DP(NETIF_MSG_HW, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7015 ctl, igu_addr_ctl);
7016 REG_WR(bp, igu_addr_ctl, ctl);
7017 mmiowb();
7018 barrier();
7019
7020 /* wait for clean up to finish */
7021 while (!(REG_RD(bp, igu_addr_ack) & sb_bit) && --cnt)
7022 msleep(20);
7023
7024
7025 if (!(REG_RD(bp, igu_addr_ack) & sb_bit)) {
7026 DP(NETIF_MSG_HW,
7027 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7028 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt);
7029 }
7030 }
7031
7032 static void bnx2x_igu_clear_sb(struct bnx2x *bp, u8 idu_sb_id)
7033 {
7034 bnx2x_igu_clear_sb_gen(bp, BP_FUNC(bp), idu_sb_id, true /*PF*/);
7035 }
7036
7037 static void bnx2x_clear_func_ilt(struct bnx2x *bp, u32 func)
7038 {
7039 u32 i, base = FUNC_ILT_BASE(func);
7040 for (i = base; i < base + ILT_PER_FUNC; i++)
7041 bnx2x_ilt_wr(bp, i, 0);
7042 }
7043
7044 static int bnx2x_init_hw_func(struct bnx2x *bp)
7045 {
7046 int port = BP_PORT(bp);
7047 int func = BP_FUNC(bp);
7048 int init_phase = PHASE_PF0 + func;
7049 struct bnx2x_ilt *ilt = BP_ILT(bp);
7050 u16 cdu_ilt_start;
7051 u32 addr, val;
7052 u32 main_mem_base, main_mem_size, main_mem_prty_clr;
7053 int i, main_mem_width, rc;
7054
7055 DP(NETIF_MSG_HW, "starting func init func %d\n", func);
7056
7057 /* FLR cleanup - hmmm */
7058 if (!CHIP_IS_E1x(bp)) {
7059 rc = bnx2x_pf_flr_clnup(bp);
7060 if (rc)
7061 return rc;
7062 }
7063
7064 /* set MSI reconfigure capability */
7065 if (bp->common.int_block == INT_BLOCK_HC) {
7066 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0);
7067 val = REG_RD(bp, addr);
7068 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0;
7069 REG_WR(bp, addr, val);
7070 }
7071
7072 bnx2x_init_block(bp, BLOCK_PXP, init_phase);
7073 bnx2x_init_block(bp, BLOCK_PXP2, init_phase);
7074
7075 ilt = BP_ILT(bp);
7076 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start;
7077
7078 for (i = 0; i < L2_ILT_LINES(bp); i++) {
7079 ilt->lines[cdu_ilt_start + i].page = bp->context[i].vcxt;
7080 ilt->lines[cdu_ilt_start + i].page_mapping =
7081 bp->context[i].cxt_mapping;
7082 ilt->lines[cdu_ilt_start + i].size = bp->context[i].size;
7083 }
7084 bnx2x_ilt_init_op(bp, INITOP_SET);
7085
7086 #ifdef BCM_CNIC
7087 bnx2x_src_init_t2(bp, bp->t2, bp->t2_mapping, SRC_CONN_NUM);
7088
7089 /* T1 hash bits value determines the T1 number of entries */
7090 REG_WR(bp, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS);
7091 #endif
7092
7093 #ifndef BCM_CNIC
7094 /* set NIC mode */
7095 REG_WR(bp, PRS_REG_NIC_MODE, 1);
7096 #endif /* BCM_CNIC */
7097
7098 if (!CHIP_IS_E1x(bp)) {
7099 u32 pf_conf = IGU_PF_CONF_FUNC_EN;
7100
7101 /* Turn on a single ISR mode in IGU if driver is going to use
7102 * INT#x or MSI
7103 */
7104 if (!(bp->flags & USING_MSIX_FLAG))
7105 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
7106 /*
7107 * Timers workaround bug: function init part.
7108 * Need to wait 20msec after initializing ILT,
7109 * needed to make sure there are no requests in
7110 * one of the PXP internal queues with "old" ILT addresses
7111 */
7112 msleep(20);
7113 /*
7114 * Master enable - Due to WB DMAE writes performed before this
7115 * register is re-initialized as part of the regular function
7116 * init
7117 */
7118 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1);
7119 /* Enable the function in IGU */
7120 REG_WR(bp, IGU_REG_PF_CONFIGURATION, pf_conf);
7121 }
7122
7123 bp->dmae_ready = 1;
7124
7125 bnx2x_init_block(bp, BLOCK_PGLUE_B, init_phase);
7126
7127 if (!CHIP_IS_E1x(bp))
7128 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func);
7129
7130 bnx2x_init_block(bp, BLOCK_ATC, init_phase);
7131 bnx2x_init_block(bp, BLOCK_DMAE, init_phase);
7132 bnx2x_init_block(bp, BLOCK_NIG, init_phase);
7133 bnx2x_init_block(bp, BLOCK_SRC, init_phase);
7134 bnx2x_init_block(bp, BLOCK_MISC, init_phase);
7135 bnx2x_init_block(bp, BLOCK_TCM, init_phase);
7136 bnx2x_init_block(bp, BLOCK_UCM, init_phase);
7137 bnx2x_init_block(bp, BLOCK_CCM, init_phase);
7138 bnx2x_init_block(bp, BLOCK_XCM, init_phase);
7139 bnx2x_init_block(bp, BLOCK_TSEM, init_phase);
7140 bnx2x_init_block(bp, BLOCK_USEM, init_phase);
7141 bnx2x_init_block(bp, BLOCK_CSEM, init_phase);
7142 bnx2x_init_block(bp, BLOCK_XSEM, init_phase);
7143
7144 if (!CHIP_IS_E1x(bp))
7145 REG_WR(bp, QM_REG_PF_EN, 1);
7146
7147 if (!CHIP_IS_E1x(bp)) {
7148 REG_WR(bp, TSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7149 REG_WR(bp, USEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7150 REG_WR(bp, CSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7151 REG_WR(bp, XSEM_REG_VFPF_ERR_NUM, BNX2X_MAX_NUM_OF_VFS + func);
7152 }
7153 bnx2x_init_block(bp, BLOCK_QM, init_phase);
7154
7155 bnx2x_init_block(bp, BLOCK_TM, init_phase);
7156 bnx2x_init_block(bp, BLOCK_DORQ, init_phase);
7157 bnx2x_init_block(bp, BLOCK_BRB1, init_phase);
7158 bnx2x_init_block(bp, BLOCK_PRS, init_phase);
7159 bnx2x_init_block(bp, BLOCK_TSDM, init_phase);
7160 bnx2x_init_block(bp, BLOCK_CSDM, init_phase);
7161 bnx2x_init_block(bp, BLOCK_USDM, init_phase);
7162 bnx2x_init_block(bp, BLOCK_XSDM, init_phase);
7163 bnx2x_init_block(bp, BLOCK_UPB, init_phase);
7164 bnx2x_init_block(bp, BLOCK_XPB, init_phase);
7165 bnx2x_init_block(bp, BLOCK_PBF, init_phase);
7166 if (!CHIP_IS_E1x(bp))
7167 REG_WR(bp, PBF_REG_DISABLE_PF, 0);
7168
7169 bnx2x_init_block(bp, BLOCK_CDU, init_phase);
7170
7171 bnx2x_init_block(bp, BLOCK_CFC, init_phase);
7172
7173 if (!CHIP_IS_E1x(bp))
7174 REG_WR(bp, CFC_REG_WEAK_ENABLE_PF, 1);
7175
7176 if (IS_MF(bp)) {
7177 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 1);
7178 REG_WR(bp, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, bp->mf_ov);
7179 }
7180
7181 bnx2x_init_block(bp, BLOCK_MISC_AEU, init_phase);
7182
7183 /* HC init per function */
7184 if (bp->common.int_block == INT_BLOCK_HC) {
7185 if (CHIP_IS_E1H(bp)) {
7186 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7187
7188 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
7189 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
7190 }
7191 bnx2x_init_block(bp, BLOCK_HC, init_phase);
7192
7193 } else {
7194 int num_segs, sb_idx, prod_offset;
7195
7196 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0);
7197
7198 if (!CHIP_IS_E1x(bp)) {
7199 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
7200 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
7201 }
7202
7203 bnx2x_init_block(bp, BLOCK_IGU, init_phase);
7204
7205 if (!CHIP_IS_E1x(bp)) {
7206 int dsb_idx = 0;
7207 /**
7208 * Producer memory:
7209 * E2 mode: address 0-135 match to the mapping memory;
7210 * 136 - PF0 default prod; 137 - PF1 default prod;
7211 * 138 - PF2 default prod; 139 - PF3 default prod;
7212 * 140 - PF0 attn prod; 141 - PF1 attn prod;
7213 * 142 - PF2 attn prod; 143 - PF3 attn prod;
7214 * 144-147 reserved.
7215 *
7216 * E1.5 mode - In backward compatible mode;
7217 * for non default SB; each even line in the memory
7218 * holds the U producer and each odd line hold
7219 * the C producer. The first 128 producers are for
7220 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
7221 * producers are for the DSB for each PF.
7222 * Each PF has five segments: (the order inside each
7223 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
7224 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
7225 * 144-147 attn prods;
7226 */
7227 /* non-default-status-blocks */
7228 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7229 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS;
7230 for (sb_idx = 0; sb_idx < bp->igu_sb_cnt; sb_idx++) {
7231 prod_offset = (bp->igu_base_sb + sb_idx) *
7232 num_segs;
7233
7234 for (i = 0; i < num_segs; i++) {
7235 addr = IGU_REG_PROD_CONS_MEMORY +
7236 (prod_offset + i) * 4;
7237 REG_WR(bp, addr, 0);
7238 }
7239 /* send consumer update with value 0 */
7240 bnx2x_ack_sb(bp, bp->igu_base_sb + sb_idx,
7241 USTORM_ID, 0, IGU_INT_NOP, 1);
7242 bnx2x_igu_clear_sb(bp,
7243 bp->igu_base_sb + sb_idx);
7244 }
7245
7246 /* default-status-blocks */
7247 num_segs = CHIP_INT_MODE_IS_BC(bp) ?
7248 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS;
7249
7250 if (CHIP_MODE_IS_4_PORT(bp))
7251 dsb_idx = BP_FUNC(bp);
7252 else
7253 dsb_idx = BP_VN(bp);
7254
7255 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
7256 IGU_BC_BASE_DSB_PROD + dsb_idx :
7257 IGU_NORM_BASE_DSB_PROD + dsb_idx);
7258
7259 /*
7260 * igu prods come in chunks of E1HVN_MAX (4) -
7261 * does not matters what is the current chip mode
7262 */
7263 for (i = 0; i < (num_segs * E1HVN_MAX);
7264 i += E1HVN_MAX) {
7265 addr = IGU_REG_PROD_CONS_MEMORY +
7266 (prod_offset + i)*4;
7267 REG_WR(bp, addr, 0);
7268 }
7269 /* send consumer update with 0 */
7270 if (CHIP_INT_MODE_IS_BC(bp)) {
7271 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7272 USTORM_ID, 0, IGU_INT_NOP, 1);
7273 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7274 CSTORM_ID, 0, IGU_INT_NOP, 1);
7275 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7276 XSTORM_ID, 0, IGU_INT_NOP, 1);
7277 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7278 TSTORM_ID, 0, IGU_INT_NOP, 1);
7279 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7280 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7281 } else {
7282 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7283 USTORM_ID, 0, IGU_INT_NOP, 1);
7284 bnx2x_ack_sb(bp, bp->igu_dsb_id,
7285 ATTENTION_ID, 0, IGU_INT_NOP, 1);
7286 }
7287 bnx2x_igu_clear_sb(bp, bp->igu_dsb_id);
7288
7289 /* !!! these should become driver const once
7290 rf-tool supports split-68 const */
7291 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0);
7292 REG_WR(bp, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0);
7293 REG_WR(bp, IGU_REG_SB_MASK_LSB, 0);
7294 REG_WR(bp, IGU_REG_SB_MASK_MSB, 0);
7295 REG_WR(bp, IGU_REG_PBA_STATUS_LSB, 0);
7296 REG_WR(bp, IGU_REG_PBA_STATUS_MSB, 0);
7297 }
7298 }
7299
7300 /* Reset PCIE errors for debug */
7301 REG_WR(bp, 0x2114, 0xffffffff);
7302 REG_WR(bp, 0x2120, 0xffffffff);
7303
7304 if (CHIP_IS_E1x(bp)) {
7305 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
7306 main_mem_base = HC_REG_MAIN_MEMORY +
7307 BP_PORT(bp) * (main_mem_size * 4);
7308 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
7309 main_mem_width = 8;
7310
7311 val = REG_RD(bp, main_mem_prty_clr);
7312 if (val)
7313 DP(NETIF_MSG_HW,
7314 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
7315 val);
7316
7317 /* Clear "false" parity errors in MSI-X table */
7318 for (i = main_mem_base;
7319 i < main_mem_base + main_mem_size * 4;
7320 i += main_mem_width) {
7321 bnx2x_read_dmae(bp, i, main_mem_width / 4);
7322 bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
7323 i, main_mem_width / 4);
7324 }
7325 /* Clear HC parity attention */
7326 REG_RD(bp, main_mem_prty_clr);
7327 }
7328
7329 #ifdef BNX2X_STOP_ON_ERROR
7330 /* Enable STORMs SP logging */
7331 REG_WR8(bp, BAR_USTRORM_INTMEM +
7332 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7333 REG_WR8(bp, BAR_TSTRORM_INTMEM +
7334 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7335 REG_WR8(bp, BAR_CSTRORM_INTMEM +
7336 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7337 REG_WR8(bp, BAR_XSTRORM_INTMEM +
7338 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp)), 1);
7339 #endif
7340
7341 bnx2x_phy_probe(&bp->link_params);
7342
7343 return 0;
7344 }
7345
7346
7347 void bnx2x_free_mem(struct bnx2x *bp)
7348 {
7349 int i;
7350
7351 /* fastpath */
7352 bnx2x_free_fp_mem(bp);
7353 /* end of fastpath */
7354
7355 BNX2X_PCI_FREE(bp->def_status_blk, bp->def_status_blk_mapping,
7356 sizeof(struct host_sp_status_block));
7357
7358 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7359 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7360
7361 BNX2X_PCI_FREE(bp->slowpath, bp->slowpath_mapping,
7362 sizeof(struct bnx2x_slowpath));
7363
7364 for (i = 0; i < L2_ILT_LINES(bp); i++)
7365 BNX2X_PCI_FREE(bp->context[i].vcxt, bp->context[i].cxt_mapping,
7366 bp->context[i].size);
7367 bnx2x_ilt_mem_op(bp, ILT_MEMOP_FREE);
7368
7369 BNX2X_FREE(bp->ilt->lines);
7370
7371 #ifdef BCM_CNIC
7372 if (!CHIP_IS_E1x(bp))
7373 BNX2X_PCI_FREE(bp->cnic_sb.e2_sb, bp->cnic_sb_mapping,
7374 sizeof(struct host_hc_status_block_e2));
7375 else
7376 BNX2X_PCI_FREE(bp->cnic_sb.e1x_sb, bp->cnic_sb_mapping,
7377 sizeof(struct host_hc_status_block_e1x));
7378
7379 BNX2X_PCI_FREE(bp->t2, bp->t2_mapping, SRC_T2_SZ);
7380 #endif
7381
7382 BNX2X_PCI_FREE(bp->spq, bp->spq_mapping, BCM_PAGE_SIZE);
7383
7384 BNX2X_PCI_FREE(bp->eq_ring, bp->eq_mapping,
7385 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7386 }
7387
7388 static int bnx2x_alloc_fw_stats_mem(struct bnx2x *bp)
7389 {
7390 int num_groups;
7391 int is_fcoe_stats = NO_FCOE(bp) ? 0 : 1;
7392
7393 /* number of queues for statistics is number of eth queues + FCoE */
7394 u8 num_queue_stats = BNX2X_NUM_ETH_QUEUES(bp) + is_fcoe_stats;
7395
7396 /* Total number of FW statistics requests =
7397 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7398 * num of queues
7399 */
7400 bp->fw_stats_num = 2 + is_fcoe_stats + num_queue_stats;
7401
7402
7403 /* Request is built from stats_query_header and an array of
7404 * stats_query_cmd_group each of which contains
7405 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7406 * configured in the stats_query_header.
7407 */
7408 num_groups = ((bp->fw_stats_num) / STATS_QUERY_CMD_COUNT) +
7409 (((bp->fw_stats_num) % STATS_QUERY_CMD_COUNT) ? 1 : 0);
7410
7411 bp->fw_stats_req_sz = sizeof(struct stats_query_header) +
7412 num_groups * sizeof(struct stats_query_cmd_group);
7413
7414 /* Data for statistics requests + stats_conter
7415 *
7416 * stats_counter holds per-STORM counters that are incremented
7417 * when STORM has finished with the current request.
7418 *
7419 * memory for FCoE offloaded statistics are counted anyway,
7420 * even if they will not be sent.
7421 */
7422 bp->fw_stats_data_sz = sizeof(struct per_port_stats) +
7423 sizeof(struct per_pf_stats) +
7424 sizeof(struct fcoe_statistics_params) +
7425 sizeof(struct per_queue_stats) * num_queue_stats +
7426 sizeof(struct stats_counter);
7427
7428 BNX2X_PCI_ALLOC(bp->fw_stats, &bp->fw_stats_mapping,
7429 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7430
7431 /* Set shortcuts */
7432 bp->fw_stats_req = (struct bnx2x_fw_stats_req *)bp->fw_stats;
7433 bp->fw_stats_req_mapping = bp->fw_stats_mapping;
7434
7435 bp->fw_stats_data = (struct bnx2x_fw_stats_data *)
7436 ((u8 *)bp->fw_stats + bp->fw_stats_req_sz);
7437
7438 bp->fw_stats_data_mapping = bp->fw_stats_mapping +
7439 bp->fw_stats_req_sz;
7440 return 0;
7441
7442 alloc_mem_err:
7443 BNX2X_PCI_FREE(bp->fw_stats, bp->fw_stats_mapping,
7444 bp->fw_stats_data_sz + bp->fw_stats_req_sz);
7445 BNX2X_ERR("Can't allocate memory\n");
7446 return -ENOMEM;
7447 }
7448
7449
7450 int bnx2x_alloc_mem(struct bnx2x *bp)
7451 {
7452 int i, allocated, context_size;
7453
7454 #ifdef BCM_CNIC
7455 if (!CHIP_IS_E1x(bp))
7456 /* size = the status block + ramrod buffers */
7457 BNX2X_PCI_ALLOC(bp->cnic_sb.e2_sb, &bp->cnic_sb_mapping,
7458 sizeof(struct host_hc_status_block_e2));
7459 else
7460 BNX2X_PCI_ALLOC(bp->cnic_sb.e1x_sb, &bp->cnic_sb_mapping,
7461 sizeof(struct host_hc_status_block_e1x));
7462
7463 /* allocate searcher T2 table */
7464 BNX2X_PCI_ALLOC(bp->t2, &bp->t2_mapping, SRC_T2_SZ);
7465 #endif
7466
7467
7468 BNX2X_PCI_ALLOC(bp->def_status_blk, &bp->def_status_blk_mapping,
7469 sizeof(struct host_sp_status_block));
7470
7471 BNX2X_PCI_ALLOC(bp->slowpath, &bp->slowpath_mapping,
7472 sizeof(struct bnx2x_slowpath));
7473
7474 #ifdef BCM_CNIC
7475 /* write address to which L5 should insert its values */
7476 bp->cnic_eth_dev.addr_drv_info_to_mcp = &bp->slowpath->drv_info_to_mcp;
7477 #endif
7478
7479 /* Allocated memory for FW statistics */
7480 if (bnx2x_alloc_fw_stats_mem(bp))
7481 goto alloc_mem_err;
7482
7483 /* Allocate memory for CDU context:
7484 * This memory is allocated separately and not in the generic ILT
7485 * functions because CDU differs in few aspects:
7486 * 1. There are multiple entities allocating memory for context -
7487 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
7488 * its own ILT lines.
7489 * 2. Since CDU page-size is not a single 4KB page (which is the case
7490 * for the other ILT clients), to be efficient we want to support
7491 * allocation of sub-page-size in the last entry.
7492 * 3. Context pointers are used by the driver to pass to FW / update
7493 * the context (for the other ILT clients the pointers are used just to
7494 * free the memory during unload).
7495 */
7496 context_size = sizeof(union cdu_context) * BNX2X_L2_CID_COUNT(bp);
7497
7498 for (i = 0, allocated = 0; allocated < context_size; i++) {
7499 bp->context[i].size = min(CDU_ILT_PAGE_SZ,
7500 (context_size - allocated));
7501 BNX2X_PCI_ALLOC(bp->context[i].vcxt,
7502 &bp->context[i].cxt_mapping,
7503 bp->context[i].size);
7504 allocated += bp->context[i].size;
7505 }
7506 BNX2X_ALLOC(bp->ilt->lines, sizeof(struct ilt_line) * ILT_MAX_LINES);
7507
7508 if (bnx2x_ilt_mem_op(bp, ILT_MEMOP_ALLOC))
7509 goto alloc_mem_err;
7510
7511 /* Slow path ring */
7512 BNX2X_PCI_ALLOC(bp->spq, &bp->spq_mapping, BCM_PAGE_SIZE);
7513
7514 /* EQ */
7515 BNX2X_PCI_ALLOC(bp->eq_ring, &bp->eq_mapping,
7516 BCM_PAGE_SIZE * NUM_EQ_PAGES);
7517
7518
7519 /* fastpath */
7520 /* need to be done at the end, since it's self adjusting to amount
7521 * of memory available for RSS queues
7522 */
7523 if (bnx2x_alloc_fp_mem(bp))
7524 goto alloc_mem_err;
7525 return 0;
7526
7527 alloc_mem_err:
7528 bnx2x_free_mem(bp);
7529 BNX2X_ERR("Can't allocate memory\n");
7530 return -ENOMEM;
7531 }
7532
7533 /*
7534 * Init service functions
7535 */
7536
7537 int bnx2x_set_mac_one(struct bnx2x *bp, u8 *mac,
7538 struct bnx2x_vlan_mac_obj *obj, bool set,
7539 int mac_type, unsigned long *ramrod_flags)
7540 {
7541 int rc;
7542 struct bnx2x_vlan_mac_ramrod_params ramrod_param;
7543
7544 memset(&ramrod_param, 0, sizeof(ramrod_param));
7545
7546 /* Fill general parameters */
7547 ramrod_param.vlan_mac_obj = obj;
7548 ramrod_param.ramrod_flags = *ramrod_flags;
7549
7550 /* Fill a user request section if needed */
7551 if (!test_bit(RAMROD_CONT, ramrod_flags)) {
7552 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN);
7553
7554 __set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);
7555
7556 /* Set the command: ADD or DEL */
7557 if (set)
7558 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_ADD;
7559 else
7560 ramrod_param.user_req.cmd = BNX2X_VLAN_MAC_DEL;
7561 }
7562
7563 rc = bnx2x_config_vlan_mac(bp, &ramrod_param);
7564
7565 if (rc == -EEXIST) {
7566 DP(BNX2X_MSG_SP, "Failed to schedule ADD operations: %d\n", rc);
7567 /* do not treat adding same MAC as error */
7568 rc = 0;
7569 } else if (rc < 0)
7570 BNX2X_ERR("%s MAC failed\n", (set ? "Set" : "Del"));
7571
7572 return rc;
7573 }
7574
7575 int bnx2x_del_all_macs(struct bnx2x *bp,
7576 struct bnx2x_vlan_mac_obj *mac_obj,
7577 int mac_type, bool wait_for_comp)
7578 {
7579 int rc;
7580 unsigned long ramrod_flags = 0, vlan_mac_flags = 0;
7581
7582 /* Wait for completion of requested */
7583 if (wait_for_comp)
7584 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7585
7586 /* Set the mac type of addresses we want to clear */
7587 __set_bit(mac_type, &vlan_mac_flags);
7588
7589 rc = mac_obj->delete_all(bp, mac_obj, &vlan_mac_flags, &ramrod_flags);
7590 if (rc < 0)
7591 BNX2X_ERR("Failed to delete MACs: %d\n", rc);
7592
7593 return rc;
7594 }
7595
7596 int bnx2x_set_eth_mac(struct bnx2x *bp, bool set)
7597 {
7598 unsigned long ramrod_flags = 0;
7599
7600 #ifdef BCM_CNIC
7601 if (is_zero_ether_addr(bp->dev->dev_addr) &&
7602 (IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp))) {
7603 DP(NETIF_MSG_IFUP | NETIF_MSG_IFDOWN,
7604 "Ignoring Zero MAC for STORAGE SD mode\n");
7605 return 0;
7606 }
7607 #endif
7608
7609 DP(NETIF_MSG_IFUP, "Adding Eth MAC\n");
7610
7611 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
7612 /* Eth MAC is set on RSS leading client (fp[0]) */
7613 return bnx2x_set_mac_one(bp, bp->dev->dev_addr, &bp->sp_objs->mac_obj,
7614 set, BNX2X_ETH_MAC, &ramrod_flags);
7615 }
7616
7617 int bnx2x_setup_leading(struct bnx2x *bp)
7618 {
7619 return bnx2x_setup_queue(bp, &bp->fp[0], 1);
7620 }
7621
7622 /**
7623 * bnx2x_set_int_mode - configure interrupt mode
7624 *
7625 * @bp: driver handle
7626 *
7627 * In case of MSI-X it will also try to enable MSI-X.
7628 */
7629 void bnx2x_set_int_mode(struct bnx2x *bp)
7630 {
7631 switch (int_mode) {
7632 case INT_MODE_MSI:
7633 bnx2x_enable_msi(bp);
7634 /* falling through... */
7635 case INT_MODE_INTx:
7636 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7637 BNX2X_DEV_INFO("set number of queues to 1\n");
7638 break;
7639 default:
7640 /* if we can't use MSI-X we only need one fp,
7641 * so try to enable MSI-X with the requested number of fp's
7642 * and fallback to MSI or legacy INTx with one fp
7643 */
7644 if (bnx2x_enable_msix(bp) ||
7645 bp->flags & USING_SINGLE_MSIX_FLAG) {
7646 /* failed to enable multiple MSI-X */
7647 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
7648 bp->num_queues, 1 + NON_ETH_CONTEXT_USE);
7649
7650 bp->num_queues = 1 + NON_ETH_CONTEXT_USE;
7651
7652 /* Try to enable MSI */
7653 if (!(bp->flags & USING_SINGLE_MSIX_FLAG) &&
7654 !(bp->flags & DISABLE_MSI_FLAG))
7655 bnx2x_enable_msi(bp);
7656 }
7657 break;
7658 }
7659 }
7660
7661 /* must be called prioir to any HW initializations */
7662 static inline u16 bnx2x_cid_ilt_lines(struct bnx2x *bp)
7663 {
7664 return L2_ILT_LINES(bp);
7665 }
7666
7667 void bnx2x_ilt_set_info(struct bnx2x *bp)
7668 {
7669 struct ilt_client_info *ilt_client;
7670 struct bnx2x_ilt *ilt = BP_ILT(bp);
7671 u16 line = 0;
7672
7673 ilt->start_line = FUNC_ILT_BASE(BP_FUNC(bp));
7674 DP(BNX2X_MSG_SP, "ilt starts at line %d\n", ilt->start_line);
7675
7676 /* CDU */
7677 ilt_client = &ilt->clients[ILT_CLIENT_CDU];
7678 ilt_client->client_num = ILT_CLIENT_CDU;
7679 ilt_client->page_size = CDU_ILT_PAGE_SZ;
7680 ilt_client->flags = ILT_CLIENT_SKIP_MEM;
7681 ilt_client->start = line;
7682 line += bnx2x_cid_ilt_lines(bp);
7683 #ifdef BCM_CNIC
7684 line += CNIC_ILT_LINES;
7685 #endif
7686 ilt_client->end = line - 1;
7687
7688 DP(NETIF_MSG_IFUP, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7689 ilt_client->start,
7690 ilt_client->end,
7691 ilt_client->page_size,
7692 ilt_client->flags,
7693 ilog2(ilt_client->page_size >> 12));
7694
7695 /* QM */
7696 if (QM_INIT(bp->qm_cid_count)) {
7697 ilt_client = &ilt->clients[ILT_CLIENT_QM];
7698 ilt_client->client_num = ILT_CLIENT_QM;
7699 ilt_client->page_size = QM_ILT_PAGE_SZ;
7700 ilt_client->flags = 0;
7701 ilt_client->start = line;
7702
7703 /* 4 bytes for each cid */
7704 line += DIV_ROUND_UP(bp->qm_cid_count * QM_QUEUES_PER_FUNC * 4,
7705 QM_ILT_PAGE_SZ);
7706
7707 ilt_client->end = line - 1;
7708
7709 DP(NETIF_MSG_IFUP,
7710 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7711 ilt_client->start,
7712 ilt_client->end,
7713 ilt_client->page_size,
7714 ilt_client->flags,
7715 ilog2(ilt_client->page_size >> 12));
7716
7717 }
7718 /* SRC */
7719 ilt_client = &ilt->clients[ILT_CLIENT_SRC];
7720 #ifdef BCM_CNIC
7721 ilt_client->client_num = ILT_CLIENT_SRC;
7722 ilt_client->page_size = SRC_ILT_PAGE_SZ;
7723 ilt_client->flags = 0;
7724 ilt_client->start = line;
7725 line += SRC_ILT_LINES;
7726 ilt_client->end = line - 1;
7727
7728 DP(NETIF_MSG_IFUP,
7729 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7730 ilt_client->start,
7731 ilt_client->end,
7732 ilt_client->page_size,
7733 ilt_client->flags,
7734 ilog2(ilt_client->page_size >> 12));
7735
7736 #else
7737 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7738 #endif
7739
7740 /* TM */
7741 ilt_client = &ilt->clients[ILT_CLIENT_TM];
7742 #ifdef BCM_CNIC
7743 ilt_client->client_num = ILT_CLIENT_TM;
7744 ilt_client->page_size = TM_ILT_PAGE_SZ;
7745 ilt_client->flags = 0;
7746 ilt_client->start = line;
7747 line += TM_ILT_LINES;
7748 ilt_client->end = line - 1;
7749
7750 DP(NETIF_MSG_IFUP,
7751 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7752 ilt_client->start,
7753 ilt_client->end,
7754 ilt_client->page_size,
7755 ilt_client->flags,
7756 ilog2(ilt_client->page_size >> 12));
7757
7758 #else
7759 ilt_client->flags = (ILT_CLIENT_SKIP_INIT | ILT_CLIENT_SKIP_MEM);
7760 #endif
7761 BUG_ON(line > ILT_MAX_LINES);
7762 }
7763
7764 /**
7765 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7766 *
7767 * @bp: driver handle
7768 * @fp: pointer to fastpath
7769 * @init_params: pointer to parameters structure
7770 *
7771 * parameters configured:
7772 * - HC configuration
7773 * - Queue's CDU context
7774 */
7775 static void bnx2x_pf_q_prep_init(struct bnx2x *bp,
7776 struct bnx2x_fastpath *fp, struct bnx2x_queue_init_params *init_params)
7777 {
7778
7779 u8 cos;
7780 int cxt_index, cxt_offset;
7781
7782 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7783 if (!IS_FCOE_FP(fp)) {
7784 __set_bit(BNX2X_Q_FLG_HC, &init_params->rx.flags);
7785 __set_bit(BNX2X_Q_FLG_HC, &init_params->tx.flags);
7786
7787 /* If HC is supporterd, enable host coalescing in the transition
7788 * to INIT state.
7789 */
7790 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->rx.flags);
7791 __set_bit(BNX2X_Q_FLG_HC_EN, &init_params->tx.flags);
7792
7793 /* HC rate */
7794 init_params->rx.hc_rate = bp->rx_ticks ?
7795 (1000000 / bp->rx_ticks) : 0;
7796 init_params->tx.hc_rate = bp->tx_ticks ?
7797 (1000000 / bp->tx_ticks) : 0;
7798
7799 /* FW SB ID */
7800 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id =
7801 fp->fw_sb_id;
7802
7803 /*
7804 * CQ index among the SB indices: FCoE clients uses the default
7805 * SB, therefore it's different.
7806 */
7807 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS;
7808 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS;
7809 }
7810
7811 /* set maximum number of COSs supported by this queue */
7812 init_params->max_cos = fp->max_cos;
7813
7814 DP(NETIF_MSG_IFUP, "fp: %d setting queue params max cos to: %d\n",
7815 fp->index, init_params->max_cos);
7816
7817 /* set the context pointers queue object */
7818 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) {
7819 cxt_index = fp->txdata_ptr[cos]->cid / ILT_PAGE_CIDS;
7820 cxt_offset = fp->txdata_ptr[cos]->cid - (cxt_index *
7821 ILT_PAGE_CIDS);
7822 init_params->cxts[cos] =
7823 &bp->context[cxt_index].vcxt[cxt_offset].eth;
7824 }
7825 }
7826
7827 int bnx2x_setup_tx_only(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7828 struct bnx2x_queue_state_params *q_params,
7829 struct bnx2x_queue_setup_tx_only_params *tx_only_params,
7830 int tx_index, bool leading)
7831 {
7832 memset(tx_only_params, 0, sizeof(*tx_only_params));
7833
7834 /* Set the command */
7835 q_params->cmd = BNX2X_Q_CMD_SETUP_TX_ONLY;
7836
7837 /* Set tx-only QUEUE flags: don't zero statistics */
7838 tx_only_params->flags = bnx2x_get_common_flags(bp, fp, false);
7839
7840 /* choose the index of the cid to send the slow path on */
7841 tx_only_params->cid_index = tx_index;
7842
7843 /* Set general TX_ONLY_SETUP parameters */
7844 bnx2x_pf_q_prep_general(bp, fp, &tx_only_params->gen_params, tx_index);
7845
7846 /* Set Tx TX_ONLY_SETUP parameters */
7847 bnx2x_pf_tx_q_prep(bp, fp, &tx_only_params->txq_params, tx_index);
7848
7849 DP(NETIF_MSG_IFUP,
7850 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7851 tx_index, q_params->q_obj->cids[FIRST_TX_COS_INDEX],
7852 q_params->q_obj->cids[tx_index], q_params->q_obj->cl_id,
7853 tx_only_params->gen_params.spcl_id, tx_only_params->flags);
7854
7855 /* send the ramrod */
7856 return bnx2x_queue_state_change(bp, q_params);
7857 }
7858
7859
7860 /**
7861 * bnx2x_setup_queue - setup queue
7862 *
7863 * @bp: driver handle
7864 * @fp: pointer to fastpath
7865 * @leading: is leading
7866 *
7867 * This function performs 2 steps in a Queue state machine
7868 * actually: 1) RESET->INIT 2) INIT->SETUP
7869 */
7870
7871 int bnx2x_setup_queue(struct bnx2x *bp, struct bnx2x_fastpath *fp,
7872 bool leading)
7873 {
7874 struct bnx2x_queue_state_params q_params = {NULL};
7875 struct bnx2x_queue_setup_params *setup_params =
7876 &q_params.params.setup;
7877 struct bnx2x_queue_setup_tx_only_params *tx_only_params =
7878 &q_params.params.tx_only;
7879 int rc;
7880 u8 tx_index;
7881
7882 DP(NETIF_MSG_IFUP, "setting up queue %d\n", fp->index);
7883
7884 /* reset IGU state skip FCoE L2 queue */
7885 if (!IS_FCOE_FP(fp))
7886 bnx2x_ack_sb(bp, fp->igu_sb_id, USTORM_ID, 0,
7887 IGU_INT_ENABLE, 0);
7888
7889 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7890 /* We want to wait for completion in this context */
7891 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7892
7893 /* Prepare the INIT parameters */
7894 bnx2x_pf_q_prep_init(bp, fp, &q_params.params.init);
7895
7896 /* Set the command */
7897 q_params.cmd = BNX2X_Q_CMD_INIT;
7898
7899 /* Change the state to INIT */
7900 rc = bnx2x_queue_state_change(bp, &q_params);
7901 if (rc) {
7902 BNX2X_ERR("Queue(%d) INIT failed\n", fp->index);
7903 return rc;
7904 }
7905
7906 DP(NETIF_MSG_IFUP, "init complete\n");
7907
7908
7909 /* Now move the Queue to the SETUP state... */
7910 memset(setup_params, 0, sizeof(*setup_params));
7911
7912 /* Set QUEUE flags */
7913 setup_params->flags = bnx2x_get_q_flags(bp, fp, leading);
7914
7915 /* Set general SETUP parameters */
7916 bnx2x_pf_q_prep_general(bp, fp, &setup_params->gen_params,
7917 FIRST_TX_COS_INDEX);
7918
7919 bnx2x_pf_rx_q_prep(bp, fp, &setup_params->pause_params,
7920 &setup_params->rxq_params);
7921
7922 bnx2x_pf_tx_q_prep(bp, fp, &setup_params->txq_params,
7923 FIRST_TX_COS_INDEX);
7924
7925 /* Set the command */
7926 q_params.cmd = BNX2X_Q_CMD_SETUP;
7927
7928 /* Change the state to SETUP */
7929 rc = bnx2x_queue_state_change(bp, &q_params);
7930 if (rc) {
7931 BNX2X_ERR("Queue(%d) SETUP failed\n", fp->index);
7932 return rc;
7933 }
7934
7935 /* loop through the relevant tx-only indices */
7936 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7937 tx_index < fp->max_cos;
7938 tx_index++) {
7939
7940 /* prepare and send tx-only ramrod*/
7941 rc = bnx2x_setup_tx_only(bp, fp, &q_params,
7942 tx_only_params, tx_index, leading);
7943 if (rc) {
7944 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7945 fp->index, tx_index);
7946 return rc;
7947 }
7948 }
7949
7950 return rc;
7951 }
7952
7953 static int bnx2x_stop_queue(struct bnx2x *bp, int index)
7954 {
7955 struct bnx2x_fastpath *fp = &bp->fp[index];
7956 struct bnx2x_fp_txdata *txdata;
7957 struct bnx2x_queue_state_params q_params = {NULL};
7958 int rc, tx_index;
7959
7960 DP(NETIF_MSG_IFDOWN, "stopping queue %d cid %d\n", index, fp->cid);
7961
7962 q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
7963 /* We want to wait for completion in this context */
7964 __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
7965
7966
7967 /* close tx-only connections */
7968 for (tx_index = FIRST_TX_ONLY_COS_INDEX;
7969 tx_index < fp->max_cos;
7970 tx_index++){
7971
7972 /* ascertain this is a normal queue*/
7973 txdata = fp->txdata_ptr[tx_index];
7974
7975 DP(NETIF_MSG_IFDOWN, "stopping tx-only queue %d\n",
7976 txdata->txq_index);
7977
7978 /* send halt terminate on tx-only connection */
7979 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
7980 memset(&q_params.params.terminate, 0,
7981 sizeof(q_params.params.terminate));
7982 q_params.params.terminate.cid_index = tx_index;
7983
7984 rc = bnx2x_queue_state_change(bp, &q_params);
7985 if (rc)
7986 return rc;
7987
7988 /* send halt terminate on tx-only connection */
7989 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
7990 memset(&q_params.params.cfc_del, 0,
7991 sizeof(q_params.params.cfc_del));
7992 q_params.params.cfc_del.cid_index = tx_index;
7993 rc = bnx2x_queue_state_change(bp, &q_params);
7994 if (rc)
7995 return rc;
7996 }
7997 /* Stop the primary connection: */
7998 /* ...halt the connection */
7999 q_params.cmd = BNX2X_Q_CMD_HALT;
8000 rc = bnx2x_queue_state_change(bp, &q_params);
8001 if (rc)
8002 return rc;
8003
8004 /* ...terminate the connection */
8005 q_params.cmd = BNX2X_Q_CMD_TERMINATE;
8006 memset(&q_params.params.terminate, 0,
8007 sizeof(q_params.params.terminate));
8008 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX;
8009 rc = bnx2x_queue_state_change(bp, &q_params);
8010 if (rc)
8011 return rc;
8012 /* ...delete cfc entry */
8013 q_params.cmd = BNX2X_Q_CMD_CFC_DEL;
8014 memset(&q_params.params.cfc_del, 0,
8015 sizeof(q_params.params.cfc_del));
8016 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX;
8017 return bnx2x_queue_state_change(bp, &q_params);
8018 }
8019
8020
8021 static void bnx2x_reset_func(struct bnx2x *bp)
8022 {
8023 int port = BP_PORT(bp);
8024 int func = BP_FUNC(bp);
8025 int i;
8026
8027 /* Disable the function in the FW */
8028 REG_WR8(bp, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0);
8029 REG_WR8(bp, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0);
8030 REG_WR8(bp, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0);
8031 REG_WR8(bp, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0);
8032
8033 /* FP SBs */
8034 for_each_eth_queue(bp, i) {
8035 struct bnx2x_fastpath *fp = &bp->fp[i];
8036 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8037 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id),
8038 SB_DISABLED);
8039 }
8040
8041 #ifdef BCM_CNIC
8042 /* CNIC SB */
8043 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8044 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp)),
8045 SB_DISABLED);
8046 #endif
8047 /* SP SB */
8048 REG_WR8(bp, BAR_CSTRORM_INTMEM +
8049 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func),
8050 SB_DISABLED);
8051
8052 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++)
8053 REG_WR(bp, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func),
8054 0);
8055
8056 /* Configure IGU */
8057 if (bp->common.int_block == INT_BLOCK_HC) {
8058 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, 0);
8059 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, 0);
8060 } else {
8061 REG_WR(bp, IGU_REG_LEADING_EDGE_LATCH, 0);
8062 REG_WR(bp, IGU_REG_TRAILING_EDGE_LATCH, 0);
8063 }
8064
8065 #ifdef BCM_CNIC
8066 /* Disable Timer scan */
8067 REG_WR(bp, TM_REG_EN_LINEAR0_TIMER + port*4, 0);
8068 /*
8069 * Wait for at least 10ms and up to 2 second for the timers scan to
8070 * complete
8071 */
8072 for (i = 0; i < 200; i++) {
8073 msleep(10);
8074 if (!REG_RD(bp, TM_REG_LIN0_SCAN_ON + port*4))
8075 break;
8076 }
8077 #endif
8078 /* Clear ILT */
8079 bnx2x_clear_func_ilt(bp, func);
8080
8081 /* Timers workaround bug for E2: if this is vnic-3,
8082 * we need to set the entire ilt range for this timers.
8083 */
8084 if (!CHIP_IS_E1x(bp) && BP_VN(bp) == 3) {
8085 struct ilt_client_info ilt_cli;
8086 /* use dummy TM client */
8087 memset(&ilt_cli, 0, sizeof(struct ilt_client_info));
8088 ilt_cli.start = 0;
8089 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1;
8090 ilt_cli.client_num = ILT_CLIENT_TM;
8091
8092 bnx2x_ilt_boundry_init_op(bp, &ilt_cli, 0, INITOP_CLEAR);
8093 }
8094
8095 /* this assumes that reset_port() called before reset_func()*/
8096 if (!CHIP_IS_E1x(bp))
8097 bnx2x_pf_disable(bp);
8098
8099 bp->dmae_ready = 0;
8100 }
8101
8102 static void bnx2x_reset_port(struct bnx2x *bp)
8103 {
8104 int port = BP_PORT(bp);
8105 u32 val;
8106
8107 /* Reset physical Link */
8108 bnx2x__link_reset(bp);
8109
8110 REG_WR(bp, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0);
8111
8112 /* Do not rcv packets to BRB */
8113 REG_WR(bp, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0);
8114 /* Do not direct rcv packets that are not for MCP to the BRB */
8115 REG_WR(bp, (port ? NIG_REG_LLH1_BRB1_NOT_MCP :
8116 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0);
8117
8118 /* Configure AEU */
8119 REG_WR(bp, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0);
8120
8121 msleep(100);
8122 /* Check for BRB port occupancy */
8123 val = REG_RD(bp, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4);
8124 if (val)
8125 DP(NETIF_MSG_IFDOWN,
8126 "BRB1 is not empty %d blocks are occupied\n", val);
8127
8128 /* TODO: Close Doorbell port? */
8129 }
8130
8131 static int bnx2x_reset_hw(struct bnx2x *bp, u32 load_code)
8132 {
8133 struct bnx2x_func_state_params func_params = {NULL};
8134
8135 /* Prepare parameters for function state transitions */
8136 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8137
8138 func_params.f_obj = &bp->func_obj;
8139 func_params.cmd = BNX2X_F_CMD_HW_RESET;
8140
8141 func_params.params.hw_init.load_phase = load_code;
8142
8143 return bnx2x_func_state_change(bp, &func_params);
8144 }
8145
8146 static int bnx2x_func_stop(struct bnx2x *bp)
8147 {
8148 struct bnx2x_func_state_params func_params = {NULL};
8149 int rc;
8150
8151 /* Prepare parameters for function state transitions */
8152 __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
8153 func_params.f_obj = &bp->func_obj;
8154 func_params.cmd = BNX2X_F_CMD_STOP;
8155
8156 /*
8157 * Try to stop the function the 'good way'. If fails (in case
8158 * of a parity error during bnx2x_chip_cleanup()) and we are
8159 * not in a debug mode, perform a state transaction in order to
8160 * enable further HW_RESET transaction.
8161 */
8162 rc = bnx2x_func_state_change(bp, &func_params);
8163 if (rc) {
8164 #ifdef BNX2X_STOP_ON_ERROR
8165 return rc;
8166 #else
8167 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
8168 __set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);
8169 return bnx2x_func_state_change(bp, &func_params);
8170 #endif
8171 }
8172
8173 return 0;
8174 }
8175
8176 /**
8177 * bnx2x_send_unload_req - request unload mode from the MCP.
8178 *
8179 * @bp: driver handle
8180 * @unload_mode: requested function's unload mode
8181 *
8182 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
8183 */
8184 u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
8185 {
8186 u32 reset_code = 0;
8187 int port = BP_PORT(bp);
8188
8189 /* Select the UNLOAD request mode */
8190 if (unload_mode == UNLOAD_NORMAL)
8191 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8192
8193 else if (bp->flags & NO_WOL_FLAG)
8194 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP;
8195
8196 else if (bp->wol) {
8197 u32 emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
8198 u8 *mac_addr = bp->dev->dev_addr;
8199 u32 val;
8200 u16 pmc;
8201
8202 /* The mac address is written to entries 1-4 to
8203 * preserve entry 0 which is used by the PMF
8204 */
8205 u8 entry = (BP_VN(bp) + 1)*8;
8206
8207 val = (mac_addr[0] << 8) | mac_addr[1];
8208 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
8209
8210 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
8211 (mac_addr[4] << 8) | mac_addr[5];
8212 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val);
8213
8214 /* Enable the PME and clear the status */
8215 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, &pmc);
8216 pmc |= PCI_PM_CTRL_PME_ENABLE | PCI_PM_CTRL_PME_STATUS;
8217 pci_write_config_word(bp->pdev, bp->pm_cap + PCI_PM_CTRL, pmc);
8218
8219 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN;
8220
8221 } else
8222 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS;
8223
8224 /* Send the request to the MCP */
8225 if (!BP_NOMCP(bp))
8226 reset_code = bnx2x_fw_command(bp, reset_code, 0);
8227 else {
8228 int path = BP_PATH(bp);
8229
8230 DP(NETIF_MSG_IFDOWN, "NO MCP - load counts[%d] %d, %d, %d\n",
8231 path, load_count[path][0], load_count[path][1],
8232 load_count[path][2]);
8233 load_count[path][0]--;
8234 load_count[path][1 + port]--;
8235 DP(NETIF_MSG_IFDOWN, "NO MCP - new load counts[%d] %d, %d, %d\n",
8236 path, load_count[path][0], load_count[path][1],
8237 load_count[path][2]);
8238 if (load_count[path][0] == 0)
8239 reset_code = FW_MSG_CODE_DRV_UNLOAD_COMMON;
8240 else if (load_count[path][1 + port] == 0)
8241 reset_code = FW_MSG_CODE_DRV_UNLOAD_PORT;
8242 else
8243 reset_code = FW_MSG_CODE_DRV_UNLOAD_FUNCTION;
8244 }
8245
8246 return reset_code;
8247 }
8248
8249 /**
8250 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
8251 *
8252 * @bp: driver handle
8253 */
8254 void bnx2x_send_unload_done(struct bnx2x *bp)
8255 {
8256 /* Report UNLOAD_DONE to MCP */
8257 if (!BP_NOMCP(bp))
8258 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8259 }
8260
8261 static int bnx2x_func_wait_started(struct bnx2x *bp)
8262 {
8263 int tout = 50;
8264 int msix = (bp->flags & USING_MSIX_FLAG) ? 1 : 0;
8265
8266 if (!bp->port.pmf)
8267 return 0;
8268
8269 /*
8270 * (assumption: No Attention from MCP at this stage)
8271 * PMF probably in the middle of TXdisable/enable transaction
8272 * 1. Sync IRS for default SB
8273 * 2. Sync SP queue - this guarantes us that attention handling started
8274 * 3. Wait, that TXdisable/enable transaction completes
8275 *
8276 * 1+2 guranty that if DCBx attention was scheduled it already changed
8277 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
8278 * received complettion for the transaction the state is TX_STOPPED.
8279 * State will return to STARTED after completion of TX_STOPPED-->STARTED
8280 * transaction.
8281 */
8282
8283 /* make sure default SB ISR is done */
8284 if (msix)
8285 synchronize_irq(bp->msix_table[0].vector);
8286 else
8287 synchronize_irq(bp->pdev->irq);
8288
8289 flush_workqueue(bnx2x_wq);
8290
8291 while (bnx2x_func_get_state(bp, &bp->func_obj) !=
8292 BNX2X_F_STATE_STARTED && tout--)
8293 msleep(20);
8294
8295 if (bnx2x_func_get_state(bp, &bp->func_obj) !=
8296 BNX2X_F_STATE_STARTED) {
8297 #ifdef BNX2X_STOP_ON_ERROR
8298 BNX2X_ERR("Wrong function state\n");
8299 return -EBUSY;
8300 #else
8301 /*
8302 * Failed to complete the transaction in a "good way"
8303 * Force both transactions with CLR bit
8304 */
8305 struct bnx2x_func_state_params func_params = {NULL};
8306
8307 DP(NETIF_MSG_IFDOWN,
8308 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
8309
8310 func_params.f_obj = &bp->func_obj;
8311 __set_bit(RAMROD_DRV_CLR_ONLY,
8312 &func_params.ramrod_flags);
8313
8314 /* STARTED-->TX_ST0PPED */
8315 func_params.cmd = BNX2X_F_CMD_TX_STOP;
8316 bnx2x_func_state_change(bp, &func_params);
8317
8318 /* TX_ST0PPED-->STARTED */
8319 func_params.cmd = BNX2X_F_CMD_TX_START;
8320 return bnx2x_func_state_change(bp, &func_params);
8321 #endif
8322 }
8323
8324 return 0;
8325 }
8326
8327 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode)
8328 {
8329 int port = BP_PORT(bp);
8330 int i, rc = 0;
8331 u8 cos;
8332 struct bnx2x_mcast_ramrod_params rparam = {NULL};
8333 u32 reset_code;
8334
8335 /* Wait until tx fastpath tasks complete */
8336 for_each_tx_queue(bp, i) {
8337 struct bnx2x_fastpath *fp = &bp->fp[i];
8338
8339 for_each_cos_in_tx_queue(fp, cos)
8340 rc = bnx2x_clean_tx_queue(bp, fp->txdata_ptr[cos]);
8341 #ifdef BNX2X_STOP_ON_ERROR
8342 if (rc)
8343 return;
8344 #endif
8345 }
8346
8347 /* Give HW time to discard old tx messages */
8348 usleep_range(1000, 1000);
8349
8350 /* Clean all ETH MACs */
8351 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_ETH_MAC,
8352 false);
8353 if (rc < 0)
8354 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc);
8355
8356 /* Clean up UC list */
8357 rc = bnx2x_del_all_macs(bp, &bp->sp_objs[0].mac_obj, BNX2X_UC_LIST_MAC,
8358 true);
8359 if (rc < 0)
8360 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
8361 rc);
8362
8363 /* Disable LLH */
8364 if (!CHIP_IS_E1(bp))
8365 REG_WR(bp, NIG_REG_LLH0_FUNC_EN + port*8, 0);
8366
8367 /* Set "drop all" (stop Rx).
8368 * We need to take a netif_addr_lock() here in order to prevent
8369 * a race between the completion code and this code.
8370 */
8371 netif_addr_lock_bh(bp->dev);
8372 /* Schedule the rx_mode command */
8373 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
8374 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
8375 else
8376 bnx2x_set_storm_rx_mode(bp);
8377
8378 /* Cleanup multicast configuration */
8379 rparam.mcast_obj = &bp->mcast_obj;
8380 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
8381 if (rc < 0)
8382 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc);
8383
8384 netif_addr_unlock_bh(bp->dev);
8385
8386
8387
8388 /*
8389 * Send the UNLOAD_REQUEST to the MCP. This will return if
8390 * this function should perform FUNC, PORT or COMMON HW
8391 * reset.
8392 */
8393 reset_code = bnx2x_send_unload_req(bp, unload_mode);
8394
8395 /*
8396 * (assumption: No Attention from MCP at this stage)
8397 * PMF probably in the middle of TXdisable/enable transaction
8398 */
8399 rc = bnx2x_func_wait_started(bp);
8400 if (rc) {
8401 BNX2X_ERR("bnx2x_func_wait_started failed\n");
8402 #ifdef BNX2X_STOP_ON_ERROR
8403 return;
8404 #endif
8405 }
8406
8407 /* Close multi and leading connections
8408 * Completions for ramrods are collected in a synchronous way
8409 */
8410 for_each_queue(bp, i)
8411 if (bnx2x_stop_queue(bp, i))
8412 #ifdef BNX2X_STOP_ON_ERROR
8413 return;
8414 #else
8415 goto unload_error;
8416 #endif
8417 /* If SP settings didn't get completed so far - something
8418 * very wrong has happen.
8419 */
8420 if (!bnx2x_wait_sp_comp(bp, ~0x0UL))
8421 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8422
8423 #ifndef BNX2X_STOP_ON_ERROR
8424 unload_error:
8425 #endif
8426 rc = bnx2x_func_stop(bp);
8427 if (rc) {
8428 BNX2X_ERR("Function stop failed!\n");
8429 #ifdef BNX2X_STOP_ON_ERROR
8430 return;
8431 #endif
8432 }
8433
8434 /* Disable HW interrupts, NAPI */
8435 bnx2x_netif_stop(bp, 1);
8436 /* Delete all NAPI objects */
8437 bnx2x_del_all_napi(bp);
8438
8439 /* Release IRQs */
8440 bnx2x_free_irq(bp);
8441
8442 /* Reset the chip */
8443 rc = bnx2x_reset_hw(bp, reset_code);
8444 if (rc)
8445 BNX2X_ERR("HW_RESET failed\n");
8446
8447
8448 /* Report UNLOAD_DONE to MCP */
8449 bnx2x_send_unload_done(bp);
8450 }
8451
8452 void bnx2x_disable_close_the_gate(struct bnx2x *bp)
8453 {
8454 u32 val;
8455
8456 DP(NETIF_MSG_IFDOWN, "Disabling \"close the gates\"\n");
8457
8458 if (CHIP_IS_E1(bp)) {
8459 int port = BP_PORT(bp);
8460 u32 addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 :
8461 MISC_REG_AEU_MASK_ATTN_FUNC_0;
8462
8463 val = REG_RD(bp, addr);
8464 val &= ~(0x300);
8465 REG_WR(bp, addr, val);
8466 } else {
8467 val = REG_RD(bp, MISC_REG_AEU_GENERAL_MASK);
8468 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK |
8469 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK);
8470 REG_WR(bp, MISC_REG_AEU_GENERAL_MASK, val);
8471 }
8472 }
8473
8474 /* Close gates #2, #3 and #4: */
8475 static void bnx2x_set_234_gates(struct bnx2x *bp, bool close)
8476 {
8477 u32 val;
8478
8479 /* Gates #2 and #4a are closed/opened for "not E1" only */
8480 if (!CHIP_IS_E1(bp)) {
8481 /* #4 */
8482 REG_WR(bp, PXP_REG_HST_DISCARD_DOORBELLS, !!close);
8483 /* #2 */
8484 REG_WR(bp, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close);
8485 }
8486
8487 /* #3 */
8488 if (CHIP_IS_E1x(bp)) {
8489 /* Prevent interrupts from HC on both ports */
8490 val = REG_RD(bp, HC_REG_CONFIG_1);
8491 REG_WR(bp, HC_REG_CONFIG_1,
8492 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) :
8493 (val & ~(u32)HC_CONFIG_1_REG_BLOCK_DISABLE_1));
8494
8495 val = REG_RD(bp, HC_REG_CONFIG_0);
8496 REG_WR(bp, HC_REG_CONFIG_0,
8497 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) :
8498 (val & ~(u32)HC_CONFIG_0_REG_BLOCK_DISABLE_0));
8499 } else {
8500 /* Prevent incomming interrupts in IGU */
8501 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
8502
8503 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION,
8504 (!close) ?
8505 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) :
8506 (val & ~(u32)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE));
8507 }
8508
8509 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "%s gates #2, #3 and #4\n",
8510 close ? "closing" : "opening");
8511 mmiowb();
8512 }
8513
8514 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8515
8516 static void bnx2x_clp_reset_prep(struct bnx2x *bp, u32 *magic_val)
8517 {
8518 /* Do some magic... */
8519 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8520 *magic_val = val & SHARED_MF_CLP_MAGIC;
8521 MF_CFG_WR(bp, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC);
8522 }
8523
8524 /**
8525 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8526 *
8527 * @bp: driver handle
8528 * @magic_val: old value of the `magic' bit.
8529 */
8530 static void bnx2x_clp_reset_done(struct bnx2x *bp, u32 magic_val)
8531 {
8532 /* Restore the `magic' bit value... */
8533 u32 val = MF_CFG_RD(bp, shared_mf_config.clp_mb);
8534 MF_CFG_WR(bp, shared_mf_config.clp_mb,
8535 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val);
8536 }
8537
8538 /**
8539 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8540 *
8541 * @bp: driver handle
8542 * @magic_val: old value of 'magic' bit.
8543 *
8544 * Takes care of CLP configurations.
8545 */
8546 static void bnx2x_reset_mcp_prep(struct bnx2x *bp, u32 *magic_val)
8547 {
8548 u32 shmem;
8549 u32 validity_offset;
8550
8551 DP(NETIF_MSG_HW | NETIF_MSG_IFUP, "Starting\n");
8552
8553 /* Set `magic' bit in order to save MF config */
8554 if (!CHIP_IS_E1(bp))
8555 bnx2x_clp_reset_prep(bp, magic_val);
8556
8557 /* Get shmem offset */
8558 shmem = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8559 validity_offset = offsetof(struct shmem_region, validity_map[0]);
8560
8561 /* Clear validity map flags */
8562 if (shmem > 0)
8563 REG_WR(bp, shmem + validity_offset, 0);
8564 }
8565
8566 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8567 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8568
8569 /**
8570 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8571 *
8572 * @bp: driver handle
8573 */
8574 static void bnx2x_mcp_wait_one(struct bnx2x *bp)
8575 {
8576 /* special handling for emulation and FPGA,
8577 wait 10 times longer */
8578 if (CHIP_REV_IS_SLOW(bp))
8579 msleep(MCP_ONE_TIMEOUT*10);
8580 else
8581 msleep(MCP_ONE_TIMEOUT);
8582 }
8583
8584 /*
8585 * initializes bp->common.shmem_base and waits for validity signature to appear
8586 */
8587 static int bnx2x_init_shmem(struct bnx2x *bp)
8588 {
8589 int cnt = 0;
8590 u32 val = 0;
8591
8592 do {
8593 bp->common.shmem_base = REG_RD(bp, MISC_REG_SHARED_MEM_ADDR);
8594 if (bp->common.shmem_base) {
8595 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
8596 if (val & SHR_MEM_VALIDITY_MB)
8597 return 0;
8598 }
8599
8600 bnx2x_mcp_wait_one(bp);
8601
8602 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT));
8603
8604 BNX2X_ERR("BAD MCP validity signature\n");
8605
8606 return -ENODEV;
8607 }
8608
8609 static int bnx2x_reset_mcp_comp(struct bnx2x *bp, u32 magic_val)
8610 {
8611 int rc = bnx2x_init_shmem(bp);
8612
8613 /* Restore the `magic' bit value */
8614 if (!CHIP_IS_E1(bp))
8615 bnx2x_clp_reset_done(bp, magic_val);
8616
8617 return rc;
8618 }
8619
8620 static void bnx2x_pxp_prep(struct bnx2x *bp)
8621 {
8622 if (!CHIP_IS_E1(bp)) {
8623 REG_WR(bp, PXP2_REG_RD_START_INIT, 0);
8624 REG_WR(bp, PXP2_REG_RQ_RBC_DONE, 0);
8625 mmiowb();
8626 }
8627 }
8628
8629 /*
8630 * Reset the whole chip except for:
8631 * - PCIE core
8632 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8633 * one reset bit)
8634 * - IGU
8635 * - MISC (including AEU)
8636 * - GRC
8637 * - RBCN, RBCP
8638 */
8639 static void bnx2x_process_kill_chip_reset(struct bnx2x *bp, bool global)
8640 {
8641 u32 not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2;
8642 u32 global_bits2, stay_reset2;
8643
8644 /*
8645 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8646 * (per chip) blocks.
8647 */
8648 global_bits2 =
8649 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU |
8650 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE;
8651
8652 /* Don't reset the following blocks */
8653 not_reset_mask1 =
8654 MISC_REGISTERS_RESET_REG_1_RST_HC |
8655 MISC_REGISTERS_RESET_REG_1_RST_PXPV |
8656 MISC_REGISTERS_RESET_REG_1_RST_PXP;
8657
8658 not_reset_mask2 =
8659 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO |
8660 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE |
8661 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE |
8662 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE |
8663 MISC_REGISTERS_RESET_REG_2_RST_RBCN |
8664 MISC_REGISTERS_RESET_REG_2_RST_GRC |
8665 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE |
8666 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B |
8667 MISC_REGISTERS_RESET_REG_2_RST_ATC |
8668 MISC_REGISTERS_RESET_REG_2_PGLC;
8669
8670 /*
8671 * Keep the following blocks in reset:
8672 * - all xxMACs are handled by the bnx2x_link code.
8673 */
8674 stay_reset2 =
8675 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 |
8676 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 |
8677 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 |
8678 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 |
8679 MISC_REGISTERS_RESET_REG_2_UMAC0 |
8680 MISC_REGISTERS_RESET_REG_2_UMAC1 |
8681 MISC_REGISTERS_RESET_REG_2_XMAC |
8682 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT;
8683
8684 /* Full reset masks according to the chip */
8685 reset_mask1 = 0xffffffff;
8686
8687 if (CHIP_IS_E1(bp))
8688 reset_mask2 = 0xffff;
8689 else if (CHIP_IS_E1H(bp))
8690 reset_mask2 = 0x1ffff;
8691 else if (CHIP_IS_E2(bp))
8692 reset_mask2 = 0xfffff;
8693 else /* CHIP_IS_E3 */
8694 reset_mask2 = 0x3ffffff;
8695
8696 /* Don't reset global blocks unless we need to */
8697 if (!global)
8698 reset_mask2 &= ~global_bits2;
8699
8700 /*
8701 * In case of attention in the QM, we need to reset PXP
8702 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8703 * because otherwise QM reset would release 'close the gates' shortly
8704 * before resetting the PXP, then the PSWRQ would send a write
8705 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8706 * read the payload data from PSWWR, but PSWWR would not
8707 * respond. The write queue in PGLUE would stuck, dmae commands
8708 * would not return. Therefore it's important to reset the second
8709 * reset register (containing the
8710 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8711 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8712 * bit).
8713 */
8714 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
8715 reset_mask2 & (~not_reset_mask2));
8716
8717 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR,
8718 reset_mask1 & (~not_reset_mask1));
8719
8720 barrier();
8721 mmiowb();
8722
8723 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
8724 reset_mask2 & (~stay_reset2));
8725
8726 barrier();
8727 mmiowb();
8728
8729 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1);
8730 mmiowb();
8731 }
8732
8733 /**
8734 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8735 * It should get cleared in no more than 1s.
8736 *
8737 * @bp: driver handle
8738 *
8739 * It should get cleared in no more than 1s. Returns 0 if
8740 * pending writes bit gets cleared.
8741 */
8742 static int bnx2x_er_poll_igu_vq(struct bnx2x *bp)
8743 {
8744 u32 cnt = 1000;
8745 u32 pend_bits = 0;
8746
8747 do {
8748 pend_bits = REG_RD(bp, IGU_REG_PENDING_BITS_STATUS);
8749
8750 if (pend_bits == 0)
8751 break;
8752
8753 usleep_range(1000, 1000);
8754 } while (cnt-- > 0);
8755
8756 if (cnt <= 0) {
8757 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8758 pend_bits);
8759 return -EBUSY;
8760 }
8761
8762 return 0;
8763 }
8764
8765 static int bnx2x_process_kill(struct bnx2x *bp, bool global)
8766 {
8767 int cnt = 1000;
8768 u32 val = 0;
8769 u32 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2;
8770
8771
8772 /* Empty the Tetris buffer, wait for 1s */
8773 do {
8774 sr_cnt = REG_RD(bp, PXP2_REG_RD_SR_CNT);
8775 blk_cnt = REG_RD(bp, PXP2_REG_RD_BLK_CNT);
8776 port_is_idle_0 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_0);
8777 port_is_idle_1 = REG_RD(bp, PXP2_REG_RD_PORT_IS_IDLE_1);
8778 pgl_exp_rom2 = REG_RD(bp, PXP2_REG_PGL_EXP_ROM2);
8779 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) &&
8780 ((port_is_idle_0 & 0x1) == 0x1) &&
8781 ((port_is_idle_1 & 0x1) == 0x1) &&
8782 (pgl_exp_rom2 == 0xffffffff))
8783 break;
8784 usleep_range(1000, 1000);
8785 } while (cnt-- > 0);
8786
8787 if (cnt <= 0) {
8788 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8789 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8790 sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1,
8791 pgl_exp_rom2);
8792 return -EAGAIN;
8793 }
8794
8795 barrier();
8796
8797 /* Close gates #2, #3 and #4 */
8798 bnx2x_set_234_gates(bp, true);
8799
8800 /* Poll for IGU VQs for 57712 and newer chips */
8801 if (!CHIP_IS_E1x(bp) && bnx2x_er_poll_igu_vq(bp))
8802 return -EAGAIN;
8803
8804
8805 /* TBD: Indicate that "process kill" is in progress to MCP */
8806
8807 /* Clear "unprepared" bit */
8808 REG_WR(bp, MISC_REG_UNPREPARED, 0);
8809 barrier();
8810
8811 /* Make sure all is written to the chip before the reset */
8812 mmiowb();
8813
8814 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8815 * PSWHST, GRC and PSWRD Tetris buffer.
8816 */
8817 usleep_range(1000, 1000);
8818
8819 /* Prepare to chip reset: */
8820 /* MCP */
8821 if (global)
8822 bnx2x_reset_mcp_prep(bp, &val);
8823
8824 /* PXP */
8825 bnx2x_pxp_prep(bp);
8826 barrier();
8827
8828 /* reset the chip */
8829 bnx2x_process_kill_chip_reset(bp, global);
8830 barrier();
8831
8832 /* Recover after reset: */
8833 /* MCP */
8834 if (global && bnx2x_reset_mcp_comp(bp, val))
8835 return -EAGAIN;
8836
8837 /* TBD: Add resetting the NO_MCP mode DB here */
8838
8839 /* PXP */
8840 bnx2x_pxp_prep(bp);
8841
8842 /* Open the gates #2, #3 and #4 */
8843 bnx2x_set_234_gates(bp, false);
8844
8845 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8846 * reset state, re-enable attentions. */
8847
8848 return 0;
8849 }
8850
8851 int bnx2x_leader_reset(struct bnx2x *bp)
8852 {
8853 int rc = 0;
8854 bool global = bnx2x_reset_is_global(bp);
8855 u32 load_code;
8856
8857 /* if not going to reset MCP - load "fake" driver to reset HW while
8858 * driver is owner of the HW
8859 */
8860 if (!global && !BP_NOMCP(bp)) {
8861 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_REQ, 0);
8862 if (!load_code) {
8863 BNX2X_ERR("MCP response failure, aborting\n");
8864 rc = -EAGAIN;
8865 goto exit_leader_reset;
8866 }
8867 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) &&
8868 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) {
8869 BNX2X_ERR("MCP unexpected resp, aborting\n");
8870 rc = -EAGAIN;
8871 goto exit_leader_reset2;
8872 }
8873 load_code = bnx2x_fw_command(bp, DRV_MSG_CODE_LOAD_DONE, 0);
8874 if (!load_code) {
8875 BNX2X_ERR("MCP response failure, aborting\n");
8876 rc = -EAGAIN;
8877 goto exit_leader_reset2;
8878 }
8879 }
8880
8881 /* Try to recover after the failure */
8882 if (bnx2x_process_kill(bp, global)) {
8883 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8884 BP_PATH(bp));
8885 rc = -EAGAIN;
8886 goto exit_leader_reset2;
8887 }
8888
8889 /*
8890 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8891 * state.
8892 */
8893 bnx2x_set_reset_done(bp);
8894 if (global)
8895 bnx2x_clear_reset_global(bp);
8896
8897 exit_leader_reset2:
8898 /* unload "fake driver" if it was loaded */
8899 if (!global && !BP_NOMCP(bp)) {
8900 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0);
8901 bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
8902 }
8903 exit_leader_reset:
8904 bp->is_leader = 0;
8905 bnx2x_release_leader_lock(bp);
8906 smp_mb();
8907 return rc;
8908 }
8909
8910 static void bnx2x_recovery_failed(struct bnx2x *bp)
8911 {
8912 netdev_err(bp->dev, "Recovery has failed. Power cycle is needed.\n");
8913
8914 /* Disconnect this device */
8915 netif_device_detach(bp->dev);
8916
8917 /*
8918 * Block ifup for all function on this engine until "process kill"
8919 * or power cycle.
8920 */
8921 bnx2x_set_reset_in_progress(bp);
8922
8923 /* Shut down the power */
8924 bnx2x_set_power_state(bp, PCI_D3hot);
8925
8926 bp->recovery_state = BNX2X_RECOVERY_FAILED;
8927
8928 smp_mb();
8929 }
8930
8931 /*
8932 * Assumption: runs under rtnl lock. This together with the fact
8933 * that it's called only from bnx2x_sp_rtnl() ensure that it
8934 * will never be called when netif_running(bp->dev) is false.
8935 */
8936 static void bnx2x_parity_recover(struct bnx2x *bp)
8937 {
8938 bool global = false;
8939 u32 error_recovered, error_unrecovered;
8940 bool is_parity;
8941
8942 DP(NETIF_MSG_HW, "Handling parity\n");
8943 while (1) {
8944 switch (bp->recovery_state) {
8945 case BNX2X_RECOVERY_INIT:
8946 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_INIT\n");
8947 is_parity = bnx2x_chk_parity_attn(bp, &global, false);
8948 WARN_ON(!is_parity);
8949
8950 /* Try to get a LEADER_LOCK HW lock */
8951 if (bnx2x_trylock_leader_lock(bp)) {
8952 bnx2x_set_reset_in_progress(bp);
8953 /*
8954 * Check if there is a global attention and if
8955 * there was a global attention, set the global
8956 * reset bit.
8957 */
8958
8959 if (global)
8960 bnx2x_set_reset_global(bp);
8961
8962 bp->is_leader = 1;
8963 }
8964
8965 /* Stop the driver */
8966 /* If interface has been removed - break */
8967 if (bnx2x_nic_unload(bp, UNLOAD_RECOVERY))
8968 return;
8969
8970 bp->recovery_state = BNX2X_RECOVERY_WAIT;
8971
8972 /* Ensure "is_leader", MCP command sequence and
8973 * "recovery_state" update values are seen on other
8974 * CPUs.
8975 */
8976 smp_mb();
8977 break;
8978
8979 case BNX2X_RECOVERY_WAIT:
8980 DP(NETIF_MSG_HW, "State is BNX2X_RECOVERY_WAIT\n");
8981 if (bp->is_leader) {
8982 int other_engine = BP_PATH(bp) ? 0 : 1;
8983 bool other_load_status =
8984 bnx2x_get_load_status(bp, other_engine);
8985 bool load_status =
8986 bnx2x_get_load_status(bp, BP_PATH(bp));
8987 global = bnx2x_reset_is_global(bp);
8988
8989 /*
8990 * In case of a parity in a global block, let
8991 * the first leader that performs a
8992 * leader_reset() reset the global blocks in
8993 * order to clear global attentions. Otherwise
8994 * the the gates will remain closed for that
8995 * engine.
8996 */
8997 if (load_status ||
8998 (global && other_load_status)) {
8999 /* Wait until all other functions get
9000 * down.
9001 */
9002 schedule_delayed_work(&bp->sp_rtnl_task,
9003 HZ/10);
9004 return;
9005 } else {
9006 /* If all other functions got down -
9007 * try to bring the chip back to
9008 * normal. In any case it's an exit
9009 * point for a leader.
9010 */
9011 if (bnx2x_leader_reset(bp)) {
9012 bnx2x_recovery_failed(bp);
9013 return;
9014 }
9015
9016 /* If we are here, means that the
9017 * leader has succeeded and doesn't
9018 * want to be a leader any more. Try
9019 * to continue as a none-leader.
9020 */
9021 break;
9022 }
9023 } else { /* non-leader */
9024 if (!bnx2x_reset_is_done(bp, BP_PATH(bp))) {
9025 /* Try to get a LEADER_LOCK HW lock as
9026 * long as a former leader may have
9027 * been unloaded by the user or
9028 * released a leadership by another
9029 * reason.
9030 */
9031 if (bnx2x_trylock_leader_lock(bp)) {
9032 /* I'm a leader now! Restart a
9033 * switch case.
9034 */
9035 bp->is_leader = 1;
9036 break;
9037 }
9038
9039 schedule_delayed_work(&bp->sp_rtnl_task,
9040 HZ/10);
9041 return;
9042
9043 } else {
9044 /*
9045 * If there was a global attention, wait
9046 * for it to be cleared.
9047 */
9048 if (bnx2x_reset_is_global(bp)) {
9049 schedule_delayed_work(
9050 &bp->sp_rtnl_task,
9051 HZ/10);
9052 return;
9053 }
9054
9055 error_recovered =
9056 bp->eth_stats.recoverable_error;
9057 error_unrecovered =
9058 bp->eth_stats.unrecoverable_error;
9059 bp->recovery_state =
9060 BNX2X_RECOVERY_NIC_LOADING;
9061 if (bnx2x_nic_load(bp, LOAD_NORMAL)) {
9062 error_unrecovered++;
9063 netdev_err(bp->dev,
9064 "Recovery failed. Power cycle needed\n");
9065 /* Disconnect this device */
9066 netif_device_detach(bp->dev);
9067 /* Shut down the power */
9068 bnx2x_set_power_state(
9069 bp, PCI_D3hot);
9070 smp_mb();
9071 } else {
9072 bp->recovery_state =
9073 BNX2X_RECOVERY_DONE;
9074 error_recovered++;
9075 smp_mb();
9076 }
9077 bp->eth_stats.recoverable_error =
9078 error_recovered;
9079 bp->eth_stats.unrecoverable_error =
9080 error_unrecovered;
9081
9082 return;
9083 }
9084 }
9085 default:
9086 return;
9087 }
9088 }
9089 }
9090
9091 static int bnx2x_close(struct net_device *dev);
9092
9093 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
9094 * scheduled on a general queue in order to prevent a dead lock.
9095 */
9096 static void bnx2x_sp_rtnl_task(struct work_struct *work)
9097 {
9098 struct bnx2x *bp = container_of(work, struct bnx2x, sp_rtnl_task.work);
9099
9100 rtnl_lock();
9101
9102 if (!netif_running(bp->dev))
9103 goto sp_rtnl_exit;
9104
9105 /* if stop on error is defined no recovery flows should be executed */
9106 #ifdef BNX2X_STOP_ON_ERROR
9107 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
9108 "you will need to reboot when done\n");
9109 goto sp_rtnl_not_reset;
9110 #endif
9111
9112 if (unlikely(bp->recovery_state != BNX2X_RECOVERY_DONE)) {
9113 /*
9114 * Clear all pending SP commands as we are going to reset the
9115 * function anyway.
9116 */
9117 bp->sp_rtnl_state = 0;
9118 smp_mb();
9119
9120 bnx2x_parity_recover(bp);
9121
9122 goto sp_rtnl_exit;
9123 }
9124
9125 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT, &bp->sp_rtnl_state)) {
9126 /*
9127 * Clear all pending SP commands as we are going to reset the
9128 * function anyway.
9129 */
9130 bp->sp_rtnl_state = 0;
9131 smp_mb();
9132
9133 bnx2x_nic_unload(bp, UNLOAD_NORMAL);
9134 bnx2x_nic_load(bp, LOAD_NORMAL);
9135
9136 goto sp_rtnl_exit;
9137 }
9138 #ifdef BNX2X_STOP_ON_ERROR
9139 sp_rtnl_not_reset:
9140 #endif
9141 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC, &bp->sp_rtnl_state))
9142 bnx2x_setup_tc(bp->dev, bp->dcbx_port_params.ets.num_of_cos);
9143 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE, &bp->sp_rtnl_state))
9144 bnx2x_after_function_update(bp);
9145 /*
9146 * in case of fan failure we need to reset id if the "stop on error"
9147 * debug flag is set, since we trying to prevent permanent overheating
9148 * damage
9149 */
9150 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE, &bp->sp_rtnl_state)) {
9151 DP(NETIF_MSG_HW, "fan failure detected. Unloading driver\n");
9152 netif_device_detach(bp->dev);
9153 bnx2x_close(bp->dev);
9154 }
9155
9156 sp_rtnl_exit:
9157 rtnl_unlock();
9158 }
9159
9160 /* end of nic load/unload */
9161
9162 static void bnx2x_period_task(struct work_struct *work)
9163 {
9164 struct bnx2x *bp = container_of(work, struct bnx2x, period_task.work);
9165
9166 if (!netif_running(bp->dev))
9167 goto period_task_exit;
9168
9169 if (CHIP_REV_IS_SLOW(bp)) {
9170 BNX2X_ERR("period task called on emulation, ignoring\n");
9171 goto period_task_exit;
9172 }
9173
9174 bnx2x_acquire_phy_lock(bp);
9175 /*
9176 * The barrier is needed to ensure the ordering between the writing to
9177 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
9178 * the reading here.
9179 */
9180 smp_mb();
9181 if (bp->port.pmf) {
9182 bnx2x_period_func(&bp->link_params, &bp->link_vars);
9183
9184 /* Re-queue task in 1 sec */
9185 queue_delayed_work(bnx2x_wq, &bp->period_task, 1*HZ);
9186 }
9187
9188 bnx2x_release_phy_lock(bp);
9189 period_task_exit:
9190 return;
9191 }
9192
9193 /*
9194 * Init service functions
9195 */
9196
9197 static u32 bnx2x_get_pretend_reg(struct bnx2x *bp)
9198 {
9199 u32 base = PXP2_REG_PGL_PRETEND_FUNC_F0;
9200 u32 stride = PXP2_REG_PGL_PRETEND_FUNC_F1 - base;
9201 return base + (BP_ABS_FUNC(bp)) * stride;
9202 }
9203
9204 static void bnx2x_undi_int_disable_e1h(struct bnx2x *bp)
9205 {
9206 u32 reg = bnx2x_get_pretend_reg(bp);
9207
9208 /* Flush all outstanding writes */
9209 mmiowb();
9210
9211 /* Pretend to be function 0 */
9212 REG_WR(bp, reg, 0);
9213 REG_RD(bp, reg); /* Flush the GRC transaction (in the chip) */
9214
9215 /* From now we are in the "like-E1" mode */
9216 bnx2x_int_disable(bp);
9217
9218 /* Flush all outstanding writes */
9219 mmiowb();
9220
9221 /* Restore the original function */
9222 REG_WR(bp, reg, BP_ABS_FUNC(bp));
9223 REG_RD(bp, reg);
9224 }
9225
9226 static inline void bnx2x_undi_int_disable(struct bnx2x *bp)
9227 {
9228 if (CHIP_IS_E1(bp))
9229 bnx2x_int_disable(bp);
9230 else
9231 bnx2x_undi_int_disable_e1h(bp);
9232 }
9233
9234 static void __devinit bnx2x_prev_unload_close_mac(struct bnx2x *bp)
9235 {
9236 u32 val, base_addr, offset, mask, reset_reg;
9237 bool mac_stopped = false;
9238 u8 port = BP_PORT(bp);
9239
9240 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_2);
9241
9242 if (!CHIP_IS_E3(bp)) {
9243 val = REG_RD(bp, NIG_REG_BMAC0_REGS_OUT_EN + port * 4);
9244 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port;
9245 if ((mask & reset_reg) && val) {
9246 u32 wb_data[2];
9247 BNX2X_DEV_INFO("Disable bmac Rx\n");
9248 base_addr = BP_PORT(bp) ? NIG_REG_INGRESS_BMAC1_MEM
9249 : NIG_REG_INGRESS_BMAC0_MEM;
9250 offset = CHIP_IS_E2(bp) ? BIGMAC2_REGISTER_BMAC_CONTROL
9251 : BIGMAC_REGISTER_BMAC_CONTROL;
9252
9253 /*
9254 * use rd/wr since we cannot use dmae. This is safe
9255 * since MCP won't access the bus due to the request
9256 * to unload, and no function on the path can be
9257 * loaded at this time.
9258 */
9259 wb_data[0] = REG_RD(bp, base_addr + offset);
9260 wb_data[1] = REG_RD(bp, base_addr + offset + 0x4);
9261 wb_data[0] &= ~BMAC_CONTROL_RX_ENABLE;
9262 REG_WR(bp, base_addr + offset, wb_data[0]);
9263 REG_WR(bp, base_addr + offset + 0x4, wb_data[1]);
9264
9265 }
9266 BNX2X_DEV_INFO("Disable emac Rx\n");
9267 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + BP_PORT(bp)*4, 0);
9268
9269 mac_stopped = true;
9270 } else {
9271 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) {
9272 BNX2X_DEV_INFO("Disable xmac Rx\n");
9273 base_addr = BP_PORT(bp) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
9274 val = REG_RD(bp, base_addr + XMAC_REG_PFC_CTRL_HI);
9275 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9276 val & ~(1 << 1));
9277 REG_WR(bp, base_addr + XMAC_REG_PFC_CTRL_HI,
9278 val | (1 << 1));
9279 REG_WR(bp, base_addr + XMAC_REG_CTRL, 0);
9280 mac_stopped = true;
9281 }
9282 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port;
9283 if (mask & reset_reg) {
9284 BNX2X_DEV_INFO("Disable umac Rx\n");
9285 base_addr = BP_PORT(bp) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
9286 REG_WR(bp, base_addr + UMAC_REG_COMMAND_CONFIG, 0);
9287 mac_stopped = true;
9288 }
9289 }
9290
9291 if (mac_stopped)
9292 msleep(20);
9293
9294 }
9295
9296 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
9297 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
9298 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
9299 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
9300
9301 static void __devinit bnx2x_prev_unload_undi_inc(struct bnx2x *bp, u8 port,
9302 u8 inc)
9303 {
9304 u16 rcq, bd;
9305 u32 tmp_reg = REG_RD(bp, BNX2X_PREV_UNDI_PROD_ADDR(port));
9306
9307 rcq = BNX2X_PREV_UNDI_RCQ(tmp_reg) + inc;
9308 bd = BNX2X_PREV_UNDI_BD(tmp_reg) + inc;
9309
9310 tmp_reg = BNX2X_PREV_UNDI_PROD(rcq, bd);
9311 REG_WR(bp, BNX2X_PREV_UNDI_PROD_ADDR(port), tmp_reg);
9312
9313 BNX2X_DEV_INFO("UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n",
9314 port, bd, rcq);
9315 }
9316
9317 static int __devinit bnx2x_prev_mcp_done(struct bnx2x *bp)
9318 {
9319 u32 rc = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_DONE, 0);
9320 if (!rc) {
9321 BNX2X_ERR("MCP response failure, aborting\n");
9322 return -EBUSY;
9323 }
9324
9325 return 0;
9326 }
9327
9328 static bool __devinit bnx2x_prev_is_path_marked(struct bnx2x *bp)
9329 {
9330 struct bnx2x_prev_path_list *tmp_list;
9331 int rc = false;
9332
9333 if (down_trylock(&bnx2x_prev_sem))
9334 return false;
9335
9336 list_for_each_entry(tmp_list, &bnx2x_prev_list, list) {
9337 if (PCI_SLOT(bp->pdev->devfn) == tmp_list->slot &&
9338 bp->pdev->bus->number == tmp_list->bus &&
9339 BP_PATH(bp) == tmp_list->path) {
9340 rc = true;
9341 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
9342 BP_PATH(bp));
9343 break;
9344 }
9345 }
9346
9347 up(&bnx2x_prev_sem);
9348
9349 return rc;
9350 }
9351
9352 static int __devinit bnx2x_prev_mark_path(struct bnx2x *bp)
9353 {
9354 struct bnx2x_prev_path_list *tmp_list;
9355 int rc;
9356
9357 tmp_list = kmalloc(sizeof(struct bnx2x_prev_path_list), GFP_KERNEL);
9358 if (!tmp_list) {
9359 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
9360 return -ENOMEM;
9361 }
9362
9363 tmp_list->bus = bp->pdev->bus->number;
9364 tmp_list->slot = PCI_SLOT(bp->pdev->devfn);
9365 tmp_list->path = BP_PATH(bp);
9366
9367 rc = down_interruptible(&bnx2x_prev_sem);
9368 if (rc) {
9369 BNX2X_ERR("Received %d when tried to take lock\n", rc);
9370 kfree(tmp_list);
9371 } else {
9372 BNX2X_DEV_INFO("Marked path [%d] - finished previous unload\n",
9373 BP_PATH(bp));
9374 list_add(&tmp_list->list, &bnx2x_prev_list);
9375 up(&bnx2x_prev_sem);
9376 }
9377
9378 return rc;
9379 }
9380
9381 static int __devinit bnx2x_do_flr(struct bnx2x *bp)
9382 {
9383 int i, pos;
9384 u16 status;
9385 struct pci_dev *dev = bp->pdev;
9386
9387
9388 if (CHIP_IS_E1x(bp)) {
9389 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
9390 return -EINVAL;
9391 }
9392
9393 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
9394 if (bp->common.bc_ver < REQ_BC_VER_4_INITIATE_FLR) {
9395 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
9396 bp->common.bc_ver);
9397 return -EINVAL;
9398 }
9399
9400 pos = pci_pcie_cap(dev);
9401 if (!pos)
9402 return -ENOTTY;
9403
9404 /* Wait for Transaction Pending bit clean */
9405 for (i = 0; i < 4; i++) {
9406 if (i)
9407 msleep((1 << (i - 1)) * 100);
9408
9409 pci_read_config_word(dev, pos + PCI_EXP_DEVSTA, &status);
9410 if (!(status & PCI_EXP_DEVSTA_TRPND))
9411 goto clear;
9412 }
9413
9414 dev_err(&dev->dev,
9415 "transaction is not cleared; proceeding with reset anyway\n");
9416
9417 clear:
9418
9419 BNX2X_DEV_INFO("Initiating FLR\n");
9420 bnx2x_fw_command(bp, DRV_MSG_CODE_INITIATE_FLR, 0);
9421
9422 return 0;
9423 }
9424
9425 static int __devinit bnx2x_prev_unload_uncommon(struct bnx2x *bp)
9426 {
9427 int rc;
9428
9429 BNX2X_DEV_INFO("Uncommon unload Flow\n");
9430
9431 /* Test if previous unload process was already finished for this path */
9432 if (bnx2x_prev_is_path_marked(bp))
9433 return bnx2x_prev_mcp_done(bp);
9434
9435 /* If function has FLR capabilities, and existing FW version matches
9436 * the one required, then FLR will be sufficient to clean any residue
9437 * left by previous driver
9438 */
9439 rc = bnx2x_test_firmware_version(bp, false);
9440
9441 if (!rc) {
9442 /* fw version is good */
9443 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
9444 rc = bnx2x_do_flr(bp);
9445 }
9446
9447 if (!rc) {
9448 /* FLR was performed */
9449 BNX2X_DEV_INFO("FLR successful\n");
9450 return 0;
9451 }
9452
9453 BNX2X_DEV_INFO("Could not FLR\n");
9454
9455 /* Close the MCP request, return failure*/
9456 rc = bnx2x_prev_mcp_done(bp);
9457 if (!rc)
9458 rc = BNX2X_PREV_WAIT_NEEDED;
9459
9460 return rc;
9461 }
9462
9463 static int __devinit bnx2x_prev_unload_common(struct bnx2x *bp)
9464 {
9465 u32 reset_reg, tmp_reg = 0, rc;
9466 /* It is possible a previous function received 'common' answer,
9467 * but hasn't loaded yet, therefore creating a scenario of
9468 * multiple functions receiving 'common' on the same path.
9469 */
9470 BNX2X_DEV_INFO("Common unload Flow\n");
9471
9472 if (bnx2x_prev_is_path_marked(bp))
9473 return bnx2x_prev_mcp_done(bp);
9474
9475 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9476
9477 /* Reset should be performed after BRB is emptied */
9478 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) {
9479 u32 timer_count = 1000;
9480 bool prev_undi = false;
9481
9482 /* Close the MAC Rx to prevent BRB from filling up */
9483 bnx2x_prev_unload_close_mac(bp);
9484
9485 /* Check if the UNDI driver was previously loaded
9486 * UNDI driver initializes CID offset for normal bell to 0x7
9487 */
9488 reset_reg = REG_RD(bp, MISC_REG_RESET_REG_1);
9489 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) {
9490 tmp_reg = REG_RD(bp, DORQ_REG_NORM_CID_OFST);
9491 if (tmp_reg == 0x7) {
9492 BNX2X_DEV_INFO("UNDI previously loaded\n");
9493 prev_undi = true;
9494 /* clear the UNDI indication */
9495 REG_WR(bp, DORQ_REG_NORM_CID_OFST, 0);
9496 }
9497 }
9498 /* wait until BRB is empty */
9499 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9500 while (timer_count) {
9501 u32 prev_brb = tmp_reg;
9502
9503 tmp_reg = REG_RD(bp, BRB1_REG_NUM_OF_FULL_BLOCKS);
9504 if (!tmp_reg)
9505 break;
9506
9507 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg);
9508
9509 /* reset timer as long as BRB actually gets emptied */
9510 if (prev_brb > tmp_reg)
9511 timer_count = 1000;
9512 else
9513 timer_count--;
9514
9515 /* If UNDI resides in memory, manually increment it */
9516 if (prev_undi)
9517 bnx2x_prev_unload_undi_inc(bp, BP_PORT(bp), 1);
9518
9519 udelay(10);
9520 }
9521
9522 if (!timer_count)
9523 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
9524
9525 }
9526
9527 /* No packets are in the pipeline, path is ready for reset */
9528 bnx2x_reset_common(bp);
9529
9530 rc = bnx2x_prev_mark_path(bp);
9531 if (rc) {
9532 bnx2x_prev_mcp_done(bp);
9533 return rc;
9534 }
9535
9536 return bnx2x_prev_mcp_done(bp);
9537 }
9538
9539 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
9540 * and boot began, or when kdump kernel was loaded. Either case would invalidate
9541 * the addresses of the transaction, resulting in was-error bit set in the pci
9542 * causing all hw-to-host pcie transactions to timeout. If this happened we want
9543 * to clear the interrupt which detected this from the pglueb and the was done
9544 * bit
9545 */
9546 static void __devinit bnx2x_prev_interrupted_dmae(struct bnx2x *bp)
9547 {
9548 u32 val = REG_RD(bp, PGLUE_B_REG_PGLUE_B_INT_STS);
9549 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) {
9550 BNX2X_ERR("was error bit was found to be set in pglueb upon startup. Clearing");
9551 REG_WR(bp, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << BP_FUNC(bp));
9552 }
9553 }
9554
9555 static int __devinit bnx2x_prev_unload(struct bnx2x *bp)
9556 {
9557 int time_counter = 10;
9558 u32 rc, fw, hw_lock_reg, hw_lock_val;
9559 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
9560
9561 /* clear hw from errors which may have resulted from an interrupted
9562 * dmae transaction.
9563 */
9564 bnx2x_prev_interrupted_dmae(bp);
9565
9566 /* Release previously held locks */
9567 hw_lock_reg = (BP_FUNC(bp) <= 5) ?
9568 (MISC_REG_DRIVER_CONTROL_1 + BP_FUNC(bp) * 8) :
9569 (MISC_REG_DRIVER_CONTROL_7 + (BP_FUNC(bp) - 6) * 8);
9570
9571 hw_lock_val = (REG_RD(bp, hw_lock_reg));
9572 if (hw_lock_val) {
9573 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) {
9574 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
9575 REG_WR(bp, MCP_REG_MCPR_NVM_SW_ARB,
9576 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << BP_PORT(bp)));
9577 }
9578
9579 BNX2X_DEV_INFO("Release Previously held hw lock\n");
9580 REG_WR(bp, hw_lock_reg, 0xffffffff);
9581 } else
9582 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
9583
9584 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(bp, MCP_REG_MCPR_ACCESS_LOCK)) {
9585 BNX2X_DEV_INFO("Release previously held alr\n");
9586 REG_WR(bp, MCP_REG_MCPR_ACCESS_LOCK, 0);
9587 }
9588
9589
9590 do {
9591 /* Lock MCP using an unload request */
9592 fw = bnx2x_fw_command(bp, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0);
9593 if (!fw) {
9594 BNX2X_ERR("MCP response failure, aborting\n");
9595 rc = -EBUSY;
9596 break;
9597 }
9598
9599 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) {
9600 rc = bnx2x_prev_unload_common(bp);
9601 break;
9602 }
9603
9604 /* non-common reply from MCP night require looping */
9605 rc = bnx2x_prev_unload_uncommon(bp);
9606 if (rc != BNX2X_PREV_WAIT_NEEDED)
9607 break;
9608
9609 msleep(20);
9610 } while (--time_counter);
9611
9612 if (!time_counter || rc) {
9613 BNX2X_ERR("Failed unloading previous driver, aborting\n");
9614 rc = -EBUSY;
9615 }
9616
9617 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc);
9618
9619 return rc;
9620 }
9621
9622 static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
9623 {
9624 u32 val, val2, val3, val4, id, boot_mode;
9625 u16 pmc;
9626
9627 /* Get the chip revision id and number. */
9628 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
9629 val = REG_RD(bp, MISC_REG_CHIP_NUM);
9630 id = ((val & 0xffff) << 16);
9631 val = REG_RD(bp, MISC_REG_CHIP_REV);
9632 id |= ((val & 0xf) << 12);
9633 val = REG_RD(bp, MISC_REG_CHIP_METAL);
9634 id |= ((val & 0xff) << 4);
9635 val = REG_RD(bp, MISC_REG_BOND_ID);
9636 id |= (val & 0xf);
9637 bp->common.chip_id = id;
9638
9639 /* force 57811 according to MISC register */
9640 if (REG_RD(bp, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) {
9641 if (CHIP_IS_57810(bp))
9642 bp->common.chip_id = (CHIP_NUM_57811 << 16) |
9643 (bp->common.chip_id & 0x0000FFFF);
9644 else if (CHIP_IS_57810_MF(bp))
9645 bp->common.chip_id = (CHIP_NUM_57811_MF << 16) |
9646 (bp->common.chip_id & 0x0000FFFF);
9647 bp->common.chip_id |= 0x1;
9648 }
9649
9650 /* Set doorbell size */
9651 bp->db_size = (1 << BNX2X_DB_SHIFT);
9652
9653 if (!CHIP_IS_E1x(bp)) {
9654 val = REG_RD(bp, MISC_REG_PORT4MODE_EN_OVWR);
9655 if ((val & 1) == 0)
9656 val = REG_RD(bp, MISC_REG_PORT4MODE_EN);
9657 else
9658 val = (val >> 1) & 1;
9659 BNX2X_DEV_INFO("chip is in %s\n", val ? "4_PORT_MODE" :
9660 "2_PORT_MODE");
9661 bp->common.chip_port_mode = val ? CHIP_4_PORT_MODE :
9662 CHIP_2_PORT_MODE;
9663
9664 if (CHIP_MODE_IS_4_PORT(bp))
9665 bp->pfid = (bp->pf_num >> 1); /* 0..3 */
9666 else
9667 bp->pfid = (bp->pf_num & 0x6); /* 0, 2, 4, 6 */
9668 } else {
9669 bp->common.chip_port_mode = CHIP_PORT_MODE_NONE; /* N/A */
9670 bp->pfid = bp->pf_num; /* 0..7 */
9671 }
9672
9673 BNX2X_DEV_INFO("pf_id: %x", bp->pfid);
9674
9675 bp->link_params.chip_id = bp->common.chip_id;
9676 BNX2X_DEV_INFO("chip ID is 0x%x\n", id);
9677
9678 val = (REG_RD(bp, 0x2874) & 0x55);
9679 if ((bp->common.chip_id & 0x1) ||
9680 (CHIP_IS_E1(bp) && val) || (CHIP_IS_E1H(bp) && (val == 0x55))) {
9681 bp->flags |= ONE_PORT_FLAG;
9682 BNX2X_DEV_INFO("single port device\n");
9683 }
9684
9685 val = REG_RD(bp, MCP_REG_MCPR_NVM_CFG4);
9686 bp->common.flash_size = (BNX2X_NVRAM_1MB_SIZE <<
9687 (val & MCPR_NVM_CFG4_FLASH_SIZE));
9688 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
9689 bp->common.flash_size, bp->common.flash_size);
9690
9691 bnx2x_init_shmem(bp);
9692
9693
9694
9695 bp->common.shmem2_base = REG_RD(bp, (BP_PATH(bp) ?
9696 MISC_REG_GENERIC_CR_1 :
9697 MISC_REG_GENERIC_CR_0));
9698
9699 bp->link_params.shmem_base = bp->common.shmem_base;
9700 bp->link_params.shmem2_base = bp->common.shmem2_base;
9701 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
9702 bp->common.shmem_base, bp->common.shmem2_base);
9703
9704 if (!bp->common.shmem_base) {
9705 BNX2X_DEV_INFO("MCP not active\n");
9706 bp->flags |= NO_MCP_FLAG;
9707 return;
9708 }
9709
9710 bp->common.hw_config = SHMEM_RD(bp, dev_info.shared_hw_config.config);
9711 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp->common.hw_config);
9712
9713 bp->link_params.hw_led_mode = ((bp->common.hw_config &
9714 SHARED_HW_CFG_LED_MODE_MASK) >>
9715 SHARED_HW_CFG_LED_MODE_SHIFT);
9716
9717 bp->link_params.feature_config_flags = 0;
9718 val = SHMEM_RD(bp, dev_info.shared_feature_config.config);
9719 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED)
9720 bp->link_params.feature_config_flags |=
9721 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9722 else
9723 bp->link_params.feature_config_flags &=
9724 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED;
9725
9726 val = SHMEM_RD(bp, dev_info.bc_rev) >> 8;
9727 bp->common.bc_ver = val;
9728 BNX2X_DEV_INFO("bc_ver %X\n", val);
9729 if (val < BNX2X_BC_VER) {
9730 /* for now only warn
9731 * later we might need to enforce this */
9732 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9733 BNX2X_BC_VER, val);
9734 }
9735 bp->link_params.feature_config_flags |=
9736 (val >= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL) ?
9737 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY : 0;
9738
9739 bp->link_params.feature_config_flags |=
9740 (val >= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL) ?
9741 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY : 0;
9742 bp->link_params.feature_config_flags |=
9743 (val >= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED) ?
9744 FEATURE_CONFIG_BC_SUPPORTS_AFEX : 0;
9745 bp->link_params.feature_config_flags |=
9746 (val >= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED) ?
9747 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED : 0;
9748 bp->flags |= (val >= REQ_BC_VER_4_PFC_STATS_SUPPORTED) ?
9749 BC_SUPPORTS_PFC_STATS : 0;
9750
9751 bp->flags |= (val >= REQ_BC_VER_4_FCOE_FEATURES) ?
9752 BC_SUPPORTS_FCOE_FEATURES : 0;
9753
9754 bp->flags |= (val >= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF) ?
9755 BC_SUPPORTS_DCBX_MSG_NON_PMF : 0;
9756 boot_mode = SHMEM_RD(bp,
9757 dev_info.port_feature_config[BP_PORT(bp)].mba_config) &
9758 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK;
9759 switch (boot_mode) {
9760 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE:
9761 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_PXE;
9762 break;
9763 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB:
9764 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_ISCSI;
9765 break;
9766 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT:
9767 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_FCOE;
9768 break;
9769 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE:
9770 bp->common.boot_mode = FEATURE_ETH_BOOTMODE_NONE;
9771 break;
9772 }
9773
9774 pci_read_config_word(bp->pdev, bp->pm_cap + PCI_PM_PMC, &pmc);
9775 bp->flags |= (pmc & PCI_PM_CAP_PME_D3cold) ? 0 : NO_WOL_FLAG;
9776
9777 BNX2X_DEV_INFO("%sWoL capable\n",
9778 (bp->flags & NO_WOL_FLAG) ? "not " : "");
9779
9780 val = SHMEM_RD(bp, dev_info.shared_hw_config.part_num);
9781 val2 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[4]);
9782 val3 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[8]);
9783 val4 = SHMEM_RD(bp, dev_info.shared_hw_config.part_num[12]);
9784
9785 dev_info(&bp->pdev->dev, "part number %X-%X-%X-%X\n",
9786 val, val2, val3, val4);
9787 }
9788
9789 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9790 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9791
9792 static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
9793 {
9794 int pfid = BP_FUNC(bp);
9795 int igu_sb_id;
9796 u32 val;
9797 u8 fid, igu_sb_cnt = 0;
9798
9799 bp->igu_base_sb = 0xff;
9800 if (CHIP_INT_MODE_IS_BC(bp)) {
9801 int vn = BP_VN(bp);
9802 igu_sb_cnt = bp->igu_sb_cnt;
9803 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
9804 FP_SB_MAX_E1x;
9805
9806 bp->igu_dsb_id = E1HVN_MAX * FP_SB_MAX_E1x +
9807 (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn);
9808
9809 return;
9810 }
9811
9812 /* IGU in normal mode - read CAM */
9813 for (igu_sb_id = 0; igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE;
9814 igu_sb_id++) {
9815 val = REG_RD(bp, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4);
9816 if (!(val & IGU_REG_MAPPING_MEMORY_VALID))
9817 continue;
9818 fid = IGU_FID(val);
9819 if ((fid & IGU_FID_ENCODE_IS_PF)) {
9820 if ((fid & IGU_FID_PF_NUM_MASK) != pfid)
9821 continue;
9822 if (IGU_VEC(val) == 0)
9823 /* default status block */
9824 bp->igu_dsb_id = igu_sb_id;
9825 else {
9826 if (bp->igu_base_sb == 0xff)
9827 bp->igu_base_sb = igu_sb_id;
9828 igu_sb_cnt++;
9829 }
9830 }
9831 }
9832
9833 #ifdef CONFIG_PCI_MSI
9834 /*
9835 * It's expected that number of CAM entries for this functions is equal
9836 * to the number evaluated based on the MSI-X table size. We want a
9837 * harsh warning if these values are different!
9838 */
9839 WARN_ON(bp->igu_sb_cnt != igu_sb_cnt);
9840 #endif
9841
9842 if (igu_sb_cnt == 0)
9843 BNX2X_ERR("CAM configuration error\n");
9844 }
9845
9846 static void __devinit bnx2x_link_settings_supported(struct bnx2x *bp,
9847 u32 switch_cfg)
9848 {
9849 int cfg_size = 0, idx, port = BP_PORT(bp);
9850
9851 /* Aggregation of supported attributes of all external phys */
9852 bp->port.supported[0] = 0;
9853 bp->port.supported[1] = 0;
9854 switch (bp->link_params.num_phys) {
9855 case 1:
9856 bp->port.supported[0] = bp->link_params.phy[INT_PHY].supported;
9857 cfg_size = 1;
9858 break;
9859 case 2:
9860 bp->port.supported[0] = bp->link_params.phy[EXT_PHY1].supported;
9861 cfg_size = 1;
9862 break;
9863 case 3:
9864 if (bp->link_params.multi_phy_config &
9865 PORT_HW_CFG_PHY_SWAPPED_ENABLED) {
9866 bp->port.supported[1] =
9867 bp->link_params.phy[EXT_PHY1].supported;
9868 bp->port.supported[0] =
9869 bp->link_params.phy[EXT_PHY2].supported;
9870 } else {
9871 bp->port.supported[0] =
9872 bp->link_params.phy[EXT_PHY1].supported;
9873 bp->port.supported[1] =
9874 bp->link_params.phy[EXT_PHY2].supported;
9875 }
9876 cfg_size = 2;
9877 break;
9878 }
9879
9880 if (!(bp->port.supported[0] || bp->port.supported[1])) {
9881 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
9882 SHMEM_RD(bp,
9883 dev_info.port_hw_config[port].external_phy_config),
9884 SHMEM_RD(bp,
9885 dev_info.port_hw_config[port].external_phy_config2));
9886 return;
9887 }
9888
9889 if (CHIP_IS_E3(bp))
9890 bp->port.phy_addr = REG_RD(bp, MISC_REG_WC0_CTRL_PHY_ADDR);
9891 else {
9892 switch (switch_cfg) {
9893 case SWITCH_CFG_1G:
9894 bp->port.phy_addr = REG_RD(
9895 bp, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10);
9896 break;
9897 case SWITCH_CFG_10G:
9898 bp->port.phy_addr = REG_RD(
9899 bp, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18);
9900 break;
9901 default:
9902 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9903 bp->port.link_config[0]);
9904 return;
9905 }
9906 }
9907 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp->port.phy_addr);
9908 /* mask what we support according to speed_cap_mask per configuration */
9909 for (idx = 0; idx < cfg_size; idx++) {
9910 if (!(bp->link_params.speed_cap_mask[idx] &
9911 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF))
9912 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Half;
9913
9914 if (!(bp->link_params.speed_cap_mask[idx] &
9915 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL))
9916 bp->port.supported[idx] &= ~SUPPORTED_10baseT_Full;
9917
9918 if (!(bp->link_params.speed_cap_mask[idx] &
9919 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF))
9920 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Half;
9921
9922 if (!(bp->link_params.speed_cap_mask[idx] &
9923 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL))
9924 bp->port.supported[idx] &= ~SUPPORTED_100baseT_Full;
9925
9926 if (!(bp->link_params.speed_cap_mask[idx] &
9927 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G))
9928 bp->port.supported[idx] &= ~(SUPPORTED_1000baseT_Half |
9929 SUPPORTED_1000baseT_Full);
9930
9931 if (!(bp->link_params.speed_cap_mask[idx] &
9932 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
9933 bp->port.supported[idx] &= ~SUPPORTED_2500baseX_Full;
9934
9935 if (!(bp->link_params.speed_cap_mask[idx] &
9936 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G))
9937 bp->port.supported[idx] &= ~SUPPORTED_10000baseT_Full;
9938
9939 }
9940
9941 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp->port.supported[0],
9942 bp->port.supported[1]);
9943 }
9944
9945 static void __devinit bnx2x_link_settings_requested(struct bnx2x *bp)
9946 {
9947 u32 link_config, idx, cfg_size = 0;
9948 bp->port.advertising[0] = 0;
9949 bp->port.advertising[1] = 0;
9950 switch (bp->link_params.num_phys) {
9951 case 1:
9952 case 2:
9953 cfg_size = 1;
9954 break;
9955 case 3:
9956 cfg_size = 2;
9957 break;
9958 }
9959 for (idx = 0; idx < cfg_size; idx++) {
9960 bp->link_params.req_duplex[idx] = DUPLEX_FULL;
9961 link_config = bp->port.link_config[idx];
9962 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
9963 case PORT_FEATURE_LINK_SPEED_AUTO:
9964 if (bp->port.supported[idx] & SUPPORTED_Autoneg) {
9965 bp->link_params.req_line_speed[idx] =
9966 SPEED_AUTO_NEG;
9967 bp->port.advertising[idx] |=
9968 bp->port.supported[idx];
9969 if (bp->link_params.phy[EXT_PHY1].type ==
9970 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833)
9971 bp->port.advertising[idx] |=
9972 (SUPPORTED_100baseT_Half |
9973 SUPPORTED_100baseT_Full);
9974 } else {
9975 /* force 10G, no AN */
9976 bp->link_params.req_line_speed[idx] =
9977 SPEED_10000;
9978 bp->port.advertising[idx] |=
9979 (ADVERTISED_10000baseT_Full |
9980 ADVERTISED_FIBRE);
9981 continue;
9982 }
9983 break;
9984
9985 case PORT_FEATURE_LINK_SPEED_10M_FULL:
9986 if (bp->port.supported[idx] & SUPPORTED_10baseT_Full) {
9987 bp->link_params.req_line_speed[idx] =
9988 SPEED_10;
9989 bp->port.advertising[idx] |=
9990 (ADVERTISED_10baseT_Full |
9991 ADVERTISED_TP);
9992 } else {
9993 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9994 link_config,
9995 bp->link_params.speed_cap_mask[idx]);
9996 return;
9997 }
9998 break;
9999
10000 case PORT_FEATURE_LINK_SPEED_10M_HALF:
10001 if (bp->port.supported[idx] & SUPPORTED_10baseT_Half) {
10002 bp->link_params.req_line_speed[idx] =
10003 SPEED_10;
10004 bp->link_params.req_duplex[idx] =
10005 DUPLEX_HALF;
10006 bp->port.advertising[idx] |=
10007 (ADVERTISED_10baseT_Half |
10008 ADVERTISED_TP);
10009 } else {
10010 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10011 link_config,
10012 bp->link_params.speed_cap_mask[idx]);
10013 return;
10014 }
10015 break;
10016
10017 case PORT_FEATURE_LINK_SPEED_100M_FULL:
10018 if (bp->port.supported[idx] &
10019 SUPPORTED_100baseT_Full) {
10020 bp->link_params.req_line_speed[idx] =
10021 SPEED_100;
10022 bp->port.advertising[idx] |=
10023 (ADVERTISED_100baseT_Full |
10024 ADVERTISED_TP);
10025 } else {
10026 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10027 link_config,
10028 bp->link_params.speed_cap_mask[idx]);
10029 return;
10030 }
10031 break;
10032
10033 case PORT_FEATURE_LINK_SPEED_100M_HALF:
10034 if (bp->port.supported[idx] &
10035 SUPPORTED_100baseT_Half) {
10036 bp->link_params.req_line_speed[idx] =
10037 SPEED_100;
10038 bp->link_params.req_duplex[idx] =
10039 DUPLEX_HALF;
10040 bp->port.advertising[idx] |=
10041 (ADVERTISED_100baseT_Half |
10042 ADVERTISED_TP);
10043 } else {
10044 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10045 link_config,
10046 bp->link_params.speed_cap_mask[idx]);
10047 return;
10048 }
10049 break;
10050
10051 case PORT_FEATURE_LINK_SPEED_1G:
10052 if (bp->port.supported[idx] &
10053 SUPPORTED_1000baseT_Full) {
10054 bp->link_params.req_line_speed[idx] =
10055 SPEED_1000;
10056 bp->port.advertising[idx] |=
10057 (ADVERTISED_1000baseT_Full |
10058 ADVERTISED_TP);
10059 } else {
10060 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10061 link_config,
10062 bp->link_params.speed_cap_mask[idx]);
10063 return;
10064 }
10065 break;
10066
10067 case PORT_FEATURE_LINK_SPEED_2_5G:
10068 if (bp->port.supported[idx] &
10069 SUPPORTED_2500baseX_Full) {
10070 bp->link_params.req_line_speed[idx] =
10071 SPEED_2500;
10072 bp->port.advertising[idx] |=
10073 (ADVERTISED_2500baseX_Full |
10074 ADVERTISED_TP);
10075 } else {
10076 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10077 link_config,
10078 bp->link_params.speed_cap_mask[idx]);
10079 return;
10080 }
10081 break;
10082
10083 case PORT_FEATURE_LINK_SPEED_10G_CX4:
10084 if (bp->port.supported[idx] &
10085 SUPPORTED_10000baseT_Full) {
10086 bp->link_params.req_line_speed[idx] =
10087 SPEED_10000;
10088 bp->port.advertising[idx] |=
10089 (ADVERTISED_10000baseT_Full |
10090 ADVERTISED_FIBRE);
10091 } else {
10092 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
10093 link_config,
10094 bp->link_params.speed_cap_mask[idx]);
10095 return;
10096 }
10097 break;
10098 case PORT_FEATURE_LINK_SPEED_20G:
10099 bp->link_params.req_line_speed[idx] = SPEED_20000;
10100
10101 break;
10102 default:
10103 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
10104 link_config);
10105 bp->link_params.req_line_speed[idx] =
10106 SPEED_AUTO_NEG;
10107 bp->port.advertising[idx] =
10108 bp->port.supported[idx];
10109 break;
10110 }
10111
10112 bp->link_params.req_flow_ctrl[idx] = (link_config &
10113 PORT_FEATURE_FLOW_CONTROL_MASK);
10114 if ((bp->link_params.req_flow_ctrl[idx] ==
10115 BNX2X_FLOW_CTRL_AUTO) &&
10116 !(bp->port.supported[idx] & SUPPORTED_Autoneg)) {
10117 bp->link_params.req_flow_ctrl[idx] =
10118 BNX2X_FLOW_CTRL_NONE;
10119 }
10120
10121 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
10122 bp->link_params.req_line_speed[idx],
10123 bp->link_params.req_duplex[idx],
10124 bp->link_params.req_flow_ctrl[idx],
10125 bp->port.advertising[idx]);
10126 }
10127 }
10128
10129 static void __devinit bnx2x_set_mac_buf(u8 *mac_buf, u32 mac_lo, u16 mac_hi)
10130 {
10131 mac_hi = cpu_to_be16(mac_hi);
10132 mac_lo = cpu_to_be32(mac_lo);
10133 memcpy(mac_buf, &mac_hi, sizeof(mac_hi));
10134 memcpy(mac_buf + sizeof(mac_hi), &mac_lo, sizeof(mac_lo));
10135 }
10136
10137 static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
10138 {
10139 int port = BP_PORT(bp);
10140 u32 config;
10141 u32 ext_phy_type, ext_phy_config, eee_mode;
10142
10143 bp->link_params.bp = bp;
10144 bp->link_params.port = port;
10145
10146 bp->link_params.lane_config =
10147 SHMEM_RD(bp, dev_info.port_hw_config[port].lane_config);
10148
10149 bp->link_params.speed_cap_mask[0] =
10150 SHMEM_RD(bp,
10151 dev_info.port_hw_config[port].speed_capability_mask);
10152 bp->link_params.speed_cap_mask[1] =
10153 SHMEM_RD(bp,
10154 dev_info.port_hw_config[port].speed_capability_mask2);
10155 bp->port.link_config[0] =
10156 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config);
10157
10158 bp->port.link_config[1] =
10159 SHMEM_RD(bp, dev_info.port_feature_config[port].link_config2);
10160
10161 bp->link_params.multi_phy_config =
10162 SHMEM_RD(bp, dev_info.port_hw_config[port].multi_phy_config);
10163 /* If the device is capable of WoL, set the default state according
10164 * to the HW
10165 */
10166 config = SHMEM_RD(bp, dev_info.port_feature_config[port].config);
10167 bp->wol = (!(bp->flags & NO_WOL_FLAG) &&
10168 (config & PORT_FEATURE_WOL_ENABLED));
10169
10170 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
10171 bp->link_params.lane_config,
10172 bp->link_params.speed_cap_mask[0],
10173 bp->port.link_config[0]);
10174
10175 bp->link_params.switch_cfg = (bp->port.link_config[0] &
10176 PORT_FEATURE_CONNECTED_SWITCH_MASK);
10177 bnx2x_phy_probe(&bp->link_params);
10178 bnx2x_link_settings_supported(bp, bp->link_params.switch_cfg);
10179
10180 bnx2x_link_settings_requested(bp);
10181
10182 /*
10183 * If connected directly, work with the internal PHY, otherwise, work
10184 * with the external PHY
10185 */
10186 ext_phy_config =
10187 SHMEM_RD(bp,
10188 dev_info.port_hw_config[port].external_phy_config);
10189 ext_phy_type = XGXS_EXT_PHY_TYPE(ext_phy_config);
10190 if (ext_phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
10191 bp->mdio.prtad = bp->port.phy_addr;
10192
10193 else if ((ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) &&
10194 (ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
10195 bp->mdio.prtad =
10196 XGXS_EXT_PHY_ADDR(ext_phy_config);
10197
10198 /*
10199 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
10200 * In MF mode, it is set to cover self test cases
10201 */
10202 if (IS_MF(bp))
10203 bp->port.need_hw_lock = 1;
10204 else
10205 bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
10206 bp->common.shmem_base,
10207 bp->common.shmem2_base);
10208
10209 /* Configure link feature according to nvram value */
10210 eee_mode = (((SHMEM_RD(bp, dev_info.
10211 port_feature_config[port].eee_power_mode)) &
10212 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
10213 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
10214 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) {
10215 bp->link_params.eee_mode = EEE_MODE_ADV_LPI |
10216 EEE_MODE_ENABLE_LPI |
10217 EEE_MODE_OUTPUT_TIME;
10218 } else {
10219 bp->link_params.eee_mode = 0;
10220 }
10221 }
10222
10223 void bnx2x_get_iscsi_info(struct bnx2x *bp)
10224 {
10225 u32 no_flags = NO_ISCSI_FLAG;
10226 #ifdef BCM_CNIC
10227 int port = BP_PORT(bp);
10228
10229 u32 max_iscsi_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10230 drv_lic_key[port].max_iscsi_conn);
10231
10232 /* Get the number of maximum allowed iSCSI connections */
10233 bp->cnic_eth_dev.max_iscsi_conn =
10234 (max_iscsi_conn & BNX2X_MAX_ISCSI_INIT_CONN_MASK) >>
10235 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT;
10236
10237 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
10238 bp->cnic_eth_dev.max_iscsi_conn);
10239
10240 /*
10241 * If maximum allowed number of connections is zero -
10242 * disable the feature.
10243 */
10244 if (!bp->cnic_eth_dev.max_iscsi_conn)
10245 bp->flags |= no_flags;
10246 #else
10247 bp->flags |= no_flags;
10248 #endif
10249 }
10250
10251 #ifdef BCM_CNIC
10252 static void __devinit bnx2x_get_ext_wwn_info(struct bnx2x *bp, int func)
10253 {
10254 /* Port info */
10255 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10256 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_upper);
10257 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10258 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_port_name_lower);
10259
10260 /* Node info */
10261 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10262 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_upper);
10263 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10264 MF_CFG_RD(bp, func_ext_config[func].fcoe_wwn_node_name_lower);
10265 }
10266 #endif
10267 static void __devinit bnx2x_get_fcoe_info(struct bnx2x *bp)
10268 {
10269 #ifdef BCM_CNIC
10270 int port = BP_PORT(bp);
10271 int func = BP_ABS_FUNC(bp);
10272
10273 u32 max_fcoe_conn = FW_ENCODE_32BIT_PATTERN ^ SHMEM_RD(bp,
10274 drv_lic_key[port].max_fcoe_conn);
10275
10276 /* Get the number of maximum allowed FCoE connections */
10277 bp->cnic_eth_dev.max_fcoe_conn =
10278 (max_fcoe_conn & BNX2X_MAX_FCOE_INIT_CONN_MASK) >>
10279 BNX2X_MAX_FCOE_INIT_CONN_SHIFT;
10280
10281 /* Read the WWN: */
10282 if (!IS_MF(bp)) {
10283 /* Port info */
10284 bp->cnic_eth_dev.fcoe_wwn_port_name_hi =
10285 SHMEM_RD(bp,
10286 dev_info.port_hw_config[port].
10287 fcoe_wwn_port_name_upper);
10288 bp->cnic_eth_dev.fcoe_wwn_port_name_lo =
10289 SHMEM_RD(bp,
10290 dev_info.port_hw_config[port].
10291 fcoe_wwn_port_name_lower);
10292
10293 /* Node info */
10294 bp->cnic_eth_dev.fcoe_wwn_node_name_hi =
10295 SHMEM_RD(bp,
10296 dev_info.port_hw_config[port].
10297 fcoe_wwn_node_name_upper);
10298 bp->cnic_eth_dev.fcoe_wwn_node_name_lo =
10299 SHMEM_RD(bp,
10300 dev_info.port_hw_config[port].
10301 fcoe_wwn_node_name_lower);
10302 } else if (!IS_MF_SD(bp)) {
10303 /*
10304 * Read the WWN info only if the FCoE feature is enabled for
10305 * this function.
10306 */
10307 if (BNX2X_MF_EXT_PROTOCOL_FCOE(bp) && !CHIP_IS_E1x(bp))
10308 bnx2x_get_ext_wwn_info(bp, func);
10309
10310 } else if (IS_MF_FCOE_SD(bp))
10311 bnx2x_get_ext_wwn_info(bp, func);
10312
10313 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp->cnic_eth_dev.max_fcoe_conn);
10314
10315 /*
10316 * If maximum allowed number of connections is zero -
10317 * disable the feature.
10318 */
10319 if (!bp->cnic_eth_dev.max_fcoe_conn)
10320 bp->flags |= NO_FCOE_FLAG;
10321 #else
10322 bp->flags |= NO_FCOE_FLAG;
10323 #endif
10324 }
10325
10326 static void __devinit bnx2x_get_cnic_info(struct bnx2x *bp)
10327 {
10328 /*
10329 * iSCSI may be dynamically disabled but reading
10330 * info here we will decrease memory usage by driver
10331 * if the feature is disabled for good
10332 */
10333 bnx2x_get_iscsi_info(bp);
10334 bnx2x_get_fcoe_info(bp);
10335 }
10336
10337 static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)
10338 {
10339 u32 val, val2;
10340 int func = BP_ABS_FUNC(bp);
10341 int port = BP_PORT(bp);
10342 #ifdef BCM_CNIC
10343 u8 *iscsi_mac = bp->cnic_eth_dev.iscsi_mac;
10344 u8 *fip_mac = bp->fip_mac;
10345 #endif
10346
10347 /* Zero primary MAC configuration */
10348 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10349
10350 if (BP_NOMCP(bp)) {
10351 BNX2X_ERROR("warning: random MAC workaround active\n");
10352 eth_hw_addr_random(bp->dev);
10353 } else if (IS_MF(bp)) {
10354 val2 = MF_CFG_RD(bp, func_mf_config[func].mac_upper);
10355 val = MF_CFG_RD(bp, func_mf_config[func].mac_lower);
10356 if ((val2 != FUNC_MF_CFG_UPPERMAC_DEFAULT) &&
10357 (val != FUNC_MF_CFG_LOWERMAC_DEFAULT))
10358 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10359
10360 #ifdef BCM_CNIC
10361 /*
10362 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
10363 * FCoE MAC then the appropriate feature should be disabled.
10364 *
10365 * In non SD mode features configuration comes from
10366 * struct func_ext_config.
10367 */
10368 if (!IS_MF_SD(bp)) {
10369 u32 cfg = MF_CFG_RD(bp, func_ext_config[func].func_cfg);
10370 if (cfg & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) {
10371 val2 = MF_CFG_RD(bp, func_ext_config[func].
10372 iscsi_mac_addr_upper);
10373 val = MF_CFG_RD(bp, func_ext_config[func].
10374 iscsi_mac_addr_lower);
10375 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10376 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10377 iscsi_mac);
10378 } else
10379 bp->flags |= NO_ISCSI_OOO_FLAG | NO_ISCSI_FLAG;
10380
10381 if (cfg & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) {
10382 val2 = MF_CFG_RD(bp, func_ext_config[func].
10383 fcoe_mac_addr_upper);
10384 val = MF_CFG_RD(bp, func_ext_config[func].
10385 fcoe_mac_addr_lower);
10386 bnx2x_set_mac_buf(fip_mac, val, val2);
10387 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
10388 fip_mac);
10389
10390 } else
10391 bp->flags |= NO_FCOE_FLAG;
10392
10393 bp->mf_ext_config = cfg;
10394
10395 } else { /* SD MODE */
10396 if (IS_MF_STORAGE_SD(bp)) {
10397 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp)) {
10398 /* use primary mac as iscsi mac */
10399 memcpy(iscsi_mac, bp->dev->dev_addr,
10400 ETH_ALEN);
10401
10402 BNX2X_DEV_INFO("SD ISCSI MODE\n");
10403 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
10404 iscsi_mac);
10405 } else { /* FCoE */
10406 memcpy(fip_mac, bp->dev->dev_addr,
10407 ETH_ALEN);
10408 BNX2X_DEV_INFO("SD FCoE MODE\n");
10409 BNX2X_DEV_INFO("Read FIP MAC: %pM\n",
10410 fip_mac);
10411 }
10412 /* Zero primary MAC configuration */
10413 memset(bp->dev->dev_addr, 0, ETH_ALEN);
10414 }
10415 }
10416
10417 if (IS_MF_FCOE_AFEX(bp))
10418 /* use FIP MAC as primary MAC */
10419 memcpy(bp->dev->dev_addr, fip_mac, ETH_ALEN);
10420
10421 #endif
10422 } else {
10423 /* in SF read MACs from port configuration */
10424 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_upper);
10425 val = SHMEM_RD(bp, dev_info.port_hw_config[port].mac_lower);
10426 bnx2x_set_mac_buf(bp->dev->dev_addr, val, val2);
10427
10428 #ifdef BCM_CNIC
10429 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10430 iscsi_mac_upper);
10431 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10432 iscsi_mac_lower);
10433 bnx2x_set_mac_buf(iscsi_mac, val, val2);
10434
10435 val2 = SHMEM_RD(bp, dev_info.port_hw_config[port].
10436 fcoe_fip_mac_upper);
10437 val = SHMEM_RD(bp, dev_info.port_hw_config[port].
10438 fcoe_fip_mac_lower);
10439 bnx2x_set_mac_buf(fip_mac, val, val2);
10440 #endif
10441 }
10442
10443 memcpy(bp->link_params.mac_addr, bp->dev->dev_addr, ETH_ALEN);
10444 memcpy(bp->dev->perm_addr, bp->dev->dev_addr, ETH_ALEN);
10445
10446 #ifdef BCM_CNIC
10447 /* Disable iSCSI if MAC configuration is
10448 * invalid.
10449 */
10450 if (!is_valid_ether_addr(iscsi_mac)) {
10451 bp->flags |= NO_ISCSI_FLAG;
10452 memset(iscsi_mac, 0, ETH_ALEN);
10453 }
10454
10455 /* Disable FCoE if MAC configuration is
10456 * invalid.
10457 */
10458 if (!is_valid_ether_addr(fip_mac)) {
10459 bp->flags |= NO_FCOE_FLAG;
10460 memset(bp->fip_mac, 0, ETH_ALEN);
10461 }
10462 #endif
10463
10464 if (!bnx2x_is_valid_ether_addr(bp, bp->dev->dev_addr))
10465 dev_err(&bp->pdev->dev,
10466 "bad Ethernet MAC address configuration: %pM\n"
10467 "change it manually before bringing up the appropriate network interface\n",
10468 bp->dev->dev_addr);
10469
10470
10471 }
10472
10473 static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
10474 {
10475 int /*abs*/func = BP_ABS_FUNC(bp);
10476 int vn;
10477 u32 val = 0;
10478 int rc = 0;
10479
10480 bnx2x_get_common_hwinfo(bp);
10481
10482 /*
10483 * initialize IGU parameters
10484 */
10485 if (CHIP_IS_E1x(bp)) {
10486 bp->common.int_block = INT_BLOCK_HC;
10487
10488 bp->igu_dsb_id = DEF_SB_IGU_ID;
10489 bp->igu_base_sb = 0;
10490 } else {
10491 bp->common.int_block = INT_BLOCK_IGU;
10492
10493 /* do not allow device reset during IGU info preocessing */
10494 bnx2x_acquire_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10495
10496 val = REG_RD(bp, IGU_REG_BLOCK_CONFIGURATION);
10497
10498 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10499 int tout = 5000;
10500
10501 BNX2X_DEV_INFO("FORCING Normal Mode\n");
10502
10503 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN);
10504 REG_WR(bp, IGU_REG_BLOCK_CONFIGURATION, val);
10505 REG_WR(bp, IGU_REG_RESET_MEMORIES, 0x7f);
10506
10507 while (tout && REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10508 tout--;
10509 usleep_range(1000, 1000);
10510 }
10511
10512 if (REG_RD(bp, IGU_REG_RESET_MEMORIES)) {
10513 dev_err(&bp->pdev->dev,
10514 "FORCING Normal Mode failed!!!\n");
10515 return -EPERM;
10516 }
10517 }
10518
10519 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) {
10520 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
10521 bp->common.int_block |= INT_BLOCK_MODE_BW_COMP;
10522 } else
10523 BNX2X_DEV_INFO("IGU Normal Mode\n");
10524
10525 bnx2x_get_igu_cam_info(bp);
10526
10527 bnx2x_release_hw_lock(bp, HW_LOCK_RESOURCE_RESET);
10528 }
10529
10530 /*
10531 * set base FW non-default (fast path) status block id, this value is
10532 * used to initialize the fw_sb_id saved on the fp/queue structure to
10533 * determine the id used by the FW.
10534 */
10535 if (CHIP_IS_E1x(bp))
10536 bp->base_fw_ndsb = BP_PORT(bp) * FP_SB_MAX_E1x + BP_L_ID(bp);
10537 else /*
10538 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
10539 * the same queue are indicated on the same IGU SB). So we prefer
10540 * FW and IGU SBs to be the same value.
10541 */
10542 bp->base_fw_ndsb = bp->igu_base_sb;
10543
10544 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
10545 "base_fw_ndsb %d\n", bp->igu_dsb_id, bp->igu_base_sb,
10546 bp->igu_sb_cnt, bp->base_fw_ndsb);
10547
10548 /*
10549 * Initialize MF configuration
10550 */
10551
10552 bp->mf_ov = 0;
10553 bp->mf_mode = 0;
10554 vn = BP_VN(bp);
10555
10556 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
10557 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
10558 bp->common.shmem2_base, SHMEM2_RD(bp, size),
10559 (u32)offsetof(struct shmem2_region, mf_cfg_addr));
10560
10561 if (SHMEM2_HAS(bp, mf_cfg_addr))
10562 bp->common.mf_cfg_base = SHMEM2_RD(bp, mf_cfg_addr);
10563 else
10564 bp->common.mf_cfg_base = bp->common.shmem_base +
10565 offsetof(struct shmem_region, func_mb) +
10566 E1H_FUNC_MAX * sizeof(struct drv_func_mb);
10567 /*
10568 * get mf configuration:
10569 * 1. existence of MF configuration
10570 * 2. MAC address must be legal (check only upper bytes)
10571 * for Switch-Independent mode;
10572 * OVLAN must be legal for Switch-Dependent mode
10573 * 3. SF_MODE configures specific MF mode
10574 */
10575 if (bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10576 /* get mf configuration */
10577 val = SHMEM_RD(bp,
10578 dev_info.shared_feature_config.config);
10579 val &= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK;
10580
10581 switch (val) {
10582 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT:
10583 val = MF_CFG_RD(bp, func_mf_config[func].
10584 mac_upper);
10585 /* check for legal mac (upper bytes)*/
10586 if (val != 0xffff) {
10587 bp->mf_mode = MULTI_FUNCTION_SI;
10588 bp->mf_config[vn] = MF_CFG_RD(bp,
10589 func_mf_config[func].config);
10590 } else
10591 BNX2X_DEV_INFO("illegal MAC address for SI\n");
10592 break;
10593 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE:
10594 if ((!CHIP_IS_E1x(bp)) &&
10595 (MF_CFG_RD(bp, func_mf_config[func].
10596 mac_upper) != 0xffff) &&
10597 (SHMEM2_HAS(bp,
10598 afex_driver_support))) {
10599 bp->mf_mode = MULTI_FUNCTION_AFEX;
10600 bp->mf_config[vn] = MF_CFG_RD(bp,
10601 func_mf_config[func].config);
10602 } else {
10603 BNX2X_DEV_INFO("can not configure afex mode\n");
10604 }
10605 break;
10606 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED:
10607 /* get OV configuration */
10608 val = MF_CFG_RD(bp,
10609 func_mf_config[FUNC_0].e1hov_tag);
10610 val &= FUNC_MF_CFG_E1HOV_TAG_MASK;
10611
10612 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10613 bp->mf_mode = MULTI_FUNCTION_SD;
10614 bp->mf_config[vn] = MF_CFG_RD(bp,
10615 func_mf_config[func].config);
10616 } else
10617 BNX2X_DEV_INFO("illegal OV for SD\n");
10618 break;
10619 default:
10620 /* Unknown configuration: reset mf_config */
10621 bp->mf_config[vn] = 0;
10622 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val);
10623 }
10624 }
10625
10626 BNX2X_DEV_INFO("%s function mode\n",
10627 IS_MF(bp) ? "multi" : "single");
10628
10629 switch (bp->mf_mode) {
10630 case MULTI_FUNCTION_SD:
10631 val = MF_CFG_RD(bp, func_mf_config[func].e1hov_tag) &
10632 FUNC_MF_CFG_E1HOV_TAG_MASK;
10633 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT) {
10634 bp->mf_ov = val;
10635 bp->path_has_ovlan = true;
10636
10637 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
10638 func, bp->mf_ov, bp->mf_ov);
10639 } else {
10640 dev_err(&bp->pdev->dev,
10641 "No valid MF OV for func %d, aborting\n",
10642 func);
10643 return -EPERM;
10644 }
10645 break;
10646 case MULTI_FUNCTION_AFEX:
10647 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func);
10648 break;
10649 case MULTI_FUNCTION_SI:
10650 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
10651 func);
10652 break;
10653 default:
10654 if (vn) {
10655 dev_err(&bp->pdev->dev,
10656 "VN %d is in a single function mode, aborting\n",
10657 vn);
10658 return -EPERM;
10659 }
10660 break;
10661 }
10662
10663 /* check if other port on the path needs ovlan:
10664 * Since MF configuration is shared between ports
10665 * Possible mixed modes are only
10666 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
10667 */
10668 if (CHIP_MODE_IS_4_PORT(bp) &&
10669 !bp->path_has_ovlan &&
10670 !IS_MF(bp) &&
10671 bp->common.mf_cfg_base != SHMEM_MF_CFG_ADDR_NONE) {
10672 u8 other_port = !BP_PORT(bp);
10673 u8 other_func = BP_PATH(bp) + 2*other_port;
10674 val = MF_CFG_RD(bp,
10675 func_mf_config[other_func].e1hov_tag);
10676 if (val != FUNC_MF_CFG_E1HOV_TAG_DEFAULT)
10677 bp->path_has_ovlan = true;
10678 }
10679 }
10680
10681 /* adjust igu_sb_cnt to MF for E1x */
10682 if (CHIP_IS_E1x(bp) && IS_MF(bp))
10683 bp->igu_sb_cnt /= E1HVN_MAX;
10684
10685 /* port info */
10686 bnx2x_get_port_hwinfo(bp);
10687
10688 /* Get MAC addresses */
10689 bnx2x_get_mac_hwinfo(bp);
10690
10691 bnx2x_get_cnic_info(bp);
10692
10693 return rc;
10694 }
10695
10696 static void __devinit bnx2x_read_fwinfo(struct bnx2x *bp)
10697 {
10698 int cnt, i, block_end, rodi;
10699 char vpd_start[BNX2X_VPD_LEN+1];
10700 char str_id_reg[VENDOR_ID_LEN+1];
10701 char str_id_cap[VENDOR_ID_LEN+1];
10702 char *vpd_data;
10703 char *vpd_extended_data = NULL;
10704 u8 len;
10705
10706 cnt = pci_read_vpd(bp->pdev, 0, BNX2X_VPD_LEN, vpd_start);
10707 memset(bp->fw_ver, 0, sizeof(bp->fw_ver));
10708
10709 if (cnt < BNX2X_VPD_LEN)
10710 goto out_not_found;
10711
10712 /* VPD RO tag should be first tag after identifier string, hence
10713 * we should be able to find it in first BNX2X_VPD_LEN chars
10714 */
10715 i = pci_vpd_find_tag(vpd_start, 0, BNX2X_VPD_LEN,
10716 PCI_VPD_LRDT_RO_DATA);
10717 if (i < 0)
10718 goto out_not_found;
10719
10720 block_end = i + PCI_VPD_LRDT_TAG_SIZE +
10721 pci_vpd_lrdt_size(&vpd_start[i]);
10722
10723 i += PCI_VPD_LRDT_TAG_SIZE;
10724
10725 if (block_end > BNX2X_VPD_LEN) {
10726 vpd_extended_data = kmalloc(block_end, GFP_KERNEL);
10727 if (vpd_extended_data == NULL)
10728 goto out_not_found;
10729
10730 /* read rest of vpd image into vpd_extended_data */
10731 memcpy(vpd_extended_data, vpd_start, BNX2X_VPD_LEN);
10732 cnt = pci_read_vpd(bp->pdev, BNX2X_VPD_LEN,
10733 block_end - BNX2X_VPD_LEN,
10734 vpd_extended_data + BNX2X_VPD_LEN);
10735 if (cnt < (block_end - BNX2X_VPD_LEN))
10736 goto out_not_found;
10737 vpd_data = vpd_extended_data;
10738 } else
10739 vpd_data = vpd_start;
10740
10741 /* now vpd_data holds full vpd content in both cases */
10742
10743 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10744 PCI_VPD_RO_KEYWORD_MFR_ID);
10745 if (rodi < 0)
10746 goto out_not_found;
10747
10748 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10749
10750 if (len != VENDOR_ID_LEN)
10751 goto out_not_found;
10752
10753 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10754
10755 /* vendor specific info */
10756 snprintf(str_id_reg, VENDOR_ID_LEN + 1, "%04x", PCI_VENDOR_ID_DELL);
10757 snprintf(str_id_cap, VENDOR_ID_LEN + 1, "%04X", PCI_VENDOR_ID_DELL);
10758 if (!strncmp(str_id_reg, &vpd_data[rodi], VENDOR_ID_LEN) ||
10759 !strncmp(str_id_cap, &vpd_data[rodi], VENDOR_ID_LEN)) {
10760
10761 rodi = pci_vpd_find_info_keyword(vpd_data, i, block_end,
10762 PCI_VPD_RO_KEYWORD_VENDOR0);
10763 if (rodi >= 0) {
10764 len = pci_vpd_info_field_size(&vpd_data[rodi]);
10765
10766 rodi += PCI_VPD_INFO_FLD_HDR_SIZE;
10767
10768 if (len < 32 && (len + rodi) <= BNX2X_VPD_LEN) {
10769 memcpy(bp->fw_ver, &vpd_data[rodi], len);
10770 bp->fw_ver[len] = ' ';
10771 }
10772 }
10773 kfree(vpd_extended_data);
10774 return;
10775 }
10776 out_not_found:
10777 kfree(vpd_extended_data);
10778 return;
10779 }
10780
10781 static void __devinit bnx2x_set_modes_bitmap(struct bnx2x *bp)
10782 {
10783 u32 flags = 0;
10784
10785 if (CHIP_REV_IS_FPGA(bp))
10786 SET_FLAGS(flags, MODE_FPGA);
10787 else if (CHIP_REV_IS_EMUL(bp))
10788 SET_FLAGS(flags, MODE_EMUL);
10789 else
10790 SET_FLAGS(flags, MODE_ASIC);
10791
10792 if (CHIP_MODE_IS_4_PORT(bp))
10793 SET_FLAGS(flags, MODE_PORT4);
10794 else
10795 SET_FLAGS(flags, MODE_PORT2);
10796
10797 if (CHIP_IS_E2(bp))
10798 SET_FLAGS(flags, MODE_E2);
10799 else if (CHIP_IS_E3(bp)) {
10800 SET_FLAGS(flags, MODE_E3);
10801 if (CHIP_REV(bp) == CHIP_REV_Ax)
10802 SET_FLAGS(flags, MODE_E3_A0);
10803 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10804 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3);
10805 }
10806
10807 if (IS_MF(bp)) {
10808 SET_FLAGS(flags, MODE_MF);
10809 switch (bp->mf_mode) {
10810 case MULTI_FUNCTION_SD:
10811 SET_FLAGS(flags, MODE_MF_SD);
10812 break;
10813 case MULTI_FUNCTION_SI:
10814 SET_FLAGS(flags, MODE_MF_SI);
10815 break;
10816 case MULTI_FUNCTION_AFEX:
10817 SET_FLAGS(flags, MODE_MF_AFEX);
10818 break;
10819 }
10820 } else
10821 SET_FLAGS(flags, MODE_SF);
10822
10823 #if defined(__LITTLE_ENDIAN)
10824 SET_FLAGS(flags, MODE_LITTLE_ENDIAN);
10825 #else /*(__BIG_ENDIAN)*/
10826 SET_FLAGS(flags, MODE_BIG_ENDIAN);
10827 #endif
10828 INIT_MODE_FLAGS(bp) = flags;
10829 }
10830
10831 static int __devinit bnx2x_init_bp(struct bnx2x *bp)
10832 {
10833 int func;
10834 int rc;
10835
10836 mutex_init(&bp->port.phy_mutex);
10837 mutex_init(&bp->fw_mb_mutex);
10838 spin_lock_init(&bp->stats_lock);
10839 #ifdef BCM_CNIC
10840 mutex_init(&bp->cnic_mutex);
10841 #endif
10842
10843 INIT_DELAYED_WORK(&bp->sp_task, bnx2x_sp_task);
10844 INIT_DELAYED_WORK(&bp->sp_rtnl_task, bnx2x_sp_rtnl_task);
10845 INIT_DELAYED_WORK(&bp->period_task, bnx2x_period_task);
10846 rc = bnx2x_get_hwinfo(bp);
10847 if (rc)
10848 return rc;
10849
10850 bnx2x_set_modes_bitmap(bp);
10851
10852 rc = bnx2x_alloc_mem_bp(bp);
10853 if (rc)
10854 return rc;
10855
10856 bnx2x_read_fwinfo(bp);
10857
10858 func = BP_FUNC(bp);
10859
10860 /* need to reset chip if undi was active */
10861 if (!BP_NOMCP(bp)) {
10862 /* init fw_seq */
10863 bp->fw_seq =
10864 SHMEM_RD(bp, func_mb[BP_FW_MB_IDX(bp)].drv_mb_header) &
10865 DRV_MSG_SEQ_NUMBER_MASK;
10866 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp->fw_seq);
10867
10868 bnx2x_prev_unload(bp);
10869 }
10870
10871
10872 if (CHIP_REV_IS_FPGA(bp))
10873 dev_err(&bp->pdev->dev, "FPGA detected\n");
10874
10875 if (BP_NOMCP(bp) && (func == 0))
10876 dev_err(&bp->pdev->dev, "MCP disabled, must load devices in order!\n");
10877
10878 bp->disable_tpa = disable_tpa;
10879
10880 #ifdef BCM_CNIC
10881 bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
10882 #endif
10883
10884 /* Set TPA flags */
10885 if (bp->disable_tpa) {
10886 bp->flags &= ~(TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10887 bp->dev->features &= ~NETIF_F_LRO;
10888 } else {
10889 bp->flags |= (TPA_ENABLE_FLAG | GRO_ENABLE_FLAG);
10890 bp->dev->features |= NETIF_F_LRO;
10891 }
10892
10893 if (CHIP_IS_E1(bp))
10894 bp->dropless_fc = 0;
10895 else
10896 bp->dropless_fc = dropless_fc;
10897
10898 bp->mrrs = mrrs;
10899
10900 bp->tx_ring_size = IS_MF_FCOE_AFEX(bp) ? 0 : MAX_TX_AVAIL;
10901
10902 /* make sure that the numbers are in the right granularity */
10903 bp->tx_ticks = (50 / BNX2X_BTR) * BNX2X_BTR;
10904 bp->rx_ticks = (25 / BNX2X_BTR) * BNX2X_BTR;
10905
10906 bp->current_interval = CHIP_REV_IS_SLOW(bp) ? 5*HZ : HZ;
10907
10908 init_timer(&bp->timer);
10909 bp->timer.expires = jiffies + bp->current_interval;
10910 bp->timer.data = (unsigned long) bp;
10911 bp->timer.function = bnx2x_timer;
10912
10913 bnx2x_dcbx_set_state(bp, true, BNX2X_DCBX_ENABLED_ON_NEG_ON);
10914 bnx2x_dcbx_init_params(bp);
10915
10916 #ifdef BCM_CNIC
10917 if (CHIP_IS_E1x(bp))
10918 bp->cnic_base_cl_id = FP_SB_MAX_E1x;
10919 else
10920 bp->cnic_base_cl_id = FP_SB_MAX_E2;
10921 #endif
10922
10923 /* multiple tx priority */
10924 if (CHIP_IS_E1x(bp))
10925 bp->max_cos = BNX2X_MULTI_TX_COS_E1X;
10926 if (CHIP_IS_E2(bp) || CHIP_IS_E3A0(bp))
10927 bp->max_cos = BNX2X_MULTI_TX_COS_E2_E3A0;
10928 if (CHIP_IS_E3B0(bp))
10929 bp->max_cos = BNX2X_MULTI_TX_COS_E3B0;
10930
10931 return rc;
10932 }
10933
10934
10935 /****************************************************************************
10936 * General service functions
10937 ****************************************************************************/
10938
10939 /*
10940 * net_device service functions
10941 */
10942
10943 /* called with rtnl_lock */
10944 static int bnx2x_open(struct net_device *dev)
10945 {
10946 struct bnx2x *bp = netdev_priv(dev);
10947 bool global = false;
10948 int other_engine = BP_PATH(bp) ? 0 : 1;
10949 bool other_load_status, load_status;
10950
10951 bp->stats_init = true;
10952
10953 netif_carrier_off(dev);
10954
10955 bnx2x_set_power_state(bp, PCI_D0);
10956
10957 other_load_status = bnx2x_get_load_status(bp, other_engine);
10958 load_status = bnx2x_get_load_status(bp, BP_PATH(bp));
10959
10960 /*
10961 * If parity had happen during the unload, then attentions
10962 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10963 * want the first function loaded on the current engine to
10964 * complete the recovery.
10965 */
10966 if (!bnx2x_reset_is_done(bp, BP_PATH(bp)) ||
10967 bnx2x_chk_parity_attn(bp, &global, true))
10968 do {
10969 /*
10970 * If there are attentions and they are in a global
10971 * blocks, set the GLOBAL_RESET bit regardless whether
10972 * it will be this function that will complete the
10973 * recovery or not.
10974 */
10975 if (global)
10976 bnx2x_set_reset_global(bp);
10977
10978 /*
10979 * Only the first function on the current engine should
10980 * try to recover in open. In case of attentions in
10981 * global blocks only the first in the chip should try
10982 * to recover.
10983 */
10984 if ((!load_status &&
10985 (!global || !other_load_status)) &&
10986 bnx2x_trylock_leader_lock(bp) &&
10987 !bnx2x_leader_reset(bp)) {
10988 netdev_info(bp->dev, "Recovered in open\n");
10989 break;
10990 }
10991
10992 /* recovery has failed... */
10993 bnx2x_set_power_state(bp, PCI_D3hot);
10994 bp->recovery_state = BNX2X_RECOVERY_FAILED;
10995
10996 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
10997 "If you still see this message after a few retries then power cycle is required.\n");
10998
10999 return -EAGAIN;
11000 } while (0);
11001
11002 bp->recovery_state = BNX2X_RECOVERY_DONE;
11003 return bnx2x_nic_load(bp, LOAD_OPEN);
11004 }
11005
11006 /* called with rtnl_lock */
11007 static int bnx2x_close(struct net_device *dev)
11008 {
11009 struct bnx2x *bp = netdev_priv(dev);
11010
11011 /* Unload the driver, release IRQs */
11012 bnx2x_nic_unload(bp, UNLOAD_CLOSE);
11013
11014 /* Power off */
11015 bnx2x_set_power_state(bp, PCI_D3hot);
11016
11017 return 0;
11018 }
11019
11020 static int bnx2x_init_mcast_macs_list(struct bnx2x *bp,
11021 struct bnx2x_mcast_ramrod_params *p)
11022 {
11023 int mc_count = netdev_mc_count(bp->dev);
11024 struct bnx2x_mcast_list_elem *mc_mac =
11025 kzalloc(sizeof(*mc_mac) * mc_count, GFP_ATOMIC);
11026 struct netdev_hw_addr *ha;
11027
11028 if (!mc_mac)
11029 return -ENOMEM;
11030
11031 INIT_LIST_HEAD(&p->mcast_list);
11032
11033 netdev_for_each_mc_addr(ha, bp->dev) {
11034 mc_mac->mac = bnx2x_mc_addr(ha);
11035 list_add_tail(&mc_mac->link, &p->mcast_list);
11036 mc_mac++;
11037 }
11038
11039 p->mcast_list_len = mc_count;
11040
11041 return 0;
11042 }
11043
11044 static void bnx2x_free_mcast_macs_list(
11045 struct bnx2x_mcast_ramrod_params *p)
11046 {
11047 struct bnx2x_mcast_list_elem *mc_mac =
11048 list_first_entry(&p->mcast_list, struct bnx2x_mcast_list_elem,
11049 link);
11050
11051 WARN_ON(!mc_mac);
11052 kfree(mc_mac);
11053 }
11054
11055 /**
11056 * bnx2x_set_uc_list - configure a new unicast MACs list.
11057 *
11058 * @bp: driver handle
11059 *
11060 * We will use zero (0) as a MAC type for these MACs.
11061 */
11062 static int bnx2x_set_uc_list(struct bnx2x *bp)
11063 {
11064 int rc;
11065 struct net_device *dev = bp->dev;
11066 struct netdev_hw_addr *ha;
11067 struct bnx2x_vlan_mac_obj *mac_obj = &bp->sp_objs->mac_obj;
11068 unsigned long ramrod_flags = 0;
11069
11070 /* First schedule a cleanup up of old configuration */
11071 rc = bnx2x_del_all_macs(bp, mac_obj, BNX2X_UC_LIST_MAC, false);
11072 if (rc < 0) {
11073 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc);
11074 return rc;
11075 }
11076
11077 netdev_for_each_uc_addr(ha, dev) {
11078 rc = bnx2x_set_mac_one(bp, bnx2x_uc_addr(ha), mac_obj, true,
11079 BNX2X_UC_LIST_MAC, &ramrod_flags);
11080 if (rc == -EEXIST) {
11081 DP(BNX2X_MSG_SP,
11082 "Failed to schedule ADD operations: %d\n", rc);
11083 /* do not treat adding same MAC as error */
11084 rc = 0;
11085
11086 } else if (rc < 0) {
11087
11088 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
11089 rc);
11090 return rc;
11091 }
11092 }
11093
11094 /* Execute the pending commands */
11095 __set_bit(RAMROD_CONT, &ramrod_flags);
11096 return bnx2x_set_mac_one(bp, NULL, mac_obj, false /* don't care */,
11097 BNX2X_UC_LIST_MAC, &ramrod_flags);
11098 }
11099
11100 static int bnx2x_set_mc_list(struct bnx2x *bp)
11101 {
11102 struct net_device *dev = bp->dev;
11103 struct bnx2x_mcast_ramrod_params rparam = {NULL};
11104 int rc = 0;
11105
11106 rparam.mcast_obj = &bp->mcast_obj;
11107
11108 /* first, clear all configured multicast MACs */
11109 rc = bnx2x_config_mcast(bp, &rparam, BNX2X_MCAST_CMD_DEL);
11110 if (rc < 0) {
11111 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc);
11112 return rc;
11113 }
11114
11115 /* then, configure a new MACs list */
11116 if (netdev_mc_count(dev)) {
11117 rc = bnx2x_init_mcast_macs_list(bp, &rparam);
11118 if (rc) {
11119 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
11120 rc);
11121 return rc;
11122 }
11123
11124 /* Now add the new MACs */
11125 rc = bnx2x_config_mcast(bp, &rparam,
11126 BNX2X_MCAST_CMD_ADD);
11127 if (rc < 0)
11128 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
11129 rc);
11130
11131 bnx2x_free_mcast_macs_list(&rparam);
11132 }
11133
11134 return rc;
11135 }
11136
11137
11138 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
11139 void bnx2x_set_rx_mode(struct net_device *dev)
11140 {
11141 struct bnx2x *bp = netdev_priv(dev);
11142 u32 rx_mode = BNX2X_RX_MODE_NORMAL;
11143
11144 if (bp->state != BNX2X_STATE_OPEN) {
11145 DP(NETIF_MSG_IFUP, "state is %x, returning\n", bp->state);
11146 return;
11147 }
11148
11149 DP(NETIF_MSG_IFUP, "dev->flags = %x\n", bp->dev->flags);
11150
11151 if (dev->flags & IFF_PROMISC)
11152 rx_mode = BNX2X_RX_MODE_PROMISC;
11153 else if ((dev->flags & IFF_ALLMULTI) ||
11154 ((netdev_mc_count(dev) > BNX2X_MAX_MULTICAST) &&
11155 CHIP_IS_E1(bp)))
11156 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11157 else {
11158 /* some multicasts */
11159 if (bnx2x_set_mc_list(bp) < 0)
11160 rx_mode = BNX2X_RX_MODE_ALLMULTI;
11161
11162 if (bnx2x_set_uc_list(bp) < 0)
11163 rx_mode = BNX2X_RX_MODE_PROMISC;
11164 }
11165
11166 bp->rx_mode = rx_mode;
11167 #ifdef BCM_CNIC
11168 /* handle ISCSI SD mode */
11169 if (IS_MF_ISCSI_SD(bp))
11170 bp->rx_mode = BNX2X_RX_MODE_NONE;
11171 #endif
11172
11173 /* Schedule the rx_mode command */
11174 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state)) {
11175 set_bit(BNX2X_FILTER_RX_MODE_SCHED, &bp->sp_state);
11176 return;
11177 }
11178
11179 bnx2x_set_storm_rx_mode(bp);
11180 }
11181
11182 /* called with rtnl_lock */
11183 static int bnx2x_mdio_read(struct net_device *netdev, int prtad,
11184 int devad, u16 addr)
11185 {
11186 struct bnx2x *bp = netdev_priv(netdev);
11187 u16 value;
11188 int rc;
11189
11190 DP(NETIF_MSG_LINK, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
11191 prtad, devad, addr);
11192
11193 /* The HW expects different devad if CL22 is used */
11194 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11195
11196 bnx2x_acquire_phy_lock(bp);
11197 rc = bnx2x_phy_read(&bp->link_params, prtad, devad, addr, &value);
11198 bnx2x_release_phy_lock(bp);
11199 DP(NETIF_MSG_LINK, "mdio_read_val 0x%x rc = 0x%x\n", value, rc);
11200
11201 if (!rc)
11202 rc = value;
11203 return rc;
11204 }
11205
11206 /* called with rtnl_lock */
11207 static int bnx2x_mdio_write(struct net_device *netdev, int prtad, int devad,
11208 u16 addr, u16 value)
11209 {
11210 struct bnx2x *bp = netdev_priv(netdev);
11211 int rc;
11212
11213 DP(NETIF_MSG_LINK,
11214 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
11215 prtad, devad, addr, value);
11216
11217 /* The HW expects different devad if CL22 is used */
11218 devad = (devad == MDIO_DEVAD_NONE) ? DEFAULT_PHY_DEV_ADDR : devad;
11219
11220 bnx2x_acquire_phy_lock(bp);
11221 rc = bnx2x_phy_write(&bp->link_params, prtad, devad, addr, value);
11222 bnx2x_release_phy_lock(bp);
11223 return rc;
11224 }
11225
11226 /* called with rtnl_lock */
11227 static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11228 {
11229 struct bnx2x *bp = netdev_priv(dev);
11230 struct mii_ioctl_data *mdio = if_mii(ifr);
11231
11232 DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
11233 mdio->phy_id, mdio->reg_num, mdio->val_in);
11234
11235 if (!netif_running(dev))
11236 return -EAGAIN;
11237
11238 return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
11239 }
11240
11241 #ifdef CONFIG_NET_POLL_CONTROLLER
11242 static void poll_bnx2x(struct net_device *dev)
11243 {
11244 struct bnx2x *bp = netdev_priv(dev);
11245 int i;
11246
11247 for_each_eth_queue(bp, i) {
11248 struct bnx2x_fastpath *fp = &bp->fp[i];
11249 napi_schedule(&bnx2x_fp(bp, fp->index, napi));
11250 }
11251 }
11252 #endif
11253
11254 static int bnx2x_validate_addr(struct net_device *dev)
11255 {
11256 struct bnx2x *bp = netdev_priv(dev);
11257
11258 if (!bnx2x_is_valid_ether_addr(bp, dev->dev_addr)) {
11259 BNX2X_ERR("Non-valid Ethernet address\n");
11260 return -EADDRNOTAVAIL;
11261 }
11262 return 0;
11263 }
11264
11265 static const struct net_device_ops bnx2x_netdev_ops = {
11266 .ndo_open = bnx2x_open,
11267 .ndo_stop = bnx2x_close,
11268 .ndo_start_xmit = bnx2x_start_xmit,
11269 .ndo_select_queue = bnx2x_select_queue,
11270 .ndo_set_rx_mode = bnx2x_set_rx_mode,
11271 .ndo_set_mac_address = bnx2x_change_mac_addr,
11272 .ndo_validate_addr = bnx2x_validate_addr,
11273 .ndo_do_ioctl = bnx2x_ioctl,
11274 .ndo_change_mtu = bnx2x_change_mtu,
11275 .ndo_fix_features = bnx2x_fix_features,
11276 .ndo_set_features = bnx2x_set_features,
11277 .ndo_tx_timeout = bnx2x_tx_timeout,
11278 #ifdef CONFIG_NET_POLL_CONTROLLER
11279 .ndo_poll_controller = poll_bnx2x,
11280 #endif
11281 .ndo_setup_tc = bnx2x_setup_tc,
11282
11283 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
11284 .ndo_fcoe_get_wwn = bnx2x_fcoe_get_wwn,
11285 #endif
11286 };
11287
11288 static int bnx2x_set_coherency_mask(struct bnx2x *bp)
11289 {
11290 struct device *dev = &bp->pdev->dev;
11291
11292 if (dma_set_mask(dev, DMA_BIT_MASK(64)) == 0) {
11293 bp->flags |= USING_DAC_FLAG;
11294 if (dma_set_coherent_mask(dev, DMA_BIT_MASK(64)) != 0) {
11295 dev_err(dev, "dma_set_coherent_mask failed, aborting\n");
11296 return -EIO;
11297 }
11298 } else if (dma_set_mask(dev, DMA_BIT_MASK(32)) != 0) {
11299 dev_err(dev, "System does not support DMA, aborting\n");
11300 return -EIO;
11301 }
11302
11303 return 0;
11304 }
11305
11306 static int __devinit bnx2x_init_dev(struct pci_dev *pdev,
11307 struct net_device *dev,
11308 unsigned long board_type)
11309 {
11310 struct bnx2x *bp;
11311 int rc;
11312 u32 pci_cfg_dword;
11313 bool chip_is_e1x = (board_type == BCM57710 ||
11314 board_type == BCM57711 ||
11315 board_type == BCM57711E);
11316
11317 SET_NETDEV_DEV(dev, &pdev->dev);
11318 bp = netdev_priv(dev);
11319
11320 bp->dev = dev;
11321 bp->pdev = pdev;
11322 bp->flags = 0;
11323
11324 rc = pci_enable_device(pdev);
11325 if (rc) {
11326 dev_err(&bp->pdev->dev,
11327 "Cannot enable PCI device, aborting\n");
11328 goto err_out;
11329 }
11330
11331 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11332 dev_err(&bp->pdev->dev,
11333 "Cannot find PCI device base address, aborting\n");
11334 rc = -ENODEV;
11335 goto err_out_disable;
11336 }
11337
11338 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
11339 dev_err(&bp->pdev->dev, "Cannot find second PCI device"
11340 " base address, aborting\n");
11341 rc = -ENODEV;
11342 goto err_out_disable;
11343 }
11344
11345 if (atomic_read(&pdev->enable_cnt) == 1) {
11346 rc = pci_request_regions(pdev, DRV_MODULE_NAME);
11347 if (rc) {
11348 dev_err(&bp->pdev->dev,
11349 "Cannot obtain PCI resources, aborting\n");
11350 goto err_out_disable;
11351 }
11352
11353 pci_set_master(pdev);
11354 pci_save_state(pdev);
11355 }
11356
11357 bp->pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11358 if (bp->pm_cap == 0) {
11359 dev_err(&bp->pdev->dev,
11360 "Cannot find power management capability, aborting\n");
11361 rc = -EIO;
11362 goto err_out_release;
11363 }
11364
11365 if (!pci_is_pcie(pdev)) {
11366 dev_err(&bp->pdev->dev, "Not PCI Express, aborting\n");
11367 rc = -EIO;
11368 goto err_out_release;
11369 }
11370
11371 rc = bnx2x_set_coherency_mask(bp);
11372 if (rc)
11373 goto err_out_release;
11374
11375 dev->mem_start = pci_resource_start(pdev, 0);
11376 dev->base_addr = dev->mem_start;
11377 dev->mem_end = pci_resource_end(pdev, 0);
11378
11379 dev->irq = pdev->irq;
11380
11381 bp->regview = pci_ioremap_bar(pdev, 0);
11382 if (!bp->regview) {
11383 dev_err(&bp->pdev->dev,
11384 "Cannot map register space, aborting\n");
11385 rc = -ENOMEM;
11386 goto err_out_release;
11387 }
11388
11389 /* In E1/E1H use pci device function given by kernel.
11390 * In E2/E3 read physical function from ME register since these chips
11391 * support Physical Device Assignment where kernel BDF maybe arbitrary
11392 * (depending on hypervisor).
11393 */
11394 if (chip_is_e1x)
11395 bp->pf_num = PCI_FUNC(pdev->devfn);
11396 else {/* chip is E2/3*/
11397 pci_read_config_dword(bp->pdev,
11398 PCICFG_ME_REGISTER, &pci_cfg_dword);
11399 bp->pf_num = (u8)((pci_cfg_dword & ME_REG_ABS_PF_NUM) >>
11400 ME_REG_ABS_PF_NUM_SHIFT);
11401 }
11402 BNX2X_DEV_INFO("me reg PF num: %d\n", bp->pf_num);
11403
11404 bnx2x_set_power_state(bp, PCI_D0);
11405
11406 /* clean indirect addresses */
11407 pci_write_config_dword(bp->pdev, PCICFG_GRC_ADDRESS,
11408 PCICFG_VENDOR_ID_OFFSET);
11409 /*
11410 * Clean the following indirect addresses for all functions since it
11411 * is not used by the driver.
11412 */
11413 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F0, 0);
11414 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F0, 0);
11415 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F0, 0);
11416 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F0, 0);
11417
11418 if (chip_is_e1x) {
11419 REG_WR(bp, PXP2_REG_PGL_ADDR_88_F1, 0);
11420 REG_WR(bp, PXP2_REG_PGL_ADDR_8C_F1, 0);
11421 REG_WR(bp, PXP2_REG_PGL_ADDR_90_F1, 0);
11422 REG_WR(bp, PXP2_REG_PGL_ADDR_94_F1, 0);
11423 }
11424
11425 /*
11426 * Enable internal target-read (in case we are probed after PF FLR).
11427 * Must be done prior to any BAR read access. Only for 57712 and up
11428 */
11429 if (!chip_is_e1x)
11430 REG_WR(bp, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1);
11431
11432 dev->watchdog_timeo = TX_TIMEOUT;
11433
11434 dev->netdev_ops = &bnx2x_netdev_ops;
11435 bnx2x_set_ethtool_ops(dev);
11436
11437 dev->priv_flags |= IFF_UNICAST_FLT;
11438
11439 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11440 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 |
11441 NETIF_F_RXCSUM | NETIF_F_LRO | NETIF_F_GRO |
11442 NETIF_F_RXHASH | NETIF_F_HW_VLAN_TX;
11443
11444 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM |
11445 NETIF_F_TSO | NETIF_F_TSO_ECN | NETIF_F_TSO6 | NETIF_F_HIGHDMA;
11446
11447 dev->features |= dev->hw_features | NETIF_F_HW_VLAN_RX;
11448 if (bp->flags & USING_DAC_FLAG)
11449 dev->features |= NETIF_F_HIGHDMA;
11450
11451 /* Add Loopback capability to the device */
11452 dev->hw_features |= NETIF_F_LOOPBACK;
11453
11454 #ifdef BCM_DCBNL
11455 dev->dcbnl_ops = &bnx2x_dcbnl_ops;
11456 #endif
11457
11458 /* get_port_hwinfo() will set prtad and mmds properly */
11459 bp->mdio.prtad = MDIO_PRTAD_NONE;
11460 bp->mdio.mmds = 0;
11461 bp->mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
11462 bp->mdio.dev = dev;
11463 bp->mdio.mdio_read = bnx2x_mdio_read;
11464 bp->mdio.mdio_write = bnx2x_mdio_write;
11465
11466 return 0;
11467
11468 err_out_release:
11469 if (atomic_read(&pdev->enable_cnt) == 1)
11470 pci_release_regions(pdev);
11471
11472 err_out_disable:
11473 pci_disable_device(pdev);
11474 pci_set_drvdata(pdev, NULL);
11475
11476 err_out:
11477 return rc;
11478 }
11479
11480 static void __devinit bnx2x_get_pcie_width_speed(struct bnx2x *bp,
11481 int *width, int *speed)
11482 {
11483 u32 val = REG_RD(bp, PCICFG_OFFSET + PCICFG_LINK_CONTROL);
11484
11485 *width = (val & PCICFG_LINK_WIDTH) >> PCICFG_LINK_WIDTH_SHIFT;
11486
11487 /* return value of 1=2.5GHz 2=5GHz */
11488 *speed = (val & PCICFG_LINK_SPEED) >> PCICFG_LINK_SPEED_SHIFT;
11489 }
11490
11491 static int bnx2x_check_firmware(struct bnx2x *bp)
11492 {
11493 const struct firmware *firmware = bp->firmware;
11494 struct bnx2x_fw_file_hdr *fw_hdr;
11495 struct bnx2x_fw_file_section *sections;
11496 u32 offset, len, num_ops;
11497 u16 *ops_offsets;
11498 int i;
11499 const u8 *fw_ver;
11500
11501 if (firmware->size < sizeof(struct bnx2x_fw_file_hdr)) {
11502 BNX2X_ERR("Wrong FW size\n");
11503 return -EINVAL;
11504 }
11505
11506 fw_hdr = (struct bnx2x_fw_file_hdr *)firmware->data;
11507 sections = (struct bnx2x_fw_file_section *)fw_hdr;
11508
11509 /* Make sure none of the offsets and sizes make us read beyond
11510 * the end of the firmware data */
11511 for (i = 0; i < sizeof(*fw_hdr) / sizeof(*sections); i++) {
11512 offset = be32_to_cpu(sections[i].offset);
11513 len = be32_to_cpu(sections[i].len);
11514 if (offset + len > firmware->size) {
11515 BNX2X_ERR("Section %d length is out of bounds\n", i);
11516 return -EINVAL;
11517 }
11518 }
11519
11520 /* Likewise for the init_ops offsets */
11521 offset = be32_to_cpu(fw_hdr->init_ops_offsets.offset);
11522 ops_offsets = (u16 *)(firmware->data + offset);
11523 num_ops = be32_to_cpu(fw_hdr->init_ops.len) / sizeof(struct raw_op);
11524
11525 for (i = 0; i < be32_to_cpu(fw_hdr->init_ops_offsets.len) / 2; i++) {
11526 if (be16_to_cpu(ops_offsets[i]) > num_ops) {
11527 BNX2X_ERR("Section offset %d is out of bounds\n", i);
11528 return -EINVAL;
11529 }
11530 }
11531
11532 /* Check FW version */
11533 offset = be32_to_cpu(fw_hdr->fw_version.offset);
11534 fw_ver = firmware->data + offset;
11535 if ((fw_ver[0] != BCM_5710_FW_MAJOR_VERSION) ||
11536 (fw_ver[1] != BCM_5710_FW_MINOR_VERSION) ||
11537 (fw_ver[2] != BCM_5710_FW_REVISION_VERSION) ||
11538 (fw_ver[3] != BCM_5710_FW_ENGINEERING_VERSION)) {
11539 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
11540 fw_ver[0], fw_ver[1], fw_ver[2], fw_ver[3],
11541 BCM_5710_FW_MAJOR_VERSION,
11542 BCM_5710_FW_MINOR_VERSION,
11543 BCM_5710_FW_REVISION_VERSION,
11544 BCM_5710_FW_ENGINEERING_VERSION);
11545 return -EINVAL;
11546 }
11547
11548 return 0;
11549 }
11550
11551 static void be32_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11552 {
11553 const __be32 *source = (const __be32 *)_source;
11554 u32 *target = (u32 *)_target;
11555 u32 i;
11556
11557 for (i = 0; i < n/4; i++)
11558 target[i] = be32_to_cpu(source[i]);
11559 }
11560
11561 /*
11562 Ops array is stored in the following format:
11563 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
11564 */
11565 static void bnx2x_prep_ops(const u8 *_source, u8 *_target, u32 n)
11566 {
11567 const __be32 *source = (const __be32 *)_source;
11568 struct raw_op *target = (struct raw_op *)_target;
11569 u32 i, j, tmp;
11570
11571 for (i = 0, j = 0; i < n/8; i++, j += 2) {
11572 tmp = be32_to_cpu(source[j]);
11573 target[i].op = (tmp >> 24) & 0xff;
11574 target[i].offset = tmp & 0xffffff;
11575 target[i].raw_data = be32_to_cpu(source[j + 1]);
11576 }
11577 }
11578
11579 /* IRO array is stored in the following format:
11580 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
11581 */
11582 static void bnx2x_prep_iro(const u8 *_source, u8 *_target, u32 n)
11583 {
11584 const __be32 *source = (const __be32 *)_source;
11585 struct iro *target = (struct iro *)_target;
11586 u32 i, j, tmp;
11587
11588 for (i = 0, j = 0; i < n/sizeof(struct iro); i++) {
11589 target[i].base = be32_to_cpu(source[j]);
11590 j++;
11591 tmp = be32_to_cpu(source[j]);
11592 target[i].m1 = (tmp >> 16) & 0xffff;
11593 target[i].m2 = tmp & 0xffff;
11594 j++;
11595 tmp = be32_to_cpu(source[j]);
11596 target[i].m3 = (tmp >> 16) & 0xffff;
11597 target[i].size = tmp & 0xffff;
11598 j++;
11599 }
11600 }
11601
11602 static void be16_to_cpu_n(const u8 *_source, u8 *_target, u32 n)
11603 {
11604 const __be16 *source = (const __be16 *)_source;
11605 u16 *target = (u16 *)_target;
11606 u32 i;
11607
11608 for (i = 0; i < n/2; i++)
11609 target[i] = be16_to_cpu(source[i]);
11610 }
11611
11612 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
11613 do { \
11614 u32 len = be32_to_cpu(fw_hdr->arr.len); \
11615 bp->arr = kmalloc(len, GFP_KERNEL); \
11616 if (!bp->arr) \
11617 goto lbl; \
11618 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
11619 (u8 *)bp->arr, len); \
11620 } while (0)
11621
11622 static int bnx2x_init_firmware(struct bnx2x *bp)
11623 {
11624 const char *fw_file_name;
11625 struct bnx2x_fw_file_hdr *fw_hdr;
11626 int rc;
11627
11628 if (bp->firmware)
11629 return 0;
11630
11631 if (CHIP_IS_E1(bp))
11632 fw_file_name = FW_FILE_NAME_E1;
11633 else if (CHIP_IS_E1H(bp))
11634 fw_file_name = FW_FILE_NAME_E1H;
11635 else if (!CHIP_IS_E1x(bp))
11636 fw_file_name = FW_FILE_NAME_E2;
11637 else {
11638 BNX2X_ERR("Unsupported chip revision\n");
11639 return -EINVAL;
11640 }
11641 BNX2X_DEV_INFO("Loading %s\n", fw_file_name);
11642
11643 rc = request_firmware(&bp->firmware, fw_file_name, &bp->pdev->dev);
11644 if (rc) {
11645 BNX2X_ERR("Can't load firmware file %s\n",
11646 fw_file_name);
11647 goto request_firmware_exit;
11648 }
11649
11650 rc = bnx2x_check_firmware(bp);
11651 if (rc) {
11652 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name);
11653 goto request_firmware_exit;
11654 }
11655
11656 fw_hdr = (struct bnx2x_fw_file_hdr *)bp->firmware->data;
11657
11658 /* Initialize the pointers to the init arrays */
11659 /* Blob */
11660 BNX2X_ALLOC_AND_SET(init_data, request_firmware_exit, be32_to_cpu_n);
11661
11662 /* Opcodes */
11663 BNX2X_ALLOC_AND_SET(init_ops, init_ops_alloc_err, bnx2x_prep_ops);
11664
11665 /* Offsets */
11666 BNX2X_ALLOC_AND_SET(init_ops_offsets, init_offsets_alloc_err,
11667 be16_to_cpu_n);
11668
11669 /* STORMs firmware */
11670 INIT_TSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11671 be32_to_cpu(fw_hdr->tsem_int_table_data.offset);
11672 INIT_TSEM_PRAM_DATA(bp) = bp->firmware->data +
11673 be32_to_cpu(fw_hdr->tsem_pram_data.offset);
11674 INIT_USEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11675 be32_to_cpu(fw_hdr->usem_int_table_data.offset);
11676 INIT_USEM_PRAM_DATA(bp) = bp->firmware->data +
11677 be32_to_cpu(fw_hdr->usem_pram_data.offset);
11678 INIT_XSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11679 be32_to_cpu(fw_hdr->xsem_int_table_data.offset);
11680 INIT_XSEM_PRAM_DATA(bp) = bp->firmware->data +
11681 be32_to_cpu(fw_hdr->xsem_pram_data.offset);
11682 INIT_CSEM_INT_TABLE_DATA(bp) = bp->firmware->data +
11683 be32_to_cpu(fw_hdr->csem_int_table_data.offset);
11684 INIT_CSEM_PRAM_DATA(bp) = bp->firmware->data +
11685 be32_to_cpu(fw_hdr->csem_pram_data.offset);
11686 /* IRO */
11687 BNX2X_ALLOC_AND_SET(iro_arr, iro_alloc_err, bnx2x_prep_iro);
11688
11689 return 0;
11690
11691 iro_alloc_err:
11692 kfree(bp->init_ops_offsets);
11693 init_offsets_alloc_err:
11694 kfree(bp->init_ops);
11695 init_ops_alloc_err:
11696 kfree(bp->init_data);
11697 request_firmware_exit:
11698 release_firmware(bp->firmware);
11699 bp->firmware = NULL;
11700
11701 return rc;
11702 }
11703
11704 static void bnx2x_release_firmware(struct bnx2x *bp)
11705 {
11706 kfree(bp->init_ops_offsets);
11707 kfree(bp->init_ops);
11708 kfree(bp->init_data);
11709 release_firmware(bp->firmware);
11710 bp->firmware = NULL;
11711 }
11712
11713
11714 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv = {
11715 .init_hw_cmn_chip = bnx2x_init_hw_common_chip,
11716 .init_hw_cmn = bnx2x_init_hw_common,
11717 .init_hw_port = bnx2x_init_hw_port,
11718 .init_hw_func = bnx2x_init_hw_func,
11719
11720 .reset_hw_cmn = bnx2x_reset_common,
11721 .reset_hw_port = bnx2x_reset_port,
11722 .reset_hw_func = bnx2x_reset_func,
11723
11724 .gunzip_init = bnx2x_gunzip_init,
11725 .gunzip_end = bnx2x_gunzip_end,
11726
11727 .init_fw = bnx2x_init_firmware,
11728 .release_fw = bnx2x_release_firmware,
11729 };
11730
11731 void bnx2x__init_func_obj(struct bnx2x *bp)
11732 {
11733 /* Prepare DMAE related driver resources */
11734 bnx2x_setup_dmae(bp);
11735
11736 bnx2x_init_func_obj(bp, &bp->func_obj,
11737 bnx2x_sp(bp, func_rdata),
11738 bnx2x_sp_mapping(bp, func_rdata),
11739 bnx2x_sp(bp, func_afex_rdata),
11740 bnx2x_sp_mapping(bp, func_afex_rdata),
11741 &bnx2x_func_sp_drv);
11742 }
11743
11744 /* must be called after sriov-enable */
11745 static int bnx2x_set_qm_cid_count(struct bnx2x *bp)
11746 {
11747 int cid_count = BNX2X_L2_MAX_CID(bp);
11748
11749 #ifdef BCM_CNIC
11750 cid_count += CNIC_CID_MAX;
11751 #endif
11752 return roundup(cid_count, QM_CID_ROUND);
11753 }
11754
11755 /**
11756 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
11757 *
11758 * @dev: pci device
11759 *
11760 */
11761 static int bnx2x_get_num_non_def_sbs(struct pci_dev *pdev)
11762 {
11763 int pos;
11764 u16 control;
11765
11766 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX);
11767
11768 /*
11769 * If MSI-X is not supported - return number of SBs needed to support
11770 * one fast path queue: one FP queue + SB for CNIC
11771 */
11772 if (!pos)
11773 return 1 + CNIC_PRESENT;
11774
11775 /*
11776 * The value in the PCI configuration space is the index of the last
11777 * entry, namely one less than the actual size of the table, which is
11778 * exactly what we want to return from this function: number of all SBs
11779 * without the default SB.
11780 */
11781 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control);
11782 return control & PCI_MSIX_FLAGS_QSIZE;
11783 }
11784
11785 static int __devinit bnx2x_init_one(struct pci_dev *pdev,
11786 const struct pci_device_id *ent)
11787 {
11788 struct net_device *dev = NULL;
11789 struct bnx2x *bp;
11790 int pcie_width, pcie_speed;
11791 int rc, max_non_def_sbs;
11792 int rx_count, tx_count, rss_count, doorbell_size;
11793 /*
11794 * An estimated maximum supported CoS number according to the chip
11795 * version.
11796 * We will try to roughly estimate the maximum number of CoSes this chip
11797 * may support in order to minimize the memory allocated for Tx
11798 * netdev_queue's. This number will be accurately calculated during the
11799 * initialization of bp->max_cos based on the chip versions AND chip
11800 * revision in the bnx2x_init_bp().
11801 */
11802 u8 max_cos_est = 0;
11803
11804 switch (ent->driver_data) {
11805 case BCM57710:
11806 case BCM57711:
11807 case BCM57711E:
11808 max_cos_est = BNX2X_MULTI_TX_COS_E1X;
11809 break;
11810
11811 case BCM57712:
11812 case BCM57712_MF:
11813 max_cos_est = BNX2X_MULTI_TX_COS_E2_E3A0;
11814 break;
11815
11816 case BCM57800:
11817 case BCM57800_MF:
11818 case BCM57810:
11819 case BCM57810_MF:
11820 case BCM57840_O:
11821 case BCM57840_4_10:
11822 case BCM57840_2_20:
11823 case BCM57840_MFO:
11824 case BCM57840_MF:
11825 case BCM57811:
11826 case BCM57811_MF:
11827 max_cos_est = BNX2X_MULTI_TX_COS_E3B0;
11828 break;
11829
11830 default:
11831 pr_err("Unknown board_type (%ld), aborting\n",
11832 ent->driver_data);
11833 return -ENODEV;
11834 }
11835
11836 max_non_def_sbs = bnx2x_get_num_non_def_sbs(pdev);
11837
11838 WARN_ON(!max_non_def_sbs);
11839
11840 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11841 rss_count = max_non_def_sbs - CNIC_PRESENT;
11842
11843 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11844 rx_count = rss_count + FCOE_PRESENT;
11845
11846 /*
11847 * Maximum number of netdev Tx queues:
11848 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11849 */
11850 tx_count = rss_count * max_cos_est + FCOE_PRESENT;
11851
11852 /* dev zeroed in init_etherdev */
11853 dev = alloc_etherdev_mqs(sizeof(*bp), tx_count, rx_count);
11854 if (!dev)
11855 return -ENOMEM;
11856
11857 bp = netdev_priv(dev);
11858
11859 bp->igu_sb_cnt = max_non_def_sbs;
11860 bp->msg_enable = debug;
11861 pci_set_drvdata(pdev, dev);
11862
11863 rc = bnx2x_init_dev(pdev, dev, ent->driver_data);
11864 if (rc < 0) {
11865 free_netdev(dev);
11866 return rc;
11867 }
11868
11869 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs);
11870
11871 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
11872 tx_count, rx_count);
11873
11874 rc = bnx2x_init_bp(bp);
11875 if (rc)
11876 goto init_one_exit;
11877
11878 /*
11879 * Map doorbels here as we need the real value of bp->max_cos which
11880 * is initialized in bnx2x_init_bp().
11881 */
11882 doorbell_size = BNX2X_L2_MAX_CID(bp) * (1 << BNX2X_DB_SHIFT);
11883 if (doorbell_size > pci_resource_len(pdev, 2)) {
11884 dev_err(&bp->pdev->dev,
11885 "Cannot map doorbells, bar size too small, aborting\n");
11886 rc = -ENOMEM;
11887 goto init_one_exit;
11888 }
11889 bp->doorbells = ioremap_nocache(pci_resource_start(pdev, 2),
11890 doorbell_size);
11891 if (!bp->doorbells) {
11892 dev_err(&bp->pdev->dev,
11893 "Cannot map doorbell space, aborting\n");
11894 rc = -ENOMEM;
11895 goto init_one_exit;
11896 }
11897
11898 /* calc qm_cid_count */
11899 bp->qm_cid_count = bnx2x_set_qm_cid_count(bp);
11900
11901 #ifdef BCM_CNIC
11902 /* disable FCOE L2 queue for E1x */
11903 if (CHIP_IS_E1x(bp))
11904 bp->flags |= NO_FCOE_FLAG;
11905
11906 #endif
11907
11908
11909 /* Set bp->num_queues for MSI-X mode*/
11910 bnx2x_set_num_queues(bp);
11911
11912 /* Configure interrupt mode: try to enable MSI-X/MSI if
11913 * needed.
11914 */
11915 bnx2x_set_int_mode(bp);
11916
11917 rc = register_netdev(dev);
11918 if (rc) {
11919 dev_err(&pdev->dev, "Cannot register net device\n");
11920 goto init_one_exit;
11921 }
11922
11923 #ifdef BCM_CNIC
11924 if (!NO_FCOE(bp)) {
11925 /* Add storage MAC address */
11926 rtnl_lock();
11927 dev_addr_add(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11928 rtnl_unlock();
11929 }
11930 #endif
11931
11932 bnx2x_get_pcie_width_speed(bp, &pcie_width, &pcie_speed);
11933
11934 BNX2X_DEV_INFO(
11935 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11936 board_info[ent->driver_data].name,
11937 (CHIP_REV(bp) >> 12) + 'A', (CHIP_METAL(bp) >> 4),
11938 pcie_width,
11939 ((!CHIP_IS_E2(bp) && pcie_speed == 2) ||
11940 (CHIP_IS_E2(bp) && pcie_speed == 1)) ?
11941 "5GHz (Gen2)" : "2.5GHz",
11942 dev->base_addr, bp->pdev->irq, dev->dev_addr);
11943
11944 return 0;
11945
11946 init_one_exit:
11947 if (bp->regview)
11948 iounmap(bp->regview);
11949
11950 if (bp->doorbells)
11951 iounmap(bp->doorbells);
11952
11953 free_netdev(dev);
11954
11955 if (atomic_read(&pdev->enable_cnt) == 1)
11956 pci_release_regions(pdev);
11957
11958 pci_disable_device(pdev);
11959 pci_set_drvdata(pdev, NULL);
11960
11961 return rc;
11962 }
11963
11964 static void __devexit bnx2x_remove_one(struct pci_dev *pdev)
11965 {
11966 struct net_device *dev = pci_get_drvdata(pdev);
11967 struct bnx2x *bp;
11968
11969 if (!dev) {
11970 dev_err(&pdev->dev, "BAD net device from bnx2x_init_one\n");
11971 return;
11972 }
11973 bp = netdev_priv(dev);
11974
11975 #ifdef BCM_CNIC
11976 /* Delete storage MAC address */
11977 if (!NO_FCOE(bp)) {
11978 rtnl_lock();
11979 dev_addr_del(bp->dev, bp->fip_mac, NETDEV_HW_ADDR_T_SAN);
11980 rtnl_unlock();
11981 }
11982 #endif
11983
11984 #ifdef BCM_DCBNL
11985 /* Delete app tlvs from dcbnl */
11986 bnx2x_dcbnl_update_applist(bp, true);
11987 #endif
11988
11989 unregister_netdev(dev);
11990
11991 /* Power on: we can't let PCI layer write to us while we are in D3 */
11992 bnx2x_set_power_state(bp, PCI_D0);
11993
11994 /* Disable MSI/MSI-X */
11995 bnx2x_disable_msi(bp);
11996
11997 /* Power off */
11998 bnx2x_set_power_state(bp, PCI_D3hot);
11999
12000 /* Make sure RESET task is not scheduled before continuing */
12001 cancel_delayed_work_sync(&bp->sp_rtnl_task);
12002
12003 if (bp->regview)
12004 iounmap(bp->regview);
12005
12006 if (bp->doorbells)
12007 iounmap(bp->doorbells);
12008
12009 bnx2x_release_firmware(bp);
12010
12011 bnx2x_free_mem_bp(bp);
12012
12013 free_netdev(dev);
12014
12015 if (atomic_read(&pdev->enable_cnt) == 1)
12016 pci_release_regions(pdev);
12017
12018 pci_disable_device(pdev);
12019 pci_set_drvdata(pdev, NULL);
12020 }
12021
12022 static int bnx2x_eeh_nic_unload(struct bnx2x *bp)
12023 {
12024 int i;
12025
12026 bp->state = BNX2X_STATE_ERROR;
12027
12028 bp->rx_mode = BNX2X_RX_MODE_NONE;
12029
12030 #ifdef BCM_CNIC
12031 bnx2x_cnic_notify(bp, CNIC_CTL_STOP_CMD);
12032 #endif
12033 /* Stop Tx */
12034 bnx2x_tx_disable(bp);
12035
12036 bnx2x_netif_stop(bp, 0);
12037 /* Delete all NAPI objects */
12038 bnx2x_del_all_napi(bp);
12039
12040 del_timer_sync(&bp->timer);
12041
12042 bnx2x_stats_handle(bp, STATS_EVENT_STOP);
12043
12044 /* Release IRQs */
12045 bnx2x_free_irq(bp);
12046
12047 /* Free SKBs, SGEs, TPA pool and driver internals */
12048 bnx2x_free_skbs(bp);
12049
12050 for_each_rx_queue(bp, i)
12051 bnx2x_free_rx_sge_range(bp, bp->fp + i, NUM_RX_SGE);
12052
12053 bnx2x_free_mem(bp);
12054
12055 bp->state = BNX2X_STATE_CLOSED;
12056
12057 netif_carrier_off(bp->dev);
12058
12059 return 0;
12060 }
12061
12062 static void bnx2x_eeh_recover(struct bnx2x *bp)
12063 {
12064 u32 val;
12065
12066 mutex_init(&bp->port.phy_mutex);
12067
12068
12069 val = SHMEM_RD(bp, validity_map[BP_PORT(bp)]);
12070 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12071 != (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB))
12072 BNX2X_ERR("BAD MCP validity signature\n");
12073 }
12074
12075 /**
12076 * bnx2x_io_error_detected - called when PCI error is detected
12077 * @pdev: Pointer to PCI device
12078 * @state: The current pci connection state
12079 *
12080 * This function is called after a PCI bus error affecting
12081 * this device has been detected.
12082 */
12083 static pci_ers_result_t bnx2x_io_error_detected(struct pci_dev *pdev,
12084 pci_channel_state_t state)
12085 {
12086 struct net_device *dev = pci_get_drvdata(pdev);
12087 struct bnx2x *bp = netdev_priv(dev);
12088
12089 rtnl_lock();
12090
12091 netif_device_detach(dev);
12092
12093 if (state == pci_channel_io_perm_failure) {
12094 rtnl_unlock();
12095 return PCI_ERS_RESULT_DISCONNECT;
12096 }
12097
12098 if (netif_running(dev))
12099 bnx2x_eeh_nic_unload(bp);
12100
12101 pci_disable_device(pdev);
12102
12103 rtnl_unlock();
12104
12105 /* Request a slot reset */
12106 return PCI_ERS_RESULT_NEED_RESET;
12107 }
12108
12109 /**
12110 * bnx2x_io_slot_reset - called after the PCI bus has been reset
12111 * @pdev: Pointer to PCI device
12112 *
12113 * Restart the card from scratch, as if from a cold-boot.
12114 */
12115 static pci_ers_result_t bnx2x_io_slot_reset(struct pci_dev *pdev)
12116 {
12117 struct net_device *dev = pci_get_drvdata(pdev);
12118 struct bnx2x *bp = netdev_priv(dev);
12119
12120 rtnl_lock();
12121
12122 if (pci_enable_device(pdev)) {
12123 dev_err(&pdev->dev,
12124 "Cannot re-enable PCI device after reset\n");
12125 rtnl_unlock();
12126 return PCI_ERS_RESULT_DISCONNECT;
12127 }
12128
12129 pci_set_master(pdev);
12130 pci_restore_state(pdev);
12131
12132 if (netif_running(dev))
12133 bnx2x_set_power_state(bp, PCI_D0);
12134
12135 rtnl_unlock();
12136
12137 return PCI_ERS_RESULT_RECOVERED;
12138 }
12139
12140 /**
12141 * bnx2x_io_resume - called when traffic can start flowing again
12142 * @pdev: Pointer to PCI device
12143 *
12144 * This callback is called when the error recovery driver tells us that
12145 * its OK to resume normal operation.
12146 */
12147 static void bnx2x_io_resume(struct pci_dev *pdev)
12148 {
12149 struct net_device *dev = pci_get_drvdata(pdev);
12150 struct bnx2x *bp = netdev_priv(dev);
12151
12152 if (bp->recovery_state != BNX2X_RECOVERY_DONE) {
12153 netdev_err(bp->dev, "Handling parity error recovery. Try again later\n");
12154 return;
12155 }
12156
12157 rtnl_lock();
12158
12159 bnx2x_eeh_recover(bp);
12160
12161 if (netif_running(dev))
12162 bnx2x_nic_load(bp, LOAD_NORMAL);
12163
12164 netif_device_attach(dev);
12165
12166 rtnl_unlock();
12167 }
12168
12169 static struct pci_error_handlers bnx2x_err_handler = {
12170 .error_detected = bnx2x_io_error_detected,
12171 .slot_reset = bnx2x_io_slot_reset,
12172 .resume = bnx2x_io_resume,
12173 };
12174
12175 static struct pci_driver bnx2x_pci_driver = {
12176 .name = DRV_MODULE_NAME,
12177 .id_table = bnx2x_pci_tbl,
12178 .probe = bnx2x_init_one,
12179 .remove = __devexit_p(bnx2x_remove_one),
12180 .suspend = bnx2x_suspend,
12181 .resume = bnx2x_resume,
12182 .err_handler = &bnx2x_err_handler,
12183 };
12184
12185 static int __init bnx2x_init(void)
12186 {
12187 int ret;
12188
12189 pr_info("%s", version);
12190
12191 bnx2x_wq = create_singlethread_workqueue("bnx2x");
12192 if (bnx2x_wq == NULL) {
12193 pr_err("Cannot create workqueue\n");
12194 return -ENOMEM;
12195 }
12196
12197 ret = pci_register_driver(&bnx2x_pci_driver);
12198 if (ret) {
12199 pr_err("Cannot register driver\n");
12200 destroy_workqueue(bnx2x_wq);
12201 }
12202 return ret;
12203 }
12204
12205 static void __exit bnx2x_cleanup(void)
12206 {
12207 struct list_head *pos, *q;
12208 pci_unregister_driver(&bnx2x_pci_driver);
12209
12210 destroy_workqueue(bnx2x_wq);
12211
12212 /* Free globablly allocated resources */
12213 list_for_each_safe(pos, q, &bnx2x_prev_list) {
12214 struct bnx2x_prev_path_list *tmp =
12215 list_entry(pos, struct bnx2x_prev_path_list, list);
12216 list_del(pos);
12217 kfree(tmp);
12218 }
12219 }
12220
12221 void bnx2x_notify_link_changed(struct bnx2x *bp)
12222 {
12223 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_12 + BP_FUNC(bp)*sizeof(u32), 1);
12224 }
12225
12226 module_init(bnx2x_init);
12227 module_exit(bnx2x_cleanup);
12228
12229 #ifdef BCM_CNIC
12230 /**
12231 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
12232 *
12233 * @bp: driver handle
12234 * @set: set or clear the CAM entry
12235 *
12236 * This function will wait until the ramdord completion returns.
12237 * Return 0 if success, -ENODEV if ramrod doesn't return.
12238 */
12239 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x *bp)
12240 {
12241 unsigned long ramrod_flags = 0;
12242
12243 __set_bit(RAMROD_COMP_WAIT, &ramrod_flags);
12244 return bnx2x_set_mac_one(bp, bp->cnic_eth_dev.iscsi_mac,
12245 &bp->iscsi_l2_mac_obj, true,
12246 BNX2X_ISCSI_ETH_MAC, &ramrod_flags);
12247 }
12248
12249 /* count denotes the number of new completions we have seen */
12250 static void bnx2x_cnic_sp_post(struct bnx2x *bp, int count)
12251 {
12252 struct eth_spe *spe;
12253 int cxt_index, cxt_offset;
12254
12255 #ifdef BNX2X_STOP_ON_ERROR
12256 if (unlikely(bp->panic))
12257 return;
12258 #endif
12259
12260 spin_lock_bh(&bp->spq_lock);
12261 BUG_ON(bp->cnic_spq_pending < count);
12262 bp->cnic_spq_pending -= count;
12263
12264
12265 for (; bp->cnic_kwq_pending; bp->cnic_kwq_pending--) {
12266 u16 type = (le16_to_cpu(bp->cnic_kwq_cons->hdr.type)
12267 & SPE_HDR_CONN_TYPE) >>
12268 SPE_HDR_CONN_TYPE_SHIFT;
12269 u8 cmd = (le32_to_cpu(bp->cnic_kwq_cons->hdr.conn_and_cmd_data)
12270 >> SPE_HDR_CMD_ID_SHIFT) & 0xff;
12271
12272 /* Set validation for iSCSI L2 client before sending SETUP
12273 * ramrod
12274 */
12275 if (type == ETH_CONNECTION_TYPE) {
12276 if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP) {
12277 cxt_index = BNX2X_ISCSI_ETH_CID(bp) /
12278 ILT_PAGE_CIDS;
12279 cxt_offset = BNX2X_ISCSI_ETH_CID(bp) -
12280 (cxt_index * ILT_PAGE_CIDS);
12281 bnx2x_set_ctx_validation(bp,
12282 &bp->context[cxt_index].
12283 vcxt[cxt_offset].eth,
12284 BNX2X_ISCSI_ETH_CID(bp));
12285 }
12286 }
12287
12288 /*
12289 * There may be not more than 8 L2, not more than 8 L5 SPEs
12290 * and in the air. We also check that number of outstanding
12291 * COMMON ramrods is not more than the EQ and SPQ can
12292 * accommodate.
12293 */
12294 if (type == ETH_CONNECTION_TYPE) {
12295 if (!atomic_read(&bp->cq_spq_left))
12296 break;
12297 else
12298 atomic_dec(&bp->cq_spq_left);
12299 } else if (type == NONE_CONNECTION_TYPE) {
12300 if (!atomic_read(&bp->eq_spq_left))
12301 break;
12302 else
12303 atomic_dec(&bp->eq_spq_left);
12304 } else if ((type == ISCSI_CONNECTION_TYPE) ||
12305 (type == FCOE_CONNECTION_TYPE)) {
12306 if (bp->cnic_spq_pending >=
12307 bp->cnic_eth_dev.max_kwqe_pending)
12308 break;
12309 else
12310 bp->cnic_spq_pending++;
12311 } else {
12312 BNX2X_ERR("Unknown SPE type: %d\n", type);
12313 bnx2x_panic();
12314 break;
12315 }
12316
12317 spe = bnx2x_sp_get_next(bp);
12318 *spe = *bp->cnic_kwq_cons;
12319
12320 DP(BNX2X_MSG_SP, "pending on SPQ %d, on KWQ %d count %d\n",
12321 bp->cnic_spq_pending, bp->cnic_kwq_pending, count);
12322
12323 if (bp->cnic_kwq_cons == bp->cnic_kwq_last)
12324 bp->cnic_kwq_cons = bp->cnic_kwq;
12325 else
12326 bp->cnic_kwq_cons++;
12327 }
12328 bnx2x_sp_prod_update(bp);
12329 spin_unlock_bh(&bp->spq_lock);
12330 }
12331
12332 static int bnx2x_cnic_sp_queue(struct net_device *dev,
12333 struct kwqe_16 *kwqes[], u32 count)
12334 {
12335 struct bnx2x *bp = netdev_priv(dev);
12336 int i;
12337
12338 #ifdef BNX2X_STOP_ON_ERROR
12339 if (unlikely(bp->panic)) {
12340 BNX2X_ERR("Can't post to SP queue while panic\n");
12341 return -EIO;
12342 }
12343 #endif
12344
12345 if ((bp->recovery_state != BNX2X_RECOVERY_DONE) &&
12346 (bp->recovery_state != BNX2X_RECOVERY_NIC_LOADING)) {
12347 BNX2X_ERR("Handling parity error recovery. Try again later\n");
12348 return -EAGAIN;
12349 }
12350
12351 spin_lock_bh(&bp->spq_lock);
12352
12353 for (i = 0; i < count; i++) {
12354 struct eth_spe *spe = (struct eth_spe *)kwqes[i];
12355
12356 if (bp->cnic_kwq_pending == MAX_SP_DESC_CNT)
12357 break;
12358
12359 *bp->cnic_kwq_prod = *spe;
12360
12361 bp->cnic_kwq_pending++;
12362
12363 DP(BNX2X_MSG_SP, "L5 SPQE %x %x %x:%x pos %d\n",
12364 spe->hdr.conn_and_cmd_data, spe->hdr.type,
12365 spe->data.update_data_addr.hi,
12366 spe->data.update_data_addr.lo,
12367 bp->cnic_kwq_pending);
12368
12369 if (bp->cnic_kwq_prod == bp->cnic_kwq_last)
12370 bp->cnic_kwq_prod = bp->cnic_kwq;
12371 else
12372 bp->cnic_kwq_prod++;
12373 }
12374
12375 spin_unlock_bh(&bp->spq_lock);
12376
12377 if (bp->cnic_spq_pending < bp->cnic_eth_dev.max_kwqe_pending)
12378 bnx2x_cnic_sp_post(bp, 0);
12379
12380 return i;
12381 }
12382
12383 static int bnx2x_cnic_ctl_send(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12384 {
12385 struct cnic_ops *c_ops;
12386 int rc = 0;
12387
12388 mutex_lock(&bp->cnic_mutex);
12389 c_ops = rcu_dereference_protected(bp->cnic_ops,
12390 lockdep_is_held(&bp->cnic_mutex));
12391 if (c_ops)
12392 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12393 mutex_unlock(&bp->cnic_mutex);
12394
12395 return rc;
12396 }
12397
12398 static int bnx2x_cnic_ctl_send_bh(struct bnx2x *bp, struct cnic_ctl_info *ctl)
12399 {
12400 struct cnic_ops *c_ops;
12401 int rc = 0;
12402
12403 rcu_read_lock();
12404 c_ops = rcu_dereference(bp->cnic_ops);
12405 if (c_ops)
12406 rc = c_ops->cnic_ctl(bp->cnic_data, ctl);
12407 rcu_read_unlock();
12408
12409 return rc;
12410 }
12411
12412 /*
12413 * for commands that have no data
12414 */
12415 int bnx2x_cnic_notify(struct bnx2x *bp, int cmd)
12416 {
12417 struct cnic_ctl_info ctl = {0};
12418
12419 ctl.cmd = cmd;
12420
12421 return bnx2x_cnic_ctl_send(bp, &ctl);
12422 }
12423
12424 static void bnx2x_cnic_cfc_comp(struct bnx2x *bp, int cid, u8 err)
12425 {
12426 struct cnic_ctl_info ctl = {0};
12427
12428 /* first we tell CNIC and only then we count this as a completion */
12429 ctl.cmd = CNIC_CTL_COMPLETION_CMD;
12430 ctl.data.comp.cid = cid;
12431 ctl.data.comp.error = err;
12432
12433 bnx2x_cnic_ctl_send_bh(bp, &ctl);
12434 bnx2x_cnic_sp_post(bp, 0);
12435 }
12436
12437
12438 /* Called with netif_addr_lock_bh() taken.
12439 * Sets an rx_mode config for an iSCSI ETH client.
12440 * Doesn't block.
12441 * Completion should be checked outside.
12442 */
12443 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x *bp, bool start)
12444 {
12445 unsigned long accept_flags = 0, ramrod_flags = 0;
12446 u8 cl_id = bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12447 int sched_state = BNX2X_FILTER_ISCSI_ETH_STOP_SCHED;
12448
12449 if (start) {
12450 /* Start accepting on iSCSI L2 ring. Accept all multicasts
12451 * because it's the only way for UIO Queue to accept
12452 * multicasts (in non-promiscuous mode only one Queue per
12453 * function will receive multicast packets (leading in our
12454 * case).
12455 */
12456 __set_bit(BNX2X_ACCEPT_UNICAST, &accept_flags);
12457 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST, &accept_flags);
12458 __set_bit(BNX2X_ACCEPT_BROADCAST, &accept_flags);
12459 __set_bit(BNX2X_ACCEPT_ANY_VLAN, &accept_flags);
12460
12461 /* Clear STOP_PENDING bit if START is requested */
12462 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &bp->sp_state);
12463
12464 sched_state = BNX2X_FILTER_ISCSI_ETH_START_SCHED;
12465 } else
12466 /* Clear START_PENDING bit if STOP is requested */
12467 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &bp->sp_state);
12468
12469 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING, &bp->sp_state))
12470 set_bit(sched_state, &bp->sp_state);
12471 else {
12472 __set_bit(RAMROD_RX, &ramrod_flags);
12473 bnx2x_set_q_rx_mode(bp, cl_id, 0, accept_flags, 0,
12474 ramrod_flags);
12475 }
12476 }
12477
12478
12479 static int bnx2x_drv_ctl(struct net_device *dev, struct drv_ctl_info *ctl)
12480 {
12481 struct bnx2x *bp = netdev_priv(dev);
12482 int rc = 0;
12483
12484 switch (ctl->cmd) {
12485 case DRV_CTL_CTXTBL_WR_CMD: {
12486 u32 index = ctl->data.io.offset;
12487 dma_addr_t addr = ctl->data.io.dma_addr;
12488
12489 bnx2x_ilt_wr(bp, index, addr);
12490 break;
12491 }
12492
12493 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD: {
12494 int count = ctl->data.credit.credit_count;
12495
12496 bnx2x_cnic_sp_post(bp, count);
12497 break;
12498 }
12499
12500 /* rtnl_lock is held. */
12501 case DRV_CTL_START_L2_CMD: {
12502 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12503 unsigned long sp_bits = 0;
12504
12505 /* Configure the iSCSI classification object */
12506 bnx2x_init_mac_obj(bp, &bp->iscsi_l2_mac_obj,
12507 cp->iscsi_l2_client_id,
12508 cp->iscsi_l2_cid, BP_FUNC(bp),
12509 bnx2x_sp(bp, mac_rdata),
12510 bnx2x_sp_mapping(bp, mac_rdata),
12511 BNX2X_FILTER_MAC_PENDING,
12512 &bp->sp_state, BNX2X_OBJ_TYPE_RX,
12513 &bp->macs_pool);
12514
12515 /* Set iSCSI MAC address */
12516 rc = bnx2x_set_iscsi_eth_mac_addr(bp);
12517 if (rc)
12518 break;
12519
12520 mmiowb();
12521 barrier();
12522
12523 /* Start accepting on iSCSI L2 ring */
12524
12525 netif_addr_lock_bh(dev);
12526 bnx2x_set_iscsi_eth_rx_mode(bp, true);
12527 netif_addr_unlock_bh(dev);
12528
12529 /* bits to wait on */
12530 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12531 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED, &sp_bits);
12532
12533 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12534 BNX2X_ERR("rx_mode completion timed out!\n");
12535
12536 break;
12537 }
12538
12539 /* rtnl_lock is held. */
12540 case DRV_CTL_STOP_L2_CMD: {
12541 unsigned long sp_bits = 0;
12542
12543 /* Stop accepting on iSCSI L2 ring */
12544 netif_addr_lock_bh(dev);
12545 bnx2x_set_iscsi_eth_rx_mode(bp, false);
12546 netif_addr_unlock_bh(dev);
12547
12548 /* bits to wait on */
12549 __set_bit(BNX2X_FILTER_RX_MODE_PENDING, &sp_bits);
12550 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED, &sp_bits);
12551
12552 if (!bnx2x_wait_sp_comp(bp, sp_bits))
12553 BNX2X_ERR("rx_mode completion timed out!\n");
12554
12555 mmiowb();
12556 barrier();
12557
12558 /* Unset iSCSI L2 MAC */
12559 rc = bnx2x_del_all_macs(bp, &bp->iscsi_l2_mac_obj,
12560 BNX2X_ISCSI_ETH_MAC, true);
12561 break;
12562 }
12563 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD: {
12564 int count = ctl->data.credit.credit_count;
12565
12566 smp_mb__before_atomic_inc();
12567 atomic_add(count, &bp->cq_spq_left);
12568 smp_mb__after_atomic_inc();
12569 break;
12570 }
12571 case DRV_CTL_ULP_REGISTER_CMD: {
12572 int ulp_type = ctl->data.register_data.ulp_type;
12573
12574 if (CHIP_IS_E3(bp)) {
12575 int idx = BP_FW_MB_IDX(bp);
12576 u32 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12577 int path = BP_PATH(bp);
12578 int port = BP_PORT(bp);
12579 int i;
12580 u32 scratch_offset;
12581 u32 *host_addr;
12582
12583 /* first write capability to shmem2 */
12584 if (ulp_type == CNIC_ULP_ISCSI)
12585 cap |= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12586 else if (ulp_type == CNIC_ULP_FCOE)
12587 cap |= DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12588 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12589
12590 if ((ulp_type != CNIC_ULP_FCOE) ||
12591 (!SHMEM2_HAS(bp, ncsi_oem_data_addr)) ||
12592 (!(bp->flags & BC_SUPPORTS_FCOE_FEATURES)))
12593 break;
12594
12595 /* if reached here - should write fcoe capabilities */
12596 scratch_offset = SHMEM2_RD(bp, ncsi_oem_data_addr);
12597 if (!scratch_offset)
12598 break;
12599 scratch_offset += offsetof(struct glob_ncsi_oem_data,
12600 fcoe_features[path][port]);
12601 host_addr = (u32 *) &(ctl->data.register_data.
12602 fcoe_features);
12603 for (i = 0; i < sizeof(struct fcoe_capabilities);
12604 i += 4)
12605 REG_WR(bp, scratch_offset + i,
12606 *(host_addr + i/4));
12607 }
12608 break;
12609 }
12610
12611 case DRV_CTL_ULP_UNREGISTER_CMD: {
12612 int ulp_type = ctl->data.ulp_type;
12613
12614 if (CHIP_IS_E3(bp)) {
12615 int idx = BP_FW_MB_IDX(bp);
12616 u32 cap;
12617
12618 cap = SHMEM2_RD(bp, drv_capabilities_flag[idx]);
12619 if (ulp_type == CNIC_ULP_ISCSI)
12620 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI;
12621 else if (ulp_type == CNIC_ULP_FCOE)
12622 cap &= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE;
12623 SHMEM2_WR(bp, drv_capabilities_flag[idx], cap);
12624 }
12625 break;
12626 }
12627
12628 default:
12629 BNX2X_ERR("unknown command %x\n", ctl->cmd);
12630 rc = -EINVAL;
12631 }
12632
12633 return rc;
12634 }
12635
12636 void bnx2x_setup_cnic_irq_info(struct bnx2x *bp)
12637 {
12638 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12639
12640 if (bp->flags & USING_MSIX_FLAG) {
12641 cp->drv_state |= CNIC_DRV_STATE_USING_MSIX;
12642 cp->irq_arr[0].irq_flags |= CNIC_IRQ_FL_MSIX;
12643 cp->irq_arr[0].vector = bp->msix_table[1].vector;
12644 } else {
12645 cp->drv_state &= ~CNIC_DRV_STATE_USING_MSIX;
12646 cp->irq_arr[0].irq_flags &= ~CNIC_IRQ_FL_MSIX;
12647 }
12648 if (!CHIP_IS_E1x(bp))
12649 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e2_sb;
12650 else
12651 cp->irq_arr[0].status_blk = (void *)bp->cnic_sb.e1x_sb;
12652
12653 cp->irq_arr[0].status_blk_num = bnx2x_cnic_fw_sb_id(bp);
12654 cp->irq_arr[0].status_blk_num2 = bnx2x_cnic_igu_sb_id(bp);
12655 cp->irq_arr[1].status_blk = bp->def_status_blk;
12656 cp->irq_arr[1].status_blk_num = DEF_SB_ID;
12657 cp->irq_arr[1].status_blk_num2 = DEF_SB_IGU_ID;
12658
12659 cp->num_irq = 2;
12660 }
12661
12662 void bnx2x_setup_cnic_info(struct bnx2x *bp)
12663 {
12664 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12665
12666
12667 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12668 bnx2x_cid_ilt_lines(bp);
12669 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12670 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12671 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12672
12673 if (NO_ISCSI_OOO(bp))
12674 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12675 }
12676
12677 static int bnx2x_register_cnic(struct net_device *dev, struct cnic_ops *ops,
12678 void *data)
12679 {
12680 struct bnx2x *bp = netdev_priv(dev);
12681 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12682
12683 if (ops == NULL) {
12684 BNX2X_ERR("NULL ops received\n");
12685 return -EINVAL;
12686 }
12687
12688 bp->cnic_kwq = kzalloc(PAGE_SIZE, GFP_KERNEL);
12689 if (!bp->cnic_kwq)
12690 return -ENOMEM;
12691
12692 bp->cnic_kwq_cons = bp->cnic_kwq;
12693 bp->cnic_kwq_prod = bp->cnic_kwq;
12694 bp->cnic_kwq_last = bp->cnic_kwq + MAX_SP_DESC_CNT;
12695
12696 bp->cnic_spq_pending = 0;
12697 bp->cnic_kwq_pending = 0;
12698
12699 bp->cnic_data = data;
12700
12701 cp->num_irq = 0;
12702 cp->drv_state |= CNIC_DRV_STATE_REGD;
12703 cp->iro_arr = bp->iro_arr;
12704
12705 bnx2x_setup_cnic_irq_info(bp);
12706
12707 rcu_assign_pointer(bp->cnic_ops, ops);
12708
12709 return 0;
12710 }
12711
12712 static int bnx2x_unregister_cnic(struct net_device *dev)
12713 {
12714 struct bnx2x *bp = netdev_priv(dev);
12715 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12716
12717 mutex_lock(&bp->cnic_mutex);
12718 cp->drv_state = 0;
12719 RCU_INIT_POINTER(bp->cnic_ops, NULL);
12720 mutex_unlock(&bp->cnic_mutex);
12721 synchronize_rcu();
12722 kfree(bp->cnic_kwq);
12723 bp->cnic_kwq = NULL;
12724
12725 return 0;
12726 }
12727
12728 struct cnic_eth_dev *bnx2x_cnic_probe(struct net_device *dev)
12729 {
12730 struct bnx2x *bp = netdev_priv(dev);
12731 struct cnic_eth_dev *cp = &bp->cnic_eth_dev;
12732
12733 /* If both iSCSI and FCoE are disabled - return NULL in
12734 * order to indicate CNIC that it should not try to work
12735 * with this device.
12736 */
12737 if (NO_ISCSI(bp) && NO_FCOE(bp))
12738 return NULL;
12739
12740 cp->drv_owner = THIS_MODULE;
12741 cp->chip_id = CHIP_ID(bp);
12742 cp->pdev = bp->pdev;
12743 cp->io_base = bp->regview;
12744 cp->io_base2 = bp->doorbells;
12745 cp->max_kwqe_pending = 8;
12746 cp->ctx_blk_size = CDU_ILT_PAGE_SZ;
12747 cp->ctx_tbl_offset = FUNC_ILT_BASE(BP_FUNC(bp)) +
12748 bnx2x_cid_ilt_lines(bp);
12749 cp->ctx_tbl_len = CNIC_ILT_LINES;
12750 cp->starting_cid = bnx2x_cid_ilt_lines(bp) * ILT_PAGE_CIDS;
12751 cp->drv_submit_kwqes_16 = bnx2x_cnic_sp_queue;
12752 cp->drv_ctl = bnx2x_drv_ctl;
12753 cp->drv_register_cnic = bnx2x_register_cnic;
12754 cp->drv_unregister_cnic = bnx2x_unregister_cnic;
12755 cp->fcoe_init_cid = BNX2X_FCOE_ETH_CID(bp);
12756 cp->iscsi_l2_client_id =
12757 bnx2x_cnic_eth_cl_id(bp, BNX2X_ISCSI_ETH_CL_ID_IDX);
12758 cp->iscsi_l2_cid = BNX2X_ISCSI_ETH_CID(bp);
12759
12760 if (NO_ISCSI_OOO(bp))
12761 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI_OOO;
12762
12763 if (NO_ISCSI(bp))
12764 cp->drv_state |= CNIC_DRV_STATE_NO_ISCSI;
12765
12766 if (NO_FCOE(bp))
12767 cp->drv_state |= CNIC_DRV_STATE_NO_FCOE;
12768
12769 BNX2X_DEV_INFO(
12770 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
12771 cp->ctx_blk_size,
12772 cp->ctx_tbl_offset,
12773 cp->ctx_tbl_len,
12774 cp->starting_cid);
12775 return cp;
12776 }
12777 EXPORT_SYMBOL(bnx2x_cnic_probe);
12778
12779 #endif /* BCM_CNIC */
12780
Linux kernel - Deliverables
This page took 0.337129 seconds and 5 git commands to generate.