1 /* bnx2x_main.c: Broadcom Everest network driver.
3 * Copyright (c) 2007-2012 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20 #include <linux/module.h>
21 #include <linux/moduleparam.h>
22 #include <linux/kernel.h>
23 #include <linux/device.h> /* for dev_info() */
24 #include <linux/timer.h>
25 #include <linux/errno.h>
26 #include <linux/ioport.h>
27 #include <linux/slab.h>
28 #include <linux/interrupt.h>
29 #include <linux/pci.h>
30 #include <linux/init.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/skbuff.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/bitops.h>
36 #include <linux/irq.h>
37 #include <linux/delay.h>
38 #include <asm/byteorder.h>
39 #include <linux/time.h>
40 #include <linux/ethtool.h>
41 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
47 #include <net/checksum.h>
48 #include <net/ip6_checksum.h>
49 #include <linux/workqueue.h>
50 #include <linux/crc32.h>
51 #include <linux/crc32c.h>
52 #include <linux/prefetch.h>
53 #include <linux/zlib.h>
55 #include <linux/stringify.h>
56 #include <linux/vmalloc.h>
59 #include "bnx2x_init.h"
60 #include "bnx2x_init_ops.h"
61 #include "bnx2x_cmn.h"
62 #include "bnx2x_dcb.h"
65 #include <linux/firmware.h>
66 #include "bnx2x_fw_file_hdr.h"
68 #define FW_FILE_VERSION \
69 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
70 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
71 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
72 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
73 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
74 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
75 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
77 /* Time in jiffies before concluding the transmitter is hung */
78 #define TX_TIMEOUT (5*HZ)
80 static char version
[] __devinitdata
=
81 "Broadcom NetXtreme II 5771x/578xx 10/20-Gigabit Ethernet Driver "
82 DRV_MODULE_NAME
" " DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
84 MODULE_AUTHOR("Eliezer Tamir");
85 MODULE_DESCRIPTION("Broadcom NetXtreme II "
86 "BCM57710/57711/57711E/"
87 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
88 "57840/57840_MF Driver");
89 MODULE_LICENSE("GPL");
90 MODULE_VERSION(DRV_MODULE_VERSION
);
91 MODULE_FIRMWARE(FW_FILE_NAME_E1
);
92 MODULE_FIRMWARE(FW_FILE_NAME_E1H
);
93 MODULE_FIRMWARE(FW_FILE_NAME_E2
);
95 static int multi_mode
= 1;
96 module_param(multi_mode
, int, 0);
97 MODULE_PARM_DESC(multi_mode
, " Multi queue mode "
98 "(0 Disable; 1 Enable (default))");
101 module_param(num_queues
, int, 0);
102 MODULE_PARM_DESC(num_queues
, " Number of queues for multi_mode=1"
103 " (default is as a number of CPUs)");
105 static int disable_tpa
;
106 module_param(disable_tpa
, int, 0);
107 MODULE_PARM_DESC(disable_tpa
, " Disable the TPA (LRO) feature");
109 #define INT_MODE_INTx 1
110 #define INT_MODE_MSI 2
112 module_param(int_mode
, int, 0);
113 MODULE_PARM_DESC(int_mode
, " Force interrupt mode other than MSI-X "
116 static int dropless_fc
;
117 module_param(dropless_fc
, int, 0);
118 MODULE_PARM_DESC(dropless_fc
, " Pause on exhausted host ring");
120 static int mrrs
= -1;
121 module_param(mrrs
, int, 0);
122 MODULE_PARM_DESC(mrrs
, " Force Max Read Req Size (0..3) (for debug)");
125 module_param(debug
, int, 0);
126 MODULE_PARM_DESC(debug
, " Default debug msglevel");
130 struct workqueue_struct
*bnx2x_wq
;
132 enum bnx2x_board_type
{
146 /* indexed by board_type, above */
149 } board_info
[] __devinitdata
= {
150 { "Broadcom NetXtreme II BCM57710 10 Gigabit PCIe [Everest]" },
151 { "Broadcom NetXtreme II BCM57711 10 Gigabit PCIe" },
152 { "Broadcom NetXtreme II BCM57711E 10 Gigabit PCIe" },
153 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet" },
154 { "Broadcom NetXtreme II BCM57712 10 Gigabit Ethernet Multi Function" },
155 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet" },
156 { "Broadcom NetXtreme II BCM57800 10 Gigabit Ethernet Multi Function" },
157 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet" },
158 { "Broadcom NetXtreme II BCM57810 10 Gigabit Ethernet Multi Function" },
159 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit Ethernet" },
160 { "Broadcom NetXtreme II BCM57840 10/20 Gigabit "
161 "Ethernet Multi Function"}
164 #ifndef PCI_DEVICE_ID_NX2_57710
165 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
167 #ifndef PCI_DEVICE_ID_NX2_57711
168 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
170 #ifndef PCI_DEVICE_ID_NX2_57711E
171 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
173 #ifndef PCI_DEVICE_ID_NX2_57712
174 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
176 #ifndef PCI_DEVICE_ID_NX2_57712_MF
177 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
179 #ifndef PCI_DEVICE_ID_NX2_57800
180 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
182 #ifndef PCI_DEVICE_ID_NX2_57800_MF
183 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
185 #ifndef PCI_DEVICE_ID_NX2_57810
186 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
188 #ifndef PCI_DEVICE_ID_NX2_57810_MF
189 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
191 #ifndef PCI_DEVICE_ID_NX2_57840
192 #define PCI_DEVICE_ID_NX2_57840 CHIP_NUM_57840
194 #ifndef PCI_DEVICE_ID_NX2_57840_MF
195 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
197 static DEFINE_PCI_DEVICE_TABLE(bnx2x_pci_tbl
) = {
198 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57710
), BCM57710
},
199 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711
), BCM57711
},
200 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711E
), BCM57711E
},
201 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712
), BCM57712
},
202 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_MF
), BCM57712_MF
},
203 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800
), BCM57800
},
204 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_MF
), BCM57800_MF
},
205 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810
), BCM57810
},
206 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_MF
), BCM57810_MF
},
207 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840
), BCM57840
},
208 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
212 MODULE_DEVICE_TABLE(pci
, bnx2x_pci_tbl
);
214 /****************************************************************************
215 * General service functions
216 ****************************************************************************/
218 static inline void __storm_memset_dma_mapping(struct bnx2x
*bp
,
219 u32 addr
, dma_addr_t mapping
)
221 REG_WR(bp
, addr
, U64_LO(mapping
));
222 REG_WR(bp
, addr
+ 4, U64_HI(mapping
));
225 static inline void storm_memset_spq_addr(struct bnx2x
*bp
,
226 dma_addr_t mapping
, u16 abs_fid
)
228 u32 addr
= XSEM_REG_FAST_MEMORY
+
229 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid
);
231 __storm_memset_dma_mapping(bp
, addr
, mapping
);
234 static inline void storm_memset_vf_to_pf(struct bnx2x
*bp
, u16 abs_fid
,
237 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_VF_TO_PF_OFFSET(abs_fid
),
239 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_VF_TO_PF_OFFSET(abs_fid
),
241 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_VF_TO_PF_OFFSET(abs_fid
),
243 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_VF_TO_PF_OFFSET(abs_fid
),
247 static inline void storm_memset_func_en(struct bnx2x
*bp
, u16 abs_fid
,
250 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(abs_fid
),
252 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(abs_fid
),
254 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(abs_fid
),
256 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(abs_fid
),
260 static inline void storm_memset_eq_data(struct bnx2x
*bp
,
261 struct event_ring_data
*eq_data
,
264 size_t size
= sizeof(struct event_ring_data
);
266 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_DATA_OFFSET(pfid
);
268 __storm_memset_struct(bp
, addr
, size
, (u32
*)eq_data
);
271 static inline void storm_memset_eq_prod(struct bnx2x
*bp
, u16 eq_prod
,
274 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_PROD_OFFSET(pfid
);
275 REG_WR16(bp
, addr
, eq_prod
);
279 * locking is done by mcp
281 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
)
283 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
284 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, val
);
285 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
286 PCICFG_VENDOR_ID_OFFSET
);
289 static u32
bnx2x_reg_rd_ind(struct bnx2x
*bp
, u32 addr
)
293 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
294 pci_read_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, &val
);
295 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
296 PCICFG_VENDOR_ID_OFFSET
);
301 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
302 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
303 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
304 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
305 #define DMAE_DP_DST_NONE "dst_addr [none]"
307 static void bnx2x_dp_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
,
310 u32 src_type
= dmae
->opcode
& DMAE_COMMAND_SRC
;
312 switch (dmae
->opcode
& DMAE_COMMAND_DST
) {
313 case DMAE_CMD_DST_PCI
:
314 if (src_type
== DMAE_CMD_SRC_PCI
)
315 DP(msglvl
, "DMAE: opcode 0x%08x\n"
316 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
317 "comp_addr [%x:%08x], comp_val 0x%08x\n",
318 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
319 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
320 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
323 DP(msglvl
, "DMAE: opcode 0x%08x\n"
324 "src [%08x], len [%d*4], dst [%x:%08x]\n"
325 "comp_addr [%x:%08x], comp_val 0x%08x\n",
326 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
327 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
328 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
331 case DMAE_CMD_DST_GRC
:
332 if (src_type
== DMAE_CMD_SRC_PCI
)
333 DP(msglvl
, "DMAE: opcode 0x%08x\n"
334 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
335 "comp_addr [%x:%08x], comp_val 0x%08x\n",
336 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
337 dmae
->len
, dmae
->dst_addr_lo
>> 2,
338 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
341 DP(msglvl
, "DMAE: opcode 0x%08x\n"
342 "src [%08x], len [%d*4], dst [%08x]\n"
343 "comp_addr [%x:%08x], comp_val 0x%08x\n",
344 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
345 dmae
->len
, dmae
->dst_addr_lo
>> 2,
346 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
350 if (src_type
== DMAE_CMD_SRC_PCI
)
351 DP(msglvl
, "DMAE: opcode 0x%08x\n"
352 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
353 "comp_addr [%x:%08x] comp_val 0x%08x\n",
354 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
355 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
358 DP(msglvl
, "DMAE: opcode 0x%08x\n"
359 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
360 "comp_addr [%x:%08x] comp_val 0x%08x\n",
361 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
362 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
369 /* copy command into DMAE command memory and set DMAE command go */
370 void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int idx
)
375 cmd_offset
= (DMAE_REG_CMD_MEM
+ sizeof(struct dmae_command
) * idx
);
376 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++) {
377 REG_WR(bp
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
379 REG_WR(bp
, dmae_reg_go_c
[idx
], 1);
382 u32
bnx2x_dmae_opcode_add_comp(u32 opcode
, u8 comp_type
)
384 return opcode
| ((comp_type
<< DMAE_COMMAND_C_DST_SHIFT
) |
388 u32
bnx2x_dmae_opcode_clr_src_reset(u32 opcode
)
390 return opcode
& ~DMAE_CMD_SRC_RESET
;
393 u32
bnx2x_dmae_opcode(struct bnx2x
*bp
, u8 src_type
, u8 dst_type
,
394 bool with_comp
, u8 comp_type
)
398 opcode
|= ((src_type
<< DMAE_COMMAND_SRC_SHIFT
) |
399 (dst_type
<< DMAE_COMMAND_DST_SHIFT
));
401 opcode
|= (DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
);
403 opcode
|= (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
);
404 opcode
|= ((BP_VN(bp
) << DMAE_CMD_E1HVN_SHIFT
) |
405 (BP_VN(bp
) << DMAE_COMMAND_DST_VN_SHIFT
));
406 opcode
|= (DMAE_COM_SET_ERR
<< DMAE_COMMAND_ERR_POLICY_SHIFT
);
409 opcode
|= DMAE_CMD_ENDIANITY_B_DW_SWAP
;
411 opcode
|= DMAE_CMD_ENDIANITY_DW_SWAP
;
414 opcode
= bnx2x_dmae_opcode_add_comp(opcode
, comp_type
);
418 static void bnx2x_prep_dmae_with_comp(struct bnx2x
*bp
,
419 struct dmae_command
*dmae
,
420 u8 src_type
, u8 dst_type
)
422 memset(dmae
, 0, sizeof(struct dmae_command
));
425 dmae
->opcode
= bnx2x_dmae_opcode(bp
, src_type
, dst_type
,
426 true, DMAE_COMP_PCI
);
428 /* fill in the completion parameters */
429 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
430 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
431 dmae
->comp_val
= DMAE_COMP_VAL
;
434 /* issue a dmae command over the init-channel and wailt for completion */
435 static int bnx2x_issue_dmae_with_comp(struct bnx2x
*bp
,
436 struct dmae_command
*dmae
)
438 u32
*wb_comp
= bnx2x_sp(bp
, wb_comp
);
439 int cnt
= CHIP_REV_IS_SLOW(bp
) ? (400000) : 4000;
443 * Lock the dmae channel. Disable BHs to prevent a dead-lock
444 * as long as this code is called both from syscall context and
445 * from ndo_set_rx_mode() flow that may be called from BH.
447 spin_lock_bh(&bp
->dmae_lock
);
449 /* reset completion */
452 /* post the command on the channel used for initializations */
453 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
455 /* wait for completion */
457 while ((*wb_comp
& ~DMAE_PCI_ERR_FLAG
) != DMAE_COMP_VAL
) {
460 (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
&&
461 bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
462 BNX2X_ERR("DMAE timeout!\n");
469 if (*wb_comp
& DMAE_PCI_ERR_FLAG
) {
470 BNX2X_ERR("DMAE PCI error!\n");
475 spin_unlock_bh(&bp
->dmae_lock
);
479 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
482 struct dmae_command dmae
;
484 if (!bp
->dmae_ready
) {
485 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
488 bnx2x_init_ind_wr(bp
, dst_addr
, data
, len32
);
490 bnx2x_init_str_wr(bp
, dst_addr
, data
, len32
);
494 /* set opcode and fixed command fields */
495 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_PCI
, DMAE_DST_GRC
);
497 /* fill in addresses and len */
498 dmae
.src_addr_lo
= U64_LO(dma_addr
);
499 dmae
.src_addr_hi
= U64_HI(dma_addr
);
500 dmae
.dst_addr_lo
= dst_addr
>> 2;
501 dmae
.dst_addr_hi
= 0;
504 bnx2x_dp_dmae(bp
, &dmae
, BNX2X_MSG_OFF
);
506 /* issue the command and wait for completion */
507 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
510 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
)
512 struct dmae_command dmae
;
514 if (!bp
->dmae_ready
) {
515 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
519 for (i
= 0; i
< len32
; i
++)
520 data
[i
] = bnx2x_reg_rd_ind(bp
, src_addr
+ i
*4);
522 for (i
= 0; i
< len32
; i
++)
523 data
[i
] = REG_RD(bp
, src_addr
+ i
*4);
528 /* set opcode and fixed command fields */
529 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_GRC
, DMAE_DST_PCI
);
531 /* fill in addresses and len */
532 dmae
.src_addr_lo
= src_addr
>> 2;
533 dmae
.src_addr_hi
= 0;
534 dmae
.dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_data
));
535 dmae
.dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_data
));
538 bnx2x_dp_dmae(bp
, &dmae
, BNX2X_MSG_OFF
);
540 /* issue the command and wait for completion */
541 bnx2x_issue_dmae_with_comp(bp
, &dmae
);
544 static void bnx2x_write_dmae_phys_len(struct bnx2x
*bp
, dma_addr_t phys_addr
,
547 int dmae_wr_max
= DMAE_LEN32_WR_MAX(bp
);
550 while (len
> dmae_wr_max
) {
551 bnx2x_write_dmae(bp
, phys_addr
+ offset
,
552 addr
+ offset
, dmae_wr_max
);
553 offset
+= dmae_wr_max
* 4;
557 bnx2x_write_dmae(bp
, phys_addr
+ offset
, addr
+ offset
, len
);
560 /* used only for slowpath so not inlined */
561 static void bnx2x_wb_wr(struct bnx2x
*bp
, int reg
, u32 val_hi
, u32 val_lo
)
565 wb_write
[0] = val_hi
;
566 wb_write
[1] = val_lo
;
567 REG_WR_DMAE(bp
, reg
, wb_write
, 2);
571 static u64
bnx2x_wb_rd(struct bnx2x
*bp
, int reg
)
575 REG_RD_DMAE(bp
, reg
, wb_data
, 2);
577 return HILO_U64(wb_data
[0], wb_data
[1]);
581 static int bnx2x_mc_assert(struct bnx2x
*bp
)
585 u32 row0
, row1
, row2
, row3
;
588 last_idx
= REG_RD8(bp
, BAR_XSTRORM_INTMEM
+
589 XSTORM_ASSERT_LIST_INDEX_OFFSET
);
591 BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
593 /* print the asserts */
594 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
596 row0
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
597 XSTORM_ASSERT_LIST_OFFSET(i
));
598 row1
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
599 XSTORM_ASSERT_LIST_OFFSET(i
) + 4);
600 row2
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
601 XSTORM_ASSERT_LIST_OFFSET(i
) + 8);
602 row3
= REG_RD(bp
, BAR_XSTRORM_INTMEM
+
603 XSTORM_ASSERT_LIST_OFFSET(i
) + 12);
605 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
606 BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
607 i
, row3
, row2
, row1
, row0
);
615 last_idx
= REG_RD8(bp
, BAR_TSTRORM_INTMEM
+
616 TSTORM_ASSERT_LIST_INDEX_OFFSET
);
618 BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
620 /* print the asserts */
621 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
623 row0
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
624 TSTORM_ASSERT_LIST_OFFSET(i
));
625 row1
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
626 TSTORM_ASSERT_LIST_OFFSET(i
) + 4);
627 row2
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
628 TSTORM_ASSERT_LIST_OFFSET(i
) + 8);
629 row3
= REG_RD(bp
, BAR_TSTRORM_INTMEM
+
630 TSTORM_ASSERT_LIST_OFFSET(i
) + 12);
632 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
633 BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
634 i
, row3
, row2
, row1
, row0
);
642 last_idx
= REG_RD8(bp
, BAR_CSTRORM_INTMEM
+
643 CSTORM_ASSERT_LIST_INDEX_OFFSET
);
645 BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
647 /* print the asserts */
648 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
650 row0
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
651 CSTORM_ASSERT_LIST_OFFSET(i
));
652 row1
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
653 CSTORM_ASSERT_LIST_OFFSET(i
) + 4);
654 row2
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
655 CSTORM_ASSERT_LIST_OFFSET(i
) + 8);
656 row3
= REG_RD(bp
, BAR_CSTRORM_INTMEM
+
657 CSTORM_ASSERT_LIST_OFFSET(i
) + 12);
659 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
660 BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
661 i
, row3
, row2
, row1
, row0
);
669 last_idx
= REG_RD8(bp
, BAR_USTRORM_INTMEM
+
670 USTORM_ASSERT_LIST_INDEX_OFFSET
);
672 BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx
);
674 /* print the asserts */
675 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
677 row0
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
678 USTORM_ASSERT_LIST_OFFSET(i
));
679 row1
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
680 USTORM_ASSERT_LIST_OFFSET(i
) + 4);
681 row2
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
682 USTORM_ASSERT_LIST_OFFSET(i
) + 8);
683 row3
= REG_RD(bp
, BAR_USTRORM_INTMEM
+
684 USTORM_ASSERT_LIST_OFFSET(i
) + 12);
686 if (row0
!= COMMON_ASM_INVALID_ASSERT_OPCODE
) {
687 BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
688 i
, row3
, row2
, row1
, row0
);
698 void bnx2x_fw_dump_lvl(struct bnx2x
*bp
, const char *lvl
)
704 u32 trace_shmem_base
;
706 BNX2X_ERR("NO MCP - can not dump\n");
709 netdev_printk(lvl
, bp
->dev
, "bc %d.%d.%d\n",
710 (bp
->common
.bc_ver
& 0xff0000) >> 16,
711 (bp
->common
.bc_ver
& 0xff00) >> 8,
712 (bp
->common
.bc_ver
& 0xff));
714 val
= REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
);
715 if (val
== REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
))
716 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl
, val
);
718 if (BP_PATH(bp
) == 0)
719 trace_shmem_base
= bp
->common
.shmem_base
;
721 trace_shmem_base
= SHMEM2_RD(bp
, other_shmem_base_addr
);
722 addr
= trace_shmem_base
- 0x800;
724 /* validate TRCB signature */
725 mark
= REG_RD(bp
, addr
);
726 if (mark
!= MFW_TRACE_SIGNATURE
) {
727 BNX2X_ERR("Trace buffer signature is missing.");
731 /* read cyclic buffer pointer */
733 mark
= REG_RD(bp
, addr
);
734 mark
= (CHIP_IS_E1x(bp
) ? MCP_REG_MCPR_SCRATCH
: MCP_A_REG_MCPR_SCRATCH
)
735 + ((mark
+ 0x3) & ~0x3) - 0x08000000;
736 printk("%s" "begin fw dump (mark 0x%x)\n", lvl
, mark
);
739 for (offset
= mark
; offset
<= trace_shmem_base
; offset
+= 0x8*4) {
740 for (word
= 0; word
< 8; word
++)
741 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
743 pr_cont("%s", (char *)data
);
745 for (offset
= addr
+ 4; offset
<= mark
; offset
+= 0x8*4) {
746 for (word
= 0; word
< 8; word
++)
747 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
749 pr_cont("%s", (char *)data
);
751 printk("%s" "end of fw dump\n", lvl
);
754 static inline void bnx2x_fw_dump(struct bnx2x
*bp
)
756 bnx2x_fw_dump_lvl(bp
, KERN_ERR
);
759 void bnx2x_panic_dump(struct bnx2x
*bp
)
763 struct hc_sp_status_block_data sp_sb_data
;
764 int func
= BP_FUNC(bp
);
765 #ifdef BNX2X_STOP_ON_ERROR
766 u16 start
= 0, end
= 0;
770 bp
->stats_state
= STATS_STATE_DISABLED
;
771 bp
->eth_stats
.unrecoverable_error
++;
772 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
774 BNX2X_ERR("begin crash dump -----------------\n");
778 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
779 bp
->def_idx
, bp
->def_att_idx
, bp
->attn_state
,
780 bp
->spq_prod_idx
, bp
->stats_counter
);
781 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
782 bp
->def_status_blk
->atten_status_block
.attn_bits
,
783 bp
->def_status_blk
->atten_status_block
.attn_bits_ack
,
784 bp
->def_status_blk
->atten_status_block
.status_block_id
,
785 bp
->def_status_blk
->atten_status_block
.attn_bits_index
);
787 for (i
= 0; i
< HC_SP_SB_MAX_INDICES
; i
++)
789 bp
->def_status_blk
->sp_sb
.index_values
[i
],
790 (i
== HC_SP_SB_MAX_INDICES
- 1) ? ") " : " ");
792 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
793 *((u32
*)&sp_sb_data
+ i
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
794 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
797 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
798 sp_sb_data
.igu_sb_id
,
799 sp_sb_data
.igu_seg_id
,
800 sp_sb_data
.p_func
.pf_id
,
801 sp_sb_data
.p_func
.vnic_id
,
802 sp_sb_data
.p_func
.vf_id
,
803 sp_sb_data
.p_func
.vf_valid
,
807 for_each_eth_queue(bp
, i
) {
808 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
810 struct hc_status_block_data_e2 sb_data_e2
;
811 struct hc_status_block_data_e1x sb_data_e1x
;
812 struct hc_status_block_sm
*hc_sm_p
=
814 sb_data_e1x
.common
.state_machine
:
815 sb_data_e2
.common
.state_machine
;
816 struct hc_index_data
*hc_index_p
=
818 sb_data_e1x
.index_data
:
819 sb_data_e2
.index_data
;
822 struct bnx2x_fp_txdata txdata
;
825 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
826 i
, fp
->rx_bd_prod
, fp
->rx_bd_cons
,
828 fp
->rx_comp_cons
, le16_to_cpu(*fp
->rx_cons_sb
));
829 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
830 fp
->rx_sge_prod
, fp
->last_max_sge
,
831 le16_to_cpu(fp
->fp_hc_idx
));
834 for_each_cos_in_tx_queue(fp
, cos
)
836 txdata
= fp
->txdata
[cos
];
837 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
838 i
, txdata
.tx_pkt_prod
,
839 txdata
.tx_pkt_cons
, txdata
.tx_bd_prod
,
841 le16_to_cpu(*txdata
.tx_cons_sb
));
844 loop
= CHIP_IS_E1x(bp
) ?
845 HC_SB_MAX_INDICES_E1X
: HC_SB_MAX_INDICES_E2
;
853 BNX2X_ERR(" run indexes (");
854 for (j
= 0; j
< HC_SB_MAX_SM
; j
++)
856 fp
->sb_running_index
[j
],
857 (j
== HC_SB_MAX_SM
- 1) ? ")" : " ");
859 BNX2X_ERR(" indexes (");
860 for (j
= 0; j
< loop
; j
++)
862 fp
->sb_index_values
[j
],
863 (j
== loop
- 1) ? ")" : " ");
865 data_size
= CHIP_IS_E1x(bp
) ?
866 sizeof(struct hc_status_block_data_e1x
) :
867 sizeof(struct hc_status_block_data_e2
);
868 data_size
/= sizeof(u32
);
869 sb_data_p
= CHIP_IS_E1x(bp
) ?
870 (u32
*)&sb_data_e1x
:
872 /* copy sb data in here */
873 for (j
= 0; j
< data_size
; j
++)
874 *(sb_data_p
+ j
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
875 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp
->fw_sb_id
) +
878 if (!CHIP_IS_E1x(bp
)) {
879 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
880 sb_data_e2
.common
.p_func
.pf_id
,
881 sb_data_e2
.common
.p_func
.vf_id
,
882 sb_data_e2
.common
.p_func
.vf_valid
,
883 sb_data_e2
.common
.p_func
.vnic_id
,
884 sb_data_e2
.common
.same_igu_sb_1b
,
885 sb_data_e2
.common
.state
);
887 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
888 sb_data_e1x
.common
.p_func
.pf_id
,
889 sb_data_e1x
.common
.p_func
.vf_id
,
890 sb_data_e1x
.common
.p_func
.vf_valid
,
891 sb_data_e1x
.common
.p_func
.vnic_id
,
892 sb_data_e1x
.common
.same_igu_sb_1b
,
893 sb_data_e1x
.common
.state
);
897 for (j
= 0; j
< HC_SB_MAX_SM
; j
++) {
898 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
899 j
, hc_sm_p
[j
].__flags
,
900 hc_sm_p
[j
].igu_sb_id
,
901 hc_sm_p
[j
].igu_seg_id
,
902 hc_sm_p
[j
].time_to_expire
,
903 hc_sm_p
[j
].timer_value
);
907 for (j
= 0; j
< loop
; j
++) {
908 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j
,
910 hc_index_p
[j
].timeout
);
914 #ifdef BNX2X_STOP_ON_ERROR
917 for_each_rx_queue(bp
, i
) {
918 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
920 start
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) - 10);
921 end
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) + 503);
922 for (j
= start
; j
!= end
; j
= RX_BD(j
+ 1)) {
923 u32
*rx_bd
= (u32
*)&fp
->rx_desc_ring
[j
];
924 struct sw_rx_bd
*sw_bd
= &fp
->rx_buf_ring
[j
];
926 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
927 i
, j
, rx_bd
[1], rx_bd
[0], sw_bd
->data
);
930 start
= RX_SGE(fp
->rx_sge_prod
);
931 end
= RX_SGE(fp
->last_max_sge
);
932 for (j
= start
; j
!= end
; j
= RX_SGE(j
+ 1)) {
933 u32
*rx_sge
= (u32
*)&fp
->rx_sge_ring
[j
];
934 struct sw_rx_page
*sw_page
= &fp
->rx_page_ring
[j
];
936 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
937 i
, j
, rx_sge
[1], rx_sge
[0], sw_page
->page
);
940 start
= RCQ_BD(fp
->rx_comp_cons
- 10);
941 end
= RCQ_BD(fp
->rx_comp_cons
+ 503);
942 for (j
= start
; j
!= end
; j
= RCQ_BD(j
+ 1)) {
943 u32
*cqe
= (u32
*)&fp
->rx_comp_ring
[j
];
945 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
946 i
, j
, cqe
[0], cqe
[1], cqe
[2], cqe
[3]);
951 for_each_tx_queue(bp
, i
) {
952 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
953 for_each_cos_in_tx_queue(fp
, cos
) {
954 struct bnx2x_fp_txdata
*txdata
= &fp
->txdata
[cos
];
956 start
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) - 10);
957 end
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) + 245);
958 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
959 struct sw_tx_bd
*sw_bd
=
960 &txdata
->tx_buf_ring
[j
];
962 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
963 i
, cos
, j
, sw_bd
->skb
,
967 start
= TX_BD(txdata
->tx_bd_cons
- 10);
968 end
= TX_BD(txdata
->tx_bd_cons
+ 254);
969 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
970 u32
*tx_bd
= (u32
*)&txdata
->tx_desc_ring
[j
];
972 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
973 i
, cos
, j
, tx_bd
[0], tx_bd
[1],
981 BNX2X_ERR("end crash dump -----------------\n");
987 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
990 #define FLR_WAIT_USEC 10000 /* 10 miliseconds */
991 #define FLR_WAIT_INTERVAL 50 /* usec */
992 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
994 struct pbf_pN_buf_regs
{
1001 struct pbf_pN_cmd_regs
{
1007 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x
*bp
,
1008 struct pbf_pN_buf_regs
*regs
,
1011 u32 init_crd
, crd
, crd_start
, crd_freed
, crd_freed_start
;
1012 u32 cur_cnt
= poll_count
;
1014 crd_freed
= crd_freed_start
= REG_RD(bp
, regs
->crd_freed
);
1015 crd
= crd_start
= REG_RD(bp
, regs
->crd
);
1016 init_crd
= REG_RD(bp
, regs
->init_crd
);
1018 DP(BNX2X_MSG_SP
, "INIT CREDIT[%d] : %x\n", regs
->pN
, init_crd
);
1019 DP(BNX2X_MSG_SP
, "CREDIT[%d] : s:%x\n", regs
->pN
, crd
);
1020 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: s:%x\n", regs
->pN
, crd_freed
);
1022 while ((crd
!= init_crd
) && ((u32
)SUB_S32(crd_freed
, crd_freed_start
) <
1023 (init_crd
- crd_start
))) {
1025 udelay(FLR_WAIT_INTERVAL
);
1026 crd
= REG_RD(bp
, regs
->crd
);
1027 crd_freed
= REG_RD(bp
, regs
->crd_freed
);
1029 DP(BNX2X_MSG_SP
, "PBF tx buffer[%d] timed out\n",
1031 DP(BNX2X_MSG_SP
, "CREDIT[%d] : c:%x\n",
1033 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: c:%x\n",
1034 regs
->pN
, crd_freed
);
1038 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1039 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1042 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x
*bp
,
1043 struct pbf_pN_cmd_regs
*regs
,
1046 u32 occup
, to_free
, freed
, freed_start
;
1047 u32 cur_cnt
= poll_count
;
1049 occup
= to_free
= REG_RD(bp
, regs
->lines_occup
);
1050 freed
= freed_start
= REG_RD(bp
, regs
->lines_freed
);
1052 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n", regs
->pN
, occup
);
1053 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n", regs
->pN
, freed
);
1055 while (occup
&& ((u32
)SUB_S32(freed
, freed_start
) < to_free
)) {
1057 udelay(FLR_WAIT_INTERVAL
);
1058 occup
= REG_RD(bp
, regs
->lines_occup
);
1059 freed
= REG_RD(bp
, regs
->lines_freed
);
1061 DP(BNX2X_MSG_SP
, "PBF cmd queue[%d] timed out\n",
1063 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n",
1065 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n",
1070 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1071 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1074 static inline u32
bnx2x_flr_clnup_reg_poll(struct bnx2x
*bp
, u32 reg
,
1075 u32 expected
, u32 poll_count
)
1077 u32 cur_cnt
= poll_count
;
1080 while ((val
= REG_RD(bp
, reg
)) != expected
&& cur_cnt
--)
1081 udelay(FLR_WAIT_INTERVAL
);
1086 static inline int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x
*bp
, u32 reg
,
1087 char *msg
, u32 poll_cnt
)
1089 u32 val
= bnx2x_flr_clnup_reg_poll(bp
, reg
, 0, poll_cnt
);
1091 BNX2X_ERR("%s usage count=%d\n", msg
, val
);
1097 static u32
bnx2x_flr_clnup_poll_count(struct bnx2x
*bp
)
1099 /* adjust polling timeout */
1100 if (CHIP_REV_IS_EMUL(bp
))
1101 return FLR_POLL_CNT
* 2000;
1103 if (CHIP_REV_IS_FPGA(bp
))
1104 return FLR_POLL_CNT
* 120;
1106 return FLR_POLL_CNT
;
1109 static void bnx2x_tx_hw_flushed(struct bnx2x
*bp
, u32 poll_count
)
1111 struct pbf_pN_cmd_regs cmd_regs
[] = {
1112 {0, (CHIP_IS_E3B0(bp
)) ?
1113 PBF_REG_TQ_OCCUPANCY_Q0
:
1114 PBF_REG_P0_TQ_OCCUPANCY
,
1115 (CHIP_IS_E3B0(bp
)) ?
1116 PBF_REG_TQ_LINES_FREED_CNT_Q0
:
1117 PBF_REG_P0_TQ_LINES_FREED_CNT
},
1118 {1, (CHIP_IS_E3B0(bp
)) ?
1119 PBF_REG_TQ_OCCUPANCY_Q1
:
1120 PBF_REG_P1_TQ_OCCUPANCY
,
1121 (CHIP_IS_E3B0(bp
)) ?
1122 PBF_REG_TQ_LINES_FREED_CNT_Q1
:
1123 PBF_REG_P1_TQ_LINES_FREED_CNT
},
1124 {4, (CHIP_IS_E3B0(bp
)) ?
1125 PBF_REG_TQ_OCCUPANCY_LB_Q
:
1126 PBF_REG_P4_TQ_OCCUPANCY
,
1127 (CHIP_IS_E3B0(bp
)) ?
1128 PBF_REG_TQ_LINES_FREED_CNT_LB_Q
:
1129 PBF_REG_P4_TQ_LINES_FREED_CNT
}
1132 struct pbf_pN_buf_regs buf_regs
[] = {
1133 {0, (CHIP_IS_E3B0(bp
)) ?
1134 PBF_REG_INIT_CRD_Q0
:
1135 PBF_REG_P0_INIT_CRD
,
1136 (CHIP_IS_E3B0(bp
)) ?
1139 (CHIP_IS_E3B0(bp
)) ?
1140 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
:
1141 PBF_REG_P0_INTERNAL_CRD_FREED_CNT
},
1142 {1, (CHIP_IS_E3B0(bp
)) ?
1143 PBF_REG_INIT_CRD_Q1
:
1144 PBF_REG_P1_INIT_CRD
,
1145 (CHIP_IS_E3B0(bp
)) ?
1148 (CHIP_IS_E3B0(bp
)) ?
1149 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
:
1150 PBF_REG_P1_INTERNAL_CRD_FREED_CNT
},
1151 {4, (CHIP_IS_E3B0(bp
)) ?
1152 PBF_REG_INIT_CRD_LB_Q
:
1153 PBF_REG_P4_INIT_CRD
,
1154 (CHIP_IS_E3B0(bp
)) ?
1155 PBF_REG_CREDIT_LB_Q
:
1157 (CHIP_IS_E3B0(bp
)) ?
1158 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
:
1159 PBF_REG_P4_INTERNAL_CRD_FREED_CNT
},
1164 /* Verify the command queues are flushed P0, P1, P4 */
1165 for (i
= 0; i
< ARRAY_SIZE(cmd_regs
); i
++)
1166 bnx2x_pbf_pN_cmd_flushed(bp
, &cmd_regs
[i
], poll_count
);
1169 /* Verify the transmission buffers are flushed P0, P1, P4 */
1170 for (i
= 0; i
< ARRAY_SIZE(buf_regs
); i
++)
1171 bnx2x_pbf_pN_buf_flushed(bp
, &buf_regs
[i
], poll_count
);
1174 #define OP_GEN_PARAM(param) \
1175 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1177 #define OP_GEN_TYPE(type) \
1178 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1180 #define OP_GEN_AGG_VECT(index) \
1181 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1184 static inline int bnx2x_send_final_clnup(struct bnx2x
*bp
, u8 clnup_func
,
1187 struct sdm_op_gen op_gen
= {0};
1189 u32 comp_addr
= BAR_CSTRORM_INTMEM
+
1190 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func
);
1193 if (REG_RD(bp
, comp_addr
)) {
1194 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1198 op_gen
.command
|= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
);
1199 op_gen
.command
|= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
);
1200 op_gen
.command
|= OP_GEN_AGG_VECT(clnup_func
);
1201 op_gen
.command
|= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT
;
1203 DP(BNX2X_MSG_SP
, "sending FW Final cleanup\n");
1204 REG_WR(bp
, XSDM_REG_OPERATION_GEN
, op_gen
.command
);
1206 if (bnx2x_flr_clnup_reg_poll(bp
, comp_addr
, 1, poll_cnt
) != 1) {
1207 BNX2X_ERR("FW final cleanup did not succeed\n");
1208 DP(BNX2X_MSG_SP
, "At timeout completion address contained %x\n",
1209 (REG_RD(bp
, comp_addr
)));
1212 /* Zero completion for nxt FLR */
1213 REG_WR(bp
, comp_addr
, 0);
1218 static inline u8
bnx2x_is_pcie_pending(struct pci_dev
*dev
)
1223 pos
= pci_pcie_cap(dev
);
1227 pci_read_config_word(dev
, pos
+ PCI_EXP_DEVSTA
, &status
);
1228 return status
& PCI_EXP_DEVSTA_TRPND
;
1231 /* PF FLR specific routines
1233 static int bnx2x_poll_hw_usage_counters(struct bnx2x
*bp
, u32 poll_cnt
)
1236 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1237 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1238 CFC_REG_NUM_LCIDS_INSIDE_PF
,
1239 "CFC PF usage counter timed out",
1244 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1245 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1246 DORQ_REG_PF_USAGE_CNT
,
1247 "DQ PF usage counter timed out",
1251 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1252 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1253 QM_REG_PF_USG_CNT_0
+ 4*BP_FUNC(bp
),
1254 "QM PF usage counter timed out",
1258 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1259 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1260 TM_REG_LIN0_VNIC_UC
+ 4*BP_PORT(bp
),
1261 "Timers VNIC usage counter timed out",
1264 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1265 TM_REG_LIN0_NUM_SCANS
+ 4*BP_PORT(bp
),
1266 "Timers NUM_SCANS usage counter timed out",
1270 /* Wait DMAE PF usage counter to zero */
1271 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1272 dmae_reg_go_c
[INIT_DMAE_C(bp
)],
1273 "DMAE dommand register timed out",
1280 static void bnx2x_hw_enable_status(struct bnx2x
*bp
)
1284 val
= REG_RD(bp
, CFC_REG_WEAK_ENABLE_PF
);
1285 DP(BNX2X_MSG_SP
, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val
);
1287 val
= REG_RD(bp
, PBF_REG_DISABLE_PF
);
1288 DP(BNX2X_MSG_SP
, "PBF_REG_DISABLE_PF is 0x%x\n", val
);
1290 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSI_EN
);
1291 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val
);
1293 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_EN
);
1294 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val
);
1296 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_FUNC_MASK
);
1297 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val
);
1299 val
= REG_RD(bp
, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
);
1300 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val
);
1302 val
= REG_RD(bp
, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
);
1303 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val
);
1305 val
= REG_RD(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
1306 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1310 static int bnx2x_pf_flr_clnup(struct bnx2x
*bp
)
1312 u32 poll_cnt
= bnx2x_flr_clnup_poll_count(bp
);
1314 DP(BNX2X_MSG_SP
, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp
));
1316 /* Re-enable PF target read access */
1317 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1319 /* Poll HW usage counters */
1320 DP(BNX2X_MSG_SP
, "Polling usage counters\n");
1321 if (bnx2x_poll_hw_usage_counters(bp
, poll_cnt
))
1324 /* Zero the igu 'trailing edge' and 'leading edge' */
1326 /* Send the FW cleanup command */
1327 if (bnx2x_send_final_clnup(bp
, (u8
)BP_FUNC(bp
), poll_cnt
))
1332 /* Verify TX hw is flushed */
1333 bnx2x_tx_hw_flushed(bp
, poll_cnt
);
1335 /* Wait 100ms (not adjusted according to platform) */
1338 /* Verify no pending pci transactions */
1339 if (bnx2x_is_pcie_pending(bp
->pdev
))
1340 BNX2X_ERR("PCIE Transactions still pending\n");
1343 bnx2x_hw_enable_status(bp
);
1346 * Master enable - Due to WB DMAE writes performed before this
1347 * register is re-initialized as part of the regular function init
1349 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
1354 static void bnx2x_hc_int_enable(struct bnx2x
*bp
)
1356 int port
= BP_PORT(bp
);
1357 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1358 u32 val
= REG_RD(bp
, addr
);
1359 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1360 int msi
= (bp
->flags
& USING_MSI_FLAG
) ? 1 : 0;
1363 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1364 HC_CONFIG_0_REG_INT_LINE_EN_0
);
1365 val
|= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1366 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1368 val
&= ~HC_CONFIG_0_REG_INT_LINE_EN_0
;
1369 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1370 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1371 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1373 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1374 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1375 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1376 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1378 if (!CHIP_IS_E1(bp
)) {
1380 "write %x to HC %d (addr 0x%x)\n", val
, port
, addr
);
1382 REG_WR(bp
, addr
, val
);
1384 val
&= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
;
1389 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0x1FFFF);
1392 "write %x to HC %d (addr 0x%x) mode %s\n", val
, port
, addr
,
1393 (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1395 REG_WR(bp
, addr
, val
);
1397 * Ensure that HC_CONFIG is written before leading/trailing edge config
1402 if (!CHIP_IS_E1(bp
)) {
1403 /* init leading/trailing edge */
1405 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1407 /* enable nig and gpio3 attention */
1412 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
1413 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
1416 /* Make sure that interrupts are indeed enabled from here on */
1420 static void bnx2x_igu_int_enable(struct bnx2x
*bp
)
1423 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1424 int msi
= (bp
->flags
& USING_MSI_FLAG
) ? 1 : 0;
1426 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1429 val
&= ~(IGU_PF_CONF_INT_LINE_EN
|
1430 IGU_PF_CONF_SINGLE_ISR_EN
);
1431 val
|= (IGU_PF_CONF_FUNC_EN
|
1432 IGU_PF_CONF_MSI_MSIX_EN
|
1433 IGU_PF_CONF_ATTN_BIT_EN
);
1435 val
&= ~IGU_PF_CONF_INT_LINE_EN
;
1436 val
|= (IGU_PF_CONF_FUNC_EN
|
1437 IGU_PF_CONF_MSI_MSIX_EN
|
1438 IGU_PF_CONF_ATTN_BIT_EN
|
1439 IGU_PF_CONF_SINGLE_ISR_EN
);
1441 val
&= ~IGU_PF_CONF_MSI_MSIX_EN
;
1442 val
|= (IGU_PF_CONF_FUNC_EN
|
1443 IGU_PF_CONF_INT_LINE_EN
|
1444 IGU_PF_CONF_ATTN_BIT_EN
|
1445 IGU_PF_CONF_SINGLE_ISR_EN
);
1448 DP(NETIF_MSG_IFUP
, "write 0x%x to IGU mode %s\n",
1449 val
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1451 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1455 /* init leading/trailing edge */
1457 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1459 /* enable nig and gpio3 attention */
1464 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
1465 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
1467 /* Make sure that interrupts are indeed enabled from here on */
1471 void bnx2x_int_enable(struct bnx2x
*bp
)
1473 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1474 bnx2x_hc_int_enable(bp
);
1476 bnx2x_igu_int_enable(bp
);
1479 static void bnx2x_hc_int_disable(struct bnx2x
*bp
)
1481 int port
= BP_PORT(bp
);
1482 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1483 u32 val
= REG_RD(bp
, addr
);
1486 * in E1 we must use only PCI configuration space to disable
1487 * MSI/MSIX capablility
1488 * It's forbitten to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
1490 if (CHIP_IS_E1(bp
)) {
1491 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
1492 * Use mask register to prevent from HC sending interrupts
1493 * after we exit the function
1495 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0);
1497 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1498 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1499 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1501 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1502 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1503 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1504 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1506 DP(NETIF_MSG_IFDOWN
,
1507 "write %x to HC %d (addr 0x%x)\n",
1510 /* flush all outstanding writes */
1513 REG_WR(bp
, addr
, val
);
1514 if (REG_RD(bp
, addr
) != val
)
1515 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1518 static void bnx2x_igu_int_disable(struct bnx2x
*bp
)
1520 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1522 val
&= ~(IGU_PF_CONF_MSI_MSIX_EN
|
1523 IGU_PF_CONF_INT_LINE_EN
|
1524 IGU_PF_CONF_ATTN_BIT_EN
);
1526 DP(NETIF_MSG_IFDOWN
, "write %x to IGU\n", val
);
1528 /* flush all outstanding writes */
1531 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1532 if (REG_RD(bp
, IGU_REG_PF_CONFIGURATION
) != val
)
1533 BNX2X_ERR("BUG! proper val not read from IGU!\n");
1536 void bnx2x_int_disable(struct bnx2x
*bp
)
1538 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1539 bnx2x_hc_int_disable(bp
);
1541 bnx2x_igu_int_disable(bp
);
1544 void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
)
1546 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1550 /* prevent the HW from sending interrupts */
1551 bnx2x_int_disable(bp
);
1553 /* make sure all ISRs are done */
1555 synchronize_irq(bp
->msix_table
[0].vector
);
1560 for_each_eth_queue(bp
, i
)
1561 synchronize_irq(bp
->msix_table
[offset
++].vector
);
1563 synchronize_irq(bp
->pdev
->irq
);
1565 /* make sure sp_task is not running */
1566 cancel_delayed_work(&bp
->sp_task
);
1567 cancel_delayed_work(&bp
->period_task
);
1568 flush_workqueue(bnx2x_wq
);
1574 * General service functions
1577 /* Return true if succeeded to acquire the lock */
1578 static bool bnx2x_trylock_hw_lock(struct bnx2x
*bp
, u32 resource
)
1581 u32 resource_bit
= (1 << resource
);
1582 int func
= BP_FUNC(bp
);
1583 u32 hw_lock_control_reg
;
1585 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1586 "Trying to take a lock on resource %d\n", resource
);
1588 /* Validating that the resource is within range */
1589 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1590 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1591 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1592 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1597 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1599 hw_lock_control_reg
=
1600 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1602 /* Try to acquire the lock */
1603 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1604 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1605 if (lock_status
& resource_bit
)
1608 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1609 "Failed to get a lock on resource %d\n", resource
);
1614 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1616 * @bp: driver handle
1618 * Returns the recovery leader resource id according to the engine this function
1619 * belongs to. Currently only only 2 engines is supported.
1621 static inline int bnx2x_get_leader_lock_resource(struct bnx2x
*bp
)
1624 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1
;
1626 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0
;
1630 * bnx2x_trylock_leader_lock- try to aquire a leader lock.
1632 * @bp: driver handle
1634 * Tries to aquire a leader lock for cuurent engine.
1636 static inline bool bnx2x_trylock_leader_lock(struct bnx2x
*bp
)
1638 return bnx2x_trylock_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1642 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
);
1645 void bnx2x_sp_event(struct bnx2x_fastpath
*fp
, union eth_rx_cqe
*rr_cqe
)
1647 struct bnx2x
*bp
= fp
->bp
;
1648 int cid
= SW_CID(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1649 int command
= CQE_CMD(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1650 enum bnx2x_queue_cmd drv_cmd
= BNX2X_Q_CMD_MAX
;
1651 struct bnx2x_queue_sp_obj
*q_obj
= &fp
->q_obj
;
1654 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1655 fp
->index
, cid
, command
, bp
->state
,
1656 rr_cqe
->ramrod_cqe
.ramrod_type
);
1659 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE
):
1660 DP(BNX2X_MSG_SP
, "got UPDATE ramrod. CID %d\n", cid
);
1661 drv_cmd
= BNX2X_Q_CMD_UPDATE
;
1664 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP
):
1665 DP(BNX2X_MSG_SP
, "got MULTI[%d] setup ramrod\n", cid
);
1666 drv_cmd
= BNX2X_Q_CMD_SETUP
;
1669 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
):
1670 DP(BNX2X_MSG_SP
, "got MULTI[%d] tx-only setup ramrod\n", cid
);
1671 drv_cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
1674 case (RAMROD_CMD_ID_ETH_HALT
):
1675 DP(BNX2X_MSG_SP
, "got MULTI[%d] halt ramrod\n", cid
);
1676 drv_cmd
= BNX2X_Q_CMD_HALT
;
1679 case (RAMROD_CMD_ID_ETH_TERMINATE
):
1680 DP(BNX2X_MSG_SP
, "got MULTI[%d] teminate ramrod\n", cid
);
1681 drv_cmd
= BNX2X_Q_CMD_TERMINATE
;
1684 case (RAMROD_CMD_ID_ETH_EMPTY
):
1685 DP(BNX2X_MSG_SP
, "got MULTI[%d] empty ramrod\n", cid
);
1686 drv_cmd
= BNX2X_Q_CMD_EMPTY
;
1690 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1691 command
, fp
->index
);
1695 if ((drv_cmd
!= BNX2X_Q_CMD_MAX
) &&
1696 q_obj
->complete_cmd(bp
, q_obj
, drv_cmd
))
1697 /* q_obj->complete_cmd() failure means that this was
1698 * an unexpected completion.
1700 * In this case we don't want to increase the bp->spq_left
1701 * because apparently we haven't sent this command the first
1704 #ifdef BNX2X_STOP_ON_ERROR
1710 smp_mb__before_atomic_inc();
1711 atomic_inc(&bp
->cq_spq_left
);
1712 /* push the change in bp->spq_left and towards the memory */
1713 smp_mb__after_atomic_inc();
1715 DP(BNX2X_MSG_SP
, "bp->cq_spq_left %x\n", atomic_read(&bp
->cq_spq_left
));
1720 void bnx2x_update_rx_prod(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
1721 u16 bd_prod
, u16 rx_comp_prod
, u16 rx_sge_prod
)
1723 u32 start
= BAR_USTRORM_INTMEM
+ fp
->ustorm_rx_prods_offset
;
1725 bnx2x_update_rx_prod_gen(bp
, fp
, bd_prod
, rx_comp_prod
, rx_sge_prod
,
1729 irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
)
1731 struct bnx2x
*bp
= netdev_priv(dev_instance
);
1732 u16 status
= bnx2x_ack_int(bp
);
1737 /* Return here if interrupt is shared and it's not for us */
1738 if (unlikely(status
== 0)) {
1739 DP(NETIF_MSG_INTR
, "not our interrupt!\n");
1742 DP(NETIF_MSG_INTR
, "got an interrupt status 0x%x\n", status
);
1744 #ifdef BNX2X_STOP_ON_ERROR
1745 if (unlikely(bp
->panic
))
1749 for_each_eth_queue(bp
, i
) {
1750 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1752 mask
= 0x2 << (fp
->index
+ CNIC_PRESENT
);
1753 if (status
& mask
) {
1754 /* Handle Rx or Tx according to SB id */
1755 prefetch(fp
->rx_cons_sb
);
1756 for_each_cos_in_tx_queue(fp
, cos
)
1757 prefetch(fp
->txdata
[cos
].tx_cons_sb
);
1758 prefetch(&fp
->sb_running_index
[SM_RX_ID
]);
1759 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
1766 if (status
& (mask
| 0x1)) {
1767 struct cnic_ops
*c_ops
= NULL
;
1769 if (likely(bp
->state
== BNX2X_STATE_OPEN
)) {
1771 c_ops
= rcu_dereference(bp
->cnic_ops
);
1773 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
1781 if (unlikely(status
& 0x1)) {
1782 queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
1789 if (unlikely(status
))
1790 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
1799 * General service functions
1802 int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
)
1805 u32 resource_bit
= (1 << resource
);
1806 int func
= BP_FUNC(bp
);
1807 u32 hw_lock_control_reg
;
1810 /* Validating that the resource is within range */
1811 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1812 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1813 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1818 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1820 hw_lock_control_reg
=
1821 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1824 /* Validating that the resource is not already taken */
1825 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1826 if (lock_status
& resource_bit
) {
1827 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
1828 lock_status
, resource_bit
);
1832 /* Try for 5 second every 5ms */
1833 for (cnt
= 0; cnt
< 1000; cnt
++) {
1834 /* Try to acquire the lock */
1835 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1836 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1837 if (lock_status
& resource_bit
)
1842 BNX2X_ERR("Timeout\n");
1846 int bnx2x_release_leader_lock(struct bnx2x
*bp
)
1848 return bnx2x_release_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1851 int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
)
1854 u32 resource_bit
= (1 << resource
);
1855 int func
= BP_FUNC(bp
);
1856 u32 hw_lock_control_reg
;
1858 /* Validating that the resource is within range */
1859 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1860 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1861 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1866 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1868 hw_lock_control_reg
=
1869 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1872 /* Validating that the resource is currently taken */
1873 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1874 if (!(lock_status
& resource_bit
)) {
1875 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. unlock was called but lock wasn't taken!\n",
1876 lock_status
, resource_bit
);
1880 REG_WR(bp
, hw_lock_control_reg
, resource_bit
);
1885 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
)
1887 /* The GPIO should be swapped if swap register is set and active */
1888 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
1889 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
1890 int gpio_shift
= gpio_num
+
1891 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
1892 u32 gpio_mask
= (1 << gpio_shift
);
1896 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
1897 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
1901 /* read GPIO value */
1902 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
1904 /* get the requested pin value */
1905 if ((gpio_reg
& gpio_mask
) == gpio_mask
)
1910 DP(NETIF_MSG_LINK
, "pin %d value 0x%x\n", gpio_num
, value
);
1915 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
1917 /* The GPIO should be swapped if swap register is set and active */
1918 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
1919 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
1920 int gpio_shift
= gpio_num
+
1921 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
1922 u32 gpio_mask
= (1 << gpio_shift
);
1925 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
1926 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
1930 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1931 /* read GPIO and mask except the float bits */
1932 gpio_reg
= (REG_RD(bp
, MISC_REG_GPIO
) & MISC_REGISTERS_GPIO_FLOAT
);
1935 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
1937 "Set GPIO %d (shift %d) -> output low\n",
1938 gpio_num
, gpio_shift
);
1939 /* clear FLOAT and set CLR */
1940 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1941 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_CLR_POS
);
1944 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
1946 "Set GPIO %d (shift %d) -> output high\n",
1947 gpio_num
, gpio_shift
);
1948 /* clear FLOAT and set SET */
1949 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1950 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_SET_POS
);
1953 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
1955 "Set GPIO %d (shift %d) -> input\n",
1956 gpio_num
, gpio_shift
);
1958 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1965 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
1966 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1971 int bnx2x_set_mult_gpio(struct bnx2x
*bp
, u8 pins
, u32 mode
)
1976 /* Any port swapping should be handled by caller. */
1978 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
1979 /* read GPIO and mask except the float bits */
1980 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
1981 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
1982 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
1983 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_SET_POS
);
1986 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
1987 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output low\n", pins
);
1989 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
1992 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
1993 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output high\n", pins
);
1995 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_SET_POS
);
1998 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
1999 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> input\n", pins
);
2001 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2005 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode
);
2011 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2013 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2018 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2020 /* The GPIO should be swapped if swap register is set and active */
2021 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2022 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2023 int gpio_shift
= gpio_num
+
2024 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2025 u32 gpio_mask
= (1 << gpio_shift
);
2028 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2029 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2033 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2035 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO_INT
);
2038 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
:
2040 "Clear GPIO INT %d (shift %d) -> output low\n",
2041 gpio_num
, gpio_shift
);
2042 /* clear SET and set CLR */
2043 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2044 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2047 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET
:
2049 "Set GPIO INT %d (shift %d) -> output high\n",
2050 gpio_num
, gpio_shift
);
2051 /* clear CLR and set SET */
2052 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2053 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2060 REG_WR(bp
, MISC_REG_GPIO_INT
, gpio_reg
);
2061 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2066 static int bnx2x_set_spio(struct bnx2x
*bp
, int spio_num
, u32 mode
)
2068 u32 spio_mask
= (1 << spio_num
);
2071 if ((spio_num
< MISC_REGISTERS_SPIO_4
) ||
2072 (spio_num
> MISC_REGISTERS_SPIO_7
)) {
2073 BNX2X_ERR("Invalid SPIO %d\n", spio_num
);
2077 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2078 /* read SPIO and mask except the float bits */
2079 spio_reg
= (REG_RD(bp
, MISC_REG_SPIO
) & MISC_REGISTERS_SPIO_FLOAT
);
2082 case MISC_REGISTERS_SPIO_OUTPUT_LOW
:
2083 DP(NETIF_MSG_HW
, "Set SPIO %d -> output low\n", spio_num
);
2084 /* clear FLOAT and set CLR */
2085 spio_reg
&= ~(spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
2086 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_CLR_POS
);
2089 case MISC_REGISTERS_SPIO_OUTPUT_HIGH
:
2090 DP(NETIF_MSG_HW
, "Set SPIO %d -> output high\n", spio_num
);
2091 /* clear FLOAT and set SET */
2092 spio_reg
&= ~(spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
2093 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_SET_POS
);
2096 case MISC_REGISTERS_SPIO_INPUT_HI_Z
:
2097 DP(NETIF_MSG_HW
, "Set SPIO %d -> input\n", spio_num
);
2099 spio_reg
|= (spio_mask
<< MISC_REGISTERS_SPIO_FLOAT_POS
);
2106 REG_WR(bp
, MISC_REG_SPIO
, spio_reg
);
2107 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2112 void bnx2x_calc_fc_adv(struct bnx2x
*bp
)
2114 u8 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
2115 switch (bp
->link_vars
.ieee_fc
&
2116 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) {
2117 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE
:
2118 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2122 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
:
2123 bp
->port
.advertising
[cfg_idx
] |= (ADVERTISED_Asym_Pause
|
2127 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
:
2128 bp
->port
.advertising
[cfg_idx
] |= ADVERTISED_Asym_Pause
;
2132 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2138 u8
bnx2x_initial_phy_init(struct bnx2x
*bp
, int load_mode
)
2140 if (!BP_NOMCP(bp
)) {
2142 int cfx_idx
= bnx2x_get_link_cfg_idx(bp
);
2143 u16 req_line_speed
= bp
->link_params
.req_line_speed
[cfx_idx
];
2145 * Initialize link parameters structure variables
2146 * It is recommended to turn off RX FC for jumbo frames
2147 * for better performance
2149 if (CHIP_IS_E1x(bp
) && (bp
->dev
->mtu
> 5000))
2150 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_TX
;
2152 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
2154 bnx2x_acquire_phy_lock(bp
);
2156 if (load_mode
== LOAD_DIAG
) {
2157 struct link_params
*lp
= &bp
->link_params
;
2158 lp
->loopback_mode
= LOOPBACK_XGXS
;
2159 /* do PHY loopback at 10G speed, if possible */
2160 if (lp
->req_line_speed
[cfx_idx
] < SPEED_10000
) {
2161 if (lp
->speed_cap_mask
[cfx_idx
] &
2162 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
2163 lp
->req_line_speed
[cfx_idx
] =
2166 lp
->req_line_speed
[cfx_idx
] =
2171 rc
= bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2173 bnx2x_release_phy_lock(bp
);
2175 bnx2x_calc_fc_adv(bp
);
2177 if (CHIP_REV_IS_SLOW(bp
) && bp
->link_vars
.link_up
) {
2178 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2179 bnx2x_link_report(bp
);
2181 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2182 bp
->link_params
.req_line_speed
[cfx_idx
] = req_line_speed
;
2185 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2189 void bnx2x_link_set(struct bnx2x
*bp
)
2191 if (!BP_NOMCP(bp
)) {
2192 bnx2x_acquire_phy_lock(bp
);
2193 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2194 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2195 bnx2x_release_phy_lock(bp
);
2197 bnx2x_calc_fc_adv(bp
);
2199 BNX2X_ERR("Bootcode is missing - can not set link\n");
2202 static void bnx2x__link_reset(struct bnx2x
*bp
)
2204 if (!BP_NOMCP(bp
)) {
2205 bnx2x_acquire_phy_lock(bp
);
2206 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2207 bnx2x_release_phy_lock(bp
);
2209 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2212 u8
bnx2x_link_test(struct bnx2x
*bp
, u8 is_serdes
)
2216 if (!BP_NOMCP(bp
)) {
2217 bnx2x_acquire_phy_lock(bp
);
2218 rc
= bnx2x_test_link(&bp
->link_params
, &bp
->link_vars
,
2220 bnx2x_release_phy_lock(bp
);
2222 BNX2X_ERR("Bootcode is missing - can not test link\n");
2227 static void bnx2x_init_port_minmax(struct bnx2x
*bp
)
2229 u32 r_param
= bp
->link_vars
.line_speed
/ 8;
2230 u32 fair_periodic_timeout_usec
;
2233 memset(&(bp
->cmng
.rs_vars
), 0,
2234 sizeof(struct rate_shaping_vars_per_port
));
2235 memset(&(bp
->cmng
.fair_vars
), 0, sizeof(struct fairness_vars_per_port
));
2237 /* 100 usec in SDM ticks = 25 since each tick is 4 usec */
2238 bp
->cmng
.rs_vars
.rs_periodic_timeout
= RS_PERIODIC_TIMEOUT_USEC
/ 4;
2240 /* this is the threshold below which no timer arming will occur
2241 1.25 coefficient is for the threshold to be a little bigger
2242 than the real time, to compensate for timer in-accuracy */
2243 bp
->cmng
.rs_vars
.rs_threshold
=
2244 (RS_PERIODIC_TIMEOUT_USEC
* r_param
* 5) / 4;
2246 /* resolution of fairness timer */
2247 fair_periodic_timeout_usec
= QM_ARB_BYTES
/ r_param
;
2248 /* for 10G it is 1000usec. for 1G it is 10000usec. */
2249 t_fair
= T_FAIR_COEF
/ bp
->link_vars
.line_speed
;
2251 /* this is the threshold below which we won't arm the timer anymore */
2252 bp
->cmng
.fair_vars
.fair_threshold
= QM_ARB_BYTES
;
2254 /* we multiply by 1e3/8 to get bytes/msec.
2255 We don't want the credits to pass a credit
2256 of the t_fair*FAIR_MEM (algorithm resolution) */
2257 bp
->cmng
.fair_vars
.upper_bound
= r_param
* t_fair
* FAIR_MEM
;
2258 /* since each tick is 4 usec */
2259 bp
->cmng
.fair_vars
.fairness_timeout
= fair_periodic_timeout_usec
/ 4;
2262 /* Calculates the sum of vn_min_rates.
2263 It's needed for further normalizing of the min_rates.
2265 sum of vn_min_rates.
2267 0 - if all the min_rates are 0.
2268 In the later case fainess algorithm should be deactivated.
2269 If not all min_rates are zero then those that are zeroes will be set to 1.
2271 static void bnx2x_calc_vn_weight_sum(struct bnx2x
*bp
)
2276 bp
->vn_weight_sum
= 0;
2277 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2278 u32 vn_cfg
= bp
->mf_config
[vn
];
2279 u32 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2280 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2282 /* Skip hidden vns */
2283 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2286 /* If min rate is zero - set it to 1 */
2288 vn_min_rate
= DEF_MIN_RATE
;
2292 bp
->vn_weight_sum
+= vn_min_rate
;
2295 /* if ETS or all min rates are zeros - disable fairness */
2296 if (BNX2X_IS_ETS_ENABLED(bp
)) {
2297 bp
->cmng
.flags
.cmng_enables
&=
2298 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2299 DP(NETIF_MSG_IFUP
, "Fairness will be disabled due to ETS\n");
2300 } else if (all_zero
) {
2301 bp
->cmng
.flags
.cmng_enables
&=
2302 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2303 DP(NETIF_MSG_IFUP
, "All MIN values are zeroes"
2304 " fairness will be disabled\n");
2306 bp
->cmng
.flags
.cmng_enables
|=
2307 CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2310 static void bnx2x_init_vn_minmax(struct bnx2x
*bp
, int vn
)
2312 struct rate_shaping_vars_per_vn m_rs_vn
;
2313 struct fairness_vars_per_vn m_fair_vn
;
2314 u32 vn_cfg
= bp
->mf_config
[vn
];
2315 int func
= func_by_vn(bp
, vn
);
2316 u16 vn_min_rate
, vn_max_rate
;
2319 /* If function is hidden - set min and max to zeroes */
2320 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
) {
2325 u32 maxCfg
= bnx2x_extract_max_cfg(bp
, vn_cfg
);
2327 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2328 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2329 /* If fairness is enabled (not all min rates are zeroes) and
2330 if current min rate is zero - set it to 1.
2331 This is a requirement of the algorithm. */
2332 if (bp
->vn_weight_sum
&& (vn_min_rate
== 0))
2333 vn_min_rate
= DEF_MIN_RATE
;
2336 /* maxCfg in percents of linkspeed */
2337 vn_max_rate
= (bp
->link_vars
.line_speed
* maxCfg
) / 100;
2339 /* maxCfg is absolute in 100Mb units */
2340 vn_max_rate
= maxCfg
* 100;
2344 "func %d: vn_min_rate %d vn_max_rate %d vn_weight_sum %d\n",
2345 func
, vn_min_rate
, vn_max_rate
, bp
->vn_weight_sum
);
2347 memset(&m_rs_vn
, 0, sizeof(struct rate_shaping_vars_per_vn
));
2348 memset(&m_fair_vn
, 0, sizeof(struct fairness_vars_per_vn
));
2350 /* global vn counter - maximal Mbps for this vn */
2351 m_rs_vn
.vn_counter
.rate
= vn_max_rate
;
2353 /* quota - number of bytes transmitted in this period */
2354 m_rs_vn
.vn_counter
.quota
=
2355 (vn_max_rate
* RS_PERIODIC_TIMEOUT_USEC
) / 8;
2357 if (bp
->vn_weight_sum
) {
2358 /* credit for each period of the fairness algorithm:
2359 number of bytes in T_FAIR (the vn share the port rate).
2360 vn_weight_sum should not be larger than 10000, thus
2361 T_FAIR_COEF / (8 * vn_weight_sum) will always be greater
2363 m_fair_vn
.vn_credit_delta
=
2364 max_t(u32
, (vn_min_rate
* (T_FAIR_COEF
/
2365 (8 * bp
->vn_weight_sum
))),
2366 (bp
->cmng
.fair_vars
.fair_threshold
+
2368 DP(NETIF_MSG_IFUP
, "m_fair_vn.vn_credit_delta %d\n",
2369 m_fair_vn
.vn_credit_delta
);
2372 /* Store it to internal memory */
2373 for (i
= 0; i
< sizeof(struct rate_shaping_vars_per_vn
)/4; i
++)
2374 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
2375 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func
) + i
* 4,
2376 ((u32
*)(&m_rs_vn
))[i
]);
2378 for (i
= 0; i
< sizeof(struct fairness_vars_per_vn
)/4; i
++)
2379 REG_WR(bp
, BAR_XSTRORM_INTMEM
+
2380 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func
) + i
* 4,
2381 ((u32
*)(&m_fair_vn
))[i
]);
2384 static int bnx2x_get_cmng_fns_mode(struct bnx2x
*bp
)
2386 if (CHIP_REV_IS_SLOW(bp
))
2387 return CMNG_FNS_NONE
;
2389 return CMNG_FNS_MINMAX
;
2391 return CMNG_FNS_NONE
;
2394 void bnx2x_read_mf_cfg(struct bnx2x
*bp
)
2396 int vn
, n
= (CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1);
2399 return; /* what should be the default bvalue in this case */
2401 /* For 2 port configuration the absolute function number formula
2403 * abs_func = 2 * vn + BP_PORT + BP_PATH
2405 * and there are 4 functions per port
2407 * For 4 port configuration it is
2408 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2410 * and there are 2 functions per port
2412 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2413 int /*abs*/func
= n
* (2 * vn
+ BP_PORT(bp
)) + BP_PATH(bp
);
2415 if (func
>= E1H_FUNC_MAX
)
2419 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2423 static void bnx2x_cmng_fns_init(struct bnx2x
*bp
, u8 read_cfg
, u8 cmng_type
)
2426 if (cmng_type
== CMNG_FNS_MINMAX
) {
2429 /* clear cmng_enables */
2430 bp
->cmng
.flags
.cmng_enables
= 0;
2432 /* read mf conf from shmem */
2434 bnx2x_read_mf_cfg(bp
);
2436 /* Init rate shaping and fairness contexts */
2437 bnx2x_init_port_minmax(bp
);
2439 /* vn_weight_sum and enable fairness if not 0 */
2440 bnx2x_calc_vn_weight_sum(bp
);
2442 /* calculate and set min-max rate for each vn */
2444 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++)
2445 bnx2x_init_vn_minmax(bp
, vn
);
2447 /* always enable rate shaping and fairness */
2448 bp
->cmng
.flags
.cmng_enables
|=
2449 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN
;
2450 if (!bp
->vn_weight_sum
)
2451 DP(NETIF_MSG_IFUP
, "All MIN values are zeroes"
2452 " fairness will be disabled\n");
2456 /* rate shaping and fairness are disabled */
2458 "rate shaping and fairness are disabled\n");
2461 /* This function is called upon link interrupt */
2462 static void bnx2x_link_attn(struct bnx2x
*bp
)
2464 /* Make sure that we are synced with the current statistics */
2465 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2467 bnx2x_link_update(&bp
->link_params
, &bp
->link_vars
);
2469 if (bp
->link_vars
.link_up
) {
2471 /* dropless flow control */
2472 if (!CHIP_IS_E1(bp
) && bp
->dropless_fc
) {
2473 int port
= BP_PORT(bp
);
2474 u32 pause_enabled
= 0;
2476 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
2479 REG_WR(bp
, BAR_USTRORM_INTMEM
+
2480 USTORM_ETH_PAUSE_ENABLED_OFFSET(port
),
2484 if (bp
->link_vars
.mac_type
!= MAC_TYPE_EMAC
) {
2485 struct host_port_stats
*pstats
;
2487 pstats
= bnx2x_sp(bp
, port_stats
);
2488 /* reset old mac stats */
2489 memset(&(pstats
->mac_stx
[0]), 0,
2490 sizeof(struct mac_stx
));
2492 if (bp
->state
== BNX2X_STATE_OPEN
)
2493 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2496 if (bp
->link_vars
.link_up
&& bp
->link_vars
.line_speed
) {
2497 int cmng_fns
= bnx2x_get_cmng_fns_mode(bp
);
2499 if (cmng_fns
!= CMNG_FNS_NONE
) {
2500 bnx2x_cmng_fns_init(bp
, false, cmng_fns
);
2501 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2503 /* rate shaping and fairness are disabled */
2505 "single function mode without fairness\n");
2508 __bnx2x_link_report(bp
);
2511 bnx2x_link_sync_notify(bp
);
2514 void bnx2x__link_status_update(struct bnx2x
*bp
)
2516 if (bp
->state
!= BNX2X_STATE_OPEN
)
2519 /* read updated dcb configuration */
2520 bnx2x_dcbx_pmf_update(bp
);
2522 bnx2x_link_status_update(&bp
->link_params
, &bp
->link_vars
);
2524 if (bp
->link_vars
.link_up
)
2525 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2527 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2529 /* indicate link status */
2530 bnx2x_link_report(bp
);
2533 static void bnx2x_pmf_update(struct bnx2x
*bp
)
2535 int port
= BP_PORT(bp
);
2539 DP(BNX2X_MSG_MCP
, "pmf %d\n", bp
->port
.pmf
);
2542 * We need the mb() to ensure the ordering between the writing to
2543 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2547 /* queue a periodic task */
2548 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2550 bnx2x_dcbx_pmf_update(bp
);
2552 /* enable nig attention */
2553 val
= (0xff0f | (1 << (BP_VN(bp
) + 4)));
2554 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
2555 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
2556 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
2557 } else if (!CHIP_IS_E1x(bp
)) {
2558 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
2559 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
2562 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
2570 * General service functions
2573 /* send the MCP a request, block until there is a reply */
2574 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
)
2576 int mb_idx
= BP_FW_MB_IDX(bp
);
2580 u8 delay
= CHIP_REV_IS_SLOW(bp
) ? 100 : 10;
2582 mutex_lock(&bp
->fw_mb_mutex
);
2584 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_param
, param
);
2585 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_header
, (command
| seq
));
2587 DP(BNX2X_MSG_MCP
, "wrote command (%x) to FW MB param 0x%08x\n",
2588 (command
| seq
), param
);
2591 /* let the FW do it's magic ... */
2594 rc
= SHMEM_RD(bp
, func_mb
[mb_idx
].fw_mb_header
);
2596 /* Give the FW up to 5 second (500*10ms) */
2597 } while ((seq
!= (rc
& FW_MSG_SEQ_NUMBER_MASK
)) && (cnt
++ < 500));
2599 DP(BNX2X_MSG_MCP
, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
2600 cnt
*delay
, rc
, seq
);
2602 /* is this a reply to our command? */
2603 if (seq
== (rc
& FW_MSG_SEQ_NUMBER_MASK
))
2604 rc
&= FW_MSG_CODE_MASK
;
2607 BNX2X_ERR("FW failed to respond!\n");
2611 mutex_unlock(&bp
->fw_mb_mutex
);
2617 void bnx2x_func_init(struct bnx2x
*bp
, struct bnx2x_func_init_params
*p
)
2619 if (CHIP_IS_E1x(bp
)) {
2620 struct tstorm_eth_function_common_config tcfg
= {0};
2622 storm_memset_func_cfg(bp
, &tcfg
, p
->func_id
);
2625 /* Enable the function in the FW */
2626 storm_memset_vf_to_pf(bp
, p
->func_id
, p
->pf_id
);
2627 storm_memset_func_en(bp
, p
->func_id
, 1);
2630 if (p
->func_flgs
& FUNC_FLG_SPQ
) {
2631 storm_memset_spq_addr(bp
, p
->spq_map
, p
->func_id
);
2632 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+
2633 XSTORM_SPQ_PROD_OFFSET(p
->func_id
), p
->spq_prod
);
2638 * bnx2x_get_tx_only_flags - Return common flags
2642 * @zero_stats TRUE if statistics zeroing is needed
2644 * Return the flags that are common for the Tx-only and not normal connections.
2646 static inline unsigned long bnx2x_get_common_flags(struct bnx2x
*bp
,
2647 struct bnx2x_fastpath
*fp
,
2650 unsigned long flags
= 0;
2652 /* PF driver will always initialize the Queue to an ACTIVE state */
2653 __set_bit(BNX2X_Q_FLG_ACTIVE
, &flags
);
2655 /* tx only connections collect statistics (on the same index as the
2656 * parent connection). The statistics are zeroed when the parent
2657 * connection is initialized.
2660 __set_bit(BNX2X_Q_FLG_STATS
, &flags
);
2662 __set_bit(BNX2X_Q_FLG_ZERO_STATS
, &flags
);
2668 static inline unsigned long bnx2x_get_q_flags(struct bnx2x
*bp
,
2669 struct bnx2x_fastpath
*fp
,
2672 unsigned long flags
= 0;
2674 /* calculate other queue flags */
2676 __set_bit(BNX2X_Q_FLG_OV
, &flags
);
2679 __set_bit(BNX2X_Q_FLG_FCOE
, &flags
);
2681 if (!fp
->disable_tpa
) {
2682 __set_bit(BNX2X_Q_FLG_TPA
, &flags
);
2683 __set_bit(BNX2X_Q_FLG_TPA_IPV6
, &flags
);
2684 if (fp
->mode
== TPA_MODE_GRO
)
2685 __set_bit(BNX2X_Q_FLG_TPA_GRO
, &flags
);
2689 __set_bit(BNX2X_Q_FLG_LEADING_RSS
, &flags
);
2690 __set_bit(BNX2X_Q_FLG_MCAST
, &flags
);
2693 /* Always set HW VLAN stripping */
2694 __set_bit(BNX2X_Q_FLG_VLAN
, &flags
);
2697 return flags
| bnx2x_get_common_flags(bp
, fp
, true);
2700 static void bnx2x_pf_q_prep_general(struct bnx2x
*bp
,
2701 struct bnx2x_fastpath
*fp
, struct bnx2x_general_setup_params
*gen_init
,
2704 gen_init
->stat_id
= bnx2x_stats_id(fp
);
2705 gen_init
->spcl_id
= fp
->cl_id
;
2707 /* Always use mini-jumbo MTU for FCoE L2 ring */
2709 gen_init
->mtu
= BNX2X_FCOE_MINI_JUMBO_MTU
;
2711 gen_init
->mtu
= bp
->dev
->mtu
;
2713 gen_init
->cos
= cos
;
2716 static void bnx2x_pf_rx_q_prep(struct bnx2x
*bp
,
2717 struct bnx2x_fastpath
*fp
, struct rxq_pause_params
*pause
,
2718 struct bnx2x_rxq_setup_params
*rxq_init
)
2722 u16 tpa_agg_size
= 0;
2724 if (!fp
->disable_tpa
) {
2725 pause
->sge_th_lo
= SGE_TH_LO(bp
);
2726 pause
->sge_th_hi
= SGE_TH_HI(bp
);
2728 /* validate SGE ring has enough to cross high threshold */
2729 WARN_ON(bp
->dropless_fc
&&
2730 pause
->sge_th_hi
+ FW_PREFETCH_CNT
>
2731 MAX_RX_SGE_CNT
* NUM_RX_SGE_PAGES
);
2733 tpa_agg_size
= min_t(u32
,
2734 (min_t(u32
, 8, MAX_SKB_FRAGS
) *
2735 SGE_PAGE_SIZE
* PAGES_PER_SGE
), 0xffff);
2736 max_sge
= SGE_PAGE_ALIGN(bp
->dev
->mtu
) >>
2738 max_sge
= ((max_sge
+ PAGES_PER_SGE
- 1) &
2739 (~(PAGES_PER_SGE
-1))) >> PAGES_PER_SGE_SHIFT
;
2740 sge_sz
= (u16
)min_t(u32
, SGE_PAGE_SIZE
* PAGES_PER_SGE
,
2744 /* pause - not for e1 */
2745 if (!CHIP_IS_E1(bp
)) {
2746 pause
->bd_th_lo
= BD_TH_LO(bp
);
2747 pause
->bd_th_hi
= BD_TH_HI(bp
);
2749 pause
->rcq_th_lo
= RCQ_TH_LO(bp
);
2750 pause
->rcq_th_hi
= RCQ_TH_HI(bp
);
2752 * validate that rings have enough entries to cross
2755 WARN_ON(bp
->dropless_fc
&&
2756 pause
->bd_th_hi
+ FW_PREFETCH_CNT
>
2758 WARN_ON(bp
->dropless_fc
&&
2759 pause
->rcq_th_hi
+ FW_PREFETCH_CNT
>
2760 NUM_RCQ_RINGS
* MAX_RCQ_DESC_CNT
);
2766 rxq_init
->dscr_map
= fp
->rx_desc_mapping
;
2767 rxq_init
->sge_map
= fp
->rx_sge_mapping
;
2768 rxq_init
->rcq_map
= fp
->rx_comp_mapping
;
2769 rxq_init
->rcq_np_map
= fp
->rx_comp_mapping
+ BCM_PAGE_SIZE
;
2771 /* This should be a maximum number of data bytes that may be
2772 * placed on the BD (not including paddings).
2774 rxq_init
->buf_sz
= fp
->rx_buf_size
- BNX2X_FW_RX_ALIGN_START
-
2775 BNX2X_FW_RX_ALIGN_END
- IP_HEADER_ALIGNMENT_PADDING
;
2777 rxq_init
->cl_qzone_id
= fp
->cl_qzone_id
;
2778 rxq_init
->tpa_agg_sz
= tpa_agg_size
;
2779 rxq_init
->sge_buf_sz
= sge_sz
;
2780 rxq_init
->max_sges_pkt
= max_sge
;
2781 rxq_init
->rss_engine_id
= BP_FUNC(bp
);
2782 rxq_init
->mcast_engine_id
= BP_FUNC(bp
);
2784 /* Maximum number or simultaneous TPA aggregation for this Queue.
2786 * For PF Clients it should be the maximum avaliable number.
2787 * VF driver(s) may want to define it to a smaller value.
2789 rxq_init
->max_tpa_queues
= MAX_AGG_QS(bp
);
2791 rxq_init
->cache_line_log
= BNX2X_RX_ALIGN_SHIFT
;
2792 rxq_init
->fw_sb_id
= fp
->fw_sb_id
;
2795 rxq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS
;
2797 rxq_init
->sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
2800 static void bnx2x_pf_tx_q_prep(struct bnx2x
*bp
,
2801 struct bnx2x_fastpath
*fp
, struct bnx2x_txq_setup_params
*txq_init
,
2804 txq_init
->dscr_map
= fp
->txdata
[cos
].tx_desc_mapping
;
2805 txq_init
->sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
+ cos
;
2806 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_NW
;
2807 txq_init
->fw_sb_id
= fp
->fw_sb_id
;
2810 * set the tss leading client id for TX classfication ==
2811 * leading RSS client id
2813 txq_init
->tss_leading_cl_id
= bnx2x_fp(bp
, 0, cl_id
);
2815 if (IS_FCOE_FP(fp
)) {
2816 txq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS
;
2817 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_FCOE
;
2821 static void bnx2x_pf_init(struct bnx2x
*bp
)
2823 struct bnx2x_func_init_params func_init
= {0};
2824 struct event_ring_data eq_data
= { {0} };
2827 if (!CHIP_IS_E1x(bp
)) {
2828 /* reset IGU PF statistics: MSIX + ATTN */
2830 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
2831 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
2832 (CHIP_MODE_IS_4_PORT(bp
) ?
2833 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
2835 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
2836 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
2837 BNX2X_IGU_STAS_MSG_PF_CNT
*4 +
2838 (CHIP_MODE_IS_4_PORT(bp
) ?
2839 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
2842 /* function setup flags */
2843 flags
= (FUNC_FLG_STATS
| FUNC_FLG_LEADING
| FUNC_FLG_SPQ
);
2845 /* This flag is relevant for E1x only.
2846 * E2 doesn't have a TPA configuration in a function level.
2848 flags
|= (bp
->flags
& TPA_ENABLE_FLAG
) ? FUNC_FLG_TPA
: 0;
2850 func_init
.func_flgs
= flags
;
2851 func_init
.pf_id
= BP_FUNC(bp
);
2852 func_init
.func_id
= BP_FUNC(bp
);
2853 func_init
.spq_map
= bp
->spq_mapping
;
2854 func_init
.spq_prod
= bp
->spq_prod_idx
;
2856 bnx2x_func_init(bp
, &func_init
);
2858 memset(&(bp
->cmng
), 0, sizeof(struct cmng_struct_per_port
));
2861 * Congestion management values depend on the link rate
2862 * There is no active link so initial link rate is set to 10 Gbps.
2863 * When the link comes up The congestion management values are
2864 * re-calculated according to the actual link rate.
2866 bp
->link_vars
.line_speed
= SPEED_10000
;
2867 bnx2x_cmng_fns_init(bp
, true, bnx2x_get_cmng_fns_mode(bp
));
2869 /* Only the PMF sets the HW */
2871 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2873 /* init Event Queue */
2874 eq_data
.base_addr
.hi
= U64_HI(bp
->eq_mapping
);
2875 eq_data
.base_addr
.lo
= U64_LO(bp
->eq_mapping
);
2876 eq_data
.producer
= bp
->eq_prod
;
2877 eq_data
.index_id
= HC_SP_INDEX_EQ_CONS
;
2878 eq_data
.sb_id
= DEF_SB_ID
;
2879 storm_memset_eq_data(bp
, &eq_data
, BP_FUNC(bp
));
2883 static void bnx2x_e1h_disable(struct bnx2x
*bp
)
2885 int port
= BP_PORT(bp
);
2887 bnx2x_tx_disable(bp
);
2889 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
2892 static void bnx2x_e1h_enable(struct bnx2x
*bp
)
2894 int port
= BP_PORT(bp
);
2896 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
2898 /* Tx queue should be only reenabled */
2899 netif_tx_wake_all_queues(bp
->dev
);
2902 * Should not call netif_carrier_on since it will be called if the link
2903 * is up when checking for link state
2907 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
2909 static void bnx2x_drv_info_ether_stat(struct bnx2x
*bp
)
2911 struct eth_stats_info
*ether_stat
=
2912 &bp
->slowpath
->drv_info_to_mcp
.ether_stat
;
2914 /* leave last char as NULL */
2915 memcpy(ether_stat
->version
, DRV_MODULE_VERSION
,
2916 ETH_STAT_INFO_VERSION_LEN
- 1);
2918 bp
->fp
[0].mac_obj
.get_n_elements(bp
, &bp
->fp
[0].mac_obj
,
2919 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
,
2920 ether_stat
->mac_local
);
2922 ether_stat
->mtu_size
= bp
->dev
->mtu
;
2924 if (bp
->dev
->features
& NETIF_F_RXCSUM
)
2925 ether_stat
->feature_flags
|= FEATURE_ETH_CHKSUM_OFFLOAD_MASK
;
2926 if (bp
->dev
->features
& NETIF_F_TSO
)
2927 ether_stat
->feature_flags
|= FEATURE_ETH_LSO_MASK
;
2928 ether_stat
->feature_flags
|= bp
->common
.boot_mode
;
2930 ether_stat
->promiscuous_mode
= (bp
->dev
->flags
& IFF_PROMISC
) ? 1 : 0;
2932 ether_stat
->txq_size
= bp
->tx_ring_size
;
2933 ether_stat
->rxq_size
= bp
->rx_ring_size
;
2936 static void bnx2x_drv_info_fcoe_stat(struct bnx2x
*bp
)
2939 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
2940 struct fcoe_stats_info
*fcoe_stat
=
2941 &bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
;
2943 memcpy(fcoe_stat
->mac_local
, bp
->fip_mac
, ETH_ALEN
);
2945 fcoe_stat
->qos_priority
=
2946 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_FCOE
];
2948 /* insert FCoE stats from ramrod response */
2950 struct tstorm_per_queue_stats
*fcoe_q_tstorm_stats
=
2951 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX
].
2952 tstorm_queue_statistics
;
2954 struct xstorm_per_queue_stats
*fcoe_q_xstorm_stats
=
2955 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX
].
2956 xstorm_queue_statistics
;
2958 struct fcoe_statistics_params
*fw_fcoe_stat
=
2959 &bp
->fw_stats_data
->fcoe
;
2961 ADD_64(fcoe_stat
->rx_bytes_hi
, 0, fcoe_stat
->rx_bytes_lo
,
2962 fw_fcoe_stat
->rx_stat0
.fcoe_rx_byte_cnt
);
2964 ADD_64(fcoe_stat
->rx_bytes_hi
,
2965 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.hi
,
2966 fcoe_stat
->rx_bytes_lo
,
2967 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.lo
);
2969 ADD_64(fcoe_stat
->rx_bytes_hi
,
2970 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.hi
,
2971 fcoe_stat
->rx_bytes_lo
,
2972 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.lo
);
2974 ADD_64(fcoe_stat
->rx_bytes_hi
,
2975 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.hi
,
2976 fcoe_stat
->rx_bytes_lo
,
2977 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.lo
);
2979 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
2980 fw_fcoe_stat
->rx_stat0
.fcoe_rx_pkt_cnt
);
2982 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
2983 fcoe_q_tstorm_stats
->rcv_ucast_pkts
);
2985 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
2986 fcoe_q_tstorm_stats
->rcv_bcast_pkts
);
2988 ADD_64(fcoe_stat
->rx_frames_hi
, 0, fcoe_stat
->rx_frames_lo
,
2989 fcoe_q_tstorm_stats
->rcv_mcast_pkts
);
2991 ADD_64(fcoe_stat
->tx_bytes_hi
, 0, fcoe_stat
->tx_bytes_lo
,
2992 fw_fcoe_stat
->tx_stat
.fcoe_tx_byte_cnt
);
2994 ADD_64(fcoe_stat
->tx_bytes_hi
,
2995 fcoe_q_xstorm_stats
->ucast_bytes_sent
.hi
,
2996 fcoe_stat
->tx_bytes_lo
,
2997 fcoe_q_xstorm_stats
->ucast_bytes_sent
.lo
);
2999 ADD_64(fcoe_stat
->tx_bytes_hi
,
3000 fcoe_q_xstorm_stats
->bcast_bytes_sent
.hi
,
3001 fcoe_stat
->tx_bytes_lo
,
3002 fcoe_q_xstorm_stats
->bcast_bytes_sent
.lo
);
3004 ADD_64(fcoe_stat
->tx_bytes_hi
,
3005 fcoe_q_xstorm_stats
->mcast_bytes_sent
.hi
,
3006 fcoe_stat
->tx_bytes_lo
,
3007 fcoe_q_xstorm_stats
->mcast_bytes_sent
.lo
);
3009 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3010 fw_fcoe_stat
->tx_stat
.fcoe_tx_pkt_cnt
);
3012 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3013 fcoe_q_xstorm_stats
->ucast_pkts_sent
);
3015 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3016 fcoe_q_xstorm_stats
->bcast_pkts_sent
);
3018 ADD_64(fcoe_stat
->tx_frames_hi
, 0, fcoe_stat
->tx_frames_lo
,
3019 fcoe_q_xstorm_stats
->mcast_pkts_sent
);
3022 /* ask L5 driver to add data to the struct */
3023 bnx2x_cnic_notify(bp
, CNIC_CTL_FCOE_STATS_GET_CMD
);
3027 static void bnx2x_drv_info_iscsi_stat(struct bnx2x
*bp
)
3030 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3031 struct iscsi_stats_info
*iscsi_stat
=
3032 &bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
;
3034 memcpy(iscsi_stat
->mac_local
, bp
->cnic_eth_dev
.iscsi_mac
, ETH_ALEN
);
3036 iscsi_stat
->qos_priority
=
3037 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_ISCSI
];
3039 /* ask L5 driver to add data to the struct */
3040 bnx2x_cnic_notify(bp
, CNIC_CTL_ISCSI_STATS_GET_CMD
);
3044 /* called due to MCP event (on pmf):
3045 * reread new bandwidth configuration
3047 * notify others function about the change
3049 static inline void bnx2x_config_mf_bw(struct bnx2x
*bp
)
3051 if (bp
->link_vars
.link_up
) {
3052 bnx2x_cmng_fns_init(bp
, true, CMNG_FNS_MINMAX
);
3053 bnx2x_link_sync_notify(bp
);
3055 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3058 static inline void bnx2x_set_mf_bw(struct bnx2x
*bp
)
3060 bnx2x_config_mf_bw(bp
);
3061 bnx2x_fw_command(bp
, DRV_MSG_CODE_SET_MF_BW_ACK
, 0);
3064 static void bnx2x_handle_drv_info_req(struct bnx2x
*bp
)
3066 enum drv_info_opcode op_code
;
3067 u32 drv_info_ctl
= SHMEM2_RD(bp
, drv_info_control
);
3069 /* if drv_info version supported by MFW doesn't match - send NACK */
3070 if ((drv_info_ctl
& DRV_INFO_CONTROL_VER_MASK
) != DRV_INFO_CUR_VER
) {
3071 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3075 op_code
= (drv_info_ctl
& DRV_INFO_CONTROL_OP_CODE_MASK
) >>
3076 DRV_INFO_CONTROL_OP_CODE_SHIFT
;
3078 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3079 sizeof(union drv_info_to_mcp
));
3082 case ETH_STATS_OPCODE
:
3083 bnx2x_drv_info_ether_stat(bp
);
3085 case FCOE_STATS_OPCODE
:
3086 bnx2x_drv_info_fcoe_stat(bp
);
3088 case ISCSI_STATS_OPCODE
:
3089 bnx2x_drv_info_iscsi_stat(bp
);
3092 /* if op code isn't supported - send NACK */
3093 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3097 /* if we got drv_info attn from MFW then these fields are defined in
3100 SHMEM2_WR(bp
, drv_info_host_addr_lo
,
3101 U64_LO(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3102 SHMEM2_WR(bp
, drv_info_host_addr_hi
,
3103 U64_HI(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3105 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_ACK
, 0);
3108 static void bnx2x_dcc_event(struct bnx2x
*bp
, u32 dcc_event
)
3110 DP(BNX2X_MSG_MCP
, "dcc_event 0x%x\n", dcc_event
);
3112 if (dcc_event
& DRV_STATUS_DCC_DISABLE_ENABLE_PF
) {
3115 * This is the only place besides the function initialization
3116 * where the bp->flags can change so it is done without any
3119 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
3120 DP(BNX2X_MSG_MCP
, "mf_cfg function disabled\n");
3121 bp
->flags
|= MF_FUNC_DIS
;
3123 bnx2x_e1h_disable(bp
);
3125 DP(BNX2X_MSG_MCP
, "mf_cfg function enabled\n");
3126 bp
->flags
&= ~MF_FUNC_DIS
;
3128 bnx2x_e1h_enable(bp
);
3130 dcc_event
&= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF
;
3132 if (dcc_event
& DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
) {
3133 bnx2x_config_mf_bw(bp
);
3134 dcc_event
&= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
;
3137 /* Report results to MCP */
3139 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_FAILURE
, 0);
3141 bnx2x_fw_command(bp
, DRV_MSG_CODE_DCC_OK
, 0);
3144 /* must be called under the spq lock */
3145 static inline struct eth_spe
*bnx2x_sp_get_next(struct bnx2x
*bp
)
3147 struct eth_spe
*next_spe
= bp
->spq_prod_bd
;
3149 if (bp
->spq_prod_bd
== bp
->spq_last_bd
) {
3150 bp
->spq_prod_bd
= bp
->spq
;
3151 bp
->spq_prod_idx
= 0;
3152 DP(BNX2X_MSG_SP
, "end of spq\n");
3160 /* must be called under the spq lock */
3161 static inline void bnx2x_sp_prod_update(struct bnx2x
*bp
)
3163 int func
= BP_FUNC(bp
);
3166 * Make sure that BD data is updated before writing the producer:
3167 * BD data is written to the memory, the producer is read from the
3168 * memory, thus we need a full memory barrier to ensure the ordering.
3172 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_PROD_OFFSET(func
),
3178 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3180 * @cmd: command to check
3181 * @cmd_type: command type
3183 static inline bool bnx2x_is_contextless_ramrod(int cmd
, int cmd_type
)
3185 if ((cmd_type
== NONE_CONNECTION_TYPE
) ||
3186 (cmd
== RAMROD_CMD_ID_ETH_FORWARD_SETUP
) ||
3187 (cmd
== RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
) ||
3188 (cmd
== RAMROD_CMD_ID_ETH_FILTER_RULES
) ||
3189 (cmd
== RAMROD_CMD_ID_ETH_MULTICAST_RULES
) ||
3190 (cmd
== RAMROD_CMD_ID_ETH_SET_MAC
) ||
3191 (cmd
== RAMROD_CMD_ID_ETH_RSS_UPDATE
))
3200 * bnx2x_sp_post - place a single command on an SP ring
3202 * @bp: driver handle
3203 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3204 * @cid: SW CID the command is related to
3205 * @data_hi: command private data address (high 32 bits)
3206 * @data_lo: command private data address (low 32 bits)
3207 * @cmd_type: command type (e.g. NONE, ETH)
3209 * SP data is handled as if it's always an address pair, thus data fields are
3210 * not swapped to little endian in upper functions. Instead this function swaps
3211 * data as if it's two u32 fields.
3213 int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
3214 u32 data_hi
, u32 data_lo
, int cmd_type
)
3216 struct eth_spe
*spe
;
3218 bool common
= bnx2x_is_contextless_ramrod(command
, cmd_type
);
3220 #ifdef BNX2X_STOP_ON_ERROR
3221 if (unlikely(bp
->panic
)) {
3222 BNX2X_ERR("Can't post SP when there is panic\n");
3227 spin_lock_bh(&bp
->spq_lock
);
3230 if (!atomic_read(&bp
->eq_spq_left
)) {
3231 BNX2X_ERR("BUG! EQ ring full!\n");
3232 spin_unlock_bh(&bp
->spq_lock
);
3236 } else if (!atomic_read(&bp
->cq_spq_left
)) {
3237 BNX2X_ERR("BUG! SPQ ring full!\n");
3238 spin_unlock_bh(&bp
->spq_lock
);
3243 spe
= bnx2x_sp_get_next(bp
);
3245 /* CID needs port number to be encoded int it */
3246 spe
->hdr
.conn_and_cmd_data
=
3247 cpu_to_le32((command
<< SPE_HDR_CMD_ID_SHIFT
) |
3250 type
= (cmd_type
<< SPE_HDR_CONN_TYPE_SHIFT
) & SPE_HDR_CONN_TYPE
;
3252 type
|= ((BP_FUNC(bp
) << SPE_HDR_FUNCTION_ID_SHIFT
) &
3253 SPE_HDR_FUNCTION_ID
);
3255 spe
->hdr
.type
= cpu_to_le16(type
);
3257 spe
->data
.update_data_addr
.hi
= cpu_to_le32(data_hi
);
3258 spe
->data
.update_data_addr
.lo
= cpu_to_le32(data_lo
);
3261 * It's ok if the actual decrement is issued towards the memory
3262 * somewhere between the spin_lock and spin_unlock. Thus no
3263 * more explict memory barrier is needed.
3266 atomic_dec(&bp
->eq_spq_left
);
3268 atomic_dec(&bp
->cq_spq_left
);
3272 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3273 bp
->spq_prod_idx
, (u32
)U64_HI(bp
->spq_mapping
),
3274 (u32
)(U64_LO(bp
->spq_mapping
) +
3275 (void *)bp
->spq_prod_bd
- (void *)bp
->spq
), command
, common
,
3276 HW_CID(bp
, cid
), data_hi
, data_lo
, type
,
3277 atomic_read(&bp
->cq_spq_left
), atomic_read(&bp
->eq_spq_left
));
3279 bnx2x_sp_prod_update(bp
);
3280 spin_unlock_bh(&bp
->spq_lock
);
3284 /* acquire split MCP access lock register */
3285 static int bnx2x_acquire_alr(struct bnx2x
*bp
)
3291 for (j
= 0; j
< 1000; j
++) {
3293 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, val
);
3294 val
= REG_RD(bp
, GRCBASE_MCP
+ 0x9c);
3295 if (val
& (1L << 31))
3300 if (!(val
& (1L << 31))) {
3301 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3308 /* release split MCP access lock register */
3309 static void bnx2x_release_alr(struct bnx2x
*bp
)
3311 REG_WR(bp
, GRCBASE_MCP
+ 0x9c, 0);
3314 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3315 #define BNX2X_DEF_SB_IDX 0x0002
3317 static inline u16
bnx2x_update_dsb_idx(struct bnx2x
*bp
)
3319 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
3322 barrier(); /* status block is written to by the chip */
3323 if (bp
->def_att_idx
!= def_sb
->atten_status_block
.attn_bits_index
) {
3324 bp
->def_att_idx
= def_sb
->atten_status_block
.attn_bits_index
;
3325 rc
|= BNX2X_DEF_SB_ATT_IDX
;
3328 if (bp
->def_idx
!= def_sb
->sp_sb
.running_index
) {
3329 bp
->def_idx
= def_sb
->sp_sb
.running_index
;
3330 rc
|= BNX2X_DEF_SB_IDX
;
3333 /* Do not reorder: indecies reading should complete before handling */
3339 * slow path service functions
3342 static void bnx2x_attn_int_asserted(struct bnx2x
*bp
, u32 asserted
)
3344 int port
= BP_PORT(bp
);
3345 u32 aeu_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
3346 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
3347 u32 nig_int_mask_addr
= port
? NIG_REG_MASK_INTERRUPT_PORT1
:
3348 NIG_REG_MASK_INTERRUPT_PORT0
;
3353 if (bp
->attn_state
& asserted
)
3354 BNX2X_ERR("IGU ERROR\n");
3356 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3357 aeu_mask
= REG_RD(bp
, aeu_addr
);
3359 DP(NETIF_MSG_HW
, "aeu_mask %x newly asserted %x\n",
3360 aeu_mask
, asserted
);
3361 aeu_mask
&= ~(asserted
& 0x3ff);
3362 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
3364 REG_WR(bp
, aeu_addr
, aeu_mask
);
3365 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
3367 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
3368 bp
->attn_state
|= asserted
;
3369 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
3371 if (asserted
& ATTN_HARD_WIRED_MASK
) {
3372 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3374 bnx2x_acquire_phy_lock(bp
);
3376 /* save nig interrupt mask */
3377 nig_mask
= REG_RD(bp
, nig_int_mask_addr
);
3379 /* If nig_mask is not set, no need to call the update
3383 REG_WR(bp
, nig_int_mask_addr
, 0);
3385 bnx2x_link_attn(bp
);
3388 /* handle unicore attn? */
3390 if (asserted
& ATTN_SW_TIMER_4_FUNC
)
3391 DP(NETIF_MSG_HW
, "ATTN_SW_TIMER_4_FUNC!\n");
3393 if (asserted
& GPIO_2_FUNC
)
3394 DP(NETIF_MSG_HW
, "GPIO_2_FUNC!\n");
3396 if (asserted
& GPIO_3_FUNC
)
3397 DP(NETIF_MSG_HW
, "GPIO_3_FUNC!\n");
3399 if (asserted
& GPIO_4_FUNC
)
3400 DP(NETIF_MSG_HW
, "GPIO_4_FUNC!\n");
3403 if (asserted
& ATTN_GENERAL_ATTN_1
) {
3404 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_1!\n");
3405 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_1
, 0x0);
3407 if (asserted
& ATTN_GENERAL_ATTN_2
) {
3408 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_2!\n");
3409 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_2
, 0x0);
3411 if (asserted
& ATTN_GENERAL_ATTN_3
) {
3412 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_3!\n");
3413 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_3
, 0x0);
3416 if (asserted
& ATTN_GENERAL_ATTN_4
) {
3417 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_4!\n");
3418 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_4
, 0x0);
3420 if (asserted
& ATTN_GENERAL_ATTN_5
) {
3421 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_5!\n");
3422 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_5
, 0x0);
3424 if (asserted
& ATTN_GENERAL_ATTN_6
) {
3425 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_6!\n");
3426 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_6
, 0x0);
3430 } /* if hardwired */
3432 if (bp
->common
.int_block
== INT_BLOCK_HC
)
3433 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
3434 COMMAND_REG_ATTN_BITS_SET
);
3436 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_SET_UPPER
*8);
3438 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", asserted
,
3439 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
3440 REG_WR(bp
, reg_addr
, asserted
);
3442 /* now set back the mask */
3443 if (asserted
& ATTN_NIG_FOR_FUNC
) {
3444 REG_WR(bp
, nig_int_mask_addr
, nig_mask
);
3445 bnx2x_release_phy_lock(bp
);
3449 static inline void bnx2x_fan_failure(struct bnx2x
*bp
)
3451 int port
= BP_PORT(bp
);
3453 /* mark the failure */
3456 dev_info
.port_hw_config
[port
].external_phy_config
);
3458 ext_phy_config
&= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
;
3459 ext_phy_config
|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
;
3460 SHMEM_WR(bp
, dev_info
.port_hw_config
[port
].external_phy_config
,
3463 /* log the failure */
3464 netdev_err(bp
->dev
, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
3465 "Please contact OEM Support for assistance\n");
3468 * Scheudle device reset (unload)
3469 * This is due to some boards consuming sufficient power when driver is
3470 * up to overheat if fan fails.
3472 smp_mb__before_clear_bit();
3473 set_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
);
3474 smp_mb__after_clear_bit();
3475 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
3479 static inline void bnx2x_attn_int_deasserted0(struct bnx2x
*bp
, u32 attn
)
3481 int port
= BP_PORT(bp
);
3485 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
3486 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
3488 if (attn
& AEU_INPUTS_ATTN_BITS_SPIO5
) {
3490 val
= REG_RD(bp
, reg_offset
);
3491 val
&= ~AEU_INPUTS_ATTN_BITS_SPIO5
;
3492 REG_WR(bp
, reg_offset
, val
);
3494 BNX2X_ERR("SPIO5 hw attention\n");
3496 /* Fan failure attention */
3497 bnx2x_hw_reset_phy(&bp
->link_params
);
3498 bnx2x_fan_failure(bp
);
3501 if ((attn
& bp
->link_vars
.aeu_int_mask
) && bp
->port
.pmf
) {
3502 bnx2x_acquire_phy_lock(bp
);
3503 bnx2x_handle_module_detect_int(&bp
->link_params
);
3504 bnx2x_release_phy_lock(bp
);
3507 if (attn
& HW_INTERRUT_ASSERT_SET_0
) {
3509 val
= REG_RD(bp
, reg_offset
);
3510 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_0
);
3511 REG_WR(bp
, reg_offset
, val
);
3513 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
3514 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_0
));
3519 static inline void bnx2x_attn_int_deasserted1(struct bnx2x
*bp
, u32 attn
)
3523 if (attn
& AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
) {
3525 val
= REG_RD(bp
, DORQ_REG_DORQ_INT_STS_CLR
);
3526 BNX2X_ERR("DB hw attention 0x%x\n", val
);
3527 /* DORQ discard attention */
3529 BNX2X_ERR("FATAL error from DORQ\n");
3532 if (attn
& HW_INTERRUT_ASSERT_SET_1
) {
3534 int port
= BP_PORT(bp
);
3537 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
:
3538 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
);
3540 val
= REG_RD(bp
, reg_offset
);
3541 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_1
);
3542 REG_WR(bp
, reg_offset
, val
);
3544 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
3545 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_1
));
3550 static inline void bnx2x_attn_int_deasserted2(struct bnx2x
*bp
, u32 attn
)
3554 if (attn
& AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
) {
3556 val
= REG_RD(bp
, CFC_REG_CFC_INT_STS_CLR
);
3557 BNX2X_ERR("CFC hw attention 0x%x\n", val
);
3558 /* CFC error attention */
3560 BNX2X_ERR("FATAL error from CFC\n");
3563 if (attn
& AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
) {
3564 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_0
);
3565 BNX2X_ERR("PXP hw attention-0 0x%x\n", val
);
3566 /* RQ_USDMDP_FIFO_OVERFLOW */
3568 BNX2X_ERR("FATAL error from PXP\n");
3570 if (!CHIP_IS_E1x(bp
)) {
3571 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_1
);
3572 BNX2X_ERR("PXP hw attention-1 0x%x\n", val
);
3576 if (attn
& HW_INTERRUT_ASSERT_SET_2
) {
3578 int port
= BP_PORT(bp
);
3581 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
:
3582 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
);
3584 val
= REG_RD(bp
, reg_offset
);
3585 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_2
);
3586 REG_WR(bp
, reg_offset
, val
);
3588 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
3589 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_2
));
3594 static inline void bnx2x_attn_int_deasserted3(struct bnx2x
*bp
, u32 attn
)
3598 if (attn
& EVEREST_GEN_ATTN_IN_USE_MASK
) {
3600 if (attn
& BNX2X_PMF_LINK_ASSERT
) {
3601 int func
= BP_FUNC(bp
);
3603 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
3604 bp
->mf_config
[BP_VN(bp
)] = MF_CFG_RD(bp
,
3605 func_mf_config
[BP_ABS_FUNC(bp
)].config
);
3607 func_mb
[BP_FW_MB_IDX(bp
)].drv_status
);
3608 if (val
& DRV_STATUS_DCC_EVENT_MASK
)
3610 (val
& DRV_STATUS_DCC_EVENT_MASK
));
3612 if (val
& DRV_STATUS_SET_MF_BW
)
3613 bnx2x_set_mf_bw(bp
);
3615 if (val
& DRV_STATUS_DRV_INFO_REQ
)
3616 bnx2x_handle_drv_info_req(bp
);
3617 if ((bp
->port
.pmf
== 0) && (val
& DRV_STATUS_PMF
))
3618 bnx2x_pmf_update(bp
);
3621 (val
& DRV_STATUS_DCBX_NEGOTIATION_RESULTS
) &&
3622 bp
->dcbx_enabled
> 0)
3623 /* start dcbx state machine */
3624 bnx2x_dcbx_set_params(bp
,
3625 BNX2X_DCBX_STATE_NEG_RECEIVED
);
3626 if (bp
->link_vars
.periodic_flags
&
3627 PERIODIC_FLAGS_LINK_EVENT
) {
3628 /* sync with link */
3629 bnx2x_acquire_phy_lock(bp
);
3630 bp
->link_vars
.periodic_flags
&=
3631 ~PERIODIC_FLAGS_LINK_EVENT
;
3632 bnx2x_release_phy_lock(bp
);
3634 bnx2x_link_sync_notify(bp
);
3635 bnx2x_link_report(bp
);
3637 /* Always call it here: bnx2x_link_report() will
3638 * prevent the link indication duplication.
3640 bnx2x__link_status_update(bp
);
3641 } else if (attn
& BNX2X_MC_ASSERT_BITS
) {
3643 BNX2X_ERR("MC assert!\n");
3644 bnx2x_mc_assert(bp
);
3645 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_10
, 0);
3646 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_9
, 0);
3647 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_8
, 0);
3648 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_7
, 0);
3651 } else if (attn
& BNX2X_MCP_ASSERT
) {
3653 BNX2X_ERR("MCP assert!\n");
3654 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_11
, 0);
3658 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn
);
3661 if (attn
& EVEREST_LATCHED_ATTN_IN_USE_MASK
) {
3662 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn
);
3663 if (attn
& BNX2X_GRC_TIMEOUT
) {
3664 val
= CHIP_IS_E1(bp
) ? 0 :
3665 REG_RD(bp
, MISC_REG_GRC_TIMEOUT_ATTN
);
3666 BNX2X_ERR("GRC time-out 0x%08x\n", val
);
3668 if (attn
& BNX2X_GRC_RSV
) {
3669 val
= CHIP_IS_E1(bp
) ? 0 :
3670 REG_RD(bp
, MISC_REG_GRC_RSV_ATTN
);
3671 BNX2X_ERR("GRC reserved 0x%08x\n", val
);
3673 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
, 0x7ff);
3679 * 0-7 - Engine0 load counter.
3680 * 8-15 - Engine1 load counter.
3681 * 16 - Engine0 RESET_IN_PROGRESS bit.
3682 * 17 - Engine1 RESET_IN_PROGRESS bit.
3683 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
3685 * 19 - Engine1 ONE_IS_LOADED.
3686 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
3687 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
3688 * just the one belonging to its engine).
3691 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
3693 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
3694 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
3695 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
3696 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
3697 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
3698 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
3699 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
3702 * Set the GLOBAL_RESET bit.
3704 * Should be run under rtnl lock
3706 void bnx2x_set_reset_global(struct bnx2x
*bp
)
3709 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3710 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3711 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
| BNX2X_GLOBAL_RESET_BIT
);
3712 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3716 * Clear the GLOBAL_RESET bit.
3718 * Should be run under rtnl lock
3720 static inline void bnx2x_clear_reset_global(struct bnx2x
*bp
)
3723 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3724 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3725 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~BNX2X_GLOBAL_RESET_BIT
));
3726 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3730 * Checks the GLOBAL_RESET bit.
3732 * should be run under rtnl lock
3734 static inline bool bnx2x_reset_is_global(struct bnx2x
*bp
)
3736 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3738 DP(NETIF_MSG_HW
, "GEN_REG_VAL=0x%08x\n", val
);
3739 return (val
& BNX2X_GLOBAL_RESET_BIT
) ? true : false;
3743 * Clear RESET_IN_PROGRESS bit for the current engine.
3745 * Should be run under rtnl lock
3747 static inline void bnx2x_set_reset_done(struct bnx2x
*bp
)
3750 u32 bit
= BP_PATH(bp
) ?
3751 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
3752 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3753 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3757 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3759 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3763 * Set RESET_IN_PROGRESS for the current engine.
3765 * should be run under rtnl lock
3767 void bnx2x_set_reset_in_progress(struct bnx2x
*bp
)
3770 u32 bit
= BP_PATH(bp
) ?
3771 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
3772 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3773 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3777 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3778 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3782 * Checks the RESET_IN_PROGRESS bit for the given engine.
3783 * should be run under rtnl lock
3785 bool bnx2x_reset_is_done(struct bnx2x
*bp
, int engine
)
3787 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3789 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
3791 /* return false if bit is set */
3792 return (val
& bit
) ? false : true;
3796 * set pf load for the current pf.
3798 * should be run under rtnl lock
3800 void bnx2x_set_pf_load(struct bnx2x
*bp
)
3803 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
3804 BNX2X_PATH0_LOAD_CNT_MASK
;
3805 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
3806 BNX2X_PATH0_LOAD_CNT_SHIFT
;
3808 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3809 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3811 DP(NETIF_MSG_IFUP
, "Old GEN_REG_VAL=0x%08x\n", val
);
3813 /* get the current counter value */
3814 val1
= (val
& mask
) >> shift
;
3816 /* set bit of that PF */
3817 val1
|= (1 << bp
->pf_num
);
3819 /* clear the old value */
3822 /* set the new one */
3823 val
|= ((val1
<< shift
) & mask
);
3825 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3826 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3830 * bnx2x_clear_pf_load - clear pf load mark
3832 * @bp: driver handle
3834 * Should be run under rtnl lock.
3835 * Decrements the load counter for the current engine. Returns
3836 * whether other functions are still loaded
3838 bool bnx2x_clear_pf_load(struct bnx2x
*bp
)
3841 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
3842 BNX2X_PATH0_LOAD_CNT_MASK
;
3843 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
3844 BNX2X_PATH0_LOAD_CNT_SHIFT
;
3846 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3847 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3848 DP(NETIF_MSG_IFDOWN
, "Old GEN_REG_VAL=0x%08x\n", val
);
3850 /* get the current counter value */
3851 val1
= (val
& mask
) >> shift
;
3853 /* clear bit of that PF */
3854 val1
&= ~(1 << bp
->pf_num
);
3856 /* clear the old value */
3859 /* set the new one */
3860 val
|= ((val1
<< shift
) & mask
);
3862 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
3863 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3868 * Read the load status for the current engine.
3870 * should be run under rtnl lock
3872 static inline bool bnx2x_get_load_status(struct bnx2x
*bp
, int engine
)
3874 u32 mask
= (engine
? BNX2X_PATH1_LOAD_CNT_MASK
:
3875 BNX2X_PATH0_LOAD_CNT_MASK
);
3876 u32 shift
= (engine
? BNX2X_PATH1_LOAD_CNT_SHIFT
:
3877 BNX2X_PATH0_LOAD_CNT_SHIFT
);
3878 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3880 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "GLOB_REG=0x%08x\n", val
);
3882 val
= (val
& mask
) >> shift
;
3884 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "load mask for engine %d = 0x%x\n",
3891 * Reset the load status for the current engine.
3893 static inline void bnx2x_clear_load_status(struct bnx2x
*bp
)
3896 u32 mask
= (BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
3897 BNX2X_PATH0_LOAD_CNT_MASK
);
3898 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3899 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
3900 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~mask
));
3901 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
3904 static inline void _print_next_block(int idx
, const char *blk
)
3906 pr_cont("%s%s", idx
? ", " : "", blk
);
3909 static inline int bnx2x_check_blocks_with_parity0(u32 sig
, int par_num
,
3914 for (i
= 0; sig
; i
++) {
3915 cur_bit
= ((u32
)0x1 << i
);
3916 if (sig
& cur_bit
) {
3918 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
:
3920 _print_next_block(par_num
++, "BRB");
3922 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
:
3924 _print_next_block(par_num
++, "PARSER");
3926 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
:
3928 _print_next_block(par_num
++, "TSDM");
3930 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
:
3932 _print_next_block(par_num
++,
3935 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
:
3937 _print_next_block(par_num
++, "TCM");
3939 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
:
3941 _print_next_block(par_num
++, "TSEMI");
3943 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
:
3945 _print_next_block(par_num
++, "XPB");
3957 static inline int bnx2x_check_blocks_with_parity1(u32 sig
, int par_num
,
3958 bool *global
, bool print
)
3962 for (i
= 0; sig
; i
++) {
3963 cur_bit
= ((u32
)0x1 << i
);
3964 if (sig
& cur_bit
) {
3966 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
:
3968 _print_next_block(par_num
++, "PBF");
3970 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
:
3972 _print_next_block(par_num
++, "QM");
3974 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
:
3976 _print_next_block(par_num
++, "TM");
3978 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
:
3980 _print_next_block(par_num
++, "XSDM");
3982 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
:
3984 _print_next_block(par_num
++, "XCM");
3986 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
:
3988 _print_next_block(par_num
++, "XSEMI");
3990 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
:
3992 _print_next_block(par_num
++,
3995 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
:
3997 _print_next_block(par_num
++, "NIG");
3999 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
:
4001 _print_next_block(par_num
++,
4005 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
:
4007 _print_next_block(par_num
++, "DEBUG");
4009 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
:
4011 _print_next_block(par_num
++, "USDM");
4013 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
:
4015 _print_next_block(par_num
++, "UCM");
4017 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
:
4019 _print_next_block(par_num
++, "USEMI");
4021 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
:
4023 _print_next_block(par_num
++, "UPB");
4025 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
:
4027 _print_next_block(par_num
++, "CSDM");
4029 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
:
4031 _print_next_block(par_num
++, "CCM");
4043 static inline int bnx2x_check_blocks_with_parity2(u32 sig
, int par_num
,
4048 for (i
= 0; sig
; i
++) {
4049 cur_bit
= ((u32
)0x1 << i
);
4050 if (sig
& cur_bit
) {
4052 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
:
4054 _print_next_block(par_num
++, "CSEMI");
4056 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
:
4058 _print_next_block(par_num
++, "PXP");
4060 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
:
4062 _print_next_block(par_num
++,
4063 "PXPPCICLOCKCLIENT");
4065 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
:
4067 _print_next_block(par_num
++, "CFC");
4069 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
:
4071 _print_next_block(par_num
++, "CDU");
4073 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
:
4075 _print_next_block(par_num
++, "DMAE");
4077 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
:
4079 _print_next_block(par_num
++, "IGU");
4081 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
:
4083 _print_next_block(par_num
++, "MISC");
4095 static inline int bnx2x_check_blocks_with_parity3(u32 sig
, int par_num
,
4096 bool *global
, bool print
)
4100 for (i
= 0; sig
; i
++) {
4101 cur_bit
= ((u32
)0x1 << i
);
4102 if (sig
& cur_bit
) {
4104 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
:
4106 _print_next_block(par_num
++, "MCP ROM");
4109 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
:
4111 _print_next_block(par_num
++,
4115 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
:
4117 _print_next_block(par_num
++,
4121 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
:
4123 _print_next_block(par_num
++,
4137 static inline int bnx2x_check_blocks_with_parity4(u32 sig
, int par_num
,
4142 for (i
= 0; sig
; i
++) {
4143 cur_bit
= ((u32
)0x1 << i
);
4144 if (sig
& cur_bit
) {
4146 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
:
4148 _print_next_block(par_num
++, "PGLUE_B");
4150 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
:
4152 _print_next_block(par_num
++, "ATC");
4164 static inline bool bnx2x_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
,
4167 if ((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4168 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4169 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4170 (sig
[3] & HW_PRTY_ASSERT_SET_3
) ||
4171 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) {
4173 DP(NETIF_MSG_HW
, "Was parity error: HW block parity attention:\n"
4174 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4175 sig
[0] & HW_PRTY_ASSERT_SET_0
,
4176 sig
[1] & HW_PRTY_ASSERT_SET_1
,
4177 sig
[2] & HW_PRTY_ASSERT_SET_2
,
4178 sig
[3] & HW_PRTY_ASSERT_SET_3
,
4179 sig
[4] & HW_PRTY_ASSERT_SET_4
);
4182 "Parity errors detected in blocks: ");
4183 par_num
= bnx2x_check_blocks_with_parity0(
4184 sig
[0] & HW_PRTY_ASSERT_SET_0
, par_num
, print
);
4185 par_num
= bnx2x_check_blocks_with_parity1(
4186 sig
[1] & HW_PRTY_ASSERT_SET_1
, par_num
, global
, print
);
4187 par_num
= bnx2x_check_blocks_with_parity2(
4188 sig
[2] & HW_PRTY_ASSERT_SET_2
, par_num
, print
);
4189 par_num
= bnx2x_check_blocks_with_parity3(
4190 sig
[3] & HW_PRTY_ASSERT_SET_3
, par_num
, global
, print
);
4191 par_num
= bnx2x_check_blocks_with_parity4(
4192 sig
[4] & HW_PRTY_ASSERT_SET_4
, par_num
, print
);
4203 * bnx2x_chk_parity_attn - checks for parity attentions.
4205 * @bp: driver handle
4206 * @global: true if there was a global attention
4207 * @print: show parity attention in syslog
4209 bool bnx2x_chk_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
)
4211 struct attn_route attn
= { {0} };
4212 int port
= BP_PORT(bp
);
4214 attn
.sig
[0] = REG_RD(bp
,
4215 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+
4217 attn
.sig
[1] = REG_RD(bp
,
4218 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+
4220 attn
.sig
[2] = REG_RD(bp
,
4221 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+
4223 attn
.sig
[3] = REG_RD(bp
,
4224 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+
4227 if (!CHIP_IS_E1x(bp
))
4228 attn
.sig
[4] = REG_RD(bp
,
4229 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+
4232 return bnx2x_parity_attn(bp
, global
, print
, attn
.sig
);
4236 static inline void bnx2x_attn_int_deasserted4(struct bnx2x
*bp
, u32 attn
)
4239 if (attn
& AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
) {
4241 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS_CLR
);
4242 BNX2X_ERR("PGLUE hw attention 0x%x\n", val
);
4243 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
)
4244 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
4245 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
)
4246 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
4247 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
)
4248 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
4249 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
)
4250 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
4252 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
)
4253 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
4255 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
)
4256 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
4257 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
)
4258 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
4259 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
)
4260 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
4261 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
)
4262 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
4264 if (attn
& AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
) {
4265 val
= REG_RD(bp
, ATC_REG_ATC_INT_STS_CLR
);
4266 BNX2X_ERR("ATC hw attention 0x%x\n", val
);
4267 if (val
& ATC_ATC_INT_STS_REG_ADDRESS_ERROR
)
4268 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
4269 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
)
4270 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
4271 if (val
& ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
)
4272 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
4273 if (val
& ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
)
4274 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
4275 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
)
4276 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
4277 if (val
& ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
)
4278 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
4281 if (attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4282 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)) {
4283 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
4284 (u32
)(attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
4285 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)));
4290 static void bnx2x_attn_int_deasserted(struct bnx2x
*bp
, u32 deasserted
)
4292 struct attn_route attn
, *group_mask
;
4293 int port
= BP_PORT(bp
);
4298 bool global
= false;
4300 /* need to take HW lock because MCP or other port might also
4301 try to handle this event */
4302 bnx2x_acquire_alr(bp
);
4304 if (bnx2x_chk_parity_attn(bp
, &global
, true)) {
4305 #ifndef BNX2X_STOP_ON_ERROR
4306 bp
->recovery_state
= BNX2X_RECOVERY_INIT
;
4307 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
4308 /* Disable HW interrupts */
4309 bnx2x_int_disable(bp
);
4310 /* In case of parity errors don't handle attentions so that
4311 * other function would "see" parity errors.
4316 bnx2x_release_alr(bp
);
4320 attn
.sig
[0] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ port
*4);
4321 attn
.sig
[1] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+ port
*4);
4322 attn
.sig
[2] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+ port
*4);
4323 attn
.sig
[3] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+ port
*4);
4324 if (!CHIP_IS_E1x(bp
))
4326 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+ port
*4);
4330 DP(NETIF_MSG_HW
, "attn: %08x %08x %08x %08x %08x\n",
4331 attn
.sig
[0], attn
.sig
[1], attn
.sig
[2], attn
.sig
[3], attn
.sig
[4]);
4333 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
4334 if (deasserted
& (1 << index
)) {
4335 group_mask
= &bp
->attn_group
[index
];
4337 DP(NETIF_MSG_HW
, "group[%d]: %08x %08x %08x %08x %08x\n",
4339 group_mask
->sig
[0], group_mask
->sig
[1],
4340 group_mask
->sig
[2], group_mask
->sig
[3],
4341 group_mask
->sig
[4]);
4343 bnx2x_attn_int_deasserted4(bp
,
4344 attn
.sig
[4] & group_mask
->sig
[4]);
4345 bnx2x_attn_int_deasserted3(bp
,
4346 attn
.sig
[3] & group_mask
->sig
[3]);
4347 bnx2x_attn_int_deasserted1(bp
,
4348 attn
.sig
[1] & group_mask
->sig
[1]);
4349 bnx2x_attn_int_deasserted2(bp
,
4350 attn
.sig
[2] & group_mask
->sig
[2]);
4351 bnx2x_attn_int_deasserted0(bp
,
4352 attn
.sig
[0] & group_mask
->sig
[0]);
4356 bnx2x_release_alr(bp
);
4358 if (bp
->common
.int_block
== INT_BLOCK_HC
)
4359 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
4360 COMMAND_REG_ATTN_BITS_CLR
);
4362 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_CLR_UPPER
*8);
4365 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", val
,
4366 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
4367 REG_WR(bp
, reg_addr
, val
);
4369 if (~bp
->attn_state
& deasserted
)
4370 BNX2X_ERR("IGU ERROR\n");
4372 reg_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
4373 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
4375 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4376 aeu_mask
= REG_RD(bp
, reg_addr
);
4378 DP(NETIF_MSG_HW
, "aeu_mask %x newly deasserted %x\n",
4379 aeu_mask
, deasserted
);
4380 aeu_mask
|= (deasserted
& 0x3ff);
4381 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
4383 REG_WR(bp
, reg_addr
, aeu_mask
);
4384 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4386 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
4387 bp
->attn_state
&= ~deasserted
;
4388 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
4391 static void bnx2x_attn_int(struct bnx2x
*bp
)
4393 /* read local copy of bits */
4394 u32 attn_bits
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4396 u32 attn_ack
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
4398 u32 attn_state
= bp
->attn_state
;
4400 /* look for changed bits */
4401 u32 asserted
= attn_bits
& ~attn_ack
& ~attn_state
;
4402 u32 deasserted
= ~attn_bits
& attn_ack
& attn_state
;
4405 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
4406 attn_bits
, attn_ack
, asserted
, deasserted
);
4408 if (~(attn_bits
^ attn_ack
) & (attn_bits
^ attn_state
))
4409 BNX2X_ERR("BAD attention state\n");
4411 /* handle bits that were raised */
4413 bnx2x_attn_int_asserted(bp
, asserted
);
4416 bnx2x_attn_int_deasserted(bp
, deasserted
);
4419 void bnx2x_igu_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 segment
,
4420 u16 index
, u8 op
, u8 update
)
4422 u32 igu_addr
= BAR_IGU_INTMEM
+ (IGU_CMD_INT_ACK_BASE
+ igu_sb_id
)*8;
4424 bnx2x_igu_ack_sb_gen(bp
, igu_sb_id
, segment
, index
, op
, update
,
4428 static inline void bnx2x_update_eq_prod(struct bnx2x
*bp
, u16 prod
)
4430 /* No memory barriers */
4431 storm_memset_eq_prod(bp
, prod
, BP_FUNC(bp
));
4432 mmiowb(); /* keep prod updates ordered */
4436 static int bnx2x_cnic_handle_cfc_del(struct bnx2x
*bp
, u32 cid
,
4437 union event_ring_elem
*elem
)
4439 u8 err
= elem
->message
.error
;
4441 if (!bp
->cnic_eth_dev
.starting_cid
||
4442 (cid
< bp
->cnic_eth_dev
.starting_cid
&&
4443 cid
!= bp
->cnic_eth_dev
.iscsi_l2_cid
))
4446 DP(BNX2X_MSG_SP
, "got delete ramrod for CNIC CID %d\n", cid
);
4448 if (unlikely(err
)) {
4450 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
4452 bnx2x_panic_dump(bp
);
4454 bnx2x_cnic_cfc_comp(bp
, cid
, err
);
4459 static inline void bnx2x_handle_mcast_eqe(struct bnx2x
*bp
)
4461 struct bnx2x_mcast_ramrod_params rparam
;
4464 memset(&rparam
, 0, sizeof(rparam
));
4466 rparam
.mcast_obj
= &bp
->mcast_obj
;
4468 netif_addr_lock_bh(bp
->dev
);
4470 /* Clear pending state for the last command */
4471 bp
->mcast_obj
.raw
.clear_pending(&bp
->mcast_obj
.raw
);
4473 /* If there are pending mcast commands - send them */
4474 if (bp
->mcast_obj
.check_pending(&bp
->mcast_obj
)) {
4475 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_CONT
);
4477 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
4481 netif_addr_unlock_bh(bp
->dev
);
4484 static inline void bnx2x_handle_classification_eqe(struct bnx2x
*bp
,
4485 union event_ring_elem
*elem
)
4487 unsigned long ramrod_flags
= 0;
4489 u32 cid
= elem
->message
.data
.eth_event
.echo
& BNX2X_SWCID_MASK
;
4490 struct bnx2x_vlan_mac_obj
*vlan_mac_obj
;
4492 /* Always push next commands out, don't wait here */
4493 __set_bit(RAMROD_CONT
, &ramrod_flags
);
4495 switch (elem
->message
.data
.eth_event
.echo
>> BNX2X_SWCID_SHIFT
) {
4496 case BNX2X_FILTER_MAC_PENDING
:
4497 DP(BNX2X_MSG_SP
, "Got SETUP_MAC completions\n");
4499 if (cid
== BNX2X_ISCSI_ETH_CID
)
4500 vlan_mac_obj
= &bp
->iscsi_l2_mac_obj
;
4503 vlan_mac_obj
= &bp
->fp
[cid
].mac_obj
;
4506 case BNX2X_FILTER_MCAST_PENDING
:
4507 DP(BNX2X_MSG_SP
, "Got SETUP_MCAST completions\n");
4508 /* This is only relevant for 57710 where multicast MACs are
4509 * configured as unicast MACs using the same ramrod.
4511 bnx2x_handle_mcast_eqe(bp
);
4514 BNX2X_ERR("Unsupported classification command: %d\n",
4515 elem
->message
.data
.eth_event
.echo
);
4519 rc
= vlan_mac_obj
->complete(bp
, vlan_mac_obj
, elem
, &ramrod_flags
);
4522 BNX2X_ERR("Failed to schedule new commands: %d\n", rc
);
4524 DP(BNX2X_MSG_SP
, "Scheduled next pending commands...\n");
4529 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
);
4532 static inline void bnx2x_handle_rx_mode_eqe(struct bnx2x
*bp
)
4534 netif_addr_lock_bh(bp
->dev
);
4536 clear_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
4538 /* Send rx_mode command again if was requested */
4539 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
))
4540 bnx2x_set_storm_rx_mode(bp
);
4542 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
,
4544 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
4545 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
,
4547 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
4550 netif_addr_unlock_bh(bp
->dev
);
4553 static inline struct bnx2x_queue_sp_obj
*bnx2x_cid_to_q_obj(
4554 struct bnx2x
*bp
, u32 cid
)
4556 DP(BNX2X_MSG_SP
, "retrieving fp from cid %d\n", cid
);
4558 if (cid
== BNX2X_FCOE_ETH_CID
)
4559 return &bnx2x_fcoe(bp
, q_obj
);
4562 return &bnx2x_fp(bp
, CID_TO_FP(cid
), q_obj
);
4565 static void bnx2x_eq_int(struct bnx2x
*bp
)
4567 u16 hw_cons
, sw_cons
, sw_prod
;
4568 union event_ring_elem
*elem
;
4572 struct bnx2x_queue_sp_obj
*q_obj
;
4573 struct bnx2x_func_sp_obj
*f_obj
= &bp
->func_obj
;
4574 struct bnx2x_raw_obj
*rss_raw
= &bp
->rss_conf_obj
.raw
;
4576 hw_cons
= le16_to_cpu(*bp
->eq_cons_sb
);
4578 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
4579 * when we get the the next-page we nned to adjust so the loop
4580 * condition below will be met. The next element is the size of a
4581 * regular element and hence incrementing by 1
4583 if ((hw_cons
& EQ_DESC_MAX_PAGE
) == EQ_DESC_MAX_PAGE
)
4586 /* This function may never run in parallel with itself for a
4587 * specific bp, thus there is no need in "paired" read memory
4590 sw_cons
= bp
->eq_cons
;
4591 sw_prod
= bp
->eq_prod
;
4593 DP(BNX2X_MSG_SP
, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
4594 hw_cons
, sw_cons
, atomic_read(&bp
->eq_spq_left
));
4596 for (; sw_cons
!= hw_cons
;
4597 sw_prod
= NEXT_EQ_IDX(sw_prod
), sw_cons
= NEXT_EQ_IDX(sw_cons
)) {
4600 elem
= &bp
->eq_ring
[EQ_DESC(sw_cons
)];
4602 cid
= SW_CID(elem
->message
.data
.cfc_del_event
.cid
);
4603 opcode
= elem
->message
.opcode
;
4606 /* handle eq element */
4608 case EVENT_RING_OPCODE_STAT_QUERY
:
4609 DP(BNX2X_MSG_SP
| BNX2X_MSG_STATS
,
4610 "got statistics comp event %d\n",
4612 /* nothing to do with stats comp */
4615 case EVENT_RING_OPCODE_CFC_DEL
:
4616 /* handle according to cid range */
4618 * we may want to verify here that the bp state is
4622 "got delete ramrod for MULTI[%d]\n", cid
);
4624 if (!bnx2x_cnic_handle_cfc_del(bp
, cid
, elem
))
4627 q_obj
= bnx2x_cid_to_q_obj(bp
, cid
);
4629 if (q_obj
->complete_cmd(bp
, q_obj
, BNX2X_Q_CMD_CFC_DEL
))
4636 case EVENT_RING_OPCODE_STOP_TRAFFIC
:
4637 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got STOP TRAFFIC\n");
4638 if (f_obj
->complete_cmd(bp
, f_obj
,
4639 BNX2X_F_CMD_TX_STOP
))
4641 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_PAUSED
);
4644 case EVENT_RING_OPCODE_START_TRAFFIC
:
4645 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got START TRAFFIC\n");
4646 if (f_obj
->complete_cmd(bp
, f_obj
,
4647 BNX2X_F_CMD_TX_START
))
4649 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_RELEASED
);
4651 case EVENT_RING_OPCODE_FUNCTION_START
:
4652 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
4653 "got FUNC_START ramrod\n");
4654 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_START
))
4659 case EVENT_RING_OPCODE_FUNCTION_STOP
:
4660 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
4661 "got FUNC_STOP ramrod\n");
4662 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_STOP
))
4668 switch (opcode
| bp
->state
) {
4669 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
4671 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
4672 BNX2X_STATE_OPENING_WAIT4_PORT
):
4673 cid
= elem
->message
.data
.eth_event
.echo
&
4675 DP(BNX2X_MSG_SP
, "got RSS_UPDATE ramrod. CID %d\n",
4677 rss_raw
->clear_pending(rss_raw
);
4680 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_OPEN
):
4681 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_DIAG
):
4682 case (EVENT_RING_OPCODE_SET_MAC
|
4683 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4684 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
4686 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
4688 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
4689 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4690 DP(BNX2X_MSG_SP
, "got (un)set mac ramrod\n");
4691 bnx2x_handle_classification_eqe(bp
, elem
);
4694 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
4696 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
4698 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
4699 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4700 DP(BNX2X_MSG_SP
, "got mcast ramrod\n");
4701 bnx2x_handle_mcast_eqe(bp
);
4704 case (EVENT_RING_OPCODE_FILTERS_RULES
|
4706 case (EVENT_RING_OPCODE_FILTERS_RULES
|
4708 case (EVENT_RING_OPCODE_FILTERS_RULES
|
4709 BNX2X_STATE_CLOSING_WAIT4_HALT
):
4710 DP(BNX2X_MSG_SP
, "got rx_mode ramrod\n");
4711 bnx2x_handle_rx_mode_eqe(bp
);
4714 /* unknown event log error and continue */
4715 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
4716 elem
->message
.opcode
, bp
->state
);
4722 smp_mb__before_atomic_inc();
4723 atomic_add(spqe_cnt
, &bp
->eq_spq_left
);
4725 bp
->eq_cons
= sw_cons
;
4726 bp
->eq_prod
= sw_prod
;
4727 /* Make sure that above mem writes were issued towards the memory */
4730 /* update producer */
4731 bnx2x_update_eq_prod(bp
, bp
->eq_prod
);
4734 static void bnx2x_sp_task(struct work_struct
*work
)
4736 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_task
.work
);
4739 status
= bnx2x_update_dsb_idx(bp
);
4740 /* if (status == 0) */
4741 /* BNX2X_ERR("spurious slowpath interrupt!\n"); */
4743 DP(BNX2X_MSG_SP
, "got a slowpath interrupt (status 0x%x)\n", status
);
4746 if (status
& BNX2X_DEF_SB_ATT_IDX
) {
4748 status
&= ~BNX2X_DEF_SB_ATT_IDX
;
4751 /* SP events: STAT_QUERY and others */
4752 if (status
& BNX2X_DEF_SB_IDX
) {
4754 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
4756 if ((!NO_FCOE(bp
)) &&
4757 (bnx2x_has_rx_work(fp
) || bnx2x_has_tx_work(fp
))) {
4759 * Prevent local bottom-halves from running as
4760 * we are going to change the local NAPI list.
4763 napi_schedule(&bnx2x_fcoe(bp
, napi
));
4767 /* Handle EQ completions */
4770 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
,
4771 le16_to_cpu(bp
->def_idx
), IGU_INT_NOP
, 1);
4773 status
&= ~BNX2X_DEF_SB_IDX
;
4776 if (unlikely(status
))
4777 DP(BNX2X_MSG_SP
, "got an unknown interrupt! (status 0x%x)\n",
4780 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, ATTENTION_ID
,
4781 le16_to_cpu(bp
->def_att_idx
), IGU_INT_ENABLE
, 1);
4784 irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
)
4786 struct net_device
*dev
= dev_instance
;
4787 struct bnx2x
*bp
= netdev_priv(dev
);
4789 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0,
4790 IGU_INT_DISABLE
, 0);
4792 #ifdef BNX2X_STOP_ON_ERROR
4793 if (unlikely(bp
->panic
))
4799 struct cnic_ops
*c_ops
;
4802 c_ops
= rcu_dereference(bp
->cnic_ops
);
4804 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
4808 queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
4813 /* end of slow path */
4816 void bnx2x_drv_pulse(struct bnx2x
*bp
)
4818 SHMEM_WR(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_pulse_mb
,
4819 bp
->fw_drv_pulse_wr_seq
);
4823 static void bnx2x_timer(unsigned long data
)
4825 struct bnx2x
*bp
= (struct bnx2x
*) data
;
4827 if (!netif_running(bp
->dev
))
4830 if (!BP_NOMCP(bp
)) {
4831 int mb_idx
= BP_FW_MB_IDX(bp
);
4835 ++bp
->fw_drv_pulse_wr_seq
;
4836 bp
->fw_drv_pulse_wr_seq
&= DRV_PULSE_SEQ_MASK
;
4837 /* TBD - add SYSTEM_TIME */
4838 drv_pulse
= bp
->fw_drv_pulse_wr_seq
;
4839 bnx2x_drv_pulse(bp
);
4841 mcp_pulse
= (SHMEM_RD(bp
, func_mb
[mb_idx
].mcp_pulse_mb
) &
4842 MCP_PULSE_SEQ_MASK
);
4843 /* The delta between driver pulse and mcp response
4844 * should be 1 (before mcp response) or 0 (after mcp response)
4846 if ((drv_pulse
!= mcp_pulse
) &&
4847 (drv_pulse
!= ((mcp_pulse
+ 1) & MCP_PULSE_SEQ_MASK
))) {
4848 /* someone lost a heartbeat... */
4849 BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
4850 drv_pulse
, mcp_pulse
);
4854 if (bp
->state
== BNX2X_STATE_OPEN
)
4855 bnx2x_stats_handle(bp
, STATS_EVENT_UPDATE
);
4857 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4860 /* end of Statistics */
4865 * nic init service functions
4868 static inline void bnx2x_fill(struct bnx2x
*bp
, u32 addr
, int fill
, u32 len
)
4871 if (!(len
%4) && !(addr
%4))
4872 for (i
= 0; i
< len
; i
+= 4)
4873 REG_WR(bp
, addr
+ i
, fill
);
4875 for (i
= 0; i
< len
; i
++)
4876 REG_WR8(bp
, addr
+ i
, fill
);
4880 /* helper: writes FP SP data to FW - data_size in dwords */
4881 static inline void bnx2x_wr_fp_sb_data(struct bnx2x
*bp
,
4887 for (index
= 0; index
< data_size
; index
++)
4888 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4889 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id
) +
4891 *(sb_data_p
+ index
));
4894 static inline void bnx2x_zero_fp_sb(struct bnx2x
*bp
, int fw_sb_id
)
4898 struct hc_status_block_data_e2 sb_data_e2
;
4899 struct hc_status_block_data_e1x sb_data_e1x
;
4901 /* disable the function first */
4902 if (!CHIP_IS_E1x(bp
)) {
4903 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
4904 sb_data_e2
.common
.state
= SB_DISABLED
;
4905 sb_data_e2
.common
.p_func
.vf_valid
= false;
4906 sb_data_p
= (u32
*)&sb_data_e2
;
4907 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
4909 memset(&sb_data_e1x
, 0,
4910 sizeof(struct hc_status_block_data_e1x
));
4911 sb_data_e1x
.common
.state
= SB_DISABLED
;
4912 sb_data_e1x
.common
.p_func
.vf_valid
= false;
4913 sb_data_p
= (u32
*)&sb_data_e1x
;
4914 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
4916 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
4918 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4919 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id
), 0,
4920 CSTORM_STATUS_BLOCK_SIZE
);
4921 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4922 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id
), 0,
4923 CSTORM_SYNC_BLOCK_SIZE
);
4926 /* helper: writes SP SB data to FW */
4927 static inline void bnx2x_wr_sp_sb_data(struct bnx2x
*bp
,
4928 struct hc_sp_status_block_data
*sp_sb_data
)
4930 int func
= BP_FUNC(bp
);
4932 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
4933 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
4934 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
4936 *((u32
*)sp_sb_data
+ i
));
4939 static inline void bnx2x_zero_sp_sb(struct bnx2x
*bp
)
4941 int func
= BP_FUNC(bp
);
4942 struct hc_sp_status_block_data sp_sb_data
;
4943 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
4945 sp_sb_data
.state
= SB_DISABLED
;
4946 sp_sb_data
.p_func
.vf_valid
= false;
4948 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
4950 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4951 CSTORM_SP_STATUS_BLOCK_OFFSET(func
), 0,
4952 CSTORM_SP_STATUS_BLOCK_SIZE
);
4953 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
4954 CSTORM_SP_SYNC_BLOCK_OFFSET(func
), 0,
4955 CSTORM_SP_SYNC_BLOCK_SIZE
);
4961 void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm
*hc_sm
,
4962 int igu_sb_id
, int igu_seg_id
)
4964 hc_sm
->igu_sb_id
= igu_sb_id
;
4965 hc_sm
->igu_seg_id
= igu_seg_id
;
4966 hc_sm
->timer_value
= 0xFF;
4967 hc_sm
->time_to_expire
= 0xFFFFFFFF;
4971 /* allocates state machine ids. */
4973 void bnx2x_map_sb_state_machines(struct hc_index_data
*index_data
)
4975 /* zero out state machine indices */
4977 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4980 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4981 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4982 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4983 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
&= ~HC_INDEX_DATA_SM_ID
;
4987 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
|=
4988 SM_RX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
4991 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
|=
4992 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
4993 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
|=
4994 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
4995 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
|=
4996 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
4997 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
|=
4998 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5001 static void bnx2x_init_sb(struct bnx2x
*bp
, dma_addr_t mapping
, int vfid
,
5002 u8 vf_valid
, int fw_sb_id
, int igu_sb_id
)
5006 struct hc_status_block_data_e2 sb_data_e2
;
5007 struct hc_status_block_data_e1x sb_data_e1x
;
5008 struct hc_status_block_sm
*hc_sm_p
;
5012 if (CHIP_INT_MODE_IS_BC(bp
))
5013 igu_seg_id
= HC_SEG_ACCESS_NORM
;
5015 igu_seg_id
= IGU_SEG_ACCESS_NORM
;
5017 bnx2x_zero_fp_sb(bp
, fw_sb_id
);
5019 if (!CHIP_IS_E1x(bp
)) {
5020 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5021 sb_data_e2
.common
.state
= SB_ENABLED
;
5022 sb_data_e2
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5023 sb_data_e2
.common
.p_func
.vf_id
= vfid
;
5024 sb_data_e2
.common
.p_func
.vf_valid
= vf_valid
;
5025 sb_data_e2
.common
.p_func
.vnic_id
= BP_VN(bp
);
5026 sb_data_e2
.common
.same_igu_sb_1b
= true;
5027 sb_data_e2
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5028 sb_data_e2
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5029 hc_sm_p
= sb_data_e2
.common
.state_machine
;
5030 sb_data_p
= (u32
*)&sb_data_e2
;
5031 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5032 bnx2x_map_sb_state_machines(sb_data_e2
.index_data
);
5034 memset(&sb_data_e1x
, 0,
5035 sizeof(struct hc_status_block_data_e1x
));
5036 sb_data_e1x
.common
.state
= SB_ENABLED
;
5037 sb_data_e1x
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5038 sb_data_e1x
.common
.p_func
.vf_id
= 0xff;
5039 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5040 sb_data_e1x
.common
.p_func
.vnic_id
= BP_VN(bp
);
5041 sb_data_e1x
.common
.same_igu_sb_1b
= true;
5042 sb_data_e1x
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5043 sb_data_e1x
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5044 hc_sm_p
= sb_data_e1x
.common
.state_machine
;
5045 sb_data_p
= (u32
*)&sb_data_e1x
;
5046 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5047 bnx2x_map_sb_state_machines(sb_data_e1x
.index_data
);
5050 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_RX_ID
],
5051 igu_sb_id
, igu_seg_id
);
5052 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_TX_ID
],
5053 igu_sb_id
, igu_seg_id
);
5055 DP(NETIF_MSG_IFUP
, "Init FW SB %d\n", fw_sb_id
);
5057 /* write indecies to HW */
5058 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5061 static void bnx2x_update_coalesce_sb(struct bnx2x
*bp
, u8 fw_sb_id
,
5062 u16 tx_usec
, u16 rx_usec
)
5064 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
, HC_INDEX_ETH_RX_CQ_CONS
,
5066 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5067 HC_INDEX_ETH_TX_CQ_CONS_COS0
, false,
5069 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5070 HC_INDEX_ETH_TX_CQ_CONS_COS1
, false,
5072 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
5073 HC_INDEX_ETH_TX_CQ_CONS_COS2
, false,
5077 static void bnx2x_init_def_sb(struct bnx2x
*bp
)
5079 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
5080 dma_addr_t mapping
= bp
->def_status_blk_mapping
;
5081 int igu_sp_sb_index
;
5083 int port
= BP_PORT(bp
);
5084 int func
= BP_FUNC(bp
);
5085 int reg_offset
, reg_offset_en5
;
5088 struct hc_sp_status_block_data sp_sb_data
;
5089 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
5091 if (CHIP_INT_MODE_IS_BC(bp
)) {
5092 igu_sp_sb_index
= DEF_SB_IGU_ID
;
5093 igu_seg_id
= HC_SEG_ACCESS_DEF
;
5095 igu_sp_sb_index
= bp
->igu_dsb_id
;
5096 igu_seg_id
= IGU_SEG_ACCESS_DEF
;
5100 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
5101 atten_status_block
);
5102 def_sb
->atten_status_block
.status_block_id
= igu_sp_sb_index
;
5106 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
5107 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
5108 reg_offset_en5
= (port
? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0
:
5109 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0
);
5110 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
5112 /* take care of sig[0]..sig[4] */
5113 for (sindex
= 0; sindex
< 4; sindex
++)
5114 bp
->attn_group
[index
].sig
[sindex
] =
5115 REG_RD(bp
, reg_offset
+ sindex
*0x4 + 0x10*index
);
5117 if (!CHIP_IS_E1x(bp
))
5119 * enable5 is separate from the rest of the registers,
5120 * and therefore the address skip is 4
5121 * and not 16 between the different groups
5123 bp
->attn_group
[index
].sig
[4] = REG_RD(bp
,
5124 reg_offset_en5
+ 0x4*index
);
5126 bp
->attn_group
[index
].sig
[4] = 0;
5129 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
5130 reg_offset
= (port
? HC_REG_ATTN_MSG1_ADDR_L
:
5131 HC_REG_ATTN_MSG0_ADDR_L
);
5133 REG_WR(bp
, reg_offset
, U64_LO(section
));
5134 REG_WR(bp
, reg_offset
+ 4, U64_HI(section
));
5135 } else if (!CHIP_IS_E1x(bp
)) {
5136 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_L
, U64_LO(section
));
5137 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_H
, U64_HI(section
));
5140 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
5143 bnx2x_zero_sp_sb(bp
);
5145 sp_sb_data
.state
= SB_ENABLED
;
5146 sp_sb_data
.host_sb_addr
.lo
= U64_LO(section
);
5147 sp_sb_data
.host_sb_addr
.hi
= U64_HI(section
);
5148 sp_sb_data
.igu_sb_id
= igu_sp_sb_index
;
5149 sp_sb_data
.igu_seg_id
= igu_seg_id
;
5150 sp_sb_data
.p_func
.pf_id
= func
;
5151 sp_sb_data
.p_func
.vnic_id
= BP_VN(bp
);
5152 sp_sb_data
.p_func
.vf_id
= 0xff;
5154 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5156 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0, IGU_INT_ENABLE
, 0);
5159 void bnx2x_update_coalesce(struct bnx2x
*bp
)
5163 for_each_eth_queue(bp
, i
)
5164 bnx2x_update_coalesce_sb(bp
, bp
->fp
[i
].fw_sb_id
,
5165 bp
->tx_ticks
, bp
->rx_ticks
);
5168 static void bnx2x_init_sp_ring(struct bnx2x
*bp
)
5170 spin_lock_init(&bp
->spq_lock
);
5171 atomic_set(&bp
->cq_spq_left
, MAX_SPQ_PENDING
);
5173 bp
->spq_prod_idx
= 0;
5174 bp
->dsb_sp_prod
= BNX2X_SP_DSB_INDEX
;
5175 bp
->spq_prod_bd
= bp
->spq
;
5176 bp
->spq_last_bd
= bp
->spq_prod_bd
+ MAX_SP_DESC_CNT
;
5179 static void bnx2x_init_eq_ring(struct bnx2x
*bp
)
5182 for (i
= 1; i
<= NUM_EQ_PAGES
; i
++) {
5183 union event_ring_elem
*elem
=
5184 &bp
->eq_ring
[EQ_DESC_CNT_PAGE
* i
- 1];
5186 elem
->next_page
.addr
.hi
=
5187 cpu_to_le32(U64_HI(bp
->eq_mapping
+
5188 BCM_PAGE_SIZE
* (i
% NUM_EQ_PAGES
)));
5189 elem
->next_page
.addr
.lo
=
5190 cpu_to_le32(U64_LO(bp
->eq_mapping
+
5191 BCM_PAGE_SIZE
*(i
% NUM_EQ_PAGES
)));
5194 bp
->eq_prod
= NUM_EQ_DESC
;
5195 bp
->eq_cons_sb
= BNX2X_EQ_INDEX
;
5196 /* we want a warning message before it gets rought... */
5197 atomic_set(&bp
->eq_spq_left
,
5198 min_t(int, MAX_SP_DESC_CNT
- MAX_SPQ_PENDING
, NUM_EQ_DESC
) - 1);
5202 /* called with netif_addr_lock_bh() */
5203 void bnx2x_set_q_rx_mode(struct bnx2x
*bp
, u8 cl_id
,
5204 unsigned long rx_mode_flags
,
5205 unsigned long rx_accept_flags
,
5206 unsigned long tx_accept_flags
,
5207 unsigned long ramrod_flags
)
5209 struct bnx2x_rx_mode_ramrod_params ramrod_param
;
5212 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
5214 /* Prepare ramrod parameters */
5215 ramrod_param
.cid
= 0;
5216 ramrod_param
.cl_id
= cl_id
;
5217 ramrod_param
.rx_mode_obj
= &bp
->rx_mode_obj
;
5218 ramrod_param
.func_id
= BP_FUNC(bp
);
5220 ramrod_param
.pstate
= &bp
->sp_state
;
5221 ramrod_param
.state
= BNX2X_FILTER_RX_MODE_PENDING
;
5223 ramrod_param
.rdata
= bnx2x_sp(bp
, rx_mode_rdata
);
5224 ramrod_param
.rdata_mapping
= bnx2x_sp_mapping(bp
, rx_mode_rdata
);
5226 set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
5228 ramrod_param
.ramrod_flags
= ramrod_flags
;
5229 ramrod_param
.rx_mode_flags
= rx_mode_flags
;
5231 ramrod_param
.rx_accept_flags
= rx_accept_flags
;
5232 ramrod_param
.tx_accept_flags
= tx_accept_flags
;
5234 rc
= bnx2x_config_rx_mode(bp
, &ramrod_param
);
5236 BNX2X_ERR("Set rx_mode %d failed\n", bp
->rx_mode
);
5241 /* called with netif_addr_lock_bh() */
5242 void bnx2x_set_storm_rx_mode(struct bnx2x
*bp
)
5244 unsigned long rx_mode_flags
= 0, ramrod_flags
= 0;
5245 unsigned long rx_accept_flags
= 0, tx_accept_flags
= 0;
5250 /* Configure rx_mode of FCoE Queue */
5251 __set_bit(BNX2X_RX_MODE_FCOE_ETH
, &rx_mode_flags
);
5254 switch (bp
->rx_mode
) {
5255 case BNX2X_RX_MODE_NONE
:
5257 * 'drop all' supersedes any accept flags that may have been
5258 * passed to the function.
5261 case BNX2X_RX_MODE_NORMAL
:
5262 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5263 __set_bit(BNX2X_ACCEPT_MULTICAST
, &rx_accept_flags
);
5264 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5266 /* internal switching mode */
5267 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5268 __set_bit(BNX2X_ACCEPT_MULTICAST
, &tx_accept_flags
);
5269 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5272 case BNX2X_RX_MODE_ALLMULTI
:
5273 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5274 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &rx_accept_flags
);
5275 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5277 /* internal switching mode */
5278 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5279 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &tx_accept_flags
);
5280 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5283 case BNX2X_RX_MODE_PROMISC
:
5284 /* According to deffinition of SI mode, iface in promisc mode
5285 * should receive matched and unmatched (in resolution of port)
5288 __set_bit(BNX2X_ACCEPT_UNMATCHED
, &rx_accept_flags
);
5289 __set_bit(BNX2X_ACCEPT_UNICAST
, &rx_accept_flags
);
5290 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &rx_accept_flags
);
5291 __set_bit(BNX2X_ACCEPT_BROADCAST
, &rx_accept_flags
);
5293 /* internal switching mode */
5294 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &tx_accept_flags
);
5295 __set_bit(BNX2X_ACCEPT_BROADCAST
, &tx_accept_flags
);
5298 __set_bit(BNX2X_ACCEPT_ALL_UNICAST
, &tx_accept_flags
);
5300 __set_bit(BNX2X_ACCEPT_UNICAST
, &tx_accept_flags
);
5304 BNX2X_ERR("Unknown rx_mode: %d\n", bp
->rx_mode
);
5308 if (bp
->rx_mode
!= BNX2X_RX_MODE_NONE
) {
5309 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &rx_accept_flags
);
5310 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &tx_accept_flags
);
5313 __set_bit(RAMROD_RX
, &ramrod_flags
);
5314 __set_bit(RAMROD_TX
, &ramrod_flags
);
5316 bnx2x_set_q_rx_mode(bp
, bp
->fp
->cl_id
, rx_mode_flags
, rx_accept_flags
,
5317 tx_accept_flags
, ramrod_flags
);
5320 static void bnx2x_init_internal_common(struct bnx2x
*bp
)
5326 * In switch independent mode, the TSTORM needs to accept
5327 * packets that failed classification, since approximate match
5328 * mac addresses aren't written to NIG LLH
5330 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5331 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 2);
5332 else if (!CHIP_IS_E1(bp
)) /* 57710 doesn't support MF */
5333 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
5334 TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET
, 0);
5336 /* Zero this manually as its initialization is
5337 currently missing in the initTool */
5338 for (i
= 0; i
< (USTORM_AGG_DATA_SIZE
>> 2); i
++)
5339 REG_WR(bp
, BAR_USTRORM_INTMEM
+
5340 USTORM_AGG_DATA_OFFSET
+ i
* 4, 0);
5341 if (!CHIP_IS_E1x(bp
)) {
5342 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_IGU_MODE_OFFSET
,
5343 CHIP_INT_MODE_IS_BC(bp
) ?
5344 HC_IGU_BC_MODE
: HC_IGU_NBC_MODE
);
5348 static void bnx2x_init_internal(struct bnx2x
*bp
, u32 load_code
)
5350 switch (load_code
) {
5351 case FW_MSG_CODE_DRV_LOAD_COMMON
:
5352 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
:
5353 bnx2x_init_internal_common(bp
);
5356 case FW_MSG_CODE_DRV_LOAD_PORT
:
5360 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
5361 /* internal memory per function is
5362 initialized inside bnx2x_pf_init */
5366 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
5371 static inline u8
bnx2x_fp_igu_sb_id(struct bnx2x_fastpath
*fp
)
5373 return fp
->bp
->igu_base_sb
+ fp
->index
+ CNIC_PRESENT
;
5376 static inline u8
bnx2x_fp_fw_sb_id(struct bnx2x_fastpath
*fp
)
5378 return fp
->bp
->base_fw_ndsb
+ fp
->index
+ CNIC_PRESENT
;
5381 static inline u8
bnx2x_fp_cl_id(struct bnx2x_fastpath
*fp
)
5383 if (CHIP_IS_E1x(fp
->bp
))
5384 return BP_L_ID(fp
->bp
) + fp
->index
;
5385 else /* We want Client ID to be the same as IGU SB ID for 57712 */
5386 return bnx2x_fp_igu_sb_id(fp
);
5389 static void bnx2x_init_eth_fp(struct bnx2x
*bp
, int fp_idx
)
5391 struct bnx2x_fastpath
*fp
= &bp
->fp
[fp_idx
];
5393 unsigned long q_type
= 0;
5394 u32 cids
[BNX2X_MULTI_TX_COS
] = { 0 };
5395 fp
->rx_queue
= fp_idx
;
5397 fp
->cl_id
= bnx2x_fp_cl_id(fp
);
5398 fp
->fw_sb_id
= bnx2x_fp_fw_sb_id(fp
);
5399 fp
->igu_sb_id
= bnx2x_fp_igu_sb_id(fp
);
5400 /* qZone id equals to FW (per path) client id */
5401 fp
->cl_qzone_id
= bnx2x_fp_qzone_id(fp
);
5404 fp
->ustorm_rx_prods_offset
= bnx2x_rx_ustorm_prods_offset(fp
);
5406 /* Setup SB indicies */
5407 fp
->rx_cons_sb
= BNX2X_RX_SB_INDEX
;
5409 /* Configure Queue State object */
5410 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
5411 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
5413 BUG_ON(fp
->max_cos
> BNX2X_MULTI_TX_COS
);
5416 for_each_cos_in_tx_queue(fp
, cos
) {
5417 bnx2x_init_txdata(bp
, &fp
->txdata
[cos
],
5418 CID_COS_TO_TX_ONLY_CID(fp
->cid
, cos
),
5419 FP_COS_TO_TXQ(fp
, cos
),
5420 BNX2X_TX_SB_INDEX_BASE
+ cos
);
5421 cids
[cos
] = fp
->txdata
[cos
].cid
;
5424 bnx2x_init_queue_obj(bp
, &fp
->q_obj
, fp
->cl_id
, cids
, fp
->max_cos
,
5425 BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
5426 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
5429 * Configure classification DBs: Always enable Tx switching
5431 bnx2x_init_vlan_mac_fp_objs(fp
, BNX2X_OBJ_TYPE_RX_TX
);
5433 DP(NETIF_MSG_IFUP
, "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
5434 fp_idx
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
5436 bnx2x_init_sb(bp
, fp
->status_blk_mapping
, BNX2X_VF_ID_INVALID
, false,
5437 fp
->fw_sb_id
, fp
->igu_sb_id
);
5439 bnx2x_update_fpsb_idx(fp
);
5442 void bnx2x_nic_init(struct bnx2x
*bp
, u32 load_code
)
5446 for_each_eth_queue(bp
, i
)
5447 bnx2x_init_eth_fp(bp
, i
);
5450 bnx2x_init_fcoe_fp(bp
);
5452 bnx2x_init_sb(bp
, bp
->cnic_sb_mapping
,
5453 BNX2X_VF_ID_INVALID
, false,
5454 bnx2x_cnic_fw_sb_id(bp
), bnx2x_cnic_igu_sb_id(bp
));
5458 /* Initialize MOD_ABS interrupts */
5459 bnx2x_init_mod_abs_int(bp
, &bp
->link_vars
, bp
->common
.chip_id
,
5460 bp
->common
.shmem_base
, bp
->common
.shmem2_base
,
5462 /* ensure status block indices were read */
5465 bnx2x_init_def_sb(bp
);
5466 bnx2x_update_dsb_idx(bp
);
5467 bnx2x_init_rx_rings(bp
);
5468 bnx2x_init_tx_rings(bp
);
5469 bnx2x_init_sp_ring(bp
);
5470 bnx2x_init_eq_ring(bp
);
5471 bnx2x_init_internal(bp
, load_code
);
5473 bnx2x_stats_init(bp
);
5475 /* flush all before enabling interrupts */
5479 bnx2x_int_enable(bp
);
5481 /* Check for SPIO5 */
5482 bnx2x_attn_int_deasserted0(bp
,
5483 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ BP_PORT(bp
)*4) &
5484 AEU_INPUTS_ATTN_BITS_SPIO5
);
5487 /* end of nic init */
5490 * gzip service functions
5493 static int bnx2x_gunzip_init(struct bnx2x
*bp
)
5495 bp
->gunzip_buf
= dma_alloc_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
,
5496 &bp
->gunzip_mapping
, GFP_KERNEL
);
5497 if (bp
->gunzip_buf
== NULL
)
5500 bp
->strm
= kmalloc(sizeof(*bp
->strm
), GFP_KERNEL
);
5501 if (bp
->strm
== NULL
)
5504 bp
->strm
->workspace
= vmalloc(zlib_inflate_workspacesize());
5505 if (bp
->strm
->workspace
== NULL
)
5515 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
5516 bp
->gunzip_mapping
);
5517 bp
->gunzip_buf
= NULL
;
5520 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
5524 static void bnx2x_gunzip_end(struct bnx2x
*bp
)
5527 vfree(bp
->strm
->workspace
);
5532 if (bp
->gunzip_buf
) {
5533 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
5534 bp
->gunzip_mapping
);
5535 bp
->gunzip_buf
= NULL
;
5539 static int bnx2x_gunzip(struct bnx2x
*bp
, const u8
*zbuf
, int len
)
5543 /* check gzip header */
5544 if ((zbuf
[0] != 0x1f) || (zbuf
[1] != 0x8b) || (zbuf
[2] != Z_DEFLATED
)) {
5545 BNX2X_ERR("Bad gzip header\n");
5553 if (zbuf
[3] & FNAME
)
5554 while ((zbuf
[n
++] != 0) && (n
< len
));
5556 bp
->strm
->next_in
= (typeof(bp
->strm
->next_in
))zbuf
+ n
;
5557 bp
->strm
->avail_in
= len
- n
;
5558 bp
->strm
->next_out
= bp
->gunzip_buf
;
5559 bp
->strm
->avail_out
= FW_BUF_SIZE
;
5561 rc
= zlib_inflateInit2(bp
->strm
, -MAX_WBITS
);
5565 rc
= zlib_inflate(bp
->strm
, Z_FINISH
);
5566 if ((rc
!= Z_OK
) && (rc
!= Z_STREAM_END
))
5567 netdev_err(bp
->dev
, "Firmware decompression error: %s\n",
5570 bp
->gunzip_outlen
= (FW_BUF_SIZE
- bp
->strm
->avail_out
);
5571 if (bp
->gunzip_outlen
& 0x3)
5573 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
5575 bp
->gunzip_outlen
>>= 2;
5577 zlib_inflateEnd(bp
->strm
);
5579 if (rc
== Z_STREAM_END
)
5585 /* nic load/unload */
5588 * General service functions
5591 /* send a NIG loopback debug packet */
5592 static void bnx2x_lb_pckt(struct bnx2x
*bp
)
5596 /* Ethernet source and destination addresses */
5597 wb_write
[0] = 0x55555555;
5598 wb_write
[1] = 0x55555555;
5599 wb_write
[2] = 0x20; /* SOP */
5600 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
5602 /* NON-IP protocol */
5603 wb_write
[0] = 0x09000000;
5604 wb_write
[1] = 0x55555555;
5605 wb_write
[2] = 0x10; /* EOP, eop_bvalid = 0 */
5606 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
5609 /* some of the internal memories
5610 * are not directly readable from the driver
5611 * to test them we send debug packets
5613 static int bnx2x_int_mem_test(struct bnx2x
*bp
)
5619 if (CHIP_REV_IS_FPGA(bp
))
5621 else if (CHIP_REV_IS_EMUL(bp
))
5626 /* Disable inputs of parser neighbor blocks */
5627 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
5628 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
5629 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
5630 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
5632 /* Write 0 to parser credits for CFC search request */
5633 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
5635 /* send Ethernet packet */
5638 /* TODO do i reset NIG statistic? */
5639 /* Wait until NIG register shows 1 packet of size 0x10 */
5640 count
= 1000 * factor
;
5643 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
5644 val
= *bnx2x_sp(bp
, wb_data
[0]);
5652 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
5656 /* Wait until PRS register shows 1 packet */
5657 count
= 1000 * factor
;
5659 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5667 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5671 /* Reset and init BRB, PRS */
5672 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
5674 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
5676 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
5677 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
5679 DP(NETIF_MSG_HW
, "part2\n");
5681 /* Disable inputs of parser neighbor blocks */
5682 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
5683 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
5684 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
5685 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
5687 /* Write 0 to parser credits for CFC search request */
5688 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
5690 /* send 10 Ethernet packets */
5691 for (i
= 0; i
< 10; i
++)
5694 /* Wait until NIG register shows 10 + 1
5695 packets of size 11*0x10 = 0xb0 */
5696 count
= 1000 * factor
;
5699 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
5700 val
= *bnx2x_sp(bp
, wb_data
[0]);
5708 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
5712 /* Wait until PRS register shows 2 packets */
5713 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5715 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5717 /* Write 1 to parser credits for CFC search request */
5718 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x1);
5720 /* Wait until PRS register shows 3 packets */
5721 msleep(10 * factor
);
5722 /* Wait until NIG register shows 1 packet of size 0x10 */
5723 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
5725 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
5727 /* clear NIG EOP FIFO */
5728 for (i
= 0; i
< 11; i
++)
5729 REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_FIFO
);
5730 val
= REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_EMPTY
);
5732 BNX2X_ERR("clear of NIG failed\n");
5736 /* Reset and init BRB, PRS, NIG */
5737 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
5739 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
5741 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
5742 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
5745 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
5748 /* Enable inputs of parser neighbor blocks */
5749 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x7fffffff);
5750 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x1);
5751 REG_WR(bp
, CFC_REG_DEBUG0
, 0x0);
5752 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x1);
5754 DP(NETIF_MSG_HW
, "done\n");
5759 static void bnx2x_enable_blocks_attention(struct bnx2x
*bp
)
5761 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
5762 if (!CHIP_IS_E1x(bp
))
5763 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0x40);
5765 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0);
5766 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
5767 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
5769 * mask read length error interrupts in brb for parser
5770 * (parsing unit and 'checksum and crc' unit)
5771 * these errors are legal (PU reads fixed length and CAC can cause
5772 * read length error on truncated packets)
5774 REG_WR(bp
, BRB1_REG_BRB1_INT_MASK
, 0xFC00);
5775 REG_WR(bp
, QM_REG_QM_INT_MASK
, 0);
5776 REG_WR(bp
, TM_REG_TM_INT_MASK
, 0);
5777 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_0
, 0);
5778 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_1
, 0);
5779 REG_WR(bp
, XCM_REG_XCM_INT_MASK
, 0);
5780 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
5781 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
5782 REG_WR(bp
, USDM_REG_USDM_INT_MASK_0
, 0);
5783 REG_WR(bp
, USDM_REG_USDM_INT_MASK_1
, 0);
5784 REG_WR(bp
, UCM_REG_UCM_INT_MASK
, 0);
5785 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
5786 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
5787 REG_WR(bp
, GRCBASE_UPB
+ PB_REG_PB_INT_MASK
, 0);
5788 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_0
, 0);
5789 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_1
, 0);
5790 REG_WR(bp
, CCM_REG_CCM_INT_MASK
, 0);
5791 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
5792 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
5794 if (CHIP_REV_IS_FPGA(bp
))
5795 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, 0x580000);
5796 else if (!CHIP_IS_E1x(bp
))
5797 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
,
5798 (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
5799 | PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
5800 | PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
5801 | PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
5802 | PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
));
5804 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, 0x480000);
5805 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_0
, 0);
5806 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_1
, 0);
5807 REG_WR(bp
, TCM_REG_TCM_INT_MASK
, 0);
5808 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
5810 if (!CHIP_IS_E1x(bp
))
5811 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
5812 REG_WR(bp
, TSEM_REG_TSEM_INT_MASK_1
, 0x07ff);
5814 REG_WR(bp
, CDU_REG_CDU_INT_MASK
, 0);
5815 REG_WR(bp
, DMAE_REG_DMAE_INT_MASK
, 0);
5816 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
5817 REG_WR(bp
, PBF_REG_PBF_INT_MASK
, 0x18); /* bit 3,4 masked */
5820 static void bnx2x_reset_common(struct bnx2x
*bp
)
5825 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
5828 if (CHIP_IS_E3(bp
)) {
5829 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
5830 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
5833 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
, val
);
5836 static void bnx2x_setup_dmae(struct bnx2x
*bp
)
5839 spin_lock_init(&bp
->dmae_lock
);
5842 static void bnx2x_init_pxp(struct bnx2x
*bp
)
5845 int r_order
, w_order
;
5847 pci_read_config_word(bp
->pdev
,
5848 pci_pcie_cap(bp
->pdev
) + PCI_EXP_DEVCTL
, &devctl
);
5849 DP(NETIF_MSG_HW
, "read 0x%x from devctl\n", devctl
);
5850 w_order
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
5852 r_order
= ((devctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
5854 DP(NETIF_MSG_HW
, "force read order to %d\n", bp
->mrrs
);
5858 bnx2x_init_pxp_arb(bp
, r_order
, w_order
);
5861 static void bnx2x_setup_fan_failure_detection(struct bnx2x
*bp
)
5871 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config2
) &
5872 SHARED_HW_CFG_FAN_FAILURE_MASK
;
5874 if (val
== SHARED_HW_CFG_FAN_FAILURE_ENABLED
)
5878 * The fan failure mechanism is usually related to the PHY type since
5879 * the power consumption of the board is affected by the PHY. Currently,
5880 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
5882 else if (val
== SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE
)
5883 for (port
= PORT_0
; port
< PORT_MAX
; port
++) {
5885 bnx2x_fan_failure_det_req(
5887 bp
->common
.shmem_base
,
5888 bp
->common
.shmem2_base
,
5892 DP(NETIF_MSG_HW
, "fan detection setting: %d\n", is_required
);
5894 if (is_required
== 0)
5897 /* Fan failure is indicated by SPIO 5 */
5898 bnx2x_set_spio(bp
, MISC_REGISTERS_SPIO_5
,
5899 MISC_REGISTERS_SPIO_INPUT_HI_Z
);
5901 /* set to active low mode */
5902 val
= REG_RD(bp
, MISC_REG_SPIO_INT
);
5903 val
|= ((1 << MISC_REGISTERS_SPIO_5
) <<
5904 MISC_REGISTERS_SPIO_INT_OLD_SET_POS
);
5905 REG_WR(bp
, MISC_REG_SPIO_INT
, val
);
5907 /* enable interrupt to signal the IGU */
5908 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
5909 val
|= (1 << MISC_REGISTERS_SPIO_5
);
5910 REG_WR(bp
, MISC_REG_SPIO_EVENT_EN
, val
);
5913 static void bnx2x_pretend_func(struct bnx2x
*bp
, u8 pretend_func_num
)
5919 if (CHIP_IS_E1H(bp
) && (pretend_func_num
>= E1H_FUNC_MAX
))
5922 switch (BP_ABS_FUNC(bp
)) {
5924 offset
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
5927 offset
= PXP2_REG_PGL_PRETEND_FUNC_F1
;
5930 offset
= PXP2_REG_PGL_PRETEND_FUNC_F2
;
5933 offset
= PXP2_REG_PGL_PRETEND_FUNC_F3
;
5936 offset
= PXP2_REG_PGL_PRETEND_FUNC_F4
;
5939 offset
= PXP2_REG_PGL_PRETEND_FUNC_F5
;
5942 offset
= PXP2_REG_PGL_PRETEND_FUNC_F6
;
5945 offset
= PXP2_REG_PGL_PRETEND_FUNC_F7
;
5951 REG_WR(bp
, offset
, pretend_func_num
);
5953 DP(NETIF_MSG_HW
, "Pretending to func %d\n", pretend_func_num
);
5956 void bnx2x_pf_disable(struct bnx2x
*bp
)
5958 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
5959 val
&= ~IGU_PF_CONF_FUNC_EN
;
5961 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
5962 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
5963 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 0);
5966 static inline void bnx2x__common_init_phy(struct bnx2x
*bp
)
5968 u32 shmem_base
[2], shmem2_base
[2];
5969 shmem_base
[0] = bp
->common
.shmem_base
;
5970 shmem2_base
[0] = bp
->common
.shmem2_base
;
5971 if (!CHIP_IS_E1x(bp
)) {
5973 SHMEM2_RD(bp
, other_shmem_base_addr
);
5975 SHMEM2_RD(bp
, other_shmem2_base_addr
);
5977 bnx2x_acquire_phy_lock(bp
);
5978 bnx2x_common_init_phy(bp
, shmem_base
, shmem2_base
,
5979 bp
->common
.chip_id
);
5980 bnx2x_release_phy_lock(bp
);
5984 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
5986 * @bp: driver handle
5988 static int bnx2x_init_hw_common(struct bnx2x
*bp
)
5992 DP(NETIF_MSG_HW
, "starting common init func %d\n", BP_ABS_FUNC(bp
));
5995 * take the UNDI lock to protect undi_unload flow from accessing
5996 * registers while we're resetting the chip
5998 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
6000 bnx2x_reset_common(bp
);
6001 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0xffffffff);
6004 if (CHIP_IS_E3(bp
)) {
6005 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
6006 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
6008 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
, val
);
6010 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
6012 bnx2x_init_block(bp
, BLOCK_MISC
, PHASE_COMMON
);
6014 if (!CHIP_IS_E1x(bp
)) {
6018 * 4-port mode or 2-port mode we need to turn of master-enable
6019 * for everyone, after that, turn it back on for self.
6020 * so, we disregard multi-function or not, and always disable
6021 * for all functions on the given path, this means 0,2,4,6 for
6022 * path 0 and 1,3,5,7 for path 1
6024 for (abs_func_id
= BP_PATH(bp
);
6025 abs_func_id
< E2_FUNC_MAX
*2; abs_func_id
+= 2) {
6026 if (abs_func_id
== BP_ABS_FUNC(bp
)) {
6028 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
,
6033 bnx2x_pretend_func(bp
, abs_func_id
);
6034 /* clear pf enable */
6035 bnx2x_pf_disable(bp
);
6036 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
6040 bnx2x_init_block(bp
, BLOCK_PXP
, PHASE_COMMON
);
6041 if (CHIP_IS_E1(bp
)) {
6042 /* enable HW interrupt from PXP on USDM overflow
6043 bit 16 on INT_MASK_0 */
6044 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
6047 bnx2x_init_block(bp
, BLOCK_PXP2
, PHASE_COMMON
);
6051 REG_WR(bp
, PXP2_REG_RQ_QM_ENDIAN_M
, 1);
6052 REG_WR(bp
, PXP2_REG_RQ_TM_ENDIAN_M
, 1);
6053 REG_WR(bp
, PXP2_REG_RQ_SRC_ENDIAN_M
, 1);
6054 REG_WR(bp
, PXP2_REG_RQ_CDU_ENDIAN_M
, 1);
6055 REG_WR(bp
, PXP2_REG_RQ_DBG_ENDIAN_M
, 1);
6056 /* make sure this value is 0 */
6057 REG_WR(bp
, PXP2_REG_RQ_HC_ENDIAN_M
, 0);
6059 /* REG_WR(bp, PXP2_REG_RD_PBF_SWAP_MODE, 1); */
6060 REG_WR(bp
, PXP2_REG_RD_QM_SWAP_MODE
, 1);
6061 REG_WR(bp
, PXP2_REG_RD_TM_SWAP_MODE
, 1);
6062 REG_WR(bp
, PXP2_REG_RD_SRC_SWAP_MODE
, 1);
6063 REG_WR(bp
, PXP2_REG_RD_CDURD_SWAP_MODE
, 1);
6066 bnx2x_ilt_init_page_size(bp
, INITOP_SET
);
6068 if (CHIP_REV_IS_FPGA(bp
) && CHIP_IS_E1H(bp
))
6069 REG_WR(bp
, PXP2_REG_PGL_TAGS_LIMIT
, 0x1);
6071 /* let the HW do it's magic ... */
6073 /* finish PXP init */
6074 val
= REG_RD(bp
, PXP2_REG_RQ_CFG_DONE
);
6076 BNX2X_ERR("PXP2 CFG failed\n");
6079 val
= REG_RD(bp
, PXP2_REG_RD_INIT_DONE
);
6081 BNX2X_ERR("PXP2 RD_INIT failed\n");
6085 /* Timers bug workaround E2 only. We need to set the entire ILT to
6086 * have entries with value "0" and valid bit on.
6087 * This needs to be done by the first PF that is loaded in a path
6088 * (i.e. common phase)
6090 if (!CHIP_IS_E1x(bp
)) {
6091 /* In E2 there is a bug in the timers block that can cause function 6 / 7
6092 * (i.e. vnic3) to start even if it is marked as "scan-off".
6093 * This occurs when a different function (func2,3) is being marked
6094 * as "scan-off". Real-life scenario for example: if a driver is being
6095 * load-unloaded while func6,7 are down. This will cause the timer to access
6096 * the ilt, translate to a logical address and send a request to read/write.
6097 * Since the ilt for the function that is down is not valid, this will cause
6098 * a translation error which is unrecoverable.
6099 * The Workaround is intended to make sure that when this happens nothing fatal
6100 * will occur. The workaround:
6101 * 1. First PF driver which loads on a path will:
6102 * a. After taking the chip out of reset, by using pretend,
6103 * it will write "0" to the following registers of
6105 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
6106 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
6107 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
6108 * And for itself it will write '1' to
6109 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
6110 * dmae-operations (writing to pram for example.)
6111 * note: can be done for only function 6,7 but cleaner this
6113 * b. Write zero+valid to the entire ILT.
6114 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
6115 * VNIC3 (of that port). The range allocated will be the
6116 * entire ILT. This is needed to prevent ILT range error.
6117 * 2. Any PF driver load flow:
6118 * a. ILT update with the physical addresses of the allocated
6120 * b. Wait 20msec. - note that this timeout is needed to make
6121 * sure there are no requests in one of the PXP internal
6122 * queues with "old" ILT addresses.
6123 * c. PF enable in the PGLC.
6124 * d. Clear the was_error of the PF in the PGLC. (could have
6125 * occured while driver was down)
6126 * e. PF enable in the CFC (WEAK + STRONG)
6127 * f. Timers scan enable
6128 * 3. PF driver unload flow:
6129 * a. Clear the Timers scan_en.
6130 * b. Polling for scan_on=0 for that PF.
6131 * c. Clear the PF enable bit in the PXP.
6132 * d. Clear the PF enable in the CFC (WEAK + STRONG)
6133 * e. Write zero+valid to all ILT entries (The valid bit must
6135 * f. If this is VNIC 3 of a port then also init
6136 * first_timers_ilt_entry to zero and last_timers_ilt_entry
6137 * to the last enrty in the ILT.
6140 * Currently the PF error in the PGLC is non recoverable.
6141 * In the future the there will be a recovery routine for this error.
6142 * Currently attention is masked.
6143 * Having an MCP lock on the load/unload process does not guarantee that
6144 * there is no Timer disable during Func6/7 enable. This is because the
6145 * Timers scan is currently being cleared by the MCP on FLR.
6146 * Step 2.d can be done only for PF6/7 and the driver can also check if
6147 * there is error before clearing it. But the flow above is simpler and
6149 * All ILT entries are written by zero+valid and not just PF6/7
6150 * ILT entries since in the future the ILT entries allocation for
6151 * PF-s might be dynamic.
6153 struct ilt_client_info ilt_cli
;
6154 struct bnx2x_ilt ilt
;
6155 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
6156 memset(&ilt
, 0, sizeof(struct bnx2x_ilt
));
6158 /* initialize dummy TM client */
6160 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
6161 ilt_cli
.client_num
= ILT_CLIENT_TM
;
6163 /* Step 1: set zeroes to all ilt page entries with valid bit on
6164 * Step 2: set the timers first/last ilt entry to point
6165 * to the entire range to prevent ILT range error for 3rd/4th
6166 * vnic (this code assumes existance of the vnic)
6168 * both steps performed by call to bnx2x_ilt_client_init_op()
6169 * with dummy TM client
6171 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
6172 * and his brother are split registers
6174 bnx2x_pretend_func(bp
, (BP_PATH(bp
) + 6));
6175 bnx2x_ilt_client_init_op_ilt(bp
, &ilt
, &ilt_cli
, INITOP_CLEAR
);
6176 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
6178 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN
, BNX2X_PXP_DRAM_ALIGN
);
6179 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_RD
, BNX2X_PXP_DRAM_ALIGN
);
6180 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_SEL
, 1);
6184 REG_WR(bp
, PXP2_REG_RQ_DISABLE_INPUTS
, 0);
6185 REG_WR(bp
, PXP2_REG_RD_DISABLE_INPUTS
, 0);
6187 if (!CHIP_IS_E1x(bp
)) {
6188 int factor
= CHIP_REV_IS_EMUL(bp
) ? 1000 :
6189 (CHIP_REV_IS_FPGA(bp
) ? 400 : 0);
6190 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, PHASE_COMMON
);
6192 bnx2x_init_block(bp
, BLOCK_ATC
, PHASE_COMMON
);
6194 /* let the HW do it's magic ... */
6197 val
= REG_RD(bp
, ATC_REG_ATC_INIT_DONE
);
6198 } while (factor
-- && (val
!= 1));
6201 BNX2X_ERR("ATC_INIT failed\n");
6206 bnx2x_init_block(bp
, BLOCK_DMAE
, PHASE_COMMON
);
6208 /* clean the DMAE memory */
6210 bnx2x_init_fill(bp
, TSEM_REG_PRAM
, 0, 8, 1);
6212 bnx2x_init_block(bp
, BLOCK_TCM
, PHASE_COMMON
);
6214 bnx2x_init_block(bp
, BLOCK_UCM
, PHASE_COMMON
);
6216 bnx2x_init_block(bp
, BLOCK_CCM
, PHASE_COMMON
);
6218 bnx2x_init_block(bp
, BLOCK_XCM
, PHASE_COMMON
);
6220 bnx2x_read_dmae(bp
, XSEM_REG_PASSIVE_BUFFER
, 3);
6221 bnx2x_read_dmae(bp
, CSEM_REG_PASSIVE_BUFFER
, 3);
6222 bnx2x_read_dmae(bp
, TSEM_REG_PASSIVE_BUFFER
, 3);
6223 bnx2x_read_dmae(bp
, USEM_REG_PASSIVE_BUFFER
, 3);
6225 bnx2x_init_block(bp
, BLOCK_QM
, PHASE_COMMON
);
6228 /* QM queues pointers table */
6229 bnx2x_qm_init_ptr_table(bp
, bp
->qm_cid_count
, INITOP_SET
);
6231 /* soft reset pulse */
6232 REG_WR(bp
, QM_REG_SOFT_RESET
, 1);
6233 REG_WR(bp
, QM_REG_SOFT_RESET
, 0);
6236 bnx2x_init_block(bp
, BLOCK_TM
, PHASE_COMMON
);
6239 bnx2x_init_block(bp
, BLOCK_DORQ
, PHASE_COMMON
);
6240 REG_WR(bp
, DORQ_REG_DPM_CID_OFST
, BNX2X_DB_SHIFT
);
6241 if (!CHIP_REV_IS_SLOW(bp
))
6242 /* enable hw interrupt from doorbell Q */
6243 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6245 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6247 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6248 REG_WR(bp
, PRS_REG_A_PRSU_20
, 0xf);
6250 if (!CHIP_IS_E1(bp
))
6251 REG_WR(bp
, PRS_REG_E1HOV_MODE
, bp
->path_has_ovlan
);
6253 if (!CHIP_IS_E1x(bp
) && !CHIP_IS_E3B0(bp
))
6254 /* Bit-map indicating which L2 hdrs may appear
6255 * after the basic Ethernet header
6257 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
,
6258 bp
->path_has_ovlan
? 7 : 6);
6260 bnx2x_init_block(bp
, BLOCK_TSDM
, PHASE_COMMON
);
6261 bnx2x_init_block(bp
, BLOCK_CSDM
, PHASE_COMMON
);
6262 bnx2x_init_block(bp
, BLOCK_USDM
, PHASE_COMMON
);
6263 bnx2x_init_block(bp
, BLOCK_XSDM
, PHASE_COMMON
);
6265 if (!CHIP_IS_E1x(bp
)) {
6266 /* reset VFC memories */
6267 REG_WR(bp
, TSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6268 VFC_MEMORIES_RST_REG_CAM_RST
|
6269 VFC_MEMORIES_RST_REG_RAM_RST
);
6270 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
6271 VFC_MEMORIES_RST_REG_CAM_RST
|
6272 VFC_MEMORIES_RST_REG_RAM_RST
);
6277 bnx2x_init_block(bp
, BLOCK_TSEM
, PHASE_COMMON
);
6278 bnx2x_init_block(bp
, BLOCK_USEM
, PHASE_COMMON
);
6279 bnx2x_init_block(bp
, BLOCK_CSEM
, PHASE_COMMON
);
6280 bnx2x_init_block(bp
, BLOCK_XSEM
, PHASE_COMMON
);
6283 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6285 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
6288 bnx2x_init_block(bp
, BLOCK_UPB
, PHASE_COMMON
);
6289 bnx2x_init_block(bp
, BLOCK_XPB
, PHASE_COMMON
);
6290 bnx2x_init_block(bp
, BLOCK_PBF
, PHASE_COMMON
);
6292 if (!CHIP_IS_E1x(bp
))
6293 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
,
6294 bp
->path_has_ovlan
? 7 : 6);
6296 REG_WR(bp
, SRC_REG_SOFT_RST
, 1);
6298 bnx2x_init_block(bp
, BLOCK_SRC
, PHASE_COMMON
);
6301 REG_WR(bp
, SRC_REG_KEYSEARCH_0
, 0x63285672);
6302 REG_WR(bp
, SRC_REG_KEYSEARCH_1
, 0x24b8f2cc);
6303 REG_WR(bp
, SRC_REG_KEYSEARCH_2
, 0x223aef9b);
6304 REG_WR(bp
, SRC_REG_KEYSEARCH_3
, 0x26001e3a);
6305 REG_WR(bp
, SRC_REG_KEYSEARCH_4
, 0x7ae91116);
6306 REG_WR(bp
, SRC_REG_KEYSEARCH_5
, 0x5ce5230b);
6307 REG_WR(bp
, SRC_REG_KEYSEARCH_6
, 0x298d8adf);
6308 REG_WR(bp
, SRC_REG_KEYSEARCH_7
, 0x6eb0ff09);
6309 REG_WR(bp
, SRC_REG_KEYSEARCH_8
, 0x1830f82f);
6310 REG_WR(bp
, SRC_REG_KEYSEARCH_9
, 0x01e46be7);
6312 REG_WR(bp
, SRC_REG_SOFT_RST
, 0);
6314 if (sizeof(union cdu_context
) != 1024)
6315 /* we currently assume that a context is 1024 bytes */
6316 dev_alert(&bp
->pdev
->dev
,
6317 "please adjust the size of cdu_context(%ld)\n",
6318 (long)sizeof(union cdu_context
));
6320 bnx2x_init_block(bp
, BLOCK_CDU
, PHASE_COMMON
);
6321 val
= (4 << 24) + (0 << 12) + 1024;
6322 REG_WR(bp
, CDU_REG_CDU_GLOBAL_PARAMS
, val
);
6324 bnx2x_init_block(bp
, BLOCK_CFC
, PHASE_COMMON
);
6325 REG_WR(bp
, CFC_REG_INIT_REG
, 0x7FF);
6326 /* enable context validation interrupt from CFC */
6327 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6329 /* set the thresholds to prevent CFC/CDU race */
6330 REG_WR(bp
, CFC_REG_DEBUG0
, 0x20020000);
6332 bnx2x_init_block(bp
, BLOCK_HC
, PHASE_COMMON
);
6334 if (!CHIP_IS_E1x(bp
) && BP_NOMCP(bp
))
6335 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x36);
6337 bnx2x_init_block(bp
, BLOCK_IGU
, PHASE_COMMON
);
6338 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, PHASE_COMMON
);
6340 /* Reset PCIE errors for debug */
6341 REG_WR(bp
, 0x2814, 0xffffffff);
6342 REG_WR(bp
, 0x3820, 0xffffffff);
6344 if (!CHIP_IS_E1x(bp
)) {
6345 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_CONTROL_5
,
6346 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
|
6347 PXPCS_TL_CONTROL_5_ERR_UNSPPORT
));
6348 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC345_STAT
,
6349 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
|
6350 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
|
6351 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
));
6352 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC678_STAT
,
6353 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
|
6354 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
|
6355 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
));
6358 bnx2x_init_block(bp
, BLOCK_NIG
, PHASE_COMMON
);
6359 if (!CHIP_IS_E1(bp
)) {
6360 /* in E3 this done in per-port section */
6361 if (!CHIP_IS_E3(bp
))
6362 REG_WR(bp
, NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
6364 if (CHIP_IS_E1H(bp
))
6365 /* not applicable for E2 (and above ...) */
6366 REG_WR(bp
, NIG_REG_LLH_E1HOV_MODE
, IS_MF_SD(bp
));
6368 if (CHIP_REV_IS_SLOW(bp
))
6371 /* finish CFC init */
6372 val
= reg_poll(bp
, CFC_REG_LL_INIT_DONE
, 1, 100, 10);
6374 BNX2X_ERR("CFC LL_INIT failed\n");
6377 val
= reg_poll(bp
, CFC_REG_AC_INIT_DONE
, 1, 100, 10);
6379 BNX2X_ERR("CFC AC_INIT failed\n");
6382 val
= reg_poll(bp
, CFC_REG_CAM_INIT_DONE
, 1, 100, 10);
6384 BNX2X_ERR("CFC CAM_INIT failed\n");
6387 REG_WR(bp
, CFC_REG_DEBUG0
, 0);
6389 if (CHIP_IS_E1(bp
)) {
6390 /* read NIG statistic
6391 to see if this is our first up since powerup */
6392 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6393 val
= *bnx2x_sp(bp
, wb_data
[0]);
6395 /* do internal memory self test */
6396 if ((val
== 0) && bnx2x_int_mem_test(bp
)) {
6397 BNX2X_ERR("internal mem self test failed\n");
6402 bnx2x_setup_fan_failure_detection(bp
);
6404 /* clear PXP2 attentions */
6405 REG_RD(bp
, PXP2_REG_PXP2_INT_STS_CLR_0
);
6407 bnx2x_enable_blocks_attention(bp
);
6408 bnx2x_enable_blocks_parity(bp
);
6410 if (!BP_NOMCP(bp
)) {
6411 if (CHIP_IS_E1x(bp
))
6412 bnx2x__common_init_phy(bp
);
6414 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
6420 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
6422 * @bp: driver handle
6424 static int bnx2x_init_hw_common_chip(struct bnx2x
*bp
)
6426 int rc
= bnx2x_init_hw_common(bp
);
6431 /* In E2 2-PORT mode, same ext phy is used for the two paths */
6433 bnx2x__common_init_phy(bp
);
6438 static int bnx2x_init_hw_port(struct bnx2x
*bp
)
6440 int port
= BP_PORT(bp
);
6441 int init_phase
= port
? PHASE_PORT1
: PHASE_PORT0
;
6445 bnx2x__link_reset(bp
);
6447 DP(NETIF_MSG_HW
, "starting port init port %d\n", port
);
6449 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
6451 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
6452 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
6453 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
6455 /* Timers bug workaround: disables the pf_master bit in pglue at
6456 * common phase, we need to enable it here before any dmae access are
6457 * attempted. Therefore we manually added the enable-master to the
6458 * port phase (it also happens in the function phase)
6460 if (!CHIP_IS_E1x(bp
))
6461 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
6463 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
6464 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
6465 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
6466 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
6468 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
6469 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
6470 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
6471 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
6473 /* QM cid (connection) count */
6474 bnx2x_qm_init_cid_count(bp
, bp
->qm_cid_count
, INITOP_SET
);
6477 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
6478 REG_WR(bp
, TM_REG_LIN0_SCAN_TIME
+ port
*4, 20);
6479 REG_WR(bp
, TM_REG_LIN0_MAX_ACTIVE_CID
+ port
*4, 31);
6482 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
6484 if (CHIP_IS_E1(bp
) || CHIP_IS_E1H(bp
)) {
6485 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
6488 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 160 : 246);
6489 else if (bp
->dev
->mtu
> 4096) {
6490 if (bp
->flags
& ONE_PORT_FLAG
)
6494 /* (24*1024 + val*4)/256 */
6495 low
= 96 + (val
/64) +
6496 ((val
% 64) ? 1 : 0);
6499 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 80 : 160);
6500 high
= low
+ 56; /* 14*1024/256 */
6501 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_0
+ port
*4, low
);
6502 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_0
+ port
*4, high
);
6505 if (CHIP_MODE_IS_4_PORT(bp
))
6506 REG_WR(bp
, (BP_PORT(bp
) ?
6507 BRB1_REG_MAC_GUARANTIED_1
:
6508 BRB1_REG_MAC_GUARANTIED_0
), 40);
6511 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
6512 if (CHIP_IS_E3B0(bp
))
6513 /* Ovlan exists only if we are in multi-function +
6514 * switch-dependent mode, in switch-independent there
6515 * is no ovlan headers
6517 REG_WR(bp
, BP_PORT(bp
) ?
6518 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
6519 PRS_REG_HDRS_AFTER_BASIC_PORT_0
,
6520 (bp
->path_has_ovlan
? 7 : 6));
6522 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
6523 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
6524 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
6525 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
6527 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
6528 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
6529 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
6530 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
6532 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
6533 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
6535 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
6537 if (CHIP_IS_E1x(bp
)) {
6538 /* configure PBF to work without PAUSE mtu 9000 */
6539 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
6541 /* update threshold */
6542 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, (9040/16));
6543 /* update init credit */
6544 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, (9040/16) + 553 - 22);
6547 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 1);
6549 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0);
6553 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
6555 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
6556 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
6558 if (CHIP_IS_E1(bp
)) {
6559 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
6560 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
6562 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
6564 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
6566 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
6567 /* init aeu_mask_attn_func_0/1:
6568 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use
6569 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF
6570 * bits 4-7 are used for "per vn group attention" */
6571 val
= IS_MF(bp
) ? 0xF7 : 0x7;
6572 /* Enable DCBX attention for all but E1 */
6573 val
|= CHIP_IS_E1(bp
) ? 0 : 0x10;
6574 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, val
);
6576 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
6578 if (!CHIP_IS_E1x(bp
)) {
6579 /* Bit-map indicating which L2 hdrs may appear after the
6580 * basic Ethernet header
6582 REG_WR(bp
, BP_PORT(bp
) ?
6583 NIG_REG_P1_HDRS_AFTER_BASIC
:
6584 NIG_REG_P0_HDRS_AFTER_BASIC
,
6585 IS_MF_SD(bp
) ? 7 : 6);
6588 REG_WR(bp
, BP_PORT(bp
) ?
6589 NIG_REG_LLH1_MF_MODE
:
6590 NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
6592 if (!CHIP_IS_E3(bp
))
6593 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
6595 if (!CHIP_IS_E1(bp
)) {
6596 /* 0x2 disable mf_ov, 0x1 enable */
6597 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ port
*4,
6598 (IS_MF_SD(bp
) ? 0x1 : 0x2));
6600 if (!CHIP_IS_E1x(bp
)) {
6602 switch (bp
->mf_mode
) {
6603 case MULTI_FUNCTION_SD
:
6606 case MULTI_FUNCTION_SI
:
6611 REG_WR(bp
, (BP_PORT(bp
) ? NIG_REG_LLH1_CLS_TYPE
:
6612 NIG_REG_LLH0_CLS_TYPE
), val
);
6615 REG_WR(bp
, NIG_REG_LLFC_ENABLE_0
+ port
*4, 0);
6616 REG_WR(bp
, NIG_REG_LLFC_OUT_EN_0
+ port
*4, 0);
6617 REG_WR(bp
, NIG_REG_PAUSE_ENABLE_0
+ port
*4, 1);
6622 /* If SPIO5 is set to generate interrupts, enable it for this port */
6623 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
6624 if (val
& (1 << MISC_REGISTERS_SPIO_5
)) {
6625 u32 reg_addr
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
6626 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
6627 val
= REG_RD(bp
, reg_addr
);
6628 val
|= AEU_INPUTS_ATTN_BITS_SPIO5
;
6629 REG_WR(bp
, reg_addr
, val
);
6635 static void bnx2x_ilt_wr(struct bnx2x
*bp
, u32 index
, dma_addr_t addr
)
6640 reg
= PXP2_REG_RQ_ONCHIP_AT
+ index
*8;
6642 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ index
*8;
6644 bnx2x_wb_wr(bp
, reg
, ONCHIP_ADDR1(addr
), ONCHIP_ADDR2(addr
));
6647 static inline void bnx2x_igu_clear_sb(struct bnx2x
*bp
, u8 idu_sb_id
)
6649 bnx2x_igu_clear_sb_gen(bp
, BP_FUNC(bp
), idu_sb_id
, true /*PF*/);
6652 static inline void bnx2x_clear_func_ilt(struct bnx2x
*bp
, u32 func
)
6654 u32 i
, base
= FUNC_ILT_BASE(func
);
6655 for (i
= base
; i
< base
+ ILT_PER_FUNC
; i
++)
6656 bnx2x_ilt_wr(bp
, i
, 0);
6659 static int bnx2x_init_hw_func(struct bnx2x
*bp
)
6661 int port
= BP_PORT(bp
);
6662 int func
= BP_FUNC(bp
);
6663 int init_phase
= PHASE_PF0
+ func
;
6664 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
6667 u32 main_mem_base
, main_mem_size
, main_mem_prty_clr
;
6668 int i
, main_mem_width
, rc
;
6670 DP(NETIF_MSG_HW
, "starting func init func %d\n", func
);
6672 /* FLR cleanup - hmmm */
6673 if (!CHIP_IS_E1x(bp
)) {
6674 rc
= bnx2x_pf_flr_clnup(bp
);
6679 /* set MSI reconfigure capability */
6680 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
6681 addr
= (port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
);
6682 val
= REG_RD(bp
, addr
);
6683 val
|= HC_CONFIG_0_REG_MSI_ATTN_EN_0
;
6684 REG_WR(bp
, addr
, val
);
6687 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
6688 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
6691 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
6693 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++) {
6694 ilt
->lines
[cdu_ilt_start
+ i
].page
=
6695 bp
->context
.vcxt
+ (ILT_PAGE_CIDS
* i
);
6696 ilt
->lines
[cdu_ilt_start
+ i
].page_mapping
=
6697 bp
->context
.cxt_mapping
+ (CDU_ILT_PAGE_SZ
* i
);
6698 /* cdu ilt pages are allocated manually so there's no need to
6701 bnx2x_ilt_init_op(bp
, INITOP_SET
);
6704 bnx2x_src_init_t2(bp
, bp
->t2
, bp
->t2_mapping
, SRC_CONN_NUM
);
6706 /* T1 hash bits value determines the T1 number of entries */
6707 REG_WR(bp
, SRC_REG_NUMBER_HASH_BITS0
+ port
*4, SRC_HASH_BITS
);
6712 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
6713 #endif /* BCM_CNIC */
6715 if (!CHIP_IS_E1x(bp
)) {
6716 u32 pf_conf
= IGU_PF_CONF_FUNC_EN
;
6718 /* Turn on a single ISR mode in IGU if driver is going to use
6721 if (!(bp
->flags
& USING_MSIX_FLAG
))
6722 pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
6724 * Timers workaround bug: function init part.
6725 * Need to wait 20msec after initializing ILT,
6726 * needed to make sure there are no requests in
6727 * one of the PXP internal queues with "old" ILT addresses
6731 * Master enable - Due to WB DMAE writes performed before this
6732 * register is re-initialized as part of the regular function
6735 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
6736 /* Enable the function in IGU */
6737 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, pf_conf
);
6742 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
6744 if (!CHIP_IS_E1x(bp
))
6745 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
, func
);
6747 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
6748 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
6749 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
6750 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
6751 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
6752 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
6753 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
6754 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
6755 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
6756 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
6757 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
6758 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
6759 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
6761 if (!CHIP_IS_E1x(bp
))
6762 REG_WR(bp
, QM_REG_PF_EN
, 1);
6764 if (!CHIP_IS_E1x(bp
)) {
6765 REG_WR(bp
, TSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6766 REG_WR(bp
, USEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6767 REG_WR(bp
, CSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6768 REG_WR(bp
, XSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
6770 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
6772 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
6773 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
6774 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
6775 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
6776 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
6777 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
6778 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
6779 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
6780 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
6781 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
6782 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
6783 if (!CHIP_IS_E1x(bp
))
6784 REG_WR(bp
, PBF_REG_DISABLE_PF
, 0);
6786 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
6788 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
6790 if (!CHIP_IS_E1x(bp
))
6791 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 1);
6794 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 1);
6795 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ port
*8, bp
->mf_ov
);
6798 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
6800 /* HC init per function */
6801 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
6802 if (CHIP_IS_E1H(bp
)) {
6803 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
6805 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
6806 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
6808 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
6811 int num_segs
, sb_idx
, prod_offset
;
6813 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
6815 if (!CHIP_IS_E1x(bp
)) {
6816 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
6817 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
6820 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
6822 if (!CHIP_IS_E1x(bp
)) {
6826 * E2 mode: address 0-135 match to the mapping memory;
6827 * 136 - PF0 default prod; 137 - PF1 default prod;
6828 * 138 - PF2 default prod; 139 - PF3 default prod;
6829 * 140 - PF0 attn prod; 141 - PF1 attn prod;
6830 * 142 - PF2 attn prod; 143 - PF3 attn prod;
6833 * E1.5 mode - In backward compatible mode;
6834 * for non default SB; each even line in the memory
6835 * holds the U producer and each odd line hold
6836 * the C producer. The first 128 producers are for
6837 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
6838 * producers are for the DSB for each PF.
6839 * Each PF has five segments: (the order inside each
6840 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
6841 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
6842 * 144-147 attn prods;
6844 /* non-default-status-blocks */
6845 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
6846 IGU_BC_NDSB_NUM_SEGS
: IGU_NORM_NDSB_NUM_SEGS
;
6847 for (sb_idx
= 0; sb_idx
< bp
->igu_sb_cnt
; sb_idx
++) {
6848 prod_offset
= (bp
->igu_base_sb
+ sb_idx
) *
6851 for (i
= 0; i
< num_segs
; i
++) {
6852 addr
= IGU_REG_PROD_CONS_MEMORY
+
6853 (prod_offset
+ i
) * 4;
6854 REG_WR(bp
, addr
, 0);
6856 /* send consumer update with value 0 */
6857 bnx2x_ack_sb(bp
, bp
->igu_base_sb
+ sb_idx
,
6858 USTORM_ID
, 0, IGU_INT_NOP
, 1);
6859 bnx2x_igu_clear_sb(bp
,
6860 bp
->igu_base_sb
+ sb_idx
);
6863 /* default-status-blocks */
6864 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
6865 IGU_BC_DSB_NUM_SEGS
: IGU_NORM_DSB_NUM_SEGS
;
6867 if (CHIP_MODE_IS_4_PORT(bp
))
6868 dsb_idx
= BP_FUNC(bp
);
6870 dsb_idx
= BP_VN(bp
);
6872 prod_offset
= (CHIP_INT_MODE_IS_BC(bp
) ?
6873 IGU_BC_BASE_DSB_PROD
+ dsb_idx
:
6874 IGU_NORM_BASE_DSB_PROD
+ dsb_idx
);
6877 * igu prods come in chunks of E1HVN_MAX (4) -
6878 * does not matters what is the current chip mode
6880 for (i
= 0; i
< (num_segs
* E1HVN_MAX
);
6882 addr
= IGU_REG_PROD_CONS_MEMORY
+
6883 (prod_offset
+ i
)*4;
6884 REG_WR(bp
, addr
, 0);
6886 /* send consumer update with 0 */
6887 if (CHIP_INT_MODE_IS_BC(bp
)) {
6888 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6889 USTORM_ID
, 0, IGU_INT_NOP
, 1);
6890 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6891 CSTORM_ID
, 0, IGU_INT_NOP
, 1);
6892 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6893 XSTORM_ID
, 0, IGU_INT_NOP
, 1);
6894 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6895 TSTORM_ID
, 0, IGU_INT_NOP
, 1);
6896 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6897 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
6899 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6900 USTORM_ID
, 0, IGU_INT_NOP
, 1);
6901 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
6902 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
6904 bnx2x_igu_clear_sb(bp
, bp
->igu_dsb_id
);
6906 /* !!! these should become driver const once
6907 rf-tool supports split-68 const */
6908 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_LSB
, 0);
6909 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_MSB
, 0);
6910 REG_WR(bp
, IGU_REG_SB_MASK_LSB
, 0);
6911 REG_WR(bp
, IGU_REG_SB_MASK_MSB
, 0);
6912 REG_WR(bp
, IGU_REG_PBA_STATUS_LSB
, 0);
6913 REG_WR(bp
, IGU_REG_PBA_STATUS_MSB
, 0);
6917 /* Reset PCIE errors for debug */
6918 REG_WR(bp
, 0x2114, 0xffffffff);
6919 REG_WR(bp
, 0x2120, 0xffffffff);
6921 if (CHIP_IS_E1x(bp
)) {
6922 main_mem_size
= HC_REG_MAIN_MEMORY_SIZE
/ 2; /*dwords*/
6923 main_mem_base
= HC_REG_MAIN_MEMORY
+
6924 BP_PORT(bp
) * (main_mem_size
* 4);
6925 main_mem_prty_clr
= HC_REG_HC_PRTY_STS_CLR
;
6928 val
= REG_RD(bp
, main_mem_prty_clr
);
6931 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
6934 /* Clear "false" parity errors in MSI-X table */
6935 for (i
= main_mem_base
;
6936 i
< main_mem_base
+ main_mem_size
* 4;
6937 i
+= main_mem_width
) {
6938 bnx2x_read_dmae(bp
, i
, main_mem_width
/ 4);
6939 bnx2x_write_dmae(bp
, bnx2x_sp_mapping(bp
, wb_data
),
6940 i
, main_mem_width
/ 4);
6942 /* Clear HC parity attention */
6943 REG_RD(bp
, main_mem_prty_clr
);
6946 #ifdef BNX2X_STOP_ON_ERROR
6947 /* Enable STORMs SP logging */
6948 REG_WR8(bp
, BAR_USTRORM_INTMEM
+
6949 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6950 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
6951 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6952 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
6953 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6954 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+
6955 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
6958 bnx2x_phy_probe(&bp
->link_params
);
6964 void bnx2x_free_mem(struct bnx2x
*bp
)
6967 bnx2x_free_fp_mem(bp
);
6968 /* end of fastpath */
6970 BNX2X_PCI_FREE(bp
->def_status_blk
, bp
->def_status_blk_mapping
,
6971 sizeof(struct host_sp_status_block
));
6973 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
6974 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
6976 BNX2X_PCI_FREE(bp
->slowpath
, bp
->slowpath_mapping
,
6977 sizeof(struct bnx2x_slowpath
));
6979 BNX2X_PCI_FREE(bp
->context
.vcxt
, bp
->context
.cxt_mapping
,
6982 bnx2x_ilt_mem_op(bp
, ILT_MEMOP_FREE
);
6984 BNX2X_FREE(bp
->ilt
->lines
);
6987 if (!CHIP_IS_E1x(bp
))
6988 BNX2X_PCI_FREE(bp
->cnic_sb
.e2_sb
, bp
->cnic_sb_mapping
,
6989 sizeof(struct host_hc_status_block_e2
));
6991 BNX2X_PCI_FREE(bp
->cnic_sb
.e1x_sb
, bp
->cnic_sb_mapping
,
6992 sizeof(struct host_hc_status_block_e1x
));
6994 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
6997 BNX2X_PCI_FREE(bp
->spq
, bp
->spq_mapping
, BCM_PAGE_SIZE
);
6999 BNX2X_PCI_FREE(bp
->eq_ring
, bp
->eq_mapping
,
7000 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
7003 static inline int bnx2x_alloc_fw_stats_mem(struct bnx2x
*bp
)
7006 int is_fcoe_stats
= NO_FCOE(bp
) ? 0 : 1;
7008 /* number of queues for statistics is number of eth queues + FCoE */
7009 u8 num_queue_stats
= BNX2X_NUM_ETH_QUEUES(bp
) + is_fcoe_stats
;
7011 /* Total number of FW statistics requests =
7012 * 1 for port stats + 1 for PF stats + potential 1 for FCoE stats +
7015 bp
->fw_stats_num
= 2 + is_fcoe_stats
+ num_queue_stats
;
7018 /* Request is built from stats_query_header and an array of
7019 * stats_query_cmd_group each of which contains
7020 * STATS_QUERY_CMD_COUNT rules. The real number or requests is
7021 * configured in the stats_query_header.
7023 num_groups
= ((bp
->fw_stats_num
) / STATS_QUERY_CMD_COUNT
) +
7024 (((bp
->fw_stats_num
) % STATS_QUERY_CMD_COUNT
) ? 1 : 0);
7026 bp
->fw_stats_req_sz
= sizeof(struct stats_query_header
) +
7027 num_groups
* sizeof(struct stats_query_cmd_group
);
7029 /* Data for statistics requests + stats_conter
7031 * stats_counter holds per-STORM counters that are incremented
7032 * when STORM has finished with the current request.
7034 * memory for FCoE offloaded statistics are counted anyway,
7035 * even if they will not be sent.
7037 bp
->fw_stats_data_sz
= sizeof(struct per_port_stats
) +
7038 sizeof(struct per_pf_stats
) +
7039 sizeof(struct fcoe_statistics_params
) +
7040 sizeof(struct per_queue_stats
) * num_queue_stats
+
7041 sizeof(struct stats_counter
);
7043 BNX2X_PCI_ALLOC(bp
->fw_stats
, &bp
->fw_stats_mapping
,
7044 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
7047 bp
->fw_stats_req
= (struct bnx2x_fw_stats_req
*)bp
->fw_stats
;
7048 bp
->fw_stats_req_mapping
= bp
->fw_stats_mapping
;
7050 bp
->fw_stats_data
= (struct bnx2x_fw_stats_data
*)
7051 ((u8
*)bp
->fw_stats
+ bp
->fw_stats_req_sz
);
7053 bp
->fw_stats_data_mapping
= bp
->fw_stats_mapping
+
7054 bp
->fw_stats_req_sz
;
7058 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
7059 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
7060 BNX2X_ERR("Can't allocate memory\n");
7065 int bnx2x_alloc_mem(struct bnx2x
*bp
)
7068 if (!CHIP_IS_E1x(bp
))
7069 /* size = the status block + ramrod buffers */
7070 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e2_sb
, &bp
->cnic_sb_mapping
,
7071 sizeof(struct host_hc_status_block_e2
));
7073 BNX2X_PCI_ALLOC(bp
->cnic_sb
.e1x_sb
, &bp
->cnic_sb_mapping
,
7074 sizeof(struct host_hc_status_block_e1x
));
7076 /* allocate searcher T2 table */
7077 BNX2X_PCI_ALLOC(bp
->t2
, &bp
->t2_mapping
, SRC_T2_SZ
);
7081 BNX2X_PCI_ALLOC(bp
->def_status_blk
, &bp
->def_status_blk_mapping
,
7082 sizeof(struct host_sp_status_block
));
7084 BNX2X_PCI_ALLOC(bp
->slowpath
, &bp
->slowpath_mapping
,
7085 sizeof(struct bnx2x_slowpath
));
7088 /* write address to which L5 should insert its values */
7089 bp
->cnic_eth_dev
.addr_drv_info_to_mcp
= &bp
->slowpath
->drv_info_to_mcp
;
7092 /* Allocated memory for FW statistics */
7093 if (bnx2x_alloc_fw_stats_mem(bp
))
7096 bp
->context
.size
= sizeof(union cdu_context
) * BNX2X_L2_CID_COUNT(bp
);
7098 BNX2X_PCI_ALLOC(bp
->context
.vcxt
, &bp
->context
.cxt_mapping
,
7101 BNX2X_ALLOC(bp
->ilt
->lines
, sizeof(struct ilt_line
) * ILT_MAX_LINES
);
7103 if (bnx2x_ilt_mem_op(bp
, ILT_MEMOP_ALLOC
))
7106 /* Slow path ring */
7107 BNX2X_PCI_ALLOC(bp
->spq
, &bp
->spq_mapping
, BCM_PAGE_SIZE
);
7110 BNX2X_PCI_ALLOC(bp
->eq_ring
, &bp
->eq_mapping
,
7111 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
7115 /* need to be done at the end, since it's self adjusting to amount
7116 * of memory available for RSS queues
7118 if (bnx2x_alloc_fp_mem(bp
))
7124 BNX2X_ERR("Can't allocate memory\n");
7129 * Init service functions
7132 int bnx2x_set_mac_one(struct bnx2x
*bp
, u8
*mac
,
7133 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
7134 int mac_type
, unsigned long *ramrod_flags
)
7137 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
7139 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
7141 /* Fill general parameters */
7142 ramrod_param
.vlan_mac_obj
= obj
;
7143 ramrod_param
.ramrod_flags
= *ramrod_flags
;
7145 /* Fill a user request section if needed */
7146 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
7147 memcpy(ramrod_param
.user_req
.u
.mac
.mac
, mac
, ETH_ALEN
);
7149 __set_bit(mac_type
, &ramrod_param
.user_req
.vlan_mac_flags
);
7151 /* Set the command: ADD or DEL */
7153 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
7155 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
7158 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
7160 BNX2X_ERR("%s MAC failed\n", (set
? "Set" : "Del"));
7164 int bnx2x_del_all_macs(struct bnx2x
*bp
,
7165 struct bnx2x_vlan_mac_obj
*mac_obj
,
7166 int mac_type
, bool wait_for_comp
)
7169 unsigned long ramrod_flags
= 0, vlan_mac_flags
= 0;
7171 /* Wait for completion of requested */
7173 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7175 /* Set the mac type of addresses we want to clear */
7176 __set_bit(mac_type
, &vlan_mac_flags
);
7178 rc
= mac_obj
->delete_all(bp
, mac_obj
, &vlan_mac_flags
, &ramrod_flags
);
7180 BNX2X_ERR("Failed to delete MACs: %d\n", rc
);
7185 int bnx2x_set_eth_mac(struct bnx2x
*bp
, bool set
)
7187 unsigned long ramrod_flags
= 0;
7190 if (is_zero_ether_addr(bp
->dev
->dev_addr
) && IS_MF_STORAGE_SD(bp
)) {
7191 DP(NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
,
7192 "Ignoring Zero MAC for STORAGE SD mode\n");
7197 DP(NETIF_MSG_IFUP
, "Adding Eth MAC\n");
7199 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
7200 /* Eth MAC is set on RSS leading client (fp[0]) */
7201 return bnx2x_set_mac_one(bp
, bp
->dev
->dev_addr
, &bp
->fp
->mac_obj
, set
,
7202 BNX2X_ETH_MAC
, &ramrod_flags
);
7205 int bnx2x_setup_leading(struct bnx2x
*bp
)
7207 return bnx2x_setup_queue(bp
, &bp
->fp
[0], 1);
7211 * bnx2x_set_int_mode - configure interrupt mode
7213 * @bp: driver handle
7215 * In case of MSI-X it will also try to enable MSI-X.
7217 static void __devinit
bnx2x_set_int_mode(struct bnx2x
*bp
)
7221 bnx2x_enable_msi(bp
);
7222 /* falling through... */
7224 bp
->num_queues
= 1 + NON_ETH_CONTEXT_USE
;
7225 BNX2X_DEV_INFO("set number of queues to 1\n");
7228 /* Set number of queues according to bp->multi_mode value */
7229 bnx2x_set_num_queues(bp
);
7231 BNX2X_DEV_INFO("set number of queues to %d\n", bp
->num_queues
);
7233 /* if we can't use MSI-X we only need one fp,
7234 * so try to enable MSI-X with the requested number of fp's
7235 * and fallback to MSI or legacy INTx with one fp
7237 if (bnx2x_enable_msix(bp
)) {
7238 /* failed to enable MSI-X */
7239 BNX2X_DEV_INFO("Failed to enable MSI-X (%d), set number of queues to %d\n",
7240 bp
->num_queues
, 1 + NON_ETH_CONTEXT_USE
);
7242 bp
->num_queues
= 1 + NON_ETH_CONTEXT_USE
;
7244 /* Try to enable MSI */
7245 if (!(bp
->flags
& DISABLE_MSI_FLAG
))
7246 bnx2x_enable_msi(bp
);
7252 /* must be called prioir to any HW initializations */
7253 static inline u16
bnx2x_cid_ilt_lines(struct bnx2x
*bp
)
7255 return L2_ILT_LINES(bp
);
7258 void bnx2x_ilt_set_info(struct bnx2x
*bp
)
7260 struct ilt_client_info
*ilt_client
;
7261 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
7264 ilt
->start_line
= FUNC_ILT_BASE(BP_FUNC(bp
));
7265 DP(BNX2X_MSG_SP
, "ilt starts at line %d\n", ilt
->start_line
);
7268 ilt_client
= &ilt
->clients
[ILT_CLIENT_CDU
];
7269 ilt_client
->client_num
= ILT_CLIENT_CDU
;
7270 ilt_client
->page_size
= CDU_ILT_PAGE_SZ
;
7271 ilt_client
->flags
= ILT_CLIENT_SKIP_MEM
;
7272 ilt_client
->start
= line
;
7273 line
+= bnx2x_cid_ilt_lines(bp
);
7275 line
+= CNIC_ILT_LINES
;
7277 ilt_client
->end
= line
- 1;
7279 DP(NETIF_MSG_IFUP
, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7282 ilt_client
->page_size
,
7284 ilog2(ilt_client
->page_size
>> 12));
7287 if (QM_INIT(bp
->qm_cid_count
)) {
7288 ilt_client
= &ilt
->clients
[ILT_CLIENT_QM
];
7289 ilt_client
->client_num
= ILT_CLIENT_QM
;
7290 ilt_client
->page_size
= QM_ILT_PAGE_SZ
;
7291 ilt_client
->flags
= 0;
7292 ilt_client
->start
= line
;
7294 /* 4 bytes for each cid */
7295 line
+= DIV_ROUND_UP(bp
->qm_cid_count
* QM_QUEUES_PER_FUNC
* 4,
7298 ilt_client
->end
= line
- 1;
7301 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7304 ilt_client
->page_size
,
7306 ilog2(ilt_client
->page_size
>> 12));
7310 ilt_client
= &ilt
->clients
[ILT_CLIENT_SRC
];
7312 ilt_client
->client_num
= ILT_CLIENT_SRC
;
7313 ilt_client
->page_size
= SRC_ILT_PAGE_SZ
;
7314 ilt_client
->flags
= 0;
7315 ilt_client
->start
= line
;
7316 line
+= SRC_ILT_LINES
;
7317 ilt_client
->end
= line
- 1;
7320 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7323 ilt_client
->page_size
,
7325 ilog2(ilt_client
->page_size
>> 12));
7328 ilt_client
->flags
= (ILT_CLIENT_SKIP_INIT
| ILT_CLIENT_SKIP_MEM
);
7332 ilt_client
= &ilt
->clients
[ILT_CLIENT_TM
];
7334 ilt_client
->client_num
= ILT_CLIENT_TM
;
7335 ilt_client
->page_size
= TM_ILT_PAGE_SZ
;
7336 ilt_client
->flags
= 0;
7337 ilt_client
->start
= line
;
7338 line
+= TM_ILT_LINES
;
7339 ilt_client
->end
= line
- 1;
7342 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
7345 ilt_client
->page_size
,
7347 ilog2(ilt_client
->page_size
>> 12));
7350 ilt_client
->flags
= (ILT_CLIENT_SKIP_INIT
| ILT_CLIENT_SKIP_MEM
);
7352 BUG_ON(line
> ILT_MAX_LINES
);
7356 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
7358 * @bp: driver handle
7359 * @fp: pointer to fastpath
7360 * @init_params: pointer to parameters structure
7362 * parameters configured:
7363 * - HC configuration
7364 * - Queue's CDU context
7366 static inline void bnx2x_pf_q_prep_init(struct bnx2x
*bp
,
7367 struct bnx2x_fastpath
*fp
, struct bnx2x_queue_init_params
*init_params
)
7371 /* FCoE Queue uses Default SB, thus has no HC capabilities */
7372 if (!IS_FCOE_FP(fp
)) {
7373 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->rx
.flags
);
7374 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->tx
.flags
);
7376 /* If HC is supporterd, enable host coalescing in the transition
7379 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->rx
.flags
);
7380 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->tx
.flags
);
7383 init_params
->rx
.hc_rate
= bp
->rx_ticks
?
7384 (1000000 / bp
->rx_ticks
) : 0;
7385 init_params
->tx
.hc_rate
= bp
->tx_ticks
?
7386 (1000000 / bp
->tx_ticks
) : 0;
7389 init_params
->rx
.fw_sb_id
= init_params
->tx
.fw_sb_id
=
7393 * CQ index among the SB indices: FCoE clients uses the default
7394 * SB, therefore it's different.
7396 init_params
->rx
.sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
7397 init_params
->tx
.sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
;
7400 /* set maximum number of COSs supported by this queue */
7401 init_params
->max_cos
= fp
->max_cos
;
7403 DP(NETIF_MSG_IFUP
, "fp: %d setting queue params max cos to: %d\n",
7404 fp
->index
, init_params
->max_cos
);
7406 /* set the context pointers queue object */
7407 for (cos
= FIRST_TX_COS_INDEX
; cos
< init_params
->max_cos
; cos
++)
7408 init_params
->cxts
[cos
] =
7409 &bp
->context
.vcxt
[fp
->txdata
[cos
].cid
].eth
;
7412 int bnx2x_setup_tx_only(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
7413 struct bnx2x_queue_state_params
*q_params
,
7414 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
,
7415 int tx_index
, bool leading
)
7417 memset(tx_only_params
, 0, sizeof(*tx_only_params
));
7419 /* Set the command */
7420 q_params
->cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
7422 /* Set tx-only QUEUE flags: don't zero statistics */
7423 tx_only_params
->flags
= bnx2x_get_common_flags(bp
, fp
, false);
7425 /* choose the index of the cid to send the slow path on */
7426 tx_only_params
->cid_index
= tx_index
;
7428 /* Set general TX_ONLY_SETUP parameters */
7429 bnx2x_pf_q_prep_general(bp
, fp
, &tx_only_params
->gen_params
, tx_index
);
7431 /* Set Tx TX_ONLY_SETUP parameters */
7432 bnx2x_pf_tx_q_prep(bp
, fp
, &tx_only_params
->txq_params
, tx_index
);
7435 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
7436 tx_index
, q_params
->q_obj
->cids
[FIRST_TX_COS_INDEX
],
7437 q_params
->q_obj
->cids
[tx_index
], q_params
->q_obj
->cl_id
,
7438 tx_only_params
->gen_params
.spcl_id
, tx_only_params
->flags
);
7440 /* send the ramrod */
7441 return bnx2x_queue_state_change(bp
, q_params
);
7446 * bnx2x_setup_queue - setup queue
7448 * @bp: driver handle
7449 * @fp: pointer to fastpath
7450 * @leading: is leading
7452 * This function performs 2 steps in a Queue state machine
7453 * actually: 1) RESET->INIT 2) INIT->SETUP
7456 int bnx2x_setup_queue(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
7459 struct bnx2x_queue_state_params q_params
= {NULL
};
7460 struct bnx2x_queue_setup_params
*setup_params
=
7461 &q_params
.params
.setup
;
7462 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
=
7463 &q_params
.params
.tx_only
;
7467 DP(NETIF_MSG_IFUP
, "setting up queue %d\n", fp
->index
);
7469 /* reset IGU state skip FCoE L2 queue */
7470 if (!IS_FCOE_FP(fp
))
7471 bnx2x_ack_sb(bp
, fp
->igu_sb_id
, USTORM_ID
, 0,
7474 q_params
.q_obj
= &fp
->q_obj
;
7475 /* We want to wait for completion in this context */
7476 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
7478 /* Prepare the INIT parameters */
7479 bnx2x_pf_q_prep_init(bp
, fp
, &q_params
.params
.init
);
7481 /* Set the command */
7482 q_params
.cmd
= BNX2X_Q_CMD_INIT
;
7484 /* Change the state to INIT */
7485 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7487 BNX2X_ERR("Queue(%d) INIT failed\n", fp
->index
);
7491 DP(NETIF_MSG_IFUP
, "init complete\n");
7494 /* Now move the Queue to the SETUP state... */
7495 memset(setup_params
, 0, sizeof(*setup_params
));
7497 /* Set QUEUE flags */
7498 setup_params
->flags
= bnx2x_get_q_flags(bp
, fp
, leading
);
7500 /* Set general SETUP parameters */
7501 bnx2x_pf_q_prep_general(bp
, fp
, &setup_params
->gen_params
,
7502 FIRST_TX_COS_INDEX
);
7504 bnx2x_pf_rx_q_prep(bp
, fp
, &setup_params
->pause_params
,
7505 &setup_params
->rxq_params
);
7507 bnx2x_pf_tx_q_prep(bp
, fp
, &setup_params
->txq_params
,
7508 FIRST_TX_COS_INDEX
);
7510 /* Set the command */
7511 q_params
.cmd
= BNX2X_Q_CMD_SETUP
;
7513 /* Change the state to SETUP */
7514 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7516 BNX2X_ERR("Queue(%d) SETUP failed\n", fp
->index
);
7520 /* loop through the relevant tx-only indices */
7521 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
7522 tx_index
< fp
->max_cos
;
7525 /* prepare and send tx-only ramrod*/
7526 rc
= bnx2x_setup_tx_only(bp
, fp
, &q_params
,
7527 tx_only_params
, tx_index
, leading
);
7529 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
7530 fp
->index
, tx_index
);
7538 static int bnx2x_stop_queue(struct bnx2x
*bp
, int index
)
7540 struct bnx2x_fastpath
*fp
= &bp
->fp
[index
];
7541 struct bnx2x_fp_txdata
*txdata
;
7542 struct bnx2x_queue_state_params q_params
= {NULL
};
7545 DP(NETIF_MSG_IFDOWN
, "stopping queue %d cid %d\n", index
, fp
->cid
);
7547 q_params
.q_obj
= &fp
->q_obj
;
7548 /* We want to wait for completion in this context */
7549 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
7552 /* close tx-only connections */
7553 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
7554 tx_index
< fp
->max_cos
;
7557 /* ascertain this is a normal queue*/
7558 txdata
= &fp
->txdata
[tx_index
];
7560 DP(NETIF_MSG_IFDOWN
, "stopping tx-only queue %d\n",
7563 /* send halt terminate on tx-only connection */
7564 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
7565 memset(&q_params
.params
.terminate
, 0,
7566 sizeof(q_params
.params
.terminate
));
7567 q_params
.params
.terminate
.cid_index
= tx_index
;
7569 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7573 /* send halt terminate on tx-only connection */
7574 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
7575 memset(&q_params
.params
.cfc_del
, 0,
7576 sizeof(q_params
.params
.cfc_del
));
7577 q_params
.params
.cfc_del
.cid_index
= tx_index
;
7578 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7582 /* Stop the primary connection: */
7583 /* ...halt the connection */
7584 q_params
.cmd
= BNX2X_Q_CMD_HALT
;
7585 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7589 /* ...terminate the connection */
7590 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
7591 memset(&q_params
.params
.terminate
, 0,
7592 sizeof(q_params
.params
.terminate
));
7593 q_params
.params
.terminate
.cid_index
= FIRST_TX_COS_INDEX
;
7594 rc
= bnx2x_queue_state_change(bp
, &q_params
);
7597 /* ...delete cfc entry */
7598 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
7599 memset(&q_params
.params
.cfc_del
, 0,
7600 sizeof(q_params
.params
.cfc_del
));
7601 q_params
.params
.cfc_del
.cid_index
= FIRST_TX_COS_INDEX
;
7602 return bnx2x_queue_state_change(bp
, &q_params
);
7606 static void bnx2x_reset_func(struct bnx2x
*bp
)
7608 int port
= BP_PORT(bp
);
7609 int func
= BP_FUNC(bp
);
7612 /* Disable the function in the FW */
7613 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(func
), 0);
7614 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(func
), 0);
7615 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(func
), 0);
7616 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(func
), 0);
7619 for_each_eth_queue(bp
, i
) {
7620 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
7621 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7622 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp
->fw_sb_id
),
7628 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7629 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(bnx2x_cnic_fw_sb_id(bp
)),
7633 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
7634 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func
),
7637 for (i
= 0; i
< XSTORM_SPQ_DATA_SIZE
/ 4; i
++)
7638 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_DATA_OFFSET(func
),
7642 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7643 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7644 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7646 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
7647 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
7651 /* Disable Timer scan */
7652 REG_WR(bp
, TM_REG_EN_LINEAR0_TIMER
+ port
*4, 0);
7654 * Wait for at least 10ms and up to 2 second for the timers scan to
7657 for (i
= 0; i
< 200; i
++) {
7659 if (!REG_RD(bp
, TM_REG_LIN0_SCAN_ON
+ port
*4))
7664 bnx2x_clear_func_ilt(bp
, func
);
7666 /* Timers workaround bug for E2: if this is vnic-3,
7667 * we need to set the entire ilt range for this timers.
7669 if (!CHIP_IS_E1x(bp
) && BP_VN(bp
) == 3) {
7670 struct ilt_client_info ilt_cli
;
7671 /* use dummy TM client */
7672 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
7674 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
7675 ilt_cli
.client_num
= ILT_CLIENT_TM
;
7677 bnx2x_ilt_boundry_init_op(bp
, &ilt_cli
, 0, INITOP_CLEAR
);
7680 /* this assumes that reset_port() called before reset_func()*/
7681 if (!CHIP_IS_E1x(bp
))
7682 bnx2x_pf_disable(bp
);
7687 static void bnx2x_reset_port(struct bnx2x
*bp
)
7689 int port
= BP_PORT(bp
);
7692 /* Reset physical Link */
7693 bnx2x__link_reset(bp
);
7695 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
7697 /* Do not rcv packets to BRB */
7698 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK
+ port
*4, 0x0);
7699 /* Do not direct rcv packets that are not for MCP to the BRB */
7700 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
7701 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
7704 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, 0);
7707 /* Check for BRB port occupancy */
7708 val
= REG_RD(bp
, BRB1_REG_PORT_NUM_OCC_BLOCKS_0
+ port
*4);
7710 DP(NETIF_MSG_IFDOWN
,
7711 "BRB1 is not empty %d blocks are occupied\n", val
);
7713 /* TODO: Close Doorbell port? */
7716 static inline int bnx2x_reset_hw(struct bnx2x
*bp
, u32 load_code
)
7718 struct bnx2x_func_state_params func_params
= {NULL
};
7720 /* Prepare parameters for function state transitions */
7721 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7723 func_params
.f_obj
= &bp
->func_obj
;
7724 func_params
.cmd
= BNX2X_F_CMD_HW_RESET
;
7726 func_params
.params
.hw_init
.load_phase
= load_code
;
7728 return bnx2x_func_state_change(bp
, &func_params
);
7731 static inline int bnx2x_func_stop(struct bnx2x
*bp
)
7733 struct bnx2x_func_state_params func_params
= {NULL
};
7736 /* Prepare parameters for function state transitions */
7737 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7738 func_params
.f_obj
= &bp
->func_obj
;
7739 func_params
.cmd
= BNX2X_F_CMD_STOP
;
7742 * Try to stop the function the 'good way'. If fails (in case
7743 * of a parity error during bnx2x_chip_cleanup()) and we are
7744 * not in a debug mode, perform a state transaction in order to
7745 * enable further HW_RESET transaction.
7747 rc
= bnx2x_func_state_change(bp
, &func_params
);
7749 #ifdef BNX2X_STOP_ON_ERROR
7752 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
7753 __set_bit(RAMROD_DRV_CLR_ONLY
, &func_params
.ramrod_flags
);
7754 return bnx2x_func_state_change(bp
, &func_params
);
7762 * bnx2x_send_unload_req - request unload mode from the MCP.
7764 * @bp: driver handle
7765 * @unload_mode: requested function's unload mode
7767 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
7769 u32
bnx2x_send_unload_req(struct bnx2x
*bp
, int unload_mode
)
7772 int port
= BP_PORT(bp
);
7774 /* Select the UNLOAD request mode */
7775 if (unload_mode
== UNLOAD_NORMAL
)
7776 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
7778 else if (bp
->flags
& NO_WOL_FLAG
)
7779 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
;
7782 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
7783 u8
*mac_addr
= bp
->dev
->dev_addr
;
7787 /* The mac address is written to entries 1-4 to
7788 * preserve entry 0 which is used by the PMF
7790 u8 entry
= (BP_VN(bp
) + 1)*8;
7792 val
= (mac_addr
[0] << 8) | mac_addr
[1];
7793 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
, val
);
7795 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
7796 (mac_addr
[4] << 8) | mac_addr
[5];
7797 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
+ 4, val
);
7799 /* Enable the PME and clear the status */
7800 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, &pmc
);
7801 pmc
|= PCI_PM_CTRL_PME_ENABLE
| PCI_PM_CTRL_PME_STATUS
;
7802 pci_write_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_CTRL
, pmc
);
7804 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
;
7807 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
7809 /* Send the request to the MCP */
7811 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
7813 int path
= BP_PATH(bp
);
7815 DP(NETIF_MSG_IFDOWN
, "NO MCP - load counts[%d] %d, %d, %d\n",
7816 path
, load_count
[path
][0], load_count
[path
][1],
7817 load_count
[path
][2]);
7818 load_count
[path
][0]--;
7819 load_count
[path
][1 + port
]--;
7820 DP(NETIF_MSG_IFDOWN
, "NO MCP - new load counts[%d] %d, %d, %d\n",
7821 path
, load_count
[path
][0], load_count
[path
][1],
7822 load_count
[path
][2]);
7823 if (load_count
[path
][0] == 0)
7824 reset_code
= FW_MSG_CODE_DRV_UNLOAD_COMMON
;
7825 else if (load_count
[path
][1 + port
] == 0)
7826 reset_code
= FW_MSG_CODE_DRV_UNLOAD_PORT
;
7828 reset_code
= FW_MSG_CODE_DRV_UNLOAD_FUNCTION
;
7835 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
7837 * @bp: driver handle
7839 void bnx2x_send_unload_done(struct bnx2x
*bp
)
7841 /* Report UNLOAD_DONE to MCP */
7843 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
7846 static inline int bnx2x_func_wait_started(struct bnx2x
*bp
)
7849 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
7855 * (assumption: No Attention from MCP at this stage)
7856 * PMF probably in the middle of TXdisable/enable transaction
7857 * 1. Sync IRS for default SB
7858 * 2. Sync SP queue - this guarantes us that attention handling started
7859 * 3. Wait, that TXdisable/enable transaction completes
7861 * 1+2 guranty that if DCBx attention was scheduled it already changed
7862 * pending bit of transaction from STARTED-->TX_STOPPED, if we alredy
7863 * received complettion for the transaction the state is TX_STOPPED.
7864 * State will return to STARTED after completion of TX_STOPPED-->STARTED
7868 /* make sure default SB ISR is done */
7870 synchronize_irq(bp
->msix_table
[0].vector
);
7872 synchronize_irq(bp
->pdev
->irq
);
7874 flush_workqueue(bnx2x_wq
);
7876 while (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
7877 BNX2X_F_STATE_STARTED
&& tout
--)
7880 if (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
7881 BNX2X_F_STATE_STARTED
) {
7882 #ifdef BNX2X_STOP_ON_ERROR
7883 BNX2X_ERR("Wrong function state\n");
7887 * Failed to complete the transaction in a "good way"
7888 * Force both transactions with CLR bit
7890 struct bnx2x_func_state_params func_params
= {NULL
};
7892 DP(NETIF_MSG_IFDOWN
,
7893 "Hmmm... unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
7895 func_params
.f_obj
= &bp
->func_obj
;
7896 __set_bit(RAMROD_DRV_CLR_ONLY
,
7897 &func_params
.ramrod_flags
);
7899 /* STARTED-->TX_ST0PPED */
7900 func_params
.cmd
= BNX2X_F_CMD_TX_STOP
;
7901 bnx2x_func_state_change(bp
, &func_params
);
7903 /* TX_ST0PPED-->STARTED */
7904 func_params
.cmd
= BNX2X_F_CMD_TX_START
;
7905 return bnx2x_func_state_change(bp
, &func_params
);
7912 void bnx2x_chip_cleanup(struct bnx2x
*bp
, int unload_mode
)
7914 int port
= BP_PORT(bp
);
7917 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
7920 /* Wait until tx fastpath tasks complete */
7921 for_each_tx_queue(bp
, i
) {
7922 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
7924 for_each_cos_in_tx_queue(fp
, cos
)
7925 rc
= bnx2x_clean_tx_queue(bp
, &fp
->txdata
[cos
]);
7926 #ifdef BNX2X_STOP_ON_ERROR
7932 /* Give HW time to discard old tx messages */
7933 usleep_range(1000, 1000);
7935 /* Clean all ETH MACs */
7936 rc
= bnx2x_del_all_macs(bp
, &bp
->fp
[0].mac_obj
, BNX2X_ETH_MAC
, false);
7938 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc
);
7940 /* Clean up UC list */
7941 rc
= bnx2x_del_all_macs(bp
, &bp
->fp
[0].mac_obj
, BNX2X_UC_LIST_MAC
,
7944 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
7948 if (!CHIP_IS_E1(bp
))
7949 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
7951 /* Set "drop all" (stop Rx).
7952 * We need to take a netif_addr_lock() here in order to prevent
7953 * a race between the completion code and this code.
7955 netif_addr_lock_bh(bp
->dev
);
7956 /* Schedule the rx_mode command */
7957 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
7958 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
7960 bnx2x_set_storm_rx_mode(bp
);
7962 /* Cleanup multicast configuration */
7963 rparam
.mcast_obj
= &bp
->mcast_obj
;
7964 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
7966 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc
);
7968 netif_addr_unlock_bh(bp
->dev
);
7973 * Send the UNLOAD_REQUEST to the MCP. This will return if
7974 * this function should perform FUNC, PORT or COMMON HW
7977 reset_code
= bnx2x_send_unload_req(bp
, unload_mode
);
7980 * (assumption: No Attention from MCP at this stage)
7981 * PMF probably in the middle of TXdisable/enable transaction
7983 rc
= bnx2x_func_wait_started(bp
);
7985 BNX2X_ERR("bnx2x_func_wait_started failed\n");
7986 #ifdef BNX2X_STOP_ON_ERROR
7991 /* Close multi and leading connections
7992 * Completions for ramrods are collected in a synchronous way
7994 for_each_queue(bp
, i
)
7995 if (bnx2x_stop_queue(bp
, i
))
7996 #ifdef BNX2X_STOP_ON_ERROR
8001 /* If SP settings didn't get completed so far - something
8002 * very wrong has happen.
8004 if (!bnx2x_wait_sp_comp(bp
, ~0x0UL
))
8005 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
8007 #ifndef BNX2X_STOP_ON_ERROR
8010 rc
= bnx2x_func_stop(bp
);
8012 BNX2X_ERR("Function stop failed!\n");
8013 #ifdef BNX2X_STOP_ON_ERROR
8018 /* Disable HW interrupts, NAPI */
8019 bnx2x_netif_stop(bp
, 1);
8024 /* Reset the chip */
8025 rc
= bnx2x_reset_hw(bp
, reset_code
);
8027 BNX2X_ERR("HW_RESET failed\n");
8030 /* Report UNLOAD_DONE to MCP */
8031 bnx2x_send_unload_done(bp
);
8034 void bnx2x_disable_close_the_gate(struct bnx2x
*bp
)
8038 DP(NETIF_MSG_IFDOWN
, "Disabling \"close the gates\"\n");
8040 if (CHIP_IS_E1(bp
)) {
8041 int port
= BP_PORT(bp
);
8042 u32 addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
8043 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
8045 val
= REG_RD(bp
, addr
);
8047 REG_WR(bp
, addr
, val
);
8049 val
= REG_RD(bp
, MISC_REG_AEU_GENERAL_MASK
);
8050 val
&= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK
|
8051 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK
);
8052 REG_WR(bp
, MISC_REG_AEU_GENERAL_MASK
, val
);
8056 /* Close gates #2, #3 and #4: */
8057 static void bnx2x_set_234_gates(struct bnx2x
*bp
, bool close
)
8061 /* Gates #2 and #4a are closed/opened for "not E1" only */
8062 if (!CHIP_IS_E1(bp
)) {
8064 REG_WR(bp
, PXP_REG_HST_DISCARD_DOORBELLS
, !!close
);
8066 REG_WR(bp
, PXP_REG_HST_DISCARD_INTERNAL_WRITES
, !!close
);
8070 if (CHIP_IS_E1x(bp
)) {
8071 /* Prevent interrupts from HC on both ports */
8072 val
= REG_RD(bp
, HC_REG_CONFIG_1
);
8073 REG_WR(bp
, HC_REG_CONFIG_1
,
8074 (!close
) ? (val
| HC_CONFIG_1_REG_BLOCK_DISABLE_1
) :
8075 (val
& ~(u32
)HC_CONFIG_1_REG_BLOCK_DISABLE_1
));
8077 val
= REG_RD(bp
, HC_REG_CONFIG_0
);
8078 REG_WR(bp
, HC_REG_CONFIG_0
,
8079 (!close
) ? (val
| HC_CONFIG_0_REG_BLOCK_DISABLE_0
) :
8080 (val
& ~(u32
)HC_CONFIG_0_REG_BLOCK_DISABLE_0
));
8082 /* Prevent incomming interrupts in IGU */
8083 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
8085 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
,
8087 (val
| IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
) :
8088 (val
& ~(u32
)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
));
8091 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "%s gates #2, #3 and #4\n",
8092 close
? "closing" : "opening");
8096 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
8098 static void bnx2x_clp_reset_prep(struct bnx2x
*bp
, u32
*magic_val
)
8100 /* Do some magic... */
8101 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
8102 *magic_val
= val
& SHARED_MF_CLP_MAGIC
;
8103 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
, val
| SHARED_MF_CLP_MAGIC
);
8107 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
8109 * @bp: driver handle
8110 * @magic_val: old value of the `magic' bit.
8112 static void bnx2x_clp_reset_done(struct bnx2x
*bp
, u32 magic_val
)
8114 /* Restore the `magic' bit value... */
8115 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
8116 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
,
8117 (val
& (~SHARED_MF_CLP_MAGIC
)) | magic_val
);
8121 * bnx2x_reset_mcp_prep - prepare for MCP reset.
8123 * @bp: driver handle
8124 * @magic_val: old value of 'magic' bit.
8126 * Takes care of CLP configurations.
8128 static void bnx2x_reset_mcp_prep(struct bnx2x
*bp
, u32
*magic_val
)
8131 u32 validity_offset
;
8133 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "Starting\n");
8135 /* Set `magic' bit in order to save MF config */
8136 if (!CHIP_IS_E1(bp
))
8137 bnx2x_clp_reset_prep(bp
, magic_val
);
8139 /* Get shmem offset */
8140 shmem
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
8141 validity_offset
= offsetof(struct shmem_region
, validity_map
[0]);
8143 /* Clear validity map flags */
8145 REG_WR(bp
, shmem
+ validity_offset
, 0);
8148 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
8149 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
8152 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
8154 * @bp: driver handle
8156 static inline void bnx2x_mcp_wait_one(struct bnx2x
*bp
)
8158 /* special handling for emulation and FPGA,
8159 wait 10 times longer */
8160 if (CHIP_REV_IS_SLOW(bp
))
8161 msleep(MCP_ONE_TIMEOUT
*10);
8163 msleep(MCP_ONE_TIMEOUT
);
8167 * initializes bp->common.shmem_base and waits for validity signature to appear
8169 static int bnx2x_init_shmem(struct bnx2x
*bp
)
8175 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
8176 if (bp
->common
.shmem_base
) {
8177 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
8178 if (val
& SHR_MEM_VALIDITY_MB
)
8182 bnx2x_mcp_wait_one(bp
);
8184 } while (cnt
++ < (MCP_TIMEOUT
/ MCP_ONE_TIMEOUT
));
8186 BNX2X_ERR("BAD MCP validity signature\n");
8191 static int bnx2x_reset_mcp_comp(struct bnx2x
*bp
, u32 magic_val
)
8193 int rc
= bnx2x_init_shmem(bp
);
8195 /* Restore the `magic' bit value */
8196 if (!CHIP_IS_E1(bp
))
8197 bnx2x_clp_reset_done(bp
, magic_val
);
8202 static void bnx2x_pxp_prep(struct bnx2x
*bp
)
8204 if (!CHIP_IS_E1(bp
)) {
8205 REG_WR(bp
, PXP2_REG_RD_START_INIT
, 0);
8206 REG_WR(bp
, PXP2_REG_RQ_RBC_DONE
, 0);
8212 * Reset the whole chip except for:
8214 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
8217 * - MISC (including AEU)
8221 static void bnx2x_process_kill_chip_reset(struct bnx2x
*bp
, bool global
)
8223 u32 not_reset_mask1
, reset_mask1
, not_reset_mask2
, reset_mask2
;
8224 u32 global_bits2
, stay_reset2
;
8227 * Bits that have to be set in reset_mask2 if we want to reset 'global'
8228 * (per chip) blocks.
8231 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU
|
8232 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE
;
8234 /* Don't reset the following blocks */
8236 MISC_REGISTERS_RESET_REG_1_RST_HC
|
8237 MISC_REGISTERS_RESET_REG_1_RST_PXPV
|
8238 MISC_REGISTERS_RESET_REG_1_RST_PXP
;
8241 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO
|
8242 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
|
8243 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE
|
8244 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE
|
8245 MISC_REGISTERS_RESET_REG_2_RST_RBCN
|
8246 MISC_REGISTERS_RESET_REG_2_RST_GRC
|
8247 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE
|
8248 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B
|
8249 MISC_REGISTERS_RESET_REG_2_RST_ATC
|
8250 MISC_REGISTERS_RESET_REG_2_PGLC
;
8253 * Keep the following blocks in reset:
8254 * - all xxMACs are handled by the bnx2x_link code.
8257 MISC_REGISTERS_RESET_REG_2_RST_BMAC0
|
8258 MISC_REGISTERS_RESET_REG_2_RST_BMAC1
|
8259 MISC_REGISTERS_RESET_REG_2_RST_EMAC0
|
8260 MISC_REGISTERS_RESET_REG_2_RST_EMAC1
|
8261 MISC_REGISTERS_RESET_REG_2_UMAC0
|
8262 MISC_REGISTERS_RESET_REG_2_UMAC1
|
8263 MISC_REGISTERS_RESET_REG_2_XMAC
|
8264 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
;
8266 /* Full reset masks according to the chip */
8267 reset_mask1
= 0xffffffff;
8270 reset_mask2
= 0xffff;
8271 else if (CHIP_IS_E1H(bp
))
8272 reset_mask2
= 0x1ffff;
8273 else if (CHIP_IS_E2(bp
))
8274 reset_mask2
= 0xfffff;
8275 else /* CHIP_IS_E3 */
8276 reset_mask2
= 0x3ffffff;
8278 /* Don't reset global blocks unless we need to */
8280 reset_mask2
&= ~global_bits2
;
8283 * In case of attention in the QM, we need to reset PXP
8284 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
8285 * because otherwise QM reset would release 'close the gates' shortly
8286 * before resetting the PXP, then the PSWRQ would send a write
8287 * request to PGLUE. Then when PXP is reset, PGLUE would try to
8288 * read the payload data from PSWWR, but PSWWR would not
8289 * respond. The write queue in PGLUE would stuck, dmae commands
8290 * would not return. Therefore it's important to reset the second
8291 * reset register (containing the
8292 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
8293 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
8296 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
8297 reset_mask2
& (~not_reset_mask2
));
8299 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
8300 reset_mask1
& (~not_reset_mask1
));
8305 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
8306 reset_mask2
& (~stay_reset2
));
8311 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, reset_mask1
);
8316 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
8317 * It should get cleared in no more than 1s.
8319 * @bp: driver handle
8321 * It should get cleared in no more than 1s. Returns 0 if
8322 * pending writes bit gets cleared.
8324 static int bnx2x_er_poll_igu_vq(struct bnx2x
*bp
)
8330 pend_bits
= REG_RD(bp
, IGU_REG_PENDING_BITS_STATUS
);
8335 usleep_range(1000, 1000);
8336 } while (cnt
-- > 0);
8339 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
8347 static int bnx2x_process_kill(struct bnx2x
*bp
, bool global
)
8351 u32 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
, pgl_exp_rom2
;
8354 /* Empty the Tetris buffer, wait for 1s */
8356 sr_cnt
= REG_RD(bp
, PXP2_REG_RD_SR_CNT
);
8357 blk_cnt
= REG_RD(bp
, PXP2_REG_RD_BLK_CNT
);
8358 port_is_idle_0
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_0
);
8359 port_is_idle_1
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_1
);
8360 pgl_exp_rom2
= REG_RD(bp
, PXP2_REG_PGL_EXP_ROM2
);
8361 if ((sr_cnt
== 0x7e) && (blk_cnt
== 0xa0) &&
8362 ((port_is_idle_0
& 0x1) == 0x1) &&
8363 ((port_is_idle_1
& 0x1) == 0x1) &&
8364 (pgl_exp_rom2
== 0xffffffff))
8366 usleep_range(1000, 1000);
8367 } while (cnt
-- > 0);
8370 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
8371 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
8372 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
,
8379 /* Close gates #2, #3 and #4 */
8380 bnx2x_set_234_gates(bp
, true);
8382 /* Poll for IGU VQs for 57712 and newer chips */
8383 if (!CHIP_IS_E1x(bp
) && bnx2x_er_poll_igu_vq(bp
))
8387 /* TBD: Indicate that "process kill" is in progress to MCP */
8389 /* Clear "unprepared" bit */
8390 REG_WR(bp
, MISC_REG_UNPREPARED
, 0);
8393 /* Make sure all is written to the chip before the reset */
8396 /* Wait for 1ms to empty GLUE and PCI-E core queues,
8397 * PSWHST, GRC and PSWRD Tetris buffer.
8399 usleep_range(1000, 1000);
8401 /* Prepare to chip reset: */
8404 bnx2x_reset_mcp_prep(bp
, &val
);
8410 /* reset the chip */
8411 bnx2x_process_kill_chip_reset(bp
, global
);
8414 /* Recover after reset: */
8416 if (global
&& bnx2x_reset_mcp_comp(bp
, val
))
8419 /* TBD: Add resetting the NO_MCP mode DB here */
8424 /* Open the gates #2, #3 and #4 */
8425 bnx2x_set_234_gates(bp
, false);
8427 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
8428 * reset state, re-enable attentions. */
8433 int bnx2x_leader_reset(struct bnx2x
*bp
)
8436 bool global
= bnx2x_reset_is_global(bp
);
8439 /* if not going to reset MCP - load "fake" driver to reset HW while
8440 * driver is owner of the HW
8442 if (!global
&& !BP_NOMCP(bp
)) {
8443 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_REQ
, 0);
8445 BNX2X_ERR("MCP response failure, aborting\n");
8447 goto exit_leader_reset
;
8449 if ((load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
) &&
8450 (load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON
)) {
8451 BNX2X_ERR("MCP unexpected resp, aborting\n");
8453 goto exit_leader_reset2
;
8455 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_DONE
, 0);
8457 BNX2X_ERR("MCP response failure, aborting\n");
8459 goto exit_leader_reset2
;
8463 /* Try to recover after the failure */
8464 if (bnx2x_process_kill(bp
, global
)) {
8465 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
8468 goto exit_leader_reset2
;
8472 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
8475 bnx2x_set_reset_done(bp
);
8477 bnx2x_clear_reset_global(bp
);
8480 /* unload "fake driver" if it was loaded */
8481 if (!global
&& !BP_NOMCP(bp
)) {
8482 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
, 0);
8483 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
8487 bnx2x_release_leader_lock(bp
);
8492 static inline void bnx2x_recovery_failed(struct bnx2x
*bp
)
8494 netdev_err(bp
->dev
, "Recovery has failed. Power cycle is needed.\n");
8496 /* Disconnect this device */
8497 netif_device_detach(bp
->dev
);
8500 * Block ifup for all function on this engine until "process kill"
8503 bnx2x_set_reset_in_progress(bp
);
8505 /* Shut down the power */
8506 bnx2x_set_power_state(bp
, PCI_D3hot
);
8508 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
8514 * Assumption: runs under rtnl lock. This together with the fact
8515 * that it's called only from bnx2x_sp_rtnl() ensure that it
8516 * will never be called when netif_running(bp->dev) is false.
8518 static void bnx2x_parity_recover(struct bnx2x
*bp
)
8520 bool global
= false;
8521 u32 error_recovered
, error_unrecovered
;
8524 DP(NETIF_MSG_HW
, "Handling parity\n");
8526 switch (bp
->recovery_state
) {
8527 case BNX2X_RECOVERY_INIT
:
8528 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_INIT\n");
8529 is_parity
= bnx2x_chk_parity_attn(bp
, &global
, false);
8530 WARN_ON(!is_parity
);
8532 /* Try to get a LEADER_LOCK HW lock */
8533 if (bnx2x_trylock_leader_lock(bp
)) {
8534 bnx2x_set_reset_in_progress(bp
);
8536 * Check if there is a global attention and if
8537 * there was a global attention, set the global
8542 bnx2x_set_reset_global(bp
);
8547 /* Stop the driver */
8548 /* If interface has been removed - break */
8549 if (bnx2x_nic_unload(bp
, UNLOAD_RECOVERY
))
8552 bp
->recovery_state
= BNX2X_RECOVERY_WAIT
;
8554 /* Ensure "is_leader", MCP command sequence and
8555 * "recovery_state" update values are seen on other
8561 case BNX2X_RECOVERY_WAIT
:
8562 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_WAIT\n");
8563 if (bp
->is_leader
) {
8564 int other_engine
= BP_PATH(bp
) ? 0 : 1;
8565 bool other_load_status
=
8566 bnx2x_get_load_status(bp
, other_engine
);
8568 bnx2x_get_load_status(bp
, BP_PATH(bp
));
8569 global
= bnx2x_reset_is_global(bp
);
8572 * In case of a parity in a global block, let
8573 * the first leader that performs a
8574 * leader_reset() reset the global blocks in
8575 * order to clear global attentions. Otherwise
8576 * the the gates will remain closed for that
8580 (global
&& other_load_status
)) {
8581 /* Wait until all other functions get
8584 schedule_delayed_work(&bp
->sp_rtnl_task
,
8588 /* If all other functions got down -
8589 * try to bring the chip back to
8590 * normal. In any case it's an exit
8591 * point for a leader.
8593 if (bnx2x_leader_reset(bp
)) {
8594 bnx2x_recovery_failed(bp
);
8598 /* If we are here, means that the
8599 * leader has succeeded and doesn't
8600 * want to be a leader any more. Try
8601 * to continue as a none-leader.
8605 } else { /* non-leader */
8606 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
))) {
8607 /* Try to get a LEADER_LOCK HW lock as
8608 * long as a former leader may have
8609 * been unloaded by the user or
8610 * released a leadership by another
8613 if (bnx2x_trylock_leader_lock(bp
)) {
8614 /* I'm a leader now! Restart a
8621 schedule_delayed_work(&bp
->sp_rtnl_task
,
8627 * If there was a global attention, wait
8628 * for it to be cleared.
8630 if (bnx2x_reset_is_global(bp
)) {
8631 schedule_delayed_work(
8638 bp
->eth_stats
.recoverable_error
;
8640 bp
->eth_stats
.unrecoverable_error
;
8641 bp
->recovery_state
=
8642 BNX2X_RECOVERY_NIC_LOADING
;
8643 if (bnx2x_nic_load(bp
, LOAD_NORMAL
)) {
8644 error_unrecovered
++;
8646 "Recovery failed. Power cycle needed\n");
8647 /* Disconnect this device */
8648 netif_device_detach(bp
->dev
);
8649 /* Shut down the power */
8650 bnx2x_set_power_state(
8654 bp
->recovery_state
=
8655 BNX2X_RECOVERY_DONE
;
8659 bp
->eth_stats
.recoverable_error
=
8661 bp
->eth_stats
.unrecoverable_error
=
8673 static int bnx2x_close(struct net_device
*dev
);
8675 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
8676 * scheduled on a general queue in order to prevent a dead lock.
8678 static void bnx2x_sp_rtnl_task(struct work_struct
*work
)
8680 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_rtnl_task
.work
);
8684 if (!netif_running(bp
->dev
))
8687 /* if stop on error is defined no recovery flows should be executed */
8688 #ifdef BNX2X_STOP_ON_ERROR
8689 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
8690 "you will need to reboot when done\n");
8691 goto sp_rtnl_not_reset
;
8694 if (unlikely(bp
->recovery_state
!= BNX2X_RECOVERY_DONE
)) {
8696 * Clear all pending SP commands as we are going to reset the
8699 bp
->sp_rtnl_state
= 0;
8702 bnx2x_parity_recover(bp
);
8707 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT
, &bp
->sp_rtnl_state
)) {
8709 * Clear all pending SP commands as we are going to reset the
8712 bp
->sp_rtnl_state
= 0;
8715 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
);
8716 bnx2x_nic_load(bp
, LOAD_NORMAL
);
8720 #ifdef BNX2X_STOP_ON_ERROR
8723 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC
, &bp
->sp_rtnl_state
))
8724 bnx2x_setup_tc(bp
->dev
, bp
->dcbx_port_params
.ets
.num_of_cos
);
8727 * in case of fan failure we need to reset id if the "stop on error"
8728 * debug flag is set, since we trying to prevent permanent overheating
8731 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
)) {
8732 DP(NETIF_MSG_HW
, "fan failure detected. Unloading driver\n");
8733 netif_device_detach(bp
->dev
);
8734 bnx2x_close(bp
->dev
);
8741 /* end of nic load/unload */
8743 static void bnx2x_period_task(struct work_struct
*work
)
8745 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, period_task
.work
);
8747 if (!netif_running(bp
->dev
))
8748 goto period_task_exit
;
8750 if (CHIP_REV_IS_SLOW(bp
)) {
8751 BNX2X_ERR("period task called on emulation, ignoring\n");
8752 goto period_task_exit
;
8755 bnx2x_acquire_phy_lock(bp
);
8757 * The barrier is needed to ensure the ordering between the writing to
8758 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
8763 bnx2x_period_func(&bp
->link_params
, &bp
->link_vars
);
8765 /* Re-queue task in 1 sec */
8766 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 1*HZ
);
8769 bnx2x_release_phy_lock(bp
);
8775 * Init service functions
8778 static u32
bnx2x_get_pretend_reg(struct bnx2x
*bp
)
8780 u32 base
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
8781 u32 stride
= PXP2_REG_PGL_PRETEND_FUNC_F1
- base
;
8782 return base
+ (BP_ABS_FUNC(bp
)) * stride
;
8785 static void bnx2x_undi_int_disable_e1h(struct bnx2x
*bp
)
8787 u32 reg
= bnx2x_get_pretend_reg(bp
);
8789 /* Flush all outstanding writes */
8792 /* Pretend to be function 0 */
8794 REG_RD(bp
, reg
); /* Flush the GRC transaction (in the chip) */
8796 /* From now we are in the "like-E1" mode */
8797 bnx2x_int_disable(bp
);
8799 /* Flush all outstanding writes */
8802 /* Restore the original function */
8803 REG_WR(bp
, reg
, BP_ABS_FUNC(bp
));
8807 static inline void bnx2x_undi_int_disable(struct bnx2x
*bp
)
8810 bnx2x_int_disable(bp
);
8812 bnx2x_undi_int_disable_e1h(bp
);
8815 static void __devinit
bnx2x_undi_unload(struct bnx2x
*bp
)
8819 /* possibly another driver is trying to reset the chip */
8820 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
8822 /* check if doorbell queue is reset */
8823 if (REG_RD(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
)
8824 & MISC_REGISTERS_RESET_REG_1_RST_DORQ
) {
8827 * Check if it is the UNDI driver
8828 * UNDI driver initializes CID offset for normal bell to 0x7
8830 val
= REG_RD(bp
, DORQ_REG_NORM_CID_OFST
);
8832 u32 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8833 /* save our pf_num */
8834 int orig_pf_num
= bp
->pf_num
;
8836 u32 swap_en
, swap_val
, value
;
8838 /* clear the UNDI indication */
8839 REG_WR(bp
, DORQ_REG_NORM_CID_OFST
, 0);
8841 BNX2X_DEV_INFO("UNDI is active! reset device\n");
8843 /* try unload UNDI on port 0 */
8846 (SHMEM_RD(bp
, func_mb
[bp
->pf_num
].drv_mb_header
) &
8847 DRV_MSG_SEQ_NUMBER_MASK
);
8848 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
8850 /* if UNDI is loaded on the other port */
8851 if (reset_code
!= FW_MSG_CODE_DRV_UNLOAD_COMMON
) {
8853 /* send "DONE" for previous unload */
8854 bnx2x_fw_command(bp
,
8855 DRV_MSG_CODE_UNLOAD_DONE
, 0);
8857 /* unload UNDI on port 1 */
8860 (SHMEM_RD(bp
, func_mb
[bp
->pf_num
].drv_mb_header
) &
8861 DRV_MSG_SEQ_NUMBER_MASK
);
8862 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
8864 bnx2x_fw_command(bp
, reset_code
, 0);
8867 bnx2x_undi_int_disable(bp
);
8870 /* close input traffic and wait for it */
8871 /* Do not rcv packets to BRB */
8872 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_DRV_MASK
:
8873 NIG_REG_LLH0_BRB1_DRV_MASK
), 0x0);
8874 /* Do not direct rcv packets that are not for MCP to
8876 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
8877 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
8879 REG_WR(bp
, (port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
8880 MISC_REG_AEU_MASK_ATTN_FUNC_0
), 0);
8883 /* save NIG port swap info */
8884 swap_val
= REG_RD(bp
, NIG_REG_PORT_SWAP
);
8885 swap_en
= REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
);
8888 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
8892 if (CHIP_IS_E3(bp
)) {
8893 value
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
8894 value
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
8898 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
8901 /* take the NIG out of reset and restore swap values */
8903 GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
8904 MISC_REGISTERS_RESET_REG_1_RST_NIG
);
8905 REG_WR(bp
, NIG_REG_PORT_SWAP
, swap_val
);
8906 REG_WR(bp
, NIG_REG_STRAP_OVERRIDE
, swap_en
);
8908 /* send unload done to the MCP */
8909 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
8911 /* restore our func and fw_seq */
8912 bp
->pf_num
= orig_pf_num
;
8916 /* now it's safe to release the lock */
8917 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
8920 static void __devinit
bnx2x_get_common_hwinfo(struct bnx2x
*bp
)
8922 u32 val
, val2
, val3
, val4
, id
, boot_mode
;
8925 /* Get the chip revision id and number. */
8926 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
8927 val
= REG_RD(bp
, MISC_REG_CHIP_NUM
);
8928 id
= ((val
& 0xffff) << 16);
8929 val
= REG_RD(bp
, MISC_REG_CHIP_REV
);
8930 id
|= ((val
& 0xf) << 12);
8931 val
= REG_RD(bp
, MISC_REG_CHIP_METAL
);
8932 id
|= ((val
& 0xff) << 4);
8933 val
= REG_RD(bp
, MISC_REG_BOND_ID
);
8935 bp
->common
.chip_id
= id
;
8937 /* Set doorbell size */
8938 bp
->db_size
= (1 << BNX2X_DB_SHIFT
);
8940 if (!CHIP_IS_E1x(bp
)) {
8941 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
);
8943 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN
);
8945 val
= (val
>> 1) & 1;
8946 BNX2X_DEV_INFO("chip is in %s\n", val
? "4_PORT_MODE" :
8948 bp
->common
.chip_port_mode
= val
? CHIP_4_PORT_MODE
:
8951 if (CHIP_MODE_IS_4_PORT(bp
))
8952 bp
->pfid
= (bp
->pf_num
>> 1); /* 0..3 */
8954 bp
->pfid
= (bp
->pf_num
& 0x6); /* 0, 2, 4, 6 */
8956 bp
->common
.chip_port_mode
= CHIP_PORT_MODE_NONE
; /* N/A */
8957 bp
->pfid
= bp
->pf_num
; /* 0..7 */
8960 BNX2X_DEV_INFO("pf_id: %x", bp
->pfid
);
8962 bp
->link_params
.chip_id
= bp
->common
.chip_id
;
8963 BNX2X_DEV_INFO("chip ID is 0x%x\n", id
);
8965 val
= (REG_RD(bp
, 0x2874) & 0x55);
8966 if ((bp
->common
.chip_id
& 0x1) ||
8967 (CHIP_IS_E1(bp
) && val
) || (CHIP_IS_E1H(bp
) && (val
== 0x55))) {
8968 bp
->flags
|= ONE_PORT_FLAG
;
8969 BNX2X_DEV_INFO("single port device\n");
8972 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_CFG4
);
8973 bp
->common
.flash_size
= (BNX2X_NVRAM_1MB_SIZE
<<
8974 (val
& MCPR_NVM_CFG4_FLASH_SIZE
));
8975 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
8976 bp
->common
.flash_size
, bp
->common
.flash_size
);
8978 bnx2x_init_shmem(bp
);
8982 bp
->common
.shmem2_base
= REG_RD(bp
, (BP_PATH(bp
) ?
8983 MISC_REG_GENERIC_CR_1
:
8984 MISC_REG_GENERIC_CR_0
));
8986 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
8987 bp
->link_params
.shmem2_base
= bp
->common
.shmem2_base
;
8988 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
8989 bp
->common
.shmem_base
, bp
->common
.shmem2_base
);
8991 if (!bp
->common
.shmem_base
) {
8992 BNX2X_DEV_INFO("MCP not active\n");
8993 bp
->flags
|= NO_MCP_FLAG
;
8997 bp
->common
.hw_config
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config
);
8998 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp
->common
.hw_config
);
9000 bp
->link_params
.hw_led_mode
= ((bp
->common
.hw_config
&
9001 SHARED_HW_CFG_LED_MODE_MASK
) >>
9002 SHARED_HW_CFG_LED_MODE_SHIFT
);
9004 bp
->link_params
.feature_config_flags
= 0;
9005 val
= SHMEM_RD(bp
, dev_info
.shared_feature_config
.config
);
9006 if (val
& SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED
)
9007 bp
->link_params
.feature_config_flags
|=
9008 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
9010 bp
->link_params
.feature_config_flags
&=
9011 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
9013 val
= SHMEM_RD(bp
, dev_info
.bc_rev
) >> 8;
9014 bp
->common
.bc_ver
= val
;
9015 BNX2X_DEV_INFO("bc_ver %X\n", val
);
9016 if (val
< BNX2X_BC_VER
) {
9017 /* for now only warn
9018 * later we might need to enforce this */
9019 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
9022 bp
->link_params
.feature_config_flags
|=
9023 (val
>= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL
) ?
9024 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
: 0;
9026 bp
->link_params
.feature_config_flags
|=
9027 (val
>= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL
) ?
9028 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
: 0;
9030 bp
->link_params
.feature_config_flags
|=
9031 (val
>= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED
) ?
9032 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
: 0;
9033 bp
->flags
|= (val
>= REQ_BC_VER_4_PFC_STATS_SUPPORTED
) ?
9034 BC_SUPPORTS_PFC_STATS
: 0;
9036 boot_mode
= SHMEM_RD(bp
,
9037 dev_info
.port_feature_config
[BP_PORT(bp
)].mba_config
) &
9038 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK
;
9039 switch (boot_mode
) {
9040 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE
:
9041 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_PXE
;
9043 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB
:
9044 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_ISCSI
;
9046 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT
:
9047 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_FCOE
;
9049 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE
:
9050 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_NONE
;
9054 pci_read_config_word(bp
->pdev
, bp
->pm_cap
+ PCI_PM_PMC
, &pmc
);
9055 bp
->flags
|= (pmc
& PCI_PM_CAP_PME_D3cold
) ? 0 : NO_WOL_FLAG
;
9057 BNX2X_DEV_INFO("%sWoL capable\n",
9058 (bp
->flags
& NO_WOL_FLAG
) ? "not " : "");
9060 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
);
9061 val2
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[4]);
9062 val3
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[8]);
9063 val4
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[12]);
9065 dev_info(&bp
->pdev
->dev
, "part number %X-%X-%X-%X\n",
9066 val
, val2
, val3
, val4
);
9069 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
9070 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
9072 static void __devinit
bnx2x_get_igu_cam_info(struct bnx2x
*bp
)
9074 int pfid
= BP_FUNC(bp
);
9077 u8 fid
, igu_sb_cnt
= 0;
9079 bp
->igu_base_sb
= 0xff;
9080 if (CHIP_INT_MODE_IS_BC(bp
)) {
9082 igu_sb_cnt
= bp
->igu_sb_cnt
;
9083 bp
->igu_base_sb
= (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
) *
9086 bp
->igu_dsb_id
= E1HVN_MAX
* FP_SB_MAX_E1x
+
9087 (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
);
9092 /* IGU in normal mode - read CAM */
9093 for (igu_sb_id
= 0; igu_sb_id
< IGU_REG_MAPPING_MEMORY_SIZE
;
9095 val
= REG_RD(bp
, IGU_REG_MAPPING_MEMORY
+ igu_sb_id
* 4);
9096 if (!(val
& IGU_REG_MAPPING_MEMORY_VALID
))
9099 if ((fid
& IGU_FID_ENCODE_IS_PF
)) {
9100 if ((fid
& IGU_FID_PF_NUM_MASK
) != pfid
)
9102 if (IGU_VEC(val
) == 0)
9103 /* default status block */
9104 bp
->igu_dsb_id
= igu_sb_id
;
9106 if (bp
->igu_base_sb
== 0xff)
9107 bp
->igu_base_sb
= igu_sb_id
;
9113 #ifdef CONFIG_PCI_MSI
9115 * It's expected that number of CAM entries for this functions is equal
9116 * to the number evaluated based on the MSI-X table size. We want a
9117 * harsh warning if these values are different!
9119 WARN_ON(bp
->igu_sb_cnt
!= igu_sb_cnt
);
9122 if (igu_sb_cnt
== 0)
9123 BNX2X_ERR("CAM configuration error\n");
9126 static void __devinit
bnx2x_link_settings_supported(struct bnx2x
*bp
,
9129 int cfg_size
= 0, idx
, port
= BP_PORT(bp
);
9131 /* Aggregation of supported attributes of all external phys */
9132 bp
->port
.supported
[0] = 0;
9133 bp
->port
.supported
[1] = 0;
9134 switch (bp
->link_params
.num_phys
) {
9136 bp
->port
.supported
[0] = bp
->link_params
.phy
[INT_PHY
].supported
;
9140 bp
->port
.supported
[0] = bp
->link_params
.phy
[EXT_PHY1
].supported
;
9144 if (bp
->link_params
.multi_phy_config
&
9145 PORT_HW_CFG_PHY_SWAPPED_ENABLED
) {
9146 bp
->port
.supported
[1] =
9147 bp
->link_params
.phy
[EXT_PHY1
].supported
;
9148 bp
->port
.supported
[0] =
9149 bp
->link_params
.phy
[EXT_PHY2
].supported
;
9151 bp
->port
.supported
[0] =
9152 bp
->link_params
.phy
[EXT_PHY1
].supported
;
9153 bp
->port
.supported
[1] =
9154 bp
->link_params
.phy
[EXT_PHY2
].supported
;
9160 if (!(bp
->port
.supported
[0] || bp
->port
.supported
[1])) {
9161 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
9163 dev_info
.port_hw_config
[port
].external_phy_config
),
9165 dev_info
.port_hw_config
[port
].external_phy_config2
));
9170 bp
->port
.phy_addr
= REG_RD(bp
, MISC_REG_WC0_CTRL_PHY_ADDR
);
9172 switch (switch_cfg
) {
9174 bp
->port
.phy_addr
= REG_RD(
9175 bp
, NIG_REG_SERDES0_CTRL_PHY_ADDR
+ port
*0x10);
9177 case SWITCH_CFG_10G
:
9178 bp
->port
.phy_addr
= REG_RD(
9179 bp
, NIG_REG_XGXS0_CTRL_PHY_ADDR
+ port
*0x18);
9182 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
9183 bp
->port
.link_config
[0]);
9187 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
9188 /* mask what we support according to speed_cap_mask per configuration */
9189 for (idx
= 0; idx
< cfg_size
; idx
++) {
9190 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9191 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
))
9192 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Half
;
9194 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9195 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
))
9196 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Full
;
9198 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9199 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))
9200 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Half
;
9202 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9203 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
))
9204 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Full
;
9206 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9207 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))
9208 bp
->port
.supported
[idx
] &= ~(SUPPORTED_1000baseT_Half
|
9209 SUPPORTED_1000baseT_Full
);
9211 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9212 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
9213 bp
->port
.supported
[idx
] &= ~SUPPORTED_2500baseX_Full
;
9215 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
9216 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
))
9217 bp
->port
.supported
[idx
] &= ~SUPPORTED_10000baseT_Full
;
9221 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp
->port
.supported
[0],
9222 bp
->port
.supported
[1]);
9225 static void __devinit
bnx2x_link_settings_requested(struct bnx2x
*bp
)
9227 u32 link_config
, idx
, cfg_size
= 0;
9228 bp
->port
.advertising
[0] = 0;
9229 bp
->port
.advertising
[1] = 0;
9230 switch (bp
->link_params
.num_phys
) {
9239 for (idx
= 0; idx
< cfg_size
; idx
++) {
9240 bp
->link_params
.req_duplex
[idx
] = DUPLEX_FULL
;
9241 link_config
= bp
->port
.link_config
[idx
];
9242 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
9243 case PORT_FEATURE_LINK_SPEED_AUTO
:
9244 if (bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
) {
9245 bp
->link_params
.req_line_speed
[idx
] =
9247 bp
->port
.advertising
[idx
] |=
9248 bp
->port
.supported
[idx
];
9249 if (bp
->link_params
.phy
[EXT_PHY1
].type
==
9250 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
)
9251 bp
->port
.advertising
[idx
] |=
9252 (SUPPORTED_100baseT_Half
|
9253 SUPPORTED_100baseT_Full
);
9255 /* force 10G, no AN */
9256 bp
->link_params
.req_line_speed
[idx
] =
9258 bp
->port
.advertising
[idx
] |=
9259 (ADVERTISED_10000baseT_Full
|
9265 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
9266 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Full
) {
9267 bp
->link_params
.req_line_speed
[idx
] =
9269 bp
->port
.advertising
[idx
] |=
9270 (ADVERTISED_10baseT_Full
|
9273 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9275 bp
->link_params
.speed_cap_mask
[idx
]);
9280 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
9281 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Half
) {
9282 bp
->link_params
.req_line_speed
[idx
] =
9284 bp
->link_params
.req_duplex
[idx
] =
9286 bp
->port
.advertising
[idx
] |=
9287 (ADVERTISED_10baseT_Half
|
9290 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9292 bp
->link_params
.speed_cap_mask
[idx
]);
9297 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
9298 if (bp
->port
.supported
[idx
] &
9299 SUPPORTED_100baseT_Full
) {
9300 bp
->link_params
.req_line_speed
[idx
] =
9302 bp
->port
.advertising
[idx
] |=
9303 (ADVERTISED_100baseT_Full
|
9306 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9308 bp
->link_params
.speed_cap_mask
[idx
]);
9313 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
9314 if (bp
->port
.supported
[idx
] &
9315 SUPPORTED_100baseT_Half
) {
9316 bp
->link_params
.req_line_speed
[idx
] =
9318 bp
->link_params
.req_duplex
[idx
] =
9320 bp
->port
.advertising
[idx
] |=
9321 (ADVERTISED_100baseT_Half
|
9324 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9326 bp
->link_params
.speed_cap_mask
[idx
]);
9331 case PORT_FEATURE_LINK_SPEED_1G
:
9332 if (bp
->port
.supported
[idx
] &
9333 SUPPORTED_1000baseT_Full
) {
9334 bp
->link_params
.req_line_speed
[idx
] =
9336 bp
->port
.advertising
[idx
] |=
9337 (ADVERTISED_1000baseT_Full
|
9340 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9342 bp
->link_params
.speed_cap_mask
[idx
]);
9347 case PORT_FEATURE_LINK_SPEED_2_5G
:
9348 if (bp
->port
.supported
[idx
] &
9349 SUPPORTED_2500baseX_Full
) {
9350 bp
->link_params
.req_line_speed
[idx
] =
9352 bp
->port
.advertising
[idx
] |=
9353 (ADVERTISED_2500baseX_Full
|
9356 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9358 bp
->link_params
.speed_cap_mask
[idx
]);
9363 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
9364 if (bp
->port
.supported
[idx
] &
9365 SUPPORTED_10000baseT_Full
) {
9366 bp
->link_params
.req_line_speed
[idx
] =
9368 bp
->port
.advertising
[idx
] |=
9369 (ADVERTISED_10000baseT_Full
|
9372 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
9374 bp
->link_params
.speed_cap_mask
[idx
]);
9378 case PORT_FEATURE_LINK_SPEED_20G
:
9379 bp
->link_params
.req_line_speed
[idx
] = SPEED_20000
;
9383 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
9385 bp
->link_params
.req_line_speed
[idx
] =
9387 bp
->port
.advertising
[idx
] =
9388 bp
->port
.supported
[idx
];
9392 bp
->link_params
.req_flow_ctrl
[idx
] = (link_config
&
9393 PORT_FEATURE_FLOW_CONTROL_MASK
);
9394 if ((bp
->link_params
.req_flow_ctrl
[idx
] ==
9395 BNX2X_FLOW_CTRL_AUTO
) &&
9396 !(bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
)) {
9397 bp
->link_params
.req_flow_ctrl
[idx
] =
9398 BNX2X_FLOW_CTRL_NONE
;
9401 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
9402 bp
->link_params
.req_line_speed
[idx
],
9403 bp
->link_params
.req_duplex
[idx
],
9404 bp
->link_params
.req_flow_ctrl
[idx
],
9405 bp
->port
.advertising
[idx
]);
9409 static void __devinit
bnx2x_set_mac_buf(u8
*mac_buf
, u32 mac_lo
, u16 mac_hi
)
9411 mac_hi
= cpu_to_be16(mac_hi
);
9412 mac_lo
= cpu_to_be32(mac_lo
);
9413 memcpy(mac_buf
, &mac_hi
, sizeof(mac_hi
));
9414 memcpy(mac_buf
+ sizeof(mac_hi
), &mac_lo
, sizeof(mac_lo
));
9417 static void __devinit
bnx2x_get_port_hwinfo(struct bnx2x
*bp
)
9419 int port
= BP_PORT(bp
);
9421 u32 ext_phy_type
, ext_phy_config
;
9423 bp
->link_params
.bp
= bp
;
9424 bp
->link_params
.port
= port
;
9426 bp
->link_params
.lane_config
=
9427 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].lane_config
);
9429 bp
->link_params
.speed_cap_mask
[0] =
9431 dev_info
.port_hw_config
[port
].speed_capability_mask
);
9432 bp
->link_params
.speed_cap_mask
[1] =
9434 dev_info
.port_hw_config
[port
].speed_capability_mask2
);
9435 bp
->port
.link_config
[0] =
9436 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config
);
9438 bp
->port
.link_config
[1] =
9439 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config2
);
9441 bp
->link_params
.multi_phy_config
=
9442 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].multi_phy_config
);
9443 /* If the device is capable of WoL, set the default state according
9446 config
= SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].config
);
9447 bp
->wol
= (!(bp
->flags
& NO_WOL_FLAG
) &&
9448 (config
& PORT_FEATURE_WOL_ENABLED
));
9450 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
9451 bp
->link_params
.lane_config
,
9452 bp
->link_params
.speed_cap_mask
[0],
9453 bp
->port
.link_config
[0]);
9455 bp
->link_params
.switch_cfg
= (bp
->port
.link_config
[0] &
9456 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
9457 bnx2x_phy_probe(&bp
->link_params
);
9458 bnx2x_link_settings_supported(bp
, bp
->link_params
.switch_cfg
);
9460 bnx2x_link_settings_requested(bp
);
9463 * If connected directly, work with the internal PHY, otherwise, work
9464 * with the external PHY
9468 dev_info
.port_hw_config
[port
].external_phy_config
);
9469 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
9470 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
9471 bp
->mdio
.prtad
= bp
->port
.phy_addr
;
9473 else if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
9474 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
9476 XGXS_EXT_PHY_ADDR(ext_phy_config
);
9479 * Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
9480 * In MF mode, it is set to cover self test cases
9483 bp
->port
.need_hw_lock
= 1;
9485 bp
->port
.need_hw_lock
= bnx2x_hw_lock_required(bp
,
9486 bp
->common
.shmem_base
,
9487 bp
->common
.shmem2_base
);
9490 void bnx2x_get_iscsi_info(struct bnx2x
*bp
)
9492 u32 no_flags
= NO_ISCSI_FLAG
;
9494 int port
= BP_PORT(bp
);
9496 u32 max_iscsi_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
9497 drv_lic_key
[port
].max_iscsi_conn
);
9499 /* Get the number of maximum allowed iSCSI connections */
9500 bp
->cnic_eth_dev
.max_iscsi_conn
=
9501 (max_iscsi_conn
& BNX2X_MAX_ISCSI_INIT_CONN_MASK
) >>
9502 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT
;
9504 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
9505 bp
->cnic_eth_dev
.max_iscsi_conn
);
9508 * If maximum allowed number of connections is zero -
9509 * disable the feature.
9511 if (!bp
->cnic_eth_dev
.max_iscsi_conn
)
9512 bp
->flags
|= no_flags
;
9514 bp
->flags
|= no_flags
;
9519 static void __devinit
bnx2x_get_ext_wwn_info(struct bnx2x
*bp
, int func
)
9522 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
9523 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_upper
);
9524 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
9525 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_lower
);
9528 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
9529 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_upper
);
9530 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
9531 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_lower
);
9534 static void __devinit
bnx2x_get_fcoe_info(struct bnx2x
*bp
)
9537 int port
= BP_PORT(bp
);
9538 int func
= BP_ABS_FUNC(bp
);
9540 u32 max_fcoe_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
9541 drv_lic_key
[port
].max_fcoe_conn
);
9543 /* Get the number of maximum allowed FCoE connections */
9544 bp
->cnic_eth_dev
.max_fcoe_conn
=
9545 (max_fcoe_conn
& BNX2X_MAX_FCOE_INIT_CONN_MASK
) >>
9546 BNX2X_MAX_FCOE_INIT_CONN_SHIFT
;
9551 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
9553 dev_info
.port_hw_config
[port
].
9554 fcoe_wwn_port_name_upper
);
9555 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
9557 dev_info
.port_hw_config
[port
].
9558 fcoe_wwn_port_name_lower
);
9561 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
9563 dev_info
.port_hw_config
[port
].
9564 fcoe_wwn_node_name_upper
);
9565 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
9567 dev_info
.port_hw_config
[port
].
9568 fcoe_wwn_node_name_lower
);
9569 } else if (!IS_MF_SD(bp
)) {
9570 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
9573 * Read the WWN info only if the FCoE feature is enabled for
9576 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
)
9577 bnx2x_get_ext_wwn_info(bp
, func
);
9579 } else if (IS_MF_FCOE_SD(bp
))
9580 bnx2x_get_ext_wwn_info(bp
, func
);
9582 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp
->cnic_eth_dev
.max_fcoe_conn
);
9585 * If maximum allowed number of connections is zero -
9586 * disable the feature.
9588 if (!bp
->cnic_eth_dev
.max_fcoe_conn
)
9589 bp
->flags
|= NO_FCOE_FLAG
;
9591 bp
->flags
|= NO_FCOE_FLAG
;
9595 static void __devinit
bnx2x_get_cnic_info(struct bnx2x
*bp
)
9598 * iSCSI may be dynamically disabled but reading
9599 * info here we will decrease memory usage by driver
9600 * if the feature is disabled for good
9602 bnx2x_get_iscsi_info(bp
);
9603 bnx2x_get_fcoe_info(bp
);
9606 static void __devinit
bnx2x_get_mac_hwinfo(struct bnx2x
*bp
)
9609 int func
= BP_ABS_FUNC(bp
);
9610 int port
= BP_PORT(bp
);
9612 u8
*iscsi_mac
= bp
->cnic_eth_dev
.iscsi_mac
;
9613 u8
*fip_mac
= bp
->fip_mac
;
9616 /* Zero primary MAC configuration */
9617 memset(bp
->dev
->dev_addr
, 0, ETH_ALEN
);
9620 BNX2X_ERROR("warning: random MAC workaround active\n");
9621 eth_hw_addr_random(bp
->dev
);
9622 } else if (IS_MF(bp
)) {
9623 val2
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
9624 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_lower
);
9625 if ((val2
!= FUNC_MF_CFG_UPPERMAC_DEFAULT
) &&
9626 (val
!= FUNC_MF_CFG_LOWERMAC_DEFAULT
))
9627 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
9631 * iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
9632 * FCoE MAC then the appropriate feature should be disabled.
9634 * In non SD mode features configuration comes from
9635 * struct func_ext_config.
9637 if (!IS_MF_SD(bp
)) {
9638 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
9639 if (cfg
& MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD
) {
9640 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
9641 iscsi_mac_addr_upper
);
9642 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
9643 iscsi_mac_addr_lower
);
9644 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
9645 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9648 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
9650 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
9651 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
9652 fcoe_mac_addr_upper
);
9653 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
9654 fcoe_mac_addr_lower
);
9655 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
9656 BNX2X_DEV_INFO("Read FCoE L2 MAC: %pM\n",
9660 bp
->flags
|= NO_FCOE_FLAG
;
9661 } else { /* SD MODE */
9662 if (IS_MF_STORAGE_SD(bp
)) {
9663 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp
)) {
9664 /* use primary mac as iscsi mac */
9665 memcpy(iscsi_mac
, bp
->dev
->dev_addr
,
9668 BNX2X_DEV_INFO("SD ISCSI MODE\n");
9669 BNX2X_DEV_INFO("Read iSCSI MAC: %pM\n",
9672 memcpy(fip_mac
, bp
->dev
->dev_addr
,
9674 BNX2X_DEV_INFO("SD FCoE MODE\n");
9675 BNX2X_DEV_INFO("Read FIP MAC: %pM\n",
9678 /* Zero primary MAC configuration */
9679 memset(bp
->dev
->dev_addr
, 0, ETH_ALEN
);
9684 /* in SF read MACs from port configuration */
9685 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
9686 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
9687 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
9690 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9692 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9694 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
9696 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9697 fcoe_fip_mac_upper
);
9698 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
9699 fcoe_fip_mac_lower
);
9700 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
9704 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
9705 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
9708 /* Disable iSCSI if MAC configuration is
9711 if (!is_valid_ether_addr(iscsi_mac
)) {
9712 bp
->flags
|= NO_ISCSI_FLAG
;
9713 memset(iscsi_mac
, 0, ETH_ALEN
);
9716 /* Disable FCoE if MAC configuration is
9719 if (!is_valid_ether_addr(fip_mac
)) {
9720 bp
->flags
|= NO_FCOE_FLAG
;
9721 memset(bp
->fip_mac
, 0, ETH_ALEN
);
9725 if (!bnx2x_is_valid_ether_addr(bp
, bp
->dev
->dev_addr
))
9726 dev_err(&bp
->pdev
->dev
,
9727 "bad Ethernet MAC address configuration: %pM\n"
9728 "change it manually before bringing up the appropriate network interface\n",
9734 static int __devinit
bnx2x_get_hwinfo(struct bnx2x
*bp
)
9736 int /*abs*/func
= BP_ABS_FUNC(bp
);
9741 bnx2x_get_common_hwinfo(bp
);
9744 * initialize IGU parameters
9746 if (CHIP_IS_E1x(bp
)) {
9747 bp
->common
.int_block
= INT_BLOCK_HC
;
9749 bp
->igu_dsb_id
= DEF_SB_IGU_ID
;
9750 bp
->igu_base_sb
= 0;
9752 bp
->common
.int_block
= INT_BLOCK_IGU
;
9754 /* do not allow device reset during IGU info preocessing */
9755 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
9757 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
9759 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
9762 BNX2X_DEV_INFO("FORCING Normal Mode\n");
9764 val
&= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
);
9765 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
, val
);
9766 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x7f);
9768 while (tout
&& REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
9770 usleep_range(1000, 1000);
9773 if (REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
9774 dev_err(&bp
->pdev
->dev
,
9775 "FORCING Normal Mode failed!!!\n");
9780 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
9781 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
9782 bp
->common
.int_block
|= INT_BLOCK_MODE_BW_COMP
;
9784 BNX2X_DEV_INFO("IGU Normal Mode\n");
9786 bnx2x_get_igu_cam_info(bp
);
9788 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
9792 * set base FW non-default (fast path) status block id, this value is
9793 * used to initialize the fw_sb_id saved on the fp/queue structure to
9794 * determine the id used by the FW.
9796 if (CHIP_IS_E1x(bp
))
9797 bp
->base_fw_ndsb
= BP_PORT(bp
) * FP_SB_MAX_E1x
+ BP_L_ID(bp
);
9799 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
9800 * the same queue are indicated on the same IGU SB). So we prefer
9801 * FW and IGU SBs to be the same value.
9803 bp
->base_fw_ndsb
= bp
->igu_base_sb
;
9805 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
9806 "base_fw_ndsb %d\n", bp
->igu_dsb_id
, bp
->igu_base_sb
,
9807 bp
->igu_sb_cnt
, bp
->base_fw_ndsb
);
9810 * Initialize MF configuration
9817 if (!CHIP_IS_E1(bp
) && !BP_NOMCP(bp
)) {
9818 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
9819 bp
->common
.shmem2_base
, SHMEM2_RD(bp
, size
),
9820 (u32
)offsetof(struct shmem2_region
, mf_cfg_addr
));
9822 if (SHMEM2_HAS(bp
, mf_cfg_addr
))
9823 bp
->common
.mf_cfg_base
= SHMEM2_RD(bp
, mf_cfg_addr
);
9825 bp
->common
.mf_cfg_base
= bp
->common
.shmem_base
+
9826 offsetof(struct shmem_region
, func_mb
) +
9827 E1H_FUNC_MAX
* sizeof(struct drv_func_mb
);
9829 * get mf configuration:
9830 * 1. existence of MF configuration
9831 * 2. MAC address must be legal (check only upper bytes)
9832 * for Switch-Independent mode;
9833 * OVLAN must be legal for Switch-Dependent mode
9834 * 3. SF_MODE configures specific MF mode
9836 if (bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
9837 /* get mf configuration */
9839 dev_info
.shared_feature_config
.config
);
9840 val
&= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK
;
9843 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT
:
9844 val
= MF_CFG_RD(bp
, func_mf_config
[func
].
9846 /* check for legal mac (upper bytes)*/
9847 if (val
!= 0xffff) {
9848 bp
->mf_mode
= MULTI_FUNCTION_SI
;
9849 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
9850 func_mf_config
[func
].config
);
9852 BNX2X_DEV_INFO("illegal MAC address for SI\n");
9854 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED
:
9855 /* get OV configuration */
9857 func_mf_config
[FUNC_0
].e1hov_tag
);
9858 val
&= FUNC_MF_CFG_E1HOV_TAG_MASK
;
9860 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
9861 bp
->mf_mode
= MULTI_FUNCTION_SD
;
9862 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
9863 func_mf_config
[func
].config
);
9865 BNX2X_DEV_INFO("illegal OV for SD\n");
9868 /* Unknown configuration: reset mf_config */
9869 bp
->mf_config
[vn
] = 0;
9870 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val
);
9874 BNX2X_DEV_INFO("%s function mode\n",
9875 IS_MF(bp
) ? "multi" : "single");
9877 switch (bp
->mf_mode
) {
9878 case MULTI_FUNCTION_SD
:
9879 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
9880 FUNC_MF_CFG_E1HOV_TAG_MASK
;
9881 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
9883 bp
->path_has_ovlan
= true;
9885 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
9886 func
, bp
->mf_ov
, bp
->mf_ov
);
9888 dev_err(&bp
->pdev
->dev
,
9889 "No valid MF OV for func %d, aborting\n",
9894 case MULTI_FUNCTION_SI
:
9895 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
9900 dev_err(&bp
->pdev
->dev
,
9901 "VN %d is in a single function mode, aborting\n",
9908 /* check if other port on the path needs ovlan:
9909 * Since MF configuration is shared between ports
9910 * Possible mixed modes are only
9911 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
9913 if (CHIP_MODE_IS_4_PORT(bp
) &&
9914 !bp
->path_has_ovlan
&&
9916 bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
9917 u8 other_port
= !BP_PORT(bp
);
9918 u8 other_func
= BP_PATH(bp
) + 2*other_port
;
9920 func_mf_config
[other_func
].e1hov_tag
);
9921 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
)
9922 bp
->path_has_ovlan
= true;
9926 /* adjust igu_sb_cnt to MF for E1x */
9927 if (CHIP_IS_E1x(bp
) && IS_MF(bp
))
9928 bp
->igu_sb_cnt
/= E1HVN_MAX
;
9931 bnx2x_get_port_hwinfo(bp
);
9933 /* Get MAC addresses */
9934 bnx2x_get_mac_hwinfo(bp
);
9936 bnx2x_get_cnic_info(bp
);
9941 static void __devinit
bnx2x_read_fwinfo(struct bnx2x
*bp
)
9943 int cnt
, i
, block_end
, rodi
;
9944 char vpd_start
[BNX2X_VPD_LEN
+1];
9945 char str_id_reg
[VENDOR_ID_LEN
+1];
9946 char str_id_cap
[VENDOR_ID_LEN
+1];
9948 char *vpd_extended_data
= NULL
;
9951 cnt
= pci_read_vpd(bp
->pdev
, 0, BNX2X_VPD_LEN
, vpd_start
);
9952 memset(bp
->fw_ver
, 0, sizeof(bp
->fw_ver
));
9954 if (cnt
< BNX2X_VPD_LEN
)
9957 /* VPD RO tag should be first tag after identifier string, hence
9958 * we should be able to find it in first BNX2X_VPD_LEN chars
9960 i
= pci_vpd_find_tag(vpd_start
, 0, BNX2X_VPD_LEN
,
9961 PCI_VPD_LRDT_RO_DATA
);
9965 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+
9966 pci_vpd_lrdt_size(&vpd_start
[i
]);
9968 i
+= PCI_VPD_LRDT_TAG_SIZE
;
9970 if (block_end
> BNX2X_VPD_LEN
) {
9971 vpd_extended_data
= kmalloc(block_end
, GFP_KERNEL
);
9972 if (vpd_extended_data
== NULL
)
9975 /* read rest of vpd image into vpd_extended_data */
9976 memcpy(vpd_extended_data
, vpd_start
, BNX2X_VPD_LEN
);
9977 cnt
= pci_read_vpd(bp
->pdev
, BNX2X_VPD_LEN
,
9978 block_end
- BNX2X_VPD_LEN
,
9979 vpd_extended_data
+ BNX2X_VPD_LEN
);
9980 if (cnt
< (block_end
- BNX2X_VPD_LEN
))
9982 vpd_data
= vpd_extended_data
;
9984 vpd_data
= vpd_start
;
9986 /* now vpd_data holds full vpd content in both cases */
9988 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
9989 PCI_VPD_RO_KEYWORD_MFR_ID
);
9993 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
9995 if (len
!= VENDOR_ID_LEN
)
9998 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
10000 /* vendor specific info */
10001 snprintf(str_id_reg
, VENDOR_ID_LEN
+ 1, "%04x", PCI_VENDOR_ID_DELL
);
10002 snprintf(str_id_cap
, VENDOR_ID_LEN
+ 1, "%04X", PCI_VENDOR_ID_DELL
);
10003 if (!strncmp(str_id_reg
, &vpd_data
[rodi
], VENDOR_ID_LEN
) ||
10004 !strncmp(str_id_cap
, &vpd_data
[rodi
], VENDOR_ID_LEN
)) {
10006 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
10007 PCI_VPD_RO_KEYWORD_VENDOR0
);
10009 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
10011 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
10013 if (len
< 32 && (len
+ rodi
) <= BNX2X_VPD_LEN
) {
10014 memcpy(bp
->fw_ver
, &vpd_data
[rodi
], len
);
10015 bp
->fw_ver
[len
] = ' ';
10018 kfree(vpd_extended_data
);
10022 kfree(vpd_extended_data
);
10026 static void __devinit
bnx2x_set_modes_bitmap(struct bnx2x
*bp
)
10030 if (CHIP_REV_IS_FPGA(bp
))
10031 SET_FLAGS(flags
, MODE_FPGA
);
10032 else if (CHIP_REV_IS_EMUL(bp
))
10033 SET_FLAGS(flags
, MODE_EMUL
);
10035 SET_FLAGS(flags
, MODE_ASIC
);
10037 if (CHIP_MODE_IS_4_PORT(bp
))
10038 SET_FLAGS(flags
, MODE_PORT4
);
10040 SET_FLAGS(flags
, MODE_PORT2
);
10042 if (CHIP_IS_E2(bp
))
10043 SET_FLAGS(flags
, MODE_E2
);
10044 else if (CHIP_IS_E3(bp
)) {
10045 SET_FLAGS(flags
, MODE_E3
);
10046 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
10047 SET_FLAGS(flags
, MODE_E3_A0
);
10048 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
10049 SET_FLAGS(flags
, MODE_E3_B0
| MODE_COS3
);
10053 SET_FLAGS(flags
, MODE_MF
);
10054 switch (bp
->mf_mode
) {
10055 case MULTI_FUNCTION_SD
:
10056 SET_FLAGS(flags
, MODE_MF_SD
);
10058 case MULTI_FUNCTION_SI
:
10059 SET_FLAGS(flags
, MODE_MF_SI
);
10063 SET_FLAGS(flags
, MODE_SF
);
10065 #if defined(__LITTLE_ENDIAN)
10066 SET_FLAGS(flags
, MODE_LITTLE_ENDIAN
);
10067 #else /*(__BIG_ENDIAN)*/
10068 SET_FLAGS(flags
, MODE_BIG_ENDIAN
);
10070 INIT_MODE_FLAGS(bp
) = flags
;
10073 static int __devinit
bnx2x_init_bp(struct bnx2x
*bp
)
10078 mutex_init(&bp
->port
.phy_mutex
);
10079 mutex_init(&bp
->fw_mb_mutex
);
10080 spin_lock_init(&bp
->stats_lock
);
10082 mutex_init(&bp
->cnic_mutex
);
10085 INIT_DELAYED_WORK(&bp
->sp_task
, bnx2x_sp_task
);
10086 INIT_DELAYED_WORK(&bp
->sp_rtnl_task
, bnx2x_sp_rtnl_task
);
10087 INIT_DELAYED_WORK(&bp
->period_task
, bnx2x_period_task
);
10088 rc
= bnx2x_get_hwinfo(bp
);
10092 bnx2x_set_modes_bitmap(bp
);
10094 rc
= bnx2x_alloc_mem_bp(bp
);
10098 bnx2x_read_fwinfo(bp
);
10100 func
= BP_FUNC(bp
);
10102 /* need to reset chip if undi was active */
10104 bnx2x_undi_unload(bp
);
10106 if (CHIP_REV_IS_FPGA(bp
))
10107 dev_err(&bp
->pdev
->dev
, "FPGA detected\n");
10109 if (BP_NOMCP(bp
) && (func
== 0))
10110 dev_err(&bp
->pdev
->dev
, "MCP disabled, must load devices in order!\n");
10112 bp
->multi_mode
= multi_mode
;
10114 bp
->disable_tpa
= disable_tpa
;
10117 bp
->disable_tpa
|= IS_MF_STORAGE_SD(bp
);
10120 /* Set TPA flags */
10121 if (bp
->disable_tpa
) {
10122 bp
->flags
&= ~(TPA_ENABLE_FLAG
| GRO_ENABLE_FLAG
);
10123 bp
->dev
->features
&= ~NETIF_F_LRO
;
10125 bp
->flags
|= (TPA_ENABLE_FLAG
| GRO_ENABLE_FLAG
);
10126 bp
->dev
->features
|= NETIF_F_LRO
;
10129 if (CHIP_IS_E1(bp
))
10130 bp
->dropless_fc
= 0;
10132 bp
->dropless_fc
= dropless_fc
;
10136 bp
->tx_ring_size
= MAX_TX_AVAIL
;
10138 /* make sure that the numbers are in the right granularity */
10139 bp
->tx_ticks
= (50 / BNX2X_BTR
) * BNX2X_BTR
;
10140 bp
->rx_ticks
= (25 / BNX2X_BTR
) * BNX2X_BTR
;
10142 bp
->current_interval
= CHIP_REV_IS_SLOW(bp
) ? 5*HZ
: HZ
;
10144 init_timer(&bp
->timer
);
10145 bp
->timer
.expires
= jiffies
+ bp
->current_interval
;
10146 bp
->timer
.data
= (unsigned long) bp
;
10147 bp
->timer
.function
= bnx2x_timer
;
10149 bnx2x_dcbx_set_state(bp
, true, BNX2X_DCBX_ENABLED_ON_NEG_ON
);
10150 bnx2x_dcbx_init_params(bp
);
10153 if (CHIP_IS_E1x(bp
))
10154 bp
->cnic_base_cl_id
= FP_SB_MAX_E1x
;
10156 bp
->cnic_base_cl_id
= FP_SB_MAX_E2
;
10159 /* multiple tx priority */
10160 if (CHIP_IS_E1x(bp
))
10161 bp
->max_cos
= BNX2X_MULTI_TX_COS_E1X
;
10162 if (CHIP_IS_E2(bp
) || CHIP_IS_E3A0(bp
))
10163 bp
->max_cos
= BNX2X_MULTI_TX_COS_E2_E3A0
;
10164 if (CHIP_IS_E3B0(bp
))
10165 bp
->max_cos
= BNX2X_MULTI_TX_COS_E3B0
;
10167 bp
->gro_check
= bnx2x_need_gro_check(bp
->dev
->mtu
);
10173 /****************************************************************************
10174 * General service functions
10175 ****************************************************************************/
10178 * net_device service functions
10181 /* called with rtnl_lock */
10182 static int bnx2x_open(struct net_device
*dev
)
10184 struct bnx2x
*bp
= netdev_priv(dev
);
10185 bool global
= false;
10186 int other_engine
= BP_PATH(bp
) ? 0 : 1;
10187 bool other_load_status
, load_status
;
10189 bp
->stats_init
= true;
10191 netif_carrier_off(dev
);
10193 bnx2x_set_power_state(bp
, PCI_D0
);
10195 other_load_status
= bnx2x_get_load_status(bp
, other_engine
);
10196 load_status
= bnx2x_get_load_status(bp
, BP_PATH(bp
));
10199 * If parity had happen during the unload, then attentions
10200 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
10201 * want the first function loaded on the current engine to
10202 * complete the recovery.
10204 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
)) ||
10205 bnx2x_chk_parity_attn(bp
, &global
, true))
10208 * If there are attentions and they are in a global
10209 * blocks, set the GLOBAL_RESET bit regardless whether
10210 * it will be this function that will complete the
10214 bnx2x_set_reset_global(bp
);
10217 * Only the first function on the current engine should
10218 * try to recover in open. In case of attentions in
10219 * global blocks only the first in the chip should try
10222 if ((!load_status
&&
10223 (!global
|| !other_load_status
)) &&
10224 bnx2x_trylock_leader_lock(bp
) &&
10225 !bnx2x_leader_reset(bp
)) {
10226 netdev_info(bp
->dev
, "Recovered in open\n");
10230 /* recovery has failed... */
10231 bnx2x_set_power_state(bp
, PCI_D3hot
);
10232 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
10234 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
10235 "If you still see this message after a few retries then power cycle is required.\n");
10240 bp
->recovery_state
= BNX2X_RECOVERY_DONE
;
10241 return bnx2x_nic_load(bp
, LOAD_OPEN
);
10244 /* called with rtnl_lock */
10245 static int bnx2x_close(struct net_device
*dev
)
10247 struct bnx2x
*bp
= netdev_priv(dev
);
10249 /* Unload the driver, release IRQs */
10250 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
);
10253 bnx2x_set_power_state(bp
, PCI_D3hot
);
10258 static inline int bnx2x_init_mcast_macs_list(struct bnx2x
*bp
,
10259 struct bnx2x_mcast_ramrod_params
*p
)
10261 int mc_count
= netdev_mc_count(bp
->dev
);
10262 struct bnx2x_mcast_list_elem
*mc_mac
=
10263 kzalloc(sizeof(*mc_mac
) * mc_count
, GFP_ATOMIC
);
10264 struct netdev_hw_addr
*ha
;
10269 INIT_LIST_HEAD(&p
->mcast_list
);
10271 netdev_for_each_mc_addr(ha
, bp
->dev
) {
10272 mc_mac
->mac
= bnx2x_mc_addr(ha
);
10273 list_add_tail(&mc_mac
->link
, &p
->mcast_list
);
10277 p
->mcast_list_len
= mc_count
;
10282 static inline void bnx2x_free_mcast_macs_list(
10283 struct bnx2x_mcast_ramrod_params
*p
)
10285 struct bnx2x_mcast_list_elem
*mc_mac
=
10286 list_first_entry(&p
->mcast_list
, struct bnx2x_mcast_list_elem
,
10294 * bnx2x_set_uc_list - configure a new unicast MACs list.
10296 * @bp: driver handle
10298 * We will use zero (0) as a MAC type for these MACs.
10300 static inline int bnx2x_set_uc_list(struct bnx2x
*bp
)
10303 struct net_device
*dev
= bp
->dev
;
10304 struct netdev_hw_addr
*ha
;
10305 struct bnx2x_vlan_mac_obj
*mac_obj
= &bp
->fp
->mac_obj
;
10306 unsigned long ramrod_flags
= 0;
10308 /* First schedule a cleanup up of old configuration */
10309 rc
= bnx2x_del_all_macs(bp
, mac_obj
, BNX2X_UC_LIST_MAC
, false);
10311 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc
);
10315 netdev_for_each_uc_addr(ha
, dev
) {
10316 rc
= bnx2x_set_mac_one(bp
, bnx2x_uc_addr(ha
), mac_obj
, true,
10317 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
10319 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
10325 /* Execute the pending commands */
10326 __set_bit(RAMROD_CONT
, &ramrod_flags
);
10327 return bnx2x_set_mac_one(bp
, NULL
, mac_obj
, false /* don't care */,
10328 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
10331 static inline int bnx2x_set_mc_list(struct bnx2x
*bp
)
10333 struct net_device
*dev
= bp
->dev
;
10334 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
10337 rparam
.mcast_obj
= &bp
->mcast_obj
;
10339 /* first, clear all configured multicast MACs */
10340 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
10342 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc
);
10346 /* then, configure a new MACs list */
10347 if (netdev_mc_count(dev
)) {
10348 rc
= bnx2x_init_mcast_macs_list(bp
, &rparam
);
10350 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
10355 /* Now add the new MACs */
10356 rc
= bnx2x_config_mcast(bp
, &rparam
,
10357 BNX2X_MCAST_CMD_ADD
);
10359 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
10362 bnx2x_free_mcast_macs_list(&rparam
);
10369 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
10370 void bnx2x_set_rx_mode(struct net_device
*dev
)
10372 struct bnx2x
*bp
= netdev_priv(dev
);
10373 u32 rx_mode
= BNX2X_RX_MODE_NORMAL
;
10375 if (bp
->state
!= BNX2X_STATE_OPEN
) {
10376 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
10380 DP(NETIF_MSG_IFUP
, "dev->flags = %x\n", bp
->dev
->flags
);
10382 if (dev
->flags
& IFF_PROMISC
)
10383 rx_mode
= BNX2X_RX_MODE_PROMISC
;
10384 else if ((dev
->flags
& IFF_ALLMULTI
) ||
10385 ((netdev_mc_count(dev
) > BNX2X_MAX_MULTICAST
) &&
10387 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
10389 /* some multicasts */
10390 if (bnx2x_set_mc_list(bp
) < 0)
10391 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
10393 if (bnx2x_set_uc_list(bp
) < 0)
10394 rx_mode
= BNX2X_RX_MODE_PROMISC
;
10397 bp
->rx_mode
= rx_mode
;
10399 /* handle ISCSI SD mode */
10400 if (IS_MF_ISCSI_SD(bp
))
10401 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
10404 /* Schedule the rx_mode command */
10405 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
)) {
10406 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
10410 bnx2x_set_storm_rx_mode(bp
);
10413 /* called with rtnl_lock */
10414 static int bnx2x_mdio_read(struct net_device
*netdev
, int prtad
,
10415 int devad
, u16 addr
)
10417 struct bnx2x
*bp
= netdev_priv(netdev
);
10421 DP(NETIF_MSG_LINK
, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
10422 prtad
, devad
, addr
);
10424 /* The HW expects different devad if CL22 is used */
10425 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
10427 bnx2x_acquire_phy_lock(bp
);
10428 rc
= bnx2x_phy_read(&bp
->link_params
, prtad
, devad
, addr
, &value
);
10429 bnx2x_release_phy_lock(bp
);
10430 DP(NETIF_MSG_LINK
, "mdio_read_val 0x%x rc = 0x%x\n", value
, rc
);
10437 /* called with rtnl_lock */
10438 static int bnx2x_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
10439 u16 addr
, u16 value
)
10441 struct bnx2x
*bp
= netdev_priv(netdev
);
10445 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
10446 prtad
, devad
, addr
, value
);
10448 /* The HW expects different devad if CL22 is used */
10449 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
10451 bnx2x_acquire_phy_lock(bp
);
10452 rc
= bnx2x_phy_write(&bp
->link_params
, prtad
, devad
, addr
, value
);
10453 bnx2x_release_phy_lock(bp
);
10457 /* called with rtnl_lock */
10458 static int bnx2x_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
10460 struct bnx2x
*bp
= netdev_priv(dev
);
10461 struct mii_ioctl_data
*mdio
= if_mii(ifr
);
10463 DP(NETIF_MSG_LINK
, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
10464 mdio
->phy_id
, mdio
->reg_num
, mdio
->val_in
);
10466 if (!netif_running(dev
))
10469 return mdio_mii_ioctl(&bp
->mdio
, mdio
, cmd
);
10472 #ifdef CONFIG_NET_POLL_CONTROLLER
10473 static void poll_bnx2x(struct net_device
*dev
)
10475 struct bnx2x
*bp
= netdev_priv(dev
);
10477 disable_irq(bp
->pdev
->irq
);
10478 bnx2x_interrupt(bp
->pdev
->irq
, dev
);
10479 enable_irq(bp
->pdev
->irq
);
10483 static int bnx2x_validate_addr(struct net_device
*dev
)
10485 struct bnx2x
*bp
= netdev_priv(dev
);
10487 if (!bnx2x_is_valid_ether_addr(bp
, dev
->dev_addr
)) {
10488 BNX2X_ERR("Non-valid Ethernet address\n");
10489 return -EADDRNOTAVAIL
;
10494 static const struct net_device_ops bnx2x_netdev_ops
= {
10495 .ndo_open
= bnx2x_open
,
10496 .ndo_stop
= bnx2x_close
,
10497 .ndo_start_xmit
= bnx2x_start_xmit
,
10498 .ndo_select_queue
= bnx2x_select_queue
,
10499 .ndo_set_rx_mode
= bnx2x_set_rx_mode
,
10500 .ndo_set_mac_address
= bnx2x_change_mac_addr
,
10501 .ndo_validate_addr
= bnx2x_validate_addr
,
10502 .ndo_do_ioctl
= bnx2x_ioctl
,
10503 .ndo_change_mtu
= bnx2x_change_mtu
,
10504 .ndo_fix_features
= bnx2x_fix_features
,
10505 .ndo_set_features
= bnx2x_set_features
,
10506 .ndo_tx_timeout
= bnx2x_tx_timeout
,
10507 #ifdef CONFIG_NET_POLL_CONTROLLER
10508 .ndo_poll_controller
= poll_bnx2x
,
10510 .ndo_setup_tc
= bnx2x_setup_tc
,
10512 #if defined(NETDEV_FCOE_WWNN) && defined(BCM_CNIC)
10513 .ndo_fcoe_get_wwn
= bnx2x_fcoe_get_wwn
,
10517 static inline int bnx2x_set_coherency_mask(struct bnx2x
*bp
)
10519 struct device
*dev
= &bp
->pdev
->dev
;
10521 if (dma_set_mask(dev
, DMA_BIT_MASK(64)) == 0) {
10522 bp
->flags
|= USING_DAC_FLAG
;
10523 if (dma_set_coherent_mask(dev
, DMA_BIT_MASK(64)) != 0) {
10524 dev_err(dev
, "dma_set_coherent_mask failed, aborting\n");
10527 } else if (dma_set_mask(dev
, DMA_BIT_MASK(32)) != 0) {
10528 dev_err(dev
, "System does not support DMA, aborting\n");
10535 static int __devinit
bnx2x_init_dev(struct pci_dev
*pdev
,
10536 struct net_device
*dev
,
10537 unsigned long board_type
)
10542 bool chip_is_e1x
= (board_type
== BCM57710
||
10543 board_type
== BCM57711
||
10544 board_type
== BCM57711E
);
10546 SET_NETDEV_DEV(dev
, &pdev
->dev
);
10547 bp
= netdev_priv(dev
);
10553 rc
= pci_enable_device(pdev
);
10555 dev_err(&bp
->pdev
->dev
,
10556 "Cannot enable PCI device, aborting\n");
10560 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
10561 dev_err(&bp
->pdev
->dev
,
10562 "Cannot find PCI device base address, aborting\n");
10564 goto err_out_disable
;
10567 if (!(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
10568 dev_err(&bp
->pdev
->dev
, "Cannot find second PCI device"
10569 " base address, aborting\n");
10571 goto err_out_disable
;
10574 if (atomic_read(&pdev
->enable_cnt
) == 1) {
10575 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
10577 dev_err(&bp
->pdev
->dev
,
10578 "Cannot obtain PCI resources, aborting\n");
10579 goto err_out_disable
;
10582 pci_set_master(pdev
);
10583 pci_save_state(pdev
);
10586 bp
->pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
10587 if (bp
->pm_cap
== 0) {
10588 dev_err(&bp
->pdev
->dev
,
10589 "Cannot find power management capability, aborting\n");
10591 goto err_out_release
;
10594 if (!pci_is_pcie(pdev
)) {
10595 dev_err(&bp
->pdev
->dev
, "Not PCI Express, aborting\n");
10597 goto err_out_release
;
10600 rc
= bnx2x_set_coherency_mask(bp
);
10602 goto err_out_release
;
10604 dev
->mem_start
= pci_resource_start(pdev
, 0);
10605 dev
->base_addr
= dev
->mem_start
;
10606 dev
->mem_end
= pci_resource_end(pdev
, 0);
10608 dev
->irq
= pdev
->irq
;
10610 bp
->regview
= pci_ioremap_bar(pdev
, 0);
10611 if (!bp
->regview
) {
10612 dev_err(&bp
->pdev
->dev
,
10613 "Cannot map register space, aborting\n");
10615 goto err_out_release
;
10618 /* In E1/E1H use pci device function given by kernel.
10619 * In E2/E3 read physical function from ME register since these chips
10620 * support Physical Device Assignment where kernel BDF maybe arbitrary
10621 * (depending on hypervisor).
10624 bp
->pf_num
= PCI_FUNC(pdev
->devfn
);
10625 else {/* chip is E2/3*/
10626 pci_read_config_dword(bp
->pdev
,
10627 PCICFG_ME_REGISTER
, &pci_cfg_dword
);
10628 bp
->pf_num
= (u8
)((pci_cfg_dword
& ME_REG_ABS_PF_NUM
) >>
10629 ME_REG_ABS_PF_NUM_SHIFT
);
10631 BNX2X_DEV_INFO("me reg PF num: %d\n", bp
->pf_num
);
10633 bnx2x_set_power_state(bp
, PCI_D0
);
10635 /* clean indirect addresses */
10636 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
10637 PCICFG_VENDOR_ID_OFFSET
);
10639 * Clean the following indirect addresses for all functions since it
10640 * is not used by the driver.
10642 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F0
, 0);
10643 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F0
, 0);
10644 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F0
, 0);
10645 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F0
, 0);
10648 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F1
, 0);
10649 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F1
, 0);
10650 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F1
, 0);
10651 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F1
, 0);
10655 * Enable internal target-read (in case we are probed after PF FLR).
10656 * Must be done prior to any BAR read access. Only for 57712 and up
10659 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
10661 /* Reset the load counter */
10662 bnx2x_clear_load_status(bp
);
10664 dev
->watchdog_timeo
= TX_TIMEOUT
;
10666 dev
->netdev_ops
= &bnx2x_netdev_ops
;
10667 bnx2x_set_ethtool_ops(dev
);
10669 dev
->priv_flags
|= IFF_UNICAST_FLT
;
10671 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
10672 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
10673 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
|
10674 NETIF_F_RXHASH
| NETIF_F_HW_VLAN_TX
;
10676 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
10677 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_HIGHDMA
;
10679 dev
->features
|= dev
->hw_features
| NETIF_F_HW_VLAN_RX
;
10680 if (bp
->flags
& USING_DAC_FLAG
)
10681 dev
->features
|= NETIF_F_HIGHDMA
;
10683 /* Add Loopback capability to the device */
10684 dev
->hw_features
|= NETIF_F_LOOPBACK
;
10687 dev
->dcbnl_ops
= &bnx2x_dcbnl_ops
;
10690 /* get_port_hwinfo() will set prtad and mmds properly */
10691 bp
->mdio
.prtad
= MDIO_PRTAD_NONE
;
10693 bp
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
10694 bp
->mdio
.dev
= dev
;
10695 bp
->mdio
.mdio_read
= bnx2x_mdio_read
;
10696 bp
->mdio
.mdio_write
= bnx2x_mdio_write
;
10701 if (atomic_read(&pdev
->enable_cnt
) == 1)
10702 pci_release_regions(pdev
);
10705 pci_disable_device(pdev
);
10706 pci_set_drvdata(pdev
, NULL
);
10712 static void __devinit
bnx2x_get_pcie_width_speed(struct bnx2x
*bp
,
10713 int *width
, int *speed
)
10715 u32 val
= REG_RD(bp
, PCICFG_OFFSET
+ PCICFG_LINK_CONTROL
);
10717 *width
= (val
& PCICFG_LINK_WIDTH
) >> PCICFG_LINK_WIDTH_SHIFT
;
10719 /* return value of 1=2.5GHz 2=5GHz */
10720 *speed
= (val
& PCICFG_LINK_SPEED
) >> PCICFG_LINK_SPEED_SHIFT
;
10723 static int bnx2x_check_firmware(struct bnx2x
*bp
)
10725 const struct firmware
*firmware
= bp
->firmware
;
10726 struct bnx2x_fw_file_hdr
*fw_hdr
;
10727 struct bnx2x_fw_file_section
*sections
;
10728 u32 offset
, len
, num_ops
;
10733 if (firmware
->size
< sizeof(struct bnx2x_fw_file_hdr
)) {
10734 BNX2X_ERR("Wrong FW size\n");
10738 fw_hdr
= (struct bnx2x_fw_file_hdr
*)firmware
->data
;
10739 sections
= (struct bnx2x_fw_file_section
*)fw_hdr
;
10741 /* Make sure none of the offsets and sizes make us read beyond
10742 * the end of the firmware data */
10743 for (i
= 0; i
< sizeof(*fw_hdr
) / sizeof(*sections
); i
++) {
10744 offset
= be32_to_cpu(sections
[i
].offset
);
10745 len
= be32_to_cpu(sections
[i
].len
);
10746 if (offset
+ len
> firmware
->size
) {
10747 BNX2X_ERR("Section %d length is out of bounds\n", i
);
10752 /* Likewise for the init_ops offsets */
10753 offset
= be32_to_cpu(fw_hdr
->init_ops_offsets
.offset
);
10754 ops_offsets
= (u16
*)(firmware
->data
+ offset
);
10755 num_ops
= be32_to_cpu(fw_hdr
->init_ops
.len
) / sizeof(struct raw_op
);
10757 for (i
= 0; i
< be32_to_cpu(fw_hdr
->init_ops_offsets
.len
) / 2; i
++) {
10758 if (be16_to_cpu(ops_offsets
[i
]) > num_ops
) {
10759 BNX2X_ERR("Section offset %d is out of bounds\n", i
);
10764 /* Check FW version */
10765 offset
= be32_to_cpu(fw_hdr
->fw_version
.offset
);
10766 fw_ver
= firmware
->data
+ offset
;
10767 if ((fw_ver
[0] != BCM_5710_FW_MAJOR_VERSION
) ||
10768 (fw_ver
[1] != BCM_5710_FW_MINOR_VERSION
) ||
10769 (fw_ver
[2] != BCM_5710_FW_REVISION_VERSION
) ||
10770 (fw_ver
[3] != BCM_5710_FW_ENGINEERING_VERSION
)) {
10771 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
10772 fw_ver
[0], fw_ver
[1], fw_ver
[2], fw_ver
[3],
10773 BCM_5710_FW_MAJOR_VERSION
,
10774 BCM_5710_FW_MINOR_VERSION
,
10775 BCM_5710_FW_REVISION_VERSION
,
10776 BCM_5710_FW_ENGINEERING_VERSION
);
10783 static inline void be32_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
10785 const __be32
*source
= (const __be32
*)_source
;
10786 u32
*target
= (u32
*)_target
;
10789 for (i
= 0; i
< n
/4; i
++)
10790 target
[i
] = be32_to_cpu(source
[i
]);
10794 Ops array is stored in the following format:
10795 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
10797 static inline void bnx2x_prep_ops(const u8
*_source
, u8
*_target
, u32 n
)
10799 const __be32
*source
= (const __be32
*)_source
;
10800 struct raw_op
*target
= (struct raw_op
*)_target
;
10803 for (i
= 0, j
= 0; i
< n
/8; i
++, j
+= 2) {
10804 tmp
= be32_to_cpu(source
[j
]);
10805 target
[i
].op
= (tmp
>> 24) & 0xff;
10806 target
[i
].offset
= tmp
& 0xffffff;
10807 target
[i
].raw_data
= be32_to_cpu(source
[j
+ 1]);
10812 * IRO array is stored in the following format:
10813 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
10815 static inline void bnx2x_prep_iro(const u8
*_source
, u8
*_target
, u32 n
)
10817 const __be32
*source
= (const __be32
*)_source
;
10818 struct iro
*target
= (struct iro
*)_target
;
10821 for (i
= 0, j
= 0; i
< n
/sizeof(struct iro
); i
++) {
10822 target
[i
].base
= be32_to_cpu(source
[j
]);
10824 tmp
= be32_to_cpu(source
[j
]);
10825 target
[i
].m1
= (tmp
>> 16) & 0xffff;
10826 target
[i
].m2
= tmp
& 0xffff;
10828 tmp
= be32_to_cpu(source
[j
]);
10829 target
[i
].m3
= (tmp
>> 16) & 0xffff;
10830 target
[i
].size
= tmp
& 0xffff;
10835 static inline void be16_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
10837 const __be16
*source
= (const __be16
*)_source
;
10838 u16
*target
= (u16
*)_target
;
10841 for (i
= 0; i
< n
/2; i
++)
10842 target
[i
] = be16_to_cpu(source
[i
]);
10845 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
10847 u32 len = be32_to_cpu(fw_hdr->arr.len); \
10848 bp->arr = kmalloc(len, GFP_KERNEL); \
10851 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
10852 (u8 *)bp->arr, len); \
10855 static int bnx2x_init_firmware(struct bnx2x
*bp
)
10857 const char *fw_file_name
;
10858 struct bnx2x_fw_file_hdr
*fw_hdr
;
10864 if (CHIP_IS_E1(bp
))
10865 fw_file_name
= FW_FILE_NAME_E1
;
10866 else if (CHIP_IS_E1H(bp
))
10867 fw_file_name
= FW_FILE_NAME_E1H
;
10868 else if (!CHIP_IS_E1x(bp
))
10869 fw_file_name
= FW_FILE_NAME_E2
;
10871 BNX2X_ERR("Unsupported chip revision\n");
10874 BNX2X_DEV_INFO("Loading %s\n", fw_file_name
);
10876 rc
= request_firmware(&bp
->firmware
, fw_file_name
, &bp
->pdev
->dev
);
10878 BNX2X_ERR("Can't load firmware file %s\n",
10880 goto request_firmware_exit
;
10883 rc
= bnx2x_check_firmware(bp
);
10885 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name
);
10886 goto request_firmware_exit
;
10889 fw_hdr
= (struct bnx2x_fw_file_hdr
*)bp
->firmware
->data
;
10891 /* Initialize the pointers to the init arrays */
10893 BNX2X_ALLOC_AND_SET(init_data
, request_firmware_exit
, be32_to_cpu_n
);
10896 BNX2X_ALLOC_AND_SET(init_ops
, init_ops_alloc_err
, bnx2x_prep_ops
);
10899 BNX2X_ALLOC_AND_SET(init_ops_offsets
, init_offsets_alloc_err
,
10902 /* STORMs firmware */
10903 INIT_TSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10904 be32_to_cpu(fw_hdr
->tsem_int_table_data
.offset
);
10905 INIT_TSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10906 be32_to_cpu(fw_hdr
->tsem_pram_data
.offset
);
10907 INIT_USEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10908 be32_to_cpu(fw_hdr
->usem_int_table_data
.offset
);
10909 INIT_USEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10910 be32_to_cpu(fw_hdr
->usem_pram_data
.offset
);
10911 INIT_XSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10912 be32_to_cpu(fw_hdr
->xsem_int_table_data
.offset
);
10913 INIT_XSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10914 be32_to_cpu(fw_hdr
->xsem_pram_data
.offset
);
10915 INIT_CSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
10916 be32_to_cpu(fw_hdr
->csem_int_table_data
.offset
);
10917 INIT_CSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
10918 be32_to_cpu(fw_hdr
->csem_pram_data
.offset
);
10920 BNX2X_ALLOC_AND_SET(iro_arr
, iro_alloc_err
, bnx2x_prep_iro
);
10925 kfree(bp
->init_ops_offsets
);
10926 init_offsets_alloc_err
:
10927 kfree(bp
->init_ops
);
10928 init_ops_alloc_err
:
10929 kfree(bp
->init_data
);
10930 request_firmware_exit
:
10931 release_firmware(bp
->firmware
);
10932 bp
->firmware
= NULL
;
10937 static void bnx2x_release_firmware(struct bnx2x
*bp
)
10939 kfree(bp
->init_ops_offsets
);
10940 kfree(bp
->init_ops
);
10941 kfree(bp
->init_data
);
10942 release_firmware(bp
->firmware
);
10943 bp
->firmware
= NULL
;
10947 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv
= {
10948 .init_hw_cmn_chip
= bnx2x_init_hw_common_chip
,
10949 .init_hw_cmn
= bnx2x_init_hw_common
,
10950 .init_hw_port
= bnx2x_init_hw_port
,
10951 .init_hw_func
= bnx2x_init_hw_func
,
10953 .reset_hw_cmn
= bnx2x_reset_common
,
10954 .reset_hw_port
= bnx2x_reset_port
,
10955 .reset_hw_func
= bnx2x_reset_func
,
10957 .gunzip_init
= bnx2x_gunzip_init
,
10958 .gunzip_end
= bnx2x_gunzip_end
,
10960 .init_fw
= bnx2x_init_firmware
,
10961 .release_fw
= bnx2x_release_firmware
,
10964 void bnx2x__init_func_obj(struct bnx2x
*bp
)
10966 /* Prepare DMAE related driver resources */
10967 bnx2x_setup_dmae(bp
);
10969 bnx2x_init_func_obj(bp
, &bp
->func_obj
,
10970 bnx2x_sp(bp
, func_rdata
),
10971 bnx2x_sp_mapping(bp
, func_rdata
),
10972 &bnx2x_func_sp_drv
);
10975 /* must be called after sriov-enable */
10976 static inline int bnx2x_set_qm_cid_count(struct bnx2x
*bp
)
10978 int cid_count
= BNX2X_L2_CID_COUNT(bp
);
10981 cid_count
+= CNIC_CID_MAX
;
10983 return roundup(cid_count
, QM_CID_ROUND
);
10987 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
10992 static inline int bnx2x_get_num_non_def_sbs(struct pci_dev
*pdev
)
10997 pos
= pci_find_capability(pdev
, PCI_CAP_ID_MSIX
);
11000 * If MSI-X is not supported - return number of SBs needed to support
11001 * one fast path queue: one FP queue + SB for CNIC
11004 return 1 + CNIC_PRESENT
;
11007 * The value in the PCI configuration space is the index of the last
11008 * entry, namely one less than the actual size of the table, which is
11009 * exactly what we want to return from this function: number of all SBs
11010 * without the default SB.
11012 pci_read_config_word(pdev
, pos
+ PCI_MSI_FLAGS
, &control
);
11013 return control
& PCI_MSIX_FLAGS_QSIZE
;
11016 static int __devinit
bnx2x_init_one(struct pci_dev
*pdev
,
11017 const struct pci_device_id
*ent
)
11019 struct net_device
*dev
= NULL
;
11021 int pcie_width
, pcie_speed
;
11022 int rc
, max_non_def_sbs
;
11023 int rx_count
, tx_count
, rss_count
;
11025 * An estimated maximum supported CoS number according to the chip
11027 * We will try to roughly estimate the maximum number of CoSes this chip
11028 * may support in order to minimize the memory allocated for Tx
11029 * netdev_queue's. This number will be accurately calculated during the
11030 * initialization of bp->max_cos based on the chip versions AND chip
11031 * revision in the bnx2x_init_bp().
11033 u8 max_cos_est
= 0;
11035 switch (ent
->driver_data
) {
11039 max_cos_est
= BNX2X_MULTI_TX_COS_E1X
;
11044 max_cos_est
= BNX2X_MULTI_TX_COS_E2_E3A0
;
11053 max_cos_est
= BNX2X_MULTI_TX_COS_E3B0
;
11057 pr_err("Unknown board_type (%ld), aborting\n",
11062 max_non_def_sbs
= bnx2x_get_num_non_def_sbs(pdev
);
11065 * Do not allow the maximum SB count to grow above 16
11066 * since Special CIDs starts from 16*BNX2X_MULTI_TX_COS=48.
11067 * We will use the FP_SB_MAX_E1x macro for this matter.
11069 max_non_def_sbs
= min_t(int, FP_SB_MAX_E1x
, max_non_def_sbs
);
11071 WARN_ON(!max_non_def_sbs
);
11073 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
11074 rss_count
= max_non_def_sbs
- CNIC_PRESENT
;
11076 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
11077 rx_count
= rss_count
+ FCOE_PRESENT
;
11080 * Maximum number of netdev Tx queues:
11081 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
11083 tx_count
= MAX_TXQS_PER_COS
* max_cos_est
+ FCOE_PRESENT
;
11085 /* dev zeroed in init_etherdev */
11086 dev
= alloc_etherdev_mqs(sizeof(*bp
), tx_count
, rx_count
);
11090 bp
= netdev_priv(dev
);
11092 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
11093 tx_count
, rx_count
);
11095 bp
->igu_sb_cnt
= max_non_def_sbs
;
11096 bp
->msg_enable
= debug
;
11097 pci_set_drvdata(pdev
, dev
);
11099 rc
= bnx2x_init_dev(pdev
, dev
, ent
->driver_data
);
11105 BNX2X_DEV_INFO("max_non_def_sbs %d\n", max_non_def_sbs
);
11107 rc
= bnx2x_init_bp(bp
);
11109 goto init_one_exit
;
11112 * Map doorbels here as we need the real value of bp->max_cos which
11113 * is initialized in bnx2x_init_bp().
11115 bp
->doorbells
= ioremap_nocache(pci_resource_start(pdev
, 2),
11116 min_t(u64
, BNX2X_DB_SIZE(bp
),
11117 pci_resource_len(pdev
, 2)));
11118 if (!bp
->doorbells
) {
11119 dev_err(&bp
->pdev
->dev
,
11120 "Cannot map doorbell space, aborting\n");
11122 goto init_one_exit
;
11125 /* calc qm_cid_count */
11126 bp
->qm_cid_count
= bnx2x_set_qm_cid_count(bp
);
11129 /* disable FCOE L2 queue for E1x */
11130 if (CHIP_IS_E1x(bp
))
11131 bp
->flags
|= NO_FCOE_FLAG
;
11135 /* Configure interrupt mode: try to enable MSI-X/MSI if
11136 * needed, set bp->num_queues appropriately.
11138 bnx2x_set_int_mode(bp
);
11140 /* Add all NAPI objects */
11141 bnx2x_add_all_napi(bp
);
11143 rc
= register_netdev(dev
);
11145 dev_err(&pdev
->dev
, "Cannot register net device\n");
11146 goto init_one_exit
;
11150 if (!NO_FCOE(bp
)) {
11151 /* Add storage MAC address */
11153 dev_addr_add(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
11158 bnx2x_get_pcie_width_speed(bp
, &pcie_width
, &pcie_speed
);
11161 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
11162 board_info
[ent
->driver_data
].name
,
11163 (CHIP_REV(bp
) >> 12) + 'A', (CHIP_METAL(bp
) >> 4),
11165 ((!CHIP_IS_E2(bp
) && pcie_speed
== 2) ||
11166 (CHIP_IS_E2(bp
) && pcie_speed
== 1)) ?
11167 "5GHz (Gen2)" : "2.5GHz",
11168 dev
->base_addr
, bp
->pdev
->irq
, dev
->dev_addr
);
11174 iounmap(bp
->regview
);
11177 iounmap(bp
->doorbells
);
11181 if (atomic_read(&pdev
->enable_cnt
) == 1)
11182 pci_release_regions(pdev
);
11184 pci_disable_device(pdev
);
11185 pci_set_drvdata(pdev
, NULL
);
11190 static void __devexit
bnx2x_remove_one(struct pci_dev
*pdev
)
11192 struct net_device
*dev
= pci_get_drvdata(pdev
);
11196 dev_err(&pdev
->dev
, "BAD net device from bnx2x_init_one\n");
11199 bp
= netdev_priv(dev
);
11202 /* Delete storage MAC address */
11203 if (!NO_FCOE(bp
)) {
11205 dev_addr_del(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
11211 /* Delete app tlvs from dcbnl */
11212 bnx2x_dcbnl_update_applist(bp
, true);
11215 unregister_netdev(dev
);
11217 /* Delete all NAPI objects */
11218 bnx2x_del_all_napi(bp
);
11220 /* Power on: we can't let PCI layer write to us while we are in D3 */
11221 bnx2x_set_power_state(bp
, PCI_D0
);
11223 /* Disable MSI/MSI-X */
11224 bnx2x_disable_msi(bp
);
11227 bnx2x_set_power_state(bp
, PCI_D3hot
);
11229 /* Make sure RESET task is not scheduled before continuing */
11230 cancel_delayed_work_sync(&bp
->sp_rtnl_task
);
11233 iounmap(bp
->regview
);
11236 iounmap(bp
->doorbells
);
11238 bnx2x_release_firmware(bp
);
11240 bnx2x_free_mem_bp(bp
);
11244 if (atomic_read(&pdev
->enable_cnt
) == 1)
11245 pci_release_regions(pdev
);
11247 pci_disable_device(pdev
);
11248 pci_set_drvdata(pdev
, NULL
);
11251 static int bnx2x_eeh_nic_unload(struct bnx2x
*bp
)
11255 bp
->state
= BNX2X_STATE_ERROR
;
11257 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
11260 bnx2x_cnic_notify(bp
, CNIC_CTL_STOP_CMD
);
11263 bnx2x_tx_disable(bp
);
11265 bnx2x_netif_stop(bp
, 0);
11267 del_timer_sync(&bp
->timer
);
11269 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
11272 bnx2x_free_irq(bp
);
11274 /* Free SKBs, SGEs, TPA pool and driver internals */
11275 bnx2x_free_skbs(bp
);
11277 for_each_rx_queue(bp
, i
)
11278 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
11280 bnx2x_free_mem(bp
);
11282 bp
->state
= BNX2X_STATE_CLOSED
;
11284 netif_carrier_off(bp
->dev
);
11289 static void bnx2x_eeh_recover(struct bnx2x
*bp
)
11293 mutex_init(&bp
->port
.phy_mutex
);
11296 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
11297 if ((val
& (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
11298 != (SHR_MEM_VALIDITY_DEV_INFO
| SHR_MEM_VALIDITY_MB
))
11299 BNX2X_ERR("BAD MCP validity signature\n");
11303 * bnx2x_io_error_detected - called when PCI error is detected
11304 * @pdev: Pointer to PCI device
11305 * @state: The current pci connection state
11307 * This function is called after a PCI bus error affecting
11308 * this device has been detected.
11310 static pci_ers_result_t
bnx2x_io_error_detected(struct pci_dev
*pdev
,
11311 pci_channel_state_t state
)
11313 struct net_device
*dev
= pci_get_drvdata(pdev
);
11314 struct bnx2x
*bp
= netdev_priv(dev
);
11318 netif_device_detach(dev
);
11320 if (state
== pci_channel_io_perm_failure
) {
11322 return PCI_ERS_RESULT_DISCONNECT
;
11325 if (netif_running(dev
))
11326 bnx2x_eeh_nic_unload(bp
);
11328 pci_disable_device(pdev
);
11332 /* Request a slot reset */
11333 return PCI_ERS_RESULT_NEED_RESET
;
11337 * bnx2x_io_slot_reset - called after the PCI bus has been reset
11338 * @pdev: Pointer to PCI device
11340 * Restart the card from scratch, as if from a cold-boot.
11342 static pci_ers_result_t
bnx2x_io_slot_reset(struct pci_dev
*pdev
)
11344 struct net_device
*dev
= pci_get_drvdata(pdev
);
11345 struct bnx2x
*bp
= netdev_priv(dev
);
11349 if (pci_enable_device(pdev
)) {
11350 dev_err(&pdev
->dev
,
11351 "Cannot re-enable PCI device after reset\n");
11353 return PCI_ERS_RESULT_DISCONNECT
;
11356 pci_set_master(pdev
);
11357 pci_restore_state(pdev
);
11359 if (netif_running(dev
))
11360 bnx2x_set_power_state(bp
, PCI_D0
);
11364 return PCI_ERS_RESULT_RECOVERED
;
11368 * bnx2x_io_resume - called when traffic can start flowing again
11369 * @pdev: Pointer to PCI device
11371 * This callback is called when the error recovery driver tells us that
11372 * its OK to resume normal operation.
11374 static void bnx2x_io_resume(struct pci_dev
*pdev
)
11376 struct net_device
*dev
= pci_get_drvdata(pdev
);
11377 struct bnx2x
*bp
= netdev_priv(dev
);
11379 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
11380 netdev_err(bp
->dev
, "Handling parity error recovery. Try again later\n");
11386 bnx2x_eeh_recover(bp
);
11388 if (netif_running(dev
))
11389 bnx2x_nic_load(bp
, LOAD_NORMAL
);
11391 netif_device_attach(dev
);
11396 static struct pci_error_handlers bnx2x_err_handler
= {
11397 .error_detected
= bnx2x_io_error_detected
,
11398 .slot_reset
= bnx2x_io_slot_reset
,
11399 .resume
= bnx2x_io_resume
,
11402 static struct pci_driver bnx2x_pci_driver
= {
11403 .name
= DRV_MODULE_NAME
,
11404 .id_table
= bnx2x_pci_tbl
,
11405 .probe
= bnx2x_init_one
,
11406 .remove
= __devexit_p(bnx2x_remove_one
),
11407 .suspend
= bnx2x_suspend
,
11408 .resume
= bnx2x_resume
,
11409 .err_handler
= &bnx2x_err_handler
,
11412 static int __init
bnx2x_init(void)
11416 pr_info("%s", version
);
11418 bnx2x_wq
= create_singlethread_workqueue("bnx2x");
11419 if (bnx2x_wq
== NULL
) {
11420 pr_err("Cannot create workqueue\n");
11424 ret
= pci_register_driver(&bnx2x_pci_driver
);
11426 pr_err("Cannot register driver\n");
11427 destroy_workqueue(bnx2x_wq
);
11432 static void __exit
bnx2x_cleanup(void)
11434 pci_unregister_driver(&bnx2x_pci_driver
);
11436 destroy_workqueue(bnx2x_wq
);
11439 void bnx2x_notify_link_changed(struct bnx2x
*bp
)
11441 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ BP_FUNC(bp
)*sizeof(u32
), 1);
11444 module_init(bnx2x_init
);
11445 module_exit(bnx2x_cleanup
);
11449 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
11451 * @bp: driver handle
11452 * @set: set or clear the CAM entry
11454 * This function will wait until the ramdord completion returns.
11455 * Return 0 if success, -ENODEV if ramrod doesn't return.
11457 static inline int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x
*bp
)
11459 unsigned long ramrod_flags
= 0;
11461 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
11462 return bnx2x_set_mac_one(bp
, bp
->cnic_eth_dev
.iscsi_mac
,
11463 &bp
->iscsi_l2_mac_obj
, true,
11464 BNX2X_ISCSI_ETH_MAC
, &ramrod_flags
);
11467 /* count denotes the number of new completions we have seen */
11468 static void bnx2x_cnic_sp_post(struct bnx2x
*bp
, int count
)
11470 struct eth_spe
*spe
;
11472 #ifdef BNX2X_STOP_ON_ERROR
11473 if (unlikely(bp
->panic
))
11477 spin_lock_bh(&bp
->spq_lock
);
11478 BUG_ON(bp
->cnic_spq_pending
< count
);
11479 bp
->cnic_spq_pending
-= count
;
11482 for (; bp
->cnic_kwq_pending
; bp
->cnic_kwq_pending
--) {
11483 u16 type
= (le16_to_cpu(bp
->cnic_kwq_cons
->hdr
.type
)
11484 & SPE_HDR_CONN_TYPE
) >>
11485 SPE_HDR_CONN_TYPE_SHIFT
;
11486 u8 cmd
= (le32_to_cpu(bp
->cnic_kwq_cons
->hdr
.conn_and_cmd_data
)
11487 >> SPE_HDR_CMD_ID_SHIFT
) & 0xff;
11489 /* Set validation for iSCSI L2 client before sending SETUP
11492 if (type
== ETH_CONNECTION_TYPE
) {
11493 if (cmd
== RAMROD_CMD_ID_ETH_CLIENT_SETUP
)
11494 bnx2x_set_ctx_validation(bp
, &bp
->context
.
11495 vcxt
[BNX2X_ISCSI_ETH_CID
].eth
,
11496 BNX2X_ISCSI_ETH_CID
);
11500 * There may be not more than 8 L2, not more than 8 L5 SPEs
11501 * and in the air. We also check that number of outstanding
11502 * COMMON ramrods is not more than the EQ and SPQ can
11505 if (type
== ETH_CONNECTION_TYPE
) {
11506 if (!atomic_read(&bp
->cq_spq_left
))
11509 atomic_dec(&bp
->cq_spq_left
);
11510 } else if (type
== NONE_CONNECTION_TYPE
) {
11511 if (!atomic_read(&bp
->eq_spq_left
))
11514 atomic_dec(&bp
->eq_spq_left
);
11515 } else if ((type
== ISCSI_CONNECTION_TYPE
) ||
11516 (type
== FCOE_CONNECTION_TYPE
)) {
11517 if (bp
->cnic_spq_pending
>=
11518 bp
->cnic_eth_dev
.max_kwqe_pending
)
11521 bp
->cnic_spq_pending
++;
11523 BNX2X_ERR("Unknown SPE type: %d\n", type
);
11528 spe
= bnx2x_sp_get_next(bp
);
11529 *spe
= *bp
->cnic_kwq_cons
;
11531 DP(BNX2X_MSG_SP
, "pending on SPQ %d, on KWQ %d count %d\n",
11532 bp
->cnic_spq_pending
, bp
->cnic_kwq_pending
, count
);
11534 if (bp
->cnic_kwq_cons
== bp
->cnic_kwq_last
)
11535 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
11537 bp
->cnic_kwq_cons
++;
11539 bnx2x_sp_prod_update(bp
);
11540 spin_unlock_bh(&bp
->spq_lock
);
11543 static int bnx2x_cnic_sp_queue(struct net_device
*dev
,
11544 struct kwqe_16
*kwqes
[], u32 count
)
11546 struct bnx2x
*bp
= netdev_priv(dev
);
11549 #ifdef BNX2X_STOP_ON_ERROR
11550 if (unlikely(bp
->panic
)) {
11551 BNX2X_ERR("Can't post to SP queue while panic\n");
11556 if ((bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) &&
11557 (bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
11558 BNX2X_ERR("Handling parity error recovery. Try again later\n");
11562 spin_lock_bh(&bp
->spq_lock
);
11564 for (i
= 0; i
< count
; i
++) {
11565 struct eth_spe
*spe
= (struct eth_spe
*)kwqes
[i
];
11567 if (bp
->cnic_kwq_pending
== MAX_SP_DESC_CNT
)
11570 *bp
->cnic_kwq_prod
= *spe
;
11572 bp
->cnic_kwq_pending
++;
11574 DP(BNX2X_MSG_SP
, "L5 SPQE %x %x %x:%x pos %d\n",
11575 spe
->hdr
.conn_and_cmd_data
, spe
->hdr
.type
,
11576 spe
->data
.update_data_addr
.hi
,
11577 spe
->data
.update_data_addr
.lo
,
11578 bp
->cnic_kwq_pending
);
11580 if (bp
->cnic_kwq_prod
== bp
->cnic_kwq_last
)
11581 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
11583 bp
->cnic_kwq_prod
++;
11586 spin_unlock_bh(&bp
->spq_lock
);
11588 if (bp
->cnic_spq_pending
< bp
->cnic_eth_dev
.max_kwqe_pending
)
11589 bnx2x_cnic_sp_post(bp
, 0);
11594 static int bnx2x_cnic_ctl_send(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
11596 struct cnic_ops
*c_ops
;
11599 mutex_lock(&bp
->cnic_mutex
);
11600 c_ops
= rcu_dereference_protected(bp
->cnic_ops
,
11601 lockdep_is_held(&bp
->cnic_mutex
));
11603 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
11604 mutex_unlock(&bp
->cnic_mutex
);
11609 static int bnx2x_cnic_ctl_send_bh(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
11611 struct cnic_ops
*c_ops
;
11615 c_ops
= rcu_dereference(bp
->cnic_ops
);
11617 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
11624 * for commands that have no data
11626 int bnx2x_cnic_notify(struct bnx2x
*bp
, int cmd
)
11628 struct cnic_ctl_info ctl
= {0};
11632 return bnx2x_cnic_ctl_send(bp
, &ctl
);
11635 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
)
11637 struct cnic_ctl_info ctl
= {0};
11639 /* first we tell CNIC and only then we count this as a completion */
11640 ctl
.cmd
= CNIC_CTL_COMPLETION_CMD
;
11641 ctl
.data
.comp
.cid
= cid
;
11642 ctl
.data
.comp
.error
= err
;
11644 bnx2x_cnic_ctl_send_bh(bp
, &ctl
);
11645 bnx2x_cnic_sp_post(bp
, 0);
11649 /* Called with netif_addr_lock_bh() taken.
11650 * Sets an rx_mode config for an iSCSI ETH client.
11652 * Completion should be checked outside.
11654 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
)
11656 unsigned long accept_flags
= 0, ramrod_flags
= 0;
11657 u8 cl_id
= bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
11658 int sched_state
= BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
;
11661 /* Start accepting on iSCSI L2 ring. Accept all multicasts
11662 * because it's the only way for UIO Queue to accept
11663 * multicasts (in non-promiscuous mode only one Queue per
11664 * function will receive multicast packets (leading in our
11667 __set_bit(BNX2X_ACCEPT_UNICAST
, &accept_flags
);
11668 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &accept_flags
);
11669 __set_bit(BNX2X_ACCEPT_BROADCAST
, &accept_flags
);
11670 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &accept_flags
);
11672 /* Clear STOP_PENDING bit if START is requested */
11673 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &bp
->sp_state
);
11675 sched_state
= BNX2X_FILTER_ISCSI_ETH_START_SCHED
;
11677 /* Clear START_PENDING bit if STOP is requested */
11678 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &bp
->sp_state
);
11680 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
11681 set_bit(sched_state
, &bp
->sp_state
);
11683 __set_bit(RAMROD_RX
, &ramrod_flags
);
11684 bnx2x_set_q_rx_mode(bp
, cl_id
, 0, accept_flags
, 0,
11690 static int bnx2x_drv_ctl(struct net_device
*dev
, struct drv_ctl_info
*ctl
)
11692 struct bnx2x
*bp
= netdev_priv(dev
);
11695 switch (ctl
->cmd
) {
11696 case DRV_CTL_CTXTBL_WR_CMD
: {
11697 u32 index
= ctl
->data
.io
.offset
;
11698 dma_addr_t addr
= ctl
->data
.io
.dma_addr
;
11700 bnx2x_ilt_wr(bp
, index
, addr
);
11704 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD
: {
11705 int count
= ctl
->data
.credit
.credit_count
;
11707 bnx2x_cnic_sp_post(bp
, count
);
11711 /* rtnl_lock is held. */
11712 case DRV_CTL_START_L2_CMD
: {
11713 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11714 unsigned long sp_bits
= 0;
11716 /* Configure the iSCSI classification object */
11717 bnx2x_init_mac_obj(bp
, &bp
->iscsi_l2_mac_obj
,
11718 cp
->iscsi_l2_client_id
,
11719 cp
->iscsi_l2_cid
, BP_FUNC(bp
),
11720 bnx2x_sp(bp
, mac_rdata
),
11721 bnx2x_sp_mapping(bp
, mac_rdata
),
11722 BNX2X_FILTER_MAC_PENDING
,
11723 &bp
->sp_state
, BNX2X_OBJ_TYPE_RX
,
11726 /* Set iSCSI MAC address */
11727 rc
= bnx2x_set_iscsi_eth_mac_addr(bp
);
11734 /* Start accepting on iSCSI L2 ring */
11736 netif_addr_lock_bh(dev
);
11737 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
11738 netif_addr_unlock_bh(dev
);
11740 /* bits to wait on */
11741 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
11742 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &sp_bits
);
11744 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
11745 BNX2X_ERR("rx_mode completion timed out!\n");
11750 /* rtnl_lock is held. */
11751 case DRV_CTL_STOP_L2_CMD
: {
11752 unsigned long sp_bits
= 0;
11754 /* Stop accepting on iSCSI L2 ring */
11755 netif_addr_lock_bh(dev
);
11756 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
11757 netif_addr_unlock_bh(dev
);
11759 /* bits to wait on */
11760 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
11761 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &sp_bits
);
11763 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
11764 BNX2X_ERR("rx_mode completion timed out!\n");
11769 /* Unset iSCSI L2 MAC */
11770 rc
= bnx2x_del_all_macs(bp
, &bp
->iscsi_l2_mac_obj
,
11771 BNX2X_ISCSI_ETH_MAC
, true);
11774 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD
: {
11775 int count
= ctl
->data
.credit
.credit_count
;
11777 smp_mb__before_atomic_inc();
11778 atomic_add(count
, &bp
->cq_spq_left
);
11779 smp_mb__after_atomic_inc();
11782 case DRV_CTL_ULP_REGISTER_CMD
: {
11783 int ulp_type
= ctl
->data
.ulp_type
;
11785 if (CHIP_IS_E3(bp
)) {
11786 int idx
= BP_FW_MB_IDX(bp
);
11789 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
11790 if (ulp_type
== CNIC_ULP_ISCSI
)
11791 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
11792 else if (ulp_type
== CNIC_ULP_FCOE
)
11793 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
11794 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
11798 case DRV_CTL_ULP_UNREGISTER_CMD
: {
11799 int ulp_type
= ctl
->data
.ulp_type
;
11801 if (CHIP_IS_E3(bp
)) {
11802 int idx
= BP_FW_MB_IDX(bp
);
11805 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
11806 if (ulp_type
== CNIC_ULP_ISCSI
)
11807 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
11808 else if (ulp_type
== CNIC_ULP_FCOE
)
11809 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
11810 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
11816 BNX2X_ERR("unknown command %x\n", ctl
->cmd
);
11823 void bnx2x_setup_cnic_irq_info(struct bnx2x
*bp
)
11825 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11827 if (bp
->flags
& USING_MSIX_FLAG
) {
11828 cp
->drv_state
|= CNIC_DRV_STATE_USING_MSIX
;
11829 cp
->irq_arr
[0].irq_flags
|= CNIC_IRQ_FL_MSIX
;
11830 cp
->irq_arr
[0].vector
= bp
->msix_table
[1].vector
;
11832 cp
->drv_state
&= ~CNIC_DRV_STATE_USING_MSIX
;
11833 cp
->irq_arr
[0].irq_flags
&= ~CNIC_IRQ_FL_MSIX
;
11835 if (!CHIP_IS_E1x(bp
))
11836 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e2_sb
;
11838 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e1x_sb
;
11840 cp
->irq_arr
[0].status_blk_num
= bnx2x_cnic_fw_sb_id(bp
);
11841 cp
->irq_arr
[0].status_blk_num2
= bnx2x_cnic_igu_sb_id(bp
);
11842 cp
->irq_arr
[1].status_blk
= bp
->def_status_blk
;
11843 cp
->irq_arr
[1].status_blk_num
= DEF_SB_ID
;
11844 cp
->irq_arr
[1].status_blk_num2
= DEF_SB_IGU_ID
;
11849 static int bnx2x_register_cnic(struct net_device
*dev
, struct cnic_ops
*ops
,
11852 struct bnx2x
*bp
= netdev_priv(dev
);
11853 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11856 BNX2X_ERR("NULL ops received\n");
11860 bp
->cnic_kwq
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
11864 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
11865 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
11866 bp
->cnic_kwq_last
= bp
->cnic_kwq
+ MAX_SP_DESC_CNT
;
11868 bp
->cnic_spq_pending
= 0;
11869 bp
->cnic_kwq_pending
= 0;
11871 bp
->cnic_data
= data
;
11874 cp
->drv_state
|= CNIC_DRV_STATE_REGD
;
11875 cp
->iro_arr
= bp
->iro_arr
;
11877 bnx2x_setup_cnic_irq_info(bp
);
11879 rcu_assign_pointer(bp
->cnic_ops
, ops
);
11884 static int bnx2x_unregister_cnic(struct net_device
*dev
)
11886 struct bnx2x
*bp
= netdev_priv(dev
);
11887 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11889 mutex_lock(&bp
->cnic_mutex
);
11891 RCU_INIT_POINTER(bp
->cnic_ops
, NULL
);
11892 mutex_unlock(&bp
->cnic_mutex
);
11894 kfree(bp
->cnic_kwq
);
11895 bp
->cnic_kwq
= NULL
;
11900 struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
)
11902 struct bnx2x
*bp
= netdev_priv(dev
);
11903 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
11905 /* If both iSCSI and FCoE are disabled - return NULL in
11906 * order to indicate CNIC that it should not try to work
11907 * with this device.
11909 if (NO_ISCSI(bp
) && NO_FCOE(bp
))
11912 cp
->drv_owner
= THIS_MODULE
;
11913 cp
->chip_id
= CHIP_ID(bp
);
11914 cp
->pdev
= bp
->pdev
;
11915 cp
->io_base
= bp
->regview
;
11916 cp
->io_base2
= bp
->doorbells
;
11917 cp
->max_kwqe_pending
= 8;
11918 cp
->ctx_blk_size
= CDU_ILT_PAGE_SZ
;
11919 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
11920 bnx2x_cid_ilt_lines(bp
);
11921 cp
->ctx_tbl_len
= CNIC_ILT_LINES
;
11922 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
11923 cp
->drv_submit_kwqes_16
= bnx2x_cnic_sp_queue
;
11924 cp
->drv_ctl
= bnx2x_drv_ctl
;
11925 cp
->drv_register_cnic
= bnx2x_register_cnic
;
11926 cp
->drv_unregister_cnic
= bnx2x_unregister_cnic
;
11927 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID
;
11928 cp
->iscsi_l2_client_id
=
11929 bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
11930 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID
;
11932 if (NO_ISCSI_OOO(bp
))
11933 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
11936 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI
;
11939 cp
->drv_state
|= CNIC_DRV_STATE_NO_FCOE
;
11942 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
11944 cp
->ctx_tbl_offset
,
11949 EXPORT_SYMBOL(bnx2x_cnic_probe
);
11951 #endif /* BCM_CNIC */