1 /* bnx2x_main.c: QLogic Everest network driver.
3 * Copyright (c) 2007-2013 Broadcom Corporation
4 * Copyright (c) 2014 QLogic Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation.
11 * Maintained by: Ariel Elior <ariel.elior@qlogic.com>
12 * Written by: Eliezer Tamir
13 * Based on code from Michael Chan's bnx2 driver
14 * UDP CSUM errata workaround by Arik Gendelman
15 * Slowpath and fastpath rework by Vladislav Zolotarov
16 * Statistics and Link management by Yitchak Gertner
20 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
22 #include <linux/module.h>
23 #include <linux/moduleparam.h>
24 #include <linux/kernel.h>
25 #include <linux/device.h> /* for dev_info() */
26 #include <linux/timer.h>
27 #include <linux/errno.h>
28 #include <linux/ioport.h>
29 #include <linux/slab.h>
30 #include <linux/interrupt.h>
31 #include <linux/pci.h>
32 #include <linux/aer.h>
33 #include <linux/init.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/bitops.h>
39 #include <linux/irq.h>
40 #include <linux/delay.h>
41 #include <asm/byteorder.h>
42 #include <linux/time.h>
43 #include <linux/ethtool.h>
44 #include <linux/mii.h>
45 #include <linux/if_vlan.h>
46 #include <linux/crash_dump.h>
50 #include <net/vxlan.h>
51 #include <net/checksum.h>
52 #include <net/ip6_checksum.h>
53 #include <linux/workqueue.h>
54 #include <linux/crc32.h>
55 #include <linux/crc32c.h>
56 #include <linux/prefetch.h>
57 #include <linux/zlib.h>
59 #include <linux/semaphore.h>
60 #include <linux/stringify.h>
61 #include <linux/vmalloc.h>
62 #if IS_ENABLED(CONFIG_BNX2X_GENEVE)
63 #include <net/geneve.h>
66 #include "bnx2x_init.h"
67 #include "bnx2x_init_ops.h"
68 #include "bnx2x_cmn.h"
69 #include "bnx2x_vfpf.h"
70 #include "bnx2x_dcb.h"
72 #include <linux/firmware.h>
73 #include "bnx2x_fw_file_hdr.h"
75 #define FW_FILE_VERSION \
76 __stringify(BCM_5710_FW_MAJOR_VERSION) "." \
77 __stringify(BCM_5710_FW_MINOR_VERSION) "." \
78 __stringify(BCM_5710_FW_REVISION_VERSION) "." \
79 __stringify(BCM_5710_FW_ENGINEERING_VERSION)
80 #define FW_FILE_NAME_E1 "bnx2x/bnx2x-e1-" FW_FILE_VERSION ".fw"
81 #define FW_FILE_NAME_E1H "bnx2x/bnx2x-e1h-" FW_FILE_VERSION ".fw"
82 #define FW_FILE_NAME_E2 "bnx2x/bnx2x-e2-" FW_FILE_VERSION ".fw"
84 /* Time in jiffies before concluding the transmitter is hung */
85 #define TX_TIMEOUT (5*HZ)
87 static char version
[] =
88 "QLogic 5771x/578xx 10/20-Gigabit Ethernet Driver "
89 DRV_MODULE_NAME
" " DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
91 MODULE_AUTHOR("Eliezer Tamir");
92 MODULE_DESCRIPTION("QLogic "
93 "BCM57710/57711/57711E/"
94 "57712/57712_MF/57800/57800_MF/57810/57810_MF/"
95 "57840/57840_MF Driver");
96 MODULE_LICENSE("GPL");
97 MODULE_VERSION(DRV_MODULE_VERSION
);
98 MODULE_FIRMWARE(FW_FILE_NAME_E1
);
99 MODULE_FIRMWARE(FW_FILE_NAME_E1H
);
100 MODULE_FIRMWARE(FW_FILE_NAME_E2
);
102 int bnx2x_num_queues
;
103 module_param_named(num_queues
, bnx2x_num_queues
, int, S_IRUGO
);
104 MODULE_PARM_DESC(num_queues
,
105 " Set number of queues (default is as a number of CPUs)");
107 static int disable_tpa
;
108 module_param(disable_tpa
, int, S_IRUGO
);
109 MODULE_PARM_DESC(disable_tpa
, " Disable the TPA (LRO) feature");
112 module_param(int_mode
, int, S_IRUGO
);
113 MODULE_PARM_DESC(int_mode
, " Force interrupt mode other than MSI-X "
116 static int dropless_fc
;
117 module_param(dropless_fc
, int, S_IRUGO
);
118 MODULE_PARM_DESC(dropless_fc
, " Pause on exhausted host ring");
120 static int mrrs
= -1;
121 module_param(mrrs
, int, S_IRUGO
);
122 MODULE_PARM_DESC(mrrs
, " Force Max Read Req Size (0..3) (for debug)");
125 module_param(debug
, int, S_IRUGO
);
126 MODULE_PARM_DESC(debug
, " Default debug msglevel");
128 static struct workqueue_struct
*bnx2x_wq
;
129 struct workqueue_struct
*bnx2x_iov_wq
;
131 struct bnx2x_mac_vals
{
142 enum bnx2x_board_type
{
166 /* indexed by board_type, above */
170 [BCM57710
] = { "QLogic BCM57710 10 Gigabit PCIe [Everest]" },
171 [BCM57711
] = { "QLogic BCM57711 10 Gigabit PCIe" },
172 [BCM57711E
] = { "QLogic BCM57711E 10 Gigabit PCIe" },
173 [BCM57712
] = { "QLogic BCM57712 10 Gigabit Ethernet" },
174 [BCM57712_MF
] = { "QLogic BCM57712 10 Gigabit Ethernet Multi Function" },
175 [BCM57712_VF
] = { "QLogic BCM57712 10 Gigabit Ethernet Virtual Function" },
176 [BCM57800
] = { "QLogic BCM57800 10 Gigabit Ethernet" },
177 [BCM57800_MF
] = { "QLogic BCM57800 10 Gigabit Ethernet Multi Function" },
178 [BCM57800_VF
] = { "QLogic BCM57800 10 Gigabit Ethernet Virtual Function" },
179 [BCM57810
] = { "QLogic BCM57810 10 Gigabit Ethernet" },
180 [BCM57810_MF
] = { "QLogic BCM57810 10 Gigabit Ethernet Multi Function" },
181 [BCM57810_VF
] = { "QLogic BCM57810 10 Gigabit Ethernet Virtual Function" },
182 [BCM57840_4_10
] = { "QLogic BCM57840 10 Gigabit Ethernet" },
183 [BCM57840_2_20
] = { "QLogic BCM57840 20 Gigabit Ethernet" },
184 [BCM57840_MF
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
185 [BCM57840_VF
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" },
186 [BCM57811
] = { "QLogic BCM57811 10 Gigabit Ethernet" },
187 [BCM57811_MF
] = { "QLogic BCM57811 10 Gigabit Ethernet Multi Function" },
188 [BCM57840_O
] = { "QLogic BCM57840 10/20 Gigabit Ethernet" },
189 [BCM57840_MFO
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Multi Function" },
190 [BCM57811_VF
] = { "QLogic BCM57840 10/20 Gigabit Ethernet Virtual Function" }
193 #ifndef PCI_DEVICE_ID_NX2_57710
194 #define PCI_DEVICE_ID_NX2_57710 CHIP_NUM_57710
196 #ifndef PCI_DEVICE_ID_NX2_57711
197 #define PCI_DEVICE_ID_NX2_57711 CHIP_NUM_57711
199 #ifndef PCI_DEVICE_ID_NX2_57711E
200 #define PCI_DEVICE_ID_NX2_57711E CHIP_NUM_57711E
202 #ifndef PCI_DEVICE_ID_NX2_57712
203 #define PCI_DEVICE_ID_NX2_57712 CHIP_NUM_57712
205 #ifndef PCI_DEVICE_ID_NX2_57712_MF
206 #define PCI_DEVICE_ID_NX2_57712_MF CHIP_NUM_57712_MF
208 #ifndef PCI_DEVICE_ID_NX2_57712_VF
209 #define PCI_DEVICE_ID_NX2_57712_VF CHIP_NUM_57712_VF
211 #ifndef PCI_DEVICE_ID_NX2_57800
212 #define PCI_DEVICE_ID_NX2_57800 CHIP_NUM_57800
214 #ifndef PCI_DEVICE_ID_NX2_57800_MF
215 #define PCI_DEVICE_ID_NX2_57800_MF CHIP_NUM_57800_MF
217 #ifndef PCI_DEVICE_ID_NX2_57800_VF
218 #define PCI_DEVICE_ID_NX2_57800_VF CHIP_NUM_57800_VF
220 #ifndef PCI_DEVICE_ID_NX2_57810
221 #define PCI_DEVICE_ID_NX2_57810 CHIP_NUM_57810
223 #ifndef PCI_DEVICE_ID_NX2_57810_MF
224 #define PCI_DEVICE_ID_NX2_57810_MF CHIP_NUM_57810_MF
226 #ifndef PCI_DEVICE_ID_NX2_57840_O
227 #define PCI_DEVICE_ID_NX2_57840_O CHIP_NUM_57840_OBSOLETE
229 #ifndef PCI_DEVICE_ID_NX2_57810_VF
230 #define PCI_DEVICE_ID_NX2_57810_VF CHIP_NUM_57810_VF
232 #ifndef PCI_DEVICE_ID_NX2_57840_4_10
233 #define PCI_DEVICE_ID_NX2_57840_4_10 CHIP_NUM_57840_4_10
235 #ifndef PCI_DEVICE_ID_NX2_57840_2_20
236 #define PCI_DEVICE_ID_NX2_57840_2_20 CHIP_NUM_57840_2_20
238 #ifndef PCI_DEVICE_ID_NX2_57840_MFO
239 #define PCI_DEVICE_ID_NX2_57840_MFO CHIP_NUM_57840_MF_OBSOLETE
241 #ifndef PCI_DEVICE_ID_NX2_57840_MF
242 #define PCI_DEVICE_ID_NX2_57840_MF CHIP_NUM_57840_MF
244 #ifndef PCI_DEVICE_ID_NX2_57840_VF
245 #define PCI_DEVICE_ID_NX2_57840_VF CHIP_NUM_57840_VF
247 #ifndef PCI_DEVICE_ID_NX2_57811
248 #define PCI_DEVICE_ID_NX2_57811 CHIP_NUM_57811
250 #ifndef PCI_DEVICE_ID_NX2_57811_MF
251 #define PCI_DEVICE_ID_NX2_57811_MF CHIP_NUM_57811_MF
253 #ifndef PCI_DEVICE_ID_NX2_57811_VF
254 #define PCI_DEVICE_ID_NX2_57811_VF CHIP_NUM_57811_VF
257 static const struct pci_device_id bnx2x_pci_tbl
[] = {
258 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57710
), BCM57710
},
259 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711
), BCM57711
},
260 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57711E
), BCM57711E
},
261 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712
), BCM57712
},
262 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_MF
), BCM57712_MF
},
263 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57712_VF
), BCM57712_VF
},
264 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800
), BCM57800
},
265 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_MF
), BCM57800_MF
},
266 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57800_VF
), BCM57800_VF
},
267 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810
), BCM57810
},
268 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_MF
), BCM57810_MF
},
269 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_O
), BCM57840_O
},
270 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_4_10
), BCM57840_4_10
},
271 { PCI_VDEVICE(QLOGIC
, PCI_DEVICE_ID_NX2_57840_4_10
), BCM57840_4_10
},
272 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_2_20
), BCM57840_2_20
},
273 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57810_VF
), BCM57810_VF
},
274 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MFO
), BCM57840_MFO
},
275 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
276 { PCI_VDEVICE(QLOGIC
, PCI_DEVICE_ID_NX2_57840_MF
), BCM57840_MF
},
277 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57840_VF
), BCM57840_VF
},
278 { PCI_VDEVICE(QLOGIC
, PCI_DEVICE_ID_NX2_57840_VF
), BCM57840_VF
},
279 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811
), BCM57811
},
280 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_MF
), BCM57811_MF
},
281 { PCI_VDEVICE(BROADCOM
, PCI_DEVICE_ID_NX2_57811_VF
), BCM57811_VF
},
285 MODULE_DEVICE_TABLE(pci
, bnx2x_pci_tbl
);
287 /* Global resources for unloading a previously loaded device */
288 #define BNX2X_PREV_WAIT_NEEDED 1
289 static DEFINE_SEMAPHORE(bnx2x_prev_sem
);
290 static LIST_HEAD(bnx2x_prev_list
);
292 /* Forward declaration */
293 static struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
);
294 static u32
bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath
*fp
);
295 static int bnx2x_set_storm_rx_mode(struct bnx2x
*bp
);
297 /****************************************************************************
298 * General service functions
299 ****************************************************************************/
301 static int bnx2x_hwtstamp_ioctl(struct bnx2x
*bp
, struct ifreq
*ifr
);
303 static void __storm_memset_dma_mapping(struct bnx2x
*bp
,
304 u32 addr
, dma_addr_t mapping
)
306 REG_WR(bp
, addr
, U64_LO(mapping
));
307 REG_WR(bp
, addr
+ 4, U64_HI(mapping
));
310 static void storm_memset_spq_addr(struct bnx2x
*bp
,
311 dma_addr_t mapping
, u16 abs_fid
)
313 u32 addr
= XSEM_REG_FAST_MEMORY
+
314 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid
);
316 __storm_memset_dma_mapping(bp
, addr
, mapping
);
319 static void storm_memset_vf_to_pf(struct bnx2x
*bp
, u16 abs_fid
,
322 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_VF_TO_PF_OFFSET(abs_fid
),
324 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_VF_TO_PF_OFFSET(abs_fid
),
326 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_VF_TO_PF_OFFSET(abs_fid
),
328 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_VF_TO_PF_OFFSET(abs_fid
),
332 static void storm_memset_func_en(struct bnx2x
*bp
, u16 abs_fid
,
335 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(abs_fid
),
337 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(abs_fid
),
339 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(abs_fid
),
341 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(abs_fid
),
345 static void storm_memset_eq_data(struct bnx2x
*bp
,
346 struct event_ring_data
*eq_data
,
349 size_t size
= sizeof(struct event_ring_data
);
351 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_DATA_OFFSET(pfid
);
353 __storm_memset_struct(bp
, addr
, size
, (u32
*)eq_data
);
356 static void storm_memset_eq_prod(struct bnx2x
*bp
, u16 eq_prod
,
359 u32 addr
= BAR_CSTRORM_INTMEM
+ CSTORM_EVENT_RING_PROD_OFFSET(pfid
);
360 REG_WR16(bp
, addr
, eq_prod
);
364 * locking is done by mcp
366 static void bnx2x_reg_wr_ind(struct bnx2x
*bp
, u32 addr
, u32 val
)
368 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
369 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, val
);
370 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
371 PCICFG_VENDOR_ID_OFFSET
);
374 static u32
bnx2x_reg_rd_ind(struct bnx2x
*bp
, u32 addr
)
378 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
, addr
);
379 pci_read_config_dword(bp
->pdev
, PCICFG_GRC_DATA
, &val
);
380 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
381 PCICFG_VENDOR_ID_OFFSET
);
386 #define DMAE_DP_SRC_GRC "grc src_addr [%08x]"
387 #define DMAE_DP_SRC_PCI "pci src_addr [%x:%08x]"
388 #define DMAE_DP_DST_GRC "grc dst_addr [%08x]"
389 #define DMAE_DP_DST_PCI "pci dst_addr [%x:%08x]"
390 #define DMAE_DP_DST_NONE "dst_addr [none]"
392 static void bnx2x_dp_dmae(struct bnx2x
*bp
,
393 struct dmae_command
*dmae
, int msglvl
)
395 u32 src_type
= dmae
->opcode
& DMAE_COMMAND_SRC
;
398 switch (dmae
->opcode
& DMAE_COMMAND_DST
) {
399 case DMAE_CMD_DST_PCI
:
400 if (src_type
== DMAE_CMD_SRC_PCI
)
401 DP(msglvl
, "DMAE: opcode 0x%08x\n"
402 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n"
403 "comp_addr [%x:%08x], comp_val 0x%08x\n",
404 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
405 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
406 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
409 DP(msglvl
, "DMAE: opcode 0x%08x\n"
410 "src [%08x], len [%d*4], dst [%x:%08x]\n"
411 "comp_addr [%x:%08x], comp_val 0x%08x\n",
412 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
413 dmae
->len
, dmae
->dst_addr_hi
, dmae
->dst_addr_lo
,
414 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
417 case DMAE_CMD_DST_GRC
:
418 if (src_type
== DMAE_CMD_SRC_PCI
)
419 DP(msglvl
, "DMAE: opcode 0x%08x\n"
420 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n"
421 "comp_addr [%x:%08x], comp_val 0x%08x\n",
422 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
423 dmae
->len
, dmae
->dst_addr_lo
>> 2,
424 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
427 DP(msglvl
, "DMAE: opcode 0x%08x\n"
428 "src [%08x], len [%d*4], dst [%08x]\n"
429 "comp_addr [%x:%08x], comp_val 0x%08x\n",
430 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
431 dmae
->len
, dmae
->dst_addr_lo
>> 2,
432 dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
436 if (src_type
== DMAE_CMD_SRC_PCI
)
437 DP(msglvl
, "DMAE: opcode 0x%08x\n"
438 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n"
439 "comp_addr [%x:%08x] comp_val 0x%08x\n",
440 dmae
->opcode
, dmae
->src_addr_hi
, dmae
->src_addr_lo
,
441 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
444 DP(msglvl
, "DMAE: opcode 0x%08x\n"
445 "src_addr [%08x] len [%d * 4] dst_addr [none]\n"
446 "comp_addr [%x:%08x] comp_val 0x%08x\n",
447 dmae
->opcode
, dmae
->src_addr_lo
>> 2,
448 dmae
->len
, dmae
->comp_addr_hi
, dmae
->comp_addr_lo
,
453 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++)
454 DP(msglvl
, "DMAE RAW [%02d]: 0x%08x\n",
455 i
, *(((u32
*)dmae
) + i
));
458 /* copy command into DMAE command memory and set DMAE command go */
459 void bnx2x_post_dmae(struct bnx2x
*bp
, struct dmae_command
*dmae
, int idx
)
464 cmd_offset
= (DMAE_REG_CMD_MEM
+ sizeof(struct dmae_command
) * idx
);
465 for (i
= 0; i
< (sizeof(struct dmae_command
)/4); i
++) {
466 REG_WR(bp
, cmd_offset
+ i
*4, *(((u32
*)dmae
) + i
));
468 REG_WR(bp
, dmae_reg_go_c
[idx
], 1);
471 u32
bnx2x_dmae_opcode_add_comp(u32 opcode
, u8 comp_type
)
473 return opcode
| ((comp_type
<< DMAE_COMMAND_C_DST_SHIFT
) |
477 u32
bnx2x_dmae_opcode_clr_src_reset(u32 opcode
)
479 return opcode
& ~DMAE_CMD_SRC_RESET
;
482 u32
bnx2x_dmae_opcode(struct bnx2x
*bp
, u8 src_type
, u8 dst_type
,
483 bool with_comp
, u8 comp_type
)
487 opcode
|= ((src_type
<< DMAE_COMMAND_SRC_SHIFT
) |
488 (dst_type
<< DMAE_COMMAND_DST_SHIFT
));
490 opcode
|= (DMAE_CMD_SRC_RESET
| DMAE_CMD_DST_RESET
);
492 opcode
|= (BP_PORT(bp
) ? DMAE_CMD_PORT_1
: DMAE_CMD_PORT_0
);
493 opcode
|= ((BP_VN(bp
) << DMAE_CMD_E1HVN_SHIFT
) |
494 (BP_VN(bp
) << DMAE_COMMAND_DST_VN_SHIFT
));
495 opcode
|= (DMAE_COM_SET_ERR
<< DMAE_COMMAND_ERR_POLICY_SHIFT
);
498 opcode
|= DMAE_CMD_ENDIANITY_B_DW_SWAP
;
500 opcode
|= DMAE_CMD_ENDIANITY_DW_SWAP
;
503 opcode
= bnx2x_dmae_opcode_add_comp(opcode
, comp_type
);
507 void bnx2x_prep_dmae_with_comp(struct bnx2x
*bp
,
508 struct dmae_command
*dmae
,
509 u8 src_type
, u8 dst_type
)
511 memset(dmae
, 0, sizeof(struct dmae_command
));
514 dmae
->opcode
= bnx2x_dmae_opcode(bp
, src_type
, dst_type
,
515 true, DMAE_COMP_PCI
);
517 /* fill in the completion parameters */
518 dmae
->comp_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_comp
));
519 dmae
->comp_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_comp
));
520 dmae
->comp_val
= DMAE_COMP_VAL
;
523 /* issue a dmae command over the init-channel and wait for completion */
524 int bnx2x_issue_dmae_with_comp(struct bnx2x
*bp
, struct dmae_command
*dmae
,
527 int cnt
= CHIP_REV_IS_SLOW(bp
) ? (400000) : 4000;
530 bnx2x_dp_dmae(bp
, dmae
, BNX2X_MSG_DMAE
);
532 /* Lock the dmae channel. Disable BHs to prevent a dead-lock
533 * as long as this code is called both from syscall context and
534 * from ndo_set_rx_mode() flow that may be called from BH.
537 spin_lock_bh(&bp
->dmae_lock
);
539 /* reset completion */
542 /* post the command on the channel used for initializations */
543 bnx2x_post_dmae(bp
, dmae
, INIT_DMAE_C(bp
));
545 /* wait for completion */
547 while ((*comp
& ~DMAE_PCI_ERR_FLAG
) != DMAE_COMP_VAL
) {
550 (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
&&
551 bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
552 BNX2X_ERR("DMAE timeout!\n");
559 if (*comp
& DMAE_PCI_ERR_FLAG
) {
560 BNX2X_ERR("DMAE PCI error!\n");
566 spin_unlock_bh(&bp
->dmae_lock
);
571 void bnx2x_write_dmae(struct bnx2x
*bp
, dma_addr_t dma_addr
, u32 dst_addr
,
575 struct dmae_command dmae
;
577 if (!bp
->dmae_ready
) {
578 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
581 bnx2x_init_ind_wr(bp
, dst_addr
, data
, len32
);
583 bnx2x_init_str_wr(bp
, dst_addr
, data
, len32
);
587 /* set opcode and fixed command fields */
588 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_PCI
, DMAE_DST_GRC
);
590 /* fill in addresses and len */
591 dmae
.src_addr_lo
= U64_LO(dma_addr
);
592 dmae
.src_addr_hi
= U64_HI(dma_addr
);
593 dmae
.dst_addr_lo
= dst_addr
>> 2;
594 dmae
.dst_addr_hi
= 0;
597 /* issue the command and wait for completion */
598 rc
= bnx2x_issue_dmae_with_comp(bp
, &dmae
, bnx2x_sp(bp
, wb_comp
));
600 BNX2X_ERR("DMAE returned failure %d\n", rc
);
601 #ifdef BNX2X_STOP_ON_ERROR
607 void bnx2x_read_dmae(struct bnx2x
*bp
, u32 src_addr
, u32 len32
)
610 struct dmae_command dmae
;
612 if (!bp
->dmae_ready
) {
613 u32
*data
= bnx2x_sp(bp
, wb_data
[0]);
617 for (i
= 0; i
< len32
; i
++)
618 data
[i
] = bnx2x_reg_rd_ind(bp
, src_addr
+ i
*4);
620 for (i
= 0; i
< len32
; i
++)
621 data
[i
] = REG_RD(bp
, src_addr
+ i
*4);
626 /* set opcode and fixed command fields */
627 bnx2x_prep_dmae_with_comp(bp
, &dmae
, DMAE_SRC_GRC
, DMAE_DST_PCI
);
629 /* fill in addresses and len */
630 dmae
.src_addr_lo
= src_addr
>> 2;
631 dmae
.src_addr_hi
= 0;
632 dmae
.dst_addr_lo
= U64_LO(bnx2x_sp_mapping(bp
, wb_data
));
633 dmae
.dst_addr_hi
= U64_HI(bnx2x_sp_mapping(bp
, wb_data
));
636 /* issue the command and wait for completion */
637 rc
= bnx2x_issue_dmae_with_comp(bp
, &dmae
, bnx2x_sp(bp
, wb_comp
));
639 BNX2X_ERR("DMAE returned failure %d\n", rc
);
640 #ifdef BNX2X_STOP_ON_ERROR
646 static void bnx2x_write_dmae_phys_len(struct bnx2x
*bp
, dma_addr_t phys_addr
,
649 int dmae_wr_max
= DMAE_LEN32_WR_MAX(bp
);
652 while (len
> dmae_wr_max
) {
653 bnx2x_write_dmae(bp
, phys_addr
+ offset
,
654 addr
+ offset
, dmae_wr_max
);
655 offset
+= dmae_wr_max
* 4;
659 bnx2x_write_dmae(bp
, phys_addr
+ offset
, addr
+ offset
, len
);
671 #define REGS_IN_ENTRY 4
673 static inline int bnx2x_get_assert_list_entry(struct bnx2x
*bp
,
679 return XSTORM_ASSERT_LIST_OFFSET(entry
);
681 return TSTORM_ASSERT_LIST_OFFSET(entry
);
683 return CSTORM_ASSERT_LIST_OFFSET(entry
);
685 return USTORM_ASSERT_LIST_OFFSET(entry
);
688 BNX2X_ERR("unknown storm\n");
693 static int bnx2x_mc_assert(struct bnx2x
*bp
)
698 u32 regs
[REGS_IN_ENTRY
];
699 u32 bar_storm_intmem
[STORMS_NUM
] = {
705 u32 storm_assert_list_index
[STORMS_NUM
] = {
706 XSTORM_ASSERT_LIST_INDEX_OFFSET
,
707 TSTORM_ASSERT_LIST_INDEX_OFFSET
,
708 CSTORM_ASSERT_LIST_INDEX_OFFSET
,
709 USTORM_ASSERT_LIST_INDEX_OFFSET
711 char *storms_string
[STORMS_NUM
] = {
718 for (storm
= XSTORM
; storm
< MAX_STORMS
; storm
++) {
719 last_idx
= REG_RD8(bp
, bar_storm_intmem
[storm
] +
720 storm_assert_list_index
[storm
]);
722 BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
723 storms_string
[storm
], last_idx
);
725 /* print the asserts */
726 for (i
= 0; i
< STROM_ASSERT_ARRAY_SIZE
; i
++) {
727 /* read a single assert entry */
728 for (j
= 0; j
< REGS_IN_ENTRY
; j
++)
729 regs
[j
] = REG_RD(bp
, bar_storm_intmem
[storm
] +
730 bnx2x_get_assert_list_entry(bp
,
735 /* log entry if it contains a valid assert */
736 if (regs
[0] != COMMON_ASM_INVALID_ASSERT_OPCODE
) {
737 BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
738 storms_string
[storm
], i
, regs
[3],
739 regs
[2], regs
[1], regs
[0]);
747 BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
748 CHIP_IS_E1(bp
) ? "everest1" :
749 CHIP_IS_E1H(bp
) ? "everest1h" :
750 CHIP_IS_E2(bp
) ? "everest2" : "everest3",
751 BCM_5710_FW_MAJOR_VERSION
,
752 BCM_5710_FW_MINOR_VERSION
,
753 BCM_5710_FW_REVISION_VERSION
);
758 #define MCPR_TRACE_BUFFER_SIZE (0x800)
759 #define SCRATCH_BUFFER_SIZE(bp) \
760 (CHIP_IS_E1(bp) ? 0x10000 : (CHIP_IS_E1H(bp) ? 0x20000 : 0x28000))
762 void bnx2x_fw_dump_lvl(struct bnx2x
*bp
, const char *lvl
)
768 u32 trace_shmem_base
;
770 BNX2X_ERR("NO MCP - can not dump\n");
773 netdev_printk(lvl
, bp
->dev
, "bc %d.%d.%d\n",
774 (bp
->common
.bc_ver
& 0xff0000) >> 16,
775 (bp
->common
.bc_ver
& 0xff00) >> 8,
776 (bp
->common
.bc_ver
& 0xff));
778 val
= REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
);
779 if (val
== REG_RD(bp
, MCP_REG_MCPR_CPU_PROGRAM_COUNTER
))
780 BNX2X_ERR("%s" "MCP PC at 0x%x\n", lvl
, val
);
782 if (BP_PATH(bp
) == 0)
783 trace_shmem_base
= bp
->common
.shmem_base
;
785 trace_shmem_base
= SHMEM2_RD(bp
, other_shmem_base_addr
);
788 if (trace_shmem_base
< MCPR_SCRATCH_BASE(bp
) + MCPR_TRACE_BUFFER_SIZE
||
789 trace_shmem_base
>= MCPR_SCRATCH_BASE(bp
) +
790 SCRATCH_BUFFER_SIZE(bp
)) {
791 BNX2X_ERR("Unable to dump trace buffer (mark %x)\n",
796 addr
= trace_shmem_base
- MCPR_TRACE_BUFFER_SIZE
;
798 /* validate TRCB signature */
799 mark
= REG_RD(bp
, addr
);
800 if (mark
!= MFW_TRACE_SIGNATURE
) {
801 BNX2X_ERR("Trace buffer signature is missing.");
805 /* read cyclic buffer pointer */
807 mark
= REG_RD(bp
, addr
);
808 mark
= MCPR_SCRATCH_BASE(bp
) + ((mark
+ 0x3) & ~0x3) - 0x08000000;
809 if (mark
>= trace_shmem_base
|| mark
< addr
+ 4) {
810 BNX2X_ERR("Mark doesn't fall inside Trace Buffer\n");
813 printk("%s" "begin fw dump (mark 0x%x)\n", lvl
, mark
);
817 /* dump buffer after the mark */
818 for (offset
= mark
; offset
< trace_shmem_base
; offset
+= 0x8*4) {
819 for (word
= 0; word
< 8; word
++)
820 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
822 pr_cont("%s", (char *)data
);
825 /* dump buffer before the mark */
826 for (offset
= addr
+ 4; offset
<= mark
; offset
+= 0x8*4) {
827 for (word
= 0; word
< 8; word
++)
828 data
[word
] = htonl(REG_RD(bp
, offset
+ 4*word
));
830 pr_cont("%s", (char *)data
);
832 printk("%s" "end of fw dump\n", lvl
);
835 static void bnx2x_fw_dump(struct bnx2x
*bp
)
837 bnx2x_fw_dump_lvl(bp
, KERN_ERR
);
840 static void bnx2x_hc_int_disable(struct bnx2x
*bp
)
842 int port
= BP_PORT(bp
);
843 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
844 u32 val
= REG_RD(bp
, addr
);
846 /* in E1 we must use only PCI configuration space to disable
847 * MSI/MSIX capability
848 * It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC block
850 if (CHIP_IS_E1(bp
)) {
851 /* Since IGU_PF_CONF_MSI_MSIX_EN still always on
852 * Use mask register to prevent from HC sending interrupts
853 * after we exit the function
855 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0);
857 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
858 HC_CONFIG_0_REG_INT_LINE_EN_0
|
859 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
861 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
862 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
863 HC_CONFIG_0_REG_INT_LINE_EN_0
|
864 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
867 "write %x to HC %d (addr 0x%x)\n",
870 /* flush all outstanding writes */
873 REG_WR(bp
, addr
, val
);
874 if (REG_RD(bp
, addr
) != val
)
875 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
878 static void bnx2x_igu_int_disable(struct bnx2x
*bp
)
880 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
882 val
&= ~(IGU_PF_CONF_MSI_MSIX_EN
|
883 IGU_PF_CONF_INT_LINE_EN
|
884 IGU_PF_CONF_ATTN_BIT_EN
);
886 DP(NETIF_MSG_IFDOWN
, "write %x to IGU\n", val
);
888 /* flush all outstanding writes */
891 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
892 if (REG_RD(bp
, IGU_REG_PF_CONFIGURATION
) != val
)
893 BNX2X_ERR("BUG! Proper val not read from IGU!\n");
896 static void bnx2x_int_disable(struct bnx2x
*bp
)
898 if (bp
->common
.int_block
== INT_BLOCK_HC
)
899 bnx2x_hc_int_disable(bp
);
901 bnx2x_igu_int_disable(bp
);
904 void bnx2x_panic_dump(struct bnx2x
*bp
, bool disable_int
)
908 struct hc_sp_status_block_data sp_sb_data
;
909 int func
= BP_FUNC(bp
);
910 #ifdef BNX2X_STOP_ON_ERROR
911 u16 start
= 0, end
= 0;
914 if (IS_PF(bp
) && disable_int
)
915 bnx2x_int_disable(bp
);
917 bp
->stats_state
= STATS_STATE_DISABLED
;
918 bp
->eth_stats
.unrecoverable_error
++;
919 DP(BNX2X_MSG_STATS
, "stats_state - DISABLED\n");
921 BNX2X_ERR("begin crash dump -----------------\n");
926 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
927 int data_size
, cstorm_offset
;
929 BNX2X_ERR("def_idx(0x%x) def_att_idx(0x%x) attn_state(0x%x) spq_prod_idx(0x%x) next_stats_cnt(0x%x)\n",
930 bp
->def_idx
, bp
->def_att_idx
, bp
->attn_state
,
931 bp
->spq_prod_idx
, bp
->stats_counter
);
932 BNX2X_ERR("DSB: attn bits(0x%x) ack(0x%x) id(0x%x) idx(0x%x)\n",
933 def_sb
->atten_status_block
.attn_bits
,
934 def_sb
->atten_status_block
.attn_bits_ack
,
935 def_sb
->atten_status_block
.status_block_id
,
936 def_sb
->atten_status_block
.attn_bits_index
);
938 for (i
= 0; i
< HC_SP_SB_MAX_INDICES
; i
++)
940 def_sb
->sp_sb
.index_values
[i
],
941 (i
== HC_SP_SB_MAX_INDICES
- 1) ? ") " : " ");
943 data_size
= sizeof(struct hc_sp_status_block_data
) /
945 cstorm_offset
= CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
);
946 for (i
= 0; i
< data_size
; i
++)
947 *((u32
*)&sp_sb_data
+ i
) =
948 REG_RD(bp
, BAR_CSTRORM_INTMEM
+ cstorm_offset
+
951 pr_cont("igu_sb_id(0x%x) igu_seg_id(0x%x) pf_id(0x%x) vnic_id(0x%x) vf_id(0x%x) vf_valid (0x%x) state(0x%x)\n",
952 sp_sb_data
.igu_sb_id
,
953 sp_sb_data
.igu_seg_id
,
954 sp_sb_data
.p_func
.pf_id
,
955 sp_sb_data
.p_func
.vnic_id
,
956 sp_sb_data
.p_func
.vf_id
,
957 sp_sb_data
.p_func
.vf_valid
,
961 for_each_eth_queue(bp
, i
) {
962 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
964 struct hc_status_block_data_e2 sb_data_e2
;
965 struct hc_status_block_data_e1x sb_data_e1x
;
966 struct hc_status_block_sm
*hc_sm_p
=
968 sb_data_e1x
.common
.state_machine
:
969 sb_data_e2
.common
.state_machine
;
970 struct hc_index_data
*hc_index_p
=
972 sb_data_e1x
.index_data
:
973 sb_data_e2
.index_data
;
976 struct bnx2x_fp_txdata txdata
;
985 BNX2X_ERR("fp%d: rx_bd_prod(0x%x) rx_bd_cons(0x%x) rx_comp_prod(0x%x) rx_comp_cons(0x%x) *rx_cons_sb(0x%x)\n",
986 i
, fp
->rx_bd_prod
, fp
->rx_bd_cons
,
988 fp
->rx_comp_cons
, le16_to_cpu(*fp
->rx_cons_sb
));
989 BNX2X_ERR(" rx_sge_prod(0x%x) last_max_sge(0x%x) fp_hc_idx(0x%x)\n",
990 fp
->rx_sge_prod
, fp
->last_max_sge
,
991 le16_to_cpu(fp
->fp_hc_idx
));
994 for_each_cos_in_tx_queue(fp
, cos
)
996 if (!fp
->txdata_ptr
[cos
])
999 txdata
= *fp
->txdata_ptr
[cos
];
1001 if (!txdata
.tx_cons_sb
)
1004 BNX2X_ERR("fp%d: tx_pkt_prod(0x%x) tx_pkt_cons(0x%x) tx_bd_prod(0x%x) tx_bd_cons(0x%x) *tx_cons_sb(0x%x)\n",
1005 i
, txdata
.tx_pkt_prod
,
1006 txdata
.tx_pkt_cons
, txdata
.tx_bd_prod
,
1008 le16_to_cpu(*txdata
.tx_cons_sb
));
1011 loop
= CHIP_IS_E1x(bp
) ?
1012 HC_SB_MAX_INDICES_E1X
: HC_SB_MAX_INDICES_E2
;
1019 BNX2X_ERR(" run indexes (");
1020 for (j
= 0; j
< HC_SB_MAX_SM
; j
++)
1022 fp
->sb_running_index
[j
],
1023 (j
== HC_SB_MAX_SM
- 1) ? ")" : " ");
1025 BNX2X_ERR(" indexes (");
1026 for (j
= 0; j
< loop
; j
++)
1028 fp
->sb_index_values
[j
],
1029 (j
== loop
- 1) ? ")" : " ");
1031 /* VF cannot access FW refelection for status block */
1036 data_size
= CHIP_IS_E1x(bp
) ?
1037 sizeof(struct hc_status_block_data_e1x
) :
1038 sizeof(struct hc_status_block_data_e2
);
1039 data_size
/= sizeof(u32
);
1040 sb_data_p
= CHIP_IS_E1x(bp
) ?
1041 (u32
*)&sb_data_e1x
:
1043 /* copy sb data in here */
1044 for (j
= 0; j
< data_size
; j
++)
1045 *(sb_data_p
+ j
) = REG_RD(bp
, BAR_CSTRORM_INTMEM
+
1046 CSTORM_STATUS_BLOCK_DATA_OFFSET(fp
->fw_sb_id
) +
1049 if (!CHIP_IS_E1x(bp
)) {
1050 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1051 sb_data_e2
.common
.p_func
.pf_id
,
1052 sb_data_e2
.common
.p_func
.vf_id
,
1053 sb_data_e2
.common
.p_func
.vf_valid
,
1054 sb_data_e2
.common
.p_func
.vnic_id
,
1055 sb_data_e2
.common
.same_igu_sb_1b
,
1056 sb_data_e2
.common
.state
);
1058 pr_cont("pf_id(0x%x) vf_id(0x%x) vf_valid(0x%x) vnic_id(0x%x) same_igu_sb_1b(0x%x) state(0x%x)\n",
1059 sb_data_e1x
.common
.p_func
.pf_id
,
1060 sb_data_e1x
.common
.p_func
.vf_id
,
1061 sb_data_e1x
.common
.p_func
.vf_valid
,
1062 sb_data_e1x
.common
.p_func
.vnic_id
,
1063 sb_data_e1x
.common
.same_igu_sb_1b
,
1064 sb_data_e1x
.common
.state
);
1068 for (j
= 0; j
< HC_SB_MAX_SM
; j
++) {
1069 pr_cont("SM[%d] __flags (0x%x) igu_sb_id (0x%x) igu_seg_id(0x%x) time_to_expire (0x%x) timer_value(0x%x)\n",
1070 j
, hc_sm_p
[j
].__flags
,
1071 hc_sm_p
[j
].igu_sb_id
,
1072 hc_sm_p
[j
].igu_seg_id
,
1073 hc_sm_p
[j
].time_to_expire
,
1074 hc_sm_p
[j
].timer_value
);
1078 for (j
= 0; j
< loop
; j
++) {
1079 pr_cont("INDEX[%d] flags (0x%x) timeout (0x%x)\n", j
,
1080 hc_index_p
[j
].flags
,
1081 hc_index_p
[j
].timeout
);
1085 #ifdef BNX2X_STOP_ON_ERROR
1088 BNX2X_ERR("eq cons %x prod %x\n", bp
->eq_cons
, bp
->eq_prod
);
1089 for (i
= 0; i
< NUM_EQ_DESC
; i
++) {
1090 u32
*data
= (u32
*)&bp
->eq_ring
[i
].message
.data
;
1092 BNX2X_ERR("event queue [%d]: header: opcode %d, error %d\n",
1093 i
, bp
->eq_ring
[i
].message
.opcode
,
1094 bp
->eq_ring
[i
].message
.error
);
1095 BNX2X_ERR("data: %x %x %x\n",
1096 data
[0], data
[1], data
[2]);
1102 for_each_valid_rx_queue(bp
, i
) {
1103 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1108 if (!fp
->rx_cons_sb
)
1111 start
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) - 10);
1112 end
= RX_BD(le16_to_cpu(*fp
->rx_cons_sb
) + 503);
1113 for (j
= start
; j
!= end
; j
= RX_BD(j
+ 1)) {
1114 u32
*rx_bd
= (u32
*)&fp
->rx_desc_ring
[j
];
1115 struct sw_rx_bd
*sw_bd
= &fp
->rx_buf_ring
[j
];
1117 BNX2X_ERR("fp%d: rx_bd[%x]=[%x:%x] sw_bd=[%p]\n",
1118 i
, j
, rx_bd
[1], rx_bd
[0], sw_bd
->data
);
1121 start
= RX_SGE(fp
->rx_sge_prod
);
1122 end
= RX_SGE(fp
->last_max_sge
);
1123 for (j
= start
; j
!= end
; j
= RX_SGE(j
+ 1)) {
1124 u32
*rx_sge
= (u32
*)&fp
->rx_sge_ring
[j
];
1125 struct sw_rx_page
*sw_page
= &fp
->rx_page_ring
[j
];
1127 BNX2X_ERR("fp%d: rx_sge[%x]=[%x:%x] sw_page=[%p]\n",
1128 i
, j
, rx_sge
[1], rx_sge
[0], sw_page
->page
);
1131 start
= RCQ_BD(fp
->rx_comp_cons
- 10);
1132 end
= RCQ_BD(fp
->rx_comp_cons
+ 503);
1133 for (j
= start
; j
!= end
; j
= RCQ_BD(j
+ 1)) {
1134 u32
*cqe
= (u32
*)&fp
->rx_comp_ring
[j
];
1136 BNX2X_ERR("fp%d: cqe[%x]=[%x:%x:%x:%x]\n",
1137 i
, j
, cqe
[0], cqe
[1], cqe
[2], cqe
[3]);
1142 for_each_valid_tx_queue(bp
, i
) {
1143 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1148 for_each_cos_in_tx_queue(fp
, cos
) {
1149 struct bnx2x_fp_txdata
*txdata
= fp
->txdata_ptr
[cos
];
1151 if (!fp
->txdata_ptr
[cos
])
1154 if (!txdata
->tx_cons_sb
)
1157 start
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) - 10);
1158 end
= TX_BD(le16_to_cpu(*txdata
->tx_cons_sb
) + 245);
1159 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1160 struct sw_tx_bd
*sw_bd
=
1161 &txdata
->tx_buf_ring
[j
];
1163 BNX2X_ERR("fp%d: txdata %d, packet[%x]=[%p,%x]\n",
1164 i
, cos
, j
, sw_bd
->skb
,
1168 start
= TX_BD(txdata
->tx_bd_cons
- 10);
1169 end
= TX_BD(txdata
->tx_bd_cons
+ 254);
1170 for (j
= start
; j
!= end
; j
= TX_BD(j
+ 1)) {
1171 u32
*tx_bd
= (u32
*)&txdata
->tx_desc_ring
[j
];
1173 BNX2X_ERR("fp%d: txdata %d, tx_bd[%x]=[%x:%x:%x:%x]\n",
1174 i
, cos
, j
, tx_bd
[0], tx_bd
[1],
1175 tx_bd
[2], tx_bd
[3]);
1182 bnx2x_mc_assert(bp
);
1184 BNX2X_ERR("end crash dump -----------------\n");
1188 * FLR Support for E2
1190 * bnx2x_pf_flr_clnup() is called during nic_load in the per function HW
1193 #define FLR_WAIT_USEC 10000 /* 10 milliseconds */
1194 #define FLR_WAIT_INTERVAL 50 /* usec */
1195 #define FLR_POLL_CNT (FLR_WAIT_USEC/FLR_WAIT_INTERVAL) /* 200 */
1197 struct pbf_pN_buf_regs
{
1204 struct pbf_pN_cmd_regs
{
1210 static void bnx2x_pbf_pN_buf_flushed(struct bnx2x
*bp
,
1211 struct pbf_pN_buf_regs
*regs
,
1214 u32 init_crd
, crd
, crd_start
, crd_freed
, crd_freed_start
;
1215 u32 cur_cnt
= poll_count
;
1217 crd_freed
= crd_freed_start
= REG_RD(bp
, regs
->crd_freed
);
1218 crd
= crd_start
= REG_RD(bp
, regs
->crd
);
1219 init_crd
= REG_RD(bp
, regs
->init_crd
);
1221 DP(BNX2X_MSG_SP
, "INIT CREDIT[%d] : %x\n", regs
->pN
, init_crd
);
1222 DP(BNX2X_MSG_SP
, "CREDIT[%d] : s:%x\n", regs
->pN
, crd
);
1223 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: s:%x\n", regs
->pN
, crd_freed
);
1225 while ((crd
!= init_crd
) && ((u32
)SUB_S32(crd_freed
, crd_freed_start
) <
1226 (init_crd
- crd_start
))) {
1228 udelay(FLR_WAIT_INTERVAL
);
1229 crd
= REG_RD(bp
, regs
->crd
);
1230 crd_freed
= REG_RD(bp
, regs
->crd_freed
);
1232 DP(BNX2X_MSG_SP
, "PBF tx buffer[%d] timed out\n",
1234 DP(BNX2X_MSG_SP
, "CREDIT[%d] : c:%x\n",
1236 DP(BNX2X_MSG_SP
, "CREDIT_FREED[%d]: c:%x\n",
1237 regs
->pN
, crd_freed
);
1241 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF tx buffer[%d]\n",
1242 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1245 static void bnx2x_pbf_pN_cmd_flushed(struct bnx2x
*bp
,
1246 struct pbf_pN_cmd_regs
*regs
,
1249 u32 occup
, to_free
, freed
, freed_start
;
1250 u32 cur_cnt
= poll_count
;
1252 occup
= to_free
= REG_RD(bp
, regs
->lines_occup
);
1253 freed
= freed_start
= REG_RD(bp
, regs
->lines_freed
);
1255 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n", regs
->pN
, occup
);
1256 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n", regs
->pN
, freed
);
1258 while (occup
&& ((u32
)SUB_S32(freed
, freed_start
) < to_free
)) {
1260 udelay(FLR_WAIT_INTERVAL
);
1261 occup
= REG_RD(bp
, regs
->lines_occup
);
1262 freed
= REG_RD(bp
, regs
->lines_freed
);
1264 DP(BNX2X_MSG_SP
, "PBF cmd queue[%d] timed out\n",
1266 DP(BNX2X_MSG_SP
, "OCCUPANCY[%d] : s:%x\n",
1268 DP(BNX2X_MSG_SP
, "LINES_FREED[%d] : s:%x\n",
1273 DP(BNX2X_MSG_SP
, "Waited %d*%d usec for PBF cmd queue[%d]\n",
1274 poll_count
-cur_cnt
, FLR_WAIT_INTERVAL
, regs
->pN
);
1277 static u32
bnx2x_flr_clnup_reg_poll(struct bnx2x
*bp
, u32 reg
,
1278 u32 expected
, u32 poll_count
)
1280 u32 cur_cnt
= poll_count
;
1283 while ((val
= REG_RD(bp
, reg
)) != expected
&& cur_cnt
--)
1284 udelay(FLR_WAIT_INTERVAL
);
1289 int bnx2x_flr_clnup_poll_hw_counter(struct bnx2x
*bp
, u32 reg
,
1290 char *msg
, u32 poll_cnt
)
1292 u32 val
= bnx2x_flr_clnup_reg_poll(bp
, reg
, 0, poll_cnt
);
1294 BNX2X_ERR("%s usage count=%d\n", msg
, val
);
1300 /* Common routines with VF FLR cleanup */
1301 u32
bnx2x_flr_clnup_poll_count(struct bnx2x
*bp
)
1303 /* adjust polling timeout */
1304 if (CHIP_REV_IS_EMUL(bp
))
1305 return FLR_POLL_CNT
* 2000;
1307 if (CHIP_REV_IS_FPGA(bp
))
1308 return FLR_POLL_CNT
* 120;
1310 return FLR_POLL_CNT
;
1313 void bnx2x_tx_hw_flushed(struct bnx2x
*bp
, u32 poll_count
)
1315 struct pbf_pN_cmd_regs cmd_regs
[] = {
1316 {0, (CHIP_IS_E3B0(bp
)) ?
1317 PBF_REG_TQ_OCCUPANCY_Q0
:
1318 PBF_REG_P0_TQ_OCCUPANCY
,
1319 (CHIP_IS_E3B0(bp
)) ?
1320 PBF_REG_TQ_LINES_FREED_CNT_Q0
:
1321 PBF_REG_P0_TQ_LINES_FREED_CNT
},
1322 {1, (CHIP_IS_E3B0(bp
)) ?
1323 PBF_REG_TQ_OCCUPANCY_Q1
:
1324 PBF_REG_P1_TQ_OCCUPANCY
,
1325 (CHIP_IS_E3B0(bp
)) ?
1326 PBF_REG_TQ_LINES_FREED_CNT_Q1
:
1327 PBF_REG_P1_TQ_LINES_FREED_CNT
},
1328 {4, (CHIP_IS_E3B0(bp
)) ?
1329 PBF_REG_TQ_OCCUPANCY_LB_Q
:
1330 PBF_REG_P4_TQ_OCCUPANCY
,
1331 (CHIP_IS_E3B0(bp
)) ?
1332 PBF_REG_TQ_LINES_FREED_CNT_LB_Q
:
1333 PBF_REG_P4_TQ_LINES_FREED_CNT
}
1336 struct pbf_pN_buf_regs buf_regs
[] = {
1337 {0, (CHIP_IS_E3B0(bp
)) ?
1338 PBF_REG_INIT_CRD_Q0
:
1339 PBF_REG_P0_INIT_CRD
,
1340 (CHIP_IS_E3B0(bp
)) ?
1343 (CHIP_IS_E3B0(bp
)) ?
1344 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0
:
1345 PBF_REG_P0_INTERNAL_CRD_FREED_CNT
},
1346 {1, (CHIP_IS_E3B0(bp
)) ?
1347 PBF_REG_INIT_CRD_Q1
:
1348 PBF_REG_P1_INIT_CRD
,
1349 (CHIP_IS_E3B0(bp
)) ?
1352 (CHIP_IS_E3B0(bp
)) ?
1353 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1
:
1354 PBF_REG_P1_INTERNAL_CRD_FREED_CNT
},
1355 {4, (CHIP_IS_E3B0(bp
)) ?
1356 PBF_REG_INIT_CRD_LB_Q
:
1357 PBF_REG_P4_INIT_CRD
,
1358 (CHIP_IS_E3B0(bp
)) ?
1359 PBF_REG_CREDIT_LB_Q
:
1361 (CHIP_IS_E3B0(bp
)) ?
1362 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q
:
1363 PBF_REG_P4_INTERNAL_CRD_FREED_CNT
},
1368 /* Verify the command queues are flushed P0, P1, P4 */
1369 for (i
= 0; i
< ARRAY_SIZE(cmd_regs
); i
++)
1370 bnx2x_pbf_pN_cmd_flushed(bp
, &cmd_regs
[i
], poll_count
);
1372 /* Verify the transmission buffers are flushed P0, P1, P4 */
1373 for (i
= 0; i
< ARRAY_SIZE(buf_regs
); i
++)
1374 bnx2x_pbf_pN_buf_flushed(bp
, &buf_regs
[i
], poll_count
);
1377 #define OP_GEN_PARAM(param) \
1378 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM)
1380 #define OP_GEN_TYPE(type) \
1381 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE)
1383 #define OP_GEN_AGG_VECT(index) \
1384 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX)
1386 int bnx2x_send_final_clnup(struct bnx2x
*bp
, u8 clnup_func
, u32 poll_cnt
)
1388 u32 op_gen_command
= 0;
1389 u32 comp_addr
= BAR_CSTRORM_INTMEM
+
1390 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func
);
1393 if (REG_RD(bp
, comp_addr
)) {
1394 BNX2X_ERR("Cleanup complete was not 0 before sending\n");
1398 op_gen_command
|= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX
);
1399 op_gen_command
|= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE
);
1400 op_gen_command
|= OP_GEN_AGG_VECT(clnup_func
);
1401 op_gen_command
|= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT
;
1403 DP(BNX2X_MSG_SP
, "sending FW Final cleanup\n");
1404 REG_WR(bp
, XSDM_REG_OPERATION_GEN
, op_gen_command
);
1406 if (bnx2x_flr_clnup_reg_poll(bp
, comp_addr
, 1, poll_cnt
) != 1) {
1407 BNX2X_ERR("FW final cleanup did not succeed\n");
1408 DP(BNX2X_MSG_SP
, "At timeout completion address contained %x\n",
1409 (REG_RD(bp
, comp_addr
)));
1413 /* Zero completion for next FLR */
1414 REG_WR(bp
, comp_addr
, 0);
1419 u8
bnx2x_is_pcie_pending(struct pci_dev
*dev
)
1423 pcie_capability_read_word(dev
, PCI_EXP_DEVSTA
, &status
);
1424 return status
& PCI_EXP_DEVSTA_TRPND
;
1427 /* PF FLR specific routines
1429 static int bnx2x_poll_hw_usage_counters(struct bnx2x
*bp
, u32 poll_cnt
)
1431 /* wait for CFC PF usage-counter to zero (includes all the VFs) */
1432 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1433 CFC_REG_NUM_LCIDS_INSIDE_PF
,
1434 "CFC PF usage counter timed out",
1438 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */
1439 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1440 DORQ_REG_PF_USAGE_CNT
,
1441 "DQ PF usage counter timed out",
1445 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */
1446 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1447 QM_REG_PF_USG_CNT_0
+ 4*BP_FUNC(bp
),
1448 "QM PF usage counter timed out",
1452 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */
1453 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1454 TM_REG_LIN0_VNIC_UC
+ 4*BP_PORT(bp
),
1455 "Timers VNIC usage counter timed out",
1458 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1459 TM_REG_LIN0_NUM_SCANS
+ 4*BP_PORT(bp
),
1460 "Timers NUM_SCANS usage counter timed out",
1464 /* Wait DMAE PF usage counter to zero */
1465 if (bnx2x_flr_clnup_poll_hw_counter(bp
,
1466 dmae_reg_go_c
[INIT_DMAE_C(bp
)],
1467 "DMAE command register timed out",
1474 static void bnx2x_hw_enable_status(struct bnx2x
*bp
)
1478 val
= REG_RD(bp
, CFC_REG_WEAK_ENABLE_PF
);
1479 DP(BNX2X_MSG_SP
, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val
);
1481 val
= REG_RD(bp
, PBF_REG_DISABLE_PF
);
1482 DP(BNX2X_MSG_SP
, "PBF_REG_DISABLE_PF is 0x%x\n", val
);
1484 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSI_EN
);
1485 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val
);
1487 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_EN
);
1488 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val
);
1490 val
= REG_RD(bp
, IGU_REG_PCI_PF_MSIX_FUNC_MASK
);
1491 DP(BNX2X_MSG_SP
, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val
);
1493 val
= REG_RD(bp
, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR
);
1494 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val
);
1496 val
= REG_RD(bp
, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR
);
1497 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val
);
1499 val
= REG_RD(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
);
1500 DP(BNX2X_MSG_SP
, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n",
1504 static int bnx2x_pf_flr_clnup(struct bnx2x
*bp
)
1506 u32 poll_cnt
= bnx2x_flr_clnup_poll_count(bp
);
1508 DP(BNX2X_MSG_SP
, "Cleanup after FLR PF[%d]\n", BP_ABS_FUNC(bp
));
1510 /* Re-enable PF target read access */
1511 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
1513 /* Poll HW usage counters */
1514 DP(BNX2X_MSG_SP
, "Polling usage counters\n");
1515 if (bnx2x_poll_hw_usage_counters(bp
, poll_cnt
))
1518 /* Zero the igu 'trailing edge' and 'leading edge' */
1520 /* Send the FW cleanup command */
1521 if (bnx2x_send_final_clnup(bp
, (u8
)BP_FUNC(bp
), poll_cnt
))
1526 /* Verify TX hw is flushed */
1527 bnx2x_tx_hw_flushed(bp
, poll_cnt
);
1529 /* Wait 100ms (not adjusted according to platform) */
1532 /* Verify no pending pci transactions */
1533 if (bnx2x_is_pcie_pending(bp
->pdev
))
1534 BNX2X_ERR("PCIE Transactions still pending\n");
1537 bnx2x_hw_enable_status(bp
);
1540 * Master enable - Due to WB DMAE writes performed before this
1541 * register is re-initialized as part of the regular function init
1543 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
1548 static void bnx2x_hc_int_enable(struct bnx2x
*bp
)
1550 int port
= BP_PORT(bp
);
1551 u32 addr
= port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
;
1552 u32 val
= REG_RD(bp
, addr
);
1553 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1554 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1555 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1558 val
&= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1559 HC_CONFIG_0_REG_INT_LINE_EN_0
);
1560 val
|= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1561 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1563 val
|= HC_CONFIG_0_REG_SINGLE_ISR_EN_0
;
1565 val
&= ~HC_CONFIG_0_REG_INT_LINE_EN_0
;
1566 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1567 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1568 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1570 val
|= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0
|
1571 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
|
1572 HC_CONFIG_0_REG_INT_LINE_EN_0
|
1573 HC_CONFIG_0_REG_ATTN_BIT_EN_0
);
1575 if (!CHIP_IS_E1(bp
)) {
1577 "write %x to HC %d (addr 0x%x)\n", val
, port
, addr
);
1579 REG_WR(bp
, addr
, val
);
1581 val
&= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0
;
1586 REG_WR(bp
, HC_REG_INT_MASK
+ port
*4, 0x1FFFF);
1589 "write %x to HC %d (addr 0x%x) mode %s\n", val
, port
, addr
,
1590 (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1592 REG_WR(bp
, addr
, val
);
1594 * Ensure that HC_CONFIG is written before leading/trailing edge config
1599 if (!CHIP_IS_E1(bp
)) {
1600 /* init leading/trailing edge */
1602 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1604 /* enable nig and gpio3 attention */
1609 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
1610 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
1613 /* Make sure that interrupts are indeed enabled from here on */
1617 static void bnx2x_igu_int_enable(struct bnx2x
*bp
)
1620 bool msix
= (bp
->flags
& USING_MSIX_FLAG
) ? true : false;
1621 bool single_msix
= (bp
->flags
& USING_SINGLE_MSIX_FLAG
) ? true : false;
1622 bool msi
= (bp
->flags
& USING_MSI_FLAG
) ? true : false;
1624 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
1627 val
&= ~(IGU_PF_CONF_INT_LINE_EN
|
1628 IGU_PF_CONF_SINGLE_ISR_EN
);
1629 val
|= (IGU_PF_CONF_MSI_MSIX_EN
|
1630 IGU_PF_CONF_ATTN_BIT_EN
);
1633 val
|= IGU_PF_CONF_SINGLE_ISR_EN
;
1635 val
&= ~IGU_PF_CONF_INT_LINE_EN
;
1636 val
|= (IGU_PF_CONF_MSI_MSIX_EN
|
1637 IGU_PF_CONF_ATTN_BIT_EN
|
1638 IGU_PF_CONF_SINGLE_ISR_EN
);
1640 val
&= ~IGU_PF_CONF_MSI_MSIX_EN
;
1641 val
|= (IGU_PF_CONF_INT_LINE_EN
|
1642 IGU_PF_CONF_ATTN_BIT_EN
|
1643 IGU_PF_CONF_SINGLE_ISR_EN
);
1646 /* Clean previous status - need to configure igu prior to ack*/
1647 if ((!msix
) || single_msix
) {
1648 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1652 val
|= IGU_PF_CONF_FUNC_EN
;
1654 DP(NETIF_MSG_IFUP
, "write 0x%x to IGU mode %s\n",
1655 val
, (msix
? "MSI-X" : (msi
? "MSI" : "INTx")));
1657 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
1659 if (val
& IGU_PF_CONF_INT_LINE_EN
)
1660 pci_intx(bp
->pdev
, true);
1664 /* init leading/trailing edge */
1666 val
= (0xee0f | (1 << (BP_VN(bp
) + 4)));
1668 /* enable nig and gpio3 attention */
1673 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
1674 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
1676 /* Make sure that interrupts are indeed enabled from here on */
1680 void bnx2x_int_enable(struct bnx2x
*bp
)
1682 if (bp
->common
.int_block
== INT_BLOCK_HC
)
1683 bnx2x_hc_int_enable(bp
);
1685 bnx2x_igu_int_enable(bp
);
1688 void bnx2x_int_disable_sync(struct bnx2x
*bp
, int disable_hw
)
1690 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
1694 /* prevent the HW from sending interrupts */
1695 bnx2x_int_disable(bp
);
1697 /* make sure all ISRs are done */
1699 synchronize_irq(bp
->msix_table
[0].vector
);
1701 if (CNIC_SUPPORT(bp
))
1703 for_each_eth_queue(bp
, i
)
1704 synchronize_irq(bp
->msix_table
[offset
++].vector
);
1706 synchronize_irq(bp
->pdev
->irq
);
1708 /* make sure sp_task is not running */
1709 cancel_delayed_work(&bp
->sp_task
);
1710 cancel_delayed_work(&bp
->period_task
);
1711 flush_workqueue(bnx2x_wq
);
1717 * General service functions
1720 /* Return true if succeeded to acquire the lock */
1721 static bool bnx2x_trylock_hw_lock(struct bnx2x
*bp
, u32 resource
)
1724 u32 resource_bit
= (1 << resource
);
1725 int func
= BP_FUNC(bp
);
1726 u32 hw_lock_control_reg
;
1728 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1729 "Trying to take a lock on resource %d\n", resource
);
1731 /* Validating that the resource is within range */
1732 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1733 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1734 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1735 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
1740 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
1742 hw_lock_control_reg
=
1743 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
1745 /* Try to acquire the lock */
1746 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
1747 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
1748 if (lock_status
& resource_bit
)
1751 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
,
1752 "Failed to get a lock on resource %d\n", resource
);
1757 * bnx2x_get_leader_lock_resource - get the recovery leader resource id
1759 * @bp: driver handle
1761 * Returns the recovery leader resource id according to the engine this function
1762 * belongs to. Currently only only 2 engines is supported.
1764 static int bnx2x_get_leader_lock_resource(struct bnx2x
*bp
)
1767 return HW_LOCK_RESOURCE_RECOVERY_LEADER_1
;
1769 return HW_LOCK_RESOURCE_RECOVERY_LEADER_0
;
1773 * bnx2x_trylock_leader_lock- try to acquire a leader lock.
1775 * @bp: driver handle
1777 * Tries to acquire a leader lock for current engine.
1779 static bool bnx2x_trylock_leader_lock(struct bnx2x
*bp
)
1781 return bnx2x_trylock_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
1784 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
);
1786 /* schedule the sp task and mark that interrupt occurred (runs from ISR) */
1787 static int bnx2x_schedule_sp_task(struct bnx2x
*bp
)
1789 /* Set the interrupt occurred bit for the sp-task to recognize it
1790 * must ack the interrupt and transition according to the IGU
1793 atomic_set(&bp
->interrupt_occurred
, 1);
1795 /* The sp_task must execute only after this bit
1796 * is set, otherwise we will get out of sync and miss all
1797 * further interrupts. Hence, the barrier.
1801 /* schedule sp_task to workqueue */
1802 return queue_delayed_work(bnx2x_wq
, &bp
->sp_task
, 0);
1805 void bnx2x_sp_event(struct bnx2x_fastpath
*fp
, union eth_rx_cqe
*rr_cqe
)
1807 struct bnx2x
*bp
= fp
->bp
;
1808 int cid
= SW_CID(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1809 int command
= CQE_CMD(rr_cqe
->ramrod_cqe
.conn_and_cmd_data
);
1810 enum bnx2x_queue_cmd drv_cmd
= BNX2X_Q_CMD_MAX
;
1811 struct bnx2x_queue_sp_obj
*q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
1814 "fp %d cid %d got ramrod #%d state is %x type is %d\n",
1815 fp
->index
, cid
, command
, bp
->state
,
1816 rr_cqe
->ramrod_cqe
.ramrod_type
);
1818 /* If cid is within VF range, replace the slowpath object with the
1819 * one corresponding to this VF
1821 if (cid
>= BNX2X_FIRST_VF_CID
&&
1822 cid
< BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)
1823 bnx2x_iov_set_queue_sp_obj(bp
, cid
, &q_obj
);
1826 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE
):
1827 DP(BNX2X_MSG_SP
, "got UPDATE ramrod. CID %d\n", cid
);
1828 drv_cmd
= BNX2X_Q_CMD_UPDATE
;
1831 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP
):
1832 DP(BNX2X_MSG_SP
, "got MULTI[%d] setup ramrod\n", cid
);
1833 drv_cmd
= BNX2X_Q_CMD_SETUP
;
1836 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP
):
1837 DP(BNX2X_MSG_SP
, "got MULTI[%d] tx-only setup ramrod\n", cid
);
1838 drv_cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
1841 case (RAMROD_CMD_ID_ETH_HALT
):
1842 DP(BNX2X_MSG_SP
, "got MULTI[%d] halt ramrod\n", cid
);
1843 drv_cmd
= BNX2X_Q_CMD_HALT
;
1846 case (RAMROD_CMD_ID_ETH_TERMINATE
):
1847 DP(BNX2X_MSG_SP
, "got MULTI[%d] terminate ramrod\n", cid
);
1848 drv_cmd
= BNX2X_Q_CMD_TERMINATE
;
1851 case (RAMROD_CMD_ID_ETH_EMPTY
):
1852 DP(BNX2X_MSG_SP
, "got MULTI[%d] empty ramrod\n", cid
);
1853 drv_cmd
= BNX2X_Q_CMD_EMPTY
;
1856 case (RAMROD_CMD_ID_ETH_TPA_UPDATE
):
1857 DP(BNX2X_MSG_SP
, "got tpa update ramrod CID=%d\n", cid
);
1858 drv_cmd
= BNX2X_Q_CMD_UPDATE_TPA
;
1862 BNX2X_ERR("unexpected MC reply (%d) on fp[%d]\n",
1863 command
, fp
->index
);
1867 if ((drv_cmd
!= BNX2X_Q_CMD_MAX
) &&
1868 q_obj
->complete_cmd(bp
, q_obj
, drv_cmd
))
1869 /* q_obj->complete_cmd() failure means that this was
1870 * an unexpected completion.
1872 * In this case we don't want to increase the bp->spq_left
1873 * because apparently we haven't sent this command the first
1876 #ifdef BNX2X_STOP_ON_ERROR
1882 smp_mb__before_atomic();
1883 atomic_inc(&bp
->cq_spq_left
);
1884 /* push the change in bp->spq_left and towards the memory */
1885 smp_mb__after_atomic();
1887 DP(BNX2X_MSG_SP
, "bp->cq_spq_left %x\n", atomic_read(&bp
->cq_spq_left
));
1889 if ((drv_cmd
== BNX2X_Q_CMD_UPDATE
) && (IS_FCOE_FP(fp
)) &&
1890 (!!test_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
))) {
1891 /* if Q update ramrod is completed for last Q in AFEX vif set
1892 * flow, then ACK MCP at the end
1894 * mark pending ACK to MCP bit.
1895 * prevent case that both bits are cleared.
1896 * At the end of load/unload driver checks that
1897 * sp_state is cleared, and this order prevents
1900 smp_mb__before_atomic();
1901 set_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
, &bp
->sp_state
);
1903 clear_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
1904 smp_mb__after_atomic();
1906 /* schedule the sp task as mcp ack is required */
1907 bnx2x_schedule_sp_task(bp
);
1913 irqreturn_t
bnx2x_interrupt(int irq
, void *dev_instance
)
1915 struct bnx2x
*bp
= netdev_priv(dev_instance
);
1916 u16 status
= bnx2x_ack_int(bp
);
1921 /* Return here if interrupt is shared and it's not for us */
1922 if (unlikely(status
== 0)) {
1923 DP(NETIF_MSG_INTR
, "not our interrupt!\n");
1926 DP(NETIF_MSG_INTR
, "got an interrupt status 0x%x\n", status
);
1928 #ifdef BNX2X_STOP_ON_ERROR
1929 if (unlikely(bp
->panic
))
1933 for_each_eth_queue(bp
, i
) {
1934 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
1936 mask
= 0x2 << (fp
->index
+ CNIC_SUPPORT(bp
));
1937 if (status
& mask
) {
1938 /* Handle Rx or Tx according to SB id */
1939 for_each_cos_in_tx_queue(fp
, cos
)
1940 prefetch(fp
->txdata_ptr
[cos
]->tx_cons_sb
);
1941 prefetch(&fp
->sb_running_index
[SM_RX_ID
]);
1942 napi_schedule_irqoff(&bnx2x_fp(bp
, fp
->index
, napi
));
1947 if (CNIC_SUPPORT(bp
)) {
1949 if (status
& (mask
| 0x1)) {
1950 struct cnic_ops
*c_ops
= NULL
;
1953 c_ops
= rcu_dereference(bp
->cnic_ops
);
1954 if (c_ops
&& (bp
->cnic_eth_dev
.drv_state
&
1955 CNIC_DRV_STATE_HANDLES_IRQ
))
1956 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
1963 if (unlikely(status
& 0x1)) {
1965 /* schedule sp task to perform default status block work, ack
1966 * attentions and enable interrupts.
1968 bnx2x_schedule_sp_task(bp
);
1975 if (unlikely(status
))
1976 DP(NETIF_MSG_INTR
, "got an unknown interrupt! (status 0x%x)\n",
1985 * General service functions
1988 int bnx2x_acquire_hw_lock(struct bnx2x
*bp
, u32 resource
)
1991 u32 resource_bit
= (1 << resource
);
1992 int func
= BP_FUNC(bp
);
1993 u32 hw_lock_control_reg
;
1996 /* Validating that the resource is within range */
1997 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
1998 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
1999 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
2004 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
2006 hw_lock_control_reg
=
2007 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
2010 /* Validating that the resource is not already taken */
2011 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
2012 if (lock_status
& resource_bit
) {
2013 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x\n",
2014 lock_status
, resource_bit
);
2018 /* Try for 5 second every 5ms */
2019 for (cnt
= 0; cnt
< 1000; cnt
++) {
2020 /* Try to acquire the lock */
2021 REG_WR(bp
, hw_lock_control_reg
+ 4, resource_bit
);
2022 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
2023 if (lock_status
& resource_bit
)
2026 usleep_range(5000, 10000);
2028 BNX2X_ERR("Timeout\n");
2032 int bnx2x_release_leader_lock(struct bnx2x
*bp
)
2034 return bnx2x_release_hw_lock(bp
, bnx2x_get_leader_lock_resource(bp
));
2037 int bnx2x_release_hw_lock(struct bnx2x
*bp
, u32 resource
)
2040 u32 resource_bit
= (1 << resource
);
2041 int func
= BP_FUNC(bp
);
2042 u32 hw_lock_control_reg
;
2044 /* Validating that the resource is within range */
2045 if (resource
> HW_LOCK_MAX_RESOURCE_VALUE
) {
2046 BNX2X_ERR("resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n",
2047 resource
, HW_LOCK_MAX_RESOURCE_VALUE
);
2052 hw_lock_control_reg
= (MISC_REG_DRIVER_CONTROL_1
+ func
*8);
2054 hw_lock_control_reg
=
2055 (MISC_REG_DRIVER_CONTROL_7
+ (func
- 6)*8);
2058 /* Validating that the resource is currently taken */
2059 lock_status
= REG_RD(bp
, hw_lock_control_reg
);
2060 if (!(lock_status
& resource_bit
)) {
2061 BNX2X_ERR("lock_status 0x%x resource_bit 0x%x. Unlock was called but lock wasn't taken!\n",
2062 lock_status
, resource_bit
);
2066 REG_WR(bp
, hw_lock_control_reg
, resource_bit
);
2070 int bnx2x_get_gpio(struct bnx2x
*bp
, int gpio_num
, u8 port
)
2072 /* The GPIO should be swapped if swap register is set and active */
2073 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2074 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2075 int gpio_shift
= gpio_num
+
2076 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2077 u32 gpio_mask
= (1 << gpio_shift
);
2081 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2082 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2086 /* read GPIO value */
2087 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2089 /* get the requested pin value */
2090 if ((gpio_reg
& gpio_mask
) == gpio_mask
)
2098 int bnx2x_set_gpio(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2100 /* The GPIO should be swapped if swap register is set and active */
2101 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2102 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2103 int gpio_shift
= gpio_num
+
2104 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2105 u32 gpio_mask
= (1 << gpio_shift
);
2108 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2109 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2113 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2114 /* read GPIO and mask except the float bits */
2115 gpio_reg
= (REG_RD(bp
, MISC_REG_GPIO
) & MISC_REGISTERS_GPIO_FLOAT
);
2118 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2120 "Set GPIO %d (shift %d) -> output low\n",
2121 gpio_num
, gpio_shift
);
2122 /* clear FLOAT and set CLR */
2123 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2124 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_CLR_POS
);
2127 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2129 "Set GPIO %d (shift %d) -> output high\n",
2130 gpio_num
, gpio_shift
);
2131 /* clear FLOAT and set SET */
2132 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2133 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_SET_POS
);
2136 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2138 "Set GPIO %d (shift %d) -> input\n",
2139 gpio_num
, gpio_shift
);
2141 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2148 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2149 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2154 int bnx2x_set_mult_gpio(struct bnx2x
*bp
, u8 pins
, u32 mode
)
2159 /* Any port swapping should be handled by caller. */
2161 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2162 /* read GPIO and mask except the float bits */
2163 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO
);
2164 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2165 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2166 gpio_reg
&= ~(pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2169 case MISC_REGISTERS_GPIO_OUTPUT_LOW
:
2170 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output low\n", pins
);
2172 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_CLR_POS
);
2175 case MISC_REGISTERS_GPIO_OUTPUT_HIGH
:
2176 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> output high\n", pins
);
2178 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_SET_POS
);
2181 case MISC_REGISTERS_GPIO_INPUT_HI_Z
:
2182 DP(NETIF_MSG_LINK
, "Set GPIO 0x%x -> input\n", pins
);
2184 gpio_reg
|= (pins
<< MISC_REGISTERS_GPIO_FLOAT_POS
);
2188 BNX2X_ERR("Invalid GPIO mode assignment %d\n", mode
);
2194 REG_WR(bp
, MISC_REG_GPIO
, gpio_reg
);
2196 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2201 int bnx2x_set_gpio_int(struct bnx2x
*bp
, int gpio_num
, u32 mode
, u8 port
)
2203 /* The GPIO should be swapped if swap register is set and active */
2204 int gpio_port
= (REG_RD(bp
, NIG_REG_PORT_SWAP
) &&
2205 REG_RD(bp
, NIG_REG_STRAP_OVERRIDE
)) ^ port
;
2206 int gpio_shift
= gpio_num
+
2207 (gpio_port
? MISC_REGISTERS_GPIO_PORT_SHIFT
: 0);
2208 u32 gpio_mask
= (1 << gpio_shift
);
2211 if (gpio_num
> MISC_REGISTERS_GPIO_3
) {
2212 BNX2X_ERR("Invalid GPIO %d\n", gpio_num
);
2216 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2218 gpio_reg
= REG_RD(bp
, MISC_REG_GPIO_INT
);
2221 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR
:
2223 "Clear GPIO INT %d (shift %d) -> output low\n",
2224 gpio_num
, gpio_shift
);
2225 /* clear SET and set CLR */
2226 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2227 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2230 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET
:
2232 "Set GPIO INT %d (shift %d) -> output high\n",
2233 gpio_num
, gpio_shift
);
2234 /* clear CLR and set SET */
2235 gpio_reg
&= ~(gpio_mask
<< MISC_REGISTERS_GPIO_INT_CLR_POS
);
2236 gpio_reg
|= (gpio_mask
<< MISC_REGISTERS_GPIO_INT_SET_POS
);
2243 REG_WR(bp
, MISC_REG_GPIO_INT
, gpio_reg
);
2244 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_GPIO
);
2249 static int bnx2x_set_spio(struct bnx2x
*bp
, int spio
, u32 mode
)
2253 /* Only 2 SPIOs are configurable */
2254 if ((spio
!= MISC_SPIO_SPIO4
) && (spio
!= MISC_SPIO_SPIO5
)) {
2255 BNX2X_ERR("Invalid SPIO 0x%x\n", spio
);
2259 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2260 /* read SPIO and mask except the float bits */
2261 spio_reg
= (REG_RD(bp
, MISC_REG_SPIO
) & MISC_SPIO_FLOAT
);
2264 case MISC_SPIO_OUTPUT_LOW
:
2265 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output low\n", spio
);
2266 /* clear FLOAT and set CLR */
2267 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2268 spio_reg
|= (spio
<< MISC_SPIO_CLR_POS
);
2271 case MISC_SPIO_OUTPUT_HIGH
:
2272 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> output high\n", spio
);
2273 /* clear FLOAT and set SET */
2274 spio_reg
&= ~(spio
<< MISC_SPIO_FLOAT_POS
);
2275 spio_reg
|= (spio
<< MISC_SPIO_SET_POS
);
2278 case MISC_SPIO_INPUT_HI_Z
:
2279 DP(NETIF_MSG_HW
, "Set SPIO 0x%x -> input\n", spio
);
2281 spio_reg
|= (spio
<< MISC_SPIO_FLOAT_POS
);
2288 REG_WR(bp
, MISC_REG_SPIO
, spio_reg
);
2289 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_SPIO
);
2294 void bnx2x_calc_fc_adv(struct bnx2x
*bp
)
2296 u8 cfg_idx
= bnx2x_get_link_cfg_idx(bp
);
2298 bp
->port
.advertising
[cfg_idx
] &= ~(ADVERTISED_Asym_Pause
|
2300 switch (bp
->link_vars
.ieee_fc
&
2301 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK
) {
2302 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH
:
2303 bp
->port
.advertising
[cfg_idx
] |= (ADVERTISED_Asym_Pause
|
2307 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC
:
2308 bp
->port
.advertising
[cfg_idx
] |= ADVERTISED_Asym_Pause
;
2316 static void bnx2x_set_requested_fc(struct bnx2x
*bp
)
2318 /* Initialize link parameters structure variables
2319 * It is recommended to turn off RX FC for jumbo frames
2320 * for better performance
2322 if (CHIP_IS_E1x(bp
) && (bp
->dev
->mtu
> 5000))
2323 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_TX
;
2325 bp
->link_params
.req_fc_auto_adv
= BNX2X_FLOW_CTRL_BOTH
;
2328 static void bnx2x_init_dropless_fc(struct bnx2x
*bp
)
2330 u32 pause_enabled
= 0;
2332 if (!CHIP_IS_E1(bp
) && bp
->dropless_fc
&& bp
->link_vars
.link_up
) {
2333 if (bp
->link_vars
.flow_ctrl
& BNX2X_FLOW_CTRL_TX
)
2336 REG_WR(bp
, BAR_USTRORM_INTMEM
+
2337 USTORM_ETH_PAUSE_ENABLED_OFFSET(BP_PORT(bp
)),
2341 DP(NETIF_MSG_IFUP
| NETIF_MSG_LINK
, "dropless_fc is %s\n",
2342 pause_enabled
? "enabled" : "disabled");
2345 int bnx2x_initial_phy_init(struct bnx2x
*bp
, int load_mode
)
2347 int rc
, cfx_idx
= bnx2x_get_link_cfg_idx(bp
);
2348 u16 req_line_speed
= bp
->link_params
.req_line_speed
[cfx_idx
];
2350 if (!BP_NOMCP(bp
)) {
2351 bnx2x_set_requested_fc(bp
);
2352 bnx2x_acquire_phy_lock(bp
);
2354 if (load_mode
== LOAD_DIAG
) {
2355 struct link_params
*lp
= &bp
->link_params
;
2356 lp
->loopback_mode
= LOOPBACK_XGXS
;
2357 /* Prefer doing PHY loopback at highest speed */
2358 if (lp
->req_line_speed
[cfx_idx
] < SPEED_20000
) {
2359 if (lp
->speed_cap_mask
[cfx_idx
] &
2360 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
)
2361 lp
->req_line_speed
[cfx_idx
] =
2363 else if (lp
->speed_cap_mask
[cfx_idx
] &
2364 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
)
2365 lp
->req_line_speed
[cfx_idx
] =
2368 lp
->req_line_speed
[cfx_idx
] =
2373 if (load_mode
== LOAD_LOOPBACK_EXT
) {
2374 struct link_params
*lp
= &bp
->link_params
;
2375 lp
->loopback_mode
= LOOPBACK_EXT
;
2378 rc
= bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2380 bnx2x_release_phy_lock(bp
);
2382 bnx2x_init_dropless_fc(bp
);
2384 bnx2x_calc_fc_adv(bp
);
2386 if (bp
->link_vars
.link_up
) {
2387 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2388 bnx2x_link_report(bp
);
2390 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2391 bp
->link_params
.req_line_speed
[cfx_idx
] = req_line_speed
;
2394 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
2398 void bnx2x_link_set(struct bnx2x
*bp
)
2400 if (!BP_NOMCP(bp
)) {
2401 bnx2x_acquire_phy_lock(bp
);
2402 bnx2x_phy_init(&bp
->link_params
, &bp
->link_vars
);
2403 bnx2x_release_phy_lock(bp
);
2405 bnx2x_init_dropless_fc(bp
);
2407 bnx2x_calc_fc_adv(bp
);
2409 BNX2X_ERR("Bootcode is missing - can not set link\n");
2412 static void bnx2x__link_reset(struct bnx2x
*bp
)
2414 if (!BP_NOMCP(bp
)) {
2415 bnx2x_acquire_phy_lock(bp
);
2416 bnx2x_lfa_reset(&bp
->link_params
, &bp
->link_vars
);
2417 bnx2x_release_phy_lock(bp
);
2419 BNX2X_ERR("Bootcode is missing - can not reset link\n");
2422 void bnx2x_force_link_reset(struct bnx2x
*bp
)
2424 bnx2x_acquire_phy_lock(bp
);
2425 bnx2x_link_reset(&bp
->link_params
, &bp
->link_vars
, 1);
2426 bnx2x_release_phy_lock(bp
);
2429 u8
bnx2x_link_test(struct bnx2x
*bp
, u8 is_serdes
)
2433 if (!BP_NOMCP(bp
)) {
2434 bnx2x_acquire_phy_lock(bp
);
2435 rc
= bnx2x_test_link(&bp
->link_params
, &bp
->link_vars
,
2437 bnx2x_release_phy_lock(bp
);
2439 BNX2X_ERR("Bootcode is missing - can not test link\n");
2444 /* Calculates the sum of vn_min_rates.
2445 It's needed for further normalizing of the min_rates.
2447 sum of vn_min_rates.
2449 0 - if all the min_rates are 0.
2450 In the later case fairness algorithm should be deactivated.
2451 If not all min_rates are zero then those that are zeroes will be set to 1.
2453 static void bnx2x_calc_vn_min(struct bnx2x
*bp
,
2454 struct cmng_init_input
*input
)
2459 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2460 u32 vn_cfg
= bp
->mf_config
[vn
];
2461 u32 vn_min_rate
= ((vn_cfg
& FUNC_MF_CFG_MIN_BW_MASK
) >>
2462 FUNC_MF_CFG_MIN_BW_SHIFT
) * 100;
2464 /* Skip hidden vns */
2465 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2467 /* If min rate is zero - set it to 1 */
2468 else if (!vn_min_rate
)
2469 vn_min_rate
= DEF_MIN_RATE
;
2473 input
->vnic_min_rate
[vn
] = vn_min_rate
;
2476 /* if ETS or all min rates are zeros - disable fairness */
2477 if (BNX2X_IS_ETS_ENABLED(bp
)) {
2478 input
->flags
.cmng_enables
&=
2479 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2480 DP(NETIF_MSG_IFUP
, "Fairness will be disabled due to ETS\n");
2481 } else if (all_zero
) {
2482 input
->flags
.cmng_enables
&=
2483 ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2485 "All MIN values are zeroes fairness will be disabled\n");
2487 input
->flags
.cmng_enables
|=
2488 CMNG_FLAGS_PER_PORT_FAIRNESS_VN
;
2491 static void bnx2x_calc_vn_max(struct bnx2x
*bp
, int vn
,
2492 struct cmng_init_input
*input
)
2495 u32 vn_cfg
= bp
->mf_config
[vn
];
2497 if (vn_cfg
& FUNC_MF_CFG_FUNC_HIDE
)
2500 u32 maxCfg
= bnx2x_extract_max_cfg(bp
, vn_cfg
);
2502 if (IS_MF_PERCENT_BW(bp
)) {
2503 /* maxCfg in percents of linkspeed */
2504 vn_max_rate
= (bp
->link_vars
.line_speed
* maxCfg
) / 100;
2505 } else /* SD modes */
2506 /* maxCfg is absolute in 100Mb units */
2507 vn_max_rate
= maxCfg
* 100;
2510 DP(NETIF_MSG_IFUP
, "vn %d: vn_max_rate %d\n", vn
, vn_max_rate
);
2512 input
->vnic_max_rate
[vn
] = vn_max_rate
;
2515 static int bnx2x_get_cmng_fns_mode(struct bnx2x
*bp
)
2517 if (CHIP_REV_IS_SLOW(bp
))
2518 return CMNG_FNS_NONE
;
2520 return CMNG_FNS_MINMAX
;
2522 return CMNG_FNS_NONE
;
2525 void bnx2x_read_mf_cfg(struct bnx2x
*bp
)
2527 int vn
, n
= (CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1);
2530 return; /* what should be the default value in this case */
2532 /* For 2 port configuration the absolute function number formula
2534 * abs_func = 2 * vn + BP_PORT + BP_PATH
2536 * and there are 4 functions per port
2538 * For 4 port configuration it is
2539 * abs_func = 4 * vn + 2 * BP_PORT + BP_PATH
2541 * and there are 2 functions per port
2543 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2544 int /*abs*/func
= n
* (2 * vn
+ BP_PORT(bp
)) + BP_PATH(bp
);
2546 if (func
>= E1H_FUNC_MAX
)
2550 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2552 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
2553 DP(NETIF_MSG_IFUP
, "mf_cfg function disabled\n");
2554 bp
->flags
|= MF_FUNC_DIS
;
2556 DP(NETIF_MSG_IFUP
, "mf_cfg function enabled\n");
2557 bp
->flags
&= ~MF_FUNC_DIS
;
2561 static void bnx2x_cmng_fns_init(struct bnx2x
*bp
, u8 read_cfg
, u8 cmng_type
)
2563 struct cmng_init_input input
;
2564 memset(&input
, 0, sizeof(struct cmng_init_input
));
2566 input
.port_rate
= bp
->link_vars
.line_speed
;
2568 if (cmng_type
== CMNG_FNS_MINMAX
&& input
.port_rate
) {
2571 /* read mf conf from shmem */
2573 bnx2x_read_mf_cfg(bp
);
2575 /* vn_weight_sum and enable fairness if not 0 */
2576 bnx2x_calc_vn_min(bp
, &input
);
2578 /* calculate and set min-max rate for each vn */
2580 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++)
2581 bnx2x_calc_vn_max(bp
, vn
, &input
);
2583 /* always enable rate shaping and fairness */
2584 input
.flags
.cmng_enables
|=
2585 CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN
;
2587 bnx2x_init_cmng(&input
, &bp
->cmng
);
2591 /* rate shaping and fairness are disabled */
2593 "rate shaping and fairness are disabled\n");
2596 static void storm_memset_cmng(struct bnx2x
*bp
,
2597 struct cmng_init
*cmng
,
2601 size_t size
= sizeof(struct cmng_struct_per_port
);
2603 u32 addr
= BAR_XSTRORM_INTMEM
+
2604 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port
);
2606 __storm_memset_struct(bp
, addr
, size
, (u32
*)&cmng
->port
);
2608 for (vn
= VN_0
; vn
< BP_MAX_VN_NUM(bp
); vn
++) {
2609 int func
= func_by_vn(bp
, vn
);
2611 addr
= BAR_XSTRORM_INTMEM
+
2612 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func
);
2613 size
= sizeof(struct rate_shaping_vars_per_vn
);
2614 __storm_memset_struct(bp
, addr
, size
,
2615 (u32
*)&cmng
->vnic
.vnic_max_rate
[vn
]);
2617 addr
= BAR_XSTRORM_INTMEM
+
2618 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func
);
2619 size
= sizeof(struct fairness_vars_per_vn
);
2620 __storm_memset_struct(bp
, addr
, size
,
2621 (u32
*)&cmng
->vnic
.vnic_min_rate
[vn
]);
2625 /* init cmng mode in HW according to local configuration */
2626 void bnx2x_set_local_cmng(struct bnx2x
*bp
)
2628 int cmng_fns
= bnx2x_get_cmng_fns_mode(bp
);
2630 if (cmng_fns
!= CMNG_FNS_NONE
) {
2631 bnx2x_cmng_fns_init(bp
, false, cmng_fns
);
2632 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
2634 /* rate shaping and fairness are disabled */
2636 "single function mode without fairness\n");
2640 /* This function is called upon link interrupt */
2641 static void bnx2x_link_attn(struct bnx2x
*bp
)
2643 /* Make sure that we are synced with the current statistics */
2644 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2646 bnx2x_link_update(&bp
->link_params
, &bp
->link_vars
);
2648 bnx2x_init_dropless_fc(bp
);
2650 if (bp
->link_vars
.link_up
) {
2652 if (bp
->link_vars
.mac_type
!= MAC_TYPE_EMAC
) {
2653 struct host_port_stats
*pstats
;
2655 pstats
= bnx2x_sp(bp
, port_stats
);
2656 /* reset old mac stats */
2657 memset(&(pstats
->mac_stx
[0]), 0,
2658 sizeof(struct mac_stx
));
2660 if (bp
->state
== BNX2X_STATE_OPEN
)
2661 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2664 if (bp
->link_vars
.link_up
&& bp
->link_vars
.line_speed
)
2665 bnx2x_set_local_cmng(bp
);
2667 __bnx2x_link_report(bp
);
2670 bnx2x_link_sync_notify(bp
);
2673 void bnx2x__link_status_update(struct bnx2x
*bp
)
2675 if (bp
->state
!= BNX2X_STATE_OPEN
)
2678 /* read updated dcb configuration */
2680 bnx2x_dcbx_pmf_update(bp
);
2681 bnx2x_link_status_update(&bp
->link_params
, &bp
->link_vars
);
2682 if (bp
->link_vars
.link_up
)
2683 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2685 bnx2x_stats_handle(bp
, STATS_EVENT_STOP
);
2686 /* indicate link status */
2687 bnx2x_link_report(bp
);
2690 bp
->port
.supported
[0] |= (SUPPORTED_10baseT_Half
|
2691 SUPPORTED_10baseT_Full
|
2692 SUPPORTED_100baseT_Half
|
2693 SUPPORTED_100baseT_Full
|
2694 SUPPORTED_1000baseT_Full
|
2695 SUPPORTED_2500baseX_Full
|
2696 SUPPORTED_10000baseT_Full
|
2701 SUPPORTED_Asym_Pause
);
2702 bp
->port
.advertising
[0] = bp
->port
.supported
[0];
2704 bp
->link_params
.bp
= bp
;
2705 bp
->link_params
.port
= BP_PORT(bp
);
2706 bp
->link_params
.req_duplex
[0] = DUPLEX_FULL
;
2707 bp
->link_params
.req_flow_ctrl
[0] = BNX2X_FLOW_CTRL_NONE
;
2708 bp
->link_params
.req_line_speed
[0] = SPEED_10000
;
2709 bp
->link_params
.speed_cap_mask
[0] = 0x7f0000;
2710 bp
->link_params
.switch_cfg
= SWITCH_CFG_10G
;
2711 bp
->link_vars
.mac_type
= MAC_TYPE_BMAC
;
2712 bp
->link_vars
.line_speed
= SPEED_10000
;
2713 bp
->link_vars
.link_status
=
2714 (LINK_STATUS_LINK_UP
|
2715 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
);
2716 bp
->link_vars
.link_up
= 1;
2717 bp
->link_vars
.duplex
= DUPLEX_FULL
;
2718 bp
->link_vars
.flow_ctrl
= BNX2X_FLOW_CTRL_NONE
;
2719 __bnx2x_link_report(bp
);
2721 bnx2x_sample_bulletin(bp
);
2723 /* if bulletin board did not have an update for link status
2724 * __bnx2x_link_report will report current status
2725 * but it will NOT duplicate report in case of already reported
2726 * during sampling bulletin board.
2728 bnx2x_stats_handle(bp
, STATS_EVENT_LINK_UP
);
2732 static int bnx2x_afex_func_update(struct bnx2x
*bp
, u16 vifid
,
2733 u16 vlan_val
, u8 allowed_prio
)
2735 struct bnx2x_func_state_params func_params
= {NULL
};
2736 struct bnx2x_func_afex_update_params
*f_update_params
=
2737 &func_params
.params
.afex_update
;
2739 func_params
.f_obj
= &bp
->func_obj
;
2740 func_params
.cmd
= BNX2X_F_CMD_AFEX_UPDATE
;
2742 /* no need to wait for RAMROD completion, so don't
2743 * set RAMROD_COMP_WAIT flag
2746 f_update_params
->vif_id
= vifid
;
2747 f_update_params
->afex_default_vlan
= vlan_val
;
2748 f_update_params
->allowed_priorities
= allowed_prio
;
2750 /* if ramrod can not be sent, response to MCP immediately */
2751 if (bnx2x_func_state_change(bp
, &func_params
) < 0)
2752 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
2757 static int bnx2x_afex_handle_vif_list_cmd(struct bnx2x
*bp
, u8 cmd_type
,
2758 u16 vif_index
, u8 func_bit_map
)
2760 struct bnx2x_func_state_params func_params
= {NULL
};
2761 struct bnx2x_func_afex_viflists_params
*update_params
=
2762 &func_params
.params
.afex_viflists
;
2766 /* validate only LIST_SET and LIST_GET are received from switch */
2767 if ((cmd_type
!= VIF_LIST_RULE_GET
) && (cmd_type
!= VIF_LIST_RULE_SET
))
2768 BNX2X_ERR("BUG! afex_handle_vif_list_cmd invalid type 0x%x\n",
2771 func_params
.f_obj
= &bp
->func_obj
;
2772 func_params
.cmd
= BNX2X_F_CMD_AFEX_VIFLISTS
;
2774 /* set parameters according to cmd_type */
2775 update_params
->afex_vif_list_command
= cmd_type
;
2776 update_params
->vif_list_index
= vif_index
;
2777 update_params
->func_bit_map
=
2778 (cmd_type
== VIF_LIST_RULE_GET
) ? 0 : func_bit_map
;
2779 update_params
->func_to_clear
= 0;
2781 (cmd_type
== VIF_LIST_RULE_GET
) ?
2782 DRV_MSG_CODE_AFEX_LISTGET_ACK
:
2783 DRV_MSG_CODE_AFEX_LISTSET_ACK
;
2785 /* if ramrod can not be sent, respond to MCP immediately for
2786 * SET and GET requests (other are not triggered from MCP)
2788 rc
= bnx2x_func_state_change(bp
, &func_params
);
2790 bnx2x_fw_command(bp
, drv_msg_code
, 0);
2795 static void bnx2x_handle_afex_cmd(struct bnx2x
*bp
, u32 cmd
)
2797 struct afex_stats afex_stats
;
2798 u32 func
= BP_ABS_FUNC(bp
);
2805 u32 addr_to_write
, vifid
, addrs
, stats_type
, i
;
2807 if (cmd
& DRV_STATUS_AFEX_LISTGET_REQ
) {
2808 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2810 "afex: got MCP req LISTGET_REQ for vifid 0x%x\n", vifid
);
2811 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_GET
, vifid
, 0);
2814 if (cmd
& DRV_STATUS_AFEX_LISTSET_REQ
) {
2815 vifid
= SHMEM2_RD(bp
, afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2816 addrs
= SHMEM2_RD(bp
, afex_param2_to_driver
[BP_FW_MB_IDX(bp
)]);
2818 "afex: got MCP req LISTSET_REQ for vifid 0x%x addrs 0x%x\n",
2820 bnx2x_afex_handle_vif_list_cmd(bp
, VIF_LIST_RULE_SET
, vifid
,
2824 if (cmd
& DRV_STATUS_AFEX_STATSGET_REQ
) {
2825 addr_to_write
= SHMEM2_RD(bp
,
2826 afex_scratchpad_addr_to_write
[BP_FW_MB_IDX(bp
)]);
2827 stats_type
= SHMEM2_RD(bp
,
2828 afex_param1_to_driver
[BP_FW_MB_IDX(bp
)]);
2831 "afex: got MCP req STATSGET_REQ, write to addr 0x%x\n",
2834 bnx2x_afex_collect_stats(bp
, (void *)&afex_stats
, stats_type
);
2836 /* write response to scratchpad, for MCP */
2837 for (i
= 0; i
< (sizeof(struct afex_stats
)/sizeof(u32
)); i
++)
2838 REG_WR(bp
, addr_to_write
+ i
*sizeof(u32
),
2839 *(((u32
*)(&afex_stats
))+i
));
2841 /* send ack message to MCP */
2842 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_STATSGET_ACK
, 0);
2845 if (cmd
& DRV_STATUS_AFEX_VIFSET_REQ
) {
2846 mf_config
= MF_CFG_RD(bp
, func_mf_config
[func
].config
);
2847 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2849 "afex: got MCP req VIFSET_REQ, mf_config 0x%x\n",
2852 /* if VIF_SET is "enabled" */
2853 if (!(mf_config
& FUNC_MF_CFG_FUNC_DISABLED
)) {
2854 /* set rate limit directly to internal RAM */
2855 struct cmng_init_input cmng_input
;
2856 struct rate_shaping_vars_per_vn m_rs_vn
;
2857 size_t size
= sizeof(struct rate_shaping_vars_per_vn
);
2858 u32 addr
= BAR_XSTRORM_INTMEM
+
2859 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(BP_FUNC(bp
));
2861 bp
->mf_config
[BP_VN(bp
)] = mf_config
;
2863 bnx2x_calc_vn_max(bp
, BP_VN(bp
), &cmng_input
);
2864 m_rs_vn
.vn_counter
.rate
=
2865 cmng_input
.vnic_max_rate
[BP_VN(bp
)];
2866 m_rs_vn
.vn_counter
.quota
=
2867 (m_rs_vn
.vn_counter
.rate
*
2868 RS_PERIODIC_TIMEOUT_USEC
) / 8;
2870 __storm_memset_struct(bp
, addr
, size
, (u32
*)&m_rs_vn
);
2872 /* read relevant values from mf_cfg struct in shmem */
2874 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2875 FUNC_MF_CFG_E1HOV_TAG_MASK
) >>
2876 FUNC_MF_CFG_E1HOV_TAG_SHIFT
;
2878 (MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2879 FUNC_MF_CFG_AFEX_VLAN_MASK
) >>
2880 FUNC_MF_CFG_AFEX_VLAN_SHIFT
;
2881 vlan_prio
= (mf_config
&
2882 FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK
) >>
2883 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT
;
2884 vlan_val
|= (vlan_prio
<< VLAN_PRIO_SHIFT
);
2887 func_mf_config
[func
].afex_config
) &
2888 FUNC_MF_CFG_AFEX_VLAN_MODE_MASK
) >>
2889 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT
;
2892 func_mf_config
[func
].afex_config
) &
2893 FUNC_MF_CFG_AFEX_COS_FILTER_MASK
) >>
2894 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT
;
2896 /* send ramrod to FW, return in case of failure */
2897 if (bnx2x_afex_func_update(bp
, vif_id
, vlan_val
,
2901 bp
->afex_def_vlan_tag
= vlan_val
;
2902 bp
->afex_vlan_mode
= vlan_mode
;
2904 /* notify link down because BP->flags is disabled */
2905 bnx2x_link_report(bp
);
2907 /* send INVALID VIF ramrod to FW */
2908 bnx2x_afex_func_update(bp
, 0xFFFF, 0, 0);
2910 /* Reset the default afex VLAN */
2911 bp
->afex_def_vlan_tag
= -1;
2916 static void bnx2x_handle_update_svid_cmd(struct bnx2x
*bp
)
2918 struct bnx2x_func_switch_update_params
*switch_update_params
;
2919 struct bnx2x_func_state_params func_params
;
2921 memset(&func_params
, 0, sizeof(struct bnx2x_func_state_params
));
2922 switch_update_params
= &func_params
.params
.switch_update
;
2923 func_params
.f_obj
= &bp
->func_obj
;
2924 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
2926 if (IS_MF_UFP(bp
) || IS_MF_BD(bp
)) {
2927 int func
= BP_ABS_FUNC(bp
);
2930 /* Re-learn the S-tag from shmem */
2931 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
2932 FUNC_MF_CFG_E1HOV_TAG_MASK
;
2933 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
2936 BNX2X_ERR("Got an SVID event, but no tag is configured in shmem\n");
2940 /* Configure new S-tag in LLH */
2941 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ BP_PORT(bp
) * 8,
2944 /* Send Ramrod to update FW of change */
2945 __set_bit(BNX2X_F_UPDATE_SD_VLAN_TAG_CHNG
,
2946 &switch_update_params
->changes
);
2947 switch_update_params
->vlan
= bp
->mf_ov
;
2949 if (bnx2x_func_state_change(bp
, &func_params
) < 0) {
2950 BNX2X_ERR("Failed to configure FW of S-tag Change to %02x\n",
2954 DP(BNX2X_MSG_MCP
, "Configured S-tag %02x\n",
2961 bnx2x_fw_command(bp
, DRV_MSG_CODE_OEM_UPDATE_SVID_OK
, 0);
2964 bnx2x_fw_command(bp
, DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE
, 0);
2967 static void bnx2x_pmf_update(struct bnx2x
*bp
)
2969 int port
= BP_PORT(bp
);
2973 DP(BNX2X_MSG_MCP
, "pmf %d\n", bp
->port
.pmf
);
2976 * We need the mb() to ensure the ordering between the writing to
2977 * bp->port.pmf here and reading it from the bnx2x_periodic_task().
2981 /* queue a periodic task */
2982 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 0);
2984 bnx2x_dcbx_pmf_update(bp
);
2986 /* enable nig attention */
2987 val
= (0xff0f | (1 << (BP_VN(bp
) + 4)));
2988 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
2989 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, val
);
2990 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, val
);
2991 } else if (!CHIP_IS_E1x(bp
)) {
2992 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, val
);
2993 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, val
);
2996 bnx2x_stats_handle(bp
, STATS_EVENT_PMF
);
3004 * General service functions
3007 /* send the MCP a request, block until there is a reply */
3008 u32
bnx2x_fw_command(struct bnx2x
*bp
, u32 command
, u32 param
)
3010 int mb_idx
= BP_FW_MB_IDX(bp
);
3014 u8 delay
= CHIP_REV_IS_SLOW(bp
) ? 100 : 10;
3016 mutex_lock(&bp
->fw_mb_mutex
);
3018 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_param
, param
);
3019 SHMEM_WR(bp
, func_mb
[mb_idx
].drv_mb_header
, (command
| seq
));
3021 DP(BNX2X_MSG_MCP
, "wrote command (%x) to FW MB param 0x%08x\n",
3022 (command
| seq
), param
);
3025 /* let the FW do it's magic ... */
3028 rc
= SHMEM_RD(bp
, func_mb
[mb_idx
].fw_mb_header
);
3030 /* Give the FW up to 5 second (500*10ms) */
3031 } while ((seq
!= (rc
& FW_MSG_SEQ_NUMBER_MASK
)) && (cnt
++ < 500));
3033 DP(BNX2X_MSG_MCP
, "[after %d ms] read (%x) seq is (%x) from FW MB\n",
3034 cnt
*delay
, rc
, seq
);
3036 /* is this a reply to our command? */
3037 if (seq
== (rc
& FW_MSG_SEQ_NUMBER_MASK
))
3038 rc
&= FW_MSG_CODE_MASK
;
3041 BNX2X_ERR("FW failed to respond!\n");
3045 mutex_unlock(&bp
->fw_mb_mutex
);
3050 static void storm_memset_func_cfg(struct bnx2x
*bp
,
3051 struct tstorm_eth_function_common_config
*tcfg
,
3054 size_t size
= sizeof(struct tstorm_eth_function_common_config
);
3056 u32 addr
= BAR_TSTRORM_INTMEM
+
3057 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid
);
3059 __storm_memset_struct(bp
, addr
, size
, (u32
*)tcfg
);
3062 void bnx2x_func_init(struct bnx2x
*bp
, struct bnx2x_func_init_params
*p
)
3064 if (CHIP_IS_E1x(bp
)) {
3065 struct tstorm_eth_function_common_config tcfg
= {0};
3067 storm_memset_func_cfg(bp
, &tcfg
, p
->func_id
);
3070 /* Enable the function in the FW */
3071 storm_memset_vf_to_pf(bp
, p
->func_id
, p
->pf_id
);
3072 storm_memset_func_en(bp
, p
->func_id
, 1);
3075 if (p
->spq_active
) {
3076 storm_memset_spq_addr(bp
, p
->spq_map
, p
->func_id
);
3077 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+
3078 XSTORM_SPQ_PROD_OFFSET(p
->func_id
), p
->spq_prod
);
3083 * bnx2x_get_common_flags - Return common flags
3087 * @zero_stats TRUE if statistics zeroing is needed
3089 * Return the flags that are common for the Tx-only and not normal connections.
3091 static unsigned long bnx2x_get_common_flags(struct bnx2x
*bp
,
3092 struct bnx2x_fastpath
*fp
,
3095 unsigned long flags
= 0;
3097 /* PF driver will always initialize the Queue to an ACTIVE state */
3098 __set_bit(BNX2X_Q_FLG_ACTIVE
, &flags
);
3100 /* tx only connections collect statistics (on the same index as the
3101 * parent connection). The statistics are zeroed when the parent
3102 * connection is initialized.
3105 __set_bit(BNX2X_Q_FLG_STATS
, &flags
);
3107 __set_bit(BNX2X_Q_FLG_ZERO_STATS
, &flags
);
3109 if (bp
->flags
& TX_SWITCHING
)
3110 __set_bit(BNX2X_Q_FLG_TX_SWITCH
, &flags
);
3112 __set_bit(BNX2X_Q_FLG_PCSUM_ON_PKT
, &flags
);
3113 __set_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
, &flags
);
3115 #ifdef BNX2X_STOP_ON_ERROR
3116 __set_bit(BNX2X_Q_FLG_TX_SEC
, &flags
);
3122 static unsigned long bnx2x_get_q_flags(struct bnx2x
*bp
,
3123 struct bnx2x_fastpath
*fp
,
3126 unsigned long flags
= 0;
3128 /* calculate other queue flags */
3130 __set_bit(BNX2X_Q_FLG_OV
, &flags
);
3132 if (IS_FCOE_FP(fp
)) {
3133 __set_bit(BNX2X_Q_FLG_FCOE
, &flags
);
3134 /* For FCoE - force usage of default priority (for afex) */
3135 __set_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI
, &flags
);
3138 if (fp
->mode
!= TPA_MODE_DISABLED
) {
3139 __set_bit(BNX2X_Q_FLG_TPA
, &flags
);
3140 __set_bit(BNX2X_Q_FLG_TPA_IPV6
, &flags
);
3141 if (fp
->mode
== TPA_MODE_GRO
)
3142 __set_bit(BNX2X_Q_FLG_TPA_GRO
, &flags
);
3146 __set_bit(BNX2X_Q_FLG_LEADING_RSS
, &flags
);
3147 __set_bit(BNX2X_Q_FLG_MCAST
, &flags
);
3150 /* Always set HW VLAN stripping */
3151 __set_bit(BNX2X_Q_FLG_VLAN
, &flags
);
3153 /* configure silent vlan removal */
3155 __set_bit(BNX2X_Q_FLG_SILENT_VLAN_REM
, &flags
);
3157 return flags
| bnx2x_get_common_flags(bp
, fp
, true);
3160 static void bnx2x_pf_q_prep_general(struct bnx2x
*bp
,
3161 struct bnx2x_fastpath
*fp
, struct bnx2x_general_setup_params
*gen_init
,
3164 gen_init
->stat_id
= bnx2x_stats_id(fp
);
3165 gen_init
->spcl_id
= fp
->cl_id
;
3167 /* Always use mini-jumbo MTU for FCoE L2 ring */
3169 gen_init
->mtu
= BNX2X_FCOE_MINI_JUMBO_MTU
;
3171 gen_init
->mtu
= bp
->dev
->mtu
;
3173 gen_init
->cos
= cos
;
3175 gen_init
->fp_hsi
= ETH_FP_HSI_VERSION
;
3178 static void bnx2x_pf_rx_q_prep(struct bnx2x
*bp
,
3179 struct bnx2x_fastpath
*fp
, struct rxq_pause_params
*pause
,
3180 struct bnx2x_rxq_setup_params
*rxq_init
)
3184 u16 tpa_agg_size
= 0;
3186 if (fp
->mode
!= TPA_MODE_DISABLED
) {
3187 pause
->sge_th_lo
= SGE_TH_LO(bp
);
3188 pause
->sge_th_hi
= SGE_TH_HI(bp
);
3190 /* validate SGE ring has enough to cross high threshold */
3191 WARN_ON(bp
->dropless_fc
&&
3192 pause
->sge_th_hi
+ FW_PREFETCH_CNT
>
3193 MAX_RX_SGE_CNT
* NUM_RX_SGE_PAGES
);
3195 tpa_agg_size
= TPA_AGG_SIZE
;
3196 max_sge
= SGE_PAGE_ALIGN(bp
->dev
->mtu
) >>
3198 max_sge
= ((max_sge
+ PAGES_PER_SGE
- 1) &
3199 (~(PAGES_PER_SGE
-1))) >> PAGES_PER_SGE_SHIFT
;
3200 sge_sz
= (u16
)min_t(u32
, SGE_PAGES
, 0xffff);
3203 /* pause - not for e1 */
3204 if (!CHIP_IS_E1(bp
)) {
3205 pause
->bd_th_lo
= BD_TH_LO(bp
);
3206 pause
->bd_th_hi
= BD_TH_HI(bp
);
3208 pause
->rcq_th_lo
= RCQ_TH_LO(bp
);
3209 pause
->rcq_th_hi
= RCQ_TH_HI(bp
);
3211 * validate that rings have enough entries to cross
3214 WARN_ON(bp
->dropless_fc
&&
3215 pause
->bd_th_hi
+ FW_PREFETCH_CNT
>
3217 WARN_ON(bp
->dropless_fc
&&
3218 pause
->rcq_th_hi
+ FW_PREFETCH_CNT
>
3219 NUM_RCQ_RINGS
* MAX_RCQ_DESC_CNT
);
3225 rxq_init
->dscr_map
= fp
->rx_desc_mapping
;
3226 rxq_init
->sge_map
= fp
->rx_sge_mapping
;
3227 rxq_init
->rcq_map
= fp
->rx_comp_mapping
;
3228 rxq_init
->rcq_np_map
= fp
->rx_comp_mapping
+ BCM_PAGE_SIZE
;
3230 /* This should be a maximum number of data bytes that may be
3231 * placed on the BD (not including paddings).
3233 rxq_init
->buf_sz
= fp
->rx_buf_size
- BNX2X_FW_RX_ALIGN_START
-
3234 BNX2X_FW_RX_ALIGN_END
- IP_HEADER_ALIGNMENT_PADDING
;
3236 rxq_init
->cl_qzone_id
= fp
->cl_qzone_id
;
3237 rxq_init
->tpa_agg_sz
= tpa_agg_size
;
3238 rxq_init
->sge_buf_sz
= sge_sz
;
3239 rxq_init
->max_sges_pkt
= max_sge
;
3240 rxq_init
->rss_engine_id
= BP_FUNC(bp
);
3241 rxq_init
->mcast_engine_id
= BP_FUNC(bp
);
3243 /* Maximum number or simultaneous TPA aggregation for this Queue.
3245 * For PF Clients it should be the maximum available number.
3246 * VF driver(s) may want to define it to a smaller value.
3248 rxq_init
->max_tpa_queues
= MAX_AGG_QS(bp
);
3250 rxq_init
->cache_line_log
= BNX2X_RX_ALIGN_SHIFT
;
3251 rxq_init
->fw_sb_id
= fp
->fw_sb_id
;
3254 rxq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS
;
3256 rxq_init
->sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
3257 /* configure silent vlan removal
3258 * if multi function mode is afex, then mask default vlan
3260 if (IS_MF_AFEX(bp
)) {
3261 rxq_init
->silent_removal_value
= bp
->afex_def_vlan_tag
;
3262 rxq_init
->silent_removal_mask
= VLAN_VID_MASK
;
3266 static void bnx2x_pf_tx_q_prep(struct bnx2x
*bp
,
3267 struct bnx2x_fastpath
*fp
, struct bnx2x_txq_setup_params
*txq_init
,
3270 txq_init
->dscr_map
= fp
->txdata_ptr
[cos
]->tx_desc_mapping
;
3271 txq_init
->sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
+ cos
;
3272 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_NW
;
3273 txq_init
->fw_sb_id
= fp
->fw_sb_id
;
3276 * set the tss leading client id for TX classification ==
3277 * leading RSS client id
3279 txq_init
->tss_leading_cl_id
= bnx2x_fp(bp
, 0, cl_id
);
3281 if (IS_FCOE_FP(fp
)) {
3282 txq_init
->sb_cq_index
= HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS
;
3283 txq_init
->traffic_type
= LLFC_TRAFFIC_TYPE_FCOE
;
3287 static void bnx2x_pf_init(struct bnx2x
*bp
)
3289 struct bnx2x_func_init_params func_init
= {0};
3290 struct event_ring_data eq_data
= { {0} };
3292 if (!CHIP_IS_E1x(bp
)) {
3293 /* reset IGU PF statistics: MSIX + ATTN */
3295 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3296 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3297 (CHIP_MODE_IS_4_PORT(bp
) ?
3298 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3300 REG_WR(bp
, IGU_REG_STATISTIC_NUM_MESSAGE_SENT
+
3301 BNX2X_IGU_STAS_MSG_VF_CNT
*4 +
3302 BNX2X_IGU_STAS_MSG_PF_CNT
*4 +
3303 (CHIP_MODE_IS_4_PORT(bp
) ?
3304 BP_FUNC(bp
) : BP_VN(bp
))*4, 0);
3307 func_init
.spq_active
= true;
3308 func_init
.pf_id
= BP_FUNC(bp
);
3309 func_init
.func_id
= BP_FUNC(bp
);
3310 func_init
.spq_map
= bp
->spq_mapping
;
3311 func_init
.spq_prod
= bp
->spq_prod_idx
;
3313 bnx2x_func_init(bp
, &func_init
);
3315 memset(&(bp
->cmng
), 0, sizeof(struct cmng_struct_per_port
));
3318 * Congestion management values depend on the link rate
3319 * There is no active link so initial link rate is set to 10 Gbps.
3320 * When the link comes up The congestion management values are
3321 * re-calculated according to the actual link rate.
3323 bp
->link_vars
.line_speed
= SPEED_10000
;
3324 bnx2x_cmng_fns_init(bp
, true, bnx2x_get_cmng_fns_mode(bp
));
3326 /* Only the PMF sets the HW */
3328 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3330 /* init Event Queue - PCI bus guarantees correct endianity*/
3331 eq_data
.base_addr
.hi
= U64_HI(bp
->eq_mapping
);
3332 eq_data
.base_addr
.lo
= U64_LO(bp
->eq_mapping
);
3333 eq_data
.producer
= bp
->eq_prod
;
3334 eq_data
.index_id
= HC_SP_INDEX_EQ_CONS
;
3335 eq_data
.sb_id
= DEF_SB_ID
;
3336 storm_memset_eq_data(bp
, &eq_data
, BP_FUNC(bp
));
3339 static void bnx2x_e1h_disable(struct bnx2x
*bp
)
3341 int port
= BP_PORT(bp
);
3343 bnx2x_tx_disable(bp
);
3345 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
3348 static void bnx2x_e1h_enable(struct bnx2x
*bp
)
3350 int port
= BP_PORT(bp
);
3352 if (!(IS_MF_UFP(bp
) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
)))
3353 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
* 8, 1);
3355 /* Tx queue should be only re-enabled */
3356 netif_tx_wake_all_queues(bp
->dev
);
3359 * Should not call netif_carrier_on since it will be called if the link
3360 * is up when checking for link state
3364 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3
3366 static void bnx2x_drv_info_ether_stat(struct bnx2x
*bp
)
3368 struct eth_stats_info
*ether_stat
=
3369 &bp
->slowpath
->drv_info_to_mcp
.ether_stat
;
3370 struct bnx2x_vlan_mac_obj
*mac_obj
=
3371 &bp
->sp_objs
->mac_obj
;
3374 strlcpy(ether_stat
->version
, DRV_MODULE_VERSION
,
3375 ETH_STAT_INFO_VERSION_LEN
);
3377 /* get DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED macs, placing them in the
3378 * mac_local field in ether_stat struct. The base address is offset by 2
3379 * bytes to account for the field being 8 bytes but a mac address is
3380 * only 6 bytes. Likewise, the stride for the get_n_elements function is
3381 * 2 bytes to compensate from the 6 bytes of a mac to the 8 bytes
3382 * allocated by the ether_stat struct, so the macs will land in their
3385 for (i
= 0; i
< DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
; i
++)
3386 memset(ether_stat
->mac_local
+ i
, 0,
3387 sizeof(ether_stat
->mac_local
[0]));
3388 mac_obj
->get_n_elements(bp
, &bp
->sp_objs
[0].mac_obj
,
3389 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED
,
3390 ether_stat
->mac_local
+ MAC_PAD
, MAC_PAD
,
3392 ether_stat
->mtu_size
= bp
->dev
->mtu
;
3393 if (bp
->dev
->features
& NETIF_F_RXCSUM
)
3394 ether_stat
->feature_flags
|= FEATURE_ETH_CHKSUM_OFFLOAD_MASK
;
3395 if (bp
->dev
->features
& NETIF_F_TSO
)
3396 ether_stat
->feature_flags
|= FEATURE_ETH_LSO_MASK
;
3397 ether_stat
->feature_flags
|= bp
->common
.boot_mode
;
3399 ether_stat
->promiscuous_mode
= (bp
->dev
->flags
& IFF_PROMISC
) ? 1 : 0;
3401 ether_stat
->txq_size
= bp
->tx_ring_size
;
3402 ether_stat
->rxq_size
= bp
->rx_ring_size
;
3404 #ifdef CONFIG_BNX2X_SRIOV
3405 ether_stat
->vf_cnt
= IS_SRIOV(bp
) ? bp
->vfdb
->sriov
.nr_virtfn
: 0;
3409 static void bnx2x_drv_info_fcoe_stat(struct bnx2x
*bp
)
3411 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3412 struct fcoe_stats_info
*fcoe_stat
=
3413 &bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
;
3415 if (!CNIC_LOADED(bp
))
3418 memcpy(fcoe_stat
->mac_local
+ MAC_PAD
, bp
->fip_mac
, ETH_ALEN
);
3420 fcoe_stat
->qos_priority
=
3421 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_FCOE
];
3423 /* insert FCoE stats from ramrod response */
3425 struct tstorm_per_queue_stats
*fcoe_q_tstorm_stats
=
3426 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3427 tstorm_queue_statistics
;
3429 struct xstorm_per_queue_stats
*fcoe_q_xstorm_stats
=
3430 &bp
->fw_stats_data
->queue_stats
[FCOE_IDX(bp
)].
3431 xstorm_queue_statistics
;
3433 struct fcoe_statistics_params
*fw_fcoe_stat
=
3434 &bp
->fw_stats_data
->fcoe
;
3436 ADD_64_LE(fcoe_stat
->rx_bytes_hi
, LE32_0
,
3437 fcoe_stat
->rx_bytes_lo
,
3438 fw_fcoe_stat
->rx_stat0
.fcoe_rx_byte_cnt
);
3440 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3441 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.hi
,
3442 fcoe_stat
->rx_bytes_lo
,
3443 fcoe_q_tstorm_stats
->rcv_ucast_bytes
.lo
);
3445 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3446 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.hi
,
3447 fcoe_stat
->rx_bytes_lo
,
3448 fcoe_q_tstorm_stats
->rcv_bcast_bytes
.lo
);
3450 ADD_64_LE(fcoe_stat
->rx_bytes_hi
,
3451 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.hi
,
3452 fcoe_stat
->rx_bytes_lo
,
3453 fcoe_q_tstorm_stats
->rcv_mcast_bytes
.lo
);
3455 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3456 fcoe_stat
->rx_frames_lo
,
3457 fw_fcoe_stat
->rx_stat0
.fcoe_rx_pkt_cnt
);
3459 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3460 fcoe_stat
->rx_frames_lo
,
3461 fcoe_q_tstorm_stats
->rcv_ucast_pkts
);
3463 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3464 fcoe_stat
->rx_frames_lo
,
3465 fcoe_q_tstorm_stats
->rcv_bcast_pkts
);
3467 ADD_64_LE(fcoe_stat
->rx_frames_hi
, LE32_0
,
3468 fcoe_stat
->rx_frames_lo
,
3469 fcoe_q_tstorm_stats
->rcv_mcast_pkts
);
3471 ADD_64_LE(fcoe_stat
->tx_bytes_hi
, LE32_0
,
3472 fcoe_stat
->tx_bytes_lo
,
3473 fw_fcoe_stat
->tx_stat
.fcoe_tx_byte_cnt
);
3475 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3476 fcoe_q_xstorm_stats
->ucast_bytes_sent
.hi
,
3477 fcoe_stat
->tx_bytes_lo
,
3478 fcoe_q_xstorm_stats
->ucast_bytes_sent
.lo
);
3480 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3481 fcoe_q_xstorm_stats
->bcast_bytes_sent
.hi
,
3482 fcoe_stat
->tx_bytes_lo
,
3483 fcoe_q_xstorm_stats
->bcast_bytes_sent
.lo
);
3485 ADD_64_LE(fcoe_stat
->tx_bytes_hi
,
3486 fcoe_q_xstorm_stats
->mcast_bytes_sent
.hi
,
3487 fcoe_stat
->tx_bytes_lo
,
3488 fcoe_q_xstorm_stats
->mcast_bytes_sent
.lo
);
3490 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3491 fcoe_stat
->tx_frames_lo
,
3492 fw_fcoe_stat
->tx_stat
.fcoe_tx_pkt_cnt
);
3494 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3495 fcoe_stat
->tx_frames_lo
,
3496 fcoe_q_xstorm_stats
->ucast_pkts_sent
);
3498 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3499 fcoe_stat
->tx_frames_lo
,
3500 fcoe_q_xstorm_stats
->bcast_pkts_sent
);
3502 ADD_64_LE(fcoe_stat
->tx_frames_hi
, LE32_0
,
3503 fcoe_stat
->tx_frames_lo
,
3504 fcoe_q_xstorm_stats
->mcast_pkts_sent
);
3507 /* ask L5 driver to add data to the struct */
3508 bnx2x_cnic_notify(bp
, CNIC_CTL_FCOE_STATS_GET_CMD
);
3511 static void bnx2x_drv_info_iscsi_stat(struct bnx2x
*bp
)
3513 struct bnx2x_dcbx_app_params
*app
= &bp
->dcbx_port_params
.app
;
3514 struct iscsi_stats_info
*iscsi_stat
=
3515 &bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
;
3517 if (!CNIC_LOADED(bp
))
3520 memcpy(iscsi_stat
->mac_local
+ MAC_PAD
, bp
->cnic_eth_dev
.iscsi_mac
,
3523 iscsi_stat
->qos_priority
=
3524 app
->traffic_type_priority
[LLFC_TRAFFIC_TYPE_ISCSI
];
3526 /* ask L5 driver to add data to the struct */
3527 bnx2x_cnic_notify(bp
, CNIC_CTL_ISCSI_STATS_GET_CMD
);
3530 /* called due to MCP event (on pmf):
3531 * reread new bandwidth configuration
3533 * notify others function about the change
3535 static void bnx2x_config_mf_bw(struct bnx2x
*bp
)
3537 if (bp
->link_vars
.link_up
) {
3538 bnx2x_cmng_fns_init(bp
, true, CMNG_FNS_MINMAX
);
3539 bnx2x_link_sync_notify(bp
);
3541 storm_memset_cmng(bp
, &bp
->cmng
, BP_PORT(bp
));
3544 static void bnx2x_set_mf_bw(struct bnx2x
*bp
)
3546 bnx2x_config_mf_bw(bp
);
3547 bnx2x_fw_command(bp
, DRV_MSG_CODE_SET_MF_BW_ACK
, 0);
3550 static void bnx2x_handle_eee_event(struct bnx2x
*bp
)
3552 DP(BNX2X_MSG_MCP
, "EEE - LLDP event\n");
3553 bnx2x_fw_command(bp
, DRV_MSG_CODE_EEE_RESULTS_ACK
, 0);
3556 #define BNX2X_UPDATE_DRV_INFO_IND_LENGTH (20)
3557 #define BNX2X_UPDATE_DRV_INFO_IND_COUNT (25)
3559 static void bnx2x_handle_drv_info_req(struct bnx2x
*bp
)
3561 enum drv_info_opcode op_code
;
3562 u32 drv_info_ctl
= SHMEM2_RD(bp
, drv_info_control
);
3563 bool release
= false;
3566 /* if drv_info version supported by MFW doesn't match - send NACK */
3567 if ((drv_info_ctl
& DRV_INFO_CONTROL_VER_MASK
) != DRV_INFO_CUR_VER
) {
3568 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3572 op_code
= (drv_info_ctl
& DRV_INFO_CONTROL_OP_CODE_MASK
) >>
3573 DRV_INFO_CONTROL_OP_CODE_SHIFT
;
3575 /* Must prevent other flows from accessing drv_info_to_mcp */
3576 mutex_lock(&bp
->drv_info_mutex
);
3578 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3579 sizeof(union drv_info_to_mcp
));
3582 case ETH_STATS_OPCODE
:
3583 bnx2x_drv_info_ether_stat(bp
);
3585 case FCOE_STATS_OPCODE
:
3586 bnx2x_drv_info_fcoe_stat(bp
);
3588 case ISCSI_STATS_OPCODE
:
3589 bnx2x_drv_info_iscsi_stat(bp
);
3592 /* if op code isn't supported - send NACK */
3593 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_NACK
, 0);
3597 /* if we got drv_info attn from MFW then these fields are defined in
3600 SHMEM2_WR(bp
, drv_info_host_addr_lo
,
3601 U64_LO(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3602 SHMEM2_WR(bp
, drv_info_host_addr_hi
,
3603 U64_HI(bnx2x_sp_mapping(bp
, drv_info_to_mcp
)));
3605 bnx2x_fw_command(bp
, DRV_MSG_CODE_DRV_INFO_ACK
, 0);
3607 /* Since possible management wants both this and get_driver_version
3608 * need to wait until management notifies us it finished utilizing
3611 if (!SHMEM2_HAS(bp
, mfw_drv_indication
)) {
3612 DP(BNX2X_MSG_MCP
, "Management does not support indication\n");
3613 } else if (!bp
->drv_info_mng_owner
) {
3614 u32 bit
= MFW_DRV_IND_READ_DONE_OFFSET((BP_ABS_FUNC(bp
) >> 1));
3616 for (wait
= 0; wait
< BNX2X_UPDATE_DRV_INFO_IND_COUNT
; wait
++) {
3617 u32 indication
= SHMEM2_RD(bp
, mfw_drv_indication
);
3619 /* Management is done; need to clear indication */
3620 if (indication
& bit
) {
3621 SHMEM2_WR(bp
, mfw_drv_indication
,
3627 msleep(BNX2X_UPDATE_DRV_INFO_IND_LENGTH
);
3631 DP(BNX2X_MSG_MCP
, "Management did not release indication\n");
3632 bp
->drv_info_mng_owner
= true;
3636 mutex_unlock(&bp
->drv_info_mutex
);
3639 static u32
bnx2x_update_mng_version_utility(u8
*version
, bool bnx2x_format
)
3645 i
= sscanf(version
, "1.%c%hhd.%hhd.%hhd",
3646 &vals
[0], &vals
[1], &vals
[2], &vals
[3]);
3650 i
= sscanf(version
, "%hhd.%hhd.%hhd.%hhd",
3651 &vals
[0], &vals
[1], &vals
[2], &vals
[3]);
3657 return (vals
[0] << 24) | (vals
[1] << 16) | (vals
[2] << 8) | vals
[3];
3660 void bnx2x_update_mng_version(struct bnx2x
*bp
)
3662 u32 iscsiver
= DRV_VER_NOT_LOADED
;
3663 u32 fcoever
= DRV_VER_NOT_LOADED
;
3664 u32 ethver
= DRV_VER_NOT_LOADED
;
3665 int idx
= BP_FW_MB_IDX(bp
);
3668 if (!SHMEM2_HAS(bp
, func_os_drv_ver
))
3671 mutex_lock(&bp
->drv_info_mutex
);
3672 /* Must not proceed when `bnx2x_handle_drv_info_req' is feasible */
3673 if (bp
->drv_info_mng_owner
)
3676 if (bp
->state
!= BNX2X_STATE_OPEN
)
3679 /* Parse ethernet driver version */
3680 ethver
= bnx2x_update_mng_version_utility(DRV_MODULE_VERSION
, true);
3681 if (!CNIC_LOADED(bp
))
3684 /* Try getting storage driver version via cnic */
3685 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3686 sizeof(union drv_info_to_mcp
));
3687 bnx2x_drv_info_iscsi_stat(bp
);
3688 version
= bp
->slowpath
->drv_info_to_mcp
.iscsi_stat
.version
;
3689 iscsiver
= bnx2x_update_mng_version_utility(version
, false);
3691 memset(&bp
->slowpath
->drv_info_to_mcp
, 0,
3692 sizeof(union drv_info_to_mcp
));
3693 bnx2x_drv_info_fcoe_stat(bp
);
3694 version
= bp
->slowpath
->drv_info_to_mcp
.fcoe_stat
.version
;
3695 fcoever
= bnx2x_update_mng_version_utility(version
, false);
3698 SHMEM2_WR(bp
, func_os_drv_ver
[idx
].versions
[DRV_PERS_ETHERNET
], ethver
);
3699 SHMEM2_WR(bp
, func_os_drv_ver
[idx
].versions
[DRV_PERS_ISCSI
], iscsiver
);
3700 SHMEM2_WR(bp
, func_os_drv_ver
[idx
].versions
[DRV_PERS_FCOE
], fcoever
);
3702 mutex_unlock(&bp
->drv_info_mutex
);
3704 DP(BNX2X_MSG_MCP
, "Setting driver version: ETH [%08x] iSCSI [%08x] FCoE [%08x]\n",
3705 ethver
, iscsiver
, fcoever
);
3708 void bnx2x_update_mfw_dump(struct bnx2x
*bp
)
3713 if (!SHMEM2_HAS(bp
, drv_info
))
3716 /* Update Driver load time, possibly broken in y2038 */
3717 SHMEM2_WR(bp
, drv_info
.epoc
, (u32
)ktime_get_real_seconds());
3719 drv_ver
= bnx2x_update_mng_version_utility(DRV_MODULE_VERSION
, true);
3720 SHMEM2_WR(bp
, drv_info
.drv_ver
, drv_ver
);
3722 SHMEM2_WR(bp
, drv_info
.fw_ver
, REG_RD(bp
, XSEM_REG_PRAM
));
3724 /* Check & notify On-Chip dump. */
3725 valid_dump
= SHMEM2_RD(bp
, drv_info
.valid_dump
);
3727 if (valid_dump
& FIRST_DUMP_VALID
)
3728 DP(NETIF_MSG_IFUP
, "A valid On-Chip MFW dump found on 1st partition\n");
3730 if (valid_dump
& SECOND_DUMP_VALID
)
3731 DP(NETIF_MSG_IFUP
, "A valid On-Chip MFW dump found on 2nd partition\n");
3734 static void bnx2x_oem_event(struct bnx2x
*bp
, u32 event
)
3736 u32 cmd_ok
, cmd_fail
;
3739 if (event
& DRV_STATUS_DCC_EVENT_MASK
&&
3740 event
& DRV_STATUS_OEM_EVENT_MASK
) {
3741 BNX2X_ERR("Received simultaneous events %08x\n", event
);
3745 if (event
& DRV_STATUS_DCC_EVENT_MASK
) {
3746 cmd_fail
= DRV_MSG_CODE_DCC_FAILURE
;
3747 cmd_ok
= DRV_MSG_CODE_DCC_OK
;
3748 } else /* if (event & DRV_STATUS_OEM_EVENT_MASK) */ {
3749 cmd_fail
= DRV_MSG_CODE_OEM_FAILURE
;
3750 cmd_ok
= DRV_MSG_CODE_OEM_OK
;
3753 DP(BNX2X_MSG_MCP
, "oem_event 0x%x\n", event
);
3755 if (event
& (DRV_STATUS_DCC_DISABLE_ENABLE_PF
|
3756 DRV_STATUS_OEM_DISABLE_ENABLE_PF
)) {
3757 /* This is the only place besides the function initialization
3758 * where the bp->flags can change so it is done without any
3761 if (bp
->mf_config
[BP_VN(bp
)] & FUNC_MF_CFG_FUNC_DISABLED
) {
3762 DP(BNX2X_MSG_MCP
, "mf_cfg function disabled\n");
3763 bp
->flags
|= MF_FUNC_DIS
;
3765 bnx2x_e1h_disable(bp
);
3767 DP(BNX2X_MSG_MCP
, "mf_cfg function enabled\n");
3768 bp
->flags
&= ~MF_FUNC_DIS
;
3770 bnx2x_e1h_enable(bp
);
3772 event
&= ~(DRV_STATUS_DCC_DISABLE_ENABLE_PF
|
3773 DRV_STATUS_OEM_DISABLE_ENABLE_PF
);
3776 if (event
& (DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
|
3777 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION
)) {
3778 bnx2x_config_mf_bw(bp
);
3779 event
&= ~(DRV_STATUS_DCC_BANDWIDTH_ALLOCATION
|
3780 DRV_STATUS_OEM_BANDWIDTH_ALLOCATION
);
3783 /* Report results to MCP */
3785 bnx2x_fw_command(bp
, cmd_fail
, 0);
3787 bnx2x_fw_command(bp
, cmd_ok
, 0);
3790 /* must be called under the spq lock */
3791 static struct eth_spe
*bnx2x_sp_get_next(struct bnx2x
*bp
)
3793 struct eth_spe
*next_spe
= bp
->spq_prod_bd
;
3795 if (bp
->spq_prod_bd
== bp
->spq_last_bd
) {
3796 bp
->spq_prod_bd
= bp
->spq
;
3797 bp
->spq_prod_idx
= 0;
3798 DP(BNX2X_MSG_SP
, "end of spq\n");
3806 /* must be called under the spq lock */
3807 static void bnx2x_sp_prod_update(struct bnx2x
*bp
)
3809 int func
= BP_FUNC(bp
);
3812 * Make sure that BD data is updated before writing the producer:
3813 * BD data is written to the memory, the producer is read from the
3814 * memory, thus we need a full memory barrier to ensure the ordering.
3818 REG_WR16(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_PROD_OFFSET(func
),
3824 * bnx2x_is_contextless_ramrod - check if the current command ends on EQ
3826 * @cmd: command to check
3827 * @cmd_type: command type
3829 static bool bnx2x_is_contextless_ramrod(int cmd
, int cmd_type
)
3831 if ((cmd_type
== NONE_CONNECTION_TYPE
) ||
3832 (cmd
== RAMROD_CMD_ID_ETH_FORWARD_SETUP
) ||
3833 (cmd
== RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES
) ||
3834 (cmd
== RAMROD_CMD_ID_ETH_FILTER_RULES
) ||
3835 (cmd
== RAMROD_CMD_ID_ETH_MULTICAST_RULES
) ||
3836 (cmd
== RAMROD_CMD_ID_ETH_SET_MAC
) ||
3837 (cmd
== RAMROD_CMD_ID_ETH_RSS_UPDATE
))
3844 * bnx2x_sp_post - place a single command on an SP ring
3846 * @bp: driver handle
3847 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.)
3848 * @cid: SW CID the command is related to
3849 * @data_hi: command private data address (high 32 bits)
3850 * @data_lo: command private data address (low 32 bits)
3851 * @cmd_type: command type (e.g. NONE, ETH)
3853 * SP data is handled as if it's always an address pair, thus data fields are
3854 * not swapped to little endian in upper functions. Instead this function swaps
3855 * data as if it's two u32 fields.
3857 int bnx2x_sp_post(struct bnx2x
*bp
, int command
, int cid
,
3858 u32 data_hi
, u32 data_lo
, int cmd_type
)
3860 struct eth_spe
*spe
;
3862 bool common
= bnx2x_is_contextless_ramrod(command
, cmd_type
);
3864 #ifdef BNX2X_STOP_ON_ERROR
3865 if (unlikely(bp
->panic
)) {
3866 BNX2X_ERR("Can't post SP when there is panic\n");
3871 spin_lock_bh(&bp
->spq_lock
);
3874 if (!atomic_read(&bp
->eq_spq_left
)) {
3875 BNX2X_ERR("BUG! EQ ring full!\n");
3876 spin_unlock_bh(&bp
->spq_lock
);
3880 } else if (!atomic_read(&bp
->cq_spq_left
)) {
3881 BNX2X_ERR("BUG! SPQ ring full!\n");
3882 spin_unlock_bh(&bp
->spq_lock
);
3887 spe
= bnx2x_sp_get_next(bp
);
3889 /* CID needs port number to be encoded int it */
3890 spe
->hdr
.conn_and_cmd_data
=
3891 cpu_to_le32((command
<< SPE_HDR_CMD_ID_SHIFT
) |
3894 /* In some cases, type may already contain the func-id
3895 * mainly in SRIOV related use cases, so we add it here only
3896 * if it's not already set.
3898 if (!(cmd_type
& SPE_HDR_FUNCTION_ID
)) {
3899 type
= (cmd_type
<< SPE_HDR_CONN_TYPE_SHIFT
) &
3901 type
|= ((BP_FUNC(bp
) << SPE_HDR_FUNCTION_ID_SHIFT
) &
3902 SPE_HDR_FUNCTION_ID
);
3907 spe
->hdr
.type
= cpu_to_le16(type
);
3909 spe
->data
.update_data_addr
.hi
= cpu_to_le32(data_hi
);
3910 spe
->data
.update_data_addr
.lo
= cpu_to_le32(data_lo
);
3913 * It's ok if the actual decrement is issued towards the memory
3914 * somewhere between the spin_lock and spin_unlock. Thus no
3915 * more explicit memory barrier is needed.
3918 atomic_dec(&bp
->eq_spq_left
);
3920 atomic_dec(&bp
->cq_spq_left
);
3923 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%x,%x)\n",
3924 bp
->spq_prod_idx
, (u32
)U64_HI(bp
->spq_mapping
),
3925 (u32
)(U64_LO(bp
->spq_mapping
) +
3926 (void *)bp
->spq_prod_bd
- (void *)bp
->spq
), command
, common
,
3927 HW_CID(bp
, cid
), data_hi
, data_lo
, type
,
3928 atomic_read(&bp
->cq_spq_left
), atomic_read(&bp
->eq_spq_left
));
3930 bnx2x_sp_prod_update(bp
);
3931 spin_unlock_bh(&bp
->spq_lock
);
3935 /* acquire split MCP access lock register */
3936 static int bnx2x_acquire_alr(struct bnx2x
*bp
)
3942 for (j
= 0; j
< 1000; j
++) {
3943 REG_WR(bp
, MCP_REG_MCPR_ACCESS_LOCK
, MCPR_ACCESS_LOCK_LOCK
);
3944 val
= REG_RD(bp
, MCP_REG_MCPR_ACCESS_LOCK
);
3945 if (val
& MCPR_ACCESS_LOCK_LOCK
)
3948 usleep_range(5000, 10000);
3950 if (!(val
& MCPR_ACCESS_LOCK_LOCK
)) {
3951 BNX2X_ERR("Cannot acquire MCP access lock register\n");
3958 /* release split MCP access lock register */
3959 static void bnx2x_release_alr(struct bnx2x
*bp
)
3961 REG_WR(bp
, MCP_REG_MCPR_ACCESS_LOCK
, 0);
3964 #define BNX2X_DEF_SB_ATT_IDX 0x0001
3965 #define BNX2X_DEF_SB_IDX 0x0002
3967 static u16
bnx2x_update_dsb_idx(struct bnx2x
*bp
)
3969 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
3972 barrier(); /* status block is written to by the chip */
3973 if (bp
->def_att_idx
!= def_sb
->atten_status_block
.attn_bits_index
) {
3974 bp
->def_att_idx
= def_sb
->atten_status_block
.attn_bits_index
;
3975 rc
|= BNX2X_DEF_SB_ATT_IDX
;
3978 if (bp
->def_idx
!= def_sb
->sp_sb
.running_index
) {
3979 bp
->def_idx
= def_sb
->sp_sb
.running_index
;
3980 rc
|= BNX2X_DEF_SB_IDX
;
3983 /* Do not reorder: indices reading should complete before handling */
3989 * slow path service functions
3992 static void bnx2x_attn_int_asserted(struct bnx2x
*bp
, u32 asserted
)
3994 int port
= BP_PORT(bp
);
3995 u32 aeu_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
3996 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
3997 u32 nig_int_mask_addr
= port
? NIG_REG_MASK_INTERRUPT_PORT1
:
3998 NIG_REG_MASK_INTERRUPT_PORT0
;
4003 if (bp
->attn_state
& asserted
)
4004 BNX2X_ERR("IGU ERROR\n");
4006 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4007 aeu_mask
= REG_RD(bp
, aeu_addr
);
4009 DP(NETIF_MSG_HW
, "aeu_mask %x newly asserted %x\n",
4010 aeu_mask
, asserted
);
4011 aeu_mask
&= ~(asserted
& 0x3ff);
4012 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
4014 REG_WR(bp
, aeu_addr
, aeu_mask
);
4015 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
4017 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
4018 bp
->attn_state
|= asserted
;
4019 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
4021 if (asserted
& ATTN_HARD_WIRED_MASK
) {
4022 if (asserted
& ATTN_NIG_FOR_FUNC
) {
4024 bnx2x_acquire_phy_lock(bp
);
4026 /* save nig interrupt mask */
4027 nig_mask
= REG_RD(bp
, nig_int_mask_addr
);
4029 /* If nig_mask is not set, no need to call the update
4033 REG_WR(bp
, nig_int_mask_addr
, 0);
4035 bnx2x_link_attn(bp
);
4038 /* handle unicore attn? */
4040 if (asserted
& ATTN_SW_TIMER_4_FUNC
)
4041 DP(NETIF_MSG_HW
, "ATTN_SW_TIMER_4_FUNC!\n");
4043 if (asserted
& GPIO_2_FUNC
)
4044 DP(NETIF_MSG_HW
, "GPIO_2_FUNC!\n");
4046 if (asserted
& GPIO_3_FUNC
)
4047 DP(NETIF_MSG_HW
, "GPIO_3_FUNC!\n");
4049 if (asserted
& GPIO_4_FUNC
)
4050 DP(NETIF_MSG_HW
, "GPIO_4_FUNC!\n");
4053 if (asserted
& ATTN_GENERAL_ATTN_1
) {
4054 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_1!\n");
4055 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_1
, 0x0);
4057 if (asserted
& ATTN_GENERAL_ATTN_2
) {
4058 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_2!\n");
4059 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_2
, 0x0);
4061 if (asserted
& ATTN_GENERAL_ATTN_3
) {
4062 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_3!\n");
4063 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_3
, 0x0);
4066 if (asserted
& ATTN_GENERAL_ATTN_4
) {
4067 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_4!\n");
4068 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_4
, 0x0);
4070 if (asserted
& ATTN_GENERAL_ATTN_5
) {
4071 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_5!\n");
4072 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_5
, 0x0);
4074 if (asserted
& ATTN_GENERAL_ATTN_6
) {
4075 DP(NETIF_MSG_HW
, "ATTN_GENERAL_ATTN_6!\n");
4076 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_6
, 0x0);
4080 } /* if hardwired */
4082 if (bp
->common
.int_block
== INT_BLOCK_HC
)
4083 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
4084 COMMAND_REG_ATTN_BITS_SET
);
4086 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_SET_UPPER
*8);
4088 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", asserted
,
4089 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
4090 REG_WR(bp
, reg_addr
, asserted
);
4092 /* now set back the mask */
4093 if (asserted
& ATTN_NIG_FOR_FUNC
) {
4094 /* Verify that IGU ack through BAR was written before restoring
4095 * NIG mask. This loop should exit after 2-3 iterations max.
4097 if (bp
->common
.int_block
!= INT_BLOCK_HC
) {
4098 u32 cnt
= 0, igu_acked
;
4100 igu_acked
= REG_RD(bp
,
4101 IGU_REG_ATTENTION_ACK_BITS
);
4102 } while (((igu_acked
& ATTN_NIG_FOR_FUNC
) == 0) &&
4103 (++cnt
< MAX_IGU_ATTN_ACK_TO
));
4106 "Failed to verify IGU ack on time\n");
4109 REG_WR(bp
, nig_int_mask_addr
, nig_mask
);
4110 bnx2x_release_phy_lock(bp
);
4114 static void bnx2x_fan_failure(struct bnx2x
*bp
)
4116 int port
= BP_PORT(bp
);
4118 /* mark the failure */
4121 dev_info
.port_hw_config
[port
].external_phy_config
);
4123 ext_phy_config
&= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK
;
4124 ext_phy_config
|= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
;
4125 SHMEM_WR(bp
, dev_info
.port_hw_config
[port
].external_phy_config
,
4128 /* log the failure */
4129 netdev_err(bp
->dev
, "Fan Failure on Network Controller has caused the driver to shutdown the card to prevent permanent damage.\n"
4130 "Please contact OEM Support for assistance\n");
4132 /* Schedule device reset (unload)
4133 * This is due to some boards consuming sufficient power when driver is
4134 * up to overheat if fan fails.
4136 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_FAN_FAILURE
, 0);
4139 static void bnx2x_attn_int_deasserted0(struct bnx2x
*bp
, u32 attn
)
4141 int port
= BP_PORT(bp
);
4145 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
4146 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
4148 if (attn
& AEU_INPUTS_ATTN_BITS_SPIO5
) {
4150 val
= REG_RD(bp
, reg_offset
);
4151 val
&= ~AEU_INPUTS_ATTN_BITS_SPIO5
;
4152 REG_WR(bp
, reg_offset
, val
);
4154 BNX2X_ERR("SPIO5 hw attention\n");
4156 /* Fan failure attention */
4157 bnx2x_hw_reset_phy(&bp
->link_params
);
4158 bnx2x_fan_failure(bp
);
4161 if ((attn
& bp
->link_vars
.aeu_int_mask
) && bp
->port
.pmf
) {
4162 bnx2x_acquire_phy_lock(bp
);
4163 bnx2x_handle_module_detect_int(&bp
->link_params
);
4164 bnx2x_release_phy_lock(bp
);
4167 if (attn
& HW_INTERRUT_ASSERT_SET_0
) {
4169 val
= REG_RD(bp
, reg_offset
);
4170 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_0
);
4171 REG_WR(bp
, reg_offset
, val
);
4173 BNX2X_ERR("FATAL HW block attention set0 0x%x\n",
4174 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_0
));
4179 static void bnx2x_attn_int_deasserted1(struct bnx2x
*bp
, u32 attn
)
4183 if (attn
& AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT
) {
4185 val
= REG_RD(bp
, DORQ_REG_DORQ_INT_STS_CLR
);
4186 BNX2X_ERR("DB hw attention 0x%x\n", val
);
4187 /* DORQ discard attention */
4189 BNX2X_ERR("FATAL error from DORQ\n");
4192 if (attn
& HW_INTERRUT_ASSERT_SET_1
) {
4194 int port
= BP_PORT(bp
);
4197 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1
:
4198 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1
);
4200 val
= REG_RD(bp
, reg_offset
);
4201 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_1
);
4202 REG_WR(bp
, reg_offset
, val
);
4204 BNX2X_ERR("FATAL HW block attention set1 0x%x\n",
4205 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_1
));
4210 static void bnx2x_attn_int_deasserted2(struct bnx2x
*bp
, u32 attn
)
4214 if (attn
& AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT
) {
4216 val
= REG_RD(bp
, CFC_REG_CFC_INT_STS_CLR
);
4217 BNX2X_ERR("CFC hw attention 0x%x\n", val
);
4218 /* CFC error attention */
4220 BNX2X_ERR("FATAL error from CFC\n");
4223 if (attn
& AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT
) {
4224 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_0
);
4225 BNX2X_ERR("PXP hw attention-0 0x%x\n", val
);
4226 /* RQ_USDMDP_FIFO_OVERFLOW */
4228 BNX2X_ERR("FATAL error from PXP\n");
4230 if (!CHIP_IS_E1x(bp
)) {
4231 val
= REG_RD(bp
, PXP_REG_PXP_INT_STS_CLR_1
);
4232 BNX2X_ERR("PXP hw attention-1 0x%x\n", val
);
4236 if (attn
& HW_INTERRUT_ASSERT_SET_2
) {
4238 int port
= BP_PORT(bp
);
4241 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2
:
4242 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2
);
4244 val
= REG_RD(bp
, reg_offset
);
4245 val
&= ~(attn
& HW_INTERRUT_ASSERT_SET_2
);
4246 REG_WR(bp
, reg_offset
, val
);
4248 BNX2X_ERR("FATAL HW block attention set2 0x%x\n",
4249 (u32
)(attn
& HW_INTERRUT_ASSERT_SET_2
));
4254 static void bnx2x_attn_int_deasserted3(struct bnx2x
*bp
, u32 attn
)
4258 if (attn
& EVEREST_GEN_ATTN_IN_USE_MASK
) {
4260 if (attn
& BNX2X_PMF_LINK_ASSERT
) {
4261 int func
= BP_FUNC(bp
);
4263 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
4264 bnx2x_read_mf_cfg(bp
);
4265 bp
->mf_config
[BP_VN(bp
)] = MF_CFG_RD(bp
,
4266 func_mf_config
[BP_ABS_FUNC(bp
)].config
);
4268 func_mb
[BP_FW_MB_IDX(bp
)].drv_status
);
4270 if (val
& (DRV_STATUS_DCC_EVENT_MASK
|
4271 DRV_STATUS_OEM_EVENT_MASK
))
4273 (val
& (DRV_STATUS_DCC_EVENT_MASK
|
4274 DRV_STATUS_OEM_EVENT_MASK
)));
4276 if (val
& DRV_STATUS_SET_MF_BW
)
4277 bnx2x_set_mf_bw(bp
);
4279 if (val
& DRV_STATUS_DRV_INFO_REQ
)
4280 bnx2x_handle_drv_info_req(bp
);
4282 if (val
& DRV_STATUS_VF_DISABLED
)
4283 bnx2x_schedule_iov_task(bp
,
4284 BNX2X_IOV_HANDLE_FLR
);
4286 if ((bp
->port
.pmf
== 0) && (val
& DRV_STATUS_PMF
))
4287 bnx2x_pmf_update(bp
);
4290 (val
& DRV_STATUS_DCBX_NEGOTIATION_RESULTS
) &&
4291 bp
->dcbx_enabled
> 0)
4292 /* start dcbx state machine */
4293 bnx2x_dcbx_set_params(bp
,
4294 BNX2X_DCBX_STATE_NEG_RECEIVED
);
4295 if (val
& DRV_STATUS_AFEX_EVENT_MASK
)
4296 bnx2x_handle_afex_cmd(bp
,
4297 val
& DRV_STATUS_AFEX_EVENT_MASK
);
4298 if (val
& DRV_STATUS_EEE_NEGOTIATION_RESULTS
)
4299 bnx2x_handle_eee_event(bp
);
4301 if (val
& DRV_STATUS_OEM_UPDATE_SVID
)
4302 bnx2x_handle_update_svid_cmd(bp
);
4304 if (bp
->link_vars
.periodic_flags
&
4305 PERIODIC_FLAGS_LINK_EVENT
) {
4306 /* sync with link */
4307 bnx2x_acquire_phy_lock(bp
);
4308 bp
->link_vars
.periodic_flags
&=
4309 ~PERIODIC_FLAGS_LINK_EVENT
;
4310 bnx2x_release_phy_lock(bp
);
4312 bnx2x_link_sync_notify(bp
);
4313 bnx2x_link_report(bp
);
4315 /* Always call it here: bnx2x_link_report() will
4316 * prevent the link indication duplication.
4318 bnx2x__link_status_update(bp
);
4319 } else if (attn
& BNX2X_MC_ASSERT_BITS
) {
4321 BNX2X_ERR("MC assert!\n");
4322 bnx2x_mc_assert(bp
);
4323 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_10
, 0);
4324 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_9
, 0);
4325 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_8
, 0);
4326 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_7
, 0);
4329 } else if (attn
& BNX2X_MCP_ASSERT
) {
4331 BNX2X_ERR("MCP assert!\n");
4332 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_11
, 0);
4336 BNX2X_ERR("Unknown HW assert! (attn 0x%x)\n", attn
);
4339 if (attn
& EVEREST_LATCHED_ATTN_IN_USE_MASK
) {
4340 BNX2X_ERR("LATCHED attention 0x%08x (masked)\n", attn
);
4341 if (attn
& BNX2X_GRC_TIMEOUT
) {
4342 val
= CHIP_IS_E1(bp
) ? 0 :
4343 REG_RD(bp
, MISC_REG_GRC_TIMEOUT_ATTN
);
4344 BNX2X_ERR("GRC time-out 0x%08x\n", val
);
4346 if (attn
& BNX2X_GRC_RSV
) {
4347 val
= CHIP_IS_E1(bp
) ? 0 :
4348 REG_RD(bp
, MISC_REG_GRC_RSV_ATTN
);
4349 BNX2X_ERR("GRC reserved 0x%08x\n", val
);
4351 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
, 0x7ff);
4357 * 0-7 - Engine0 load counter.
4358 * 8-15 - Engine1 load counter.
4359 * 16 - Engine0 RESET_IN_PROGRESS bit.
4360 * 17 - Engine1 RESET_IN_PROGRESS bit.
4361 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active function
4363 * 19 - Engine1 ONE_IS_LOADED.
4364 * 20 - Chip reset flow bit. When set none-leader must wait for both engines
4365 * leader to complete (check for both RESET_IN_PROGRESS bits and not for
4366 * just the one belonging to its engine).
4369 #define BNX2X_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1
4371 #define BNX2X_PATH0_LOAD_CNT_MASK 0x000000ff
4372 #define BNX2X_PATH0_LOAD_CNT_SHIFT 0
4373 #define BNX2X_PATH1_LOAD_CNT_MASK 0x0000ff00
4374 #define BNX2X_PATH1_LOAD_CNT_SHIFT 8
4375 #define BNX2X_PATH0_RST_IN_PROG_BIT 0x00010000
4376 #define BNX2X_PATH1_RST_IN_PROG_BIT 0x00020000
4377 #define BNX2X_GLOBAL_RESET_BIT 0x00040000
4380 * Set the GLOBAL_RESET bit.
4382 * Should be run under rtnl lock
4384 void bnx2x_set_reset_global(struct bnx2x
*bp
)
4387 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4388 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4389 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
| BNX2X_GLOBAL_RESET_BIT
);
4390 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4394 * Clear the GLOBAL_RESET bit.
4396 * Should be run under rtnl lock
4398 static void bnx2x_clear_reset_global(struct bnx2x
*bp
)
4401 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4402 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4403 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
& (~BNX2X_GLOBAL_RESET_BIT
));
4404 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4408 * Checks the GLOBAL_RESET bit.
4410 * should be run under rtnl lock
4412 static bool bnx2x_reset_is_global(struct bnx2x
*bp
)
4414 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4416 DP(NETIF_MSG_HW
, "GEN_REG_VAL=0x%08x\n", val
);
4417 return (val
& BNX2X_GLOBAL_RESET_BIT
) ? true : false;
4421 * Clear RESET_IN_PROGRESS bit for the current engine.
4423 * Should be run under rtnl lock
4425 static void bnx2x_set_reset_done(struct bnx2x
*bp
)
4428 u32 bit
= BP_PATH(bp
) ?
4429 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4430 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4431 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4435 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4437 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4441 * Set RESET_IN_PROGRESS for the current engine.
4443 * should be run under rtnl lock
4445 void bnx2x_set_reset_in_progress(struct bnx2x
*bp
)
4448 u32 bit
= BP_PATH(bp
) ?
4449 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4450 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4451 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4455 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4456 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4460 * Checks the RESET_IN_PROGRESS bit for the given engine.
4461 * should be run under rtnl lock
4463 bool bnx2x_reset_is_done(struct bnx2x
*bp
, int engine
)
4465 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4467 BNX2X_PATH1_RST_IN_PROG_BIT
: BNX2X_PATH0_RST_IN_PROG_BIT
;
4469 /* return false if bit is set */
4470 return (val
& bit
) ? false : true;
4474 * set pf load for the current pf.
4476 * should be run under rtnl lock
4478 void bnx2x_set_pf_load(struct bnx2x
*bp
)
4481 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4482 BNX2X_PATH0_LOAD_CNT_MASK
;
4483 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4484 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4486 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4487 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4489 DP(NETIF_MSG_IFUP
, "Old GEN_REG_VAL=0x%08x\n", val
);
4491 /* get the current counter value */
4492 val1
= (val
& mask
) >> shift
;
4494 /* set bit of that PF */
4495 val1
|= (1 << bp
->pf_num
);
4497 /* clear the old value */
4500 /* set the new one */
4501 val
|= ((val1
<< shift
) & mask
);
4503 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4504 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4508 * bnx2x_clear_pf_load - clear pf load mark
4510 * @bp: driver handle
4512 * Should be run under rtnl lock.
4513 * Decrements the load counter for the current engine. Returns
4514 * whether other functions are still loaded
4516 bool bnx2x_clear_pf_load(struct bnx2x
*bp
)
4519 u32 mask
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_MASK
:
4520 BNX2X_PATH0_LOAD_CNT_MASK
;
4521 u32 shift
= BP_PATH(bp
) ? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4522 BNX2X_PATH0_LOAD_CNT_SHIFT
;
4524 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4525 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4526 DP(NETIF_MSG_IFDOWN
, "Old GEN_REG_VAL=0x%08x\n", val
);
4528 /* get the current counter value */
4529 val1
= (val
& mask
) >> shift
;
4531 /* clear bit of that PF */
4532 val1
&= ~(1 << bp
->pf_num
);
4534 /* clear the old value */
4537 /* set the new one */
4538 val
|= ((val1
<< shift
) & mask
);
4540 REG_WR(bp
, BNX2X_RECOVERY_GLOB_REG
, val
);
4541 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RECOVERY_REG
);
4546 * Read the load status for the current engine.
4548 * should be run under rtnl lock
4550 static bool bnx2x_get_load_status(struct bnx2x
*bp
, int engine
)
4552 u32 mask
= (engine
? BNX2X_PATH1_LOAD_CNT_MASK
:
4553 BNX2X_PATH0_LOAD_CNT_MASK
);
4554 u32 shift
= (engine
? BNX2X_PATH1_LOAD_CNT_SHIFT
:
4555 BNX2X_PATH0_LOAD_CNT_SHIFT
);
4556 u32 val
= REG_RD(bp
, BNX2X_RECOVERY_GLOB_REG
);
4558 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "GLOB_REG=0x%08x\n", val
);
4560 val
= (val
& mask
) >> shift
;
4562 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "load mask for engine %d = 0x%x\n",
4568 static void _print_parity(struct bnx2x
*bp
, u32 reg
)
4570 pr_cont(" [0x%08x] ", REG_RD(bp
, reg
));
4573 static void _print_next_block(int idx
, const char *blk
)
4575 pr_cont("%s%s", idx
? ", " : "", blk
);
4578 static bool bnx2x_check_blocks_with_parity0(struct bnx2x
*bp
, u32 sig
,
4579 int *par_num
, bool print
)
4587 for (i
= 0; sig
; i
++) {
4588 cur_bit
= (0x1UL
<< i
);
4589 if (sig
& cur_bit
) {
4590 res
|= true; /* Each bit is real error! */
4594 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR
:
4595 _print_next_block((*par_num
)++, "BRB");
4597 BRB1_REG_BRB1_PRTY_STS
);
4599 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR
:
4600 _print_next_block((*par_num
)++,
4602 _print_parity(bp
, PRS_REG_PRS_PRTY_STS
);
4604 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR
:
4605 _print_next_block((*par_num
)++, "TSDM");
4607 TSDM_REG_TSDM_PRTY_STS
);
4609 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR
:
4610 _print_next_block((*par_num
)++,
4612 _print_parity(bp
, SRC_REG_SRC_PRTY_STS
);
4614 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR
:
4615 _print_next_block((*par_num
)++, "TCM");
4616 _print_parity(bp
, TCM_REG_TCM_PRTY_STS
);
4618 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR
:
4619 _print_next_block((*par_num
)++,
4622 TSEM_REG_TSEM_PRTY_STS_0
);
4624 TSEM_REG_TSEM_PRTY_STS_1
);
4626 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR
:
4627 _print_next_block((*par_num
)++, "XPB");
4628 _print_parity(bp
, GRCBASE_XPB
+
4629 PB_REG_PB_PRTY_STS
);
4642 static bool bnx2x_check_blocks_with_parity1(struct bnx2x
*bp
, u32 sig
,
4643 int *par_num
, bool *global
,
4652 for (i
= 0; sig
; i
++) {
4653 cur_bit
= (0x1UL
<< i
);
4654 if (sig
& cur_bit
) {
4655 res
|= true; /* Each bit is real error! */
4657 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR
:
4659 _print_next_block((*par_num
)++, "PBF");
4660 _print_parity(bp
, PBF_REG_PBF_PRTY_STS
);
4663 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR
:
4665 _print_next_block((*par_num
)++, "QM");
4666 _print_parity(bp
, QM_REG_QM_PRTY_STS
);
4669 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR
:
4671 _print_next_block((*par_num
)++, "TM");
4672 _print_parity(bp
, TM_REG_TM_PRTY_STS
);
4675 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR
:
4677 _print_next_block((*par_num
)++, "XSDM");
4679 XSDM_REG_XSDM_PRTY_STS
);
4682 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR
:
4684 _print_next_block((*par_num
)++, "XCM");
4685 _print_parity(bp
, XCM_REG_XCM_PRTY_STS
);
4688 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR
:
4690 _print_next_block((*par_num
)++,
4693 XSEM_REG_XSEM_PRTY_STS_0
);
4695 XSEM_REG_XSEM_PRTY_STS_1
);
4698 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR
:
4700 _print_next_block((*par_num
)++,
4703 DORQ_REG_DORQ_PRTY_STS
);
4706 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR
:
4708 _print_next_block((*par_num
)++, "NIG");
4709 if (CHIP_IS_E1x(bp
)) {
4711 NIG_REG_NIG_PRTY_STS
);
4714 NIG_REG_NIG_PRTY_STS_0
);
4716 NIG_REG_NIG_PRTY_STS_1
);
4720 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR
:
4722 _print_next_block((*par_num
)++,
4726 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR
:
4728 _print_next_block((*par_num
)++,
4730 _print_parity(bp
, DBG_REG_DBG_PRTY_STS
);
4733 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR
:
4735 _print_next_block((*par_num
)++, "USDM");
4737 USDM_REG_USDM_PRTY_STS
);
4740 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR
:
4742 _print_next_block((*par_num
)++, "UCM");
4743 _print_parity(bp
, UCM_REG_UCM_PRTY_STS
);
4746 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR
:
4748 _print_next_block((*par_num
)++,
4751 USEM_REG_USEM_PRTY_STS_0
);
4753 USEM_REG_USEM_PRTY_STS_1
);
4756 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR
:
4758 _print_next_block((*par_num
)++, "UPB");
4759 _print_parity(bp
, GRCBASE_UPB
+
4760 PB_REG_PB_PRTY_STS
);
4763 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR
:
4765 _print_next_block((*par_num
)++, "CSDM");
4767 CSDM_REG_CSDM_PRTY_STS
);
4770 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR
:
4772 _print_next_block((*par_num
)++, "CCM");
4773 _print_parity(bp
, CCM_REG_CCM_PRTY_STS
);
4786 static bool bnx2x_check_blocks_with_parity2(struct bnx2x
*bp
, u32 sig
,
4787 int *par_num
, bool print
)
4795 for (i
= 0; sig
; i
++) {
4796 cur_bit
= (0x1UL
<< i
);
4797 if (sig
& cur_bit
) {
4798 res
= true; /* Each bit is real error! */
4801 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR
:
4802 _print_next_block((*par_num
)++,
4805 CSEM_REG_CSEM_PRTY_STS_0
);
4807 CSEM_REG_CSEM_PRTY_STS_1
);
4809 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR
:
4810 _print_next_block((*par_num
)++, "PXP");
4811 _print_parity(bp
, PXP_REG_PXP_PRTY_STS
);
4813 PXP2_REG_PXP2_PRTY_STS_0
);
4815 PXP2_REG_PXP2_PRTY_STS_1
);
4817 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
:
4818 _print_next_block((*par_num
)++,
4819 "PXPPCICLOCKCLIENT");
4821 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR
:
4822 _print_next_block((*par_num
)++, "CFC");
4824 CFC_REG_CFC_PRTY_STS
);
4826 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR
:
4827 _print_next_block((*par_num
)++, "CDU");
4828 _print_parity(bp
, CDU_REG_CDU_PRTY_STS
);
4830 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR
:
4831 _print_next_block((*par_num
)++, "DMAE");
4833 DMAE_REG_DMAE_PRTY_STS
);
4835 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR
:
4836 _print_next_block((*par_num
)++, "IGU");
4837 if (CHIP_IS_E1x(bp
))
4839 HC_REG_HC_PRTY_STS
);
4842 IGU_REG_IGU_PRTY_STS
);
4844 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR
:
4845 _print_next_block((*par_num
)++, "MISC");
4847 MISC_REG_MISC_PRTY_STS
);
4860 static bool bnx2x_check_blocks_with_parity3(struct bnx2x
*bp
, u32 sig
,
4861 int *par_num
, bool *global
,
4868 for (i
= 0; sig
; i
++) {
4869 cur_bit
= (0x1UL
<< i
);
4870 if (sig
& cur_bit
) {
4872 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY
:
4874 _print_next_block((*par_num
)++,
4879 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY
:
4881 _print_next_block((*par_num
)++,
4886 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY
:
4888 _print_next_block((*par_num
)++,
4893 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
:
4895 /* clear latched SCPAD PATIRY from MCP */
4896 REG_WR(bp
, MISC_REG_AEU_CLR_LATCH_SIGNAL
,
4909 static bool bnx2x_check_blocks_with_parity4(struct bnx2x
*bp
, u32 sig
,
4910 int *par_num
, bool print
)
4918 for (i
= 0; sig
; i
++) {
4919 cur_bit
= (0x1UL
<< i
);
4920 if (sig
& cur_bit
) {
4921 res
= true; /* Each bit is real error! */
4924 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
:
4925 _print_next_block((*par_num
)++,
4928 PGLUE_B_REG_PGLUE_B_PRTY_STS
);
4930 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
:
4931 _print_next_block((*par_num
)++, "ATC");
4933 ATC_REG_ATC_PRTY_STS
);
4945 static bool bnx2x_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
,
4950 if ((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4951 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4952 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4953 (sig
[3] & HW_PRTY_ASSERT_SET_3
) ||
4954 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) {
4957 DP(NETIF_MSG_HW
, "Was parity error: HW block parity attention:\n"
4958 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n",
4959 sig
[0] & HW_PRTY_ASSERT_SET_0
,
4960 sig
[1] & HW_PRTY_ASSERT_SET_1
,
4961 sig
[2] & HW_PRTY_ASSERT_SET_2
,
4962 sig
[3] & HW_PRTY_ASSERT_SET_3
,
4963 sig
[4] & HW_PRTY_ASSERT_SET_4
);
4965 if (((sig
[0] & HW_PRTY_ASSERT_SET_0
) ||
4966 (sig
[1] & HW_PRTY_ASSERT_SET_1
) ||
4967 (sig
[2] & HW_PRTY_ASSERT_SET_2
) ||
4968 (sig
[4] & HW_PRTY_ASSERT_SET_4
)) ||
4969 (sig
[3] & HW_PRTY_ASSERT_SET_3_WITHOUT_SCPAD
)) {
4971 "Parity errors detected in blocks: ");
4976 res
|= bnx2x_check_blocks_with_parity0(bp
,
4977 sig
[0] & HW_PRTY_ASSERT_SET_0
, &par_num
, print
);
4978 res
|= bnx2x_check_blocks_with_parity1(bp
,
4979 sig
[1] & HW_PRTY_ASSERT_SET_1
, &par_num
, global
, print
);
4980 res
|= bnx2x_check_blocks_with_parity2(bp
,
4981 sig
[2] & HW_PRTY_ASSERT_SET_2
, &par_num
, print
);
4982 res
|= bnx2x_check_blocks_with_parity3(bp
,
4983 sig
[3] & HW_PRTY_ASSERT_SET_3
, &par_num
, global
, print
);
4984 res
|= bnx2x_check_blocks_with_parity4(bp
,
4985 sig
[4] & HW_PRTY_ASSERT_SET_4
, &par_num
, print
);
4995 * bnx2x_chk_parity_attn - checks for parity attentions.
4997 * @bp: driver handle
4998 * @global: true if there was a global attention
4999 * @print: show parity attention in syslog
5001 bool bnx2x_chk_parity_attn(struct bnx2x
*bp
, bool *global
, bool print
)
5003 struct attn_route attn
= { {0} };
5004 int port
= BP_PORT(bp
);
5006 attn
.sig
[0] = REG_RD(bp
,
5007 MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+
5009 attn
.sig
[1] = REG_RD(bp
,
5010 MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+
5012 attn
.sig
[2] = REG_RD(bp
,
5013 MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+
5015 attn
.sig
[3] = REG_RD(bp
,
5016 MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+
5018 /* Since MCP attentions can't be disabled inside the block, we need to
5019 * read AEU registers to see whether they're currently disabled
5021 attn
.sig
[3] &= ((REG_RD(bp
,
5022 !port
? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
5023 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0
) &
5024 MISC_AEU_ENABLE_MCP_PRTY_BITS
) |
5025 ~MISC_AEU_ENABLE_MCP_PRTY_BITS
);
5027 if (!CHIP_IS_E1x(bp
))
5028 attn
.sig
[4] = REG_RD(bp
,
5029 MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+
5032 return bnx2x_parity_attn(bp
, global
, print
, attn
.sig
);
5035 static void bnx2x_attn_int_deasserted4(struct bnx2x
*bp
, u32 attn
)
5038 if (attn
& AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT
) {
5040 val
= REG_RD(bp
, PGLUE_B_REG_PGLUE_B_INT_STS_CLR
);
5041 BNX2X_ERR("PGLUE hw attention 0x%x\n", val
);
5042 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR
)
5043 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n");
5044 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR
)
5045 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n");
5046 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN
)
5047 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n");
5048 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN
)
5049 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n");
5051 PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN
)
5052 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n");
5054 PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN
)
5055 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n");
5056 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN
)
5057 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n");
5058 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN
)
5059 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n");
5060 if (val
& PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW
)
5061 BNX2X_ERR("PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n");
5063 if (attn
& AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT
) {
5064 val
= REG_RD(bp
, ATC_REG_ATC_INT_STS_CLR
);
5065 BNX2X_ERR("ATC hw attention 0x%x\n", val
);
5066 if (val
& ATC_ATC_INT_STS_REG_ADDRESS_ERROR
)
5067 BNX2X_ERR("ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n");
5068 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND
)
5069 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n");
5070 if (val
& ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS
)
5071 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n");
5072 if (val
& ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT
)
5073 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n");
5074 if (val
& ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR
)
5075 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n");
5076 if (val
& ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU
)
5077 BNX2X_ERR("ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n");
5080 if (attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
5081 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)) {
5082 BNX2X_ERR("FATAL parity attention set4 0x%x\n",
5083 (u32
)(attn
& (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR
|
5084 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR
)));
5088 static void bnx2x_attn_int_deasserted(struct bnx2x
*bp
, u32 deasserted
)
5090 struct attn_route attn
, *group_mask
;
5091 int port
= BP_PORT(bp
);
5096 bool global
= false;
5098 /* need to take HW lock because MCP or other port might also
5099 try to handle this event */
5100 bnx2x_acquire_alr(bp
);
5102 if (bnx2x_chk_parity_attn(bp
, &global
, true)) {
5103 #ifndef BNX2X_STOP_ON_ERROR
5104 bp
->recovery_state
= BNX2X_RECOVERY_INIT
;
5105 schedule_delayed_work(&bp
->sp_rtnl_task
, 0);
5106 /* Disable HW interrupts */
5107 bnx2x_int_disable(bp
);
5108 /* In case of parity errors don't handle attentions so that
5109 * other function would "see" parity errors.
5114 bnx2x_release_alr(bp
);
5118 attn
.sig
[0] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ port
*4);
5119 attn
.sig
[1] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0
+ port
*4);
5120 attn
.sig
[2] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0
+ port
*4);
5121 attn
.sig
[3] = REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0
+ port
*4);
5122 if (!CHIP_IS_E1x(bp
))
5124 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0
+ port
*4);
5128 DP(NETIF_MSG_HW
, "attn: %08x %08x %08x %08x %08x\n",
5129 attn
.sig
[0], attn
.sig
[1], attn
.sig
[2], attn
.sig
[3], attn
.sig
[4]);
5131 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
5132 if (deasserted
& (1 << index
)) {
5133 group_mask
= &bp
->attn_group
[index
];
5135 DP(NETIF_MSG_HW
, "group[%d]: %08x %08x %08x %08x %08x\n",
5137 group_mask
->sig
[0], group_mask
->sig
[1],
5138 group_mask
->sig
[2], group_mask
->sig
[3],
5139 group_mask
->sig
[4]);
5141 bnx2x_attn_int_deasserted4(bp
,
5142 attn
.sig
[4] & group_mask
->sig
[4]);
5143 bnx2x_attn_int_deasserted3(bp
,
5144 attn
.sig
[3] & group_mask
->sig
[3]);
5145 bnx2x_attn_int_deasserted1(bp
,
5146 attn
.sig
[1] & group_mask
->sig
[1]);
5147 bnx2x_attn_int_deasserted2(bp
,
5148 attn
.sig
[2] & group_mask
->sig
[2]);
5149 bnx2x_attn_int_deasserted0(bp
,
5150 attn
.sig
[0] & group_mask
->sig
[0]);
5154 bnx2x_release_alr(bp
);
5156 if (bp
->common
.int_block
== INT_BLOCK_HC
)
5157 reg_addr
= (HC_REG_COMMAND_REG
+ port
*32 +
5158 COMMAND_REG_ATTN_BITS_CLR
);
5160 reg_addr
= (BAR_IGU_INTMEM
+ IGU_CMD_ATTN_BIT_CLR_UPPER
*8);
5163 DP(NETIF_MSG_HW
, "about to mask 0x%08x at %s addr 0x%x\n", val
,
5164 (bp
->common
.int_block
== INT_BLOCK_HC
) ? "HC" : "IGU", reg_addr
);
5165 REG_WR(bp
, reg_addr
, val
);
5167 if (~bp
->attn_state
& deasserted
)
5168 BNX2X_ERR("IGU ERROR\n");
5170 reg_addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
5171 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
5173 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
5174 aeu_mask
= REG_RD(bp
, reg_addr
);
5176 DP(NETIF_MSG_HW
, "aeu_mask %x newly deasserted %x\n",
5177 aeu_mask
, deasserted
);
5178 aeu_mask
|= (deasserted
& 0x3ff);
5179 DP(NETIF_MSG_HW
, "new mask %x\n", aeu_mask
);
5181 REG_WR(bp
, reg_addr
, aeu_mask
);
5182 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_PORT0_ATT_MASK
+ port
);
5184 DP(NETIF_MSG_HW
, "attn_state %x\n", bp
->attn_state
);
5185 bp
->attn_state
&= ~deasserted
;
5186 DP(NETIF_MSG_HW
, "new state %x\n", bp
->attn_state
);
5189 static void bnx2x_attn_int(struct bnx2x
*bp
)
5191 /* read local copy of bits */
5192 u32 attn_bits
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
5194 u32 attn_ack
= le32_to_cpu(bp
->def_status_blk
->atten_status_block
.
5196 u32 attn_state
= bp
->attn_state
;
5198 /* look for changed bits */
5199 u32 asserted
= attn_bits
& ~attn_ack
& ~attn_state
;
5200 u32 deasserted
= ~attn_bits
& attn_ack
& attn_state
;
5203 "attn_bits %x attn_ack %x asserted %x deasserted %x\n",
5204 attn_bits
, attn_ack
, asserted
, deasserted
);
5206 if (~(attn_bits
^ attn_ack
) & (attn_bits
^ attn_state
))
5207 BNX2X_ERR("BAD attention state\n");
5209 /* handle bits that were raised */
5211 bnx2x_attn_int_asserted(bp
, asserted
);
5214 bnx2x_attn_int_deasserted(bp
, deasserted
);
5217 void bnx2x_igu_ack_sb(struct bnx2x
*bp
, u8 igu_sb_id
, u8 segment
,
5218 u16 index
, u8 op
, u8 update
)
5220 u32 igu_addr
= bp
->igu_base_addr
;
5221 igu_addr
+= (IGU_CMD_INT_ACK_BASE
+ igu_sb_id
)*8;
5222 bnx2x_igu_ack_sb_gen(bp
, igu_sb_id
, segment
, index
, op
, update
,
5226 static void bnx2x_update_eq_prod(struct bnx2x
*bp
, u16 prod
)
5228 /* No memory barriers */
5229 storm_memset_eq_prod(bp
, prod
, BP_FUNC(bp
));
5230 mmiowb(); /* keep prod updates ordered */
5233 static int bnx2x_cnic_handle_cfc_del(struct bnx2x
*bp
, u32 cid
,
5234 union event_ring_elem
*elem
)
5236 u8 err
= elem
->message
.error
;
5238 if (!bp
->cnic_eth_dev
.starting_cid
||
5239 (cid
< bp
->cnic_eth_dev
.starting_cid
&&
5240 cid
!= bp
->cnic_eth_dev
.iscsi_l2_cid
))
5243 DP(BNX2X_MSG_SP
, "got delete ramrod for CNIC CID %d\n", cid
);
5245 if (unlikely(err
)) {
5247 BNX2X_ERR("got delete ramrod for CNIC CID %d with error!\n",
5249 bnx2x_panic_dump(bp
, false);
5251 bnx2x_cnic_cfc_comp(bp
, cid
, err
);
5255 static void bnx2x_handle_mcast_eqe(struct bnx2x
*bp
)
5257 struct bnx2x_mcast_ramrod_params rparam
;
5260 memset(&rparam
, 0, sizeof(rparam
));
5262 rparam
.mcast_obj
= &bp
->mcast_obj
;
5264 netif_addr_lock_bh(bp
->dev
);
5266 /* Clear pending state for the last command */
5267 bp
->mcast_obj
.raw
.clear_pending(&bp
->mcast_obj
.raw
);
5269 /* If there are pending mcast commands - send them */
5270 if (bp
->mcast_obj
.check_pending(&bp
->mcast_obj
)) {
5271 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_CONT
);
5273 BNX2X_ERR("Failed to send pending mcast commands: %d\n",
5277 netif_addr_unlock_bh(bp
->dev
);
5280 static void bnx2x_handle_classification_eqe(struct bnx2x
*bp
,
5281 union event_ring_elem
*elem
)
5283 unsigned long ramrod_flags
= 0;
5285 u32 echo
= le32_to_cpu(elem
->message
.data
.eth_event
.echo
);
5286 u32 cid
= echo
& BNX2X_SWCID_MASK
;
5287 struct bnx2x_vlan_mac_obj
*vlan_mac_obj
;
5289 /* Always push next commands out, don't wait here */
5290 __set_bit(RAMROD_CONT
, &ramrod_flags
);
5292 switch (echo
>> BNX2X_SWCID_SHIFT
) {
5293 case BNX2X_FILTER_MAC_PENDING
:
5294 DP(BNX2X_MSG_SP
, "Got SETUP_MAC completions\n");
5295 if (CNIC_LOADED(bp
) && (cid
== BNX2X_ISCSI_ETH_CID(bp
)))
5296 vlan_mac_obj
= &bp
->iscsi_l2_mac_obj
;
5298 vlan_mac_obj
= &bp
->sp_objs
[cid
].mac_obj
;
5301 case BNX2X_FILTER_VLAN_PENDING
:
5302 DP(BNX2X_MSG_SP
, "Got SETUP_VLAN completions\n");
5303 vlan_mac_obj
= &bp
->sp_objs
[cid
].vlan_obj
;
5305 case BNX2X_FILTER_MCAST_PENDING
:
5306 DP(BNX2X_MSG_SP
, "Got SETUP_MCAST completions\n");
5307 /* This is only relevant for 57710 where multicast MACs are
5308 * configured as unicast MACs using the same ramrod.
5310 bnx2x_handle_mcast_eqe(bp
);
5313 BNX2X_ERR("Unsupported classification command: 0x%x\n", echo
);
5317 rc
= vlan_mac_obj
->complete(bp
, vlan_mac_obj
, elem
, &ramrod_flags
);
5320 BNX2X_ERR("Failed to schedule new commands: %d\n", rc
);
5322 DP(BNX2X_MSG_SP
, "Scheduled next pending commands...\n");
5325 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
);
5327 static void bnx2x_handle_rx_mode_eqe(struct bnx2x
*bp
)
5329 netif_addr_lock_bh(bp
->dev
);
5331 clear_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
5333 /* Send rx_mode command again if was requested */
5334 if (test_and_clear_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
))
5335 bnx2x_set_storm_rx_mode(bp
);
5336 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
,
5338 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
5339 else if (test_and_clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
,
5341 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
5343 netif_addr_unlock_bh(bp
->dev
);
5346 static void bnx2x_after_afex_vif_lists(struct bnx2x
*bp
,
5347 union event_ring_elem
*elem
)
5349 if (elem
->message
.data
.vif_list_event
.echo
== VIF_LIST_RULE_GET
) {
5351 "afex: ramrod completed VIF LIST_GET, addrs 0x%x\n",
5352 elem
->message
.data
.vif_list_event
.func_bit_map
);
5353 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTGET_ACK
,
5354 elem
->message
.data
.vif_list_event
.func_bit_map
);
5355 } else if (elem
->message
.data
.vif_list_event
.echo
==
5356 VIF_LIST_RULE_SET
) {
5357 DP(BNX2X_MSG_SP
, "afex: ramrod completed VIF LIST_SET\n");
5358 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_LISTSET_ACK
, 0);
5362 /* called with rtnl_lock */
5363 static void bnx2x_after_function_update(struct bnx2x
*bp
)
5366 struct bnx2x_fastpath
*fp
;
5367 struct bnx2x_queue_state_params queue_params
= {NULL
};
5368 struct bnx2x_queue_update_params
*q_update_params
=
5369 &queue_params
.params
.update
;
5371 /* Send Q update command with afex vlan removal values for all Qs */
5372 queue_params
.cmd
= BNX2X_Q_CMD_UPDATE
;
5374 /* set silent vlan removal values according to vlan mode */
5375 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG
,
5376 &q_update_params
->update_flags
);
5377 __set_bit(BNX2X_Q_UPDATE_SILENT_VLAN_REM
,
5378 &q_update_params
->update_flags
);
5379 __set_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
5381 /* in access mode mark mask and value are 0 to strip all vlans */
5382 if (bp
->afex_vlan_mode
== FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE
) {
5383 q_update_params
->silent_removal_value
= 0;
5384 q_update_params
->silent_removal_mask
= 0;
5386 q_update_params
->silent_removal_value
=
5387 (bp
->afex_def_vlan_tag
& VLAN_VID_MASK
);
5388 q_update_params
->silent_removal_mask
= VLAN_VID_MASK
;
5391 for_each_eth_queue(bp
, q
) {
5392 /* Set the appropriate Queue object */
5394 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
5396 /* send the ramrod */
5397 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
5399 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5403 if (!NO_FCOE(bp
) && CNIC_ENABLED(bp
)) {
5404 fp
= &bp
->fp
[FCOE_IDX(bp
)];
5405 queue_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
5407 /* clear pending completion bit */
5408 __clear_bit(RAMROD_COMP_WAIT
, &queue_params
.ramrod_flags
);
5410 /* mark latest Q bit */
5411 smp_mb__before_atomic();
5412 set_bit(BNX2X_AFEX_FCOE_Q_UPDATE_PENDING
, &bp
->sp_state
);
5413 smp_mb__after_atomic();
5415 /* send Q update ramrod for FCoE Q */
5416 rc
= bnx2x_queue_state_change(bp
, &queue_params
);
5418 BNX2X_ERR("Failed to config silent vlan rem for Q %d\n",
5421 /* If no FCoE ring - ACK MCP now */
5422 bnx2x_link_report(bp
);
5423 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
5427 static struct bnx2x_queue_sp_obj
*bnx2x_cid_to_q_obj(
5428 struct bnx2x
*bp
, u32 cid
)
5430 DP(BNX2X_MSG_SP
, "retrieving fp from cid %d\n", cid
);
5432 if (CNIC_LOADED(bp
) && (cid
== BNX2X_FCOE_ETH_CID(bp
)))
5433 return &bnx2x_fcoe_sp_obj(bp
, q_obj
);
5435 return &bp
->sp_objs
[CID_TO_FP(cid
, bp
)].q_obj
;
5438 static void bnx2x_eq_int(struct bnx2x
*bp
)
5440 u16 hw_cons
, sw_cons
, sw_prod
;
5441 union event_ring_elem
*elem
;
5445 int rc
, spqe_cnt
= 0;
5446 struct bnx2x_queue_sp_obj
*q_obj
;
5447 struct bnx2x_func_sp_obj
*f_obj
= &bp
->func_obj
;
5448 struct bnx2x_raw_obj
*rss_raw
= &bp
->rss_conf_obj
.raw
;
5450 hw_cons
= le16_to_cpu(*bp
->eq_cons_sb
);
5452 /* The hw_cos range is 1-255, 257 - the sw_cons range is 0-254, 256.
5453 * when we get the next-page we need to adjust so the loop
5454 * condition below will be met. The next element is the size of a
5455 * regular element and hence incrementing by 1
5457 if ((hw_cons
& EQ_DESC_MAX_PAGE
) == EQ_DESC_MAX_PAGE
)
5460 /* This function may never run in parallel with itself for a
5461 * specific bp, thus there is no need in "paired" read memory
5464 sw_cons
= bp
->eq_cons
;
5465 sw_prod
= bp
->eq_prod
;
5467 DP(BNX2X_MSG_SP
, "EQ: hw_cons %u sw_cons %u bp->eq_spq_left %x\n",
5468 hw_cons
, sw_cons
, atomic_read(&bp
->eq_spq_left
));
5470 for (; sw_cons
!= hw_cons
;
5471 sw_prod
= NEXT_EQ_IDX(sw_prod
), sw_cons
= NEXT_EQ_IDX(sw_cons
)) {
5473 elem
= &bp
->eq_ring
[EQ_DESC(sw_cons
)];
5475 rc
= bnx2x_iov_eq_sp_event(bp
, elem
);
5477 DP(BNX2X_MSG_IOV
, "bnx2x_iov_eq_sp_event returned %d\n",
5482 opcode
= elem
->message
.opcode
;
5484 /* handle eq element */
5486 case EVENT_RING_OPCODE_VF_PF_CHANNEL
:
5487 bnx2x_vf_mbx_schedule(bp
,
5488 &elem
->message
.data
.vf_pf_event
);
5491 case EVENT_RING_OPCODE_STAT_QUERY
:
5492 DP_AND((BNX2X_MSG_SP
| BNX2X_MSG_STATS
),
5493 "got statistics comp event %d\n",
5495 /* nothing to do with stats comp */
5498 case EVENT_RING_OPCODE_CFC_DEL
:
5499 /* handle according to cid range */
5501 * we may want to verify here that the bp state is
5505 /* elem CID originates from FW; actually LE */
5506 cid
= SW_CID(elem
->message
.data
.cfc_del_event
.cid
);
5509 "got delete ramrod for MULTI[%d]\n", cid
);
5511 if (CNIC_LOADED(bp
) &&
5512 !bnx2x_cnic_handle_cfc_del(bp
, cid
, elem
))
5515 q_obj
= bnx2x_cid_to_q_obj(bp
, cid
);
5517 if (q_obj
->complete_cmd(bp
, q_obj
, BNX2X_Q_CMD_CFC_DEL
))
5522 case EVENT_RING_OPCODE_STOP_TRAFFIC
:
5523 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got STOP TRAFFIC\n");
5524 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_PAUSED
);
5525 if (f_obj
->complete_cmd(bp
, f_obj
,
5526 BNX2X_F_CMD_TX_STOP
))
5530 case EVENT_RING_OPCODE_START_TRAFFIC
:
5531 DP(BNX2X_MSG_SP
| BNX2X_MSG_DCB
, "got START TRAFFIC\n");
5532 bnx2x_dcbx_set_params(bp
, BNX2X_DCBX_STATE_TX_RELEASED
);
5533 if (f_obj
->complete_cmd(bp
, f_obj
,
5534 BNX2X_F_CMD_TX_START
))
5538 case EVENT_RING_OPCODE_FUNCTION_UPDATE
:
5539 echo
= elem
->message
.data
.function_update_event
.echo
;
5540 if (echo
== SWITCH_UPDATE
) {
5541 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5542 "got FUNC_SWITCH_UPDATE ramrod\n");
5543 if (f_obj
->complete_cmd(
5544 bp
, f_obj
, BNX2X_F_CMD_SWITCH_UPDATE
))
5548 int cmd
= BNX2X_SP_RTNL_AFEX_F_UPDATE
;
5550 DP(BNX2X_MSG_SP
| BNX2X_MSG_MCP
,
5551 "AFEX: ramrod completed FUNCTION_UPDATE\n");
5552 f_obj
->complete_cmd(bp
, f_obj
,
5553 BNX2X_F_CMD_AFEX_UPDATE
);
5555 /* We will perform the Queues update from
5556 * sp_rtnl task as all Queue SP operations
5557 * should run under rtnl_lock.
5559 bnx2x_schedule_sp_rtnl(bp
, cmd
, 0);
5564 case EVENT_RING_OPCODE_AFEX_VIF_LISTS
:
5565 f_obj
->complete_cmd(bp
, f_obj
,
5566 BNX2X_F_CMD_AFEX_VIFLISTS
);
5567 bnx2x_after_afex_vif_lists(bp
, elem
);
5569 case EVENT_RING_OPCODE_FUNCTION_START
:
5570 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5571 "got FUNC_START ramrod\n");
5572 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_START
))
5577 case EVENT_RING_OPCODE_FUNCTION_STOP
:
5578 DP(BNX2X_MSG_SP
| NETIF_MSG_IFUP
,
5579 "got FUNC_STOP ramrod\n");
5580 if (f_obj
->complete_cmd(bp
, f_obj
, BNX2X_F_CMD_STOP
))
5585 case EVENT_RING_OPCODE_SET_TIMESYNC
:
5586 DP(BNX2X_MSG_SP
| BNX2X_MSG_PTP
,
5587 "got set_timesync ramrod completion\n");
5588 if (f_obj
->complete_cmd(bp
, f_obj
,
5589 BNX2X_F_CMD_SET_TIMESYNC
))
5594 switch (opcode
| bp
->state
) {
5595 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5597 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5598 BNX2X_STATE_OPENING_WAIT4_PORT
):
5599 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES
|
5600 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5601 DP(BNX2X_MSG_SP
, "got RSS_UPDATE ramrod. CID %d\n",
5602 SW_CID(elem
->message
.data
.eth_event
.echo
));
5603 rss_raw
->clear_pending(rss_raw
);
5606 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_OPEN
):
5607 case (EVENT_RING_OPCODE_SET_MAC
| BNX2X_STATE_DIAG
):
5608 case (EVENT_RING_OPCODE_SET_MAC
|
5609 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5610 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5612 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5614 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES
|
5615 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5616 DP(BNX2X_MSG_SP
, "got (un)set vlan/mac ramrod\n");
5617 bnx2x_handle_classification_eqe(bp
, elem
);
5620 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5622 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5624 case (EVENT_RING_OPCODE_MULTICAST_RULES
|
5625 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5626 DP(BNX2X_MSG_SP
, "got mcast ramrod\n");
5627 bnx2x_handle_mcast_eqe(bp
);
5630 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5632 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5634 case (EVENT_RING_OPCODE_FILTERS_RULES
|
5635 BNX2X_STATE_CLOSING_WAIT4_HALT
):
5636 DP(BNX2X_MSG_SP
, "got rx_mode ramrod\n");
5637 bnx2x_handle_rx_mode_eqe(bp
);
5640 /* unknown event log error and continue */
5641 BNX2X_ERR("Unknown EQ event %d, bp->state 0x%x\n",
5642 elem
->message
.opcode
, bp
->state
);
5648 smp_mb__before_atomic();
5649 atomic_add(spqe_cnt
, &bp
->eq_spq_left
);
5651 bp
->eq_cons
= sw_cons
;
5652 bp
->eq_prod
= sw_prod
;
5653 /* Make sure that above mem writes were issued towards the memory */
5656 /* update producer */
5657 bnx2x_update_eq_prod(bp
, bp
->eq_prod
);
5660 static void bnx2x_sp_task(struct work_struct
*work
)
5662 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_task
.work
);
5664 DP(BNX2X_MSG_SP
, "sp task invoked\n");
5666 /* make sure the atomic interrupt_occurred has been written */
5668 if (atomic_read(&bp
->interrupt_occurred
)) {
5670 /* what work needs to be performed? */
5671 u16 status
= bnx2x_update_dsb_idx(bp
);
5673 DP(BNX2X_MSG_SP
, "status %x\n", status
);
5674 DP(BNX2X_MSG_SP
, "setting interrupt_occurred to 0\n");
5675 atomic_set(&bp
->interrupt_occurred
, 0);
5678 if (status
& BNX2X_DEF_SB_ATT_IDX
) {
5680 status
&= ~BNX2X_DEF_SB_ATT_IDX
;
5683 /* SP events: STAT_QUERY and others */
5684 if (status
& BNX2X_DEF_SB_IDX
) {
5685 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
5687 if (FCOE_INIT(bp
) &&
5688 (bnx2x_has_rx_work(fp
) || bnx2x_has_tx_work(fp
))) {
5689 /* Prevent local bottom-halves from running as
5690 * we are going to change the local NAPI list.
5693 napi_schedule(&bnx2x_fcoe(bp
, napi
));
5697 /* Handle EQ completions */
5699 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
,
5700 le16_to_cpu(bp
->def_idx
), IGU_INT_NOP
, 1);
5702 status
&= ~BNX2X_DEF_SB_IDX
;
5705 /* if status is non zero then perhaps something went wrong */
5706 if (unlikely(status
))
5708 "got an unknown interrupt! (status 0x%x)\n", status
);
5710 /* ack status block only if something was actually handled */
5711 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, ATTENTION_ID
,
5712 le16_to_cpu(bp
->def_att_idx
), IGU_INT_ENABLE
, 1);
5715 /* afex - poll to check if VIFSET_ACK should be sent to MFW */
5716 if (test_and_clear_bit(BNX2X_AFEX_PENDING_VIFSET_MCP_ACK
,
5718 bnx2x_link_report(bp
);
5719 bnx2x_fw_command(bp
, DRV_MSG_CODE_AFEX_VIFSET_ACK
, 0);
5723 irqreturn_t
bnx2x_msix_sp_int(int irq
, void *dev_instance
)
5725 struct net_device
*dev
= dev_instance
;
5726 struct bnx2x
*bp
= netdev_priv(dev
);
5728 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0,
5729 IGU_INT_DISABLE
, 0);
5731 #ifdef BNX2X_STOP_ON_ERROR
5732 if (unlikely(bp
->panic
))
5736 if (CNIC_LOADED(bp
)) {
5737 struct cnic_ops
*c_ops
;
5740 c_ops
= rcu_dereference(bp
->cnic_ops
);
5742 c_ops
->cnic_handler(bp
->cnic_data
, NULL
);
5746 /* schedule sp task to perform default status block work, ack
5747 * attentions and enable interrupts.
5749 bnx2x_schedule_sp_task(bp
);
5754 /* end of slow path */
5756 void bnx2x_drv_pulse(struct bnx2x
*bp
)
5758 SHMEM_WR(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_pulse_mb
,
5759 bp
->fw_drv_pulse_wr_seq
);
5762 static void bnx2x_timer(unsigned long data
)
5764 struct bnx2x
*bp
= (struct bnx2x
*) data
;
5766 if (!netif_running(bp
->dev
))
5771 int mb_idx
= BP_FW_MB_IDX(bp
);
5775 ++bp
->fw_drv_pulse_wr_seq
;
5776 bp
->fw_drv_pulse_wr_seq
&= DRV_PULSE_SEQ_MASK
;
5777 drv_pulse
= bp
->fw_drv_pulse_wr_seq
;
5778 bnx2x_drv_pulse(bp
);
5780 mcp_pulse
= (SHMEM_RD(bp
, func_mb
[mb_idx
].mcp_pulse_mb
) &
5781 MCP_PULSE_SEQ_MASK
);
5782 /* The delta between driver pulse and mcp response
5783 * should not get too big. If the MFW is more than 5 pulses
5784 * behind, we should worry about it enough to generate an error
5787 if (((drv_pulse
- mcp_pulse
) & MCP_PULSE_SEQ_MASK
) > 5)
5788 BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
5789 drv_pulse
, mcp_pulse
);
5792 if (bp
->state
== BNX2X_STATE_OPEN
)
5793 bnx2x_stats_handle(bp
, STATS_EVENT_UPDATE
);
5795 /* sample pf vf bulletin board for new posts from pf */
5797 bnx2x_timer_sriov(bp
);
5799 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5802 /* end of Statistics */
5807 * nic init service functions
5810 static void bnx2x_fill(struct bnx2x
*bp
, u32 addr
, int fill
, u32 len
)
5813 if (!(len
%4) && !(addr
%4))
5814 for (i
= 0; i
< len
; i
+= 4)
5815 REG_WR(bp
, addr
+ i
, fill
);
5817 for (i
= 0; i
< len
; i
++)
5818 REG_WR8(bp
, addr
+ i
, fill
);
5821 /* helper: writes FP SP data to FW - data_size in dwords */
5822 static void bnx2x_wr_fp_sb_data(struct bnx2x
*bp
,
5828 for (index
= 0; index
< data_size
; index
++)
5829 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5830 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id
) +
5832 *(sb_data_p
+ index
));
5835 static void bnx2x_zero_fp_sb(struct bnx2x
*bp
, int fw_sb_id
)
5839 struct hc_status_block_data_e2 sb_data_e2
;
5840 struct hc_status_block_data_e1x sb_data_e1x
;
5842 /* disable the function first */
5843 if (!CHIP_IS_E1x(bp
)) {
5844 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5845 sb_data_e2
.common
.state
= SB_DISABLED
;
5846 sb_data_e2
.common
.p_func
.vf_valid
= false;
5847 sb_data_p
= (u32
*)&sb_data_e2
;
5848 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5850 memset(&sb_data_e1x
, 0,
5851 sizeof(struct hc_status_block_data_e1x
));
5852 sb_data_e1x
.common
.state
= SB_DISABLED
;
5853 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5854 sb_data_p
= (u32
*)&sb_data_e1x
;
5855 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5857 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5859 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5860 CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id
), 0,
5861 CSTORM_STATUS_BLOCK_SIZE
);
5862 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5863 CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id
), 0,
5864 CSTORM_SYNC_BLOCK_SIZE
);
5867 /* helper: writes SP SB data to FW */
5868 static void bnx2x_wr_sp_sb_data(struct bnx2x
*bp
,
5869 struct hc_sp_status_block_data
*sp_sb_data
)
5871 int func
= BP_FUNC(bp
);
5873 for (i
= 0; i
< sizeof(struct hc_sp_status_block_data
)/sizeof(u32
); i
++)
5874 REG_WR(bp
, BAR_CSTRORM_INTMEM
+
5875 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(func
) +
5877 *((u32
*)sp_sb_data
+ i
));
5880 static void bnx2x_zero_sp_sb(struct bnx2x
*bp
)
5882 int func
= BP_FUNC(bp
);
5883 struct hc_sp_status_block_data sp_sb_data
;
5884 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
5886 sp_sb_data
.state
= SB_DISABLED
;
5887 sp_sb_data
.p_func
.vf_valid
= false;
5889 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
5891 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5892 CSTORM_SP_STATUS_BLOCK_OFFSET(func
), 0,
5893 CSTORM_SP_STATUS_BLOCK_SIZE
);
5894 bnx2x_fill(bp
, BAR_CSTRORM_INTMEM
+
5895 CSTORM_SP_SYNC_BLOCK_OFFSET(func
), 0,
5896 CSTORM_SP_SYNC_BLOCK_SIZE
);
5899 static void bnx2x_setup_ndsb_state_machine(struct hc_status_block_sm
*hc_sm
,
5900 int igu_sb_id
, int igu_seg_id
)
5902 hc_sm
->igu_sb_id
= igu_sb_id
;
5903 hc_sm
->igu_seg_id
= igu_seg_id
;
5904 hc_sm
->timer_value
= 0xFF;
5905 hc_sm
->time_to_expire
= 0xFFFFFFFF;
5908 /* allocates state machine ids. */
5909 static void bnx2x_map_sb_state_machines(struct hc_index_data
*index_data
)
5911 /* zero out state machine indices */
5913 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5916 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5917 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5918 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5919 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
&= ~HC_INDEX_DATA_SM_ID
;
5923 index_data
[HC_INDEX_ETH_RX_CQ_CONS
].flags
|=
5924 SM_RX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5927 index_data
[HC_INDEX_OOO_TX_CQ_CONS
].flags
|=
5928 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5929 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS0
].flags
|=
5930 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5931 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS1
].flags
|=
5932 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5933 index_data
[HC_INDEX_ETH_TX_CQ_CONS_COS2
].flags
|=
5934 SM_TX_ID
<< HC_INDEX_DATA_SM_ID_SHIFT
;
5937 void bnx2x_init_sb(struct bnx2x
*bp
, dma_addr_t mapping
, int vfid
,
5938 u8 vf_valid
, int fw_sb_id
, int igu_sb_id
)
5942 struct hc_status_block_data_e2 sb_data_e2
;
5943 struct hc_status_block_data_e1x sb_data_e1x
;
5944 struct hc_status_block_sm
*hc_sm_p
;
5948 if (CHIP_INT_MODE_IS_BC(bp
))
5949 igu_seg_id
= HC_SEG_ACCESS_NORM
;
5951 igu_seg_id
= IGU_SEG_ACCESS_NORM
;
5953 bnx2x_zero_fp_sb(bp
, fw_sb_id
);
5955 if (!CHIP_IS_E1x(bp
)) {
5956 memset(&sb_data_e2
, 0, sizeof(struct hc_status_block_data_e2
));
5957 sb_data_e2
.common
.state
= SB_ENABLED
;
5958 sb_data_e2
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5959 sb_data_e2
.common
.p_func
.vf_id
= vfid
;
5960 sb_data_e2
.common
.p_func
.vf_valid
= vf_valid
;
5961 sb_data_e2
.common
.p_func
.vnic_id
= BP_VN(bp
);
5962 sb_data_e2
.common
.same_igu_sb_1b
= true;
5963 sb_data_e2
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5964 sb_data_e2
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5965 hc_sm_p
= sb_data_e2
.common
.state_machine
;
5966 sb_data_p
= (u32
*)&sb_data_e2
;
5967 data_size
= sizeof(struct hc_status_block_data_e2
)/sizeof(u32
);
5968 bnx2x_map_sb_state_machines(sb_data_e2
.index_data
);
5970 memset(&sb_data_e1x
, 0,
5971 sizeof(struct hc_status_block_data_e1x
));
5972 sb_data_e1x
.common
.state
= SB_ENABLED
;
5973 sb_data_e1x
.common
.p_func
.pf_id
= BP_FUNC(bp
);
5974 sb_data_e1x
.common
.p_func
.vf_id
= 0xff;
5975 sb_data_e1x
.common
.p_func
.vf_valid
= false;
5976 sb_data_e1x
.common
.p_func
.vnic_id
= BP_VN(bp
);
5977 sb_data_e1x
.common
.same_igu_sb_1b
= true;
5978 sb_data_e1x
.common
.host_sb_addr
.hi
= U64_HI(mapping
);
5979 sb_data_e1x
.common
.host_sb_addr
.lo
= U64_LO(mapping
);
5980 hc_sm_p
= sb_data_e1x
.common
.state_machine
;
5981 sb_data_p
= (u32
*)&sb_data_e1x
;
5982 data_size
= sizeof(struct hc_status_block_data_e1x
)/sizeof(u32
);
5983 bnx2x_map_sb_state_machines(sb_data_e1x
.index_data
);
5986 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_RX_ID
],
5987 igu_sb_id
, igu_seg_id
);
5988 bnx2x_setup_ndsb_state_machine(&hc_sm_p
[SM_TX_ID
],
5989 igu_sb_id
, igu_seg_id
);
5991 DP(NETIF_MSG_IFUP
, "Init FW SB %d\n", fw_sb_id
);
5993 /* write indices to HW - PCI guarantees endianity of regpairs */
5994 bnx2x_wr_fp_sb_data(bp
, fw_sb_id
, sb_data_p
, data_size
);
5997 static void bnx2x_update_coalesce_sb(struct bnx2x
*bp
, u8 fw_sb_id
,
5998 u16 tx_usec
, u16 rx_usec
)
6000 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
, HC_INDEX_ETH_RX_CQ_CONS
,
6002 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
6003 HC_INDEX_ETH_TX_CQ_CONS_COS0
, false,
6005 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
6006 HC_INDEX_ETH_TX_CQ_CONS_COS1
, false,
6008 bnx2x_update_coalesce_sb_index(bp
, fw_sb_id
,
6009 HC_INDEX_ETH_TX_CQ_CONS_COS2
, false,
6013 static void bnx2x_init_def_sb(struct bnx2x
*bp
)
6015 struct host_sp_status_block
*def_sb
= bp
->def_status_blk
;
6016 dma_addr_t mapping
= bp
->def_status_blk_mapping
;
6017 int igu_sp_sb_index
;
6019 int port
= BP_PORT(bp
);
6020 int func
= BP_FUNC(bp
);
6021 int reg_offset
, reg_offset_en5
;
6024 struct hc_sp_status_block_data sp_sb_data
;
6025 memset(&sp_sb_data
, 0, sizeof(struct hc_sp_status_block_data
));
6027 if (CHIP_INT_MODE_IS_BC(bp
)) {
6028 igu_sp_sb_index
= DEF_SB_IGU_ID
;
6029 igu_seg_id
= HC_SEG_ACCESS_DEF
;
6031 igu_sp_sb_index
= bp
->igu_dsb_id
;
6032 igu_seg_id
= IGU_SEG_ACCESS_DEF
;
6036 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
6037 atten_status_block
);
6038 def_sb
->atten_status_block
.status_block_id
= igu_sp_sb_index
;
6042 reg_offset
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
6043 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
6044 reg_offset_en5
= (port
? MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0
:
6045 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0
);
6046 for (index
= 0; index
< MAX_DYNAMIC_ATTN_GRPS
; index
++) {
6048 /* take care of sig[0]..sig[4] */
6049 for (sindex
= 0; sindex
< 4; sindex
++)
6050 bp
->attn_group
[index
].sig
[sindex
] =
6051 REG_RD(bp
, reg_offset
+ sindex
*0x4 + 0x10*index
);
6053 if (!CHIP_IS_E1x(bp
))
6055 * enable5 is separate from the rest of the registers,
6056 * and therefore the address skip is 4
6057 * and not 16 between the different groups
6059 bp
->attn_group
[index
].sig
[4] = REG_RD(bp
,
6060 reg_offset_en5
+ 0x4*index
);
6062 bp
->attn_group
[index
].sig
[4] = 0;
6065 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
6066 reg_offset
= (port
? HC_REG_ATTN_MSG1_ADDR_L
:
6067 HC_REG_ATTN_MSG0_ADDR_L
);
6069 REG_WR(bp
, reg_offset
, U64_LO(section
));
6070 REG_WR(bp
, reg_offset
+ 4, U64_HI(section
));
6071 } else if (!CHIP_IS_E1x(bp
)) {
6072 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_L
, U64_LO(section
));
6073 REG_WR(bp
, IGU_REG_ATTN_MSG_ADDR_H
, U64_HI(section
));
6076 section
= ((u64
)mapping
) + offsetof(struct host_sp_status_block
,
6079 bnx2x_zero_sp_sb(bp
);
6081 /* PCI guarantees endianity of regpairs */
6082 sp_sb_data
.state
= SB_ENABLED
;
6083 sp_sb_data
.host_sb_addr
.lo
= U64_LO(section
);
6084 sp_sb_data
.host_sb_addr
.hi
= U64_HI(section
);
6085 sp_sb_data
.igu_sb_id
= igu_sp_sb_index
;
6086 sp_sb_data
.igu_seg_id
= igu_seg_id
;
6087 sp_sb_data
.p_func
.pf_id
= func
;
6088 sp_sb_data
.p_func
.vnic_id
= BP_VN(bp
);
6089 sp_sb_data
.p_func
.vf_id
= 0xff;
6091 bnx2x_wr_sp_sb_data(bp
, &sp_sb_data
);
6093 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
, USTORM_ID
, 0, IGU_INT_ENABLE
, 0);
6096 void bnx2x_update_coalesce(struct bnx2x
*bp
)
6100 for_each_eth_queue(bp
, i
)
6101 bnx2x_update_coalesce_sb(bp
, bp
->fp
[i
].fw_sb_id
,
6102 bp
->tx_ticks
, bp
->rx_ticks
);
6105 static void bnx2x_init_sp_ring(struct bnx2x
*bp
)
6107 spin_lock_init(&bp
->spq_lock
);
6108 atomic_set(&bp
->cq_spq_left
, MAX_SPQ_PENDING
);
6110 bp
->spq_prod_idx
= 0;
6111 bp
->dsb_sp_prod
= BNX2X_SP_DSB_INDEX
;
6112 bp
->spq_prod_bd
= bp
->spq
;
6113 bp
->spq_last_bd
= bp
->spq_prod_bd
+ MAX_SP_DESC_CNT
;
6116 static void bnx2x_init_eq_ring(struct bnx2x
*bp
)
6119 for (i
= 1; i
<= NUM_EQ_PAGES
; i
++) {
6120 union event_ring_elem
*elem
=
6121 &bp
->eq_ring
[EQ_DESC_CNT_PAGE
* i
- 1];
6123 elem
->next_page
.addr
.hi
=
6124 cpu_to_le32(U64_HI(bp
->eq_mapping
+
6125 BCM_PAGE_SIZE
* (i
% NUM_EQ_PAGES
)));
6126 elem
->next_page
.addr
.lo
=
6127 cpu_to_le32(U64_LO(bp
->eq_mapping
+
6128 BCM_PAGE_SIZE
*(i
% NUM_EQ_PAGES
)));
6131 bp
->eq_prod
= NUM_EQ_DESC
;
6132 bp
->eq_cons_sb
= BNX2X_EQ_INDEX
;
6133 /* we want a warning message before it gets wrought... */
6134 atomic_set(&bp
->eq_spq_left
,
6135 min_t(int, MAX_SP_DESC_CNT
- MAX_SPQ_PENDING
, NUM_EQ_DESC
) - 1);
6138 /* called with netif_addr_lock_bh() */
6139 static int bnx2x_set_q_rx_mode(struct bnx2x
*bp
, u8 cl_id
,
6140 unsigned long rx_mode_flags
,
6141 unsigned long rx_accept_flags
,
6142 unsigned long tx_accept_flags
,
6143 unsigned long ramrod_flags
)
6145 struct bnx2x_rx_mode_ramrod_params ramrod_param
;
6148 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
6150 /* Prepare ramrod parameters */
6151 ramrod_param
.cid
= 0;
6152 ramrod_param
.cl_id
= cl_id
;
6153 ramrod_param
.rx_mode_obj
= &bp
->rx_mode_obj
;
6154 ramrod_param
.func_id
= BP_FUNC(bp
);
6156 ramrod_param
.pstate
= &bp
->sp_state
;
6157 ramrod_param
.state
= BNX2X_FILTER_RX_MODE_PENDING
;
6159 ramrod_param
.rdata
= bnx2x_sp(bp
, rx_mode_rdata
);
6160 ramrod_param
.rdata_mapping
= bnx2x_sp_mapping(bp
, rx_mode_rdata
);
6162 set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
);
6164 ramrod_param
.ramrod_flags
= ramrod_flags
;
6165 ramrod_param
.rx_mode_flags
= rx_mode_flags
;
6167 ramrod_param
.rx_accept_flags
= rx_accept_flags
;
6168 ramrod_param
.tx_accept_flags
= tx_accept_flags
;
6170 rc
= bnx2x_config_rx_mode(bp
, &ramrod_param
);
6172 BNX2X_ERR("Set rx_mode %d failed\n", bp
->rx_mode
);
6179 static int bnx2x_fill_accept_flags(struct bnx2x
*bp
, u32 rx_mode
,
6180 unsigned long *rx_accept_flags
,
6181 unsigned long *tx_accept_flags
)
6183 /* Clear the flags first */
6184 *rx_accept_flags
= 0;
6185 *tx_accept_flags
= 0;
6188 case BNX2X_RX_MODE_NONE
:
6190 * 'drop all' supersedes any accept flags that may have been
6191 * passed to the function.
6194 case BNX2X_RX_MODE_NORMAL
:
6195 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
6196 __set_bit(BNX2X_ACCEPT_MULTICAST
, rx_accept_flags
);
6197 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
6199 /* internal switching mode */
6200 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
6201 __set_bit(BNX2X_ACCEPT_MULTICAST
, tx_accept_flags
);
6202 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
6204 if (bp
->accept_any_vlan
) {
6205 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
6206 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
6210 case BNX2X_RX_MODE_ALLMULTI
:
6211 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
6212 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, rx_accept_flags
);
6213 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
6215 /* internal switching mode */
6216 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
6217 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, tx_accept_flags
);
6218 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
6220 if (bp
->accept_any_vlan
) {
6221 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
6222 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
6226 case BNX2X_RX_MODE_PROMISC
:
6227 /* According to definition of SI mode, iface in promisc mode
6228 * should receive matched and unmatched (in resolution of port)
6231 __set_bit(BNX2X_ACCEPT_UNMATCHED
, rx_accept_flags
);
6232 __set_bit(BNX2X_ACCEPT_UNICAST
, rx_accept_flags
);
6233 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, rx_accept_flags
);
6234 __set_bit(BNX2X_ACCEPT_BROADCAST
, rx_accept_flags
);
6236 /* internal switching mode */
6237 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, tx_accept_flags
);
6238 __set_bit(BNX2X_ACCEPT_BROADCAST
, tx_accept_flags
);
6241 __set_bit(BNX2X_ACCEPT_ALL_UNICAST
, tx_accept_flags
);
6243 __set_bit(BNX2X_ACCEPT_UNICAST
, tx_accept_flags
);
6245 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, rx_accept_flags
);
6246 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, tx_accept_flags
);
6250 BNX2X_ERR("Unknown rx_mode: %d\n", rx_mode
);
6257 /* called with netif_addr_lock_bh() */
6258 static int bnx2x_set_storm_rx_mode(struct bnx2x
*bp
)
6260 unsigned long rx_mode_flags
= 0, ramrod_flags
= 0;
6261 unsigned long rx_accept_flags
= 0, tx_accept_flags
= 0;
6265 /* Configure rx_mode of FCoE Queue */
6266 __set_bit(BNX2X_RX_MODE_FCOE_ETH
, &rx_mode_flags
);
6268 rc
= bnx2x_fill_accept_flags(bp
, bp
->rx_mode
, &rx_accept_flags
,
6273 __set_bit(RAMROD_RX
, &ramrod_flags
);
6274 __set_bit(RAMROD_TX
, &ramrod_flags
);
6276 return bnx2x_set_q_rx_mode(bp
, bp
->fp
->cl_id
, rx_mode_flags
,
6277 rx_accept_flags
, tx_accept_flags
,
6281 static void bnx2x_init_internal_common(struct bnx2x
*bp
)
6285 /* Zero this manually as its initialization is
6286 currently missing in the initTool */
6287 for (i
= 0; i
< (USTORM_AGG_DATA_SIZE
>> 2); i
++)
6288 REG_WR(bp
, BAR_USTRORM_INTMEM
+
6289 USTORM_AGG_DATA_OFFSET
+ i
* 4, 0);
6290 if (!CHIP_IS_E1x(bp
)) {
6291 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_IGU_MODE_OFFSET
,
6292 CHIP_INT_MODE_IS_BC(bp
) ?
6293 HC_IGU_BC_MODE
: HC_IGU_NBC_MODE
);
6297 static void bnx2x_init_internal(struct bnx2x
*bp
, u32 load_code
)
6299 switch (load_code
) {
6300 case FW_MSG_CODE_DRV_LOAD_COMMON
:
6301 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
:
6302 bnx2x_init_internal_common(bp
);
6305 case FW_MSG_CODE_DRV_LOAD_PORT
:
6309 case FW_MSG_CODE_DRV_LOAD_FUNCTION
:
6310 /* internal memory per function is
6311 initialized inside bnx2x_pf_init */
6315 BNX2X_ERR("Unknown load_code (0x%x) from MCP\n", load_code
);
6320 static inline u8
bnx2x_fp_igu_sb_id(struct bnx2x_fastpath
*fp
)
6322 return fp
->bp
->igu_base_sb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
6325 static inline u8
bnx2x_fp_fw_sb_id(struct bnx2x_fastpath
*fp
)
6327 return fp
->bp
->base_fw_ndsb
+ fp
->index
+ CNIC_SUPPORT(fp
->bp
);
6330 static u8
bnx2x_fp_cl_id(struct bnx2x_fastpath
*fp
)
6332 if (CHIP_IS_E1x(fp
->bp
))
6333 return BP_L_ID(fp
->bp
) + fp
->index
;
6334 else /* We want Client ID to be the same as IGU SB ID for 57712 */
6335 return bnx2x_fp_igu_sb_id(fp
);
6338 static void bnx2x_init_eth_fp(struct bnx2x
*bp
, int fp_idx
)
6340 struct bnx2x_fastpath
*fp
= &bp
->fp
[fp_idx
];
6342 unsigned long q_type
= 0;
6343 u32 cids
[BNX2X_MULTI_TX_COS
] = { 0 };
6344 fp
->rx_queue
= fp_idx
;
6346 fp
->cl_id
= bnx2x_fp_cl_id(fp
);
6347 fp
->fw_sb_id
= bnx2x_fp_fw_sb_id(fp
);
6348 fp
->igu_sb_id
= bnx2x_fp_igu_sb_id(fp
);
6349 /* qZone id equals to FW (per path) client id */
6350 fp
->cl_qzone_id
= bnx2x_fp_qzone_id(fp
);
6353 fp
->ustorm_rx_prods_offset
= bnx2x_rx_ustorm_prods_offset(fp
);
6355 /* Setup SB indices */
6356 fp
->rx_cons_sb
= BNX2X_RX_SB_INDEX
;
6358 /* Configure Queue State object */
6359 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
6360 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
6362 BUG_ON(fp
->max_cos
> BNX2X_MULTI_TX_COS
);
6365 for_each_cos_in_tx_queue(fp
, cos
) {
6366 bnx2x_init_txdata(bp
, fp
->txdata_ptr
[cos
],
6367 CID_COS_TO_TX_ONLY_CID(fp
->cid
, cos
, bp
),
6368 FP_COS_TO_TXQ(fp
, cos
, bp
),
6369 BNX2X_TX_SB_INDEX_BASE
+ cos
, fp
);
6370 cids
[cos
] = fp
->txdata_ptr
[cos
]->cid
;
6373 /* nothing more for vf to do here */
6377 bnx2x_init_sb(bp
, fp
->status_blk_mapping
, BNX2X_VF_ID_INVALID
, false,
6378 fp
->fw_sb_id
, fp
->igu_sb_id
);
6379 bnx2x_update_fpsb_idx(fp
);
6380 bnx2x_init_queue_obj(bp
, &bnx2x_sp_obj(bp
, fp
).q_obj
, fp
->cl_id
, cids
,
6381 fp
->max_cos
, BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
6382 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
6385 * Configure classification DBs: Always enable Tx switching
6387 bnx2x_init_vlan_mac_fp_objs(fp
, BNX2X_OBJ_TYPE_RX_TX
);
6390 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6391 fp_idx
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
6395 static void bnx2x_init_tx_ring_one(struct bnx2x_fp_txdata
*txdata
)
6399 for (i
= 1; i
<= NUM_TX_RINGS
; i
++) {
6400 struct eth_tx_next_bd
*tx_next_bd
=
6401 &txdata
->tx_desc_ring
[TX_DESC_CNT
* i
- 1].next_bd
;
6403 tx_next_bd
->addr_hi
=
6404 cpu_to_le32(U64_HI(txdata
->tx_desc_mapping
+
6405 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
6406 tx_next_bd
->addr_lo
=
6407 cpu_to_le32(U64_LO(txdata
->tx_desc_mapping
+
6408 BCM_PAGE_SIZE
*(i
% NUM_TX_RINGS
)));
6411 *txdata
->tx_cons_sb
= cpu_to_le16(0);
6413 SET_FLAG(txdata
->tx_db
.data
.header
.header
, DOORBELL_HDR_DB_TYPE
, 1);
6414 txdata
->tx_db
.data
.zero_fill1
= 0;
6415 txdata
->tx_db
.data
.prod
= 0;
6417 txdata
->tx_pkt_prod
= 0;
6418 txdata
->tx_pkt_cons
= 0;
6419 txdata
->tx_bd_prod
= 0;
6420 txdata
->tx_bd_cons
= 0;
6424 static void bnx2x_init_tx_rings_cnic(struct bnx2x
*bp
)
6428 for_each_tx_queue_cnic(bp
, i
)
6429 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[0]);
6432 static void bnx2x_init_tx_rings(struct bnx2x
*bp
)
6437 for_each_eth_queue(bp
, i
)
6438 for_each_cos_in_tx_queue(&bp
->fp
[i
], cos
)
6439 bnx2x_init_tx_ring_one(bp
->fp
[i
].txdata_ptr
[cos
]);
6442 static void bnx2x_init_fcoe_fp(struct bnx2x
*bp
)
6444 struct bnx2x_fastpath
*fp
= bnx2x_fcoe_fp(bp
);
6445 unsigned long q_type
= 0;
6447 bnx2x_fcoe(bp
, rx_queue
) = BNX2X_NUM_ETH_QUEUES(bp
);
6448 bnx2x_fcoe(bp
, cl_id
) = bnx2x_cnic_eth_cl_id(bp
,
6449 BNX2X_FCOE_ETH_CL_ID_IDX
);
6450 bnx2x_fcoe(bp
, cid
) = BNX2X_FCOE_ETH_CID(bp
);
6451 bnx2x_fcoe(bp
, fw_sb_id
) = DEF_SB_ID
;
6452 bnx2x_fcoe(bp
, igu_sb_id
) = bp
->igu_dsb_id
;
6453 bnx2x_fcoe(bp
, rx_cons_sb
) = BNX2X_FCOE_L2_RX_INDEX
;
6454 bnx2x_init_txdata(bp
, bnx2x_fcoe(bp
, txdata_ptr
[0]),
6455 fp
->cid
, FCOE_TXQ_IDX(bp
), BNX2X_FCOE_L2_TX_INDEX
,
6458 DP(NETIF_MSG_IFUP
, "created fcoe tx data (fp index %d)\n", fp
->index
);
6460 /* qZone id equals to FW (per path) client id */
6461 bnx2x_fcoe(bp
, cl_qzone_id
) = bnx2x_fp_qzone_id(fp
);
6463 bnx2x_fcoe(bp
, ustorm_rx_prods_offset
) =
6464 bnx2x_rx_ustorm_prods_offset(fp
);
6466 /* Configure Queue State object */
6467 __set_bit(BNX2X_Q_TYPE_HAS_RX
, &q_type
);
6468 __set_bit(BNX2X_Q_TYPE_HAS_TX
, &q_type
);
6470 /* No multi-CoS for FCoE L2 client */
6471 BUG_ON(fp
->max_cos
!= 1);
6473 bnx2x_init_queue_obj(bp
, &bnx2x_sp_obj(bp
, fp
).q_obj
, fp
->cl_id
,
6474 &fp
->cid
, 1, BP_FUNC(bp
), bnx2x_sp(bp
, q_rdata
),
6475 bnx2x_sp_mapping(bp
, q_rdata
), q_type
);
6478 "queue[%d]: bnx2x_init_sb(%p,%p) cl_id %d fw_sb %d igu_sb %d\n",
6479 fp
->index
, bp
, fp
->status_blk
.e2_sb
, fp
->cl_id
, fp
->fw_sb_id
,
6483 void bnx2x_nic_init_cnic(struct bnx2x
*bp
)
6486 bnx2x_init_fcoe_fp(bp
);
6488 bnx2x_init_sb(bp
, bp
->cnic_sb_mapping
,
6489 BNX2X_VF_ID_INVALID
, false,
6490 bnx2x_cnic_fw_sb_id(bp
), bnx2x_cnic_igu_sb_id(bp
));
6492 /* ensure status block indices were read */
6494 bnx2x_init_rx_rings_cnic(bp
);
6495 bnx2x_init_tx_rings_cnic(bp
);
6502 void bnx2x_pre_irq_nic_init(struct bnx2x
*bp
)
6506 /* Setup NIC internals and enable interrupts */
6507 for_each_eth_queue(bp
, i
)
6508 bnx2x_init_eth_fp(bp
, i
);
6510 /* ensure status block indices were read */
6512 bnx2x_init_rx_rings(bp
);
6513 bnx2x_init_tx_rings(bp
);
6516 /* Initialize MOD_ABS interrupts */
6517 bnx2x_init_mod_abs_int(bp
, &bp
->link_vars
, bp
->common
.chip_id
,
6518 bp
->common
.shmem_base
,
6519 bp
->common
.shmem2_base
, BP_PORT(bp
));
6521 /* initialize the default status block and sp ring */
6522 bnx2x_init_def_sb(bp
);
6523 bnx2x_update_dsb_idx(bp
);
6524 bnx2x_init_sp_ring(bp
);
6526 bnx2x_memset_stats(bp
);
6530 void bnx2x_post_irq_nic_init(struct bnx2x
*bp
, u32 load_code
)
6532 bnx2x_init_eq_ring(bp
);
6533 bnx2x_init_internal(bp
, load_code
);
6535 bnx2x_stats_init(bp
);
6537 /* flush all before enabling interrupts */
6541 bnx2x_int_enable(bp
);
6543 /* Check for SPIO5 */
6544 bnx2x_attn_int_deasserted0(bp
,
6545 REG_RD(bp
, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0
+ BP_PORT(bp
)*4) &
6546 AEU_INPUTS_ATTN_BITS_SPIO5
);
6549 /* gzip service functions */
6550 static int bnx2x_gunzip_init(struct bnx2x
*bp
)
6552 bp
->gunzip_buf
= dma_alloc_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
,
6553 &bp
->gunzip_mapping
, GFP_KERNEL
);
6554 if (bp
->gunzip_buf
== NULL
)
6557 bp
->strm
= kmalloc(sizeof(*bp
->strm
), GFP_KERNEL
);
6558 if (bp
->strm
== NULL
)
6561 bp
->strm
->workspace
= vmalloc(zlib_inflate_workspacesize());
6562 if (bp
->strm
->workspace
== NULL
)
6572 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6573 bp
->gunzip_mapping
);
6574 bp
->gunzip_buf
= NULL
;
6577 BNX2X_ERR("Cannot allocate firmware buffer for un-compression\n");
6581 static void bnx2x_gunzip_end(struct bnx2x
*bp
)
6584 vfree(bp
->strm
->workspace
);
6589 if (bp
->gunzip_buf
) {
6590 dma_free_coherent(&bp
->pdev
->dev
, FW_BUF_SIZE
, bp
->gunzip_buf
,
6591 bp
->gunzip_mapping
);
6592 bp
->gunzip_buf
= NULL
;
6596 static int bnx2x_gunzip(struct bnx2x
*bp
, const u8
*zbuf
, int len
)
6600 /* check gzip header */
6601 if ((zbuf
[0] != 0x1f) || (zbuf
[1] != 0x8b) || (zbuf
[2] != Z_DEFLATED
)) {
6602 BNX2X_ERR("Bad gzip header\n");
6610 if (zbuf
[3] & FNAME
)
6611 while ((zbuf
[n
++] != 0) && (n
< len
));
6613 bp
->strm
->next_in
= (typeof(bp
->strm
->next_in
))zbuf
+ n
;
6614 bp
->strm
->avail_in
= len
- n
;
6615 bp
->strm
->next_out
= bp
->gunzip_buf
;
6616 bp
->strm
->avail_out
= FW_BUF_SIZE
;
6618 rc
= zlib_inflateInit2(bp
->strm
, -MAX_WBITS
);
6622 rc
= zlib_inflate(bp
->strm
, Z_FINISH
);
6623 if ((rc
!= Z_OK
) && (rc
!= Z_STREAM_END
))
6624 netdev_err(bp
->dev
, "Firmware decompression error: %s\n",
6627 bp
->gunzip_outlen
= (FW_BUF_SIZE
- bp
->strm
->avail_out
);
6628 if (bp
->gunzip_outlen
& 0x3)
6630 "Firmware decompression error: gunzip_outlen (%d) not aligned\n",
6632 bp
->gunzip_outlen
>>= 2;
6634 zlib_inflateEnd(bp
->strm
);
6636 if (rc
== Z_STREAM_END
)
6642 /* nic load/unload */
6645 * General service functions
6648 /* send a NIG loopback debug packet */
6649 static void bnx2x_lb_pckt(struct bnx2x
*bp
)
6653 /* Ethernet source and destination addresses */
6654 wb_write
[0] = 0x55555555;
6655 wb_write
[1] = 0x55555555;
6656 wb_write
[2] = 0x20; /* SOP */
6657 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6659 /* NON-IP protocol */
6660 wb_write
[0] = 0x09000000;
6661 wb_write
[1] = 0x55555555;
6662 wb_write
[2] = 0x10; /* EOP, eop_bvalid = 0 */
6663 REG_WR_DMAE(bp
, NIG_REG_DEBUG_PACKET_LB
, wb_write
, 3);
6666 /* some of the internal memories
6667 * are not directly readable from the driver
6668 * to test them we send debug packets
6670 static int bnx2x_int_mem_test(struct bnx2x
*bp
)
6676 if (CHIP_REV_IS_FPGA(bp
))
6678 else if (CHIP_REV_IS_EMUL(bp
))
6683 /* Disable inputs of parser neighbor blocks */
6684 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6685 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6686 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6687 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6689 /* Write 0 to parser credits for CFC search request */
6690 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6692 /* send Ethernet packet */
6695 /* TODO do i reset NIG statistic? */
6696 /* Wait until NIG register shows 1 packet of size 0x10 */
6697 count
= 1000 * factor
;
6700 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6701 val
= *bnx2x_sp(bp
, wb_data
[0]);
6705 usleep_range(10000, 20000);
6709 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6713 /* Wait until PRS register shows 1 packet */
6714 count
= 1000 * factor
;
6716 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6720 usleep_range(10000, 20000);
6724 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6728 /* Reset and init BRB, PRS */
6729 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6731 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6733 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6734 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6736 DP(NETIF_MSG_HW
, "part2\n");
6738 /* Disable inputs of parser neighbor blocks */
6739 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x0);
6740 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x0);
6741 REG_WR(bp
, CFC_REG_DEBUG0
, 0x1);
6742 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x0);
6744 /* Write 0 to parser credits for CFC search request */
6745 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x0);
6747 /* send 10 Ethernet packets */
6748 for (i
= 0; i
< 10; i
++)
6751 /* Wait until NIG register shows 10 + 1
6752 packets of size 11*0x10 = 0xb0 */
6753 count
= 1000 * factor
;
6756 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
6757 val
= *bnx2x_sp(bp
, wb_data
[0]);
6761 usleep_range(10000, 20000);
6765 BNX2X_ERR("NIG timeout val = 0x%x\n", val
);
6769 /* Wait until PRS register shows 2 packets */
6770 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6772 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6774 /* Write 1 to parser credits for CFC search request */
6775 REG_WR(bp
, PRS_REG_CFC_SEARCH_INITIAL_CREDIT
, 0x1);
6777 /* Wait until PRS register shows 3 packets */
6778 msleep(10 * factor
);
6779 /* Wait until NIG register shows 1 packet of size 0x10 */
6780 val
= REG_RD(bp
, PRS_REG_NUM_OF_PACKETS
);
6782 BNX2X_ERR("PRS timeout val = 0x%x\n", val
);
6784 /* clear NIG EOP FIFO */
6785 for (i
= 0; i
< 11; i
++)
6786 REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_FIFO
);
6787 val
= REG_RD(bp
, NIG_REG_INGRESS_EOP_LB_EMPTY
);
6789 BNX2X_ERR("clear of NIG failed\n");
6793 /* Reset and init BRB, PRS, NIG */
6794 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
, 0x03);
6796 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0x03);
6798 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
6799 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
6800 if (!CNIC_SUPPORT(bp
))
6802 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
6804 /* Enable inputs of parser neighbor blocks */
6805 REG_WR(bp
, TSDM_REG_ENABLE_IN1
, 0x7fffffff);
6806 REG_WR(bp
, TCM_REG_PRS_IFEN
, 0x1);
6807 REG_WR(bp
, CFC_REG_DEBUG0
, 0x0);
6808 REG_WR(bp
, NIG_REG_PRS_REQ_IN_EN
, 0x1);
6810 DP(NETIF_MSG_HW
, "done\n");
6815 static void bnx2x_enable_blocks_attention(struct bnx2x
*bp
)
6819 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
6820 if (!CHIP_IS_E1x(bp
))
6821 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0x40);
6823 REG_WR(bp
, PXP_REG_PXP_INT_MASK_1
, 0);
6824 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
6825 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
6827 * mask read length error interrupts in brb for parser
6828 * (parsing unit and 'checksum and crc' unit)
6829 * these errors are legal (PU reads fixed length and CAC can cause
6830 * read length error on truncated packets)
6832 REG_WR(bp
, BRB1_REG_BRB1_INT_MASK
, 0xFC00);
6833 REG_WR(bp
, QM_REG_QM_INT_MASK
, 0);
6834 REG_WR(bp
, TM_REG_TM_INT_MASK
, 0);
6835 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_0
, 0);
6836 REG_WR(bp
, XSDM_REG_XSDM_INT_MASK_1
, 0);
6837 REG_WR(bp
, XCM_REG_XCM_INT_MASK
, 0);
6838 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_0, 0); */
6839 /* REG_WR(bp, XSEM_REG_XSEM_INT_MASK_1, 0); */
6840 REG_WR(bp
, USDM_REG_USDM_INT_MASK_0
, 0);
6841 REG_WR(bp
, USDM_REG_USDM_INT_MASK_1
, 0);
6842 REG_WR(bp
, UCM_REG_UCM_INT_MASK
, 0);
6843 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_0, 0); */
6844 /* REG_WR(bp, USEM_REG_USEM_INT_MASK_1, 0); */
6845 REG_WR(bp
, GRCBASE_UPB
+ PB_REG_PB_INT_MASK
, 0);
6846 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_0
, 0);
6847 REG_WR(bp
, CSDM_REG_CSDM_INT_MASK_1
, 0);
6848 REG_WR(bp
, CCM_REG_CCM_INT_MASK
, 0);
6849 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_0, 0); */
6850 /* REG_WR(bp, CSEM_REG_CSEM_INT_MASK_1, 0); */
6852 val
= PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT
|
6853 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF
|
6854 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN
;
6855 if (!CHIP_IS_E1x(bp
))
6856 val
|= PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED
|
6857 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED
;
6858 REG_WR(bp
, PXP2_REG_PXP2_INT_MASK_0
, val
);
6860 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_0
, 0);
6861 REG_WR(bp
, TSDM_REG_TSDM_INT_MASK_1
, 0);
6862 REG_WR(bp
, TCM_REG_TCM_INT_MASK
, 0);
6863 /* REG_WR(bp, TSEM_REG_TSEM_INT_MASK_0, 0); */
6865 if (!CHIP_IS_E1x(bp
))
6866 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */
6867 REG_WR(bp
, TSEM_REG_TSEM_INT_MASK_1
, 0x07ff);
6869 REG_WR(bp
, CDU_REG_CDU_INT_MASK
, 0);
6870 REG_WR(bp
, DMAE_REG_DMAE_INT_MASK
, 0);
6871 /* REG_WR(bp, MISC_REG_MISC_INT_MASK, 0); */
6872 REG_WR(bp
, PBF_REG_PBF_INT_MASK
, 0x18); /* bit 3,4 masked */
6875 static void bnx2x_reset_common(struct bnx2x
*bp
)
6880 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
6883 if (CHIP_IS_E3(bp
)) {
6884 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
6885 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
6888 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
, val
);
6891 static void bnx2x_setup_dmae(struct bnx2x
*bp
)
6894 spin_lock_init(&bp
->dmae_lock
);
6897 static void bnx2x_init_pxp(struct bnx2x
*bp
)
6900 int r_order
, w_order
;
6902 pcie_capability_read_word(bp
->pdev
, PCI_EXP_DEVCTL
, &devctl
);
6903 DP(NETIF_MSG_HW
, "read 0x%x from devctl\n", devctl
);
6904 w_order
= ((devctl
& PCI_EXP_DEVCTL_PAYLOAD
) >> 5);
6906 r_order
= ((devctl
& PCI_EXP_DEVCTL_READRQ
) >> 12);
6908 DP(NETIF_MSG_HW
, "force read order to %d\n", bp
->mrrs
);
6912 bnx2x_init_pxp_arb(bp
, r_order
, w_order
);
6915 static void bnx2x_setup_fan_failure_detection(struct bnx2x
*bp
)
6925 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config2
) &
6926 SHARED_HW_CFG_FAN_FAILURE_MASK
;
6928 if (val
== SHARED_HW_CFG_FAN_FAILURE_ENABLED
)
6932 * The fan failure mechanism is usually related to the PHY type since
6933 * the power consumption of the board is affected by the PHY. Currently,
6934 * fan is required for most designs with SFX7101, BCM8727 and BCM8481.
6936 else if (val
== SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE
)
6937 for (port
= PORT_0
; port
< PORT_MAX
; port
++) {
6939 bnx2x_fan_failure_det_req(
6941 bp
->common
.shmem_base
,
6942 bp
->common
.shmem2_base
,
6946 DP(NETIF_MSG_HW
, "fan detection setting: %d\n", is_required
);
6948 if (is_required
== 0)
6951 /* Fan failure is indicated by SPIO 5 */
6952 bnx2x_set_spio(bp
, MISC_SPIO_SPIO5
, MISC_SPIO_INPUT_HI_Z
);
6954 /* set to active low mode */
6955 val
= REG_RD(bp
, MISC_REG_SPIO_INT
);
6956 val
|= (MISC_SPIO_SPIO5
<< MISC_SPIO_INT_OLD_SET_POS
);
6957 REG_WR(bp
, MISC_REG_SPIO_INT
, val
);
6959 /* enable interrupt to signal the IGU */
6960 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
6961 val
|= MISC_SPIO_SPIO5
;
6962 REG_WR(bp
, MISC_REG_SPIO_EVENT_EN
, val
);
6965 void bnx2x_pf_disable(struct bnx2x
*bp
)
6967 u32 val
= REG_RD(bp
, IGU_REG_PF_CONFIGURATION
);
6968 val
&= ~IGU_PF_CONF_FUNC_EN
;
6970 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, val
);
6971 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
6972 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 0);
6975 static void bnx2x__common_init_phy(struct bnx2x
*bp
)
6977 u32 shmem_base
[2], shmem2_base
[2];
6978 /* Avoid common init in case MFW supports LFA */
6979 if (SHMEM2_RD(bp
, size
) >
6980 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
6982 shmem_base
[0] = bp
->common
.shmem_base
;
6983 shmem2_base
[0] = bp
->common
.shmem2_base
;
6984 if (!CHIP_IS_E1x(bp
)) {
6986 SHMEM2_RD(bp
, other_shmem_base_addr
);
6988 SHMEM2_RD(bp
, other_shmem2_base_addr
);
6990 bnx2x_acquire_phy_lock(bp
);
6991 bnx2x_common_init_phy(bp
, shmem_base
, shmem2_base
,
6992 bp
->common
.chip_id
);
6993 bnx2x_release_phy_lock(bp
);
6996 static void bnx2x_config_endianity(struct bnx2x
*bp
, u32 val
)
6998 REG_WR(bp
, PXP2_REG_RQ_QM_ENDIAN_M
, val
);
6999 REG_WR(bp
, PXP2_REG_RQ_TM_ENDIAN_M
, val
);
7000 REG_WR(bp
, PXP2_REG_RQ_SRC_ENDIAN_M
, val
);
7001 REG_WR(bp
, PXP2_REG_RQ_CDU_ENDIAN_M
, val
);
7002 REG_WR(bp
, PXP2_REG_RQ_DBG_ENDIAN_M
, val
);
7004 /* make sure this value is 0 */
7005 REG_WR(bp
, PXP2_REG_RQ_HC_ENDIAN_M
, 0);
7007 REG_WR(bp
, PXP2_REG_RD_QM_SWAP_MODE
, val
);
7008 REG_WR(bp
, PXP2_REG_RD_TM_SWAP_MODE
, val
);
7009 REG_WR(bp
, PXP2_REG_RD_SRC_SWAP_MODE
, val
);
7010 REG_WR(bp
, PXP2_REG_RD_CDURD_SWAP_MODE
, val
);
7013 static void bnx2x_set_endianity(struct bnx2x
*bp
)
7016 bnx2x_config_endianity(bp
, 1);
7018 bnx2x_config_endianity(bp
, 0);
7022 static void bnx2x_reset_endianity(struct bnx2x
*bp
)
7024 bnx2x_config_endianity(bp
, 0);
7028 * bnx2x_init_hw_common - initialize the HW at the COMMON phase.
7030 * @bp: driver handle
7032 static int bnx2x_init_hw_common(struct bnx2x
*bp
)
7036 DP(NETIF_MSG_HW
, "starting common init func %d\n", BP_ABS_FUNC(bp
));
7039 * take the RESET lock to protect undi_unload flow from accessing
7040 * registers while we're resetting the chip
7042 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
7044 bnx2x_reset_common(bp
);
7045 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, 0xffffffff);
7048 if (CHIP_IS_E3(bp
)) {
7049 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT0
;
7050 val
|= MISC_REGISTERS_RESET_REG_2_MSTAT1
;
7052 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
, val
);
7054 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
7056 bnx2x_init_block(bp
, BLOCK_MISC
, PHASE_COMMON
);
7058 if (!CHIP_IS_E1x(bp
)) {
7062 * 4-port mode or 2-port mode we need to turn of master-enable
7063 * for everyone, after that, turn it back on for self.
7064 * so, we disregard multi-function or not, and always disable
7065 * for all functions on the given path, this means 0,2,4,6 for
7066 * path 0 and 1,3,5,7 for path 1
7068 for (abs_func_id
= BP_PATH(bp
);
7069 abs_func_id
< E2_FUNC_MAX
*2; abs_func_id
+= 2) {
7070 if (abs_func_id
== BP_ABS_FUNC(bp
)) {
7072 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
,
7077 bnx2x_pretend_func(bp
, abs_func_id
);
7078 /* clear pf enable */
7079 bnx2x_pf_disable(bp
);
7080 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
7084 bnx2x_init_block(bp
, BLOCK_PXP
, PHASE_COMMON
);
7085 if (CHIP_IS_E1(bp
)) {
7086 /* enable HW interrupt from PXP on USDM overflow
7087 bit 16 on INT_MASK_0 */
7088 REG_WR(bp
, PXP_REG_PXP_INT_MASK_0
, 0);
7091 bnx2x_init_block(bp
, BLOCK_PXP2
, PHASE_COMMON
);
7093 bnx2x_set_endianity(bp
);
7094 bnx2x_ilt_init_page_size(bp
, INITOP_SET
);
7096 if (CHIP_REV_IS_FPGA(bp
) && CHIP_IS_E1H(bp
))
7097 REG_WR(bp
, PXP2_REG_PGL_TAGS_LIMIT
, 0x1);
7099 /* let the HW do it's magic ... */
7101 /* finish PXP init */
7102 val
= REG_RD(bp
, PXP2_REG_RQ_CFG_DONE
);
7104 BNX2X_ERR("PXP2 CFG failed\n");
7107 val
= REG_RD(bp
, PXP2_REG_RD_INIT_DONE
);
7109 BNX2X_ERR("PXP2 RD_INIT failed\n");
7113 /* Timers bug workaround E2 only. We need to set the entire ILT to
7114 * have entries with value "0" and valid bit on.
7115 * This needs to be done by the first PF that is loaded in a path
7116 * (i.e. common phase)
7118 if (!CHIP_IS_E1x(bp
)) {
7119 /* In E2 there is a bug in the timers block that can cause function 6 / 7
7120 * (i.e. vnic3) to start even if it is marked as "scan-off".
7121 * This occurs when a different function (func2,3) is being marked
7122 * as "scan-off". Real-life scenario for example: if a driver is being
7123 * load-unloaded while func6,7 are down. This will cause the timer to access
7124 * the ilt, translate to a logical address and send a request to read/write.
7125 * Since the ilt for the function that is down is not valid, this will cause
7126 * a translation error which is unrecoverable.
7127 * The Workaround is intended to make sure that when this happens nothing fatal
7128 * will occur. The workaround:
7129 * 1. First PF driver which loads on a path will:
7130 * a. After taking the chip out of reset, by using pretend,
7131 * it will write "0" to the following registers of
7133 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0);
7134 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0);
7135 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0);
7136 * And for itself it will write '1' to
7137 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable
7138 * dmae-operations (writing to pram for example.)
7139 * note: can be done for only function 6,7 but cleaner this
7141 * b. Write zero+valid to the entire ILT.
7142 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of
7143 * VNIC3 (of that port). The range allocated will be the
7144 * entire ILT. This is needed to prevent ILT range error.
7145 * 2. Any PF driver load flow:
7146 * a. ILT update with the physical addresses of the allocated
7148 * b. Wait 20msec. - note that this timeout is needed to make
7149 * sure there are no requests in one of the PXP internal
7150 * queues with "old" ILT addresses.
7151 * c. PF enable in the PGLC.
7152 * d. Clear the was_error of the PF in the PGLC. (could have
7153 * occurred while driver was down)
7154 * e. PF enable in the CFC (WEAK + STRONG)
7155 * f. Timers scan enable
7156 * 3. PF driver unload flow:
7157 * a. Clear the Timers scan_en.
7158 * b. Polling for scan_on=0 for that PF.
7159 * c. Clear the PF enable bit in the PXP.
7160 * d. Clear the PF enable in the CFC (WEAK + STRONG)
7161 * e. Write zero+valid to all ILT entries (The valid bit must
7163 * f. If this is VNIC 3 of a port then also init
7164 * first_timers_ilt_entry to zero and last_timers_ilt_entry
7165 * to the last entry in the ILT.
7168 * Currently the PF error in the PGLC is non recoverable.
7169 * In the future the there will be a recovery routine for this error.
7170 * Currently attention is masked.
7171 * Having an MCP lock on the load/unload process does not guarantee that
7172 * there is no Timer disable during Func6/7 enable. This is because the
7173 * Timers scan is currently being cleared by the MCP on FLR.
7174 * Step 2.d can be done only for PF6/7 and the driver can also check if
7175 * there is error before clearing it. But the flow above is simpler and
7177 * All ILT entries are written by zero+valid and not just PF6/7
7178 * ILT entries since in the future the ILT entries allocation for
7179 * PF-s might be dynamic.
7181 struct ilt_client_info ilt_cli
;
7182 struct bnx2x_ilt ilt
;
7183 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
7184 memset(&ilt
, 0, sizeof(struct bnx2x_ilt
));
7186 /* initialize dummy TM client */
7188 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
7189 ilt_cli
.client_num
= ILT_CLIENT_TM
;
7191 /* Step 1: set zeroes to all ilt page entries with valid bit on
7192 * Step 2: set the timers first/last ilt entry to point
7193 * to the entire range to prevent ILT range error for 3rd/4th
7194 * vnic (this code assumes existence of the vnic)
7196 * both steps performed by call to bnx2x_ilt_client_init_op()
7197 * with dummy TM client
7199 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT
7200 * and his brother are split registers
7202 bnx2x_pretend_func(bp
, (BP_PATH(bp
) + 6));
7203 bnx2x_ilt_client_init_op_ilt(bp
, &ilt
, &ilt_cli
, INITOP_CLEAR
);
7204 bnx2x_pretend_func(bp
, BP_ABS_FUNC(bp
));
7206 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN
, BNX2X_PXP_DRAM_ALIGN
);
7207 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_RD
, BNX2X_PXP_DRAM_ALIGN
);
7208 REG_WR(bp
, PXP2_REG_RQ_DRAM_ALIGN_SEL
, 1);
7211 REG_WR(bp
, PXP2_REG_RQ_DISABLE_INPUTS
, 0);
7212 REG_WR(bp
, PXP2_REG_RD_DISABLE_INPUTS
, 0);
7214 if (!CHIP_IS_E1x(bp
)) {
7215 int factor
= CHIP_REV_IS_EMUL(bp
) ? 1000 :
7216 (CHIP_REV_IS_FPGA(bp
) ? 400 : 0);
7217 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, PHASE_COMMON
);
7219 bnx2x_init_block(bp
, BLOCK_ATC
, PHASE_COMMON
);
7221 /* let the HW do it's magic ... */
7224 val
= REG_RD(bp
, ATC_REG_ATC_INIT_DONE
);
7225 } while (factor
-- && (val
!= 1));
7228 BNX2X_ERR("ATC_INIT failed\n");
7233 bnx2x_init_block(bp
, BLOCK_DMAE
, PHASE_COMMON
);
7235 bnx2x_iov_init_dmae(bp
);
7237 /* clean the DMAE memory */
7239 bnx2x_init_fill(bp
, TSEM_REG_PRAM
, 0, 8, 1);
7241 bnx2x_init_block(bp
, BLOCK_TCM
, PHASE_COMMON
);
7243 bnx2x_init_block(bp
, BLOCK_UCM
, PHASE_COMMON
);
7245 bnx2x_init_block(bp
, BLOCK_CCM
, PHASE_COMMON
);
7247 bnx2x_init_block(bp
, BLOCK_XCM
, PHASE_COMMON
);
7249 bnx2x_read_dmae(bp
, XSEM_REG_PASSIVE_BUFFER
, 3);
7250 bnx2x_read_dmae(bp
, CSEM_REG_PASSIVE_BUFFER
, 3);
7251 bnx2x_read_dmae(bp
, TSEM_REG_PASSIVE_BUFFER
, 3);
7252 bnx2x_read_dmae(bp
, USEM_REG_PASSIVE_BUFFER
, 3);
7254 bnx2x_init_block(bp
, BLOCK_QM
, PHASE_COMMON
);
7256 /* QM queues pointers table */
7257 bnx2x_qm_init_ptr_table(bp
, bp
->qm_cid_count
, INITOP_SET
);
7259 /* soft reset pulse */
7260 REG_WR(bp
, QM_REG_SOFT_RESET
, 1);
7261 REG_WR(bp
, QM_REG_SOFT_RESET
, 0);
7263 if (CNIC_SUPPORT(bp
))
7264 bnx2x_init_block(bp
, BLOCK_TM
, PHASE_COMMON
);
7266 bnx2x_init_block(bp
, BLOCK_DORQ
, PHASE_COMMON
);
7268 if (!CHIP_REV_IS_SLOW(bp
))
7269 /* enable hw interrupt from doorbell Q */
7270 REG_WR(bp
, DORQ_REG_DORQ_INT_MASK
, 0);
7272 bnx2x_init_block(bp
, BLOCK_BRB1
, PHASE_COMMON
);
7274 bnx2x_init_block(bp
, BLOCK_PRS
, PHASE_COMMON
);
7275 REG_WR(bp
, PRS_REG_A_PRSU_20
, 0xf);
7277 if (!CHIP_IS_E1(bp
))
7278 REG_WR(bp
, PRS_REG_E1HOV_MODE
, bp
->path_has_ovlan
);
7280 if (!CHIP_IS_E1x(bp
) && !CHIP_IS_E3B0(bp
)) {
7281 if (IS_MF_AFEX(bp
)) {
7282 /* configure that VNTag and VLAN headers must be
7283 * received in afex mode
7285 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
, 0xE);
7286 REG_WR(bp
, PRS_REG_MUST_HAVE_HDRS
, 0xA);
7287 REG_WR(bp
, PRS_REG_HDRS_AFTER_TAG_0
, 0x6);
7288 REG_WR(bp
, PRS_REG_TAG_ETHERTYPE_0
, 0x8926);
7289 REG_WR(bp
, PRS_REG_TAG_LEN_0
, 0x4);
7291 /* Bit-map indicating which L2 hdrs may appear
7292 * after the basic Ethernet header
7294 REG_WR(bp
, PRS_REG_HDRS_AFTER_BASIC
,
7295 bp
->path_has_ovlan
? 7 : 6);
7299 bnx2x_init_block(bp
, BLOCK_TSDM
, PHASE_COMMON
);
7300 bnx2x_init_block(bp
, BLOCK_CSDM
, PHASE_COMMON
);
7301 bnx2x_init_block(bp
, BLOCK_USDM
, PHASE_COMMON
);
7302 bnx2x_init_block(bp
, BLOCK_XSDM
, PHASE_COMMON
);
7304 if (!CHIP_IS_E1x(bp
)) {
7305 /* reset VFC memories */
7306 REG_WR(bp
, TSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
7307 VFC_MEMORIES_RST_REG_CAM_RST
|
7308 VFC_MEMORIES_RST_REG_RAM_RST
);
7309 REG_WR(bp
, XSEM_REG_FAST_MEMORY
+ VFC_REG_MEMORIES_RST
,
7310 VFC_MEMORIES_RST_REG_CAM_RST
|
7311 VFC_MEMORIES_RST_REG_RAM_RST
);
7316 bnx2x_init_block(bp
, BLOCK_TSEM
, PHASE_COMMON
);
7317 bnx2x_init_block(bp
, BLOCK_USEM
, PHASE_COMMON
);
7318 bnx2x_init_block(bp
, BLOCK_CSEM
, PHASE_COMMON
);
7319 bnx2x_init_block(bp
, BLOCK_XSEM
, PHASE_COMMON
);
7322 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
7324 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
,
7327 bnx2x_init_block(bp
, BLOCK_UPB
, PHASE_COMMON
);
7328 bnx2x_init_block(bp
, BLOCK_XPB
, PHASE_COMMON
);
7329 bnx2x_init_block(bp
, BLOCK_PBF
, PHASE_COMMON
);
7331 if (!CHIP_IS_E1x(bp
)) {
7332 if (IS_MF_AFEX(bp
)) {
7333 /* configure that VNTag and VLAN headers must be
7336 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
, 0xE);
7337 REG_WR(bp
, PBF_REG_MUST_HAVE_HDRS
, 0xA);
7338 REG_WR(bp
, PBF_REG_HDRS_AFTER_TAG_0
, 0x6);
7339 REG_WR(bp
, PBF_REG_TAG_ETHERTYPE_0
, 0x8926);
7340 REG_WR(bp
, PBF_REG_TAG_LEN_0
, 0x4);
7342 REG_WR(bp
, PBF_REG_HDRS_AFTER_BASIC
,
7343 bp
->path_has_ovlan
? 7 : 6);
7347 REG_WR(bp
, SRC_REG_SOFT_RST
, 1);
7349 bnx2x_init_block(bp
, BLOCK_SRC
, PHASE_COMMON
);
7351 if (CNIC_SUPPORT(bp
)) {
7352 REG_WR(bp
, SRC_REG_KEYSEARCH_0
, 0x63285672);
7353 REG_WR(bp
, SRC_REG_KEYSEARCH_1
, 0x24b8f2cc);
7354 REG_WR(bp
, SRC_REG_KEYSEARCH_2
, 0x223aef9b);
7355 REG_WR(bp
, SRC_REG_KEYSEARCH_3
, 0x26001e3a);
7356 REG_WR(bp
, SRC_REG_KEYSEARCH_4
, 0x7ae91116);
7357 REG_WR(bp
, SRC_REG_KEYSEARCH_5
, 0x5ce5230b);
7358 REG_WR(bp
, SRC_REG_KEYSEARCH_6
, 0x298d8adf);
7359 REG_WR(bp
, SRC_REG_KEYSEARCH_7
, 0x6eb0ff09);
7360 REG_WR(bp
, SRC_REG_KEYSEARCH_8
, 0x1830f82f);
7361 REG_WR(bp
, SRC_REG_KEYSEARCH_9
, 0x01e46be7);
7363 REG_WR(bp
, SRC_REG_SOFT_RST
, 0);
7365 if (sizeof(union cdu_context
) != 1024)
7366 /* we currently assume that a context is 1024 bytes */
7367 dev_alert(&bp
->pdev
->dev
,
7368 "please adjust the size of cdu_context(%ld)\n",
7369 (long)sizeof(union cdu_context
));
7371 bnx2x_init_block(bp
, BLOCK_CDU
, PHASE_COMMON
);
7372 val
= (4 << 24) + (0 << 12) + 1024;
7373 REG_WR(bp
, CDU_REG_CDU_GLOBAL_PARAMS
, val
);
7375 bnx2x_init_block(bp
, BLOCK_CFC
, PHASE_COMMON
);
7376 REG_WR(bp
, CFC_REG_INIT_REG
, 0x7FF);
7377 /* enable context validation interrupt from CFC */
7378 REG_WR(bp
, CFC_REG_CFC_INT_MASK
, 0);
7380 /* set the thresholds to prevent CFC/CDU race */
7381 REG_WR(bp
, CFC_REG_DEBUG0
, 0x20020000);
7383 bnx2x_init_block(bp
, BLOCK_HC
, PHASE_COMMON
);
7385 if (!CHIP_IS_E1x(bp
) && BP_NOMCP(bp
))
7386 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x36);
7388 bnx2x_init_block(bp
, BLOCK_IGU
, PHASE_COMMON
);
7389 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, PHASE_COMMON
);
7391 /* Reset PCIE errors for debug */
7392 REG_WR(bp
, 0x2814, 0xffffffff);
7393 REG_WR(bp
, 0x3820, 0xffffffff);
7395 if (!CHIP_IS_E1x(bp
)) {
7396 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_CONTROL_5
,
7397 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1
|
7398 PXPCS_TL_CONTROL_5_ERR_UNSPPORT
));
7399 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC345_STAT
,
7400 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4
|
7401 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3
|
7402 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2
));
7403 REG_WR(bp
, PCICFG_OFFSET
+ PXPCS_TL_FUNC678_STAT
,
7404 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7
|
7405 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6
|
7406 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5
));
7409 bnx2x_init_block(bp
, BLOCK_NIG
, PHASE_COMMON
);
7410 if (!CHIP_IS_E1(bp
)) {
7411 /* in E3 this done in per-port section */
7412 if (!CHIP_IS_E3(bp
))
7413 REG_WR(bp
, NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
7415 if (CHIP_IS_E1H(bp
))
7416 /* not applicable for E2 (and above ...) */
7417 REG_WR(bp
, NIG_REG_LLH_E1HOV_MODE
, IS_MF_SD(bp
));
7419 if (CHIP_REV_IS_SLOW(bp
))
7422 /* finish CFC init */
7423 val
= reg_poll(bp
, CFC_REG_LL_INIT_DONE
, 1, 100, 10);
7425 BNX2X_ERR("CFC LL_INIT failed\n");
7428 val
= reg_poll(bp
, CFC_REG_AC_INIT_DONE
, 1, 100, 10);
7430 BNX2X_ERR("CFC AC_INIT failed\n");
7433 val
= reg_poll(bp
, CFC_REG_CAM_INIT_DONE
, 1, 100, 10);
7435 BNX2X_ERR("CFC CAM_INIT failed\n");
7438 REG_WR(bp
, CFC_REG_DEBUG0
, 0);
7440 if (CHIP_IS_E1(bp
)) {
7441 /* read NIG statistic
7442 to see if this is our first up since powerup */
7443 bnx2x_read_dmae(bp
, NIG_REG_STAT2_BRB_OCTET
, 2);
7444 val
= *bnx2x_sp(bp
, wb_data
[0]);
7446 /* do internal memory self test */
7447 if ((val
== 0) && bnx2x_int_mem_test(bp
)) {
7448 BNX2X_ERR("internal mem self test failed\n");
7453 bnx2x_setup_fan_failure_detection(bp
);
7455 /* clear PXP2 attentions */
7456 REG_RD(bp
, PXP2_REG_PXP2_INT_STS_CLR_0
);
7458 bnx2x_enable_blocks_attention(bp
);
7459 bnx2x_enable_blocks_parity(bp
);
7461 if (!BP_NOMCP(bp
)) {
7462 if (CHIP_IS_E1x(bp
))
7463 bnx2x__common_init_phy(bp
);
7465 BNX2X_ERR("Bootcode is missing - can not initialize link\n");
7467 if (SHMEM2_HAS(bp
, netproc_fw_ver
))
7468 SHMEM2_WR(bp
, netproc_fw_ver
, REG_RD(bp
, XSEM_REG_PRAM
));
7474 * bnx2x_init_hw_common_chip - init HW at the COMMON_CHIP phase.
7476 * @bp: driver handle
7478 static int bnx2x_init_hw_common_chip(struct bnx2x
*bp
)
7480 int rc
= bnx2x_init_hw_common(bp
);
7485 /* In E2 2-PORT mode, same ext phy is used for the two paths */
7487 bnx2x__common_init_phy(bp
);
7492 static int bnx2x_init_hw_port(struct bnx2x
*bp
)
7494 int port
= BP_PORT(bp
);
7495 int init_phase
= port
? PHASE_PORT1
: PHASE_PORT0
;
7499 DP(NETIF_MSG_HW
, "starting port init port %d\n", port
);
7501 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
7503 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
7504 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
7505 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
7507 /* Timers bug workaround: disables the pf_master bit in pglue at
7508 * common phase, we need to enable it here before any dmae access are
7509 * attempted. Therefore we manually added the enable-master to the
7510 * port phase (it also happens in the function phase)
7512 if (!CHIP_IS_E1x(bp
))
7513 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
7515 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
7516 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
7517 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
7518 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
7520 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
7521 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
7522 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
7523 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
7525 /* QM cid (connection) count */
7526 bnx2x_qm_init_cid_count(bp
, bp
->qm_cid_count
, INITOP_SET
);
7528 if (CNIC_SUPPORT(bp
)) {
7529 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
7530 REG_WR(bp
, TM_REG_LIN0_SCAN_TIME
+ port
*4, 20);
7531 REG_WR(bp
, TM_REG_LIN0_MAX_ACTIVE_CID
+ port
*4, 31);
7534 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
7536 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
7538 if (CHIP_IS_E1(bp
) || CHIP_IS_E1H(bp
)) {
7541 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 160 : 246);
7542 else if (bp
->dev
->mtu
> 4096) {
7543 if (bp
->flags
& ONE_PORT_FLAG
)
7547 /* (24*1024 + val*4)/256 */
7548 low
= 96 + (val
/64) +
7549 ((val
% 64) ? 1 : 0);
7552 low
= ((bp
->flags
& ONE_PORT_FLAG
) ? 80 : 160);
7553 high
= low
+ 56; /* 14*1024/256 */
7554 REG_WR(bp
, BRB1_REG_PAUSE_LOW_THRESHOLD_0
+ port
*4, low
);
7555 REG_WR(bp
, BRB1_REG_PAUSE_HIGH_THRESHOLD_0
+ port
*4, high
);
7558 if (CHIP_MODE_IS_4_PORT(bp
))
7559 REG_WR(bp
, (BP_PORT(bp
) ?
7560 BRB1_REG_MAC_GUARANTIED_1
:
7561 BRB1_REG_MAC_GUARANTIED_0
), 40);
7563 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
7564 if (CHIP_IS_E3B0(bp
)) {
7565 if (IS_MF_AFEX(bp
)) {
7566 /* configure headers for AFEX mode */
7567 REG_WR(bp
, BP_PORT(bp
) ?
7568 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7569 PRS_REG_HDRS_AFTER_BASIC_PORT_0
, 0xE);
7570 REG_WR(bp
, BP_PORT(bp
) ?
7571 PRS_REG_HDRS_AFTER_TAG_0_PORT_1
:
7572 PRS_REG_HDRS_AFTER_TAG_0_PORT_0
, 0x6);
7573 REG_WR(bp
, BP_PORT(bp
) ?
7574 PRS_REG_MUST_HAVE_HDRS_PORT_1
:
7575 PRS_REG_MUST_HAVE_HDRS_PORT_0
, 0xA);
7577 /* Ovlan exists only if we are in multi-function +
7578 * switch-dependent mode, in switch-independent there
7579 * is no ovlan headers
7581 REG_WR(bp
, BP_PORT(bp
) ?
7582 PRS_REG_HDRS_AFTER_BASIC_PORT_1
:
7583 PRS_REG_HDRS_AFTER_BASIC_PORT_0
,
7584 (bp
->path_has_ovlan
? 7 : 6));
7588 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
7589 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
7590 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
7591 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
7593 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
7594 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
7595 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
7596 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
7598 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
7599 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
7601 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
7603 if (CHIP_IS_E1x(bp
)) {
7604 /* configure PBF to work without PAUSE mtu 9000 */
7605 REG_WR(bp
, PBF_REG_P0_PAUSE_ENABLE
+ port
*4, 0);
7607 /* update threshold */
7608 REG_WR(bp
, PBF_REG_P0_ARB_THRSH
+ port
*4, (9040/16));
7609 /* update init credit */
7610 REG_WR(bp
, PBF_REG_P0_INIT_CRD
+ port
*4, (9040/16) + 553 - 22);
7613 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 1);
7615 REG_WR(bp
, PBF_REG_INIT_P0
+ port
*4, 0);
7618 if (CNIC_SUPPORT(bp
))
7619 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
7621 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
7622 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
7624 if (CHIP_IS_E1(bp
)) {
7625 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
7626 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
7628 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
7630 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
7632 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
7633 /* init aeu_mask_attn_func_0/1:
7634 * - SF mode: bits 3-7 are masked. Only bits 0-2 are in use
7635 * - MF mode: bit 3 is masked. Bits 0-2 are in use as in SF
7636 * bits 4-7 are used for "per vn group attention" */
7637 val
= IS_MF(bp
) ? 0xF7 : 0x7;
7638 /* Enable DCBX attention for all but E1 */
7639 val
|= CHIP_IS_E1(bp
) ? 0 : 0x10;
7640 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, val
);
7642 /* SCPAD_PARITY should NOT trigger close the gates */
7643 reg
= port
? MISC_REG_AEU_ENABLE4_NIG_1
: MISC_REG_AEU_ENABLE4_NIG_0
;
7646 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
);
7648 reg
= port
? MISC_REG_AEU_ENABLE4_PXP_1
: MISC_REG_AEU_ENABLE4_PXP_0
;
7651 ~AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY
);
7653 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
7655 if (!CHIP_IS_E1x(bp
)) {
7656 /* Bit-map indicating which L2 hdrs may appear after the
7657 * basic Ethernet header
7660 REG_WR(bp
, BP_PORT(bp
) ?
7661 NIG_REG_P1_HDRS_AFTER_BASIC
:
7662 NIG_REG_P0_HDRS_AFTER_BASIC
, 0xE);
7664 REG_WR(bp
, BP_PORT(bp
) ?
7665 NIG_REG_P1_HDRS_AFTER_BASIC
:
7666 NIG_REG_P0_HDRS_AFTER_BASIC
,
7667 IS_MF_SD(bp
) ? 7 : 6);
7670 REG_WR(bp
, BP_PORT(bp
) ?
7671 NIG_REG_LLH1_MF_MODE
:
7672 NIG_REG_LLH_MF_MODE
, IS_MF(bp
));
7674 if (!CHIP_IS_E3(bp
))
7675 REG_WR(bp
, NIG_REG_XGXS_SERDES0_MODE_SEL
+ port
*4, 1);
7677 if (!CHIP_IS_E1(bp
)) {
7678 /* 0x2 disable mf_ov, 0x1 enable */
7679 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK_MF
+ port
*4,
7680 (IS_MF_SD(bp
) ? 0x1 : 0x2));
7682 if (!CHIP_IS_E1x(bp
)) {
7684 switch (bp
->mf_mode
) {
7685 case MULTI_FUNCTION_SD
:
7688 case MULTI_FUNCTION_SI
:
7689 case MULTI_FUNCTION_AFEX
:
7694 REG_WR(bp
, (BP_PORT(bp
) ? NIG_REG_LLH1_CLS_TYPE
:
7695 NIG_REG_LLH0_CLS_TYPE
), val
);
7698 REG_WR(bp
, NIG_REG_LLFC_ENABLE_0
+ port
*4, 0);
7699 REG_WR(bp
, NIG_REG_LLFC_OUT_EN_0
+ port
*4, 0);
7700 REG_WR(bp
, NIG_REG_PAUSE_ENABLE_0
+ port
*4, 1);
7704 /* If SPIO5 is set to generate interrupts, enable it for this port */
7705 val
= REG_RD(bp
, MISC_REG_SPIO_EVENT_EN
);
7706 if (val
& MISC_SPIO_SPIO5
) {
7707 u32 reg_addr
= (port
? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0
:
7708 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0
);
7709 val
= REG_RD(bp
, reg_addr
);
7710 val
|= AEU_INPUTS_ATTN_BITS_SPIO5
;
7711 REG_WR(bp
, reg_addr
, val
);
7717 static void bnx2x_ilt_wr(struct bnx2x
*bp
, u32 index
, dma_addr_t addr
)
7723 reg
= PXP2_REG_RQ_ONCHIP_AT
+ index
*8;
7725 reg
= PXP2_REG_RQ_ONCHIP_AT_B0
+ index
*8;
7727 wb_write
[0] = ONCHIP_ADDR1(addr
);
7728 wb_write
[1] = ONCHIP_ADDR2(addr
);
7729 REG_WR_DMAE(bp
, reg
, wb_write
, 2);
7732 void bnx2x_igu_clear_sb_gen(struct bnx2x
*bp
, u8 func
, u8 idu_sb_id
, bool is_pf
)
7734 u32 data
, ctl
, cnt
= 100;
7735 u32 igu_addr_data
= IGU_REG_COMMAND_REG_32LSB_DATA
;
7736 u32 igu_addr_ctl
= IGU_REG_COMMAND_REG_CTRL
;
7737 u32 igu_addr_ack
= IGU_REG_CSTORM_TYPE_0_SB_CLEANUP
+ (idu_sb_id
/32)*4;
7738 u32 sb_bit
= 1 << (idu_sb_id
%32);
7739 u32 func_encode
= func
| (is_pf
? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT
;
7740 u32 addr_encode
= IGU_CMD_E2_PROD_UPD_BASE
+ idu_sb_id
;
7742 /* Not supported in BC mode */
7743 if (CHIP_INT_MODE_IS_BC(bp
))
7746 data
= (IGU_USE_REGISTER_cstorm_type_0_sb_cleanup
7747 << IGU_REGULAR_CLEANUP_TYPE_SHIFT
) |
7748 IGU_REGULAR_CLEANUP_SET
|
7749 IGU_REGULAR_BCLEANUP
;
7751 ctl
= addr_encode
<< IGU_CTRL_REG_ADDRESS_SHIFT
|
7752 func_encode
<< IGU_CTRL_REG_FID_SHIFT
|
7753 IGU_CTRL_CMD_TYPE_WR
<< IGU_CTRL_REG_TYPE_SHIFT
;
7755 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7756 data
, igu_addr_data
);
7757 REG_WR(bp
, igu_addr_data
, data
);
7760 DP(NETIF_MSG_HW
, "write 0x%08x to IGU(via GRC) addr 0x%x\n",
7762 REG_WR(bp
, igu_addr_ctl
, ctl
);
7766 /* wait for clean up to finish */
7767 while (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
) && --cnt
)
7770 if (!(REG_RD(bp
, igu_addr_ack
) & sb_bit
)) {
7772 "Unable to finish IGU cleanup: idu_sb_id %d offset %d bit %d (cnt %d)\n",
7773 idu_sb_id
, idu_sb_id
/32, idu_sb_id
%32, cnt
);
7777 static void bnx2x_igu_clear_sb(struct bnx2x
*bp
, u8 idu_sb_id
)
7779 bnx2x_igu_clear_sb_gen(bp
, BP_FUNC(bp
), idu_sb_id
, true /*PF*/);
7782 static void bnx2x_clear_func_ilt(struct bnx2x
*bp
, u32 func
)
7784 u32 i
, base
= FUNC_ILT_BASE(func
);
7785 for (i
= base
; i
< base
+ ILT_PER_FUNC
; i
++)
7786 bnx2x_ilt_wr(bp
, i
, 0);
7789 static void bnx2x_init_searcher(struct bnx2x
*bp
)
7791 int port
= BP_PORT(bp
);
7792 bnx2x_src_init_t2(bp
, bp
->t2
, bp
->t2_mapping
, SRC_CONN_NUM
);
7793 /* T1 hash bits value determines the T1 number of entries */
7794 REG_WR(bp
, SRC_REG_NUMBER_HASH_BITS0
+ port
*4, SRC_HASH_BITS
);
7797 static inline int bnx2x_func_switch_update(struct bnx2x
*bp
, int suspend
)
7800 struct bnx2x_func_state_params func_params
= {NULL
};
7801 struct bnx2x_func_switch_update_params
*switch_update_params
=
7802 &func_params
.params
.switch_update
;
7804 /* Prepare parameters for function state transitions */
7805 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
7806 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
7808 func_params
.f_obj
= &bp
->func_obj
;
7809 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
7811 /* Function parameters */
7812 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG
,
7813 &switch_update_params
->changes
);
7815 __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND
,
7816 &switch_update_params
->changes
);
7818 rc
= bnx2x_func_state_change(bp
, &func_params
);
7823 static int bnx2x_reset_nic_mode(struct bnx2x
*bp
)
7825 int rc
, i
, port
= BP_PORT(bp
);
7826 int vlan_en
= 0, mac_en
[NUM_MACS
];
7828 /* Close input from network */
7829 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7830 bnx2x_set_rx_filter(&bp
->link_params
, 0);
7832 vlan_en
= REG_RD(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7833 NIG_REG_LLH0_FUNC_EN
);
7834 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7835 NIG_REG_LLH0_FUNC_EN
, 0);
7836 for (i
= 0; i
< NUM_MACS
; i
++) {
7837 mac_en
[i
] = REG_RD(bp
, port
?
7838 (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7840 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+
7842 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7844 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
), 0);
7848 /* Close BMC to host */
7849 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7850 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 0);
7852 /* Suspend Tx switching to the PF. Completion of this ramrod
7853 * further guarantees that all the packets of that PF / child
7854 * VFs in BRB were processed by the Parser, so it is safe to
7855 * change the NIC_MODE register.
7857 rc
= bnx2x_func_switch_update(bp
, 1);
7859 BNX2X_ERR("Can't suspend tx-switching!\n");
7863 /* Change NIC_MODE register */
7864 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7866 /* Open input from network */
7867 if (bp
->mf_mode
== SINGLE_FUNCTION
) {
7868 bnx2x_set_rx_filter(&bp
->link_params
, 1);
7870 REG_WR(bp
, port
? NIG_REG_LLH1_FUNC_EN
:
7871 NIG_REG_LLH0_FUNC_EN
, vlan_en
);
7872 for (i
= 0; i
< NUM_MACS
; i
++) {
7873 REG_WR(bp
, port
? (NIG_REG_LLH1_FUNC_MEM_ENABLE
+
7875 (NIG_REG_LLH0_FUNC_MEM_ENABLE
+ 4 * i
),
7880 /* Enable BMC to host */
7881 REG_WR(bp
, port
? NIG_REG_P0_TX_MNG_HOST_ENABLE
:
7882 NIG_REG_P1_TX_MNG_HOST_ENABLE
, 1);
7884 /* Resume Tx switching to the PF */
7885 rc
= bnx2x_func_switch_update(bp
, 0);
7887 BNX2X_ERR("Can't resume tx-switching!\n");
7891 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7895 int bnx2x_init_hw_func_cnic(struct bnx2x
*bp
)
7899 bnx2x_ilt_init_op_cnic(bp
, INITOP_SET
);
7901 if (CONFIGURE_NIC_MODE(bp
)) {
7902 /* Configure searcher as part of function hw init */
7903 bnx2x_init_searcher(bp
);
7905 /* Reset NIC mode */
7906 rc
= bnx2x_reset_nic_mode(bp
);
7908 BNX2X_ERR("Can't change NIC mode!\n");
7915 /* previous driver DMAE transaction may have occurred when pre-boot stage ended
7916 * and boot began, or when kdump kernel was loaded. Either case would invalidate
7917 * the addresses of the transaction, resulting in was-error bit set in the pci
7918 * causing all hw-to-host pcie transactions to timeout. If this happened we want
7919 * to clear the interrupt which detected this from the pglueb and the was done
7922 static void bnx2x_clean_pglue_errors(struct bnx2x
*bp
)
7924 if (!CHIP_IS_E1x(bp
))
7925 REG_WR(bp
, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR
,
7926 1 << BP_ABS_FUNC(bp
));
7929 static int bnx2x_init_hw_func(struct bnx2x
*bp
)
7931 int port
= BP_PORT(bp
);
7932 int func
= BP_FUNC(bp
);
7933 int init_phase
= PHASE_PF0
+ func
;
7934 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
7937 u32 main_mem_base
, main_mem_size
, main_mem_prty_clr
;
7938 int i
, main_mem_width
, rc
;
7940 DP(NETIF_MSG_HW
, "starting func init func %d\n", func
);
7942 /* FLR cleanup - hmmm */
7943 if (!CHIP_IS_E1x(bp
)) {
7944 rc
= bnx2x_pf_flr_clnup(bp
);
7951 /* set MSI reconfigure capability */
7952 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
7953 addr
= (port
? HC_REG_CONFIG_1
: HC_REG_CONFIG_0
);
7954 val
= REG_RD(bp
, addr
);
7955 val
|= HC_CONFIG_0_REG_MSI_ATTN_EN_0
;
7956 REG_WR(bp
, addr
, val
);
7959 bnx2x_init_block(bp
, BLOCK_PXP
, init_phase
);
7960 bnx2x_init_block(bp
, BLOCK_PXP2
, init_phase
);
7963 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7966 cdu_ilt_start
+= BNX2X_FIRST_VF_CID
/ILT_PAGE_CIDS
;
7967 cdu_ilt_start
= bnx2x_iov_init_ilt(bp
, cdu_ilt_start
);
7969 /* since BNX2X_FIRST_VF_CID > 0 the PF L2 cids precedes
7970 * those of the VFs, so start line should be reset
7972 cdu_ilt_start
= ilt
->clients
[ILT_CLIENT_CDU
].start
;
7973 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++) {
7974 ilt
->lines
[cdu_ilt_start
+ i
].page
= bp
->context
[i
].vcxt
;
7975 ilt
->lines
[cdu_ilt_start
+ i
].page_mapping
=
7976 bp
->context
[i
].cxt_mapping
;
7977 ilt
->lines
[cdu_ilt_start
+ i
].size
= bp
->context
[i
].size
;
7980 bnx2x_ilt_init_op(bp
, INITOP_SET
);
7982 if (!CONFIGURE_NIC_MODE(bp
)) {
7983 bnx2x_init_searcher(bp
);
7984 REG_WR(bp
, PRS_REG_NIC_MODE
, 0);
7985 DP(NETIF_MSG_IFUP
, "NIC MODE disabled\n");
7988 REG_WR(bp
, PRS_REG_NIC_MODE
, 1);
7989 DP(NETIF_MSG_IFUP
, "NIC MODE configured\n");
7992 if (!CHIP_IS_E1x(bp
)) {
7993 u32 pf_conf
= IGU_PF_CONF_FUNC_EN
;
7995 /* Turn on a single ISR mode in IGU if driver is going to use
7998 if (!(bp
->flags
& USING_MSIX_FLAG
))
7999 pf_conf
|= IGU_PF_CONF_SINGLE_ISR_EN
;
8001 * Timers workaround bug: function init part.
8002 * Need to wait 20msec after initializing ILT,
8003 * needed to make sure there are no requests in
8004 * one of the PXP internal queues with "old" ILT addresses
8008 * Master enable - Due to WB DMAE writes performed before this
8009 * register is re-initialized as part of the regular function
8012 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 1);
8013 /* Enable the function in IGU */
8014 REG_WR(bp
, IGU_REG_PF_CONFIGURATION
, pf_conf
);
8019 bnx2x_init_block(bp
, BLOCK_PGLUE_B
, init_phase
);
8021 bnx2x_clean_pglue_errors(bp
);
8023 bnx2x_init_block(bp
, BLOCK_ATC
, init_phase
);
8024 bnx2x_init_block(bp
, BLOCK_DMAE
, init_phase
);
8025 bnx2x_init_block(bp
, BLOCK_NIG
, init_phase
);
8026 bnx2x_init_block(bp
, BLOCK_SRC
, init_phase
);
8027 bnx2x_init_block(bp
, BLOCK_MISC
, init_phase
);
8028 bnx2x_init_block(bp
, BLOCK_TCM
, init_phase
);
8029 bnx2x_init_block(bp
, BLOCK_UCM
, init_phase
);
8030 bnx2x_init_block(bp
, BLOCK_CCM
, init_phase
);
8031 bnx2x_init_block(bp
, BLOCK_XCM
, init_phase
);
8032 bnx2x_init_block(bp
, BLOCK_TSEM
, init_phase
);
8033 bnx2x_init_block(bp
, BLOCK_USEM
, init_phase
);
8034 bnx2x_init_block(bp
, BLOCK_CSEM
, init_phase
);
8035 bnx2x_init_block(bp
, BLOCK_XSEM
, init_phase
);
8037 if (!CHIP_IS_E1x(bp
))
8038 REG_WR(bp
, QM_REG_PF_EN
, 1);
8040 if (!CHIP_IS_E1x(bp
)) {
8041 REG_WR(bp
, TSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8042 REG_WR(bp
, USEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8043 REG_WR(bp
, CSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8044 REG_WR(bp
, XSEM_REG_VFPF_ERR_NUM
, BNX2X_MAX_NUM_OF_VFS
+ func
);
8046 bnx2x_init_block(bp
, BLOCK_QM
, init_phase
);
8048 bnx2x_init_block(bp
, BLOCK_TM
, init_phase
);
8049 bnx2x_init_block(bp
, BLOCK_DORQ
, init_phase
);
8050 REG_WR(bp
, DORQ_REG_MODE_ACT
, 1); /* no dpm */
8052 bnx2x_iov_init_dq(bp
);
8054 bnx2x_init_block(bp
, BLOCK_BRB1
, init_phase
);
8055 bnx2x_init_block(bp
, BLOCK_PRS
, init_phase
);
8056 bnx2x_init_block(bp
, BLOCK_TSDM
, init_phase
);
8057 bnx2x_init_block(bp
, BLOCK_CSDM
, init_phase
);
8058 bnx2x_init_block(bp
, BLOCK_USDM
, init_phase
);
8059 bnx2x_init_block(bp
, BLOCK_XSDM
, init_phase
);
8060 bnx2x_init_block(bp
, BLOCK_UPB
, init_phase
);
8061 bnx2x_init_block(bp
, BLOCK_XPB
, init_phase
);
8062 bnx2x_init_block(bp
, BLOCK_PBF
, init_phase
);
8063 if (!CHIP_IS_E1x(bp
))
8064 REG_WR(bp
, PBF_REG_DISABLE_PF
, 0);
8066 bnx2x_init_block(bp
, BLOCK_CDU
, init_phase
);
8068 bnx2x_init_block(bp
, BLOCK_CFC
, init_phase
);
8070 if (!CHIP_IS_E1x(bp
))
8071 REG_WR(bp
, CFC_REG_WEAK_ENABLE_PF
, 1);
8074 if (!(IS_MF_UFP(bp
) && BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
))) {
8075 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
* 8, 1);
8076 REG_WR(bp
, NIG_REG_LLH0_FUNC_VLAN_ID
+ port
* 8,
8081 bnx2x_init_block(bp
, BLOCK_MISC_AEU
, init_phase
);
8083 /* HC init per function */
8084 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
8085 if (CHIP_IS_E1H(bp
)) {
8086 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
8088 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
8089 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
8091 bnx2x_init_block(bp
, BLOCK_HC
, init_phase
);
8094 int num_segs
, sb_idx
, prod_offset
;
8096 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ func
*4, 0);
8098 if (!CHIP_IS_E1x(bp
)) {
8099 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
8100 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
8103 bnx2x_init_block(bp
, BLOCK_IGU
, init_phase
);
8105 if (!CHIP_IS_E1x(bp
)) {
8109 * E2 mode: address 0-135 match to the mapping memory;
8110 * 136 - PF0 default prod; 137 - PF1 default prod;
8111 * 138 - PF2 default prod; 139 - PF3 default prod;
8112 * 140 - PF0 attn prod; 141 - PF1 attn prod;
8113 * 142 - PF2 attn prod; 143 - PF3 attn prod;
8116 * E1.5 mode - In backward compatible mode;
8117 * for non default SB; each even line in the memory
8118 * holds the U producer and each odd line hold
8119 * the C producer. The first 128 producers are for
8120 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20
8121 * producers are for the DSB for each PF.
8122 * Each PF has five segments: (the order inside each
8123 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods;
8124 * 132-135 C prods; 136-139 X prods; 140-143 T prods;
8125 * 144-147 attn prods;
8127 /* non-default-status-blocks */
8128 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
8129 IGU_BC_NDSB_NUM_SEGS
: IGU_NORM_NDSB_NUM_SEGS
;
8130 for (sb_idx
= 0; sb_idx
< bp
->igu_sb_cnt
; sb_idx
++) {
8131 prod_offset
= (bp
->igu_base_sb
+ sb_idx
) *
8134 for (i
= 0; i
< num_segs
; i
++) {
8135 addr
= IGU_REG_PROD_CONS_MEMORY
+
8136 (prod_offset
+ i
) * 4;
8137 REG_WR(bp
, addr
, 0);
8139 /* send consumer update with value 0 */
8140 bnx2x_ack_sb(bp
, bp
->igu_base_sb
+ sb_idx
,
8141 USTORM_ID
, 0, IGU_INT_NOP
, 1);
8142 bnx2x_igu_clear_sb(bp
,
8143 bp
->igu_base_sb
+ sb_idx
);
8146 /* default-status-blocks */
8147 num_segs
= CHIP_INT_MODE_IS_BC(bp
) ?
8148 IGU_BC_DSB_NUM_SEGS
: IGU_NORM_DSB_NUM_SEGS
;
8150 if (CHIP_MODE_IS_4_PORT(bp
))
8151 dsb_idx
= BP_FUNC(bp
);
8153 dsb_idx
= BP_VN(bp
);
8155 prod_offset
= (CHIP_INT_MODE_IS_BC(bp
) ?
8156 IGU_BC_BASE_DSB_PROD
+ dsb_idx
:
8157 IGU_NORM_BASE_DSB_PROD
+ dsb_idx
);
8160 * igu prods come in chunks of E1HVN_MAX (4) -
8161 * does not matters what is the current chip mode
8163 for (i
= 0; i
< (num_segs
* E1HVN_MAX
);
8165 addr
= IGU_REG_PROD_CONS_MEMORY
+
8166 (prod_offset
+ i
)*4;
8167 REG_WR(bp
, addr
, 0);
8169 /* send consumer update with 0 */
8170 if (CHIP_INT_MODE_IS_BC(bp
)) {
8171 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8172 USTORM_ID
, 0, IGU_INT_NOP
, 1);
8173 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8174 CSTORM_ID
, 0, IGU_INT_NOP
, 1);
8175 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8176 XSTORM_ID
, 0, IGU_INT_NOP
, 1);
8177 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8178 TSTORM_ID
, 0, IGU_INT_NOP
, 1);
8179 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8180 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
8182 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8183 USTORM_ID
, 0, IGU_INT_NOP
, 1);
8184 bnx2x_ack_sb(bp
, bp
->igu_dsb_id
,
8185 ATTENTION_ID
, 0, IGU_INT_NOP
, 1);
8187 bnx2x_igu_clear_sb(bp
, bp
->igu_dsb_id
);
8189 /* !!! These should become driver const once
8190 rf-tool supports split-68 const */
8191 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_LSB
, 0);
8192 REG_WR(bp
, IGU_REG_SB_INT_BEFORE_MASK_MSB
, 0);
8193 REG_WR(bp
, IGU_REG_SB_MASK_LSB
, 0);
8194 REG_WR(bp
, IGU_REG_SB_MASK_MSB
, 0);
8195 REG_WR(bp
, IGU_REG_PBA_STATUS_LSB
, 0);
8196 REG_WR(bp
, IGU_REG_PBA_STATUS_MSB
, 0);
8200 /* Reset PCIE errors for debug */
8201 REG_WR(bp
, 0x2114, 0xffffffff);
8202 REG_WR(bp
, 0x2120, 0xffffffff);
8204 if (CHIP_IS_E1x(bp
)) {
8205 main_mem_size
= HC_REG_MAIN_MEMORY_SIZE
/ 2; /*dwords*/
8206 main_mem_base
= HC_REG_MAIN_MEMORY
+
8207 BP_PORT(bp
) * (main_mem_size
* 4);
8208 main_mem_prty_clr
= HC_REG_HC_PRTY_STS_CLR
;
8211 val
= REG_RD(bp
, main_mem_prty_clr
);
8214 "Hmmm... Parity errors in HC block during function init (0x%x)!\n",
8217 /* Clear "false" parity errors in MSI-X table */
8218 for (i
= main_mem_base
;
8219 i
< main_mem_base
+ main_mem_size
* 4;
8220 i
+= main_mem_width
) {
8221 bnx2x_read_dmae(bp
, i
, main_mem_width
/ 4);
8222 bnx2x_write_dmae(bp
, bnx2x_sp_mapping(bp
, wb_data
),
8223 i
, main_mem_width
/ 4);
8225 /* Clear HC parity attention */
8226 REG_RD(bp
, main_mem_prty_clr
);
8229 #ifdef BNX2X_STOP_ON_ERROR
8230 /* Enable STORMs SP logging */
8231 REG_WR8(bp
, BAR_USTRORM_INTMEM
+
8232 USTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8233 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+
8234 TSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8235 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8236 CSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8237 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+
8238 XSTORM_RECORD_SLOW_PATH_OFFSET(BP_FUNC(bp
)), 1);
8241 bnx2x_phy_probe(&bp
->link_params
);
8246 void bnx2x_free_mem_cnic(struct bnx2x
*bp
)
8248 bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_FREE
);
8250 if (!CHIP_IS_E1x(bp
))
8251 BNX2X_PCI_FREE(bp
->cnic_sb
.e2_sb
, bp
->cnic_sb_mapping
,
8252 sizeof(struct host_hc_status_block_e2
));
8254 BNX2X_PCI_FREE(bp
->cnic_sb
.e1x_sb
, bp
->cnic_sb_mapping
,
8255 sizeof(struct host_hc_status_block_e1x
));
8257 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
8260 void bnx2x_free_mem(struct bnx2x
*bp
)
8264 BNX2X_PCI_FREE(bp
->fw_stats
, bp
->fw_stats_mapping
,
8265 bp
->fw_stats_data_sz
+ bp
->fw_stats_req_sz
);
8270 BNX2X_PCI_FREE(bp
->def_status_blk
, bp
->def_status_blk_mapping
,
8271 sizeof(struct host_sp_status_block
));
8273 BNX2X_PCI_FREE(bp
->slowpath
, bp
->slowpath_mapping
,
8274 sizeof(struct bnx2x_slowpath
));
8276 for (i
= 0; i
< L2_ILT_LINES(bp
); i
++)
8277 BNX2X_PCI_FREE(bp
->context
[i
].vcxt
, bp
->context
[i
].cxt_mapping
,
8278 bp
->context
[i
].size
);
8279 bnx2x_ilt_mem_op(bp
, ILT_MEMOP_FREE
);
8281 BNX2X_FREE(bp
->ilt
->lines
);
8283 BNX2X_PCI_FREE(bp
->spq
, bp
->spq_mapping
, BCM_PAGE_SIZE
);
8285 BNX2X_PCI_FREE(bp
->eq_ring
, bp
->eq_mapping
,
8286 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
8288 BNX2X_PCI_FREE(bp
->t2
, bp
->t2_mapping
, SRC_T2_SZ
);
8290 bnx2x_iov_free_mem(bp
);
8293 int bnx2x_alloc_mem_cnic(struct bnx2x
*bp
)
8295 if (!CHIP_IS_E1x(bp
)) {
8296 /* size = the status block + ramrod buffers */
8297 bp
->cnic_sb
.e2_sb
= BNX2X_PCI_ALLOC(&bp
->cnic_sb_mapping
,
8298 sizeof(struct host_hc_status_block_e2
));
8299 if (!bp
->cnic_sb
.e2_sb
)
8302 bp
->cnic_sb
.e1x_sb
= BNX2X_PCI_ALLOC(&bp
->cnic_sb_mapping
,
8303 sizeof(struct host_hc_status_block_e1x
));
8304 if (!bp
->cnic_sb
.e1x_sb
)
8308 if (CONFIGURE_NIC_MODE(bp
) && !bp
->t2
) {
8309 /* allocate searcher T2 table, as it wasn't allocated before */
8310 bp
->t2
= BNX2X_PCI_ALLOC(&bp
->t2_mapping
, SRC_T2_SZ
);
8315 /* write address to which L5 should insert its values */
8316 bp
->cnic_eth_dev
.addr_drv_info_to_mcp
=
8317 &bp
->slowpath
->drv_info_to_mcp
;
8319 if (bnx2x_ilt_mem_op_cnic(bp
, ILT_MEMOP_ALLOC
))
8325 bnx2x_free_mem_cnic(bp
);
8326 BNX2X_ERR("Can't allocate memory\n");
8330 int bnx2x_alloc_mem(struct bnx2x
*bp
)
8332 int i
, allocated
, context_size
;
8334 if (!CONFIGURE_NIC_MODE(bp
) && !bp
->t2
) {
8335 /* allocate searcher T2 table */
8336 bp
->t2
= BNX2X_PCI_ALLOC(&bp
->t2_mapping
, SRC_T2_SZ
);
8341 bp
->def_status_blk
= BNX2X_PCI_ALLOC(&bp
->def_status_blk_mapping
,
8342 sizeof(struct host_sp_status_block
));
8343 if (!bp
->def_status_blk
)
8346 bp
->slowpath
= BNX2X_PCI_ALLOC(&bp
->slowpath_mapping
,
8347 sizeof(struct bnx2x_slowpath
));
8351 /* Allocate memory for CDU context:
8352 * This memory is allocated separately and not in the generic ILT
8353 * functions because CDU differs in few aspects:
8354 * 1. There are multiple entities allocating memory for context -
8355 * 'regular' driver, CNIC and SRIOV driver. Each separately controls
8356 * its own ILT lines.
8357 * 2. Since CDU page-size is not a single 4KB page (which is the case
8358 * for the other ILT clients), to be efficient we want to support
8359 * allocation of sub-page-size in the last entry.
8360 * 3. Context pointers are used by the driver to pass to FW / update
8361 * the context (for the other ILT clients the pointers are used just to
8362 * free the memory during unload).
8364 context_size
= sizeof(union cdu_context
) * BNX2X_L2_CID_COUNT(bp
);
8366 for (i
= 0, allocated
= 0; allocated
< context_size
; i
++) {
8367 bp
->context
[i
].size
= min(CDU_ILT_PAGE_SZ
,
8368 (context_size
- allocated
));
8369 bp
->context
[i
].vcxt
= BNX2X_PCI_ALLOC(&bp
->context
[i
].cxt_mapping
,
8370 bp
->context
[i
].size
);
8371 if (!bp
->context
[i
].vcxt
)
8373 allocated
+= bp
->context
[i
].size
;
8375 bp
->ilt
->lines
= kcalloc(ILT_MAX_LINES
, sizeof(struct ilt_line
),
8377 if (!bp
->ilt
->lines
)
8380 if (bnx2x_ilt_mem_op(bp
, ILT_MEMOP_ALLOC
))
8383 if (bnx2x_iov_alloc_mem(bp
))
8386 /* Slow path ring */
8387 bp
->spq
= BNX2X_PCI_ALLOC(&bp
->spq_mapping
, BCM_PAGE_SIZE
);
8392 bp
->eq_ring
= BNX2X_PCI_ALLOC(&bp
->eq_mapping
,
8393 BCM_PAGE_SIZE
* NUM_EQ_PAGES
);
8401 BNX2X_ERR("Can't allocate memory\n");
8406 * Init service functions
8409 int bnx2x_set_mac_one(struct bnx2x
*bp
, u8
*mac
,
8410 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
8411 int mac_type
, unsigned long *ramrod_flags
)
8414 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
8416 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
8418 /* Fill general parameters */
8419 ramrod_param
.vlan_mac_obj
= obj
;
8420 ramrod_param
.ramrod_flags
= *ramrod_flags
;
8422 /* Fill a user request section if needed */
8423 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
8424 memcpy(ramrod_param
.user_req
.u
.mac
.mac
, mac
, ETH_ALEN
);
8426 __set_bit(mac_type
, &ramrod_param
.user_req
.vlan_mac_flags
);
8428 /* Set the command: ADD or DEL */
8430 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
8432 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
8435 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
8437 if (rc
== -EEXIST
) {
8438 DP(BNX2X_MSG_SP
, "Failed to schedule ADD operations: %d\n", rc
);
8439 /* do not treat adding same MAC as error */
8442 BNX2X_ERR("%s MAC failed\n", (set
? "Set" : "Del"));
8447 int bnx2x_set_vlan_one(struct bnx2x
*bp
, u16 vlan
,
8448 struct bnx2x_vlan_mac_obj
*obj
, bool set
,
8449 unsigned long *ramrod_flags
)
8452 struct bnx2x_vlan_mac_ramrod_params ramrod_param
;
8454 memset(&ramrod_param
, 0, sizeof(ramrod_param
));
8456 /* Fill general parameters */
8457 ramrod_param
.vlan_mac_obj
= obj
;
8458 ramrod_param
.ramrod_flags
= *ramrod_flags
;
8460 /* Fill a user request section if needed */
8461 if (!test_bit(RAMROD_CONT
, ramrod_flags
)) {
8462 ramrod_param
.user_req
.u
.vlan
.vlan
= vlan
;
8463 /* Set the command: ADD or DEL */
8465 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_ADD
;
8467 ramrod_param
.user_req
.cmd
= BNX2X_VLAN_MAC_DEL
;
8470 rc
= bnx2x_config_vlan_mac(bp
, &ramrod_param
);
8472 if (rc
== -EEXIST
) {
8473 /* Do not treat adding same vlan as error. */
8474 DP(BNX2X_MSG_SP
, "Failed to schedule ADD operations: %d\n", rc
);
8476 } else if (rc
< 0) {
8477 BNX2X_ERR("%s VLAN failed\n", (set
? "Set" : "Del"));
8483 int bnx2x_del_all_macs(struct bnx2x
*bp
,
8484 struct bnx2x_vlan_mac_obj
*mac_obj
,
8485 int mac_type
, bool wait_for_comp
)
8488 unsigned long ramrod_flags
= 0, vlan_mac_flags
= 0;
8490 /* Wait for completion of requested */
8492 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
8494 /* Set the mac type of addresses we want to clear */
8495 __set_bit(mac_type
, &vlan_mac_flags
);
8497 rc
= mac_obj
->delete_all(bp
, mac_obj
, &vlan_mac_flags
, &ramrod_flags
);
8499 BNX2X_ERR("Failed to delete MACs: %d\n", rc
);
8504 int bnx2x_set_eth_mac(struct bnx2x
*bp
, bool set
)
8507 unsigned long ramrod_flags
= 0;
8509 DP(NETIF_MSG_IFUP
, "Adding Eth MAC\n");
8510 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
8511 return bnx2x_set_mac_one(bp
, bp
->dev
->dev_addr
,
8512 &bp
->sp_objs
->mac_obj
, set
,
8513 BNX2X_ETH_MAC
, &ramrod_flags
);
8515 return bnx2x_vfpf_config_mac(bp
, bp
->dev
->dev_addr
,
8516 bp
->fp
->index
, set
);
8520 int bnx2x_setup_leading(struct bnx2x
*bp
)
8523 return bnx2x_setup_queue(bp
, &bp
->fp
[0], true);
8525 return bnx2x_vfpf_setup_q(bp
, &bp
->fp
[0], true);
8529 * bnx2x_set_int_mode - configure interrupt mode
8531 * @bp: driver handle
8533 * In case of MSI-X it will also try to enable MSI-X.
8535 int bnx2x_set_int_mode(struct bnx2x
*bp
)
8539 if (IS_VF(bp
) && int_mode
!= BNX2X_INT_MODE_MSIX
) {
8540 BNX2X_ERR("VF not loaded since interrupt mode not msix\n");
8545 case BNX2X_INT_MODE_MSIX
:
8546 /* attempt to enable msix */
8547 rc
= bnx2x_enable_msix(bp
);
8553 /* vfs use only msix */
8554 if (rc
&& IS_VF(bp
))
8557 /* failed to enable multiple MSI-X */
8558 BNX2X_DEV_INFO("Failed to enable multiple MSI-X (%d), set number of queues to %d\n",
8560 1 + bp
->num_cnic_queues
);
8562 /* falling through... */
8563 case BNX2X_INT_MODE_MSI
:
8564 bnx2x_enable_msi(bp
);
8566 /* falling through... */
8567 case BNX2X_INT_MODE_INTX
:
8568 bp
->num_ethernet_queues
= 1;
8569 bp
->num_queues
= bp
->num_ethernet_queues
+ bp
->num_cnic_queues
;
8570 BNX2X_DEV_INFO("set number of queues to 1\n");
8573 BNX2X_DEV_INFO("unknown value in int_mode module parameter\n");
8579 /* must be called prior to any HW initializations */
8580 static inline u16
bnx2x_cid_ilt_lines(struct bnx2x
*bp
)
8583 return (BNX2X_FIRST_VF_CID
+ BNX2X_VF_CIDS
)/ILT_PAGE_CIDS
;
8584 return L2_ILT_LINES(bp
);
8587 void bnx2x_ilt_set_info(struct bnx2x
*bp
)
8589 struct ilt_client_info
*ilt_client
;
8590 struct bnx2x_ilt
*ilt
= BP_ILT(bp
);
8593 ilt
->start_line
= FUNC_ILT_BASE(BP_FUNC(bp
));
8594 DP(BNX2X_MSG_SP
, "ilt starts at line %d\n", ilt
->start_line
);
8597 ilt_client
= &ilt
->clients
[ILT_CLIENT_CDU
];
8598 ilt_client
->client_num
= ILT_CLIENT_CDU
;
8599 ilt_client
->page_size
= CDU_ILT_PAGE_SZ
;
8600 ilt_client
->flags
= ILT_CLIENT_SKIP_MEM
;
8601 ilt_client
->start
= line
;
8602 line
+= bnx2x_cid_ilt_lines(bp
);
8604 if (CNIC_SUPPORT(bp
))
8605 line
+= CNIC_ILT_LINES
;
8606 ilt_client
->end
= line
- 1;
8608 DP(NETIF_MSG_IFUP
, "ilt client[CDU]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8611 ilt_client
->page_size
,
8613 ilog2(ilt_client
->page_size
>> 12));
8616 if (QM_INIT(bp
->qm_cid_count
)) {
8617 ilt_client
= &ilt
->clients
[ILT_CLIENT_QM
];
8618 ilt_client
->client_num
= ILT_CLIENT_QM
;
8619 ilt_client
->page_size
= QM_ILT_PAGE_SZ
;
8620 ilt_client
->flags
= 0;
8621 ilt_client
->start
= line
;
8623 /* 4 bytes for each cid */
8624 line
+= DIV_ROUND_UP(bp
->qm_cid_count
* QM_QUEUES_PER_FUNC
* 4,
8627 ilt_client
->end
= line
- 1;
8630 "ilt client[QM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8633 ilt_client
->page_size
,
8635 ilog2(ilt_client
->page_size
>> 12));
8638 if (CNIC_SUPPORT(bp
)) {
8640 ilt_client
= &ilt
->clients
[ILT_CLIENT_SRC
];
8641 ilt_client
->client_num
= ILT_CLIENT_SRC
;
8642 ilt_client
->page_size
= SRC_ILT_PAGE_SZ
;
8643 ilt_client
->flags
= 0;
8644 ilt_client
->start
= line
;
8645 line
+= SRC_ILT_LINES
;
8646 ilt_client
->end
= line
- 1;
8649 "ilt client[SRC]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8652 ilt_client
->page_size
,
8654 ilog2(ilt_client
->page_size
>> 12));
8657 ilt_client
= &ilt
->clients
[ILT_CLIENT_TM
];
8658 ilt_client
->client_num
= ILT_CLIENT_TM
;
8659 ilt_client
->page_size
= TM_ILT_PAGE_SZ
;
8660 ilt_client
->flags
= 0;
8661 ilt_client
->start
= line
;
8662 line
+= TM_ILT_LINES
;
8663 ilt_client
->end
= line
- 1;
8666 "ilt client[TM]: start %d, end %d, psz 0x%x, flags 0x%x, hw psz %d\n",
8669 ilt_client
->page_size
,
8671 ilog2(ilt_client
->page_size
>> 12));
8674 BUG_ON(line
> ILT_MAX_LINES
);
8678 * bnx2x_pf_q_prep_init - prepare INIT transition parameters
8680 * @bp: driver handle
8681 * @fp: pointer to fastpath
8682 * @init_params: pointer to parameters structure
8684 * parameters configured:
8685 * - HC configuration
8686 * - Queue's CDU context
8688 static void bnx2x_pf_q_prep_init(struct bnx2x
*bp
,
8689 struct bnx2x_fastpath
*fp
, struct bnx2x_queue_init_params
*init_params
)
8692 int cxt_index
, cxt_offset
;
8694 /* FCoE Queue uses Default SB, thus has no HC capabilities */
8695 if (!IS_FCOE_FP(fp
)) {
8696 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->rx
.flags
);
8697 __set_bit(BNX2X_Q_FLG_HC
, &init_params
->tx
.flags
);
8699 /* If HC is supported, enable host coalescing in the transition
8702 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->rx
.flags
);
8703 __set_bit(BNX2X_Q_FLG_HC_EN
, &init_params
->tx
.flags
);
8706 init_params
->rx
.hc_rate
= bp
->rx_ticks
?
8707 (1000000 / bp
->rx_ticks
) : 0;
8708 init_params
->tx
.hc_rate
= bp
->tx_ticks
?
8709 (1000000 / bp
->tx_ticks
) : 0;
8712 init_params
->rx
.fw_sb_id
= init_params
->tx
.fw_sb_id
=
8716 * CQ index among the SB indices: FCoE clients uses the default
8717 * SB, therefore it's different.
8719 init_params
->rx
.sb_cq_index
= HC_INDEX_ETH_RX_CQ_CONS
;
8720 init_params
->tx
.sb_cq_index
= HC_INDEX_ETH_FIRST_TX_CQ_CONS
;
8723 /* set maximum number of COSs supported by this queue */
8724 init_params
->max_cos
= fp
->max_cos
;
8726 DP(NETIF_MSG_IFUP
, "fp: %d setting queue params max cos to: %d\n",
8727 fp
->index
, init_params
->max_cos
);
8729 /* set the context pointers queue object */
8730 for (cos
= FIRST_TX_COS_INDEX
; cos
< init_params
->max_cos
; cos
++) {
8731 cxt_index
= fp
->txdata_ptr
[cos
]->cid
/ ILT_PAGE_CIDS
;
8732 cxt_offset
= fp
->txdata_ptr
[cos
]->cid
- (cxt_index
*
8734 init_params
->cxts
[cos
] =
8735 &bp
->context
[cxt_index
].vcxt
[cxt_offset
].eth
;
8739 static int bnx2x_setup_tx_only(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8740 struct bnx2x_queue_state_params
*q_params
,
8741 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
,
8742 int tx_index
, bool leading
)
8744 memset(tx_only_params
, 0, sizeof(*tx_only_params
));
8746 /* Set the command */
8747 q_params
->cmd
= BNX2X_Q_CMD_SETUP_TX_ONLY
;
8749 /* Set tx-only QUEUE flags: don't zero statistics */
8750 tx_only_params
->flags
= bnx2x_get_common_flags(bp
, fp
, false);
8752 /* choose the index of the cid to send the slow path on */
8753 tx_only_params
->cid_index
= tx_index
;
8755 /* Set general TX_ONLY_SETUP parameters */
8756 bnx2x_pf_q_prep_general(bp
, fp
, &tx_only_params
->gen_params
, tx_index
);
8758 /* Set Tx TX_ONLY_SETUP parameters */
8759 bnx2x_pf_tx_q_prep(bp
, fp
, &tx_only_params
->txq_params
, tx_index
);
8762 "preparing to send tx-only ramrod for connection: cos %d, primary cid %d, cid %d, client id %d, sp-client id %d, flags %lx\n",
8763 tx_index
, q_params
->q_obj
->cids
[FIRST_TX_COS_INDEX
],
8764 q_params
->q_obj
->cids
[tx_index
], q_params
->q_obj
->cl_id
,
8765 tx_only_params
->gen_params
.spcl_id
, tx_only_params
->flags
);
8767 /* send the ramrod */
8768 return bnx2x_queue_state_change(bp
, q_params
);
8772 * bnx2x_setup_queue - setup queue
8774 * @bp: driver handle
8775 * @fp: pointer to fastpath
8776 * @leading: is leading
8778 * This function performs 2 steps in a Queue state machine
8779 * actually: 1) RESET->INIT 2) INIT->SETUP
8782 int bnx2x_setup_queue(struct bnx2x
*bp
, struct bnx2x_fastpath
*fp
,
8785 struct bnx2x_queue_state_params q_params
= {NULL
};
8786 struct bnx2x_queue_setup_params
*setup_params
=
8787 &q_params
.params
.setup
;
8788 struct bnx2x_queue_setup_tx_only_params
*tx_only_params
=
8789 &q_params
.params
.tx_only
;
8793 DP(NETIF_MSG_IFUP
, "setting up queue %d\n", fp
->index
);
8795 /* reset IGU state skip FCoE L2 queue */
8796 if (!IS_FCOE_FP(fp
))
8797 bnx2x_ack_sb(bp
, fp
->igu_sb_id
, USTORM_ID
, 0,
8800 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8801 /* We want to wait for completion in this context */
8802 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8804 /* Prepare the INIT parameters */
8805 bnx2x_pf_q_prep_init(bp
, fp
, &q_params
.params
.init
);
8807 /* Set the command */
8808 q_params
.cmd
= BNX2X_Q_CMD_INIT
;
8810 /* Change the state to INIT */
8811 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8813 BNX2X_ERR("Queue(%d) INIT failed\n", fp
->index
);
8817 DP(NETIF_MSG_IFUP
, "init complete\n");
8819 /* Now move the Queue to the SETUP state... */
8820 memset(setup_params
, 0, sizeof(*setup_params
));
8822 /* Set QUEUE flags */
8823 setup_params
->flags
= bnx2x_get_q_flags(bp
, fp
, leading
);
8825 /* Set general SETUP parameters */
8826 bnx2x_pf_q_prep_general(bp
, fp
, &setup_params
->gen_params
,
8827 FIRST_TX_COS_INDEX
);
8829 bnx2x_pf_rx_q_prep(bp
, fp
, &setup_params
->pause_params
,
8830 &setup_params
->rxq_params
);
8832 bnx2x_pf_tx_q_prep(bp
, fp
, &setup_params
->txq_params
,
8833 FIRST_TX_COS_INDEX
);
8835 /* Set the command */
8836 q_params
.cmd
= BNX2X_Q_CMD_SETUP
;
8839 bp
->fcoe_init
= true;
8841 /* Change the state to SETUP */
8842 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8844 BNX2X_ERR("Queue(%d) SETUP failed\n", fp
->index
);
8848 /* loop through the relevant tx-only indices */
8849 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8850 tx_index
< fp
->max_cos
;
8853 /* prepare and send tx-only ramrod*/
8854 rc
= bnx2x_setup_tx_only(bp
, fp
, &q_params
,
8855 tx_only_params
, tx_index
, leading
);
8857 BNX2X_ERR("Queue(%d.%d) TX_ONLY_SETUP failed\n",
8858 fp
->index
, tx_index
);
8866 static int bnx2x_stop_queue(struct bnx2x
*bp
, int index
)
8868 struct bnx2x_fastpath
*fp
= &bp
->fp
[index
];
8869 struct bnx2x_fp_txdata
*txdata
;
8870 struct bnx2x_queue_state_params q_params
= {NULL
};
8873 DP(NETIF_MSG_IFDOWN
, "stopping queue %d cid %d\n", index
, fp
->cid
);
8875 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
8876 /* We want to wait for completion in this context */
8877 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
8879 /* close tx-only connections */
8880 for (tx_index
= FIRST_TX_ONLY_COS_INDEX
;
8881 tx_index
< fp
->max_cos
;
8884 /* ascertain this is a normal queue*/
8885 txdata
= fp
->txdata_ptr
[tx_index
];
8887 DP(NETIF_MSG_IFDOWN
, "stopping tx-only queue %d\n",
8890 /* send halt terminate on tx-only connection */
8891 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8892 memset(&q_params
.params
.terminate
, 0,
8893 sizeof(q_params
.params
.terminate
));
8894 q_params
.params
.terminate
.cid_index
= tx_index
;
8896 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8900 /* send halt terminate on tx-only connection */
8901 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8902 memset(&q_params
.params
.cfc_del
, 0,
8903 sizeof(q_params
.params
.cfc_del
));
8904 q_params
.params
.cfc_del
.cid_index
= tx_index
;
8905 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8909 /* Stop the primary connection: */
8910 /* ...halt the connection */
8911 q_params
.cmd
= BNX2X_Q_CMD_HALT
;
8912 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8916 /* ...terminate the connection */
8917 q_params
.cmd
= BNX2X_Q_CMD_TERMINATE
;
8918 memset(&q_params
.params
.terminate
, 0,
8919 sizeof(q_params
.params
.terminate
));
8920 q_params
.params
.terminate
.cid_index
= FIRST_TX_COS_INDEX
;
8921 rc
= bnx2x_queue_state_change(bp
, &q_params
);
8924 /* ...delete cfc entry */
8925 q_params
.cmd
= BNX2X_Q_CMD_CFC_DEL
;
8926 memset(&q_params
.params
.cfc_del
, 0,
8927 sizeof(q_params
.params
.cfc_del
));
8928 q_params
.params
.cfc_del
.cid_index
= FIRST_TX_COS_INDEX
;
8929 return bnx2x_queue_state_change(bp
, &q_params
);
8932 static void bnx2x_reset_func(struct bnx2x
*bp
)
8934 int port
= BP_PORT(bp
);
8935 int func
= BP_FUNC(bp
);
8938 /* Disable the function in the FW */
8939 REG_WR8(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_FUNC_EN_OFFSET(func
), 0);
8940 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+ CSTORM_FUNC_EN_OFFSET(func
), 0);
8941 REG_WR8(bp
, BAR_TSTRORM_INTMEM
+ TSTORM_FUNC_EN_OFFSET(func
), 0);
8942 REG_WR8(bp
, BAR_USTRORM_INTMEM
+ USTORM_FUNC_EN_OFFSET(func
), 0);
8945 for_each_eth_queue(bp
, i
) {
8946 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
8947 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8948 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp
->fw_sb_id
),
8952 if (CNIC_LOADED(bp
))
8954 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8955 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET
8956 (bnx2x_cnic_fw_sb_id(bp
)), SB_DISABLED
);
8959 REG_WR8(bp
, BAR_CSTRORM_INTMEM
+
8960 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func
),
8963 for (i
= 0; i
< XSTORM_SPQ_DATA_SIZE
/ 4; i
++)
8964 REG_WR(bp
, BAR_XSTRORM_INTMEM
+ XSTORM_SPQ_DATA_OFFSET(func
),
8968 if (bp
->common
.int_block
== INT_BLOCK_HC
) {
8969 REG_WR(bp
, HC_REG_LEADING_EDGE_0
+ port
*8, 0);
8970 REG_WR(bp
, HC_REG_TRAILING_EDGE_0
+ port
*8, 0);
8972 REG_WR(bp
, IGU_REG_LEADING_EDGE_LATCH
, 0);
8973 REG_WR(bp
, IGU_REG_TRAILING_EDGE_LATCH
, 0);
8976 if (CNIC_LOADED(bp
)) {
8977 /* Disable Timer scan */
8978 REG_WR(bp
, TM_REG_EN_LINEAR0_TIMER
+ port
*4, 0);
8980 * Wait for at least 10ms and up to 2 second for the timers
8983 for (i
= 0; i
< 200; i
++) {
8984 usleep_range(10000, 20000);
8985 if (!REG_RD(bp
, TM_REG_LIN0_SCAN_ON
+ port
*4))
8990 bnx2x_clear_func_ilt(bp
, func
);
8992 /* Timers workaround bug for E2: if this is vnic-3,
8993 * we need to set the entire ilt range for this timers.
8995 if (!CHIP_IS_E1x(bp
) && BP_VN(bp
) == 3) {
8996 struct ilt_client_info ilt_cli
;
8997 /* use dummy TM client */
8998 memset(&ilt_cli
, 0, sizeof(struct ilt_client_info
));
9000 ilt_cli
.end
= ILT_NUM_PAGE_ENTRIES
- 1;
9001 ilt_cli
.client_num
= ILT_CLIENT_TM
;
9003 bnx2x_ilt_boundry_init_op(bp
, &ilt_cli
, 0, INITOP_CLEAR
);
9006 /* this assumes that reset_port() called before reset_func()*/
9007 if (!CHIP_IS_E1x(bp
))
9008 bnx2x_pf_disable(bp
);
9013 static void bnx2x_reset_port(struct bnx2x
*bp
)
9015 int port
= BP_PORT(bp
);
9018 /* Reset physical Link */
9019 bnx2x__link_reset(bp
);
9021 REG_WR(bp
, NIG_REG_MASK_INTERRUPT_PORT0
+ port
*4, 0);
9023 /* Do not rcv packets to BRB */
9024 REG_WR(bp
, NIG_REG_LLH0_BRB1_DRV_MASK
+ port
*4, 0x0);
9025 /* Do not direct rcv packets that are not for MCP to the BRB */
9026 REG_WR(bp
, (port
? NIG_REG_LLH1_BRB1_NOT_MCP
:
9027 NIG_REG_LLH0_BRB1_NOT_MCP
), 0x0);
9030 REG_WR(bp
, MISC_REG_AEU_MASK_ATTN_FUNC_0
+ port
*4, 0);
9033 /* Check for BRB port occupancy */
9034 val
= REG_RD(bp
, BRB1_REG_PORT_NUM_OCC_BLOCKS_0
+ port
*4);
9036 DP(NETIF_MSG_IFDOWN
,
9037 "BRB1 is not empty %d blocks are occupied\n", val
);
9039 /* TODO: Close Doorbell port? */
9042 static int bnx2x_reset_hw(struct bnx2x
*bp
, u32 load_code
)
9044 struct bnx2x_func_state_params func_params
= {NULL
};
9046 /* Prepare parameters for function state transitions */
9047 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
9049 func_params
.f_obj
= &bp
->func_obj
;
9050 func_params
.cmd
= BNX2X_F_CMD_HW_RESET
;
9052 func_params
.params
.hw_init
.load_phase
= load_code
;
9054 return bnx2x_func_state_change(bp
, &func_params
);
9057 static int bnx2x_func_stop(struct bnx2x
*bp
)
9059 struct bnx2x_func_state_params func_params
= {NULL
};
9062 /* Prepare parameters for function state transitions */
9063 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
9064 func_params
.f_obj
= &bp
->func_obj
;
9065 func_params
.cmd
= BNX2X_F_CMD_STOP
;
9068 * Try to stop the function the 'good way'. If fails (in case
9069 * of a parity error during bnx2x_chip_cleanup()) and we are
9070 * not in a debug mode, perform a state transaction in order to
9071 * enable further HW_RESET transaction.
9073 rc
= bnx2x_func_state_change(bp
, &func_params
);
9075 #ifdef BNX2X_STOP_ON_ERROR
9078 BNX2X_ERR("FUNC_STOP ramrod failed. Running a dry transaction\n");
9079 __set_bit(RAMROD_DRV_CLR_ONLY
, &func_params
.ramrod_flags
);
9080 return bnx2x_func_state_change(bp
, &func_params
);
9088 * bnx2x_send_unload_req - request unload mode from the MCP.
9090 * @bp: driver handle
9091 * @unload_mode: requested function's unload mode
9093 * Return unload mode returned by the MCP: COMMON, PORT or FUNC.
9095 u32
bnx2x_send_unload_req(struct bnx2x
*bp
, int unload_mode
)
9098 int port
= BP_PORT(bp
);
9100 /* Select the UNLOAD request mode */
9101 if (unload_mode
== UNLOAD_NORMAL
)
9102 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
9104 else if (bp
->flags
& NO_WOL_FLAG
)
9105 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
;
9108 u32 emac_base
= port
? GRCBASE_EMAC1
: GRCBASE_EMAC0
;
9109 u8
*mac_addr
= bp
->dev
->dev_addr
;
9110 struct pci_dev
*pdev
= bp
->pdev
;
9114 /* The mac address is written to entries 1-4 to
9115 * preserve entry 0 which is used by the PMF
9117 u8 entry
= (BP_VN(bp
) + 1)*8;
9119 val
= (mac_addr
[0] << 8) | mac_addr
[1];
9120 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
, val
);
9122 val
= (mac_addr
[2] << 24) | (mac_addr
[3] << 16) |
9123 (mac_addr
[4] << 8) | mac_addr
[5];
9124 EMAC_WR(bp
, EMAC_REG_EMAC_MAC_MATCH
+ entry
+ 4, val
);
9126 /* Enable the PME and clear the status */
9127 pci_read_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, &pmc
);
9128 pmc
|= PCI_PM_CTRL_PME_ENABLE
| PCI_PM_CTRL_PME_STATUS
;
9129 pci_write_config_word(pdev
, pdev
->pm_cap
+ PCI_PM_CTRL
, pmc
);
9131 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_EN
;
9134 reset_code
= DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
;
9136 /* Send the request to the MCP */
9138 reset_code
= bnx2x_fw_command(bp
, reset_code
, 0);
9140 int path
= BP_PATH(bp
);
9142 DP(NETIF_MSG_IFDOWN
, "NO MCP - load counts[%d] %d, %d, %d\n",
9143 path
, bnx2x_load_count
[path
][0], bnx2x_load_count
[path
][1],
9144 bnx2x_load_count
[path
][2]);
9145 bnx2x_load_count
[path
][0]--;
9146 bnx2x_load_count
[path
][1 + port
]--;
9147 DP(NETIF_MSG_IFDOWN
, "NO MCP - new load counts[%d] %d, %d, %d\n",
9148 path
, bnx2x_load_count
[path
][0], bnx2x_load_count
[path
][1],
9149 bnx2x_load_count
[path
][2]);
9150 if (bnx2x_load_count
[path
][0] == 0)
9151 reset_code
= FW_MSG_CODE_DRV_UNLOAD_COMMON
;
9152 else if (bnx2x_load_count
[path
][1 + port
] == 0)
9153 reset_code
= FW_MSG_CODE_DRV_UNLOAD_PORT
;
9155 reset_code
= FW_MSG_CODE_DRV_UNLOAD_FUNCTION
;
9162 * bnx2x_send_unload_done - send UNLOAD_DONE command to the MCP.
9164 * @bp: driver handle
9165 * @keep_link: true iff link should be kept up
9167 void bnx2x_send_unload_done(struct bnx2x
*bp
, bool keep_link
)
9169 u32 reset_param
= keep_link
? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
: 0;
9171 /* Report UNLOAD_DONE to MCP */
9173 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, reset_param
);
9176 static int bnx2x_func_wait_started(struct bnx2x
*bp
)
9179 int msix
= (bp
->flags
& USING_MSIX_FLAG
) ? 1 : 0;
9185 * (assumption: No Attention from MCP at this stage)
9186 * PMF probably in the middle of TX disable/enable transaction
9187 * 1. Sync IRS for default SB
9188 * 2. Sync SP queue - this guarantees us that attention handling started
9189 * 3. Wait, that TX disable/enable transaction completes
9191 * 1+2 guarantee that if DCBx attention was scheduled it already changed
9192 * pending bit of transaction from STARTED-->TX_STOPPED, if we already
9193 * received completion for the transaction the state is TX_STOPPED.
9194 * State will return to STARTED after completion of TX_STOPPED-->STARTED
9198 /* make sure default SB ISR is done */
9200 synchronize_irq(bp
->msix_table
[0].vector
);
9202 synchronize_irq(bp
->pdev
->irq
);
9204 flush_workqueue(bnx2x_wq
);
9205 flush_workqueue(bnx2x_iov_wq
);
9207 while (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
9208 BNX2X_F_STATE_STARTED
&& tout
--)
9211 if (bnx2x_func_get_state(bp
, &bp
->func_obj
) !=
9212 BNX2X_F_STATE_STARTED
) {
9213 #ifdef BNX2X_STOP_ON_ERROR
9214 BNX2X_ERR("Wrong function state\n");
9218 * Failed to complete the transaction in a "good way"
9219 * Force both transactions with CLR bit
9221 struct bnx2x_func_state_params func_params
= {NULL
};
9223 DP(NETIF_MSG_IFDOWN
,
9224 "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
9226 func_params
.f_obj
= &bp
->func_obj
;
9227 __set_bit(RAMROD_DRV_CLR_ONLY
,
9228 &func_params
.ramrod_flags
);
9230 /* STARTED-->TX_ST0PPED */
9231 func_params
.cmd
= BNX2X_F_CMD_TX_STOP
;
9232 bnx2x_func_state_change(bp
, &func_params
);
9234 /* TX_ST0PPED-->STARTED */
9235 func_params
.cmd
= BNX2X_F_CMD_TX_START
;
9236 return bnx2x_func_state_change(bp
, &func_params
);
9243 static void bnx2x_disable_ptp(struct bnx2x
*bp
)
9245 int port
= BP_PORT(bp
);
9247 /* Disable sending PTP packets to host */
9248 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_TO_HOST
:
9249 NIG_REG_P0_LLH_PTP_TO_HOST
, 0x0);
9251 /* Reset PTP event detection rules */
9252 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
9253 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7FF);
9254 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
9255 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FFF);
9256 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_PARAM_MASK
:
9257 NIG_REG_P0_TLLH_PTP_PARAM_MASK
, 0x7FF);
9258 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_RULE_MASK
:
9259 NIG_REG_P0_TLLH_PTP_RULE_MASK
, 0x3FFF);
9261 /* Disable the PTP feature */
9262 REG_WR(bp
, port
? NIG_REG_P1_PTP_EN
:
9263 NIG_REG_P0_PTP_EN
, 0x0);
9266 /* Called during unload, to stop PTP-related stuff */
9267 static void bnx2x_stop_ptp(struct bnx2x
*bp
)
9269 /* Cancel PTP work queue. Should be done after the Tx queues are
9270 * drained to prevent additional scheduling.
9272 cancel_work_sync(&bp
->ptp_task
);
9274 if (bp
->ptp_tx_skb
) {
9275 dev_kfree_skb_any(bp
->ptp_tx_skb
);
9276 bp
->ptp_tx_skb
= NULL
;
9279 /* Disable PTP in HW */
9280 bnx2x_disable_ptp(bp
);
9282 DP(BNX2X_MSG_PTP
, "PTP stop ended successfully\n");
9285 void bnx2x_chip_cleanup(struct bnx2x
*bp
, int unload_mode
, bool keep_link
)
9287 int port
= BP_PORT(bp
);
9290 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
9293 /* Wait until tx fastpath tasks complete */
9294 for_each_tx_queue(bp
, i
) {
9295 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
9297 for_each_cos_in_tx_queue(fp
, cos
)
9298 rc
= bnx2x_clean_tx_queue(bp
, fp
->txdata_ptr
[cos
]);
9299 #ifdef BNX2X_STOP_ON_ERROR
9305 /* Give HW time to discard old tx messages */
9306 usleep_range(1000, 2000);
9308 /* Clean all ETH MACs */
9309 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_ETH_MAC
,
9312 BNX2X_ERR("Failed to delete all ETH macs: %d\n", rc
);
9314 /* Clean up UC list */
9315 rc
= bnx2x_del_all_macs(bp
, &bp
->sp_objs
[0].mac_obj
, BNX2X_UC_LIST_MAC
,
9318 BNX2X_ERR("Failed to schedule DEL commands for UC MACs list: %d\n",
9322 if (!CHIP_IS_E1(bp
))
9323 REG_WR(bp
, NIG_REG_LLH0_FUNC_EN
+ port
*8, 0);
9325 /* Set "drop all" (stop Rx).
9326 * We need to take a netif_addr_lock() here in order to prevent
9327 * a race between the completion code and this code.
9329 netif_addr_lock_bh(bp
->dev
);
9330 /* Schedule the rx_mode command */
9331 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
9332 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
9334 bnx2x_set_storm_rx_mode(bp
);
9336 /* Cleanup multicast configuration */
9337 rparam
.mcast_obj
= &bp
->mcast_obj
;
9338 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
9340 BNX2X_ERR("Failed to send DEL multicast command: %d\n", rc
);
9342 netif_addr_unlock_bh(bp
->dev
);
9344 bnx2x_iov_chip_cleanup(bp
);
9347 * Send the UNLOAD_REQUEST to the MCP. This will return if
9348 * this function should perform FUNC, PORT or COMMON HW
9351 reset_code
= bnx2x_send_unload_req(bp
, unload_mode
);
9354 * (assumption: No Attention from MCP at this stage)
9355 * PMF probably in the middle of TX disable/enable transaction
9357 rc
= bnx2x_func_wait_started(bp
);
9359 BNX2X_ERR("bnx2x_func_wait_started failed\n");
9360 #ifdef BNX2X_STOP_ON_ERROR
9365 /* Close multi and leading connections
9366 * Completions for ramrods are collected in a synchronous way
9368 for_each_eth_queue(bp
, i
)
9369 if (bnx2x_stop_queue(bp
, i
))
9370 #ifdef BNX2X_STOP_ON_ERROR
9376 if (CNIC_LOADED(bp
)) {
9377 for_each_cnic_queue(bp
, i
)
9378 if (bnx2x_stop_queue(bp
, i
))
9379 #ifdef BNX2X_STOP_ON_ERROR
9386 /* If SP settings didn't get completed so far - something
9387 * very wrong has happen.
9389 if (!bnx2x_wait_sp_comp(bp
, ~0x0UL
))
9390 BNX2X_ERR("Hmmm... Common slow path ramrods got stuck!\n");
9392 #ifndef BNX2X_STOP_ON_ERROR
9395 rc
= bnx2x_func_stop(bp
);
9397 BNX2X_ERR("Function stop failed!\n");
9398 #ifdef BNX2X_STOP_ON_ERROR
9403 /* stop_ptp should be after the Tx queues are drained to prevent
9404 * scheduling to the cancelled PTP work queue. It should also be after
9405 * function stop ramrod is sent, since as part of this ramrod FW access
9408 if (bp
->flags
& PTP_SUPPORTED
)
9411 /* Disable HW interrupts, NAPI */
9412 bnx2x_netif_stop(bp
, 1);
9413 /* Delete all NAPI objects */
9414 bnx2x_del_all_napi(bp
);
9415 if (CNIC_LOADED(bp
))
9416 bnx2x_del_all_napi_cnic(bp
);
9421 /* Reset the chip */
9422 rc
= bnx2x_reset_hw(bp
, reset_code
);
9424 BNX2X_ERR("HW_RESET failed\n");
9426 /* Report UNLOAD_DONE to MCP */
9427 bnx2x_send_unload_done(bp
, keep_link
);
9430 void bnx2x_disable_close_the_gate(struct bnx2x
*bp
)
9434 DP(NETIF_MSG_IFDOWN
, "Disabling \"close the gates\"\n");
9436 if (CHIP_IS_E1(bp
)) {
9437 int port
= BP_PORT(bp
);
9438 u32 addr
= port
? MISC_REG_AEU_MASK_ATTN_FUNC_1
:
9439 MISC_REG_AEU_MASK_ATTN_FUNC_0
;
9441 val
= REG_RD(bp
, addr
);
9443 REG_WR(bp
, addr
, val
);
9445 val
= REG_RD(bp
, MISC_REG_AEU_GENERAL_MASK
);
9446 val
&= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK
|
9447 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK
);
9448 REG_WR(bp
, MISC_REG_AEU_GENERAL_MASK
, val
);
9452 /* Close gates #2, #3 and #4: */
9453 static void bnx2x_set_234_gates(struct bnx2x
*bp
, bool close
)
9457 /* Gates #2 and #4a are closed/opened for "not E1" only */
9458 if (!CHIP_IS_E1(bp
)) {
9460 REG_WR(bp
, PXP_REG_HST_DISCARD_DOORBELLS
, !!close
);
9462 REG_WR(bp
, PXP_REG_HST_DISCARD_INTERNAL_WRITES
, !!close
);
9466 if (CHIP_IS_E1x(bp
)) {
9467 /* Prevent interrupts from HC on both ports */
9468 val
= REG_RD(bp
, HC_REG_CONFIG_1
);
9469 REG_WR(bp
, HC_REG_CONFIG_1
,
9470 (!close
) ? (val
| HC_CONFIG_1_REG_BLOCK_DISABLE_1
) :
9471 (val
& ~(u32
)HC_CONFIG_1_REG_BLOCK_DISABLE_1
));
9473 val
= REG_RD(bp
, HC_REG_CONFIG_0
);
9474 REG_WR(bp
, HC_REG_CONFIG_0
,
9475 (!close
) ? (val
| HC_CONFIG_0_REG_BLOCK_DISABLE_0
) :
9476 (val
& ~(u32
)HC_CONFIG_0_REG_BLOCK_DISABLE_0
));
9478 /* Prevent incoming interrupts in IGU */
9479 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
9481 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
,
9483 (val
| IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
) :
9484 (val
& ~(u32
)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE
));
9487 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "%s gates #2, #3 and #4\n",
9488 close
? "closing" : "opening");
9492 #define SHARED_MF_CLP_MAGIC 0x80000000 /* `magic' bit */
9494 static void bnx2x_clp_reset_prep(struct bnx2x
*bp
, u32
*magic_val
)
9496 /* Do some magic... */
9497 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
9498 *magic_val
= val
& SHARED_MF_CLP_MAGIC
;
9499 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
, val
| SHARED_MF_CLP_MAGIC
);
9503 * bnx2x_clp_reset_done - restore the value of the `magic' bit.
9505 * @bp: driver handle
9506 * @magic_val: old value of the `magic' bit.
9508 static void bnx2x_clp_reset_done(struct bnx2x
*bp
, u32 magic_val
)
9510 /* Restore the `magic' bit value... */
9511 u32 val
= MF_CFG_RD(bp
, shared_mf_config
.clp_mb
);
9512 MF_CFG_WR(bp
, shared_mf_config
.clp_mb
,
9513 (val
& (~SHARED_MF_CLP_MAGIC
)) | magic_val
);
9517 * bnx2x_reset_mcp_prep - prepare for MCP reset.
9519 * @bp: driver handle
9520 * @magic_val: old value of 'magic' bit.
9522 * Takes care of CLP configurations.
9524 static void bnx2x_reset_mcp_prep(struct bnx2x
*bp
, u32
*magic_val
)
9527 u32 validity_offset
;
9529 DP(NETIF_MSG_HW
| NETIF_MSG_IFUP
, "Starting\n");
9531 /* Set `magic' bit in order to save MF config */
9532 if (!CHIP_IS_E1(bp
))
9533 bnx2x_clp_reset_prep(bp
, magic_val
);
9535 /* Get shmem offset */
9536 shmem
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
9538 offsetof(struct shmem_region
, validity_map
[BP_PORT(bp
)]);
9540 /* Clear validity map flags */
9542 REG_WR(bp
, shmem
+ validity_offset
, 0);
9545 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */
9546 #define MCP_ONE_TIMEOUT 100 /* 100 ms */
9549 * bnx2x_mcp_wait_one - wait for MCP_ONE_TIMEOUT
9551 * @bp: driver handle
9553 static void bnx2x_mcp_wait_one(struct bnx2x
*bp
)
9555 /* special handling for emulation and FPGA,
9556 wait 10 times longer */
9557 if (CHIP_REV_IS_SLOW(bp
))
9558 msleep(MCP_ONE_TIMEOUT
*10);
9560 msleep(MCP_ONE_TIMEOUT
);
9564 * initializes bp->common.shmem_base and waits for validity signature to appear
9566 static int bnx2x_init_shmem(struct bnx2x
*bp
)
9572 bp
->common
.shmem_base
= REG_RD(bp
, MISC_REG_SHARED_MEM_ADDR
);
9573 if (bp
->common
.shmem_base
) {
9574 val
= SHMEM_RD(bp
, validity_map
[BP_PORT(bp
)]);
9575 if (val
& SHR_MEM_VALIDITY_MB
)
9579 bnx2x_mcp_wait_one(bp
);
9581 } while (cnt
++ < (MCP_TIMEOUT
/ MCP_ONE_TIMEOUT
));
9583 BNX2X_ERR("BAD MCP validity signature\n");
9588 static int bnx2x_reset_mcp_comp(struct bnx2x
*bp
, u32 magic_val
)
9590 int rc
= bnx2x_init_shmem(bp
);
9592 /* Restore the `magic' bit value */
9593 if (!CHIP_IS_E1(bp
))
9594 bnx2x_clp_reset_done(bp
, magic_val
);
9599 static void bnx2x_pxp_prep(struct bnx2x
*bp
)
9601 if (!CHIP_IS_E1(bp
)) {
9602 REG_WR(bp
, PXP2_REG_RD_START_INIT
, 0);
9603 REG_WR(bp
, PXP2_REG_RQ_RBC_DONE
, 0);
9609 * Reset the whole chip except for:
9611 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by
9614 * - MISC (including AEU)
9618 static void bnx2x_process_kill_chip_reset(struct bnx2x
*bp
, bool global
)
9620 u32 not_reset_mask1
, reset_mask1
, not_reset_mask2
, reset_mask2
;
9621 u32 global_bits2
, stay_reset2
;
9624 * Bits that have to be set in reset_mask2 if we want to reset 'global'
9625 * (per chip) blocks.
9628 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU
|
9629 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE
;
9631 /* Don't reset the following blocks.
9632 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be
9633 * reset, as in 4 port device they might still be owned
9634 * by the MCP (there is only one leader per path).
9637 MISC_REGISTERS_RESET_REG_1_RST_HC
|
9638 MISC_REGISTERS_RESET_REG_1_RST_PXPV
|
9639 MISC_REGISTERS_RESET_REG_1_RST_PXP
;
9642 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO
|
9643 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE
|
9644 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE
|
9645 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE
|
9646 MISC_REGISTERS_RESET_REG_2_RST_RBCN
|
9647 MISC_REGISTERS_RESET_REG_2_RST_GRC
|
9648 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE
|
9649 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B
|
9650 MISC_REGISTERS_RESET_REG_2_RST_ATC
|
9651 MISC_REGISTERS_RESET_REG_2_PGLC
|
9652 MISC_REGISTERS_RESET_REG_2_RST_BMAC0
|
9653 MISC_REGISTERS_RESET_REG_2_RST_BMAC1
|
9654 MISC_REGISTERS_RESET_REG_2_RST_EMAC0
|
9655 MISC_REGISTERS_RESET_REG_2_RST_EMAC1
|
9656 MISC_REGISTERS_RESET_REG_2_UMAC0
|
9657 MISC_REGISTERS_RESET_REG_2_UMAC1
;
9660 * Keep the following blocks in reset:
9661 * - all xxMACs are handled by the bnx2x_link code.
9664 MISC_REGISTERS_RESET_REG_2_XMAC
|
9665 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT
;
9667 /* Full reset masks according to the chip */
9668 reset_mask1
= 0xffffffff;
9671 reset_mask2
= 0xffff;
9672 else if (CHIP_IS_E1H(bp
))
9673 reset_mask2
= 0x1ffff;
9674 else if (CHIP_IS_E2(bp
))
9675 reset_mask2
= 0xfffff;
9676 else /* CHIP_IS_E3 */
9677 reset_mask2
= 0x3ffffff;
9679 /* Don't reset global blocks unless we need to */
9681 reset_mask2
&= ~global_bits2
;
9684 * In case of attention in the QM, we need to reset PXP
9685 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM
9686 * because otherwise QM reset would release 'close the gates' shortly
9687 * before resetting the PXP, then the PSWRQ would send a write
9688 * request to PGLUE. Then when PXP is reset, PGLUE would try to
9689 * read the payload data from PSWWR, but PSWWR would not
9690 * respond. The write queue in PGLUE would stuck, dmae commands
9691 * would not return. Therefore it's important to reset the second
9692 * reset register (containing the
9693 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the
9694 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM
9697 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_CLEAR
,
9698 reset_mask2
& (~not_reset_mask2
));
9700 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_CLEAR
,
9701 reset_mask1
& (~not_reset_mask1
));
9706 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_2_SET
,
9707 reset_mask2
& (~stay_reset2
));
9712 REG_WR(bp
, GRCBASE_MISC
+ MISC_REGISTERS_RESET_REG_1_SET
, reset_mask1
);
9717 * bnx2x_er_poll_igu_vq - poll for pending writes bit.
9718 * It should get cleared in no more than 1s.
9720 * @bp: driver handle
9722 * It should get cleared in no more than 1s. Returns 0 if
9723 * pending writes bit gets cleared.
9725 static int bnx2x_er_poll_igu_vq(struct bnx2x
*bp
)
9731 pend_bits
= REG_RD(bp
, IGU_REG_PENDING_BITS_STATUS
);
9736 usleep_range(1000, 2000);
9737 } while (cnt
-- > 0);
9740 BNX2X_ERR("Still pending IGU requests pend_bits=%x!\n",
9748 static int bnx2x_process_kill(struct bnx2x
*bp
, bool global
)
9752 u32 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
, pgl_exp_rom2
;
9755 /* Empty the Tetris buffer, wait for 1s */
9757 sr_cnt
= REG_RD(bp
, PXP2_REG_RD_SR_CNT
);
9758 blk_cnt
= REG_RD(bp
, PXP2_REG_RD_BLK_CNT
);
9759 port_is_idle_0
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_0
);
9760 port_is_idle_1
= REG_RD(bp
, PXP2_REG_RD_PORT_IS_IDLE_1
);
9761 pgl_exp_rom2
= REG_RD(bp
, PXP2_REG_PGL_EXP_ROM2
);
9763 tags_63_32
= REG_RD(bp
, PGLUE_B_REG_TAGS_63_32
);
9765 if ((sr_cnt
== 0x7e) && (blk_cnt
== 0xa0) &&
9766 ((port_is_idle_0
& 0x1) == 0x1) &&
9767 ((port_is_idle_1
& 0x1) == 0x1) &&
9768 (pgl_exp_rom2
== 0xffffffff) &&
9769 (!CHIP_IS_E3(bp
) || (tags_63_32
== 0xffffffff)))
9771 usleep_range(1000, 2000);
9772 } while (cnt
-- > 0);
9775 BNX2X_ERR("Tetris buffer didn't get empty or there are still outstanding read requests after 1s!\n");
9776 BNX2X_ERR("sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n",
9777 sr_cnt
, blk_cnt
, port_is_idle_0
, port_is_idle_1
,
9784 /* Close gates #2, #3 and #4 */
9785 bnx2x_set_234_gates(bp
, true);
9787 /* Poll for IGU VQs for 57712 and newer chips */
9788 if (!CHIP_IS_E1x(bp
) && bnx2x_er_poll_igu_vq(bp
))
9791 /* TBD: Indicate that "process kill" is in progress to MCP */
9793 /* Clear "unprepared" bit */
9794 REG_WR(bp
, MISC_REG_UNPREPARED
, 0);
9797 /* Make sure all is written to the chip before the reset */
9800 /* Wait for 1ms to empty GLUE and PCI-E core queues,
9801 * PSWHST, GRC and PSWRD Tetris buffer.
9803 usleep_range(1000, 2000);
9805 /* Prepare to chip reset: */
9808 bnx2x_reset_mcp_prep(bp
, &val
);
9814 /* reset the chip */
9815 bnx2x_process_kill_chip_reset(bp
, global
);
9818 /* clear errors in PGB */
9819 if (!CHIP_IS_E1x(bp
))
9820 REG_WR(bp
, PGLUE_B_REG_LATCHED_ERRORS_CLR
, 0x7f);
9822 /* Recover after reset: */
9824 if (global
&& bnx2x_reset_mcp_comp(bp
, val
))
9827 /* TBD: Add resetting the NO_MCP mode DB here */
9829 /* Open the gates #2, #3 and #4 */
9830 bnx2x_set_234_gates(bp
, false);
9832 /* TBD: IGU/AEU preparation bring back the AEU/IGU to a
9833 * reset state, re-enable attentions. */
9838 static int bnx2x_leader_reset(struct bnx2x
*bp
)
9841 bool global
= bnx2x_reset_is_global(bp
);
9844 /* if not going to reset MCP - load "fake" driver to reset HW while
9845 * driver is owner of the HW
9847 if (!global
&& !BP_NOMCP(bp
)) {
9848 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_REQ
,
9849 DRV_MSG_CODE_LOAD_REQ_WITH_LFA
);
9851 BNX2X_ERR("MCP response failure, aborting\n");
9853 goto exit_leader_reset
;
9855 if ((load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
) &&
9856 (load_code
!= FW_MSG_CODE_DRV_LOAD_COMMON
)) {
9857 BNX2X_ERR("MCP unexpected resp, aborting\n");
9859 goto exit_leader_reset2
;
9861 load_code
= bnx2x_fw_command(bp
, DRV_MSG_CODE_LOAD_DONE
, 0);
9863 BNX2X_ERR("MCP response failure, aborting\n");
9865 goto exit_leader_reset2
;
9869 /* Try to recover after the failure */
9870 if (bnx2x_process_kill(bp
, global
)) {
9871 BNX2X_ERR("Something bad had happen on engine %d! Aii!\n",
9874 goto exit_leader_reset2
;
9878 * Clear RESET_IN_PROGRES and RESET_GLOBAL bits and update the driver
9881 bnx2x_set_reset_done(bp
);
9883 bnx2x_clear_reset_global(bp
);
9886 /* unload "fake driver" if it was loaded */
9887 if (!global
&& !BP_NOMCP(bp
)) {
9888 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP
, 0);
9889 bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
, 0);
9893 bnx2x_release_leader_lock(bp
);
9898 static void bnx2x_recovery_failed(struct bnx2x
*bp
)
9900 netdev_err(bp
->dev
, "Recovery has failed. Power cycle is needed.\n");
9902 /* Disconnect this device */
9903 netif_device_detach(bp
->dev
);
9906 * Block ifup for all function on this engine until "process kill"
9909 bnx2x_set_reset_in_progress(bp
);
9911 /* Shut down the power */
9912 bnx2x_set_power_state(bp
, PCI_D3hot
);
9914 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
9920 * Assumption: runs under rtnl lock. This together with the fact
9921 * that it's called only from bnx2x_sp_rtnl() ensure that it
9922 * will never be called when netif_running(bp->dev) is false.
9924 static void bnx2x_parity_recover(struct bnx2x
*bp
)
9926 bool global
= false;
9927 u32 error_recovered
, error_unrecovered
;
9930 DP(NETIF_MSG_HW
, "Handling parity\n");
9932 switch (bp
->recovery_state
) {
9933 case BNX2X_RECOVERY_INIT
:
9934 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_INIT\n");
9935 is_parity
= bnx2x_chk_parity_attn(bp
, &global
, false);
9936 WARN_ON(!is_parity
);
9938 /* Try to get a LEADER_LOCK HW lock */
9939 if (bnx2x_trylock_leader_lock(bp
)) {
9940 bnx2x_set_reset_in_progress(bp
);
9942 * Check if there is a global attention and if
9943 * there was a global attention, set the global
9948 bnx2x_set_reset_global(bp
);
9953 /* Stop the driver */
9954 /* If interface has been removed - break */
9955 if (bnx2x_nic_unload(bp
, UNLOAD_RECOVERY
, false))
9958 bp
->recovery_state
= BNX2X_RECOVERY_WAIT
;
9960 /* Ensure "is_leader", MCP command sequence and
9961 * "recovery_state" update values are seen on other
9967 case BNX2X_RECOVERY_WAIT
:
9968 DP(NETIF_MSG_HW
, "State is BNX2X_RECOVERY_WAIT\n");
9969 if (bp
->is_leader
) {
9970 int other_engine
= BP_PATH(bp
) ? 0 : 1;
9971 bool other_load_status
=
9972 bnx2x_get_load_status(bp
, other_engine
);
9974 bnx2x_get_load_status(bp
, BP_PATH(bp
));
9975 global
= bnx2x_reset_is_global(bp
);
9978 * In case of a parity in a global block, let
9979 * the first leader that performs a
9980 * leader_reset() reset the global blocks in
9981 * order to clear global attentions. Otherwise
9982 * the gates will remain closed for that
9986 (global
&& other_load_status
)) {
9987 /* Wait until all other functions get
9990 schedule_delayed_work(&bp
->sp_rtnl_task
,
9994 /* If all other functions got down -
9995 * try to bring the chip back to
9996 * normal. In any case it's an exit
9997 * point for a leader.
9999 if (bnx2x_leader_reset(bp
)) {
10000 bnx2x_recovery_failed(bp
);
10004 /* If we are here, means that the
10005 * leader has succeeded and doesn't
10006 * want to be a leader any more. Try
10007 * to continue as a none-leader.
10011 } else { /* non-leader */
10012 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
))) {
10013 /* Try to get a LEADER_LOCK HW lock as
10014 * long as a former leader may have
10015 * been unloaded by the user or
10016 * released a leadership by another
10019 if (bnx2x_trylock_leader_lock(bp
)) {
10020 /* I'm a leader now! Restart a
10027 schedule_delayed_work(&bp
->sp_rtnl_task
,
10033 * If there was a global attention, wait
10034 * for it to be cleared.
10036 if (bnx2x_reset_is_global(bp
)) {
10037 schedule_delayed_work(
10044 bp
->eth_stats
.recoverable_error
;
10045 error_unrecovered
=
10046 bp
->eth_stats
.unrecoverable_error
;
10047 bp
->recovery_state
=
10048 BNX2X_RECOVERY_NIC_LOADING
;
10049 if (bnx2x_nic_load(bp
, LOAD_NORMAL
)) {
10050 error_unrecovered
++;
10051 netdev_err(bp
->dev
,
10052 "Recovery failed. Power cycle needed\n");
10053 /* Disconnect this device */
10054 netif_device_detach(bp
->dev
);
10055 /* Shut down the power */
10056 bnx2x_set_power_state(
10060 bp
->recovery_state
=
10061 BNX2X_RECOVERY_DONE
;
10065 bp
->eth_stats
.recoverable_error
=
10067 bp
->eth_stats
.unrecoverable_error
=
10079 #if defined(CONFIG_BNX2X_VXLAN) || IS_ENABLED(CONFIG_BNX2X_GENEVE)
10080 static int bnx2x_udp_port_update(struct bnx2x
*bp
)
10082 struct bnx2x_func_switch_update_params
*switch_update_params
;
10083 struct bnx2x_func_state_params func_params
= {NULL
};
10084 struct bnx2x_udp_tunnel
*udp_tunnel
;
10085 u16 vxlan_port
= 0, geneve_port
= 0;
10088 switch_update_params
= &func_params
.params
.switch_update
;
10090 /* Prepare parameters for function state transitions */
10091 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
10092 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
10094 func_params
.f_obj
= &bp
->func_obj
;
10095 func_params
.cmd
= BNX2X_F_CMD_SWITCH_UPDATE
;
10097 /* Function parameters */
10098 __set_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG
,
10099 &switch_update_params
->changes
);
10101 if (bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_GENEVE
].count
) {
10102 udp_tunnel
= &bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_GENEVE
];
10103 geneve_port
= udp_tunnel
->dst_port
;
10104 switch_update_params
->geneve_dst_port
= geneve_port
;
10107 if (bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_VXLAN
].count
) {
10108 udp_tunnel
= &bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_VXLAN
];
10109 vxlan_port
= udp_tunnel
->dst_port
;
10110 switch_update_params
->vxlan_dst_port
= vxlan_port
;
10113 /* Re-enable inner-rss for the offloaded UDP tunnels */
10114 __set_bit(BNX2X_F_UPDATE_TUNNEL_INNER_RSS
,
10115 &switch_update_params
->changes
);
10117 rc
= bnx2x_func_state_change(bp
, &func_params
);
10119 BNX2X_ERR("failed to set UDP dst port to %04x %04x (rc = 0x%x)\n",
10120 vxlan_port
, geneve_port
, rc
);
10123 "Configured UDP ports: Vxlan [%04x] Geneve [%04x]\n",
10124 vxlan_port
, geneve_port
);
10129 static void __bnx2x_add_udp_port(struct bnx2x
*bp
, u16 port
,
10130 enum bnx2x_udp_port_type type
)
10132 struct bnx2x_udp_tunnel
*udp_port
= &bp
->udp_tunnel_ports
[type
];
10134 if (!netif_running(bp
->dev
) || !IS_PF(bp
))
10137 if (udp_port
->count
&& udp_port
->dst_port
== port
) {
10142 if (udp_port
->count
) {
10144 "UDP tunnel [%d] - destination port limit reached\n",
10149 udp_port
->dst_port
= port
;
10150 udp_port
->count
= 1;
10151 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_CHANGE_UDP_PORT
, 0);
10154 static void __bnx2x_del_udp_port(struct bnx2x
*bp
, u16 port
,
10155 enum bnx2x_udp_port_type type
)
10157 struct bnx2x_udp_tunnel
*udp_port
= &bp
->udp_tunnel_ports
[type
];
10162 if (!udp_port
->count
|| udp_port
->dst_port
!= port
) {
10163 DP(BNX2X_MSG_SP
, "Invalid UDP tunnel [%d] port\n",
10168 /* Remove reference, and make certain it's no longer in use */
10170 if (udp_port
->count
)
10172 udp_port
->dst_port
= 0;
10174 if (netif_running(bp
->dev
))
10175 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_CHANGE_UDP_PORT
, 0);
10177 DP(BNX2X_MSG_SP
, "Deleted UDP tunnel [%d] port %d\n",
10182 #ifdef CONFIG_BNX2X_VXLAN
10183 static void bnx2x_add_vxlan_port(struct net_device
*netdev
,
10184 sa_family_t sa_family
, __be16 port
)
10186 struct bnx2x
*bp
= netdev_priv(netdev
);
10187 u16 t_port
= ntohs(port
);
10189 __bnx2x_add_udp_port(bp
, t_port
, BNX2X_UDP_PORT_VXLAN
);
10192 static void bnx2x_del_vxlan_port(struct net_device
*netdev
,
10193 sa_family_t sa_family
, __be16 port
)
10195 struct bnx2x
*bp
= netdev_priv(netdev
);
10196 u16 t_port
= ntohs(port
);
10198 __bnx2x_del_udp_port(bp
, t_port
, BNX2X_UDP_PORT_VXLAN
);
10202 #if IS_ENABLED(CONFIG_BNX2X_GENEVE)
10203 static void bnx2x_add_geneve_port(struct net_device
*netdev
,
10204 sa_family_t sa_family
, __be16 port
)
10206 struct bnx2x
*bp
= netdev_priv(netdev
);
10207 u16 t_port
= ntohs(port
);
10209 __bnx2x_add_udp_port(bp
, t_port
, BNX2X_UDP_PORT_GENEVE
);
10212 static void bnx2x_del_geneve_port(struct net_device
*netdev
,
10213 sa_family_t sa_family
, __be16 port
)
10215 struct bnx2x
*bp
= netdev_priv(netdev
);
10216 u16 t_port
= ntohs(port
);
10218 __bnx2x_del_udp_port(bp
, t_port
, BNX2X_UDP_PORT_GENEVE
);
10222 static int bnx2x_close(struct net_device
*dev
);
10224 /* bnx2x_nic_unload() flushes the bnx2x_wq, thus reset task is
10225 * scheduled on a general queue in order to prevent a dead lock.
10227 static void bnx2x_sp_rtnl_task(struct work_struct
*work
)
10229 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, sp_rtnl_task
.work
);
10233 if (!netif_running(bp
->dev
)) {
10238 if (unlikely(bp
->recovery_state
!= BNX2X_RECOVERY_DONE
)) {
10239 #ifdef BNX2X_STOP_ON_ERROR
10240 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10241 "you will need to reboot when done\n");
10242 goto sp_rtnl_not_reset
;
10245 * Clear all pending SP commands as we are going to reset the
10248 bp
->sp_rtnl_state
= 0;
10251 bnx2x_parity_recover(bp
);
10257 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_TIMEOUT
, &bp
->sp_rtnl_state
)) {
10258 #ifdef BNX2X_STOP_ON_ERROR
10259 BNX2X_ERR("recovery flow called but STOP_ON_ERROR defined so reset not done to allow debug dump,\n"
10260 "you will need to reboot when done\n");
10261 goto sp_rtnl_not_reset
;
10265 * Clear all pending SP commands as we are going to reset the
10268 bp
->sp_rtnl_state
= 0;
10271 bnx2x_nic_unload(bp
, UNLOAD_NORMAL
, true);
10272 bnx2x_nic_load(bp
, LOAD_NORMAL
);
10277 #ifdef BNX2X_STOP_ON_ERROR
10280 if (test_and_clear_bit(BNX2X_SP_RTNL_SETUP_TC
, &bp
->sp_rtnl_state
))
10281 bnx2x_setup_tc(bp
->dev
, bp
->dcbx_port_params
.ets
.num_of_cos
);
10282 if (test_and_clear_bit(BNX2X_SP_RTNL_AFEX_F_UPDATE
, &bp
->sp_rtnl_state
))
10283 bnx2x_after_function_update(bp
);
10285 * in case of fan failure we need to reset id if the "stop on error"
10286 * debug flag is set, since we trying to prevent permanent overheating
10289 if (test_and_clear_bit(BNX2X_SP_RTNL_FAN_FAILURE
, &bp
->sp_rtnl_state
)) {
10290 DP(NETIF_MSG_HW
, "fan failure detected. Unloading driver\n");
10291 netif_device_detach(bp
->dev
);
10292 bnx2x_close(bp
->dev
);
10297 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_MCAST
, &bp
->sp_rtnl_state
)) {
10299 "sending set mcast vf pf channel message from rtnl sp-task\n");
10300 bnx2x_vfpf_set_mcast(bp
->dev
);
10302 if (test_and_clear_bit(BNX2X_SP_RTNL_VFPF_CHANNEL_DOWN
,
10303 &bp
->sp_rtnl_state
)){
10304 if (!test_bit(__LINK_STATE_NOCARRIER
, &bp
->dev
->state
)) {
10305 bnx2x_tx_disable(bp
);
10306 BNX2X_ERR("PF indicated channel is not servicable anymore. This means this VF device is no longer operational\n");
10310 if (test_and_clear_bit(BNX2X_SP_RTNL_RX_MODE
, &bp
->sp_rtnl_state
)) {
10311 DP(BNX2X_MSG_SP
, "Handling Rx Mode setting\n");
10312 bnx2x_set_rx_mode_inner(bp
);
10315 if (test_and_clear_bit(BNX2X_SP_RTNL_HYPERVISOR_VLAN
,
10316 &bp
->sp_rtnl_state
))
10317 bnx2x_pf_set_vfs_vlan(bp
);
10319 if (test_and_clear_bit(BNX2X_SP_RTNL_TX_STOP
, &bp
->sp_rtnl_state
)) {
10320 bnx2x_dcbx_stop_hw_tx(bp
);
10321 bnx2x_dcbx_resume_hw_tx(bp
);
10324 if (test_and_clear_bit(BNX2X_SP_RTNL_GET_DRV_VERSION
,
10325 &bp
->sp_rtnl_state
))
10326 bnx2x_update_mng_version(bp
);
10328 #if defined(CONFIG_BNX2X_VXLAN) || IS_ENABLED(CONFIG_BNX2X_GENEVE)
10329 if (test_and_clear_bit(BNX2X_SP_RTNL_CHANGE_UDP_PORT
,
10330 &bp
->sp_rtnl_state
)) {
10331 if (bnx2x_udp_port_update(bp
)) {
10332 /* On error, forget configuration */
10333 memset(bp
->udp_tunnel_ports
, 0,
10334 sizeof(struct bnx2x_udp_tunnel
) *
10335 BNX2X_UDP_PORT_MAX
);
10337 /* Since we don't store additional port information,
10338 * if no port is configured for any feature ask for
10339 * information about currently configured ports.
10341 #ifdef CONFIG_BNX2X_VXLAN
10342 if (!bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_VXLAN
].count
)
10343 vxlan_get_rx_port(bp
->dev
);
10345 #if IS_ENABLED(CONFIG_BNX2X_GENEVE)
10346 if (!bp
->udp_tunnel_ports
[BNX2X_UDP_PORT_GENEVE
].count
)
10347 geneve_get_rx_port(bp
->dev
);
10353 /* work which needs rtnl lock not-taken (as it takes the lock itself and
10354 * can be called from other contexts as well)
10358 /* enable SR-IOV if applicable */
10359 if (IS_SRIOV(bp
) && test_and_clear_bit(BNX2X_SP_RTNL_ENABLE_SRIOV
,
10360 &bp
->sp_rtnl_state
)) {
10361 bnx2x_disable_sriov(bp
);
10362 bnx2x_enable_sriov(bp
);
10366 static void bnx2x_period_task(struct work_struct
*work
)
10368 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, period_task
.work
);
10370 if (!netif_running(bp
->dev
))
10371 goto period_task_exit
;
10373 if (CHIP_REV_IS_SLOW(bp
)) {
10374 BNX2X_ERR("period task called on emulation, ignoring\n");
10375 goto period_task_exit
;
10378 bnx2x_acquire_phy_lock(bp
);
10380 * The barrier is needed to ensure the ordering between the writing to
10381 * the bp->port.pmf in the bnx2x_nic_load() or bnx2x_pmf_update() and
10382 * the reading here.
10385 if (bp
->port
.pmf
) {
10386 bnx2x_period_func(&bp
->link_params
, &bp
->link_vars
);
10388 /* Re-queue task in 1 sec */
10389 queue_delayed_work(bnx2x_wq
, &bp
->period_task
, 1*HZ
);
10392 bnx2x_release_phy_lock(bp
);
10398 * Init service functions
10401 static u32
bnx2x_get_pretend_reg(struct bnx2x
*bp
)
10403 u32 base
= PXP2_REG_PGL_PRETEND_FUNC_F0
;
10404 u32 stride
= PXP2_REG_PGL_PRETEND_FUNC_F1
- base
;
10405 return base
+ (BP_ABS_FUNC(bp
)) * stride
;
10408 static bool bnx2x_prev_unload_close_umac(struct bnx2x
*bp
,
10409 u8 port
, u32 reset_reg
,
10410 struct bnx2x_mac_vals
*vals
)
10412 u32 mask
= MISC_REGISTERS_RESET_REG_2_UMAC0
<< port
;
10415 if (!(mask
& reset_reg
))
10418 BNX2X_DEV_INFO("Disable umac Rx %02x\n", port
);
10419 base_addr
= port
? GRCBASE_UMAC1
: GRCBASE_UMAC0
;
10420 vals
->umac_addr
[port
] = base_addr
+ UMAC_REG_COMMAND_CONFIG
;
10421 vals
->umac_val
[port
] = REG_RD(bp
, vals
->umac_addr
[port
]);
10422 REG_WR(bp
, vals
->umac_addr
[port
], 0);
10427 static void bnx2x_prev_unload_close_mac(struct bnx2x
*bp
,
10428 struct bnx2x_mac_vals
*vals
)
10430 u32 val
, base_addr
, offset
, mask
, reset_reg
;
10431 bool mac_stopped
= false;
10432 u8 port
= BP_PORT(bp
);
10434 /* reset addresses as they also mark which values were changed */
10435 memset(vals
, 0, sizeof(*vals
));
10437 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_2
);
10439 if (!CHIP_IS_E3(bp
)) {
10440 val
= REG_RD(bp
, NIG_REG_BMAC0_REGS_OUT_EN
+ port
* 4);
10441 mask
= MISC_REGISTERS_RESET_REG_2_RST_BMAC0
<< port
;
10442 if ((mask
& reset_reg
) && val
) {
10444 BNX2X_DEV_INFO("Disable bmac Rx\n");
10445 base_addr
= BP_PORT(bp
) ? NIG_REG_INGRESS_BMAC1_MEM
10446 : NIG_REG_INGRESS_BMAC0_MEM
;
10447 offset
= CHIP_IS_E2(bp
) ? BIGMAC2_REGISTER_BMAC_CONTROL
10448 : BIGMAC_REGISTER_BMAC_CONTROL
;
10451 * use rd/wr since we cannot use dmae. This is safe
10452 * since MCP won't access the bus due to the request
10453 * to unload, and no function on the path can be
10454 * loaded at this time.
10456 wb_data
[0] = REG_RD(bp
, base_addr
+ offset
);
10457 wb_data
[1] = REG_RD(bp
, base_addr
+ offset
+ 0x4);
10458 vals
->bmac_addr
= base_addr
+ offset
;
10459 vals
->bmac_val
[0] = wb_data
[0];
10460 vals
->bmac_val
[1] = wb_data
[1];
10461 wb_data
[0] &= ~BMAC_CONTROL_RX_ENABLE
;
10462 REG_WR(bp
, vals
->bmac_addr
, wb_data
[0]);
10463 REG_WR(bp
, vals
->bmac_addr
+ 0x4, wb_data
[1]);
10465 BNX2X_DEV_INFO("Disable emac Rx\n");
10466 vals
->emac_addr
= NIG_REG_NIG_EMAC0_EN
+ BP_PORT(bp
)*4;
10467 vals
->emac_val
= REG_RD(bp
, vals
->emac_addr
);
10468 REG_WR(bp
, vals
->emac_addr
, 0);
10469 mac_stopped
= true;
10471 if (reset_reg
& MISC_REGISTERS_RESET_REG_2_XMAC
) {
10472 BNX2X_DEV_INFO("Disable xmac Rx\n");
10473 base_addr
= BP_PORT(bp
) ? GRCBASE_XMAC1
: GRCBASE_XMAC0
;
10474 val
= REG_RD(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
);
10475 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
10477 REG_WR(bp
, base_addr
+ XMAC_REG_PFC_CTRL_HI
,
10479 vals
->xmac_addr
= base_addr
+ XMAC_REG_CTRL
;
10480 vals
->xmac_val
= REG_RD(bp
, vals
->xmac_addr
);
10481 REG_WR(bp
, vals
->xmac_addr
, 0);
10482 mac_stopped
= true;
10485 mac_stopped
|= bnx2x_prev_unload_close_umac(bp
, 0,
10487 mac_stopped
|= bnx2x_prev_unload_close_umac(bp
, 1,
10495 #define BNX2X_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4))
10496 #define BNX2X_PREV_UNDI_PROD_ADDR_H(f) (BAR_TSTRORM_INTMEM + \
10497 0x1848 + ((f) << 4))
10498 #define BNX2X_PREV_UNDI_RCQ(val) ((val) & 0xffff)
10499 #define BNX2X_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff)
10500 #define BNX2X_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq))
10502 #define BCM_5710_UNDI_FW_MF_MAJOR (0x07)
10503 #define BCM_5710_UNDI_FW_MF_MINOR (0x08)
10504 #define BCM_5710_UNDI_FW_MF_VERS (0x05)
10506 static bool bnx2x_prev_is_after_undi(struct bnx2x
*bp
)
10508 /* UNDI marks its presence in DORQ -
10509 * it initializes CID offset for normal bell to 0x7
10511 if (!(REG_RD(bp
, MISC_REG_RESET_REG_1
) &
10512 MISC_REGISTERS_RESET_REG_1_RST_DORQ
))
10515 if (REG_RD(bp
, DORQ_REG_NORM_CID_OFST
) == 0x7) {
10516 BNX2X_DEV_INFO("UNDI previously loaded\n");
10523 static void bnx2x_prev_unload_undi_inc(struct bnx2x
*bp
, u8 inc
)
10528 if (BP_FUNC(bp
) < 2)
10529 addr
= BNX2X_PREV_UNDI_PROD_ADDR(BP_PORT(bp
));
10531 addr
= BNX2X_PREV_UNDI_PROD_ADDR_H(BP_FUNC(bp
) - 2);
10533 tmp_reg
= REG_RD(bp
, addr
);
10534 rcq
= BNX2X_PREV_UNDI_RCQ(tmp_reg
) + inc
;
10535 bd
= BNX2X_PREV_UNDI_BD(tmp_reg
) + inc
;
10537 tmp_reg
= BNX2X_PREV_UNDI_PROD(rcq
, bd
);
10538 REG_WR(bp
, addr
, tmp_reg
);
10540 BNX2X_DEV_INFO("UNDI producer [%d/%d][%08x] rings bd -> 0x%04x, rcq -> 0x%04x\n",
10541 BP_PORT(bp
), BP_FUNC(bp
), addr
, bd
, rcq
);
10544 static int bnx2x_prev_mcp_done(struct bnx2x
*bp
)
10546 u32 rc
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_DONE
,
10547 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET
);
10549 BNX2X_ERR("MCP response failure, aborting\n");
10556 static struct bnx2x_prev_path_list
*
10557 bnx2x_prev_path_get_entry(struct bnx2x
*bp
)
10559 struct bnx2x_prev_path_list
*tmp_list
;
10561 list_for_each_entry(tmp_list
, &bnx2x_prev_list
, list
)
10562 if (PCI_SLOT(bp
->pdev
->devfn
) == tmp_list
->slot
&&
10563 bp
->pdev
->bus
->number
== tmp_list
->bus
&&
10564 BP_PATH(bp
) == tmp_list
->path
)
10570 static int bnx2x_prev_path_mark_eeh(struct bnx2x
*bp
)
10572 struct bnx2x_prev_path_list
*tmp_list
;
10575 rc
= down_interruptible(&bnx2x_prev_sem
);
10577 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
10581 tmp_list
= bnx2x_prev_path_get_entry(bp
);
10586 BNX2X_ERR("path %d: Entry does not exist for eeh; Flow occurs before initial insmod is over ?\n",
10590 up(&bnx2x_prev_sem
);
10595 static bool bnx2x_prev_is_path_marked(struct bnx2x
*bp
)
10597 struct bnx2x_prev_path_list
*tmp_list
;
10600 if (down_trylock(&bnx2x_prev_sem
))
10603 tmp_list
= bnx2x_prev_path_get_entry(bp
);
10605 if (tmp_list
->aer
) {
10606 DP(NETIF_MSG_HW
, "Path %d was marked by AER\n",
10610 BNX2X_DEV_INFO("Path %d was already cleaned from previous drivers\n",
10615 up(&bnx2x_prev_sem
);
10620 bool bnx2x_port_after_undi(struct bnx2x
*bp
)
10622 struct bnx2x_prev_path_list
*entry
;
10625 down(&bnx2x_prev_sem
);
10627 entry
= bnx2x_prev_path_get_entry(bp
);
10628 val
= !!(entry
&& (entry
->undi
& (1 << BP_PORT(bp
))));
10630 up(&bnx2x_prev_sem
);
10635 static int bnx2x_prev_mark_path(struct bnx2x
*bp
, bool after_undi
)
10637 struct bnx2x_prev_path_list
*tmp_list
;
10640 rc
= down_interruptible(&bnx2x_prev_sem
);
10642 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
10646 /* Check whether the entry for this path already exists */
10647 tmp_list
= bnx2x_prev_path_get_entry(bp
);
10649 if (!tmp_list
->aer
) {
10650 BNX2X_ERR("Re-Marking the path.\n");
10652 DP(NETIF_MSG_HW
, "Removing AER indication from path %d\n",
10656 up(&bnx2x_prev_sem
);
10659 up(&bnx2x_prev_sem
);
10661 /* Create an entry for this path and add it */
10662 tmp_list
= kmalloc(sizeof(struct bnx2x_prev_path_list
), GFP_KERNEL
);
10664 BNX2X_ERR("Failed to allocate 'bnx2x_prev_path_list'\n");
10668 tmp_list
->bus
= bp
->pdev
->bus
->number
;
10669 tmp_list
->slot
= PCI_SLOT(bp
->pdev
->devfn
);
10670 tmp_list
->path
= BP_PATH(bp
);
10672 tmp_list
->undi
= after_undi
? (1 << BP_PORT(bp
)) : 0;
10674 rc
= down_interruptible(&bnx2x_prev_sem
);
10676 BNX2X_ERR("Received %d when tried to take lock\n", rc
);
10679 DP(NETIF_MSG_HW
, "Marked path [%d] - finished previous unload\n",
10681 list_add(&tmp_list
->list
, &bnx2x_prev_list
);
10682 up(&bnx2x_prev_sem
);
10688 static int bnx2x_do_flr(struct bnx2x
*bp
)
10690 struct pci_dev
*dev
= bp
->pdev
;
10692 if (CHIP_IS_E1x(bp
)) {
10693 BNX2X_DEV_INFO("FLR not supported in E1/E1H\n");
10697 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */
10698 if (bp
->common
.bc_ver
< REQ_BC_VER_4_INITIATE_FLR
) {
10699 BNX2X_ERR("FLR not supported by BC_VER: 0x%x\n",
10700 bp
->common
.bc_ver
);
10704 if (!pci_wait_for_pending_transaction(dev
))
10705 dev_err(&dev
->dev
, "transaction is not cleared; proceeding with reset anyway\n");
10707 BNX2X_DEV_INFO("Initiating FLR\n");
10708 bnx2x_fw_command(bp
, DRV_MSG_CODE_INITIATE_FLR
, 0);
10713 static int bnx2x_prev_unload_uncommon(struct bnx2x
*bp
)
10717 BNX2X_DEV_INFO("Uncommon unload Flow\n");
10719 /* Test if previous unload process was already finished for this path */
10720 if (bnx2x_prev_is_path_marked(bp
))
10721 return bnx2x_prev_mcp_done(bp
);
10723 BNX2X_DEV_INFO("Path is unmarked\n");
10725 /* Cannot proceed with FLR if UNDI is loaded, since FW does not match */
10726 if (bnx2x_prev_is_after_undi(bp
))
10729 /* If function has FLR capabilities, and existing FW version matches
10730 * the one required, then FLR will be sufficient to clean any residue
10731 * left by previous driver
10733 rc
= bnx2x_compare_fw_ver(bp
, FW_MSG_CODE_DRV_LOAD_FUNCTION
, false);
10736 /* fw version is good */
10737 BNX2X_DEV_INFO("FW version matches our own. Attempting FLR\n");
10738 rc
= bnx2x_do_flr(bp
);
10742 /* FLR was performed */
10743 BNX2X_DEV_INFO("FLR successful\n");
10747 BNX2X_DEV_INFO("Could not FLR\n");
10750 /* Close the MCP request, return failure*/
10751 rc
= bnx2x_prev_mcp_done(bp
);
10753 rc
= BNX2X_PREV_WAIT_NEEDED
;
10758 static int bnx2x_prev_unload_common(struct bnx2x
*bp
)
10760 u32 reset_reg
, tmp_reg
= 0, rc
;
10761 bool prev_undi
= false;
10762 struct bnx2x_mac_vals mac_vals
;
10764 /* It is possible a previous function received 'common' answer,
10765 * but hasn't loaded yet, therefore creating a scenario of
10766 * multiple functions receiving 'common' on the same path.
10768 BNX2X_DEV_INFO("Common unload Flow\n");
10770 memset(&mac_vals
, 0, sizeof(mac_vals
));
10772 if (bnx2x_prev_is_path_marked(bp
))
10773 return bnx2x_prev_mcp_done(bp
);
10775 reset_reg
= REG_RD(bp
, MISC_REG_RESET_REG_1
);
10777 /* Reset should be performed after BRB is emptied */
10778 if (reset_reg
& MISC_REGISTERS_RESET_REG_1_RST_BRB1
) {
10779 u32 timer_count
= 1000;
10781 /* Close the MAC Rx to prevent BRB from filling up */
10782 bnx2x_prev_unload_close_mac(bp
, &mac_vals
);
10784 /* close LLH filters for both ports towards the BRB */
10785 bnx2x_set_rx_filter(&bp
->link_params
, 0);
10786 bp
->link_params
.port
^= 1;
10787 bnx2x_set_rx_filter(&bp
->link_params
, 0);
10788 bp
->link_params
.port
^= 1;
10790 /* Check if the UNDI driver was previously loaded */
10791 if (bnx2x_prev_is_after_undi(bp
)) {
10793 /* clear the UNDI indication */
10794 REG_WR(bp
, DORQ_REG_NORM_CID_OFST
, 0);
10795 /* clear possible idle check errors */
10796 REG_RD(bp
, NIG_REG_NIG_INT_STS_CLR_0
);
10798 if (!CHIP_IS_E1x(bp
))
10799 /* block FW from writing to host */
10800 REG_WR(bp
, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER
, 0);
10802 /* wait until BRB is empty */
10803 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
10804 while (timer_count
) {
10805 u32 prev_brb
= tmp_reg
;
10807 tmp_reg
= REG_RD(bp
, BRB1_REG_NUM_OF_FULL_BLOCKS
);
10811 BNX2X_DEV_INFO("BRB still has 0x%08x\n", tmp_reg
);
10813 /* reset timer as long as BRB actually gets emptied */
10814 if (prev_brb
> tmp_reg
)
10815 timer_count
= 1000;
10819 /* If UNDI resides in memory, manually increment it */
10821 bnx2x_prev_unload_undi_inc(bp
, 1);
10827 BNX2X_ERR("Failed to empty BRB, hope for the best\n");
10830 /* No packets are in the pipeline, path is ready for reset */
10831 bnx2x_reset_common(bp
);
10833 if (mac_vals
.xmac_addr
)
10834 REG_WR(bp
, mac_vals
.xmac_addr
, mac_vals
.xmac_val
);
10835 if (mac_vals
.umac_addr
[0])
10836 REG_WR(bp
, mac_vals
.umac_addr
[0], mac_vals
.umac_val
[0]);
10837 if (mac_vals
.umac_addr
[1])
10838 REG_WR(bp
, mac_vals
.umac_addr
[1], mac_vals
.umac_val
[1]);
10839 if (mac_vals
.emac_addr
)
10840 REG_WR(bp
, mac_vals
.emac_addr
, mac_vals
.emac_val
);
10841 if (mac_vals
.bmac_addr
) {
10842 REG_WR(bp
, mac_vals
.bmac_addr
, mac_vals
.bmac_val
[0]);
10843 REG_WR(bp
, mac_vals
.bmac_addr
+ 4, mac_vals
.bmac_val
[1]);
10846 rc
= bnx2x_prev_mark_path(bp
, prev_undi
);
10848 bnx2x_prev_mcp_done(bp
);
10852 return bnx2x_prev_mcp_done(bp
);
10855 static int bnx2x_prev_unload(struct bnx2x
*bp
)
10857 int time_counter
= 10;
10858 u32 rc
, fw
, hw_lock_reg
, hw_lock_val
;
10859 BNX2X_DEV_INFO("Entering Previous Unload Flow\n");
10861 /* clear hw from errors which may have resulted from an interrupted
10862 * dmae transaction.
10864 bnx2x_clean_pglue_errors(bp
);
10866 /* Release previously held locks */
10867 hw_lock_reg
= (BP_FUNC(bp
) <= 5) ?
10868 (MISC_REG_DRIVER_CONTROL_1
+ BP_FUNC(bp
) * 8) :
10869 (MISC_REG_DRIVER_CONTROL_7
+ (BP_FUNC(bp
) - 6) * 8);
10871 hw_lock_val
= REG_RD(bp
, hw_lock_reg
);
10873 if (hw_lock_val
& HW_LOCK_RESOURCE_NVRAM
) {
10874 BNX2X_DEV_INFO("Release Previously held NVRAM lock\n");
10875 REG_WR(bp
, MCP_REG_MCPR_NVM_SW_ARB
,
10876 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1
<< BP_PORT(bp
)));
10879 BNX2X_DEV_INFO("Release Previously held hw lock\n");
10880 REG_WR(bp
, hw_lock_reg
, 0xffffffff);
10882 BNX2X_DEV_INFO("No need to release hw/nvram locks\n");
10884 if (MCPR_ACCESS_LOCK_LOCK
& REG_RD(bp
, MCP_REG_MCPR_ACCESS_LOCK
)) {
10885 BNX2X_DEV_INFO("Release previously held alr\n");
10886 bnx2x_release_alr(bp
);
10891 /* Lock MCP using an unload request */
10892 fw
= bnx2x_fw_command(bp
, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS
, 0);
10894 BNX2X_ERR("MCP response failure, aborting\n");
10899 rc
= down_interruptible(&bnx2x_prev_sem
);
10901 BNX2X_ERR("Cannot check for AER; Received %d when tried to take lock\n",
10904 /* If Path is marked by EEH, ignore unload status */
10905 aer
= !!(bnx2x_prev_path_get_entry(bp
) &&
10906 bnx2x_prev_path_get_entry(bp
)->aer
);
10907 up(&bnx2x_prev_sem
);
10910 if (fw
== FW_MSG_CODE_DRV_UNLOAD_COMMON
|| aer
) {
10911 rc
= bnx2x_prev_unload_common(bp
);
10915 /* non-common reply from MCP might require looping */
10916 rc
= bnx2x_prev_unload_uncommon(bp
);
10917 if (rc
!= BNX2X_PREV_WAIT_NEEDED
)
10921 } while (--time_counter
);
10923 if (!time_counter
|| rc
) {
10924 BNX2X_DEV_INFO("Unloading previous driver did not occur, Possibly due to MF UNDI\n");
10925 rc
= -EPROBE_DEFER
;
10928 /* Mark function if its port was used to boot from SAN */
10929 if (bnx2x_port_after_undi(bp
))
10930 bp
->link_params
.feature_config_flags
|=
10931 FEATURE_CONFIG_BOOT_FROM_SAN
;
10933 BNX2X_DEV_INFO("Finished Previous Unload Flow [%d]\n", rc
);
10938 static void bnx2x_get_common_hwinfo(struct bnx2x
*bp
)
10940 u32 val
, val2
, val3
, val4
, id
, boot_mode
;
10943 /* Get the chip revision id and number. */
10944 /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
10945 val
= REG_RD(bp
, MISC_REG_CHIP_NUM
);
10946 id
= ((val
& 0xffff) << 16);
10947 val
= REG_RD(bp
, MISC_REG_CHIP_REV
);
10948 id
|= ((val
& 0xf) << 12);
10950 /* Metal is read from PCI regs, but we can't access >=0x400 from
10951 * the configuration space (so we need to reg_rd)
10953 val
= REG_RD(bp
, PCICFG_OFFSET
+ PCI_ID_VAL3
);
10954 id
|= (((val
>> 24) & 0xf) << 4);
10955 val
= REG_RD(bp
, MISC_REG_BOND_ID
);
10957 bp
->common
.chip_id
= id
;
10959 /* force 57811 according to MISC register */
10960 if (REG_RD(bp
, MISC_REG_CHIP_TYPE
) & MISC_REG_CHIP_TYPE_57811_MASK
) {
10961 if (CHIP_IS_57810(bp
))
10962 bp
->common
.chip_id
= (CHIP_NUM_57811
<< 16) |
10963 (bp
->common
.chip_id
& 0x0000FFFF);
10964 else if (CHIP_IS_57810_MF(bp
))
10965 bp
->common
.chip_id
= (CHIP_NUM_57811_MF
<< 16) |
10966 (bp
->common
.chip_id
& 0x0000FFFF);
10967 bp
->common
.chip_id
|= 0x1;
10970 /* Set doorbell size */
10971 bp
->db_size
= (1 << BNX2X_DB_SHIFT
);
10973 if (!CHIP_IS_E1x(bp
)) {
10974 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN_OVWR
);
10975 if ((val
& 1) == 0)
10976 val
= REG_RD(bp
, MISC_REG_PORT4MODE_EN
);
10978 val
= (val
>> 1) & 1;
10979 BNX2X_DEV_INFO("chip is in %s\n", val
? "4_PORT_MODE" :
10981 bp
->common
.chip_port_mode
= val
? CHIP_4_PORT_MODE
:
10984 if (CHIP_MODE_IS_4_PORT(bp
))
10985 bp
->pfid
= (bp
->pf_num
>> 1); /* 0..3 */
10987 bp
->pfid
= (bp
->pf_num
& 0x6); /* 0, 2, 4, 6 */
10989 bp
->common
.chip_port_mode
= CHIP_PORT_MODE_NONE
; /* N/A */
10990 bp
->pfid
= bp
->pf_num
; /* 0..7 */
10993 BNX2X_DEV_INFO("pf_id: %x", bp
->pfid
);
10995 bp
->link_params
.chip_id
= bp
->common
.chip_id
;
10996 BNX2X_DEV_INFO("chip ID is 0x%x\n", id
);
10998 val
= (REG_RD(bp
, 0x2874) & 0x55);
10999 if ((bp
->common
.chip_id
& 0x1) ||
11000 (CHIP_IS_E1(bp
) && val
) || (CHIP_IS_E1H(bp
) && (val
== 0x55))) {
11001 bp
->flags
|= ONE_PORT_FLAG
;
11002 BNX2X_DEV_INFO("single port device\n");
11005 val
= REG_RD(bp
, MCP_REG_MCPR_NVM_CFG4
);
11006 bp
->common
.flash_size
= (BNX2X_NVRAM_1MB_SIZE
<<
11007 (val
& MCPR_NVM_CFG4_FLASH_SIZE
));
11008 BNX2X_DEV_INFO("flash_size 0x%x (%d)\n",
11009 bp
->common
.flash_size
, bp
->common
.flash_size
);
11011 bnx2x_init_shmem(bp
);
11013 bp
->common
.shmem2_base
= REG_RD(bp
, (BP_PATH(bp
) ?
11014 MISC_REG_GENERIC_CR_1
:
11015 MISC_REG_GENERIC_CR_0
));
11017 bp
->link_params
.shmem_base
= bp
->common
.shmem_base
;
11018 bp
->link_params
.shmem2_base
= bp
->common
.shmem2_base
;
11019 if (SHMEM2_RD(bp
, size
) >
11020 (u32
)offsetof(struct shmem2_region
, lfa_host_addr
[BP_PORT(bp
)]))
11021 bp
->link_params
.lfa_base
=
11022 REG_RD(bp
, bp
->common
.shmem2_base
+
11023 (u32
)offsetof(struct shmem2_region
,
11024 lfa_host_addr
[BP_PORT(bp
)]));
11026 bp
->link_params
.lfa_base
= 0;
11027 BNX2X_DEV_INFO("shmem offset 0x%x shmem2 offset 0x%x\n",
11028 bp
->common
.shmem_base
, bp
->common
.shmem2_base
);
11030 if (!bp
->common
.shmem_base
) {
11031 BNX2X_DEV_INFO("MCP not active\n");
11032 bp
->flags
|= NO_MCP_FLAG
;
11036 bp
->common
.hw_config
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.config
);
11037 BNX2X_DEV_INFO("hw_config 0x%08x\n", bp
->common
.hw_config
);
11039 bp
->link_params
.hw_led_mode
= ((bp
->common
.hw_config
&
11040 SHARED_HW_CFG_LED_MODE_MASK
) >>
11041 SHARED_HW_CFG_LED_MODE_SHIFT
);
11043 bp
->link_params
.feature_config_flags
= 0;
11044 val
= SHMEM_RD(bp
, dev_info
.shared_feature_config
.config
);
11045 if (val
& SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED
)
11046 bp
->link_params
.feature_config_flags
|=
11047 FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
11049 bp
->link_params
.feature_config_flags
&=
11050 ~FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED
;
11052 val
= SHMEM_RD(bp
, dev_info
.bc_rev
) >> 8;
11053 bp
->common
.bc_ver
= val
;
11054 BNX2X_DEV_INFO("bc_ver %X\n", val
);
11055 if (val
< BNX2X_BC_VER
) {
11056 /* for now only warn
11057 * later we might need to enforce this */
11058 BNX2X_ERR("This driver needs bc_ver %X but found %X, please upgrade BC\n",
11059 BNX2X_BC_VER
, val
);
11061 bp
->link_params
.feature_config_flags
|=
11062 (val
>= REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL
) ?
11063 FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY
: 0;
11065 bp
->link_params
.feature_config_flags
|=
11066 (val
>= REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL
) ?
11067 FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY
: 0;
11068 bp
->link_params
.feature_config_flags
|=
11069 (val
>= REQ_BC_VER_4_VRFY_AFEX_SUPPORTED
) ?
11070 FEATURE_CONFIG_BC_SUPPORTS_AFEX
: 0;
11071 bp
->link_params
.feature_config_flags
|=
11072 (val
>= REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED
) ?
11073 FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED
: 0;
11075 bp
->link_params
.feature_config_flags
|=
11076 (val
>= REQ_BC_VER_4_MT_SUPPORTED
) ?
11077 FEATURE_CONFIG_MT_SUPPORT
: 0;
11079 bp
->flags
|= (val
>= REQ_BC_VER_4_PFC_STATS_SUPPORTED
) ?
11080 BC_SUPPORTS_PFC_STATS
: 0;
11082 bp
->flags
|= (val
>= REQ_BC_VER_4_FCOE_FEATURES
) ?
11083 BC_SUPPORTS_FCOE_FEATURES
: 0;
11085 bp
->flags
|= (val
>= REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF
) ?
11086 BC_SUPPORTS_DCBX_MSG_NON_PMF
: 0;
11088 bp
->flags
|= (val
>= REQ_BC_VER_4_RMMOD_CMD
) ?
11089 BC_SUPPORTS_RMMOD_CMD
: 0;
11091 boot_mode
= SHMEM_RD(bp
,
11092 dev_info
.port_feature_config
[BP_PORT(bp
)].mba_config
) &
11093 PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK
;
11094 switch (boot_mode
) {
11095 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE
:
11096 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_PXE
;
11098 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB
:
11099 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_ISCSI
;
11101 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT
:
11102 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_FCOE
;
11104 case PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE
:
11105 bp
->common
.boot_mode
= FEATURE_ETH_BOOTMODE_NONE
;
11109 pci_read_config_word(bp
->pdev
, bp
->pdev
->pm_cap
+ PCI_PM_PMC
, &pmc
);
11110 bp
->flags
|= (pmc
& PCI_PM_CAP_PME_D3cold
) ? 0 : NO_WOL_FLAG
;
11112 BNX2X_DEV_INFO("%sWoL capable\n",
11113 (bp
->flags
& NO_WOL_FLAG
) ? "not " : "");
11115 val
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
);
11116 val2
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[4]);
11117 val3
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[8]);
11118 val4
= SHMEM_RD(bp
, dev_info
.shared_hw_config
.part_num
[12]);
11120 dev_info(&bp
->pdev
->dev
, "part number %X-%X-%X-%X\n",
11121 val
, val2
, val3
, val4
);
11124 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID)
11125 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR)
11127 static int bnx2x_get_igu_cam_info(struct bnx2x
*bp
)
11129 int pfid
= BP_FUNC(bp
);
11132 u8 fid
, igu_sb_cnt
= 0;
11134 bp
->igu_base_sb
= 0xff;
11135 if (CHIP_INT_MODE_IS_BC(bp
)) {
11136 int vn
= BP_VN(bp
);
11137 igu_sb_cnt
= bp
->igu_sb_cnt
;
11138 bp
->igu_base_sb
= (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
) *
11141 bp
->igu_dsb_id
= E1HVN_MAX
* FP_SB_MAX_E1x
+
11142 (CHIP_MODE_IS_4_PORT(bp
) ? pfid
: vn
);
11147 /* IGU in normal mode - read CAM */
11148 for (igu_sb_id
= 0; igu_sb_id
< IGU_REG_MAPPING_MEMORY_SIZE
;
11150 val
= REG_RD(bp
, IGU_REG_MAPPING_MEMORY
+ igu_sb_id
* 4);
11151 if (!(val
& IGU_REG_MAPPING_MEMORY_VALID
))
11153 fid
= IGU_FID(val
);
11154 if ((fid
& IGU_FID_ENCODE_IS_PF
)) {
11155 if ((fid
& IGU_FID_PF_NUM_MASK
) != pfid
)
11157 if (IGU_VEC(val
) == 0)
11158 /* default status block */
11159 bp
->igu_dsb_id
= igu_sb_id
;
11161 if (bp
->igu_base_sb
== 0xff)
11162 bp
->igu_base_sb
= igu_sb_id
;
11168 #ifdef CONFIG_PCI_MSI
11169 /* Due to new PF resource allocation by MFW T7.4 and above, it's
11170 * optional that number of CAM entries will not be equal to the value
11171 * advertised in PCI.
11172 * Driver should use the minimal value of both as the actual status
11175 bp
->igu_sb_cnt
= min_t(int, bp
->igu_sb_cnt
, igu_sb_cnt
);
11178 if (igu_sb_cnt
== 0) {
11179 BNX2X_ERR("CAM configuration error\n");
11186 static void bnx2x_link_settings_supported(struct bnx2x
*bp
, u32 switch_cfg
)
11188 int cfg_size
= 0, idx
, port
= BP_PORT(bp
);
11190 /* Aggregation of supported attributes of all external phys */
11191 bp
->port
.supported
[0] = 0;
11192 bp
->port
.supported
[1] = 0;
11193 switch (bp
->link_params
.num_phys
) {
11195 bp
->port
.supported
[0] = bp
->link_params
.phy
[INT_PHY
].supported
;
11199 bp
->port
.supported
[0] = bp
->link_params
.phy
[EXT_PHY1
].supported
;
11203 if (bp
->link_params
.multi_phy_config
&
11204 PORT_HW_CFG_PHY_SWAPPED_ENABLED
) {
11205 bp
->port
.supported
[1] =
11206 bp
->link_params
.phy
[EXT_PHY1
].supported
;
11207 bp
->port
.supported
[0] =
11208 bp
->link_params
.phy
[EXT_PHY2
].supported
;
11210 bp
->port
.supported
[0] =
11211 bp
->link_params
.phy
[EXT_PHY1
].supported
;
11212 bp
->port
.supported
[1] =
11213 bp
->link_params
.phy
[EXT_PHY2
].supported
;
11219 if (!(bp
->port
.supported
[0] || bp
->port
.supported
[1])) {
11220 BNX2X_ERR("NVRAM config error. BAD phy config. PHY1 config 0x%x, PHY2 config 0x%x\n",
11222 dev_info
.port_hw_config
[port
].external_phy_config
),
11224 dev_info
.port_hw_config
[port
].external_phy_config2
));
11228 if (CHIP_IS_E3(bp
))
11229 bp
->port
.phy_addr
= REG_RD(bp
, MISC_REG_WC0_CTRL_PHY_ADDR
);
11231 switch (switch_cfg
) {
11232 case SWITCH_CFG_1G
:
11233 bp
->port
.phy_addr
= REG_RD(
11234 bp
, NIG_REG_SERDES0_CTRL_PHY_ADDR
+ port
*0x10);
11236 case SWITCH_CFG_10G
:
11237 bp
->port
.phy_addr
= REG_RD(
11238 bp
, NIG_REG_XGXS0_CTRL_PHY_ADDR
+ port
*0x18);
11241 BNX2X_ERR("BAD switch_cfg link_config 0x%x\n",
11242 bp
->port
.link_config
[0]);
11246 BNX2X_DEV_INFO("phy_addr 0x%x\n", bp
->port
.phy_addr
);
11247 /* mask what we support according to speed_cap_mask per configuration */
11248 for (idx
= 0; idx
< cfg_size
; idx
++) {
11249 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11250 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF
))
11251 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Half
;
11253 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11254 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL
))
11255 bp
->port
.supported
[idx
] &= ~SUPPORTED_10baseT_Full
;
11257 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11258 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF
))
11259 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Half
;
11261 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11262 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL
))
11263 bp
->port
.supported
[idx
] &= ~SUPPORTED_100baseT_Full
;
11265 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11266 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G
))
11267 bp
->port
.supported
[idx
] &= ~(SUPPORTED_1000baseT_Half
|
11268 SUPPORTED_1000baseT_Full
);
11270 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11271 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G
))
11272 bp
->port
.supported
[idx
] &= ~SUPPORTED_2500baseX_Full
;
11274 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11275 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G
))
11276 bp
->port
.supported
[idx
] &= ~SUPPORTED_10000baseT_Full
;
11278 if (!(bp
->link_params
.speed_cap_mask
[idx
] &
11279 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G
))
11280 bp
->port
.supported
[idx
] &= ~SUPPORTED_20000baseKR2_Full
;
11283 BNX2X_DEV_INFO("supported 0x%x 0x%x\n", bp
->port
.supported
[0],
11284 bp
->port
.supported
[1]);
11287 static void bnx2x_link_settings_requested(struct bnx2x
*bp
)
11289 u32 link_config
, idx
, cfg_size
= 0;
11290 bp
->port
.advertising
[0] = 0;
11291 bp
->port
.advertising
[1] = 0;
11292 switch (bp
->link_params
.num_phys
) {
11301 for (idx
= 0; idx
< cfg_size
; idx
++) {
11302 bp
->link_params
.req_duplex
[idx
] = DUPLEX_FULL
;
11303 link_config
= bp
->port
.link_config
[idx
];
11304 switch (link_config
& PORT_FEATURE_LINK_SPEED_MASK
) {
11305 case PORT_FEATURE_LINK_SPEED_AUTO
:
11306 if (bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
) {
11307 bp
->link_params
.req_line_speed
[idx
] =
11309 bp
->port
.advertising
[idx
] |=
11310 bp
->port
.supported
[idx
];
11311 if (bp
->link_params
.phy
[EXT_PHY1
].type
==
11312 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833
)
11313 bp
->port
.advertising
[idx
] |=
11314 (SUPPORTED_100baseT_Half
|
11315 SUPPORTED_100baseT_Full
);
11317 /* force 10G, no AN */
11318 bp
->link_params
.req_line_speed
[idx
] =
11320 bp
->port
.advertising
[idx
] |=
11321 (ADVERTISED_10000baseT_Full
|
11327 case PORT_FEATURE_LINK_SPEED_10M_FULL
:
11328 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Full
) {
11329 bp
->link_params
.req_line_speed
[idx
] =
11331 bp
->port
.advertising
[idx
] |=
11332 (ADVERTISED_10baseT_Full
|
11335 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11337 bp
->link_params
.speed_cap_mask
[idx
]);
11342 case PORT_FEATURE_LINK_SPEED_10M_HALF
:
11343 if (bp
->port
.supported
[idx
] & SUPPORTED_10baseT_Half
) {
11344 bp
->link_params
.req_line_speed
[idx
] =
11346 bp
->link_params
.req_duplex
[idx
] =
11348 bp
->port
.advertising
[idx
] |=
11349 (ADVERTISED_10baseT_Half
|
11352 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11354 bp
->link_params
.speed_cap_mask
[idx
]);
11359 case PORT_FEATURE_LINK_SPEED_100M_FULL
:
11360 if (bp
->port
.supported
[idx
] &
11361 SUPPORTED_100baseT_Full
) {
11362 bp
->link_params
.req_line_speed
[idx
] =
11364 bp
->port
.advertising
[idx
] |=
11365 (ADVERTISED_100baseT_Full
|
11368 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11370 bp
->link_params
.speed_cap_mask
[idx
]);
11375 case PORT_FEATURE_LINK_SPEED_100M_HALF
:
11376 if (bp
->port
.supported
[idx
] &
11377 SUPPORTED_100baseT_Half
) {
11378 bp
->link_params
.req_line_speed
[idx
] =
11380 bp
->link_params
.req_duplex
[idx
] =
11382 bp
->port
.advertising
[idx
] |=
11383 (ADVERTISED_100baseT_Half
|
11386 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11388 bp
->link_params
.speed_cap_mask
[idx
]);
11393 case PORT_FEATURE_LINK_SPEED_1G
:
11394 if (bp
->port
.supported
[idx
] &
11395 SUPPORTED_1000baseT_Full
) {
11396 bp
->link_params
.req_line_speed
[idx
] =
11398 bp
->port
.advertising
[idx
] |=
11399 (ADVERTISED_1000baseT_Full
|
11401 } else if (bp
->port
.supported
[idx
] &
11402 SUPPORTED_1000baseKX_Full
) {
11403 bp
->link_params
.req_line_speed
[idx
] =
11405 bp
->port
.advertising
[idx
] |=
11406 ADVERTISED_1000baseKX_Full
;
11408 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11410 bp
->link_params
.speed_cap_mask
[idx
]);
11415 case PORT_FEATURE_LINK_SPEED_2_5G
:
11416 if (bp
->port
.supported
[idx
] &
11417 SUPPORTED_2500baseX_Full
) {
11418 bp
->link_params
.req_line_speed
[idx
] =
11420 bp
->port
.advertising
[idx
] |=
11421 (ADVERTISED_2500baseX_Full
|
11424 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11426 bp
->link_params
.speed_cap_mask
[idx
]);
11431 case PORT_FEATURE_LINK_SPEED_10G_CX4
:
11432 if (bp
->port
.supported
[idx
] &
11433 SUPPORTED_10000baseT_Full
) {
11434 bp
->link_params
.req_line_speed
[idx
] =
11436 bp
->port
.advertising
[idx
] |=
11437 (ADVERTISED_10000baseT_Full
|
11439 } else if (bp
->port
.supported
[idx
] &
11440 SUPPORTED_10000baseKR_Full
) {
11441 bp
->link_params
.req_line_speed
[idx
] =
11443 bp
->port
.advertising
[idx
] |=
11444 (ADVERTISED_10000baseKR_Full
|
11447 BNX2X_ERR("NVRAM config error. Invalid link_config 0x%x speed_cap_mask 0x%x\n",
11449 bp
->link_params
.speed_cap_mask
[idx
]);
11453 case PORT_FEATURE_LINK_SPEED_20G
:
11454 bp
->link_params
.req_line_speed
[idx
] = SPEED_20000
;
11458 BNX2X_ERR("NVRAM config error. BAD link speed link_config 0x%x\n",
11460 bp
->link_params
.req_line_speed
[idx
] =
11462 bp
->port
.advertising
[idx
] =
11463 bp
->port
.supported
[idx
];
11467 bp
->link_params
.req_flow_ctrl
[idx
] = (link_config
&
11468 PORT_FEATURE_FLOW_CONTROL_MASK
);
11469 if (bp
->link_params
.req_flow_ctrl
[idx
] ==
11470 BNX2X_FLOW_CTRL_AUTO
) {
11471 if (!(bp
->port
.supported
[idx
] & SUPPORTED_Autoneg
))
11472 bp
->link_params
.req_flow_ctrl
[idx
] =
11473 BNX2X_FLOW_CTRL_NONE
;
11475 bnx2x_set_requested_fc(bp
);
11478 BNX2X_DEV_INFO("req_line_speed %d req_duplex %d req_flow_ctrl 0x%x advertising 0x%x\n",
11479 bp
->link_params
.req_line_speed
[idx
],
11480 bp
->link_params
.req_duplex
[idx
],
11481 bp
->link_params
.req_flow_ctrl
[idx
],
11482 bp
->port
.advertising
[idx
]);
11486 static void bnx2x_set_mac_buf(u8
*mac_buf
, u32 mac_lo
, u16 mac_hi
)
11488 __be16 mac_hi_be
= cpu_to_be16(mac_hi
);
11489 __be32 mac_lo_be
= cpu_to_be32(mac_lo
);
11490 memcpy(mac_buf
, &mac_hi_be
, sizeof(mac_hi_be
));
11491 memcpy(mac_buf
+ sizeof(mac_hi_be
), &mac_lo_be
, sizeof(mac_lo_be
));
11494 static void bnx2x_get_port_hwinfo(struct bnx2x
*bp
)
11496 int port
= BP_PORT(bp
);
11498 u32 ext_phy_type
, ext_phy_config
, eee_mode
;
11500 bp
->link_params
.bp
= bp
;
11501 bp
->link_params
.port
= port
;
11503 bp
->link_params
.lane_config
=
11504 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].lane_config
);
11506 bp
->link_params
.speed_cap_mask
[0] =
11508 dev_info
.port_hw_config
[port
].speed_capability_mask
) &
11509 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK
;
11510 bp
->link_params
.speed_cap_mask
[1] =
11512 dev_info
.port_hw_config
[port
].speed_capability_mask2
) &
11513 PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK
;
11514 bp
->port
.link_config
[0] =
11515 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config
);
11517 bp
->port
.link_config
[1] =
11518 SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].link_config2
);
11520 bp
->link_params
.multi_phy_config
=
11521 SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].multi_phy_config
);
11522 /* If the device is capable of WoL, set the default state according
11525 config
= SHMEM_RD(bp
, dev_info
.port_feature_config
[port
].config
);
11526 bp
->wol
= (!(bp
->flags
& NO_WOL_FLAG
) &&
11527 (config
& PORT_FEATURE_WOL_ENABLED
));
11529 if ((config
& PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK
) ==
11530 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE
&& !IS_MF(bp
))
11531 bp
->flags
|= NO_ISCSI_FLAG
;
11532 if ((config
& PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK
) ==
11533 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI
&& !(IS_MF(bp
)))
11534 bp
->flags
|= NO_FCOE_FLAG
;
11536 BNX2X_DEV_INFO("lane_config 0x%08x speed_cap_mask0 0x%08x link_config0 0x%08x\n",
11537 bp
->link_params
.lane_config
,
11538 bp
->link_params
.speed_cap_mask
[0],
11539 bp
->port
.link_config
[0]);
11541 bp
->link_params
.switch_cfg
= (bp
->port
.link_config
[0] &
11542 PORT_FEATURE_CONNECTED_SWITCH_MASK
);
11543 bnx2x_phy_probe(&bp
->link_params
);
11544 bnx2x_link_settings_supported(bp
, bp
->link_params
.switch_cfg
);
11546 bnx2x_link_settings_requested(bp
);
11549 * If connected directly, work with the internal PHY, otherwise, work
11550 * with the external PHY
11554 dev_info
.port_hw_config
[port
].external_phy_config
);
11555 ext_phy_type
= XGXS_EXT_PHY_TYPE(ext_phy_config
);
11556 if (ext_phy_type
== PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT
)
11557 bp
->mdio
.prtad
= bp
->port
.phy_addr
;
11559 else if ((ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE
) &&
11560 (ext_phy_type
!= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN
))
11562 XGXS_EXT_PHY_ADDR(ext_phy_config
);
11564 /* Configure link feature according to nvram value */
11565 eee_mode
= (((SHMEM_RD(bp
, dev_info
.
11566 port_feature_config
[port
].eee_power_mode
)) &
11567 PORT_FEAT_CFG_EEE_POWER_MODE_MASK
) >>
11568 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT
);
11569 if (eee_mode
!= PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED
) {
11570 bp
->link_params
.eee_mode
= EEE_MODE_ADV_LPI
|
11571 EEE_MODE_ENABLE_LPI
|
11572 EEE_MODE_OUTPUT_TIME
;
11574 bp
->link_params
.eee_mode
= 0;
11578 void bnx2x_get_iscsi_info(struct bnx2x
*bp
)
11580 u32 no_flags
= NO_ISCSI_FLAG
;
11581 int port
= BP_PORT(bp
);
11582 u32 max_iscsi_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
11583 drv_lic_key
[port
].max_iscsi_conn
);
11585 if (!CNIC_SUPPORT(bp
)) {
11586 bp
->flags
|= no_flags
;
11590 /* Get the number of maximum allowed iSCSI connections */
11591 bp
->cnic_eth_dev
.max_iscsi_conn
=
11592 (max_iscsi_conn
& BNX2X_MAX_ISCSI_INIT_CONN_MASK
) >>
11593 BNX2X_MAX_ISCSI_INIT_CONN_SHIFT
;
11595 BNX2X_DEV_INFO("max_iscsi_conn 0x%x\n",
11596 bp
->cnic_eth_dev
.max_iscsi_conn
);
11599 * If maximum allowed number of connections is zero -
11600 * disable the feature.
11602 if (!bp
->cnic_eth_dev
.max_iscsi_conn
)
11603 bp
->flags
|= no_flags
;
11606 static void bnx2x_get_ext_wwn_info(struct bnx2x
*bp
, int func
)
11609 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
11610 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_upper
);
11611 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
11612 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_port_name_lower
);
11615 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
11616 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_upper
);
11617 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
11618 MF_CFG_RD(bp
, func_ext_config
[func
].fcoe_wwn_node_name_lower
);
11621 static int bnx2x_shared_fcoe_funcs(struct bnx2x
*bp
)
11628 /* iterate over absolute function ids for this path: */
11629 for (fid
= BP_PATH(bp
); fid
< E2_FUNC_MAX
* 2; fid
+= 2) {
11630 if (IS_MF_SD(bp
)) {
11631 u32 cfg
= MF_CFG_RD(bp
,
11632 func_mf_config
[fid
].config
);
11634 if (!(cfg
& FUNC_MF_CFG_FUNC_HIDE
) &&
11635 ((cfg
& FUNC_MF_CFG_PROTOCOL_MASK
) ==
11636 FUNC_MF_CFG_PROTOCOL_FCOE
))
11639 u32 cfg
= MF_CFG_RD(bp
,
11640 func_ext_config
[fid
].
11643 if ((cfg
& MACP_FUNC_CFG_FLAGS_ENABLED
) &&
11644 (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
))
11649 int port
, port_cnt
= CHIP_MODE_IS_4_PORT(bp
) ? 2 : 1;
11651 for (port
= 0; port
< port_cnt
; port
++) {
11652 u32 lic
= SHMEM_RD(bp
,
11653 drv_lic_key
[port
].max_fcoe_conn
) ^
11654 FW_ENCODE_32BIT_PATTERN
;
11663 static void bnx2x_get_fcoe_info(struct bnx2x
*bp
)
11665 int port
= BP_PORT(bp
);
11666 int func
= BP_ABS_FUNC(bp
);
11667 u32 max_fcoe_conn
= FW_ENCODE_32BIT_PATTERN
^ SHMEM_RD(bp
,
11668 drv_lic_key
[port
].max_fcoe_conn
);
11669 u8 num_fcoe_func
= bnx2x_shared_fcoe_funcs(bp
);
11671 if (!CNIC_SUPPORT(bp
)) {
11672 bp
->flags
|= NO_FCOE_FLAG
;
11676 /* Get the number of maximum allowed FCoE connections */
11677 bp
->cnic_eth_dev
.max_fcoe_conn
=
11678 (max_fcoe_conn
& BNX2X_MAX_FCOE_INIT_CONN_MASK
) >>
11679 BNX2X_MAX_FCOE_INIT_CONN_SHIFT
;
11681 /* Calculate the number of maximum allowed FCoE tasks */
11682 bp
->cnic_eth_dev
.max_fcoe_exchanges
= MAX_NUM_FCOE_TASKS_PER_ENGINE
;
11684 /* check if FCoE resources must be shared between different functions */
11686 bp
->cnic_eth_dev
.max_fcoe_exchanges
/= num_fcoe_func
;
11688 /* Read the WWN: */
11691 bp
->cnic_eth_dev
.fcoe_wwn_port_name_hi
=
11693 dev_info
.port_hw_config
[port
].
11694 fcoe_wwn_port_name_upper
);
11695 bp
->cnic_eth_dev
.fcoe_wwn_port_name_lo
=
11697 dev_info
.port_hw_config
[port
].
11698 fcoe_wwn_port_name_lower
);
11701 bp
->cnic_eth_dev
.fcoe_wwn_node_name_hi
=
11703 dev_info
.port_hw_config
[port
].
11704 fcoe_wwn_node_name_upper
);
11705 bp
->cnic_eth_dev
.fcoe_wwn_node_name_lo
=
11707 dev_info
.port_hw_config
[port
].
11708 fcoe_wwn_node_name_lower
);
11709 } else if (!IS_MF_SD(bp
)) {
11710 /* Read the WWN info only if the FCoE feature is enabled for
11713 if (BNX2X_HAS_MF_EXT_PROTOCOL_FCOE(bp
))
11714 bnx2x_get_ext_wwn_info(bp
, func
);
11716 if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
) && !CHIP_IS_E1x(bp
))
11717 bnx2x_get_ext_wwn_info(bp
, func
);
11720 BNX2X_DEV_INFO("max_fcoe_conn 0x%x\n", bp
->cnic_eth_dev
.max_fcoe_conn
);
11723 * If maximum allowed number of connections is zero -
11724 * disable the feature.
11726 if (!bp
->cnic_eth_dev
.max_fcoe_conn
)
11727 bp
->flags
|= NO_FCOE_FLAG
;
11730 static void bnx2x_get_cnic_info(struct bnx2x
*bp
)
11733 * iSCSI may be dynamically disabled but reading
11734 * info here we will decrease memory usage by driver
11735 * if the feature is disabled for good
11737 bnx2x_get_iscsi_info(bp
);
11738 bnx2x_get_fcoe_info(bp
);
11741 static void bnx2x_get_cnic_mac_hwinfo(struct bnx2x
*bp
)
11744 int func
= BP_ABS_FUNC(bp
);
11745 int port
= BP_PORT(bp
);
11746 u8
*iscsi_mac
= bp
->cnic_eth_dev
.iscsi_mac
;
11747 u8
*fip_mac
= bp
->fip_mac
;
11750 /* iSCSI and FCoE NPAR MACs: if there is no either iSCSI or
11751 * FCoE MAC then the appropriate feature should be disabled.
11752 * In non SD mode features configuration comes from struct
11755 if (!IS_MF_SD(bp
)) {
11756 u32 cfg
= MF_CFG_RD(bp
, func_ext_config
[func
].func_cfg
);
11757 if (cfg
& MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD
) {
11758 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
11759 iscsi_mac_addr_upper
);
11760 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
11761 iscsi_mac_addr_lower
);
11762 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
11764 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
11766 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
11769 if (cfg
& MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD
) {
11770 val2
= MF_CFG_RD(bp
, func_ext_config
[func
].
11771 fcoe_mac_addr_upper
);
11772 val
= MF_CFG_RD(bp
, func_ext_config
[func
].
11773 fcoe_mac_addr_lower
);
11774 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
11776 ("Read FCoE L2 MAC: %pM\n", fip_mac
);
11778 bp
->flags
|= NO_FCOE_FLAG
;
11781 bp
->mf_ext_config
= cfg
;
11783 } else { /* SD MODE */
11784 if (BNX2X_IS_MF_SD_PROTOCOL_ISCSI(bp
)) {
11785 /* use primary mac as iscsi mac */
11786 memcpy(iscsi_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
11788 BNX2X_DEV_INFO("SD ISCSI MODE\n");
11790 ("Read iSCSI MAC: %pM\n", iscsi_mac
);
11791 } else if (BNX2X_IS_MF_SD_PROTOCOL_FCOE(bp
)) {
11792 /* use primary mac as fip mac */
11793 memcpy(fip_mac
, bp
->dev
->dev_addr
, ETH_ALEN
);
11794 BNX2X_DEV_INFO("SD FCoE MODE\n");
11796 ("Read FIP MAC: %pM\n", fip_mac
);
11800 /* If this is a storage-only interface, use SAN mac as
11801 * primary MAC. Notice that for SD this is already the case,
11802 * as the SAN mac was copied from the primary MAC.
11804 if (IS_MF_FCOE_AFEX(bp
))
11805 memcpy(bp
->dev
->dev_addr
, fip_mac
, ETH_ALEN
);
11807 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11809 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11811 bnx2x_set_mac_buf(iscsi_mac
, val
, val2
);
11813 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11814 fcoe_fip_mac_upper
);
11815 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].
11816 fcoe_fip_mac_lower
);
11817 bnx2x_set_mac_buf(fip_mac
, val
, val2
);
11820 /* Disable iSCSI OOO if MAC configuration is invalid. */
11821 if (!is_valid_ether_addr(iscsi_mac
)) {
11822 bp
->flags
|= NO_ISCSI_OOO_FLAG
| NO_ISCSI_FLAG
;
11823 eth_zero_addr(iscsi_mac
);
11826 /* Disable FCoE if MAC configuration is invalid. */
11827 if (!is_valid_ether_addr(fip_mac
)) {
11828 bp
->flags
|= NO_FCOE_FLAG
;
11829 eth_zero_addr(bp
->fip_mac
);
11833 static void bnx2x_get_mac_hwinfo(struct bnx2x
*bp
)
11836 int func
= BP_ABS_FUNC(bp
);
11837 int port
= BP_PORT(bp
);
11839 /* Zero primary MAC configuration */
11840 eth_zero_addr(bp
->dev
->dev_addr
);
11842 if (BP_NOMCP(bp
)) {
11843 BNX2X_ERROR("warning: random MAC workaround active\n");
11844 eth_hw_addr_random(bp
->dev
);
11845 } else if (IS_MF(bp
)) {
11846 val2
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
11847 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_lower
);
11848 if ((val2
!= FUNC_MF_CFG_UPPERMAC_DEFAULT
) &&
11849 (val
!= FUNC_MF_CFG_LOWERMAC_DEFAULT
))
11850 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
11852 if (CNIC_SUPPORT(bp
))
11853 bnx2x_get_cnic_mac_hwinfo(bp
);
11855 /* in SF read MACs from port configuration */
11856 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
11857 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
11858 bnx2x_set_mac_buf(bp
->dev
->dev_addr
, val
, val2
);
11860 if (CNIC_SUPPORT(bp
))
11861 bnx2x_get_cnic_mac_hwinfo(bp
);
11864 if (!BP_NOMCP(bp
)) {
11865 /* Read physical port identifier from shmem */
11866 val2
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_upper
);
11867 val
= SHMEM_RD(bp
, dev_info
.port_hw_config
[port
].mac_lower
);
11868 bnx2x_set_mac_buf(bp
->phys_port_id
, val
, val2
);
11869 bp
->flags
|= HAS_PHYS_PORT_ID
;
11872 memcpy(bp
->link_params
.mac_addr
, bp
->dev
->dev_addr
, ETH_ALEN
);
11874 if (!is_valid_ether_addr(bp
->dev
->dev_addr
))
11875 dev_err(&bp
->pdev
->dev
,
11876 "bad Ethernet MAC address configuration: %pM\n"
11877 "change it manually before bringing up the appropriate network interface\n",
11878 bp
->dev
->dev_addr
);
11881 static bool bnx2x_get_dropless_info(struct bnx2x
*bp
)
11889 if (IS_MF(bp
) && !CHIP_IS_E1x(bp
)) {
11890 /* Take function: tmp = func */
11891 tmp
= BP_ABS_FUNC(bp
);
11892 cfg
= MF_CFG_RD(bp
, func_ext_config
[tmp
].func_cfg
);
11893 cfg
= !!(cfg
& MACP_FUNC_CFG_PAUSE_ON_HOST_RING
);
11895 /* Take port: tmp = port */
11898 dev_info
.port_hw_config
[tmp
].generic_features
);
11899 cfg
= !!(cfg
& PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED
);
11904 static void validate_set_si_mode(struct bnx2x
*bp
)
11906 u8 func
= BP_ABS_FUNC(bp
);
11909 val
= MF_CFG_RD(bp
, func_mf_config
[func
].mac_upper
);
11911 /* check for legal mac (upper bytes) */
11912 if (val
!= 0xffff) {
11913 bp
->mf_mode
= MULTI_FUNCTION_SI
;
11914 bp
->mf_config
[BP_VN(bp
)] =
11915 MF_CFG_RD(bp
, func_mf_config
[func
].config
);
11917 BNX2X_DEV_INFO("illegal MAC address for SI\n");
11920 static int bnx2x_get_hwinfo(struct bnx2x
*bp
)
11922 int /*abs*/func
= BP_ABS_FUNC(bp
);
11924 u32 val
= 0, val2
= 0;
11927 /* Validate that chip access is feasible */
11928 if (REG_RD(bp
, MISC_REG_CHIP_NUM
) == 0xffffffff) {
11929 dev_err(&bp
->pdev
->dev
,
11930 "Chip read returns all Fs. Preventing probe from continuing\n");
11934 bnx2x_get_common_hwinfo(bp
);
11937 * initialize IGU parameters
11939 if (CHIP_IS_E1x(bp
)) {
11940 bp
->common
.int_block
= INT_BLOCK_HC
;
11942 bp
->igu_dsb_id
= DEF_SB_IGU_ID
;
11943 bp
->igu_base_sb
= 0;
11945 bp
->common
.int_block
= INT_BLOCK_IGU
;
11947 /* do not allow device reset during IGU info processing */
11948 bnx2x_acquire_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
11950 val
= REG_RD(bp
, IGU_REG_BLOCK_CONFIGURATION
);
11952 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
11955 BNX2X_DEV_INFO("FORCING Normal Mode\n");
11957 val
&= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
);
11958 REG_WR(bp
, IGU_REG_BLOCK_CONFIGURATION
, val
);
11959 REG_WR(bp
, IGU_REG_RESET_MEMORIES
, 0x7f);
11961 while (tout
&& REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
11963 usleep_range(1000, 2000);
11966 if (REG_RD(bp
, IGU_REG_RESET_MEMORIES
)) {
11967 dev_err(&bp
->pdev
->dev
,
11968 "FORCING Normal Mode failed!!!\n");
11969 bnx2x_release_hw_lock(bp
,
11970 HW_LOCK_RESOURCE_RESET
);
11975 if (val
& IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN
) {
11976 BNX2X_DEV_INFO("IGU Backward Compatible Mode\n");
11977 bp
->common
.int_block
|= INT_BLOCK_MODE_BW_COMP
;
11979 BNX2X_DEV_INFO("IGU Normal Mode\n");
11981 rc
= bnx2x_get_igu_cam_info(bp
);
11982 bnx2x_release_hw_lock(bp
, HW_LOCK_RESOURCE_RESET
);
11988 * set base FW non-default (fast path) status block id, this value is
11989 * used to initialize the fw_sb_id saved on the fp/queue structure to
11990 * determine the id used by the FW.
11992 if (CHIP_IS_E1x(bp
))
11993 bp
->base_fw_ndsb
= BP_PORT(bp
) * FP_SB_MAX_E1x
+ BP_L_ID(bp
);
11995 * 57712 - we currently use one FW SB per IGU SB (Rx and Tx of
11996 * the same queue are indicated on the same IGU SB). So we prefer
11997 * FW and IGU SBs to be the same value.
11999 bp
->base_fw_ndsb
= bp
->igu_base_sb
;
12001 BNX2X_DEV_INFO("igu_dsb_id %d igu_base_sb %d igu_sb_cnt %d\n"
12002 "base_fw_ndsb %d\n", bp
->igu_dsb_id
, bp
->igu_base_sb
,
12003 bp
->igu_sb_cnt
, bp
->base_fw_ndsb
);
12006 * Initialize MF configuration
12011 bp
->mf_sub_mode
= 0;
12013 mfw_vn
= BP_FW_MB_IDX(bp
);
12015 if (!CHIP_IS_E1(bp
) && !BP_NOMCP(bp
)) {
12016 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
12017 bp
->common
.shmem2_base
, SHMEM2_RD(bp
, size
),
12018 (u32
)offsetof(struct shmem2_region
, mf_cfg_addr
));
12020 if (SHMEM2_HAS(bp
, mf_cfg_addr
))
12021 bp
->common
.mf_cfg_base
= SHMEM2_RD(bp
, mf_cfg_addr
);
12023 bp
->common
.mf_cfg_base
= bp
->common
.shmem_base
+
12024 offsetof(struct shmem_region
, func_mb
) +
12025 E1H_FUNC_MAX
* sizeof(struct drv_func_mb
);
12027 * get mf configuration:
12028 * 1. Existence of MF configuration
12029 * 2. MAC address must be legal (check only upper bytes)
12030 * for Switch-Independent mode;
12031 * OVLAN must be legal for Switch-Dependent mode
12032 * 3. SF_MODE configures specific MF mode
12034 if (bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
12035 /* get mf configuration */
12037 dev_info
.shared_feature_config
.config
);
12038 val
&= SHARED_FEAT_CFG_FORCE_SF_MODE_MASK
;
12041 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT
:
12042 validate_set_si_mode(bp
);
12044 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE
:
12045 if ((!CHIP_IS_E1x(bp
)) &&
12046 (MF_CFG_RD(bp
, func_mf_config
[func
].
12047 mac_upper
) != 0xffff) &&
12049 afex_driver_support
))) {
12050 bp
->mf_mode
= MULTI_FUNCTION_AFEX
;
12051 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
12052 func_mf_config
[func
].config
);
12054 BNX2X_DEV_INFO("can not configure afex mode\n");
12057 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED
:
12058 /* get OV configuration */
12059 val
= MF_CFG_RD(bp
,
12060 func_mf_config
[FUNC_0
].e1hov_tag
);
12061 val
&= FUNC_MF_CFG_E1HOV_TAG_MASK
;
12063 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
12064 bp
->mf_mode
= MULTI_FUNCTION_SD
;
12065 bp
->mf_config
[vn
] = MF_CFG_RD(bp
,
12066 func_mf_config
[func
].config
);
12068 BNX2X_DEV_INFO("illegal OV for SD\n");
12070 case SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE
:
12071 bp
->mf_mode
= MULTI_FUNCTION_SD
;
12072 bp
->mf_sub_mode
= SUB_MF_MODE_BD
;
12073 bp
->mf_config
[vn
] =
12075 func_mf_config
[func
].config
);
12077 if (SHMEM2_HAS(bp
, mtu_size
)) {
12078 int mtu_idx
= BP_FW_MB_IDX(bp
);
12082 mtu
= SHMEM2_RD(bp
, mtu_size
[mtu_idx
]);
12083 mtu_size
= (u16
)mtu
;
12084 DP(NETIF_MSG_IFUP
, "Read MTU size %04x [%08x]\n",
12087 /* if valid: update device mtu */
12088 if (((mtu_size
+ ETH_HLEN
) >=
12089 ETH_MIN_PACKET_SIZE
) &&
12091 ETH_MAX_JUMBO_PACKET_SIZE
))
12092 bp
->dev
->mtu
= mtu_size
;
12095 case SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE
:
12096 bp
->mf_mode
= MULTI_FUNCTION_SD
;
12097 bp
->mf_sub_mode
= SUB_MF_MODE_UFP
;
12098 bp
->mf_config
[vn
] =
12100 func_mf_config
[func
].config
);
12102 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF
:
12103 bp
->mf_config
[vn
] = 0;
12105 case SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE
:
12106 val2
= SHMEM_RD(bp
,
12107 dev_info
.shared_hw_config
.config_3
);
12108 val2
&= SHARED_HW_CFG_EXTENDED_MF_MODE_MASK
;
12110 case SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5
:
12111 validate_set_si_mode(bp
);
12113 SUB_MF_MODE_NPAR1_DOT_5
;
12116 /* Unknown configuration */
12117 bp
->mf_config
[vn
] = 0;
12118 BNX2X_DEV_INFO("unknown extended MF mode 0x%x\n",
12123 /* Unknown configuration: reset mf_config */
12124 bp
->mf_config
[vn
] = 0;
12125 BNX2X_DEV_INFO("unknown MF mode 0x%x\n", val
);
12129 BNX2X_DEV_INFO("%s function mode\n",
12130 IS_MF(bp
) ? "multi" : "single");
12132 switch (bp
->mf_mode
) {
12133 case MULTI_FUNCTION_SD
:
12134 val
= MF_CFG_RD(bp
, func_mf_config
[func
].e1hov_tag
) &
12135 FUNC_MF_CFG_E1HOV_TAG_MASK
;
12136 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
) {
12138 bp
->path_has_ovlan
= true;
12140 BNX2X_DEV_INFO("MF OV for func %d is %d (0x%04x)\n",
12141 func
, bp
->mf_ov
, bp
->mf_ov
);
12142 } else if ((bp
->mf_sub_mode
== SUB_MF_MODE_UFP
) ||
12143 (bp
->mf_sub_mode
== SUB_MF_MODE_BD
)) {
12144 dev_err(&bp
->pdev
->dev
,
12145 "Unexpected - no valid MF OV for func %d in UFP/BD mode\n",
12147 bp
->path_has_ovlan
= true;
12149 dev_err(&bp
->pdev
->dev
,
12150 "No valid MF OV for func %d, aborting\n",
12155 case MULTI_FUNCTION_AFEX
:
12156 BNX2X_DEV_INFO("func %d is in MF afex mode\n", func
);
12158 case MULTI_FUNCTION_SI
:
12159 BNX2X_DEV_INFO("func %d is in MF switch-independent mode\n",
12164 dev_err(&bp
->pdev
->dev
,
12165 "VN %d is in a single function mode, aborting\n",
12172 /* check if other port on the path needs ovlan:
12173 * Since MF configuration is shared between ports
12174 * Possible mixed modes are only
12175 * {SF, SI} {SF, SD} {SD, SF} {SI, SF}
12177 if (CHIP_MODE_IS_4_PORT(bp
) &&
12178 !bp
->path_has_ovlan
&&
12180 bp
->common
.mf_cfg_base
!= SHMEM_MF_CFG_ADDR_NONE
) {
12181 u8 other_port
= !BP_PORT(bp
);
12182 u8 other_func
= BP_PATH(bp
) + 2*other_port
;
12183 val
= MF_CFG_RD(bp
,
12184 func_mf_config
[other_func
].e1hov_tag
);
12185 if (val
!= FUNC_MF_CFG_E1HOV_TAG_DEFAULT
)
12186 bp
->path_has_ovlan
= true;
12190 /* adjust igu_sb_cnt to MF for E1H */
12191 if (CHIP_IS_E1H(bp
) && IS_MF(bp
))
12192 bp
->igu_sb_cnt
= min_t(u8
, bp
->igu_sb_cnt
, E1H_MAX_MF_SB_COUNT
);
12195 bnx2x_get_port_hwinfo(bp
);
12197 /* Get MAC addresses */
12198 bnx2x_get_mac_hwinfo(bp
);
12200 bnx2x_get_cnic_info(bp
);
12205 static void bnx2x_read_fwinfo(struct bnx2x
*bp
)
12207 int cnt
, i
, block_end
, rodi
;
12208 char vpd_start
[BNX2X_VPD_LEN
+1];
12209 char str_id_reg
[VENDOR_ID_LEN
+1];
12210 char str_id_cap
[VENDOR_ID_LEN
+1];
12212 char *vpd_extended_data
= NULL
;
12215 cnt
= pci_read_vpd(bp
->pdev
, 0, BNX2X_VPD_LEN
, vpd_start
);
12216 memset(bp
->fw_ver
, 0, sizeof(bp
->fw_ver
));
12218 if (cnt
< BNX2X_VPD_LEN
)
12219 goto out_not_found
;
12221 /* VPD RO tag should be first tag after identifier string, hence
12222 * we should be able to find it in first BNX2X_VPD_LEN chars
12224 i
= pci_vpd_find_tag(vpd_start
, 0, BNX2X_VPD_LEN
,
12225 PCI_VPD_LRDT_RO_DATA
);
12227 goto out_not_found
;
12229 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+
12230 pci_vpd_lrdt_size(&vpd_start
[i
]);
12232 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12234 if (block_end
> BNX2X_VPD_LEN
) {
12235 vpd_extended_data
= kmalloc(block_end
, GFP_KERNEL
);
12236 if (vpd_extended_data
== NULL
)
12237 goto out_not_found
;
12239 /* read rest of vpd image into vpd_extended_data */
12240 memcpy(vpd_extended_data
, vpd_start
, BNX2X_VPD_LEN
);
12241 cnt
= pci_read_vpd(bp
->pdev
, BNX2X_VPD_LEN
,
12242 block_end
- BNX2X_VPD_LEN
,
12243 vpd_extended_data
+ BNX2X_VPD_LEN
);
12244 if (cnt
< (block_end
- BNX2X_VPD_LEN
))
12245 goto out_not_found
;
12246 vpd_data
= vpd_extended_data
;
12248 vpd_data
= vpd_start
;
12250 /* now vpd_data holds full vpd content in both cases */
12252 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
12253 PCI_VPD_RO_KEYWORD_MFR_ID
);
12255 goto out_not_found
;
12257 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
12259 if (len
!= VENDOR_ID_LEN
)
12260 goto out_not_found
;
12262 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12264 /* vendor specific info */
12265 snprintf(str_id_reg
, VENDOR_ID_LEN
+ 1, "%04x", PCI_VENDOR_ID_DELL
);
12266 snprintf(str_id_cap
, VENDOR_ID_LEN
+ 1, "%04X", PCI_VENDOR_ID_DELL
);
12267 if (!strncmp(str_id_reg
, &vpd_data
[rodi
], VENDOR_ID_LEN
) ||
12268 !strncmp(str_id_cap
, &vpd_data
[rodi
], VENDOR_ID_LEN
)) {
12270 rodi
= pci_vpd_find_info_keyword(vpd_data
, i
, block_end
,
12271 PCI_VPD_RO_KEYWORD_VENDOR0
);
12273 len
= pci_vpd_info_field_size(&vpd_data
[rodi
]);
12275 rodi
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12277 if (len
< 32 && (len
+ rodi
) <= BNX2X_VPD_LEN
) {
12278 memcpy(bp
->fw_ver
, &vpd_data
[rodi
], len
);
12279 bp
->fw_ver
[len
] = ' ';
12282 kfree(vpd_extended_data
);
12286 kfree(vpd_extended_data
);
12290 static void bnx2x_set_modes_bitmap(struct bnx2x
*bp
)
12294 if (CHIP_REV_IS_FPGA(bp
))
12295 SET_FLAGS(flags
, MODE_FPGA
);
12296 else if (CHIP_REV_IS_EMUL(bp
))
12297 SET_FLAGS(flags
, MODE_EMUL
);
12299 SET_FLAGS(flags
, MODE_ASIC
);
12301 if (CHIP_MODE_IS_4_PORT(bp
))
12302 SET_FLAGS(flags
, MODE_PORT4
);
12304 SET_FLAGS(flags
, MODE_PORT2
);
12306 if (CHIP_IS_E2(bp
))
12307 SET_FLAGS(flags
, MODE_E2
);
12308 else if (CHIP_IS_E3(bp
)) {
12309 SET_FLAGS(flags
, MODE_E3
);
12310 if (CHIP_REV(bp
) == CHIP_REV_Ax
)
12311 SET_FLAGS(flags
, MODE_E3_A0
);
12312 else /*if (CHIP_REV(bp) == CHIP_REV_Bx)*/
12313 SET_FLAGS(flags
, MODE_E3_B0
| MODE_COS3
);
12317 SET_FLAGS(flags
, MODE_MF
);
12318 switch (bp
->mf_mode
) {
12319 case MULTI_FUNCTION_SD
:
12320 SET_FLAGS(flags
, MODE_MF_SD
);
12322 case MULTI_FUNCTION_SI
:
12323 SET_FLAGS(flags
, MODE_MF_SI
);
12325 case MULTI_FUNCTION_AFEX
:
12326 SET_FLAGS(flags
, MODE_MF_AFEX
);
12330 SET_FLAGS(flags
, MODE_SF
);
12332 #if defined(__LITTLE_ENDIAN)
12333 SET_FLAGS(flags
, MODE_LITTLE_ENDIAN
);
12334 #else /*(__BIG_ENDIAN)*/
12335 SET_FLAGS(flags
, MODE_BIG_ENDIAN
);
12337 INIT_MODE_FLAGS(bp
) = flags
;
12340 static int bnx2x_init_bp(struct bnx2x
*bp
)
12345 mutex_init(&bp
->port
.phy_mutex
);
12346 mutex_init(&bp
->fw_mb_mutex
);
12347 mutex_init(&bp
->drv_info_mutex
);
12348 sema_init(&bp
->stats_lock
, 1);
12349 bp
->drv_info_mng_owner
= false;
12350 INIT_LIST_HEAD(&bp
->vlan_reg
);
12352 INIT_DELAYED_WORK(&bp
->sp_task
, bnx2x_sp_task
);
12353 INIT_DELAYED_WORK(&bp
->sp_rtnl_task
, bnx2x_sp_rtnl_task
);
12354 INIT_DELAYED_WORK(&bp
->period_task
, bnx2x_period_task
);
12355 INIT_DELAYED_WORK(&bp
->iov_task
, bnx2x_iov_task
);
12357 rc
= bnx2x_get_hwinfo(bp
);
12361 eth_zero_addr(bp
->dev
->dev_addr
);
12364 bnx2x_set_modes_bitmap(bp
);
12366 rc
= bnx2x_alloc_mem_bp(bp
);
12370 bnx2x_read_fwinfo(bp
);
12372 func
= BP_FUNC(bp
);
12374 /* need to reset chip if undi was active */
12375 if (IS_PF(bp
) && !BP_NOMCP(bp
)) {
12378 SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
12379 DRV_MSG_SEQ_NUMBER_MASK
;
12380 BNX2X_DEV_INFO("fw_seq 0x%08x\n", bp
->fw_seq
);
12382 rc
= bnx2x_prev_unload(bp
);
12384 bnx2x_free_mem_bp(bp
);
12389 if (CHIP_REV_IS_FPGA(bp
))
12390 dev_err(&bp
->pdev
->dev
, "FPGA detected\n");
12392 if (BP_NOMCP(bp
) && (func
== 0))
12393 dev_err(&bp
->pdev
->dev
, "MCP disabled, must load devices in order!\n");
12395 bp
->disable_tpa
= disable_tpa
;
12396 bp
->disable_tpa
|= !!IS_MF_STORAGE_ONLY(bp
);
12397 /* Reduce memory usage in kdump environment by disabling TPA */
12398 bp
->disable_tpa
|= is_kdump_kernel();
12400 /* Set TPA flags */
12401 if (bp
->disable_tpa
) {
12402 bp
->dev
->hw_features
&= ~NETIF_F_LRO
;
12403 bp
->dev
->features
&= ~NETIF_F_LRO
;
12406 if (CHIP_IS_E1(bp
))
12407 bp
->dropless_fc
= 0;
12409 bp
->dropless_fc
= dropless_fc
| bnx2x_get_dropless_info(bp
);
12413 bp
->tx_ring_size
= IS_MF_STORAGE_ONLY(bp
) ? 0 : MAX_TX_AVAIL
;
12415 bp
->rx_ring_size
= MAX_RX_AVAIL
;
12417 /* make sure that the numbers are in the right granularity */
12418 bp
->tx_ticks
= (50 / BNX2X_BTR
) * BNX2X_BTR
;
12419 bp
->rx_ticks
= (25 / BNX2X_BTR
) * BNX2X_BTR
;
12421 bp
->current_interval
= CHIP_REV_IS_SLOW(bp
) ? 5*HZ
: HZ
;
12423 init_timer(&bp
->timer
);
12424 bp
->timer
.expires
= jiffies
+ bp
->current_interval
;
12425 bp
->timer
.data
= (unsigned long) bp
;
12426 bp
->timer
.function
= bnx2x_timer
;
12428 if (SHMEM2_HAS(bp
, dcbx_lldp_params_offset
) &&
12429 SHMEM2_HAS(bp
, dcbx_lldp_dcbx_stat_offset
) &&
12430 SHMEM2_HAS(bp
, dcbx_en
) &&
12431 SHMEM2_RD(bp
, dcbx_lldp_params_offset
) &&
12432 SHMEM2_RD(bp
, dcbx_lldp_dcbx_stat_offset
) &&
12433 SHMEM2_RD(bp
, dcbx_en
[BP_PORT(bp
)])) {
12434 bnx2x_dcbx_set_state(bp
, true, BNX2X_DCBX_ENABLED_ON_NEG_ON
);
12435 bnx2x_dcbx_init_params(bp
);
12437 bnx2x_dcbx_set_state(bp
, false, BNX2X_DCBX_ENABLED_OFF
);
12440 if (CHIP_IS_E1x(bp
))
12441 bp
->cnic_base_cl_id
= FP_SB_MAX_E1x
;
12443 bp
->cnic_base_cl_id
= FP_SB_MAX_E2
;
12445 /* multiple tx priority */
12448 else if (CHIP_IS_E1x(bp
))
12449 bp
->max_cos
= BNX2X_MULTI_TX_COS_E1X
;
12450 else if (CHIP_IS_E2(bp
) || CHIP_IS_E3A0(bp
))
12451 bp
->max_cos
= BNX2X_MULTI_TX_COS_E2_E3A0
;
12452 else if (CHIP_IS_E3B0(bp
))
12453 bp
->max_cos
= BNX2X_MULTI_TX_COS_E3B0
;
12455 BNX2X_ERR("unknown chip %x revision %x\n",
12456 CHIP_NUM(bp
), CHIP_REV(bp
));
12457 BNX2X_DEV_INFO("set bp->max_cos to %d\n", bp
->max_cos
);
12459 /* We need at least one default status block for slow-path events,
12460 * second status block for the L2 queue, and a third status block for
12461 * CNIC if supported.
12464 bp
->min_msix_vec_cnt
= 1;
12465 else if (CNIC_SUPPORT(bp
))
12466 bp
->min_msix_vec_cnt
= 3;
12467 else /* PF w/o cnic */
12468 bp
->min_msix_vec_cnt
= 2;
12469 BNX2X_DEV_INFO("bp->min_msix_vec_cnt %d", bp
->min_msix_vec_cnt
);
12471 bp
->dump_preset_idx
= 1;
12473 if (CHIP_IS_E3B0(bp
))
12474 bp
->flags
|= PTP_SUPPORTED
;
12479 /****************************************************************************
12480 * General service functions
12481 ****************************************************************************/
12484 * net_device service functions
12487 /* called with rtnl_lock */
12488 static int bnx2x_open(struct net_device
*dev
)
12490 struct bnx2x
*bp
= netdev_priv(dev
);
12493 bp
->stats_init
= true;
12495 netif_carrier_off(dev
);
12497 bnx2x_set_power_state(bp
, PCI_D0
);
12499 /* If parity had happen during the unload, then attentions
12500 * and/or RECOVERY_IN_PROGRES may still be set. In this case we
12501 * want the first function loaded on the current engine to
12502 * complete the recovery.
12503 * Parity recovery is only relevant for PF driver.
12506 int other_engine
= BP_PATH(bp
) ? 0 : 1;
12507 bool other_load_status
, load_status
;
12508 bool global
= false;
12510 other_load_status
= bnx2x_get_load_status(bp
, other_engine
);
12511 load_status
= bnx2x_get_load_status(bp
, BP_PATH(bp
));
12512 if (!bnx2x_reset_is_done(bp
, BP_PATH(bp
)) ||
12513 bnx2x_chk_parity_attn(bp
, &global
, true)) {
12515 /* If there are attentions and they are in a
12516 * global blocks, set the GLOBAL_RESET bit
12517 * regardless whether it will be this function
12518 * that will complete the recovery or not.
12521 bnx2x_set_reset_global(bp
);
12523 /* Only the first function on the current
12524 * engine should try to recover in open. In case
12525 * of attentions in global blocks only the first
12526 * in the chip should try to recover.
12528 if ((!load_status
&&
12529 (!global
|| !other_load_status
)) &&
12530 bnx2x_trylock_leader_lock(bp
) &&
12531 !bnx2x_leader_reset(bp
)) {
12532 netdev_info(bp
->dev
,
12533 "Recovered in open\n");
12537 /* recovery has failed... */
12538 bnx2x_set_power_state(bp
, PCI_D3hot
);
12539 bp
->recovery_state
= BNX2X_RECOVERY_FAILED
;
12541 BNX2X_ERR("Recovery flow hasn't been properly completed yet. Try again later.\n"
12542 "If you still see this message after a few retries then power cycle is required.\n");
12549 bp
->recovery_state
= BNX2X_RECOVERY_DONE
;
12550 rc
= bnx2x_nic_load(bp
, LOAD_OPEN
);
12554 #ifdef CONFIG_BNX2X_VXLAN
12556 vxlan_get_rx_port(dev
);
12558 #if IS_ENABLED(CONFIG_BNX2X_GENEVE)
12560 geneve_get_rx_port(dev
);
12566 /* called with rtnl_lock */
12567 static int bnx2x_close(struct net_device
*dev
)
12569 struct bnx2x
*bp
= netdev_priv(dev
);
12571 /* Unload the driver, release IRQs */
12572 bnx2x_nic_unload(bp
, UNLOAD_CLOSE
, false);
12577 static int bnx2x_init_mcast_macs_list(struct bnx2x
*bp
,
12578 struct bnx2x_mcast_ramrod_params
*p
)
12580 int mc_count
= netdev_mc_count(bp
->dev
);
12581 struct bnx2x_mcast_list_elem
*mc_mac
=
12582 kcalloc(mc_count
, sizeof(*mc_mac
), GFP_ATOMIC
);
12583 struct netdev_hw_addr
*ha
;
12588 INIT_LIST_HEAD(&p
->mcast_list
);
12590 netdev_for_each_mc_addr(ha
, bp
->dev
) {
12591 mc_mac
->mac
= bnx2x_mc_addr(ha
);
12592 list_add_tail(&mc_mac
->link
, &p
->mcast_list
);
12596 p
->mcast_list_len
= mc_count
;
12601 static void bnx2x_free_mcast_macs_list(
12602 struct bnx2x_mcast_ramrod_params
*p
)
12604 struct bnx2x_mcast_list_elem
*mc_mac
=
12605 list_first_entry(&p
->mcast_list
, struct bnx2x_mcast_list_elem
,
12613 * bnx2x_set_uc_list - configure a new unicast MACs list.
12615 * @bp: driver handle
12617 * We will use zero (0) as a MAC type for these MACs.
12619 static int bnx2x_set_uc_list(struct bnx2x
*bp
)
12622 struct net_device
*dev
= bp
->dev
;
12623 struct netdev_hw_addr
*ha
;
12624 struct bnx2x_vlan_mac_obj
*mac_obj
= &bp
->sp_objs
->mac_obj
;
12625 unsigned long ramrod_flags
= 0;
12627 /* First schedule a cleanup up of old configuration */
12628 rc
= bnx2x_del_all_macs(bp
, mac_obj
, BNX2X_UC_LIST_MAC
, false);
12630 BNX2X_ERR("Failed to schedule DELETE operations: %d\n", rc
);
12634 netdev_for_each_uc_addr(ha
, dev
) {
12635 rc
= bnx2x_set_mac_one(bp
, bnx2x_uc_addr(ha
), mac_obj
, true,
12636 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
12637 if (rc
== -EEXIST
) {
12639 "Failed to schedule ADD operations: %d\n", rc
);
12640 /* do not treat adding same MAC as error */
12643 } else if (rc
< 0) {
12645 BNX2X_ERR("Failed to schedule ADD operations: %d\n",
12651 /* Execute the pending commands */
12652 __set_bit(RAMROD_CONT
, &ramrod_flags
);
12653 return bnx2x_set_mac_one(bp
, NULL
, mac_obj
, false /* don't care */,
12654 BNX2X_UC_LIST_MAC
, &ramrod_flags
);
12657 static int bnx2x_set_mc_list(struct bnx2x
*bp
)
12659 struct net_device
*dev
= bp
->dev
;
12660 struct bnx2x_mcast_ramrod_params rparam
= {NULL
};
12663 rparam
.mcast_obj
= &bp
->mcast_obj
;
12665 /* first, clear all configured multicast MACs */
12666 rc
= bnx2x_config_mcast(bp
, &rparam
, BNX2X_MCAST_CMD_DEL
);
12668 BNX2X_ERR("Failed to clear multicast configuration: %d\n", rc
);
12672 /* then, configure a new MACs list */
12673 if (netdev_mc_count(dev
)) {
12674 rc
= bnx2x_init_mcast_macs_list(bp
, &rparam
);
12676 BNX2X_ERR("Failed to create multicast MACs list: %d\n",
12681 /* Now add the new MACs */
12682 rc
= bnx2x_config_mcast(bp
, &rparam
,
12683 BNX2X_MCAST_CMD_ADD
);
12685 BNX2X_ERR("Failed to set a new multicast configuration: %d\n",
12688 bnx2x_free_mcast_macs_list(&rparam
);
12694 /* If bp->state is OPEN, should be called with netif_addr_lock_bh() */
12695 static void bnx2x_set_rx_mode(struct net_device
*dev
)
12697 struct bnx2x
*bp
= netdev_priv(dev
);
12699 if (bp
->state
!= BNX2X_STATE_OPEN
) {
12700 DP(NETIF_MSG_IFUP
, "state is %x, returning\n", bp
->state
);
12703 /* Schedule an SP task to handle rest of change */
12704 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_RX_MODE
,
12709 void bnx2x_set_rx_mode_inner(struct bnx2x
*bp
)
12711 u32 rx_mode
= BNX2X_RX_MODE_NORMAL
;
12713 DP(NETIF_MSG_IFUP
, "dev->flags = %x\n", bp
->dev
->flags
);
12715 netif_addr_lock_bh(bp
->dev
);
12717 if (bp
->dev
->flags
& IFF_PROMISC
) {
12718 rx_mode
= BNX2X_RX_MODE_PROMISC
;
12719 } else if ((bp
->dev
->flags
& IFF_ALLMULTI
) ||
12720 ((netdev_mc_count(bp
->dev
) > BNX2X_MAX_MULTICAST
) &&
12722 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
12725 /* some multicasts */
12726 if (bnx2x_set_mc_list(bp
) < 0)
12727 rx_mode
= BNX2X_RX_MODE_ALLMULTI
;
12729 /* release bh lock, as bnx2x_set_uc_list might sleep */
12730 netif_addr_unlock_bh(bp
->dev
);
12731 if (bnx2x_set_uc_list(bp
) < 0)
12732 rx_mode
= BNX2X_RX_MODE_PROMISC
;
12733 netif_addr_lock_bh(bp
->dev
);
12735 /* configuring mcast to a vf involves sleeping (when we
12736 * wait for the pf's response).
12738 bnx2x_schedule_sp_rtnl(bp
,
12739 BNX2X_SP_RTNL_VFPF_MCAST
, 0);
12743 bp
->rx_mode
= rx_mode
;
12744 /* handle ISCSI SD mode */
12745 if (IS_MF_ISCSI_ONLY(bp
))
12746 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
12748 /* Schedule the rx_mode command */
12749 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
)) {
12750 set_bit(BNX2X_FILTER_RX_MODE_SCHED
, &bp
->sp_state
);
12751 netif_addr_unlock_bh(bp
->dev
);
12756 bnx2x_set_storm_rx_mode(bp
);
12757 netif_addr_unlock_bh(bp
->dev
);
12759 /* VF will need to request the PF to make this change, and so
12760 * the VF needs to release the bottom-half lock prior to the
12761 * request (as it will likely require sleep on the VF side)
12763 netif_addr_unlock_bh(bp
->dev
);
12764 bnx2x_vfpf_storm_rx_mode(bp
);
12768 /* called with rtnl_lock */
12769 static int bnx2x_mdio_read(struct net_device
*netdev
, int prtad
,
12770 int devad
, u16 addr
)
12772 struct bnx2x
*bp
= netdev_priv(netdev
);
12776 DP(NETIF_MSG_LINK
, "mdio_read: prtad 0x%x, devad 0x%x, addr 0x%x\n",
12777 prtad
, devad
, addr
);
12779 /* The HW expects different devad if CL22 is used */
12780 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
12782 bnx2x_acquire_phy_lock(bp
);
12783 rc
= bnx2x_phy_read(&bp
->link_params
, prtad
, devad
, addr
, &value
);
12784 bnx2x_release_phy_lock(bp
);
12785 DP(NETIF_MSG_LINK
, "mdio_read_val 0x%x rc = 0x%x\n", value
, rc
);
12792 /* called with rtnl_lock */
12793 static int bnx2x_mdio_write(struct net_device
*netdev
, int prtad
, int devad
,
12794 u16 addr
, u16 value
)
12796 struct bnx2x
*bp
= netdev_priv(netdev
);
12800 "mdio_write: prtad 0x%x, devad 0x%x, addr 0x%x, value 0x%x\n",
12801 prtad
, devad
, addr
, value
);
12803 /* The HW expects different devad if CL22 is used */
12804 devad
= (devad
== MDIO_DEVAD_NONE
) ? DEFAULT_PHY_DEV_ADDR
: devad
;
12806 bnx2x_acquire_phy_lock(bp
);
12807 rc
= bnx2x_phy_write(&bp
->link_params
, prtad
, devad
, addr
, value
);
12808 bnx2x_release_phy_lock(bp
);
12812 /* called with rtnl_lock */
12813 static int bnx2x_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
12815 struct bnx2x
*bp
= netdev_priv(dev
);
12816 struct mii_ioctl_data
*mdio
= if_mii(ifr
);
12818 if (!netif_running(dev
))
12822 case SIOCSHWTSTAMP
:
12823 return bnx2x_hwtstamp_ioctl(bp
, ifr
);
12825 DP(NETIF_MSG_LINK
, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
12826 mdio
->phy_id
, mdio
->reg_num
, mdio
->val_in
);
12827 return mdio_mii_ioctl(&bp
->mdio
, mdio
, cmd
);
12831 #ifdef CONFIG_NET_POLL_CONTROLLER
12832 static void poll_bnx2x(struct net_device
*dev
)
12834 struct bnx2x
*bp
= netdev_priv(dev
);
12837 for_each_eth_queue(bp
, i
) {
12838 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
12839 napi_schedule(&bnx2x_fp(bp
, fp
->index
, napi
));
12844 static int bnx2x_validate_addr(struct net_device
*dev
)
12846 struct bnx2x
*bp
= netdev_priv(dev
);
12848 /* query the bulletin board for mac address configured by the PF */
12850 bnx2x_sample_bulletin(bp
);
12852 if (!is_valid_ether_addr(dev
->dev_addr
)) {
12853 BNX2X_ERR("Non-valid Ethernet address\n");
12854 return -EADDRNOTAVAIL
;
12859 static int bnx2x_get_phys_port_id(struct net_device
*netdev
,
12860 struct netdev_phys_item_id
*ppid
)
12862 struct bnx2x
*bp
= netdev_priv(netdev
);
12864 if (!(bp
->flags
& HAS_PHYS_PORT_ID
))
12865 return -EOPNOTSUPP
;
12867 ppid
->id_len
= sizeof(bp
->phys_port_id
);
12868 memcpy(ppid
->id
, bp
->phys_port_id
, ppid
->id_len
);
12873 static netdev_features_t
bnx2x_features_check(struct sk_buff
*skb
,
12874 struct net_device
*dev
,
12875 netdev_features_t features
)
12877 features
= vlan_features_check(skb
, features
);
12878 return vxlan_features_check(skb
, features
);
12881 static int __bnx2x_vlan_configure_vid(struct bnx2x
*bp
, u16 vid
, bool add
)
12886 unsigned long ramrod_flags
= 0;
12888 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
12889 rc
= bnx2x_set_vlan_one(bp
, vid
, &bp
->sp_objs
->vlan_obj
,
12890 add
, &ramrod_flags
);
12892 rc
= bnx2x_vfpf_update_vlan(bp
, vid
, bp
->fp
->index
, add
);
12898 static int bnx2x_vlan_configure_vid_list(struct bnx2x
*bp
)
12900 struct bnx2x_vlan_entry
*vlan
;
12903 /* Configure all non-configured entries */
12904 list_for_each_entry(vlan
, &bp
->vlan_reg
, link
) {
12908 if (bp
->vlan_cnt
>= bp
->vlan_credit
)
12911 rc
= __bnx2x_vlan_configure_vid(bp
, vlan
->vid
, true);
12913 BNX2X_ERR("Unable to config VLAN %d\n", vlan
->vid
);
12917 DP(NETIF_MSG_IFUP
, "HW configured for VLAN %d\n", vlan
->vid
);
12925 static void bnx2x_vlan_configure(struct bnx2x
*bp
, bool set_rx_mode
)
12927 bool need_accept_any_vlan
;
12929 need_accept_any_vlan
= !!bnx2x_vlan_configure_vid_list(bp
);
12931 if (bp
->accept_any_vlan
!= need_accept_any_vlan
) {
12932 bp
->accept_any_vlan
= need_accept_any_vlan
;
12933 DP(NETIF_MSG_IFUP
, "Accept all VLAN %s\n",
12934 bp
->accept_any_vlan
? "raised" : "cleared");
12937 bnx2x_set_rx_mode_inner(bp
);
12939 bnx2x_vfpf_storm_rx_mode(bp
);
12944 int bnx2x_vlan_reconfigure_vid(struct bnx2x
*bp
)
12946 struct bnx2x_vlan_entry
*vlan
;
12948 /* The hw forgot all entries after reload */
12949 list_for_each_entry(vlan
, &bp
->vlan_reg
, link
)
12953 /* Don't set rx mode here. Our caller will do it. */
12954 bnx2x_vlan_configure(bp
, false);
12959 static int bnx2x_vlan_rx_add_vid(struct net_device
*dev
, __be16 proto
, u16 vid
)
12961 struct bnx2x
*bp
= netdev_priv(dev
);
12962 struct bnx2x_vlan_entry
*vlan
;
12964 DP(NETIF_MSG_IFUP
, "Adding VLAN %d\n", vid
);
12966 vlan
= kmalloc(sizeof(*vlan
), GFP_KERNEL
);
12972 list_add_tail(&vlan
->link
, &bp
->vlan_reg
);
12974 if (netif_running(dev
))
12975 bnx2x_vlan_configure(bp
, true);
12980 static int bnx2x_vlan_rx_kill_vid(struct net_device
*dev
, __be16 proto
, u16 vid
)
12982 struct bnx2x
*bp
= netdev_priv(dev
);
12983 struct bnx2x_vlan_entry
*vlan
;
12984 bool found
= false;
12987 DP(NETIF_MSG_IFUP
, "Removing VLAN %d\n", vid
);
12989 list_for_each_entry(vlan
, &bp
->vlan_reg
, link
)
12990 if (vlan
->vid
== vid
) {
12996 BNX2X_ERR("Unable to kill VLAN %d - not found\n", vid
);
13000 if (netif_running(dev
) && vlan
->hw
) {
13001 rc
= __bnx2x_vlan_configure_vid(bp
, vid
, false);
13002 DP(NETIF_MSG_IFUP
, "HW deconfigured for VLAN %d\n", vid
);
13006 list_del(&vlan
->link
);
13009 if (netif_running(dev
))
13010 bnx2x_vlan_configure(bp
, true);
13012 DP(NETIF_MSG_IFUP
, "Removing VLAN result %d\n", rc
);
13017 static const struct net_device_ops bnx2x_netdev_ops
= {
13018 .ndo_open
= bnx2x_open
,
13019 .ndo_stop
= bnx2x_close
,
13020 .ndo_start_xmit
= bnx2x_start_xmit
,
13021 .ndo_select_queue
= bnx2x_select_queue
,
13022 .ndo_set_rx_mode
= bnx2x_set_rx_mode
,
13023 .ndo_set_mac_address
= bnx2x_change_mac_addr
,
13024 .ndo_validate_addr
= bnx2x_validate_addr
,
13025 .ndo_do_ioctl
= bnx2x_ioctl
,
13026 .ndo_change_mtu
= bnx2x_change_mtu
,
13027 .ndo_fix_features
= bnx2x_fix_features
,
13028 .ndo_set_features
= bnx2x_set_features
,
13029 .ndo_tx_timeout
= bnx2x_tx_timeout
,
13030 .ndo_vlan_rx_add_vid
= bnx2x_vlan_rx_add_vid
,
13031 .ndo_vlan_rx_kill_vid
= bnx2x_vlan_rx_kill_vid
,
13032 #ifdef CONFIG_NET_POLL_CONTROLLER
13033 .ndo_poll_controller
= poll_bnx2x
,
13035 .ndo_setup_tc
= __bnx2x_setup_tc
,
13036 #ifdef CONFIG_BNX2X_SRIOV
13037 .ndo_set_vf_mac
= bnx2x_set_vf_mac
,
13038 .ndo_set_vf_vlan
= bnx2x_set_vf_vlan
,
13039 .ndo_get_vf_config
= bnx2x_get_vf_config
,
13041 #ifdef NETDEV_FCOE_WWNN
13042 .ndo_fcoe_get_wwn
= bnx2x_fcoe_get_wwn
,
13045 .ndo_get_phys_port_id
= bnx2x_get_phys_port_id
,
13046 .ndo_set_vf_link_state
= bnx2x_set_vf_link_state
,
13047 .ndo_features_check
= bnx2x_features_check
,
13048 #ifdef CONFIG_BNX2X_VXLAN
13049 .ndo_add_vxlan_port
= bnx2x_add_vxlan_port
,
13050 .ndo_del_vxlan_port
= bnx2x_del_vxlan_port
,
13052 #if IS_ENABLED(CONFIG_BNX2X_GENEVE)
13053 .ndo_add_geneve_port
= bnx2x_add_geneve_port
,
13054 .ndo_del_geneve_port
= bnx2x_del_geneve_port
,
13058 static int bnx2x_set_coherency_mask(struct bnx2x
*bp
)
13060 struct device
*dev
= &bp
->pdev
->dev
;
13062 if (dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(64)) != 0 &&
13063 dma_set_mask_and_coherent(dev
, DMA_BIT_MASK(32)) != 0) {
13064 dev_err(dev
, "System does not support DMA, aborting\n");
13071 static void bnx2x_disable_pcie_error_reporting(struct bnx2x
*bp
)
13073 if (bp
->flags
& AER_ENABLED
) {
13074 pci_disable_pcie_error_reporting(bp
->pdev
);
13075 bp
->flags
&= ~AER_ENABLED
;
13079 static int bnx2x_init_dev(struct bnx2x
*bp
, struct pci_dev
*pdev
,
13080 struct net_device
*dev
, unsigned long board_type
)
13084 bool chip_is_e1x
= (board_type
== BCM57710
||
13085 board_type
== BCM57711
||
13086 board_type
== BCM57711E
);
13088 SET_NETDEV_DEV(dev
, &pdev
->dev
);
13093 rc
= pci_enable_device(pdev
);
13095 dev_err(&bp
->pdev
->dev
,
13096 "Cannot enable PCI device, aborting\n");
13100 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
13101 dev_err(&bp
->pdev
->dev
,
13102 "Cannot find PCI device base address, aborting\n");
13104 goto err_out_disable
;
13107 if (IS_PF(bp
) && !(pci_resource_flags(pdev
, 2) & IORESOURCE_MEM
)) {
13108 dev_err(&bp
->pdev
->dev
, "Cannot find second PCI device base address, aborting\n");
13110 goto err_out_disable
;
13113 pci_read_config_dword(pdev
, PCICFG_REVISION_ID_OFFSET
, &pci_cfg_dword
);
13114 if ((pci_cfg_dword
& PCICFG_REVESION_ID_MASK
) ==
13115 PCICFG_REVESION_ID_ERROR_VAL
) {
13116 pr_err("PCI device error, probably due to fan failure, aborting\n");
13118 goto err_out_disable
;
13121 if (atomic_read(&pdev
->enable_cnt
) == 1) {
13122 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
13124 dev_err(&bp
->pdev
->dev
,
13125 "Cannot obtain PCI resources, aborting\n");
13126 goto err_out_disable
;
13129 pci_set_master(pdev
);
13130 pci_save_state(pdev
);
13134 if (!pdev
->pm_cap
) {
13135 dev_err(&bp
->pdev
->dev
,
13136 "Cannot find power management capability, aborting\n");
13138 goto err_out_release
;
13142 if (!pci_is_pcie(pdev
)) {
13143 dev_err(&bp
->pdev
->dev
, "Not PCI Express, aborting\n");
13145 goto err_out_release
;
13148 rc
= bnx2x_set_coherency_mask(bp
);
13150 goto err_out_release
;
13152 dev
->mem_start
= pci_resource_start(pdev
, 0);
13153 dev
->base_addr
= dev
->mem_start
;
13154 dev
->mem_end
= pci_resource_end(pdev
, 0);
13156 dev
->irq
= pdev
->irq
;
13158 bp
->regview
= pci_ioremap_bar(pdev
, 0);
13159 if (!bp
->regview
) {
13160 dev_err(&bp
->pdev
->dev
,
13161 "Cannot map register space, aborting\n");
13163 goto err_out_release
;
13166 /* In E1/E1H use pci device function given by kernel.
13167 * In E2/E3 read physical function from ME register since these chips
13168 * support Physical Device Assignment where kernel BDF maybe arbitrary
13169 * (depending on hypervisor).
13172 bp
->pf_num
= PCI_FUNC(pdev
->devfn
);
13175 pci_read_config_dword(bp
->pdev
,
13176 PCICFG_ME_REGISTER
, &pci_cfg_dword
);
13177 bp
->pf_num
= (u8
)((pci_cfg_dword
& ME_REG_ABS_PF_NUM
) >>
13178 ME_REG_ABS_PF_NUM_SHIFT
);
13180 BNX2X_DEV_INFO("me reg PF num: %d\n", bp
->pf_num
);
13182 /* clean indirect addresses */
13183 pci_write_config_dword(bp
->pdev
, PCICFG_GRC_ADDRESS
,
13184 PCICFG_VENDOR_ID_OFFSET
);
13186 /* Set PCIe reset type to fundamental for EEH recovery */
13187 pdev
->needs_freset
= 1;
13189 /* AER (Advanced Error reporting) configuration */
13190 rc
= pci_enable_pcie_error_reporting(pdev
);
13192 bp
->flags
|= AER_ENABLED
;
13194 BNX2X_DEV_INFO("Failed To configure PCIe AER [%d]\n", rc
);
13197 * Clean the following indirect addresses for all functions since it
13198 * is not used by the driver.
13201 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F0
, 0);
13202 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F0
, 0);
13203 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F0
, 0);
13204 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F0
, 0);
13207 REG_WR(bp
, PXP2_REG_PGL_ADDR_88_F1
, 0);
13208 REG_WR(bp
, PXP2_REG_PGL_ADDR_8C_F1
, 0);
13209 REG_WR(bp
, PXP2_REG_PGL_ADDR_90_F1
, 0);
13210 REG_WR(bp
, PXP2_REG_PGL_ADDR_94_F1
, 0);
13213 /* Enable internal target-read (in case we are probed after PF
13214 * FLR). Must be done prior to any BAR read access. Only for
13219 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ
, 1);
13222 dev
->watchdog_timeo
= TX_TIMEOUT
;
13224 dev
->netdev_ops
= &bnx2x_netdev_ops
;
13225 bnx2x_set_ethtool_ops(bp
, dev
);
13227 dev
->priv_flags
|= IFF_UNICAST_FLT
;
13229 dev
->hw_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
13230 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
13231 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
|
13232 NETIF_F_RXHASH
| NETIF_F_HW_VLAN_CTAG_TX
;
13233 if (!chip_is_e1x
) {
13234 dev
->hw_features
|= NETIF_F_GSO_GRE
| NETIF_F_GSO_UDP_TUNNEL
|
13235 NETIF_F_GSO_IPXIP4
;
13236 dev
->hw_enc_features
=
13237 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
13238 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
|
13239 NETIF_F_GSO_IPXIP4
|
13240 NETIF_F_GSO_GRE
| NETIF_F_GSO_UDP_TUNNEL
;
13243 dev
->vlan_features
= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
13244 NETIF_F_TSO
| NETIF_F_TSO_ECN
| NETIF_F_TSO6
| NETIF_F_HIGHDMA
;
13246 /* VF with OLD Hypervisor or old PF do not support filtering */
13249 bp
->accept_any_vlan
= true;
13251 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
13252 #ifdef CONFIG_BNX2X_SRIOV
13253 } else if (bp
->acquire_resp
.pfdev_info
.pf_cap
& PFVF_CAP_VLAN_FILTER
) {
13254 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_FILTER
;
13258 dev
->features
|= dev
->hw_features
| NETIF_F_HW_VLAN_CTAG_RX
;
13259 dev
->features
|= NETIF_F_HIGHDMA
;
13261 /* Add Loopback capability to the device */
13262 dev
->hw_features
|= NETIF_F_LOOPBACK
;
13265 dev
->dcbnl_ops
= &bnx2x_dcbnl_ops
;
13268 /* get_port_hwinfo() will set prtad and mmds properly */
13269 bp
->mdio
.prtad
= MDIO_PRTAD_NONE
;
13271 bp
->mdio
.mode_support
= MDIO_SUPPORTS_C45
| MDIO_EMULATE_C22
;
13272 bp
->mdio
.dev
= dev
;
13273 bp
->mdio
.mdio_read
= bnx2x_mdio_read
;
13274 bp
->mdio
.mdio_write
= bnx2x_mdio_write
;
13279 if (atomic_read(&pdev
->enable_cnt
) == 1)
13280 pci_release_regions(pdev
);
13283 pci_disable_device(pdev
);
13289 static int bnx2x_check_firmware(struct bnx2x
*bp
)
13291 const struct firmware
*firmware
= bp
->firmware
;
13292 struct bnx2x_fw_file_hdr
*fw_hdr
;
13293 struct bnx2x_fw_file_section
*sections
;
13294 u32 offset
, len
, num_ops
;
13295 __be16
*ops_offsets
;
13299 if (firmware
->size
< sizeof(struct bnx2x_fw_file_hdr
)) {
13300 BNX2X_ERR("Wrong FW size\n");
13304 fw_hdr
= (struct bnx2x_fw_file_hdr
*)firmware
->data
;
13305 sections
= (struct bnx2x_fw_file_section
*)fw_hdr
;
13307 /* Make sure none of the offsets and sizes make us read beyond
13308 * the end of the firmware data */
13309 for (i
= 0; i
< sizeof(*fw_hdr
) / sizeof(*sections
); i
++) {
13310 offset
= be32_to_cpu(sections
[i
].offset
);
13311 len
= be32_to_cpu(sections
[i
].len
);
13312 if (offset
+ len
> firmware
->size
) {
13313 BNX2X_ERR("Section %d length is out of bounds\n", i
);
13318 /* Likewise for the init_ops offsets */
13319 offset
= be32_to_cpu(fw_hdr
->init_ops_offsets
.offset
);
13320 ops_offsets
= (__force __be16
*)(firmware
->data
+ offset
);
13321 num_ops
= be32_to_cpu(fw_hdr
->init_ops
.len
) / sizeof(struct raw_op
);
13323 for (i
= 0; i
< be32_to_cpu(fw_hdr
->init_ops_offsets
.len
) / 2; i
++) {
13324 if (be16_to_cpu(ops_offsets
[i
]) > num_ops
) {
13325 BNX2X_ERR("Section offset %d is out of bounds\n", i
);
13330 /* Check FW version */
13331 offset
= be32_to_cpu(fw_hdr
->fw_version
.offset
);
13332 fw_ver
= firmware
->data
+ offset
;
13333 if ((fw_ver
[0] != BCM_5710_FW_MAJOR_VERSION
) ||
13334 (fw_ver
[1] != BCM_5710_FW_MINOR_VERSION
) ||
13335 (fw_ver
[2] != BCM_5710_FW_REVISION_VERSION
) ||
13336 (fw_ver
[3] != BCM_5710_FW_ENGINEERING_VERSION
)) {
13337 BNX2X_ERR("Bad FW version:%d.%d.%d.%d. Should be %d.%d.%d.%d\n",
13338 fw_ver
[0], fw_ver
[1], fw_ver
[2], fw_ver
[3],
13339 BCM_5710_FW_MAJOR_VERSION
,
13340 BCM_5710_FW_MINOR_VERSION
,
13341 BCM_5710_FW_REVISION_VERSION
,
13342 BCM_5710_FW_ENGINEERING_VERSION
);
13349 static void be32_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
13351 const __be32
*source
= (const __be32
*)_source
;
13352 u32
*target
= (u32
*)_target
;
13355 for (i
= 0; i
< n
/4; i
++)
13356 target
[i
] = be32_to_cpu(source
[i
]);
13360 Ops array is stored in the following format:
13361 {op(8bit), offset(24bit, big endian), data(32bit, big endian)}
13363 static void bnx2x_prep_ops(const u8
*_source
, u8
*_target
, u32 n
)
13365 const __be32
*source
= (const __be32
*)_source
;
13366 struct raw_op
*target
= (struct raw_op
*)_target
;
13369 for (i
= 0, j
= 0; i
< n
/8; i
++, j
+= 2) {
13370 tmp
= be32_to_cpu(source
[j
]);
13371 target
[i
].op
= (tmp
>> 24) & 0xff;
13372 target
[i
].offset
= tmp
& 0xffffff;
13373 target
[i
].raw_data
= be32_to_cpu(source
[j
+ 1]);
13377 /* IRO array is stored in the following format:
13378 * {base(24bit), m1(16bit), m2(16bit), m3(16bit), size(16bit) }
13380 static void bnx2x_prep_iro(const u8
*_source
, u8
*_target
, u32 n
)
13382 const __be32
*source
= (const __be32
*)_source
;
13383 struct iro
*target
= (struct iro
*)_target
;
13386 for (i
= 0, j
= 0; i
< n
/sizeof(struct iro
); i
++) {
13387 target
[i
].base
= be32_to_cpu(source
[j
]);
13389 tmp
= be32_to_cpu(source
[j
]);
13390 target
[i
].m1
= (tmp
>> 16) & 0xffff;
13391 target
[i
].m2
= tmp
& 0xffff;
13393 tmp
= be32_to_cpu(source
[j
]);
13394 target
[i
].m3
= (tmp
>> 16) & 0xffff;
13395 target
[i
].size
= tmp
& 0xffff;
13400 static void be16_to_cpu_n(const u8
*_source
, u8
*_target
, u32 n
)
13402 const __be16
*source
= (const __be16
*)_source
;
13403 u16
*target
= (u16
*)_target
;
13406 for (i
= 0; i
< n
/2; i
++)
13407 target
[i
] = be16_to_cpu(source
[i
]);
13410 #define BNX2X_ALLOC_AND_SET(arr, lbl, func) \
13412 u32 len = be32_to_cpu(fw_hdr->arr.len); \
13413 bp->arr = kmalloc(len, GFP_KERNEL); \
13416 func(bp->firmware->data + be32_to_cpu(fw_hdr->arr.offset), \
13417 (u8 *)bp->arr, len); \
13420 static int bnx2x_init_firmware(struct bnx2x
*bp
)
13422 const char *fw_file_name
;
13423 struct bnx2x_fw_file_hdr
*fw_hdr
;
13429 if (CHIP_IS_E1(bp
))
13430 fw_file_name
= FW_FILE_NAME_E1
;
13431 else if (CHIP_IS_E1H(bp
))
13432 fw_file_name
= FW_FILE_NAME_E1H
;
13433 else if (!CHIP_IS_E1x(bp
))
13434 fw_file_name
= FW_FILE_NAME_E2
;
13436 BNX2X_ERR("Unsupported chip revision\n");
13439 BNX2X_DEV_INFO("Loading %s\n", fw_file_name
);
13441 rc
= request_firmware(&bp
->firmware
, fw_file_name
, &bp
->pdev
->dev
);
13443 BNX2X_ERR("Can't load firmware file %s\n",
13445 goto request_firmware_exit
;
13448 rc
= bnx2x_check_firmware(bp
);
13450 BNX2X_ERR("Corrupt firmware file %s\n", fw_file_name
);
13451 goto request_firmware_exit
;
13454 fw_hdr
= (struct bnx2x_fw_file_hdr
*)bp
->firmware
->data
;
13456 /* Initialize the pointers to the init arrays */
13458 BNX2X_ALLOC_AND_SET(init_data
, request_firmware_exit
, be32_to_cpu_n
);
13461 BNX2X_ALLOC_AND_SET(init_ops
, init_ops_alloc_err
, bnx2x_prep_ops
);
13464 BNX2X_ALLOC_AND_SET(init_ops_offsets
, init_offsets_alloc_err
,
13467 /* STORMs firmware */
13468 INIT_TSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13469 be32_to_cpu(fw_hdr
->tsem_int_table_data
.offset
);
13470 INIT_TSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13471 be32_to_cpu(fw_hdr
->tsem_pram_data
.offset
);
13472 INIT_USEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13473 be32_to_cpu(fw_hdr
->usem_int_table_data
.offset
);
13474 INIT_USEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13475 be32_to_cpu(fw_hdr
->usem_pram_data
.offset
);
13476 INIT_XSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13477 be32_to_cpu(fw_hdr
->xsem_int_table_data
.offset
);
13478 INIT_XSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13479 be32_to_cpu(fw_hdr
->xsem_pram_data
.offset
);
13480 INIT_CSEM_INT_TABLE_DATA(bp
) = bp
->firmware
->data
+
13481 be32_to_cpu(fw_hdr
->csem_int_table_data
.offset
);
13482 INIT_CSEM_PRAM_DATA(bp
) = bp
->firmware
->data
+
13483 be32_to_cpu(fw_hdr
->csem_pram_data
.offset
);
13485 BNX2X_ALLOC_AND_SET(iro_arr
, iro_alloc_err
, bnx2x_prep_iro
);
13490 kfree(bp
->init_ops_offsets
);
13491 init_offsets_alloc_err
:
13492 kfree(bp
->init_ops
);
13493 init_ops_alloc_err
:
13494 kfree(bp
->init_data
);
13495 request_firmware_exit
:
13496 release_firmware(bp
->firmware
);
13497 bp
->firmware
= NULL
;
13502 static void bnx2x_release_firmware(struct bnx2x
*bp
)
13504 kfree(bp
->init_ops_offsets
);
13505 kfree(bp
->init_ops
);
13506 kfree(bp
->init_data
);
13507 release_firmware(bp
->firmware
);
13508 bp
->firmware
= NULL
;
13511 static struct bnx2x_func_sp_drv_ops bnx2x_func_sp_drv
= {
13512 .init_hw_cmn_chip
= bnx2x_init_hw_common_chip
,
13513 .init_hw_cmn
= bnx2x_init_hw_common
,
13514 .init_hw_port
= bnx2x_init_hw_port
,
13515 .init_hw_func
= bnx2x_init_hw_func
,
13517 .reset_hw_cmn
= bnx2x_reset_common
,
13518 .reset_hw_port
= bnx2x_reset_port
,
13519 .reset_hw_func
= bnx2x_reset_func
,
13521 .gunzip_init
= bnx2x_gunzip_init
,
13522 .gunzip_end
= bnx2x_gunzip_end
,
13524 .init_fw
= bnx2x_init_firmware
,
13525 .release_fw
= bnx2x_release_firmware
,
13528 void bnx2x__init_func_obj(struct bnx2x
*bp
)
13530 /* Prepare DMAE related driver resources */
13531 bnx2x_setup_dmae(bp
);
13533 bnx2x_init_func_obj(bp
, &bp
->func_obj
,
13534 bnx2x_sp(bp
, func_rdata
),
13535 bnx2x_sp_mapping(bp
, func_rdata
),
13536 bnx2x_sp(bp
, func_afex_rdata
),
13537 bnx2x_sp_mapping(bp
, func_afex_rdata
),
13538 &bnx2x_func_sp_drv
);
13541 /* must be called after sriov-enable */
13542 static int bnx2x_set_qm_cid_count(struct bnx2x
*bp
)
13544 int cid_count
= BNX2X_L2_MAX_CID(bp
);
13547 cid_count
+= BNX2X_VF_CIDS
;
13549 if (CNIC_SUPPORT(bp
))
13550 cid_count
+= CNIC_CID_MAX
;
13552 return roundup(cid_count
, QM_CID_ROUND
);
13556 * bnx2x_get_num_none_def_sbs - return the number of none default SBs
13561 static int bnx2x_get_num_non_def_sbs(struct pci_dev
*pdev
, int cnic_cnt
)
13567 * If MSI-X is not supported - return number of SBs needed to support
13568 * one fast path queue: one FP queue + SB for CNIC
13570 if (!pdev
->msix_cap
) {
13571 dev_info(&pdev
->dev
, "no msix capability found\n");
13572 return 1 + cnic_cnt
;
13574 dev_info(&pdev
->dev
, "msix capability found\n");
13577 * The value in the PCI configuration space is the index of the last
13578 * entry, namely one less than the actual size of the table, which is
13579 * exactly what we want to return from this function: number of all SBs
13580 * without the default SB.
13581 * For VFs there is no default SB, then we return (index+1).
13583 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &control
);
13585 index
= control
& PCI_MSIX_FLAGS_QSIZE
;
13590 static int set_max_cos_est(int chip_id
)
13596 return BNX2X_MULTI_TX_COS_E1X
;
13599 return BNX2X_MULTI_TX_COS_E2_E3A0
;
13604 case BCM57840_4_10
:
13605 case BCM57840_2_20
:
13611 return BNX2X_MULTI_TX_COS_E3B0
;
13619 pr_err("Unknown board_type (%d), aborting\n", chip_id
);
13624 static int set_is_vf(int chip_id
)
13638 /* nig_tsgen registers relative address */
13639 #define tsgen_ctrl 0x0
13640 #define tsgen_freecount 0x10
13641 #define tsgen_synctime_t0 0x20
13642 #define tsgen_offset_t0 0x28
13643 #define tsgen_drift_t0 0x30
13644 #define tsgen_synctime_t1 0x58
13645 #define tsgen_offset_t1 0x60
13646 #define tsgen_drift_t1 0x68
13648 /* FW workaround for setting drift */
13649 static int bnx2x_send_update_drift_ramrod(struct bnx2x
*bp
, int drift_dir
,
13650 int best_val
, int best_period
)
13652 struct bnx2x_func_state_params func_params
= {NULL
};
13653 struct bnx2x_func_set_timesync_params
*set_timesync_params
=
13654 &func_params
.params
.set_timesync
;
13656 /* Prepare parameters for function state transitions */
13657 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
13658 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
13660 func_params
.f_obj
= &bp
->func_obj
;
13661 func_params
.cmd
= BNX2X_F_CMD_SET_TIMESYNC
;
13663 /* Function parameters */
13664 set_timesync_params
->drift_adjust_cmd
= TS_DRIFT_ADJUST_SET
;
13665 set_timesync_params
->offset_cmd
= TS_OFFSET_KEEP
;
13666 set_timesync_params
->add_sub_drift_adjust_value
=
13667 drift_dir
? TS_ADD_VALUE
: TS_SUB_VALUE
;
13668 set_timesync_params
->drift_adjust_value
= best_val
;
13669 set_timesync_params
->drift_adjust_period
= best_period
;
13671 return bnx2x_func_state_change(bp
, &func_params
);
13674 static int bnx2x_ptp_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
13676 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13679 int val
, period
, period1
, period2
, dif
, dif1
, dif2
;
13680 int best_dif
= BNX2X_MAX_PHC_DRIFT
, best_period
= 0, best_val
= 0;
13682 DP(BNX2X_MSG_PTP
, "PTP adjfreq called, ppb = %d\n", ppb
);
13684 if (!netif_running(bp
->dev
)) {
13686 "PTP adjfreq called while the interface is down\n");
13697 best_period
= 0x1FFFFFF;
13698 } else if (ppb
>= BNX2X_MAX_PHC_DRIFT
) {
13702 /* Changed not to allow val = 8, 16, 24 as these values
13703 * are not supported in workaround.
13705 for (val
= 0; val
<= 31; val
++) {
13706 if ((val
& 0x7) == 0)
13708 period1
= val
* 1000000 / ppb
;
13709 period2
= period1
+ 1;
13711 dif1
= ppb
- (val
* 1000000 / period1
);
13713 dif1
= BNX2X_MAX_PHC_DRIFT
;
13716 dif2
= ppb
- (val
* 1000000 / period2
);
13719 dif
= (dif1
< dif2
) ? dif1
: dif2
;
13720 period
= (dif1
< dif2
) ? period1
: period2
;
13721 if (dif
< best_dif
) {
13724 best_period
= period
;
13729 rc
= bnx2x_send_update_drift_ramrod(bp
, drift_dir
, best_val
,
13732 BNX2X_ERR("Failed to set drift\n");
13736 DP(BNX2X_MSG_PTP
, "Configured val = %d, period = %d\n", best_val
,
13742 static int bnx2x_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
13744 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13746 DP(BNX2X_MSG_PTP
, "PTP adjtime called, delta = %llx\n", delta
);
13748 timecounter_adjtime(&bp
->timecounter
, delta
);
13753 static int bnx2x_ptp_gettime(struct ptp_clock_info
*ptp
, struct timespec64
*ts
)
13755 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13758 ns
= timecounter_read(&bp
->timecounter
);
13760 DP(BNX2X_MSG_PTP
, "PTP gettime called, ns = %llu\n", ns
);
13762 *ts
= ns_to_timespec64(ns
);
13767 static int bnx2x_ptp_settime(struct ptp_clock_info
*ptp
,
13768 const struct timespec64
*ts
)
13770 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13773 ns
= timespec64_to_ns(ts
);
13775 DP(BNX2X_MSG_PTP
, "PTP settime called, ns = %llu\n", ns
);
13777 /* Re-init the timecounter */
13778 timecounter_init(&bp
->timecounter
, &bp
->cyclecounter
, ns
);
13783 /* Enable (or disable) ancillary features of the phc subsystem */
13784 static int bnx2x_ptp_enable(struct ptp_clock_info
*ptp
,
13785 struct ptp_clock_request
*rq
, int on
)
13787 struct bnx2x
*bp
= container_of(ptp
, struct bnx2x
, ptp_clock_info
);
13789 BNX2X_ERR("PHC ancillary features are not supported\n");
13793 static void bnx2x_register_phc(struct bnx2x
*bp
)
13795 /* Fill the ptp_clock_info struct and register PTP clock*/
13796 bp
->ptp_clock_info
.owner
= THIS_MODULE
;
13797 snprintf(bp
->ptp_clock_info
.name
, 16, "%s", bp
->dev
->name
);
13798 bp
->ptp_clock_info
.max_adj
= BNX2X_MAX_PHC_DRIFT
; /* In PPB */
13799 bp
->ptp_clock_info
.n_alarm
= 0;
13800 bp
->ptp_clock_info
.n_ext_ts
= 0;
13801 bp
->ptp_clock_info
.n_per_out
= 0;
13802 bp
->ptp_clock_info
.pps
= 0;
13803 bp
->ptp_clock_info
.adjfreq
= bnx2x_ptp_adjfreq
;
13804 bp
->ptp_clock_info
.adjtime
= bnx2x_ptp_adjtime
;
13805 bp
->ptp_clock_info
.gettime64
= bnx2x_ptp_gettime
;
13806 bp
->ptp_clock_info
.settime64
= bnx2x_ptp_settime
;
13807 bp
->ptp_clock_info
.enable
= bnx2x_ptp_enable
;
13809 bp
->ptp_clock
= ptp_clock_register(&bp
->ptp_clock_info
, &bp
->pdev
->dev
);
13810 if (IS_ERR(bp
->ptp_clock
)) {
13811 bp
->ptp_clock
= NULL
;
13812 BNX2X_ERR("PTP clock registeration failed\n");
13816 static int bnx2x_init_one(struct pci_dev
*pdev
,
13817 const struct pci_device_id
*ent
)
13819 struct net_device
*dev
= NULL
;
13821 enum pcie_link_width pcie_width
;
13822 enum pci_bus_speed pcie_speed
;
13823 int rc
, max_non_def_sbs
;
13824 int rx_count
, tx_count
, rss_count
, doorbell_size
;
13829 /* Management FW 'remembers' living interfaces. Allow it some time
13830 * to forget previously living interfaces, allowing a proper re-load.
13832 if (is_kdump_kernel()) {
13833 ktime_t now
= ktime_get_boottime();
13834 ktime_t fw_ready_time
= ktime_set(5, 0);
13836 if (ktime_before(now
, fw_ready_time
))
13837 msleep(ktime_ms_delta(fw_ready_time
, now
));
13840 /* An estimated maximum supported CoS number according to the chip
13842 * We will try to roughly estimate the maximum number of CoSes this chip
13843 * may support in order to minimize the memory allocated for Tx
13844 * netdev_queue's. This number will be accurately calculated during the
13845 * initialization of bp->max_cos based on the chip versions AND chip
13846 * revision in the bnx2x_init_bp().
13848 max_cos_est
= set_max_cos_est(ent
->driver_data
);
13849 if (max_cos_est
< 0)
13850 return max_cos_est
;
13851 is_vf
= set_is_vf(ent
->driver_data
);
13852 cnic_cnt
= is_vf
? 0 : 1;
13854 max_non_def_sbs
= bnx2x_get_num_non_def_sbs(pdev
, cnic_cnt
);
13856 /* add another SB for VF as it has no default SB */
13857 max_non_def_sbs
+= is_vf
? 1 : 0;
13859 /* Maximum number of RSS queues: one IGU SB goes to CNIC */
13860 rss_count
= max_non_def_sbs
- cnic_cnt
;
13865 /* Maximum number of netdev Rx queues: RSS + FCoE L2 */
13866 rx_count
= rss_count
+ cnic_cnt
;
13868 /* Maximum number of netdev Tx queues:
13869 * Maximum TSS queues * Maximum supported number of CoS + FCoE L2
13871 tx_count
= rss_count
* max_cos_est
+ cnic_cnt
;
13873 /* dev zeroed in init_etherdev */
13874 dev
= alloc_etherdev_mqs(sizeof(*bp
), tx_count
, rx_count
);
13878 bp
= netdev_priv(dev
);
13882 bp
->flags
|= IS_VF_FLAG
;
13884 bp
->igu_sb_cnt
= max_non_def_sbs
;
13885 bp
->igu_base_addr
= IS_VF(bp
) ? PXP_VF_ADDR_IGU_START
: BAR_IGU_INTMEM
;
13886 bp
->msg_enable
= debug
;
13887 bp
->cnic_support
= cnic_cnt
;
13888 bp
->cnic_probe
= bnx2x_cnic_probe
;
13890 pci_set_drvdata(pdev
, dev
);
13892 rc
= bnx2x_init_dev(bp
, pdev
, dev
, ent
->driver_data
);
13898 BNX2X_DEV_INFO("This is a %s function\n",
13899 IS_PF(bp
) ? "physical" : "virtual");
13900 BNX2X_DEV_INFO("Cnic support is %s\n", CNIC_SUPPORT(bp
) ? "on" : "off");
13901 BNX2X_DEV_INFO("Max num of status blocks %d\n", max_non_def_sbs
);
13902 BNX2X_DEV_INFO("Allocated netdev with %d tx and %d rx queues\n",
13903 tx_count
, rx_count
);
13905 rc
= bnx2x_init_bp(bp
);
13907 goto init_one_exit
;
13909 /* Map doorbells here as we need the real value of bp->max_cos which
13910 * is initialized in bnx2x_init_bp() to determine the number of
13914 bp
->doorbells
= bnx2x_vf_doorbells(bp
);
13915 rc
= bnx2x_vf_pci_alloc(bp
);
13917 goto init_one_freemem
;
13919 doorbell_size
= BNX2X_L2_MAX_CID(bp
) * (1 << BNX2X_DB_SHIFT
);
13920 if (doorbell_size
> pci_resource_len(pdev
, 2)) {
13921 dev_err(&bp
->pdev
->dev
,
13922 "Cannot map doorbells, bar size too small, aborting\n");
13924 goto init_one_freemem
;
13926 bp
->doorbells
= ioremap_nocache(pci_resource_start(pdev
, 2),
13929 if (!bp
->doorbells
) {
13930 dev_err(&bp
->pdev
->dev
,
13931 "Cannot map doorbell space, aborting\n");
13933 goto init_one_freemem
;
13937 rc
= bnx2x_vfpf_acquire(bp
, tx_count
, rx_count
);
13939 goto init_one_freemem
;
13942 /* Enable SRIOV if capability found in configuration space */
13943 rc
= bnx2x_iov_init_one(bp
, int_mode
, BNX2X_MAX_NUM_OF_VFS
);
13945 goto init_one_freemem
;
13947 /* calc qm_cid_count */
13948 bp
->qm_cid_count
= bnx2x_set_qm_cid_count(bp
);
13949 BNX2X_DEV_INFO("qm_cid_count %d\n", bp
->qm_cid_count
);
13951 /* disable FCOE L2 queue for E1x*/
13952 if (CHIP_IS_E1x(bp
))
13953 bp
->flags
|= NO_FCOE_FLAG
;
13955 /* Set bp->num_queues for MSI-X mode*/
13956 bnx2x_set_num_queues(bp
);
13958 /* Configure interrupt mode: try to enable MSI-X/MSI if
13961 rc
= bnx2x_set_int_mode(bp
);
13963 dev_err(&pdev
->dev
, "Cannot set interrupts\n");
13964 goto init_one_freemem
;
13966 BNX2X_DEV_INFO("set interrupts successfully\n");
13968 /* register the net device */
13969 rc
= register_netdev(dev
);
13971 dev_err(&pdev
->dev
, "Cannot register net device\n");
13972 goto init_one_freemem
;
13974 BNX2X_DEV_INFO("device name after netdev register %s\n", dev
->name
);
13976 if (!NO_FCOE(bp
)) {
13977 /* Add storage MAC address */
13979 dev_addr_add(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
13982 if (pcie_get_minimum_link(bp
->pdev
, &pcie_speed
, &pcie_width
) ||
13983 pcie_speed
== PCI_SPEED_UNKNOWN
||
13984 pcie_width
== PCIE_LNK_WIDTH_UNKNOWN
)
13985 BNX2X_DEV_INFO("Failed to determine PCI Express Bandwidth\n");
13988 "%s (%c%d) PCI-E x%d %s found at mem %lx, IRQ %d, node addr %pM\n",
13989 board_info
[ent
->driver_data
].name
,
13990 (CHIP_REV(bp
) >> 12) + 'A', (CHIP_METAL(bp
) >> 4),
13992 pcie_speed
== PCIE_SPEED_2_5GT
? "2.5GHz" :
13993 pcie_speed
== PCIE_SPEED_5_0GT
? "5.0GHz" :
13994 pcie_speed
== PCIE_SPEED_8_0GT
? "8.0GHz" :
13996 dev
->base_addr
, bp
->pdev
->irq
, dev
->dev_addr
);
13998 bnx2x_register_phc(bp
);
14000 if (!IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp
))
14001 bnx2x_set_os_driver_state(bp
, OS_DRIVER_STATE_DISABLED
);
14006 bnx2x_free_mem_bp(bp
);
14009 bnx2x_disable_pcie_error_reporting(bp
);
14012 iounmap(bp
->regview
);
14014 if (IS_PF(bp
) && bp
->doorbells
)
14015 iounmap(bp
->doorbells
);
14019 if (atomic_read(&pdev
->enable_cnt
) == 1)
14020 pci_release_regions(pdev
);
14022 pci_disable_device(pdev
);
14027 static void __bnx2x_remove(struct pci_dev
*pdev
,
14028 struct net_device
*dev
,
14030 bool remove_netdev
)
14032 if (bp
->ptp_clock
) {
14033 ptp_clock_unregister(bp
->ptp_clock
);
14034 bp
->ptp_clock
= NULL
;
14037 /* Delete storage MAC address */
14038 if (!NO_FCOE(bp
)) {
14040 dev_addr_del(bp
->dev
, bp
->fip_mac
, NETDEV_HW_ADDR_T_SAN
);
14045 /* Delete app tlvs from dcbnl */
14046 bnx2x_dcbnl_update_applist(bp
, true);
14051 (bp
->flags
& BC_SUPPORTS_RMMOD_CMD
))
14052 bnx2x_fw_command(bp
, DRV_MSG_CODE_RMMOD
, 0);
14054 /* Close the interface - either directly or implicitly */
14055 if (remove_netdev
) {
14056 unregister_netdev(dev
);
14063 bnx2x_iov_remove_one(bp
);
14065 /* Power on: we can't let PCI layer write to us while we are in D3 */
14067 bnx2x_set_power_state(bp
, PCI_D0
);
14068 bnx2x_set_os_driver_state(bp
, OS_DRIVER_STATE_NOT_LOADED
);
14070 /* Set endianity registers to reset values in case next driver
14071 * boots in different endianty environment.
14073 bnx2x_reset_endianity(bp
);
14076 /* Disable MSI/MSI-X */
14077 bnx2x_disable_msi(bp
);
14081 bnx2x_set_power_state(bp
, PCI_D3hot
);
14083 /* Make sure RESET task is not scheduled before continuing */
14084 cancel_delayed_work_sync(&bp
->sp_rtnl_task
);
14086 /* send message via vfpf channel to release the resources of this vf */
14088 bnx2x_vfpf_release(bp
);
14090 /* Assumes no further PCIe PM changes will occur */
14091 if (system_state
== SYSTEM_POWER_OFF
) {
14092 pci_wake_from_d3(pdev
, bp
->wol
);
14093 pci_set_power_state(pdev
, PCI_D3hot
);
14096 bnx2x_disable_pcie_error_reporting(bp
);
14097 if (remove_netdev
) {
14099 iounmap(bp
->regview
);
14101 /* For vfs, doorbells are part of the regview and were unmapped
14102 * along with it. FW is only loaded by PF.
14106 iounmap(bp
->doorbells
);
14108 bnx2x_release_firmware(bp
);
14110 bnx2x_vf_pci_dealloc(bp
);
14112 bnx2x_free_mem_bp(bp
);
14116 if (atomic_read(&pdev
->enable_cnt
) == 1)
14117 pci_release_regions(pdev
);
14119 pci_disable_device(pdev
);
14123 static void bnx2x_remove_one(struct pci_dev
*pdev
)
14125 struct net_device
*dev
= pci_get_drvdata(pdev
);
14129 dev_err(&pdev
->dev
, "BAD net device from bnx2x_init_one\n");
14132 bp
= netdev_priv(dev
);
14134 __bnx2x_remove(pdev
, dev
, bp
, true);
14137 static int bnx2x_eeh_nic_unload(struct bnx2x
*bp
)
14139 bp
->state
= BNX2X_STATE_CLOSING_WAIT4_HALT
;
14141 bp
->rx_mode
= BNX2X_RX_MODE_NONE
;
14143 if (CNIC_LOADED(bp
))
14144 bnx2x_cnic_notify(bp
, CNIC_CTL_STOP_CMD
);
14147 bnx2x_tx_disable(bp
);
14148 /* Delete all NAPI objects */
14149 bnx2x_del_all_napi(bp
);
14150 if (CNIC_LOADED(bp
))
14151 bnx2x_del_all_napi_cnic(bp
);
14152 netdev_reset_tc(bp
->dev
);
14154 del_timer_sync(&bp
->timer
);
14155 cancel_delayed_work_sync(&bp
->sp_task
);
14156 cancel_delayed_work_sync(&bp
->period_task
);
14158 if (!down_timeout(&bp
->stats_lock
, HZ
/ 10)) {
14159 bp
->stats_state
= STATS_STATE_DISABLED
;
14160 up(&bp
->stats_lock
);
14163 bnx2x_save_statistics(bp
);
14165 netif_carrier_off(bp
->dev
);
14171 * bnx2x_io_error_detected - called when PCI error is detected
14172 * @pdev: Pointer to PCI device
14173 * @state: The current pci connection state
14175 * This function is called after a PCI bus error affecting
14176 * this device has been detected.
14178 static pci_ers_result_t
bnx2x_io_error_detected(struct pci_dev
*pdev
,
14179 pci_channel_state_t state
)
14181 struct net_device
*dev
= pci_get_drvdata(pdev
);
14182 struct bnx2x
*bp
= netdev_priv(dev
);
14186 BNX2X_ERR("IO error detected\n");
14188 netif_device_detach(dev
);
14190 if (state
== pci_channel_io_perm_failure
) {
14192 return PCI_ERS_RESULT_DISCONNECT
;
14195 if (netif_running(dev
))
14196 bnx2x_eeh_nic_unload(bp
);
14198 bnx2x_prev_path_mark_eeh(bp
);
14200 pci_disable_device(pdev
);
14204 /* Request a slot reset */
14205 return PCI_ERS_RESULT_NEED_RESET
;
14209 * bnx2x_io_slot_reset - called after the PCI bus has been reset
14210 * @pdev: Pointer to PCI device
14212 * Restart the card from scratch, as if from a cold-boot.
14214 static pci_ers_result_t
bnx2x_io_slot_reset(struct pci_dev
*pdev
)
14216 struct net_device
*dev
= pci_get_drvdata(pdev
);
14217 struct bnx2x
*bp
= netdev_priv(dev
);
14221 BNX2X_ERR("IO slot reset initializing...\n");
14222 if (pci_enable_device(pdev
)) {
14223 dev_err(&pdev
->dev
,
14224 "Cannot re-enable PCI device after reset\n");
14226 return PCI_ERS_RESULT_DISCONNECT
;
14229 pci_set_master(pdev
);
14230 pci_restore_state(pdev
);
14231 pci_save_state(pdev
);
14233 if (netif_running(dev
))
14234 bnx2x_set_power_state(bp
, PCI_D0
);
14236 if (netif_running(dev
)) {
14237 BNX2X_ERR("IO slot reset --> driver unload\n");
14239 /* MCP should have been reset; Need to wait for validity */
14240 bnx2x_init_shmem(bp
);
14242 if (IS_PF(bp
) && SHMEM2_HAS(bp
, drv_capabilities_flag
)) {
14246 drv_capabilities_flag
[BP_FW_MB_IDX(bp
)]);
14247 SHMEM2_WR(bp
, drv_capabilities_flag
[BP_FW_MB_IDX(bp
)],
14248 v
& ~DRV_FLAGS_CAPABILITIES_LOADED_L2
);
14250 bnx2x_drain_tx_queues(bp
);
14251 bnx2x_send_unload_req(bp
, UNLOAD_RECOVERY
);
14252 bnx2x_netif_stop(bp
, 1);
14253 bnx2x_free_irq(bp
);
14255 /* Report UNLOAD_DONE to MCP */
14256 bnx2x_send_unload_done(bp
, true);
14261 bnx2x_prev_unload(bp
);
14263 /* We should have reseted the engine, so It's fair to
14264 * assume the FW will no longer write to the bnx2x driver.
14266 bnx2x_squeeze_objects(bp
);
14267 bnx2x_free_skbs(bp
);
14268 for_each_rx_queue(bp
, i
)
14269 bnx2x_free_rx_sge_range(bp
, bp
->fp
+ i
, NUM_RX_SGE
);
14270 bnx2x_free_fp_mem(bp
);
14271 bnx2x_free_mem(bp
);
14273 bp
->state
= BNX2X_STATE_CLOSED
;
14278 /* If AER, perform cleanup of the PCIe registers */
14279 if (bp
->flags
& AER_ENABLED
) {
14280 if (pci_cleanup_aer_uncorrect_error_status(pdev
))
14281 BNX2X_ERR("pci_cleanup_aer_uncorrect_error_status failed\n");
14283 DP(NETIF_MSG_HW
, "pci_cleanup_aer_uncorrect_error_status succeeded\n");
14286 return PCI_ERS_RESULT_RECOVERED
;
14290 * bnx2x_io_resume - called when traffic can start flowing again
14291 * @pdev: Pointer to PCI device
14293 * This callback is called when the error recovery driver tells us that
14294 * its OK to resume normal operation.
14296 static void bnx2x_io_resume(struct pci_dev
*pdev
)
14298 struct net_device
*dev
= pci_get_drvdata(pdev
);
14299 struct bnx2x
*bp
= netdev_priv(dev
);
14301 if (bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) {
14302 netdev_err(bp
->dev
, "Handling parity error recovery. Try again later\n");
14308 bp
->fw_seq
= SHMEM_RD(bp
, func_mb
[BP_FW_MB_IDX(bp
)].drv_mb_header
) &
14309 DRV_MSG_SEQ_NUMBER_MASK
;
14311 if (netif_running(dev
))
14312 bnx2x_nic_load(bp
, LOAD_NORMAL
);
14314 netif_device_attach(dev
);
14319 static const struct pci_error_handlers bnx2x_err_handler
= {
14320 .error_detected
= bnx2x_io_error_detected
,
14321 .slot_reset
= bnx2x_io_slot_reset
,
14322 .resume
= bnx2x_io_resume
,
14325 static void bnx2x_shutdown(struct pci_dev
*pdev
)
14327 struct net_device
*dev
= pci_get_drvdata(pdev
);
14333 bp
= netdev_priv(dev
);
14338 netif_device_detach(dev
);
14341 /* Don't remove the netdevice, as there are scenarios which will cause
14342 * the kernel to hang, e.g., when trying to remove bnx2i while the
14343 * rootfs is mounted from SAN.
14345 __bnx2x_remove(pdev
, dev
, bp
, false);
14348 static struct pci_driver bnx2x_pci_driver
= {
14349 .name
= DRV_MODULE_NAME
,
14350 .id_table
= bnx2x_pci_tbl
,
14351 .probe
= bnx2x_init_one
,
14352 .remove
= bnx2x_remove_one
,
14353 .suspend
= bnx2x_suspend
,
14354 .resume
= bnx2x_resume
,
14355 .err_handler
= &bnx2x_err_handler
,
14356 #ifdef CONFIG_BNX2X_SRIOV
14357 .sriov_configure
= bnx2x_sriov_configure
,
14359 .shutdown
= bnx2x_shutdown
,
14362 static int __init
bnx2x_init(void)
14366 pr_info("%s", version
);
14368 bnx2x_wq
= create_singlethread_workqueue("bnx2x");
14369 if (bnx2x_wq
== NULL
) {
14370 pr_err("Cannot create workqueue\n");
14373 bnx2x_iov_wq
= create_singlethread_workqueue("bnx2x_iov");
14374 if (!bnx2x_iov_wq
) {
14375 pr_err("Cannot create iov workqueue\n");
14376 destroy_workqueue(bnx2x_wq
);
14380 ret
= pci_register_driver(&bnx2x_pci_driver
);
14382 pr_err("Cannot register driver\n");
14383 destroy_workqueue(bnx2x_wq
);
14384 destroy_workqueue(bnx2x_iov_wq
);
14389 static void __exit
bnx2x_cleanup(void)
14391 struct list_head
*pos
, *q
;
14393 pci_unregister_driver(&bnx2x_pci_driver
);
14395 destroy_workqueue(bnx2x_wq
);
14396 destroy_workqueue(bnx2x_iov_wq
);
14398 /* Free globally allocated resources */
14399 list_for_each_safe(pos
, q
, &bnx2x_prev_list
) {
14400 struct bnx2x_prev_path_list
*tmp
=
14401 list_entry(pos
, struct bnx2x_prev_path_list
, list
);
14407 void bnx2x_notify_link_changed(struct bnx2x
*bp
)
14409 REG_WR(bp
, MISC_REG_AEU_GENERAL_ATTN_12
+ BP_FUNC(bp
)*sizeof(u32
), 1);
14412 module_init(bnx2x_init
);
14413 module_exit(bnx2x_cleanup
);
14416 * bnx2x_set_iscsi_eth_mac_addr - set iSCSI MAC(s).
14418 * @bp: driver handle
14419 * @set: set or clear the CAM entry
14421 * This function will wait until the ramrod completion returns.
14422 * Return 0 if success, -ENODEV if ramrod doesn't return.
14424 static int bnx2x_set_iscsi_eth_mac_addr(struct bnx2x
*bp
)
14426 unsigned long ramrod_flags
= 0;
14428 __set_bit(RAMROD_COMP_WAIT
, &ramrod_flags
);
14429 return bnx2x_set_mac_one(bp
, bp
->cnic_eth_dev
.iscsi_mac
,
14430 &bp
->iscsi_l2_mac_obj
, true,
14431 BNX2X_ISCSI_ETH_MAC
, &ramrod_flags
);
14434 /* count denotes the number of new completions we have seen */
14435 static void bnx2x_cnic_sp_post(struct bnx2x
*bp
, int count
)
14437 struct eth_spe
*spe
;
14438 int cxt_index
, cxt_offset
;
14440 #ifdef BNX2X_STOP_ON_ERROR
14441 if (unlikely(bp
->panic
))
14445 spin_lock_bh(&bp
->spq_lock
);
14446 BUG_ON(bp
->cnic_spq_pending
< count
);
14447 bp
->cnic_spq_pending
-= count
;
14449 for (; bp
->cnic_kwq_pending
; bp
->cnic_kwq_pending
--) {
14450 u16 type
= (le16_to_cpu(bp
->cnic_kwq_cons
->hdr
.type
)
14451 & SPE_HDR_CONN_TYPE
) >>
14452 SPE_HDR_CONN_TYPE_SHIFT
;
14453 u8 cmd
= (le32_to_cpu(bp
->cnic_kwq_cons
->hdr
.conn_and_cmd_data
)
14454 >> SPE_HDR_CMD_ID_SHIFT
) & 0xff;
14456 /* Set validation for iSCSI L2 client before sending SETUP
14459 if (type
== ETH_CONNECTION_TYPE
) {
14460 if (cmd
== RAMROD_CMD_ID_ETH_CLIENT_SETUP
) {
14461 cxt_index
= BNX2X_ISCSI_ETH_CID(bp
) /
14463 cxt_offset
= BNX2X_ISCSI_ETH_CID(bp
) -
14464 (cxt_index
* ILT_PAGE_CIDS
);
14465 bnx2x_set_ctx_validation(bp
,
14466 &bp
->context
[cxt_index
].
14467 vcxt
[cxt_offset
].eth
,
14468 BNX2X_ISCSI_ETH_CID(bp
));
14473 * There may be not more than 8 L2, not more than 8 L5 SPEs
14474 * and in the air. We also check that number of outstanding
14475 * COMMON ramrods is not more than the EQ and SPQ can
14478 if (type
== ETH_CONNECTION_TYPE
) {
14479 if (!atomic_read(&bp
->cq_spq_left
))
14482 atomic_dec(&bp
->cq_spq_left
);
14483 } else if (type
== NONE_CONNECTION_TYPE
) {
14484 if (!atomic_read(&bp
->eq_spq_left
))
14487 atomic_dec(&bp
->eq_spq_left
);
14488 } else if ((type
== ISCSI_CONNECTION_TYPE
) ||
14489 (type
== FCOE_CONNECTION_TYPE
)) {
14490 if (bp
->cnic_spq_pending
>=
14491 bp
->cnic_eth_dev
.max_kwqe_pending
)
14494 bp
->cnic_spq_pending
++;
14496 BNX2X_ERR("Unknown SPE type: %d\n", type
);
14501 spe
= bnx2x_sp_get_next(bp
);
14502 *spe
= *bp
->cnic_kwq_cons
;
14504 DP(BNX2X_MSG_SP
, "pending on SPQ %d, on KWQ %d count %d\n",
14505 bp
->cnic_spq_pending
, bp
->cnic_kwq_pending
, count
);
14507 if (bp
->cnic_kwq_cons
== bp
->cnic_kwq_last
)
14508 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
14510 bp
->cnic_kwq_cons
++;
14512 bnx2x_sp_prod_update(bp
);
14513 spin_unlock_bh(&bp
->spq_lock
);
14516 static int bnx2x_cnic_sp_queue(struct net_device
*dev
,
14517 struct kwqe_16
*kwqes
[], u32 count
)
14519 struct bnx2x
*bp
= netdev_priv(dev
);
14522 #ifdef BNX2X_STOP_ON_ERROR
14523 if (unlikely(bp
->panic
)) {
14524 BNX2X_ERR("Can't post to SP queue while panic\n");
14529 if ((bp
->recovery_state
!= BNX2X_RECOVERY_DONE
) &&
14530 (bp
->recovery_state
!= BNX2X_RECOVERY_NIC_LOADING
)) {
14531 BNX2X_ERR("Handling parity error recovery. Try again later\n");
14535 spin_lock_bh(&bp
->spq_lock
);
14537 for (i
= 0; i
< count
; i
++) {
14538 struct eth_spe
*spe
= (struct eth_spe
*)kwqes
[i
];
14540 if (bp
->cnic_kwq_pending
== MAX_SP_DESC_CNT
)
14543 *bp
->cnic_kwq_prod
= *spe
;
14545 bp
->cnic_kwq_pending
++;
14547 DP(BNX2X_MSG_SP
, "L5 SPQE %x %x %x:%x pos %d\n",
14548 spe
->hdr
.conn_and_cmd_data
, spe
->hdr
.type
,
14549 spe
->data
.update_data_addr
.hi
,
14550 spe
->data
.update_data_addr
.lo
,
14551 bp
->cnic_kwq_pending
);
14553 if (bp
->cnic_kwq_prod
== bp
->cnic_kwq_last
)
14554 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
14556 bp
->cnic_kwq_prod
++;
14559 spin_unlock_bh(&bp
->spq_lock
);
14561 if (bp
->cnic_spq_pending
< bp
->cnic_eth_dev
.max_kwqe_pending
)
14562 bnx2x_cnic_sp_post(bp
, 0);
14567 static int bnx2x_cnic_ctl_send(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
14569 struct cnic_ops
*c_ops
;
14572 mutex_lock(&bp
->cnic_mutex
);
14573 c_ops
= rcu_dereference_protected(bp
->cnic_ops
,
14574 lockdep_is_held(&bp
->cnic_mutex
));
14576 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
14577 mutex_unlock(&bp
->cnic_mutex
);
14582 static int bnx2x_cnic_ctl_send_bh(struct bnx2x
*bp
, struct cnic_ctl_info
*ctl
)
14584 struct cnic_ops
*c_ops
;
14588 c_ops
= rcu_dereference(bp
->cnic_ops
);
14590 rc
= c_ops
->cnic_ctl(bp
->cnic_data
, ctl
);
14597 * for commands that have no data
14599 int bnx2x_cnic_notify(struct bnx2x
*bp
, int cmd
)
14601 struct cnic_ctl_info ctl
= {0};
14605 return bnx2x_cnic_ctl_send(bp
, &ctl
);
14608 static void bnx2x_cnic_cfc_comp(struct bnx2x
*bp
, int cid
, u8 err
)
14610 struct cnic_ctl_info ctl
= {0};
14612 /* first we tell CNIC and only then we count this as a completion */
14613 ctl
.cmd
= CNIC_CTL_COMPLETION_CMD
;
14614 ctl
.data
.comp
.cid
= cid
;
14615 ctl
.data
.comp
.error
= err
;
14617 bnx2x_cnic_ctl_send_bh(bp
, &ctl
);
14618 bnx2x_cnic_sp_post(bp
, 0);
14621 /* Called with netif_addr_lock_bh() taken.
14622 * Sets an rx_mode config for an iSCSI ETH client.
14624 * Completion should be checked outside.
14626 static void bnx2x_set_iscsi_eth_rx_mode(struct bnx2x
*bp
, bool start
)
14628 unsigned long accept_flags
= 0, ramrod_flags
= 0;
14629 u8 cl_id
= bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
14630 int sched_state
= BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
;
14633 /* Start accepting on iSCSI L2 ring. Accept all multicasts
14634 * because it's the only way for UIO Queue to accept
14635 * multicasts (in non-promiscuous mode only one Queue per
14636 * function will receive multicast packets (leading in our
14639 __set_bit(BNX2X_ACCEPT_UNICAST
, &accept_flags
);
14640 __set_bit(BNX2X_ACCEPT_ALL_MULTICAST
, &accept_flags
);
14641 __set_bit(BNX2X_ACCEPT_BROADCAST
, &accept_flags
);
14642 __set_bit(BNX2X_ACCEPT_ANY_VLAN
, &accept_flags
);
14644 /* Clear STOP_PENDING bit if START is requested */
14645 clear_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &bp
->sp_state
);
14647 sched_state
= BNX2X_FILTER_ISCSI_ETH_START_SCHED
;
14649 /* Clear START_PENDING bit if STOP is requested */
14650 clear_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &bp
->sp_state
);
14652 if (test_bit(BNX2X_FILTER_RX_MODE_PENDING
, &bp
->sp_state
))
14653 set_bit(sched_state
, &bp
->sp_state
);
14655 __set_bit(RAMROD_RX
, &ramrod_flags
);
14656 bnx2x_set_q_rx_mode(bp
, cl_id
, 0, accept_flags
, 0,
14661 static int bnx2x_drv_ctl(struct net_device
*dev
, struct drv_ctl_info
*ctl
)
14663 struct bnx2x
*bp
= netdev_priv(dev
);
14666 switch (ctl
->cmd
) {
14667 case DRV_CTL_CTXTBL_WR_CMD
: {
14668 u32 index
= ctl
->data
.io
.offset
;
14669 dma_addr_t addr
= ctl
->data
.io
.dma_addr
;
14671 bnx2x_ilt_wr(bp
, index
, addr
);
14675 case DRV_CTL_RET_L5_SPQ_CREDIT_CMD
: {
14676 int count
= ctl
->data
.credit
.credit_count
;
14678 bnx2x_cnic_sp_post(bp
, count
);
14682 /* rtnl_lock is held. */
14683 case DRV_CTL_START_L2_CMD
: {
14684 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14685 unsigned long sp_bits
= 0;
14687 /* Configure the iSCSI classification object */
14688 bnx2x_init_mac_obj(bp
, &bp
->iscsi_l2_mac_obj
,
14689 cp
->iscsi_l2_client_id
,
14690 cp
->iscsi_l2_cid
, BP_FUNC(bp
),
14691 bnx2x_sp(bp
, mac_rdata
),
14692 bnx2x_sp_mapping(bp
, mac_rdata
),
14693 BNX2X_FILTER_MAC_PENDING
,
14694 &bp
->sp_state
, BNX2X_OBJ_TYPE_RX
,
14697 /* Set iSCSI MAC address */
14698 rc
= bnx2x_set_iscsi_eth_mac_addr(bp
);
14705 /* Start accepting on iSCSI L2 ring */
14707 netif_addr_lock_bh(dev
);
14708 bnx2x_set_iscsi_eth_rx_mode(bp
, true);
14709 netif_addr_unlock_bh(dev
);
14711 /* bits to wait on */
14712 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
14713 __set_bit(BNX2X_FILTER_ISCSI_ETH_START_SCHED
, &sp_bits
);
14715 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
14716 BNX2X_ERR("rx_mode completion timed out!\n");
14721 /* rtnl_lock is held. */
14722 case DRV_CTL_STOP_L2_CMD
: {
14723 unsigned long sp_bits
= 0;
14725 /* Stop accepting on iSCSI L2 ring */
14726 netif_addr_lock_bh(dev
);
14727 bnx2x_set_iscsi_eth_rx_mode(bp
, false);
14728 netif_addr_unlock_bh(dev
);
14730 /* bits to wait on */
14731 __set_bit(BNX2X_FILTER_RX_MODE_PENDING
, &sp_bits
);
14732 __set_bit(BNX2X_FILTER_ISCSI_ETH_STOP_SCHED
, &sp_bits
);
14734 if (!bnx2x_wait_sp_comp(bp
, sp_bits
))
14735 BNX2X_ERR("rx_mode completion timed out!\n");
14740 /* Unset iSCSI L2 MAC */
14741 rc
= bnx2x_del_all_macs(bp
, &bp
->iscsi_l2_mac_obj
,
14742 BNX2X_ISCSI_ETH_MAC
, true);
14745 case DRV_CTL_RET_L2_SPQ_CREDIT_CMD
: {
14746 int count
= ctl
->data
.credit
.credit_count
;
14748 smp_mb__before_atomic();
14749 atomic_add(count
, &bp
->cq_spq_left
);
14750 smp_mb__after_atomic();
14753 case DRV_CTL_ULP_REGISTER_CMD
: {
14754 int ulp_type
= ctl
->data
.register_data
.ulp_type
;
14756 if (CHIP_IS_E3(bp
)) {
14757 int idx
= BP_FW_MB_IDX(bp
);
14758 u32 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
14759 int path
= BP_PATH(bp
);
14760 int port
= BP_PORT(bp
);
14762 u32 scratch_offset
;
14765 /* first write capability to shmem2 */
14766 if (ulp_type
== CNIC_ULP_ISCSI
)
14767 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
14768 else if (ulp_type
== CNIC_ULP_FCOE
)
14769 cap
|= DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
14770 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
14772 if ((ulp_type
!= CNIC_ULP_FCOE
) ||
14773 (!SHMEM2_HAS(bp
, ncsi_oem_data_addr
)) ||
14774 (!(bp
->flags
& BC_SUPPORTS_FCOE_FEATURES
)))
14777 /* if reached here - should write fcoe capabilities */
14778 scratch_offset
= SHMEM2_RD(bp
, ncsi_oem_data_addr
);
14779 if (!scratch_offset
)
14781 scratch_offset
+= offsetof(struct glob_ncsi_oem_data
,
14782 fcoe_features
[path
][port
]);
14783 host_addr
= (u32
*) &(ctl
->data
.register_data
.
14785 for (i
= 0; i
< sizeof(struct fcoe_capabilities
);
14787 REG_WR(bp
, scratch_offset
+ i
,
14788 *(host_addr
+ i
/4));
14790 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_GET_DRV_VERSION
, 0);
14794 case DRV_CTL_ULP_UNREGISTER_CMD
: {
14795 int ulp_type
= ctl
->data
.ulp_type
;
14797 if (CHIP_IS_E3(bp
)) {
14798 int idx
= BP_FW_MB_IDX(bp
);
14801 cap
= SHMEM2_RD(bp
, drv_capabilities_flag
[idx
]);
14802 if (ulp_type
== CNIC_ULP_ISCSI
)
14803 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_ISCSI
;
14804 else if (ulp_type
== CNIC_ULP_FCOE
)
14805 cap
&= ~DRV_FLAGS_CAPABILITIES_LOADED_FCOE
;
14806 SHMEM2_WR(bp
, drv_capabilities_flag
[idx
], cap
);
14808 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_GET_DRV_VERSION
, 0);
14813 BNX2X_ERR("unknown command %x\n", ctl
->cmd
);
14817 /* For storage-only interfaces, change driver state */
14818 if (IS_MF_SD_STORAGE_PERSONALITY_ONLY(bp
)) {
14819 switch (ctl
->drv_state
) {
14823 bnx2x_set_os_driver_state(bp
,
14824 OS_DRIVER_STATE_ACTIVE
);
14827 bnx2x_set_os_driver_state(bp
,
14828 OS_DRIVER_STATE_DISABLED
);
14831 bnx2x_set_os_driver_state(bp
,
14832 OS_DRIVER_STATE_NOT_LOADED
);
14835 BNX2X_ERR("Unknown cnic driver state: %d\n", ctl
->drv_state
);
14842 static int bnx2x_get_fc_npiv(struct net_device
*dev
,
14843 struct cnic_fc_npiv_tbl
*cnic_tbl
)
14845 struct bnx2x
*bp
= netdev_priv(dev
);
14846 struct bdn_fc_npiv_tbl
*tbl
= NULL
;
14847 u32 offset
, entries
;
14851 if (!SHMEM2_HAS(bp
, fc_npiv_nvram_tbl_addr
[0]))
14854 DP(BNX2X_MSG_MCP
, "About to read the FC-NPIV table\n");
14856 tbl
= kmalloc(sizeof(*tbl
), GFP_KERNEL
);
14858 BNX2X_ERR("Failed to allocate fc_npiv table\n");
14862 offset
= SHMEM2_RD(bp
, fc_npiv_nvram_tbl_addr
[BP_PORT(bp
)]);
14864 DP(BNX2X_MSG_MCP
, "No FC-NPIV in NVRAM\n");
14867 DP(BNX2X_MSG_MCP
, "Offset of FC-NPIV in NVRAM: %08x\n", offset
);
14869 /* Read the table contents from nvram */
14870 if (bnx2x_nvram_read(bp
, offset
, (u8
*)tbl
, sizeof(*tbl
))) {
14871 BNX2X_ERR("Failed to read FC-NPIV table\n");
14875 /* Since bnx2x_nvram_read() returns data in be32, we need to convert
14876 * the number of entries back to cpu endianness.
14878 entries
= tbl
->fc_npiv_cfg
.num_of_npiv
;
14879 entries
= (__force u32
)be32_to_cpu((__force __be32
)entries
);
14880 tbl
->fc_npiv_cfg
.num_of_npiv
= entries
;
14882 if (!tbl
->fc_npiv_cfg
.num_of_npiv
) {
14884 "No FC-NPIV table [valid, simply not present]\n");
14886 } else if (tbl
->fc_npiv_cfg
.num_of_npiv
> MAX_NUMBER_NPIV
) {
14887 BNX2X_ERR("FC-NPIV table with bad length 0x%08x\n",
14888 tbl
->fc_npiv_cfg
.num_of_npiv
);
14891 DP(BNX2X_MSG_MCP
, "Read 0x%08x entries from NVRAM\n",
14892 tbl
->fc_npiv_cfg
.num_of_npiv
);
14895 /* Copy the data into cnic-provided struct */
14896 cnic_tbl
->count
= tbl
->fc_npiv_cfg
.num_of_npiv
;
14897 for (i
= 0; i
< cnic_tbl
->count
; i
++) {
14898 memcpy(cnic_tbl
->wwpn
[i
], tbl
->settings
[i
].npiv_wwpn
, 8);
14899 memcpy(cnic_tbl
->wwnn
[i
], tbl
->settings
[i
].npiv_wwnn
, 8);
14908 void bnx2x_setup_cnic_irq_info(struct bnx2x
*bp
)
14910 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14912 if (bp
->flags
& USING_MSIX_FLAG
) {
14913 cp
->drv_state
|= CNIC_DRV_STATE_USING_MSIX
;
14914 cp
->irq_arr
[0].irq_flags
|= CNIC_IRQ_FL_MSIX
;
14915 cp
->irq_arr
[0].vector
= bp
->msix_table
[1].vector
;
14917 cp
->drv_state
&= ~CNIC_DRV_STATE_USING_MSIX
;
14918 cp
->irq_arr
[0].irq_flags
&= ~CNIC_IRQ_FL_MSIX
;
14920 if (!CHIP_IS_E1x(bp
))
14921 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e2_sb
;
14923 cp
->irq_arr
[0].status_blk
= (void *)bp
->cnic_sb
.e1x_sb
;
14925 cp
->irq_arr
[0].status_blk_num
= bnx2x_cnic_fw_sb_id(bp
);
14926 cp
->irq_arr
[0].status_blk_num2
= bnx2x_cnic_igu_sb_id(bp
);
14927 cp
->irq_arr
[1].status_blk
= bp
->def_status_blk
;
14928 cp
->irq_arr
[1].status_blk_num
= DEF_SB_ID
;
14929 cp
->irq_arr
[1].status_blk_num2
= DEF_SB_IGU_ID
;
14934 void bnx2x_setup_cnic_info(struct bnx2x
*bp
)
14936 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14938 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
14939 bnx2x_cid_ilt_lines(bp
);
14940 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
14941 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
14942 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
14944 DP(NETIF_MSG_IFUP
, "BNX2X_1st_NON_L2_ETH_CID(bp) %x, cp->starting_cid %x, cp->fcoe_init_cid %x, cp->iscsi_l2_cid %x\n",
14945 BNX2X_1st_NON_L2_ETH_CID(bp
), cp
->starting_cid
, cp
->fcoe_init_cid
,
14948 if (NO_ISCSI_OOO(bp
))
14949 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
14952 static int bnx2x_register_cnic(struct net_device
*dev
, struct cnic_ops
*ops
,
14955 struct bnx2x
*bp
= netdev_priv(dev
);
14956 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
14959 DP(NETIF_MSG_IFUP
, "Register_cnic called\n");
14962 BNX2X_ERR("NULL ops received\n");
14966 if (!CNIC_SUPPORT(bp
)) {
14967 BNX2X_ERR("Can't register CNIC when not supported\n");
14968 return -EOPNOTSUPP
;
14971 if (!CNIC_LOADED(bp
)) {
14972 rc
= bnx2x_load_cnic(bp
);
14974 BNX2X_ERR("CNIC-related load failed\n");
14979 bp
->cnic_enabled
= true;
14981 bp
->cnic_kwq
= kzalloc(PAGE_SIZE
, GFP_KERNEL
);
14985 bp
->cnic_kwq_cons
= bp
->cnic_kwq
;
14986 bp
->cnic_kwq_prod
= bp
->cnic_kwq
;
14987 bp
->cnic_kwq_last
= bp
->cnic_kwq
+ MAX_SP_DESC_CNT
;
14989 bp
->cnic_spq_pending
= 0;
14990 bp
->cnic_kwq_pending
= 0;
14992 bp
->cnic_data
= data
;
14995 cp
->drv_state
|= CNIC_DRV_STATE_REGD
;
14996 cp
->iro_arr
= bp
->iro_arr
;
14998 bnx2x_setup_cnic_irq_info(bp
);
15000 rcu_assign_pointer(bp
->cnic_ops
, ops
);
15002 /* Schedule driver to read CNIC driver versions */
15003 bnx2x_schedule_sp_rtnl(bp
, BNX2X_SP_RTNL_GET_DRV_VERSION
, 0);
15008 static int bnx2x_unregister_cnic(struct net_device
*dev
)
15010 struct bnx2x
*bp
= netdev_priv(dev
);
15011 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
15013 mutex_lock(&bp
->cnic_mutex
);
15015 RCU_INIT_POINTER(bp
->cnic_ops
, NULL
);
15016 mutex_unlock(&bp
->cnic_mutex
);
15018 bp
->cnic_enabled
= false;
15019 kfree(bp
->cnic_kwq
);
15020 bp
->cnic_kwq
= NULL
;
15025 static struct cnic_eth_dev
*bnx2x_cnic_probe(struct net_device
*dev
)
15027 struct bnx2x
*bp
= netdev_priv(dev
);
15028 struct cnic_eth_dev
*cp
= &bp
->cnic_eth_dev
;
15030 /* If both iSCSI and FCoE are disabled - return NULL in
15031 * order to indicate CNIC that it should not try to work
15032 * with this device.
15034 if (NO_ISCSI(bp
) && NO_FCOE(bp
))
15037 cp
->drv_owner
= THIS_MODULE
;
15038 cp
->chip_id
= CHIP_ID(bp
);
15039 cp
->pdev
= bp
->pdev
;
15040 cp
->io_base
= bp
->regview
;
15041 cp
->io_base2
= bp
->doorbells
;
15042 cp
->max_kwqe_pending
= 8;
15043 cp
->ctx_blk_size
= CDU_ILT_PAGE_SZ
;
15044 cp
->ctx_tbl_offset
= FUNC_ILT_BASE(BP_FUNC(bp
)) +
15045 bnx2x_cid_ilt_lines(bp
);
15046 cp
->ctx_tbl_len
= CNIC_ILT_LINES
;
15047 cp
->starting_cid
= bnx2x_cid_ilt_lines(bp
) * ILT_PAGE_CIDS
;
15048 cp
->drv_submit_kwqes_16
= bnx2x_cnic_sp_queue
;
15049 cp
->drv_ctl
= bnx2x_drv_ctl
;
15050 cp
->drv_get_fc_npiv_tbl
= bnx2x_get_fc_npiv
;
15051 cp
->drv_register_cnic
= bnx2x_register_cnic
;
15052 cp
->drv_unregister_cnic
= bnx2x_unregister_cnic
;
15053 cp
->fcoe_init_cid
= BNX2X_FCOE_ETH_CID(bp
);
15054 cp
->iscsi_l2_client_id
=
15055 bnx2x_cnic_eth_cl_id(bp
, BNX2X_ISCSI_ETH_CL_ID_IDX
);
15056 cp
->iscsi_l2_cid
= BNX2X_ISCSI_ETH_CID(bp
);
15058 if (NO_ISCSI_OOO(bp
))
15059 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI_OOO
;
15062 cp
->drv_state
|= CNIC_DRV_STATE_NO_ISCSI
;
15065 cp
->drv_state
|= CNIC_DRV_STATE_NO_FCOE
;
15068 "page_size %d, tbl_offset %d, tbl_lines %d, starting cid %d\n",
15070 cp
->ctx_tbl_offset
,
15076 static u32
bnx2x_rx_ustorm_prods_offset(struct bnx2x_fastpath
*fp
)
15078 struct bnx2x
*bp
= fp
->bp
;
15079 u32 offset
= BAR_USTRORM_INTMEM
;
15082 return bnx2x_vf_ustorm_prods_offset(bp
, fp
);
15083 else if (!CHIP_IS_E1x(bp
))
15084 offset
+= USTORM_RX_PRODS_E2_OFFSET(fp
->cl_qzone_id
);
15086 offset
+= USTORM_RX_PRODS_E1X_OFFSET(BP_PORT(bp
), fp
->cl_id
);
15091 /* called only on E1H or E2.
15092 * When pretending to be PF, the pretend value is the function number 0...7
15093 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID
15096 int bnx2x_pretend_func(struct bnx2x
*bp
, u16 pretend_func_val
)
15100 if (CHIP_IS_E1H(bp
) && pretend_func_val
>= E1H_FUNC_MAX
)
15103 /* get my own pretend register */
15104 pretend_reg
= bnx2x_get_pretend_reg(bp
);
15105 REG_WR(bp
, pretend_reg
, pretend_func_val
);
15106 REG_RD(bp
, pretend_reg
);
15110 static void bnx2x_ptp_task(struct work_struct
*work
)
15112 struct bnx2x
*bp
= container_of(work
, struct bnx2x
, ptp_task
);
15113 int port
= BP_PORT(bp
);
15116 struct skb_shared_hwtstamps shhwtstamps
;
15118 /* Read Tx timestamp registers */
15119 val_seq
= REG_RD(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_SEQID
:
15120 NIG_REG_P0_TLLH_PTP_BUF_SEQID
);
15121 if (val_seq
& 0x10000) {
15122 /* There is a valid timestamp value */
15123 timestamp
= REG_RD(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB
:
15124 NIG_REG_P0_TLLH_PTP_BUF_TS_MSB
);
15126 timestamp
|= REG_RD(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB
:
15127 NIG_REG_P0_TLLH_PTP_BUF_TS_LSB
);
15128 /* Reset timestamp register to allow new timestamp */
15129 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_SEQID
:
15130 NIG_REG_P0_TLLH_PTP_BUF_SEQID
, 0x10000);
15131 ns
= timecounter_cyc2time(&bp
->timecounter
, timestamp
);
15133 memset(&shhwtstamps
, 0, sizeof(shhwtstamps
));
15134 shhwtstamps
.hwtstamp
= ns_to_ktime(ns
);
15135 skb_tstamp_tx(bp
->ptp_tx_skb
, &shhwtstamps
);
15136 dev_kfree_skb_any(bp
->ptp_tx_skb
);
15137 bp
->ptp_tx_skb
= NULL
;
15139 DP(BNX2X_MSG_PTP
, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
15142 DP(BNX2X_MSG_PTP
, "There is no valid Tx timestamp yet\n");
15143 /* Reschedule to keep checking for a valid timestamp value */
15144 schedule_work(&bp
->ptp_task
);
15148 void bnx2x_set_rx_ts(struct bnx2x
*bp
, struct sk_buff
*skb
)
15150 int port
= BP_PORT(bp
);
15153 timestamp
= REG_RD(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB
:
15154 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB
);
15156 timestamp
|= REG_RD(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB
:
15157 NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB
);
15159 /* Reset timestamp register to allow new timestamp */
15160 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID
:
15161 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID
, 0x10000);
15163 ns
= timecounter_cyc2time(&bp
->timecounter
, timestamp
);
15165 skb_hwtstamps(skb
)->hwtstamp
= ns_to_ktime(ns
);
15167 DP(BNX2X_MSG_PTP
, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
15172 static cycle_t
bnx2x_cyclecounter_read(const struct cyclecounter
*cc
)
15174 struct bnx2x
*bp
= container_of(cc
, struct bnx2x
, cyclecounter
);
15175 int port
= BP_PORT(bp
);
15179 REG_RD_DMAE(bp
, port
? NIG_REG_TIMESYNC_GEN_REG
+ tsgen_synctime_t1
:
15180 NIG_REG_TIMESYNC_GEN_REG
+ tsgen_synctime_t0
, wb_data
, 2);
15181 phc_cycles
= wb_data
[1];
15182 phc_cycles
= (phc_cycles
<< 32) + wb_data
[0];
15184 DP(BNX2X_MSG_PTP
, "PHC read cycles = %llu\n", phc_cycles
);
15189 static void bnx2x_init_cyclecounter(struct bnx2x
*bp
)
15191 memset(&bp
->cyclecounter
, 0, sizeof(bp
->cyclecounter
));
15192 bp
->cyclecounter
.read
= bnx2x_cyclecounter_read
;
15193 bp
->cyclecounter
.mask
= CYCLECOUNTER_MASK(64);
15194 bp
->cyclecounter
.shift
= 1;
15195 bp
->cyclecounter
.mult
= 1;
15198 static int bnx2x_send_reset_timesync_ramrod(struct bnx2x
*bp
)
15200 struct bnx2x_func_state_params func_params
= {NULL
};
15201 struct bnx2x_func_set_timesync_params
*set_timesync_params
=
15202 &func_params
.params
.set_timesync
;
15204 /* Prepare parameters for function state transitions */
15205 __set_bit(RAMROD_COMP_WAIT
, &func_params
.ramrod_flags
);
15206 __set_bit(RAMROD_RETRY
, &func_params
.ramrod_flags
);
15208 func_params
.f_obj
= &bp
->func_obj
;
15209 func_params
.cmd
= BNX2X_F_CMD_SET_TIMESYNC
;
15211 /* Function parameters */
15212 set_timesync_params
->drift_adjust_cmd
= TS_DRIFT_ADJUST_RESET
;
15213 set_timesync_params
->offset_cmd
= TS_OFFSET_KEEP
;
15215 return bnx2x_func_state_change(bp
, &func_params
);
15218 static int bnx2x_enable_ptp_packets(struct bnx2x
*bp
)
15220 struct bnx2x_queue_state_params q_params
;
15223 /* send queue update ramrod to enable PTP packets */
15224 memset(&q_params
, 0, sizeof(q_params
));
15225 __set_bit(RAMROD_COMP_WAIT
, &q_params
.ramrod_flags
);
15226 q_params
.cmd
= BNX2X_Q_CMD_UPDATE
;
15227 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG
,
15228 &q_params
.params
.update
.update_flags
);
15229 __set_bit(BNX2X_Q_UPDATE_PTP_PKTS
,
15230 &q_params
.params
.update
.update_flags
);
15232 /* send the ramrod on all the queues of the PF */
15233 for_each_eth_queue(bp
, i
) {
15234 struct bnx2x_fastpath
*fp
= &bp
->fp
[i
];
15236 /* Set the appropriate Queue object */
15237 q_params
.q_obj
= &bnx2x_sp_obj(bp
, fp
).q_obj
;
15239 /* Update the Queue state */
15240 rc
= bnx2x_queue_state_change(bp
, &q_params
);
15242 BNX2X_ERR("Failed to enable PTP packets\n");
15250 int bnx2x_configure_ptp_filters(struct bnx2x
*bp
)
15252 int port
= BP_PORT(bp
);
15255 if (!bp
->hwtstamp_ioctl_called
)
15258 switch (bp
->tx_type
) {
15259 case HWTSTAMP_TX_ON
:
15260 bp
->flags
|= TX_TIMESTAMPING_EN
;
15261 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_PARAM_MASK
:
15262 NIG_REG_P0_TLLH_PTP_PARAM_MASK
, 0x6AA);
15263 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_RULE_MASK
:
15264 NIG_REG_P0_TLLH_PTP_RULE_MASK
, 0x3EEE);
15266 case HWTSTAMP_TX_ONESTEP_SYNC
:
15267 BNX2X_ERR("One-step timestamping is not supported\n");
15271 switch (bp
->rx_filter
) {
15272 case HWTSTAMP_FILTER_NONE
:
15274 case HWTSTAMP_FILTER_ALL
:
15275 case HWTSTAMP_FILTER_SOME
:
15276 bp
->rx_filter
= HWTSTAMP_FILTER_NONE
;
15278 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
15279 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
15280 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
15281 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
15282 /* Initialize PTP detection for UDP/IPv4 events */
15283 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15284 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7EE);
15285 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15286 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FFE);
15288 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
15289 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
15290 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
15291 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
15292 /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
15293 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15294 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7EA);
15295 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15296 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FEE);
15298 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
15299 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
15300 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
15301 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_L2_EVENT
;
15302 /* Initialize PTP detection L2 events */
15303 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15304 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x6BF);
15305 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15306 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3EFF);
15309 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
15310 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
15311 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
15312 bp
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_EVENT
;
15313 /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
15314 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15315 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x6AA);
15316 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15317 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3EEE);
15321 /* Indicate to FW that this PF expects recorded PTP packets */
15322 rc
= bnx2x_enable_ptp_packets(bp
);
15326 /* Enable sending PTP packets to host */
15327 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_TO_HOST
:
15328 NIG_REG_P0_LLH_PTP_TO_HOST
, 0x1);
15333 static int bnx2x_hwtstamp_ioctl(struct bnx2x
*bp
, struct ifreq
*ifr
)
15335 struct hwtstamp_config config
;
15338 DP(BNX2X_MSG_PTP
, "HWTSTAMP IOCTL called\n");
15340 if (copy_from_user(&config
, ifr
->ifr_data
, sizeof(config
)))
15343 DP(BNX2X_MSG_PTP
, "Requested tx_type: %d, requested rx_filters = %d\n",
15344 config
.tx_type
, config
.rx_filter
);
15346 if (config
.flags
) {
15347 BNX2X_ERR("config.flags is reserved for future use\n");
15351 bp
->hwtstamp_ioctl_called
= 1;
15352 bp
->tx_type
= config
.tx_type
;
15353 bp
->rx_filter
= config
.rx_filter
;
15355 rc
= bnx2x_configure_ptp_filters(bp
);
15359 config
.rx_filter
= bp
->rx_filter
;
15361 return copy_to_user(ifr
->ifr_data
, &config
, sizeof(config
)) ?
15365 /* Configures HW for PTP */
15366 static int bnx2x_configure_ptp(struct bnx2x
*bp
)
15368 int rc
, port
= BP_PORT(bp
);
15371 /* Reset PTP event detection rules - will be configured in the IOCTL */
15372 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_PARAM_MASK
:
15373 NIG_REG_P0_LLH_PTP_PARAM_MASK
, 0x7FF);
15374 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_RULE_MASK
:
15375 NIG_REG_P0_LLH_PTP_RULE_MASK
, 0x3FFF);
15376 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_PARAM_MASK
:
15377 NIG_REG_P0_TLLH_PTP_PARAM_MASK
, 0x7FF);
15378 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_RULE_MASK
:
15379 NIG_REG_P0_TLLH_PTP_RULE_MASK
, 0x3FFF);
15381 /* Disable PTP packets to host - will be configured in the IOCTL*/
15382 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_TO_HOST
:
15383 NIG_REG_P0_LLH_PTP_TO_HOST
, 0x0);
15385 /* Enable the PTP feature */
15386 REG_WR(bp
, port
? NIG_REG_P1_PTP_EN
:
15387 NIG_REG_P0_PTP_EN
, 0x3F);
15389 /* Enable the free-running counter */
15392 REG_WR_DMAE(bp
, NIG_REG_TIMESYNC_GEN_REG
+ tsgen_ctrl
, wb_data
, 2);
15394 /* Reset drift register (offset register is not reset) */
15395 rc
= bnx2x_send_reset_timesync_ramrod(bp
);
15397 BNX2X_ERR("Failed to reset PHC drift register\n");
15401 /* Reset possibly old timestamps */
15402 REG_WR(bp
, port
? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID
:
15403 NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID
, 0x10000);
15404 REG_WR(bp
, port
? NIG_REG_P1_TLLH_PTP_BUF_SEQID
:
15405 NIG_REG_P0_TLLH_PTP_BUF_SEQID
, 0x10000);
15410 /* Called during load, to initialize PTP-related stuff */
15411 void bnx2x_init_ptp(struct bnx2x
*bp
)
15415 /* Configure PTP in HW */
15416 rc
= bnx2x_configure_ptp(bp
);
15418 BNX2X_ERR("Stopping PTP initialization\n");
15422 /* Init work queue for Tx timestamping */
15423 INIT_WORK(&bp
->ptp_task
, bnx2x_ptp_task
);
15425 /* Init cyclecounter and timecounter. This is done only in the first
15426 * load. If done in every load, PTP application will fail when doing
15427 * unload / load (e.g. MTU change) while it is running.
15429 if (!bp
->timecounter_init_done
) {
15430 bnx2x_init_cyclecounter(bp
);
15431 timecounter_init(&bp
->timecounter
, &bp
->cyclecounter
,
15432 ktime_to_ns(ktime_get_real()));
15433 bp
->timecounter_init_done
= 1;
15436 DP(BNX2X_MSG_PTP
, "PTP initialization ended successfully\n");