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broadcom: Move the Broadcom drivers
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_sp.h
1 /* bnx2x_sp.h: Broadcom Everest network driver.
2 *
3 * Copyright 2011 Broadcom Corporation
4 *
5 * Unless you and Broadcom execute a separate written software license
6 * agreement governing use of this software, this software is licensed to you
7 * under the terms of the GNU General Public License version 2, available
8 * at http://www.gnu.org/licenses/old-licenses/gpl-2.0.html (the "GPL").
9 *
10 * Notwithstanding the above, under no circumstances may you combine this
11 * software in any way with any other Broadcom software provided under a
12 * license other than the GPL, without Broadcom's express prior written
13 * consent.
14 *
15 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
16 * Written by: Vladislav Zolotarov
17 *
18 */
19 #ifndef BNX2X_SP_VERBS
20 #define BNX2X_SP_VERBS
21
22 struct bnx2x;
23 struct eth_context;
24
25 /* Bits representing general command's configuration */
26 enum {
27 RAMROD_TX,
28 RAMROD_RX,
29 /* Wait until all pending commands complete */
30 RAMROD_COMP_WAIT,
31 /* Don't send a ramrod, only update a registry */
32 RAMROD_DRV_CLR_ONLY,
33 /* Configure HW according to the current object state */
34 RAMROD_RESTORE,
35 /* Execute the next command now */
36 RAMROD_EXEC,
37 /*
38 * Don't add a new command and continue execution of posponed
39 * commands. If not set a new command will be added to the
40 * pending commands list.
41 */
42 RAMROD_CONT,
43 };
44
45 typedef enum {
46 BNX2X_OBJ_TYPE_RX,
47 BNX2X_OBJ_TYPE_TX,
48 BNX2X_OBJ_TYPE_RX_TX,
49 } bnx2x_obj_type;
50
51 /* Filtering states */
52 enum {
53 BNX2X_FILTER_MAC_PENDING,
54 BNX2X_FILTER_VLAN_PENDING,
55 BNX2X_FILTER_VLAN_MAC_PENDING,
56 BNX2X_FILTER_RX_MODE_PENDING,
57 BNX2X_FILTER_RX_MODE_SCHED,
58 BNX2X_FILTER_ISCSI_ETH_START_SCHED,
59 BNX2X_FILTER_ISCSI_ETH_STOP_SCHED,
60 BNX2X_FILTER_FCOE_ETH_START_SCHED,
61 BNX2X_FILTER_FCOE_ETH_STOP_SCHED,
62 BNX2X_FILTER_MCAST_PENDING,
63 BNX2X_FILTER_MCAST_SCHED,
64 BNX2X_FILTER_RSS_CONF_PENDING,
65 };
66
67 struct bnx2x_raw_obj {
68 u8 func_id;
69
70 /* Queue params */
71 u8 cl_id;
72 u32 cid;
73
74 /* Ramrod data buffer params */
75 void *rdata;
76 dma_addr_t rdata_mapping;
77
78 /* Ramrod state params */
79 int state; /* "ramrod is pending" state bit */
80 unsigned long *pstate; /* pointer to state buffer */
81
82 bnx2x_obj_type obj_type;
83
84 int (*wait_comp)(struct bnx2x *bp,
85 struct bnx2x_raw_obj *o);
86
87 bool (*check_pending)(struct bnx2x_raw_obj *o);
88 void (*clear_pending)(struct bnx2x_raw_obj *o);
89 void (*set_pending)(struct bnx2x_raw_obj *o);
90 };
91
92 /************************* VLAN-MAC commands related parameters ***************/
93 struct bnx2x_mac_ramrod_data {
94 u8 mac[ETH_ALEN];
95 };
96
97 struct bnx2x_vlan_ramrod_data {
98 u16 vlan;
99 };
100
101 struct bnx2x_vlan_mac_ramrod_data {
102 u8 mac[ETH_ALEN];
103 u16 vlan;
104 };
105
106 union bnx2x_classification_ramrod_data {
107 struct bnx2x_mac_ramrod_data mac;
108 struct bnx2x_vlan_ramrod_data vlan;
109 struct bnx2x_vlan_mac_ramrod_data vlan_mac;
110 };
111
112 /* VLAN_MAC commands */
113 enum bnx2x_vlan_mac_cmd {
114 BNX2X_VLAN_MAC_ADD,
115 BNX2X_VLAN_MAC_DEL,
116 BNX2X_VLAN_MAC_MOVE,
117 };
118
119 struct bnx2x_vlan_mac_data {
120 /* Requested command: BNX2X_VLAN_MAC_XX */
121 enum bnx2x_vlan_mac_cmd cmd;
122 /*
123 * used to contain the data related vlan_mac_flags bits from
124 * ramrod parameters.
125 */
126 unsigned long vlan_mac_flags;
127
128 /* Needed for MOVE command */
129 struct bnx2x_vlan_mac_obj *target_obj;
130
131 union bnx2x_classification_ramrod_data u;
132 };
133
134 /*************************** Exe Queue obj ************************************/
135 union bnx2x_exe_queue_cmd_data {
136 struct bnx2x_vlan_mac_data vlan_mac;
137
138 struct {
139 /* TODO */
140 } mcast;
141 };
142
143 struct bnx2x_exeq_elem {
144 struct list_head link;
145
146 /* Length of this element in the exe_chunk. */
147 int cmd_len;
148
149 union bnx2x_exe_queue_cmd_data cmd_data;
150 };
151
152 union bnx2x_qable_obj;
153
154 union bnx2x_exeq_comp_elem {
155 union event_ring_elem *elem;
156 };
157
158 struct bnx2x_exe_queue_obj;
159
160 typedef int (*exe_q_validate)(struct bnx2x *bp,
161 union bnx2x_qable_obj *o,
162 struct bnx2x_exeq_elem *elem);
163
164 /**
165 * @return positive is entry was optimized, 0 - if not, negative
166 * in case of an error.
167 */
168 typedef int (*exe_q_optimize)(struct bnx2x *bp,
169 union bnx2x_qable_obj *o,
170 struct bnx2x_exeq_elem *elem);
171 typedef int (*exe_q_execute)(struct bnx2x *bp,
172 union bnx2x_qable_obj *o,
173 struct list_head *exe_chunk,
174 unsigned long *ramrod_flags);
175 typedef struct bnx2x_exeq_elem *
176 (*exe_q_get)(struct bnx2x_exe_queue_obj *o,
177 struct bnx2x_exeq_elem *elem);
178
179 struct bnx2x_exe_queue_obj {
180 /*
181 * Commands pending for an execution.
182 */
183 struct list_head exe_queue;
184
185 /*
186 * Commands pending for an completion.
187 */
188 struct list_head pending_comp;
189
190 spinlock_t lock;
191
192 /* Maximum length of commands' list for one execution */
193 int exe_chunk_len;
194
195 union bnx2x_qable_obj *owner;
196
197 /****** Virtual functions ******/
198 /**
199 * Called before commands execution for commands that are really
200 * going to be executed (after 'optimize').
201 *
202 * Must run under exe_queue->lock
203 */
204 exe_q_validate validate;
205
206
207 /**
208 * This will try to cancel the current pending commands list
209 * considering the new command.
210 *
211 * Must run under exe_queue->lock
212 */
213 exe_q_optimize optimize;
214
215 /**
216 * Run the next commands chunk (owner specific).
217 */
218 exe_q_execute execute;
219
220 /**
221 * Return the exe_queue element containing the specific command
222 * if any. Otherwise return NULL.
223 */
224 exe_q_get get;
225 };
226 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/
227 /*
228 * Element in the VLAN_MAC registry list having all currenty configured
229 * rules.
230 */
231 struct bnx2x_vlan_mac_registry_elem {
232 struct list_head link;
233
234 /*
235 * Used to store the cam offset used for the mac/vlan/vlan-mac.
236 * Relevant for 57710 and 57711 only. VLANs and MACs share the
237 * same CAM for these chips.
238 */
239 int cam_offset;
240
241 /* Needed for DEL and RESTORE flows */
242 unsigned long vlan_mac_flags;
243
244 union bnx2x_classification_ramrod_data u;
245 };
246
247 /* Bits representing VLAN_MAC commands specific flags */
248 enum {
249 BNX2X_UC_LIST_MAC,
250 BNX2X_ETH_MAC,
251 BNX2X_ISCSI_ETH_MAC,
252 BNX2X_NETQ_ETH_MAC,
253 BNX2X_DONT_CONSUME_CAM_CREDIT,
254 BNX2X_DONT_CONSUME_CAM_CREDIT_DEST,
255 };
256
257 struct bnx2x_vlan_mac_ramrod_params {
258 /* Object to run the command from */
259 struct bnx2x_vlan_mac_obj *vlan_mac_obj;
260
261 /* General command flags: COMP_WAIT, etc. */
262 unsigned long ramrod_flags;
263
264 /* Command specific configuration request */
265 struct bnx2x_vlan_mac_data user_req;
266 };
267
268 struct bnx2x_vlan_mac_obj {
269 struct bnx2x_raw_obj raw;
270
271 /* Bookkeeping list: will prevent the addition of already existing
272 * entries.
273 */
274 struct list_head head;
275
276 /* TODO: Add it's initialization in the init functions */
277 struct bnx2x_exe_queue_obj exe_queue;
278
279 /* MACs credit pool */
280 struct bnx2x_credit_pool_obj *macs_pool;
281
282 /* VLANs credit pool */
283 struct bnx2x_credit_pool_obj *vlans_pool;
284
285 /* RAMROD command to be used */
286 int ramrod_cmd;
287
288 /**
289 * Checks if ADD-ramrod with the given params may be performed.
290 *
291 * @return zero if the element may be added
292 */
293
294 int (*check_add)(struct bnx2x_vlan_mac_obj *o,
295 union bnx2x_classification_ramrod_data *data);
296
297 /**
298 * Checks if DEL-ramrod with the given params may be performed.
299 *
300 * @return true if the element may be deleted
301 */
302 struct bnx2x_vlan_mac_registry_elem *
303 (*check_del)(struct bnx2x_vlan_mac_obj *o,
304 union bnx2x_classification_ramrod_data *data);
305
306 /**
307 * Checks if DEL-ramrod with the given params may be performed.
308 *
309 * @return true if the element may be deleted
310 */
311 bool (*check_move)(struct bnx2x_vlan_mac_obj *src_o,
312 struct bnx2x_vlan_mac_obj *dst_o,
313 union bnx2x_classification_ramrod_data *data);
314
315 /**
316 * Update the relevant credit object(s) (consume/return
317 * correspondingly).
318 */
319 bool (*get_credit)(struct bnx2x_vlan_mac_obj *o);
320 bool (*put_credit)(struct bnx2x_vlan_mac_obj *o);
321 bool (*get_cam_offset)(struct bnx2x_vlan_mac_obj *o, int *offset);
322 bool (*put_cam_offset)(struct bnx2x_vlan_mac_obj *o, int offset);
323
324 /**
325 * Configures one rule in the ramrod data buffer.
326 */
327 void (*set_one_rule)(struct bnx2x *bp,
328 struct bnx2x_vlan_mac_obj *o,
329 struct bnx2x_exeq_elem *elem, int rule_idx,
330 int cam_offset);
331
332 /**
333 * Delete all configured elements having the given
334 * vlan_mac_flags specification. Assumes no pending for
335 * execution commands. Will schedule all all currently
336 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags
337 * specification for deletion and will use the given
338 * ramrod_flags for the last DEL operation.
339 *
340 * @param bp
341 * @param o
342 * @param ramrod_flags RAMROD_XX flags
343 *
344 * @return 0 if the last operation has completed successfully
345 * and there are no more elements left, positive value
346 * if there are pending for completion commands,
347 * negative value in case of failure.
348 */
349 int (*delete_all)(struct bnx2x *bp,
350 struct bnx2x_vlan_mac_obj *o,
351 unsigned long *vlan_mac_flags,
352 unsigned long *ramrod_flags);
353
354 /**
355 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously
356 * configured elements list.
357 *
358 * @param bp
359 * @param p Command parameters (RAMROD_COMP_WAIT bit in
360 * ramrod_flags is only taken into an account)
361 * @param ppos a pointer to the cooky that should be given back in the
362 * next call to make function handle the next element. If
363 * *ppos is set to NULL it will restart the iterator.
364 * If returned *ppos == NULL this means that the last
365 * element has been handled.
366 *
367 * @return int
368 */
369 int (*restore)(struct bnx2x *bp,
370 struct bnx2x_vlan_mac_ramrod_params *p,
371 struct bnx2x_vlan_mac_registry_elem **ppos);
372
373 /**
374 * Should be called on a completion arival.
375 *
376 * @param bp
377 * @param o
378 * @param cqe Completion element we are handling
379 * @param ramrod_flags if RAMROD_CONT is set the next bulk of
380 * pending commands will be executed.
381 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE
382 * may also be set if needed.
383 *
384 * @return 0 if there are neither pending nor waiting for
385 * completion commands. Positive value if there are
386 * pending for execution or for completion commands.
387 * Negative value in case of an error (including an
388 * error in the cqe).
389 */
390 int (*complete)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o,
391 union event_ring_elem *cqe,
392 unsigned long *ramrod_flags);
393
394 /**
395 * Wait for completion of all commands. Don't schedule new ones,
396 * just wait. It assumes that the completion code will schedule
397 * for new commands.
398 */
399 int (*wait)(struct bnx2x *bp, struct bnx2x_vlan_mac_obj *o);
400 };
401
402 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */
403
404 /* RX_MODE ramrod spesial flags: set in rx_mode_flags field in
405 * a bnx2x_rx_mode_ramrod_params.
406 */
407 enum {
408 BNX2X_RX_MODE_FCOE_ETH,
409 BNX2X_RX_MODE_ISCSI_ETH,
410 };
411
412 enum {
413 BNX2X_ACCEPT_UNICAST,
414 BNX2X_ACCEPT_MULTICAST,
415 BNX2X_ACCEPT_ALL_UNICAST,
416 BNX2X_ACCEPT_ALL_MULTICAST,
417 BNX2X_ACCEPT_BROADCAST,
418 BNX2X_ACCEPT_UNMATCHED,
419 BNX2X_ACCEPT_ANY_VLAN
420 };
421
422 struct bnx2x_rx_mode_ramrod_params {
423 struct bnx2x_rx_mode_obj *rx_mode_obj;
424 unsigned long *pstate;
425 int state;
426 u8 cl_id;
427 u32 cid;
428 u8 func_id;
429 unsigned long ramrod_flags;
430 unsigned long rx_mode_flags;
431
432 /*
433 * rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to
434 * a tstorm_eth_mac_filter_config (e1x).
435 */
436 void *rdata;
437 dma_addr_t rdata_mapping;
438
439 /* Rx mode settings */
440 unsigned long rx_accept_flags;
441
442 /* internal switching settings */
443 unsigned long tx_accept_flags;
444 };
445
446 struct bnx2x_rx_mode_obj {
447 int (*config_rx_mode)(struct bnx2x *bp,
448 struct bnx2x_rx_mode_ramrod_params *p);
449
450 int (*wait_comp)(struct bnx2x *bp,
451 struct bnx2x_rx_mode_ramrod_params *p);
452 };
453
454 /********************** Set multicast group ***********************************/
455
456 struct bnx2x_mcast_list_elem {
457 struct list_head link;
458 u8 *mac;
459 };
460
461 union bnx2x_mcast_config_data {
462 u8 *mac;
463 u8 bin; /* used in a RESTORE flow */
464 };
465
466 struct bnx2x_mcast_ramrod_params {
467 struct bnx2x_mcast_obj *mcast_obj;
468
469 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */
470 unsigned long ramrod_flags;
471
472 struct list_head mcast_list; /* list of struct bnx2x_mcast_list_elem */
473 /** TODO:
474 * - rename it to macs_num.
475 * - Add a new command type for handling pending commands
476 * (remove "zero semantics").
477 *
478 * Length of mcast_list. If zero and ADD_CONT command - post
479 * pending commands.
480 */
481 int mcast_list_len;
482 };
483
484 enum {
485 BNX2X_MCAST_CMD_ADD,
486 BNX2X_MCAST_CMD_CONT,
487 BNX2X_MCAST_CMD_DEL,
488 BNX2X_MCAST_CMD_RESTORE,
489 };
490
491 struct bnx2x_mcast_obj {
492 struct bnx2x_raw_obj raw;
493
494 union {
495 struct {
496 #define BNX2X_MCAST_BINS_NUM 256
497 #define BNX2X_MCAST_VEC_SZ (BNX2X_MCAST_BINS_NUM / 64)
498 u64 vec[BNX2X_MCAST_VEC_SZ];
499
500 /** Number of BINs to clear. Should be updated
501 * immediately when a command arrives in order to
502 * properly create DEL commands.
503 */
504 int num_bins_set;
505 } aprox_match;
506
507 struct {
508 struct list_head macs;
509 int num_macs_set;
510 } exact_match;
511 } registry;
512
513 /* Pending commands */
514 struct list_head pending_cmds_head;
515
516 /* A state that is set in raw.pstate, when there are pending commands */
517 int sched_state;
518
519 /* Maximal number of mcast MACs configured in one command */
520 int max_cmd_len;
521
522 /* Total number of currently pending MACs to configure: both
523 * in the pending commands list and in the current command.
524 */
525 int total_pending_num;
526
527 u8 engine_id;
528
529 /**
530 * @param cmd command to execute (BNX2X_MCAST_CMD_X, see above)
531 */
532 int (*config_mcast)(struct bnx2x *bp,
533 struct bnx2x_mcast_ramrod_params *p, int cmd);
534
535 /**
536 * Fills the ramrod data during the RESTORE flow.
537 *
538 * @param bp
539 * @param o
540 * @param start_idx Registry index to start from
541 * @param rdata_idx Index in the ramrod data to start from
542 *
543 * @return -1 if we handled the whole registry or index of the last
544 * handled registry element.
545 */
546 int (*hdl_restore)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
547 int start_bin, int *rdata_idx);
548
549 int (*enqueue_cmd)(struct bnx2x *bp, struct bnx2x_mcast_obj *o,
550 struct bnx2x_mcast_ramrod_params *p, int cmd);
551
552 void (*set_one_rule)(struct bnx2x *bp,
553 struct bnx2x_mcast_obj *o, int idx,
554 union bnx2x_mcast_config_data *cfg_data, int cmd);
555
556 /** Checks if there are more mcast MACs to be set or a previous
557 * command is still pending.
558 */
559 bool (*check_pending)(struct bnx2x_mcast_obj *o);
560
561 /**
562 * Set/Clear/Check SCHEDULED state of the object
563 */
564 void (*set_sched)(struct bnx2x_mcast_obj *o);
565 void (*clear_sched)(struct bnx2x_mcast_obj *o);
566 bool (*check_sched)(struct bnx2x_mcast_obj *o);
567
568 /* Wait until all pending commands complete */
569 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_mcast_obj *o);
570
571 /**
572 * Handle the internal object counters needed for proper
573 * commands handling. Checks that the provided parameters are
574 * feasible.
575 */
576 int (*validate)(struct bnx2x *bp,
577 struct bnx2x_mcast_ramrod_params *p, int cmd);
578
579 /**
580 * Restore the values of internal counters in case of a failure.
581 */
582 void (*revert)(struct bnx2x *bp,
583 struct bnx2x_mcast_ramrod_params *p,
584 int old_num_bins);
585
586 int (*get_registry_size)(struct bnx2x_mcast_obj *o);
587 void (*set_registry_size)(struct bnx2x_mcast_obj *o, int n);
588 };
589
590 /*************************** Credit handling **********************************/
591 struct bnx2x_credit_pool_obj {
592
593 /* Current amount of credit in the pool */
594 atomic_t credit;
595
596 /* Maximum allowed credit. put() will check against it. */
597 int pool_sz;
598
599 /*
600 * Allocate a pool table statically.
601 *
602 * Currently the mamimum allowed size is MAX_MAC_CREDIT_E2(272)
603 *
604 * The set bit in the table will mean that the entry is available.
605 */
606 #define BNX2X_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64)
607 u64 pool_mirror[BNX2X_POOL_VEC_SIZE];
608
609 /* Base pool offset (initialized differently */
610 int base_pool_offset;
611
612 /**
613 * Get the next free pool entry.
614 *
615 * @return true if there was a free entry in the pool
616 */
617 bool (*get_entry)(struct bnx2x_credit_pool_obj *o, int *entry);
618
619 /**
620 * Return the entry back to the pool.
621 *
622 * @return true if entry is legal and has been successfully
623 * returned to the pool.
624 */
625 bool (*put_entry)(struct bnx2x_credit_pool_obj *o, int entry);
626
627 /**
628 * Get the requested amount of credit from the pool.
629 *
630 * @param cnt Amount of requested credit
631 * @return true if the operation is successful
632 */
633 bool (*get)(struct bnx2x_credit_pool_obj *o, int cnt);
634
635 /**
636 * Returns the credit to the pool.
637 *
638 * @param cnt Amount of credit to return
639 * @return true if the operation is successful
640 */
641 bool (*put)(struct bnx2x_credit_pool_obj *o, int cnt);
642
643 /**
644 * Reads the current amount of credit.
645 */
646 int (*check)(struct bnx2x_credit_pool_obj *o);
647 };
648
649 /*************************** RSS configuration ********************************/
650 enum {
651 /* RSS_MODE bits are mutually exclusive */
652 BNX2X_RSS_MODE_DISABLED,
653 BNX2X_RSS_MODE_REGULAR,
654 BNX2X_RSS_MODE_VLAN_PRI,
655 BNX2X_RSS_MODE_E1HOV_PRI,
656 BNX2X_RSS_MODE_IP_DSCP,
657
658 BNX2X_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */
659
660 BNX2X_RSS_IPV4,
661 BNX2X_RSS_IPV4_TCP,
662 BNX2X_RSS_IPV6,
663 BNX2X_RSS_IPV6_TCP,
664 };
665
666 struct bnx2x_config_rss_params {
667 struct bnx2x_rss_config_obj *rss_obj;
668
669 /* may have RAMROD_COMP_WAIT set only */
670 unsigned long ramrod_flags;
671
672 /* BNX2X_RSS_X bits */
673 unsigned long rss_flags;
674
675 /* Number hash bits to take into an account */
676 u8 rss_result_mask;
677
678 /* Indirection table */
679 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
680
681 /* RSS hash values */
682 u32 rss_key[10];
683
684 /* valid only iff BNX2X_RSS_UPDATE_TOE is set */
685 u16 toe_rss_bitmap;
686 };
687
688 struct bnx2x_rss_config_obj {
689 struct bnx2x_raw_obj raw;
690
691 /* RSS engine to use */
692 u8 engine_id;
693
694 /* Last configured indirection table */
695 u8 ind_table[T_ETH_INDIRECTION_TABLE_SIZE];
696
697 int (*config_rss)(struct bnx2x *bp,
698 struct bnx2x_config_rss_params *p);
699 };
700
701 /*********************** Queue state update ***********************************/
702
703 /* UPDATE command options */
704 enum {
705 BNX2X_Q_UPDATE_IN_VLAN_REM,
706 BNX2X_Q_UPDATE_IN_VLAN_REM_CHNG,
707 BNX2X_Q_UPDATE_OUT_VLAN_REM,
708 BNX2X_Q_UPDATE_OUT_VLAN_REM_CHNG,
709 BNX2X_Q_UPDATE_ANTI_SPOOF,
710 BNX2X_Q_UPDATE_ANTI_SPOOF_CHNG,
711 BNX2X_Q_UPDATE_ACTIVATE,
712 BNX2X_Q_UPDATE_ACTIVATE_CHNG,
713 BNX2X_Q_UPDATE_DEF_VLAN_EN,
714 BNX2X_Q_UPDATE_DEF_VLAN_EN_CHNG,
715 BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
716 BNX2X_Q_UPDATE_SILENT_VLAN_REM
717 };
718
719 /* Allowed Queue states */
720 enum bnx2x_q_state {
721 BNX2X_Q_STATE_RESET,
722 BNX2X_Q_STATE_INITIALIZED,
723 BNX2X_Q_STATE_ACTIVE,
724 BNX2X_Q_STATE_MULTI_COS,
725 BNX2X_Q_STATE_MCOS_TERMINATED,
726 BNX2X_Q_STATE_INACTIVE,
727 BNX2X_Q_STATE_STOPPED,
728 BNX2X_Q_STATE_TERMINATED,
729 BNX2X_Q_STATE_FLRED,
730 BNX2X_Q_STATE_MAX,
731 };
732
733 /* Allowed commands */
734 enum bnx2x_queue_cmd {
735 BNX2X_Q_CMD_INIT,
736 BNX2X_Q_CMD_SETUP,
737 BNX2X_Q_CMD_SETUP_TX_ONLY,
738 BNX2X_Q_CMD_DEACTIVATE,
739 BNX2X_Q_CMD_ACTIVATE,
740 BNX2X_Q_CMD_UPDATE,
741 BNX2X_Q_CMD_UPDATE_TPA,
742 BNX2X_Q_CMD_HALT,
743 BNX2X_Q_CMD_CFC_DEL,
744 BNX2X_Q_CMD_TERMINATE,
745 BNX2X_Q_CMD_EMPTY,
746 BNX2X_Q_CMD_MAX,
747 };
748
749 /* queue SETUP + INIT flags */
750 enum {
751 BNX2X_Q_FLG_TPA,
752 BNX2X_Q_FLG_TPA_IPV6,
753 BNX2X_Q_FLG_STATS,
754 BNX2X_Q_FLG_ZERO_STATS,
755 BNX2X_Q_FLG_ACTIVE,
756 BNX2X_Q_FLG_OV,
757 BNX2X_Q_FLG_VLAN,
758 BNX2X_Q_FLG_COS,
759 BNX2X_Q_FLG_HC,
760 BNX2X_Q_FLG_HC_EN,
761 BNX2X_Q_FLG_DHC,
762 BNX2X_Q_FLG_FCOE,
763 BNX2X_Q_FLG_LEADING_RSS,
764 BNX2X_Q_FLG_MCAST,
765 BNX2X_Q_FLG_DEF_VLAN,
766 BNX2X_Q_FLG_TX_SWITCH,
767 BNX2X_Q_FLG_TX_SEC,
768 BNX2X_Q_FLG_ANTI_SPOOF,
769 BNX2X_Q_FLG_SILENT_VLAN_REM
770 };
771
772 /* Queue type options: queue type may be a compination of below. */
773 enum bnx2x_q_type {
774 /** TODO: Consider moving both these flags into the init()
775 * ramrod params.
776 */
777 BNX2X_Q_TYPE_HAS_RX,
778 BNX2X_Q_TYPE_HAS_TX,
779 };
780
781 #define BNX2X_PRIMARY_CID_INDEX 0
782 #define BNX2X_MULTI_TX_COS_E1X 1
783 #define BNX2X_MULTI_TX_COS_E2_E3A0 2
784 #define BNX2X_MULTI_TX_COS_E3B0 3
785 #define BNX2X_MULTI_TX_COS BNX2X_MULTI_TX_COS_E3B0
786
787
788 struct bnx2x_queue_init_params {
789 struct {
790 unsigned long flags;
791 u16 hc_rate;
792 u8 fw_sb_id;
793 u8 sb_cq_index;
794 } tx;
795
796 struct {
797 unsigned long flags;
798 u16 hc_rate;
799 u8 fw_sb_id;
800 u8 sb_cq_index;
801 } rx;
802
803 /* CID context in the host memory */
804 struct eth_context *cxts[BNX2X_MULTI_TX_COS];
805
806 /* maximum number of cos supported by hardware */
807 u8 max_cos;
808 };
809
810 struct bnx2x_queue_terminate_params {
811 /* index within the tx_only cids of this queue object */
812 u8 cid_index;
813 };
814
815 struct bnx2x_queue_cfc_del_params {
816 /* index within the tx_only cids of this queue object */
817 u8 cid_index;
818 };
819
820 struct bnx2x_queue_update_params {
821 unsigned long update_flags; /* BNX2X_Q_UPDATE_XX bits */
822 u16 def_vlan;
823 u16 silent_removal_value;
824 u16 silent_removal_mask;
825 /* index within the tx_only cids of this queue object */
826 u8 cid_index;
827 };
828
829 struct rxq_pause_params {
830 u16 bd_th_lo;
831 u16 bd_th_hi;
832 u16 rcq_th_lo;
833 u16 rcq_th_hi;
834 u16 sge_th_lo; /* valid iff BNX2X_Q_FLG_TPA */
835 u16 sge_th_hi; /* valid iff BNX2X_Q_FLG_TPA */
836 u16 pri_map;
837 };
838
839 /* general */
840 struct bnx2x_general_setup_params {
841 /* valid iff BNX2X_Q_FLG_STATS */
842 u8 stat_id;
843
844 u8 spcl_id;
845 u16 mtu;
846 u8 cos;
847 };
848
849 struct bnx2x_rxq_setup_params {
850 /* dma */
851 dma_addr_t dscr_map;
852 dma_addr_t sge_map;
853 dma_addr_t rcq_map;
854 dma_addr_t rcq_np_map;
855
856 u16 drop_flags;
857 u16 buf_sz;
858 u8 fw_sb_id;
859 u8 cl_qzone_id;
860
861 /* valid iff BNX2X_Q_FLG_TPA */
862 u16 tpa_agg_sz;
863 u16 sge_buf_sz;
864 u8 max_sges_pkt;
865 u8 max_tpa_queues;
866 u8 rss_engine_id;
867
868 u8 cache_line_log;
869
870 u8 sb_cq_index;
871
872 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */
873 u16 silent_removal_value;
874 u16 silent_removal_mask;
875 };
876
877 struct bnx2x_txq_setup_params {
878 /* dma */
879 dma_addr_t dscr_map;
880
881 u8 fw_sb_id;
882 u8 sb_cq_index;
883 u8 cos; /* valid iff BNX2X_Q_FLG_COS */
884 u16 traffic_type;
885 /* equals to the leading rss client id, used for TX classification*/
886 u8 tss_leading_cl_id;
887
888 /* valid iff BNX2X_Q_FLG_DEF_VLAN */
889 u16 default_vlan;
890 };
891
892 struct bnx2x_queue_setup_params {
893 struct bnx2x_general_setup_params gen_params;
894 struct bnx2x_txq_setup_params txq_params;
895 struct bnx2x_rxq_setup_params rxq_params;
896 struct rxq_pause_params pause_params;
897 unsigned long flags;
898 };
899
900 struct bnx2x_queue_setup_tx_only_params {
901 struct bnx2x_general_setup_params gen_params;
902 struct bnx2x_txq_setup_params txq_params;
903 unsigned long flags;
904 /* index within the tx_only cids of this queue object */
905 u8 cid_index;
906 };
907
908 struct bnx2x_queue_state_params {
909 struct bnx2x_queue_sp_obj *q_obj;
910
911 /* Current command */
912 enum bnx2x_queue_cmd cmd;
913
914 /* may have RAMROD_COMP_WAIT set only */
915 unsigned long ramrod_flags;
916
917 /* Params according to the current command */
918 union {
919 struct bnx2x_queue_update_params update;
920 struct bnx2x_queue_setup_params setup;
921 struct bnx2x_queue_init_params init;
922 struct bnx2x_queue_setup_tx_only_params tx_only;
923 struct bnx2x_queue_terminate_params terminate;
924 struct bnx2x_queue_cfc_del_params cfc_del;
925 } params;
926 };
927
928 struct bnx2x_queue_sp_obj {
929 u32 cids[BNX2X_MULTI_TX_COS];
930 u8 cl_id;
931 u8 func_id;
932
933 /*
934 * number of traffic classes supported by queue.
935 * The primary connection of the queue suppotrs the first traffic
936 * class. Any further traffic class is suppoted by a tx-only
937 * connection.
938 *
939 * Therefore max_cos is also a number of valid entries in the cids
940 * array.
941 */
942 u8 max_cos;
943 u8 num_tx_only, next_tx_only;
944
945 enum bnx2x_q_state state, next_state;
946
947 /* bits from enum bnx2x_q_type */
948 unsigned long type;
949
950 /* BNX2X_Q_CMD_XX bits. This object implements "one
951 * pending" paradigm but for debug and tracing purposes it's
952 * more convinient to have different bits for different
953 * commands.
954 */
955 unsigned long pending;
956
957 /* Buffer to use as a ramrod data and its mapping */
958 void *rdata;
959 dma_addr_t rdata_mapping;
960
961 /**
962 * Performs one state change according to the given parameters.
963 *
964 * @return 0 in case of success and negative value otherwise.
965 */
966 int (*send_cmd)(struct bnx2x *bp,
967 struct bnx2x_queue_state_params *params);
968
969 /**
970 * Sets the pending bit according to the requested transition.
971 */
972 int (*set_pending)(struct bnx2x_queue_sp_obj *o,
973 struct bnx2x_queue_state_params *params);
974
975 /**
976 * Checks that the requested state transition is legal.
977 */
978 int (*check_transition)(struct bnx2x *bp,
979 struct bnx2x_queue_sp_obj *o,
980 struct bnx2x_queue_state_params *params);
981
982 /**
983 * Completes the pending command.
984 */
985 int (*complete_cmd)(struct bnx2x *bp,
986 struct bnx2x_queue_sp_obj *o,
987 enum bnx2x_queue_cmd);
988
989 int (*wait_comp)(struct bnx2x *bp,
990 struct bnx2x_queue_sp_obj *o,
991 enum bnx2x_queue_cmd cmd);
992 };
993
994 /********************** Function state update *********************************/
995 /* Allowed Function states */
996 enum bnx2x_func_state {
997 BNX2X_F_STATE_RESET,
998 BNX2X_F_STATE_INITIALIZED,
999 BNX2X_F_STATE_STARTED,
1000 BNX2X_F_STATE_TX_STOPPED,
1001 BNX2X_F_STATE_MAX,
1002 };
1003
1004 /* Allowed Function commands */
1005 enum bnx2x_func_cmd {
1006 BNX2X_F_CMD_HW_INIT,
1007 BNX2X_F_CMD_START,
1008 BNX2X_F_CMD_STOP,
1009 BNX2X_F_CMD_HW_RESET,
1010 BNX2X_F_CMD_TX_STOP,
1011 BNX2X_F_CMD_TX_START,
1012 BNX2X_F_CMD_MAX,
1013 };
1014
1015 struct bnx2x_func_hw_init_params {
1016 /* A load phase returned by MCP.
1017 *
1018 * May be:
1019 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1020 * FW_MSG_CODE_DRV_LOAD_COMMON
1021 * FW_MSG_CODE_DRV_LOAD_PORT
1022 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1023 */
1024 u32 load_phase;
1025 };
1026
1027 struct bnx2x_func_hw_reset_params {
1028 /* A load phase returned by MCP.
1029 *
1030 * May be:
1031 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP
1032 * FW_MSG_CODE_DRV_LOAD_COMMON
1033 * FW_MSG_CODE_DRV_LOAD_PORT
1034 * FW_MSG_CODE_DRV_LOAD_FUNCTION
1035 */
1036 u32 reset_phase;
1037 };
1038
1039 struct bnx2x_func_start_params {
1040 /* Multi Function mode:
1041 * - Single Function
1042 * - Switch Dependent
1043 * - Switch Independent
1044 */
1045 u16 mf_mode;
1046
1047 /* Switch Dependent mode outer VLAN tag */
1048 u16 sd_vlan_tag;
1049
1050 /* Function cos mode */
1051 u8 network_cos_mode;
1052 };
1053
1054 struct bnx2x_func_tx_start_params {
1055 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
1056 u8 dcb_enabled;
1057 u8 dcb_version;
1058 u8 dont_add_pri_0_en;
1059 };
1060
1061 struct bnx2x_func_state_params {
1062 struct bnx2x_func_sp_obj *f_obj;
1063
1064 /* Current command */
1065 enum bnx2x_func_cmd cmd;
1066
1067 /* may have RAMROD_COMP_WAIT set only */
1068 unsigned long ramrod_flags;
1069
1070 /* Params according to the current command */
1071 union {
1072 struct bnx2x_func_hw_init_params hw_init;
1073 struct bnx2x_func_hw_reset_params hw_reset;
1074 struct bnx2x_func_start_params start;
1075 struct bnx2x_func_tx_start_params tx_start;
1076 } params;
1077 };
1078
1079 struct bnx2x_func_sp_drv_ops {
1080 /* Init tool + runtime initialization:
1081 * - Common Chip
1082 * - Common (per Path)
1083 * - Port
1084 * - Function phases
1085 */
1086 int (*init_hw_cmn_chip)(struct bnx2x *bp);
1087 int (*init_hw_cmn)(struct bnx2x *bp);
1088 int (*init_hw_port)(struct bnx2x *bp);
1089 int (*init_hw_func)(struct bnx2x *bp);
1090
1091 /* Reset Function HW: Common, Port, Function phases. */
1092 void (*reset_hw_cmn)(struct bnx2x *bp);
1093 void (*reset_hw_port)(struct bnx2x *bp);
1094 void (*reset_hw_func)(struct bnx2x *bp);
1095
1096 /* Init/Free GUNZIP resources */
1097 int (*gunzip_init)(struct bnx2x *bp);
1098 void (*gunzip_end)(struct bnx2x *bp);
1099
1100 /* Prepare/Release FW resources */
1101 int (*init_fw)(struct bnx2x *bp);
1102 void (*release_fw)(struct bnx2x *bp);
1103 };
1104
1105 struct bnx2x_func_sp_obj {
1106 enum bnx2x_func_state state, next_state;
1107
1108 /* BNX2X_FUNC_CMD_XX bits. This object implements "one
1109 * pending" paradigm but for debug and tracing purposes it's
1110 * more convinient to have different bits for different
1111 * commands.
1112 */
1113 unsigned long pending;
1114
1115 /* Buffer to use as a ramrod data and its mapping */
1116 void *rdata;
1117 dma_addr_t rdata_mapping;
1118
1119 /* this mutex validates that when pending flag is taken, the next
1120 * ramrod to be sent will be the one set the pending bit
1121 */
1122 struct mutex one_pending_mutex;
1123
1124 /* Driver interface */
1125 struct bnx2x_func_sp_drv_ops *drv;
1126
1127 /**
1128 * Performs one state change according to the given parameters.
1129 *
1130 * @return 0 in case of success and negative value otherwise.
1131 */
1132 int (*send_cmd)(struct bnx2x *bp,
1133 struct bnx2x_func_state_params *params);
1134
1135 /**
1136 * Checks that the requested state transition is legal.
1137 */
1138 int (*check_transition)(struct bnx2x *bp,
1139 struct bnx2x_func_sp_obj *o,
1140 struct bnx2x_func_state_params *params);
1141
1142 /**
1143 * Completes the pending command.
1144 */
1145 int (*complete_cmd)(struct bnx2x *bp,
1146 struct bnx2x_func_sp_obj *o,
1147 enum bnx2x_func_cmd cmd);
1148
1149 int (*wait_comp)(struct bnx2x *bp, struct bnx2x_func_sp_obj *o,
1150 enum bnx2x_func_cmd cmd);
1151 };
1152
1153 /********************** Interfaces ********************************************/
1154 /* Queueable objects set */
1155 union bnx2x_qable_obj {
1156 struct bnx2x_vlan_mac_obj vlan_mac;
1157 };
1158 /************** Function state update *********/
1159 void bnx2x_init_func_obj(struct bnx2x *bp,
1160 struct bnx2x_func_sp_obj *obj,
1161 void *rdata, dma_addr_t rdata_mapping,
1162 struct bnx2x_func_sp_drv_ops *drv_iface);
1163
1164 int bnx2x_func_state_change(struct bnx2x *bp,
1165 struct bnx2x_func_state_params *params);
1166
1167 enum bnx2x_func_state bnx2x_func_get_state(struct bnx2x *bp,
1168 struct bnx2x_func_sp_obj *o);
1169 /******************* Queue State **************/
1170 void bnx2x_init_queue_obj(struct bnx2x *bp,
1171 struct bnx2x_queue_sp_obj *obj, u8 cl_id, u32 *cids,
1172 u8 cid_cnt, u8 func_id, void *rdata,
1173 dma_addr_t rdata_mapping, unsigned long type);
1174
1175 int bnx2x_queue_state_change(struct bnx2x *bp,
1176 struct bnx2x_queue_state_params *params);
1177
1178 /********************* VLAN-MAC ****************/
1179 void bnx2x_init_mac_obj(struct bnx2x *bp,
1180 struct bnx2x_vlan_mac_obj *mac_obj,
1181 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1182 dma_addr_t rdata_mapping, int state,
1183 unsigned long *pstate, bnx2x_obj_type type,
1184 struct bnx2x_credit_pool_obj *macs_pool);
1185
1186 void bnx2x_init_vlan_obj(struct bnx2x *bp,
1187 struct bnx2x_vlan_mac_obj *vlan_obj,
1188 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1189 dma_addr_t rdata_mapping, int state,
1190 unsigned long *pstate, bnx2x_obj_type type,
1191 struct bnx2x_credit_pool_obj *vlans_pool);
1192
1193 void bnx2x_init_vlan_mac_obj(struct bnx2x *bp,
1194 struct bnx2x_vlan_mac_obj *vlan_mac_obj,
1195 u8 cl_id, u32 cid, u8 func_id, void *rdata,
1196 dma_addr_t rdata_mapping, int state,
1197 unsigned long *pstate, bnx2x_obj_type type,
1198 struct bnx2x_credit_pool_obj *macs_pool,
1199 struct bnx2x_credit_pool_obj *vlans_pool);
1200
1201 int bnx2x_config_vlan_mac(struct bnx2x *bp,
1202 struct bnx2x_vlan_mac_ramrod_params *p);
1203
1204 int bnx2x_vlan_mac_move(struct bnx2x *bp,
1205 struct bnx2x_vlan_mac_ramrod_params *p,
1206 struct bnx2x_vlan_mac_obj *dest_o);
1207
1208 /********************* RX MODE ****************/
1209
1210 void bnx2x_init_rx_mode_obj(struct bnx2x *bp,
1211 struct bnx2x_rx_mode_obj *o);
1212
1213 /**
1214 * Send and RX_MODE ramrod according to the provided parameters.
1215 *
1216 * @param bp
1217 * @param p Command parameters
1218 *
1219 * @return 0 - if operation was successfull and there is no pending completions,
1220 * positive number - if there are pending completions,
1221 * negative - if there were errors
1222 */
1223 int bnx2x_config_rx_mode(struct bnx2x *bp,
1224 struct bnx2x_rx_mode_ramrod_params *p);
1225
1226 /****************** MULTICASTS ****************/
1227
1228 void bnx2x_init_mcast_obj(struct bnx2x *bp,
1229 struct bnx2x_mcast_obj *mcast_obj,
1230 u8 mcast_cl_id, u32 mcast_cid, u8 func_id,
1231 u8 engine_id, void *rdata, dma_addr_t rdata_mapping,
1232 int state, unsigned long *pstate,
1233 bnx2x_obj_type type);
1234
1235 /**
1236 * Configure multicast MACs list. May configure a new list
1237 * provided in p->mcast_list (BNX2X_MCAST_CMD_ADD), clean up
1238 * (BNX2X_MCAST_CMD_DEL) or restore (BNX2X_MCAST_CMD_RESTORE) a current
1239 * configuration, continue to execute the pending commands
1240 * (BNX2X_MCAST_CMD_CONT).
1241 *
1242 * If previous command is still pending or if number of MACs to
1243 * configure is more that maximum number of MACs in one command,
1244 * the current command will be enqueued to the tail of the
1245 * pending commands list.
1246 *
1247 * @param bp
1248 * @param p
1249 * @param command to execute: BNX2X_MCAST_CMD_X
1250 *
1251 * @return 0 is operation was sucessfull and there are no pending completions,
1252 * negative if there were errors, positive if there are pending
1253 * completions.
1254 */
1255 int bnx2x_config_mcast(struct bnx2x *bp,
1256 struct bnx2x_mcast_ramrod_params *p, int cmd);
1257
1258 /****************** CREDIT POOL ****************/
1259 void bnx2x_init_mac_credit_pool(struct bnx2x *bp,
1260 struct bnx2x_credit_pool_obj *p, u8 func_id,
1261 u8 func_num);
1262 void bnx2x_init_vlan_credit_pool(struct bnx2x *bp,
1263 struct bnx2x_credit_pool_obj *p, u8 func_id,
1264 u8 func_num);
1265
1266
1267 /****************** RSS CONFIGURATION ****************/
1268 void bnx2x_init_rss_config_obj(struct bnx2x *bp,
1269 struct bnx2x_rss_config_obj *rss_obj,
1270 u8 cl_id, u32 cid, u8 func_id, u8 engine_id,
1271 void *rdata, dma_addr_t rdata_mapping,
1272 int state, unsigned long *pstate,
1273 bnx2x_obj_type type);
1274
1275 /**
1276 * Updates RSS configuration according to provided parameters.
1277 *
1278 * @param bp
1279 * @param p
1280 *
1281 * @return 0 in case of success
1282 */
1283 int bnx2x_config_rss(struct bnx2x *bp,
1284 struct bnx2x_config_rss_params *p);
1285
1286 /**
1287 * Return the current ind_table configuration.
1288 *
1289 * @param bp
1290 * @param ind_table buffer to fill with the current indirection
1291 * table content. Should be at least
1292 * T_ETH_INDIRECTION_TABLE_SIZE bytes long.
1293 */
1294 void bnx2x_get_rss_ind_table(struct bnx2x_rss_config_obj *rss_obj,
1295 u8 *ind_table);
1296
1297 #endif /* BNX2X_SP_VERBS */
Linux kernel - Deliverables
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