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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
[deliverable/linux.git] / drivers / net / ethernet / broadcom / bnx2x / bnx2x_stats.c
1 /* bnx2x_stats.c: Broadcom Everest network driver.
2 *
3 * Copyright (c) 2007-2012 Broadcom Corporation
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
8 *
9 * Maintained by: Eilon Greenstein <eilong@broadcom.com>
10 * Written by: Eliezer Tamir
11 * Based on code from Michael Chan's bnx2 driver
12 * UDP CSUM errata workaround by Arik Gendelman
13 * Slowpath and fastpath rework by Vladislav Zolotarov
14 * Statistics and Link management by Yitchak Gertner
15 *
16 */
17
18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20 #include "bnx2x_stats.h"
21 #include "bnx2x_cmn.h"
22
23
24 /* Statistics */
25
26 /*
27 * General service functions
28 */
29
30 static inline long bnx2x_hilo(u32 *hiref)
31 {
32 u32 lo = *(hiref + 1);
33 #if (BITS_PER_LONG == 64)
34 u32 hi = *hiref;
35
36 return HILO_U64(hi, lo);
37 #else
38 return lo;
39 #endif
40 }
41
42 static u16 bnx2x_get_port_stats_dma_len(struct bnx2x *bp)
43 {
44 u16 res = sizeof(struct host_port_stats) >> 2;
45
46 /* if PFC stats are not supported by the MFW, don't DMA them */
47 if (!(bp->flags & BC_SUPPORTS_PFC_STATS))
48 res -= (sizeof(u32)*4) >> 2;
49
50 return res;
51 }
52
53 /*
54 * Init service functions
55 */
56
57 /* Post the next statistics ramrod. Protect it with the spin in
58 * order to ensure the strict order between statistics ramrods
59 * (each ramrod has a sequence number passed in a
60 * bp->fw_stats_req->hdr.drv_stats_counter and ramrods must be
61 * sent in order).
62 */
63 static void bnx2x_storm_stats_post(struct bnx2x *bp)
64 {
65 if (!bp->stats_pending) {
66 int rc;
67
68 spin_lock_bh(&bp->stats_lock);
69
70 if (bp->stats_pending) {
71 spin_unlock_bh(&bp->stats_lock);
72 return;
73 }
74
75 bp->fw_stats_req->hdr.drv_stats_counter =
76 cpu_to_le16(bp->stats_counter++);
77
78 DP(NETIF_MSG_TIMER, "Sending statistics ramrod %d\n",
79 bp->fw_stats_req->hdr.drv_stats_counter);
80
81
82
83 /* send FW stats ramrod */
84 rc = bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_STAT_QUERY, 0,
85 U64_HI(bp->fw_stats_req_mapping),
86 U64_LO(bp->fw_stats_req_mapping),
87 NONE_CONNECTION_TYPE);
88 if (rc == 0)
89 bp->stats_pending = 1;
90
91 spin_unlock_bh(&bp->stats_lock);
92 }
93 }
94
95 static void bnx2x_hw_stats_post(struct bnx2x *bp)
96 {
97 struct dmae_command *dmae = &bp->stats_dmae;
98 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
99
100 *stats_comp = DMAE_COMP_VAL;
101 if (CHIP_REV_IS_SLOW(bp))
102 return;
103
104 /* loader */
105 if (bp->executer_idx) {
106 int loader_idx = PMF_DMAE_C(bp);
107 u32 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
108 true, DMAE_COMP_GRC);
109 opcode = bnx2x_dmae_opcode_clr_src_reset(opcode);
110
111 memset(dmae, 0, sizeof(struct dmae_command));
112 dmae->opcode = opcode;
113 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, dmae[0]));
114 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, dmae[0]));
115 dmae->dst_addr_lo = (DMAE_REG_CMD_MEM +
116 sizeof(struct dmae_command) *
117 (loader_idx + 1)) >> 2;
118 dmae->dst_addr_hi = 0;
119 dmae->len = sizeof(struct dmae_command) >> 2;
120 if (CHIP_IS_E1(bp))
121 dmae->len--;
122 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx + 1] >> 2;
123 dmae->comp_addr_hi = 0;
124 dmae->comp_val = 1;
125
126 *stats_comp = 0;
127 bnx2x_post_dmae(bp, dmae, loader_idx);
128
129 } else if (bp->func_stx) {
130 *stats_comp = 0;
131 bnx2x_post_dmae(bp, dmae, INIT_DMAE_C(bp));
132 }
133 }
134
135 static int bnx2x_stats_comp(struct bnx2x *bp)
136 {
137 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
138 int cnt = 10;
139
140 might_sleep();
141 while (*stats_comp != DMAE_COMP_VAL) {
142 if (!cnt) {
143 BNX2X_ERR("timeout waiting for stats finished\n");
144 break;
145 }
146 cnt--;
147 usleep_range(1000, 1000);
148 }
149 return 1;
150 }
151
152 /*
153 * Statistics service functions
154 */
155
156 static void bnx2x_stats_pmf_update(struct bnx2x *bp)
157 {
158 struct dmae_command *dmae;
159 u32 opcode;
160 int loader_idx = PMF_DMAE_C(bp);
161 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
162
163 /* sanity */
164 if (!bp->port.pmf || !bp->port.port_stx) {
165 BNX2X_ERR("BUG!\n");
166 return;
167 }
168
169 bp->executer_idx = 0;
170
171 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI, false, 0);
172
173 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
174 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_GRC);
175 dmae->src_addr_lo = bp->port.port_stx >> 2;
176 dmae->src_addr_hi = 0;
177 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
178 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
179 dmae->len = DMAE_LEN32_RD_MAX;
180 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
181 dmae->comp_addr_hi = 0;
182 dmae->comp_val = 1;
183
184 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
185 dmae->opcode = bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
186 dmae->src_addr_lo = (bp->port.port_stx >> 2) + DMAE_LEN32_RD_MAX;
187 dmae->src_addr_hi = 0;
188 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats) +
189 DMAE_LEN32_RD_MAX * 4);
190 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats) +
191 DMAE_LEN32_RD_MAX * 4);
192 dmae->len = bnx2x_get_port_stats_dma_len(bp) - DMAE_LEN32_RD_MAX;
193
194 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
195 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
196 dmae->comp_val = DMAE_COMP_VAL;
197
198 *stats_comp = 0;
199 bnx2x_hw_stats_post(bp);
200 bnx2x_stats_comp(bp);
201 }
202
203 static void bnx2x_port_stats_init(struct bnx2x *bp)
204 {
205 struct dmae_command *dmae;
206 int port = BP_PORT(bp);
207 u32 opcode;
208 int loader_idx = PMF_DMAE_C(bp);
209 u32 mac_addr;
210 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
211
212 /* sanity */
213 if (!bp->link_vars.link_up || !bp->port.pmf) {
214 BNX2X_ERR("BUG!\n");
215 return;
216 }
217
218 bp->executer_idx = 0;
219
220 /* MCP */
221 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
222 true, DMAE_COMP_GRC);
223
224 if (bp->port.port_stx) {
225
226 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
227 dmae->opcode = opcode;
228 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
229 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
230 dmae->dst_addr_lo = bp->port.port_stx >> 2;
231 dmae->dst_addr_hi = 0;
232 dmae->len = bnx2x_get_port_stats_dma_len(bp);
233 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
234 dmae->comp_addr_hi = 0;
235 dmae->comp_val = 1;
236 }
237
238 if (bp->func_stx) {
239
240 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
241 dmae->opcode = opcode;
242 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
243 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
244 dmae->dst_addr_lo = bp->func_stx >> 2;
245 dmae->dst_addr_hi = 0;
246 dmae->len = sizeof(struct host_func_stats) >> 2;
247 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
248 dmae->comp_addr_hi = 0;
249 dmae->comp_val = 1;
250 }
251
252 /* MAC */
253 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
254 true, DMAE_COMP_GRC);
255
256 /* EMAC is special */
257 if (bp->link_vars.mac_type == MAC_TYPE_EMAC) {
258 mac_addr = (port ? GRCBASE_EMAC1 : GRCBASE_EMAC0);
259
260 /* EMAC_REG_EMAC_RX_STAT_AC (EMAC_REG_EMAC_RX_STAT_AC_COUNT)*/
261 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
262 dmae->opcode = opcode;
263 dmae->src_addr_lo = (mac_addr +
264 EMAC_REG_EMAC_RX_STAT_AC) >> 2;
265 dmae->src_addr_hi = 0;
266 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
267 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
268 dmae->len = EMAC_REG_EMAC_RX_STAT_AC_COUNT;
269 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
270 dmae->comp_addr_hi = 0;
271 dmae->comp_val = 1;
272
273 /* EMAC_REG_EMAC_RX_STAT_AC_28 */
274 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
275 dmae->opcode = opcode;
276 dmae->src_addr_lo = (mac_addr +
277 EMAC_REG_EMAC_RX_STAT_AC_28) >> 2;
278 dmae->src_addr_hi = 0;
279 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
280 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
281 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
282 offsetof(struct emac_stats, rx_stat_falsecarriererrors));
283 dmae->len = 1;
284 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
285 dmae->comp_addr_hi = 0;
286 dmae->comp_val = 1;
287
288 /* EMAC_REG_EMAC_TX_STAT_AC (EMAC_REG_EMAC_TX_STAT_AC_COUNT)*/
289 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
290 dmae->opcode = opcode;
291 dmae->src_addr_lo = (mac_addr +
292 EMAC_REG_EMAC_TX_STAT_AC) >> 2;
293 dmae->src_addr_hi = 0;
294 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats) +
295 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
296 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats) +
297 offsetof(struct emac_stats, tx_stat_ifhcoutoctets));
298 dmae->len = EMAC_REG_EMAC_TX_STAT_AC_COUNT;
299 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
300 dmae->comp_addr_hi = 0;
301 dmae->comp_val = 1;
302 } else {
303 u32 tx_src_addr_lo, rx_src_addr_lo;
304 u16 rx_len, tx_len;
305
306 /* configure the params according to MAC type */
307 switch (bp->link_vars.mac_type) {
308 case MAC_TYPE_BMAC:
309 mac_addr = (port ? NIG_REG_INGRESS_BMAC1_MEM :
310 NIG_REG_INGRESS_BMAC0_MEM);
311
312 /* BIGMAC_REGISTER_TX_STAT_GTPKT ..
313 BIGMAC_REGISTER_TX_STAT_GTBYT */
314 if (CHIP_IS_E1x(bp)) {
315 tx_src_addr_lo = (mac_addr +
316 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
317 tx_len = (8 + BIGMAC_REGISTER_TX_STAT_GTBYT -
318 BIGMAC_REGISTER_TX_STAT_GTPKT) >> 2;
319 rx_src_addr_lo = (mac_addr +
320 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
321 rx_len = (8 + BIGMAC_REGISTER_RX_STAT_GRIPJ -
322 BIGMAC_REGISTER_RX_STAT_GR64) >> 2;
323 } else {
324 tx_src_addr_lo = (mac_addr +
325 BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
326 tx_len = (8 + BIGMAC2_REGISTER_TX_STAT_GTBYT -
327 BIGMAC2_REGISTER_TX_STAT_GTPOK) >> 2;
328 rx_src_addr_lo = (mac_addr +
329 BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
330 rx_len = (8 + BIGMAC2_REGISTER_RX_STAT_GRIPJ -
331 BIGMAC2_REGISTER_RX_STAT_GR64) >> 2;
332 }
333 break;
334
335 case MAC_TYPE_UMAC: /* handled by MSTAT */
336 case MAC_TYPE_XMAC: /* handled by MSTAT */
337 default:
338 mac_addr = port ? GRCBASE_MSTAT1 : GRCBASE_MSTAT0;
339 tx_src_addr_lo = (mac_addr +
340 MSTAT_REG_TX_STAT_GTXPOK_LO) >> 2;
341 rx_src_addr_lo = (mac_addr +
342 MSTAT_REG_RX_STAT_GR64_LO) >> 2;
343 tx_len = sizeof(bp->slowpath->
344 mac_stats.mstat_stats.stats_tx) >> 2;
345 rx_len = sizeof(bp->slowpath->
346 mac_stats.mstat_stats.stats_rx) >> 2;
347 break;
348 }
349
350 /* TX stats */
351 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
352 dmae->opcode = opcode;
353 dmae->src_addr_lo = tx_src_addr_lo;
354 dmae->src_addr_hi = 0;
355 dmae->len = tx_len;
356 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, mac_stats));
357 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, mac_stats));
358 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
359 dmae->comp_addr_hi = 0;
360 dmae->comp_val = 1;
361
362 /* RX stats */
363 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
364 dmae->opcode = opcode;
365 dmae->src_addr_hi = 0;
366 dmae->src_addr_lo = rx_src_addr_lo;
367 dmae->dst_addr_lo =
368 U64_LO(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
369 dmae->dst_addr_hi =
370 U64_HI(bnx2x_sp_mapping(bp, mac_stats) + (tx_len << 2));
371 dmae->len = rx_len;
372 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
373 dmae->comp_addr_hi = 0;
374 dmae->comp_val = 1;
375 }
376
377 /* NIG */
378 if (!CHIP_IS_E3(bp)) {
379 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
380 dmae->opcode = opcode;
381 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT0 :
382 NIG_REG_STAT0_EGRESS_MAC_PKT0) >> 2;
383 dmae->src_addr_hi = 0;
384 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
385 offsetof(struct nig_stats, egress_mac_pkt0_lo));
386 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
387 offsetof(struct nig_stats, egress_mac_pkt0_lo));
388 dmae->len = (2*sizeof(u32)) >> 2;
389 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
390 dmae->comp_addr_hi = 0;
391 dmae->comp_val = 1;
392
393 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
394 dmae->opcode = opcode;
395 dmae->src_addr_lo = (port ? NIG_REG_STAT1_EGRESS_MAC_PKT1 :
396 NIG_REG_STAT0_EGRESS_MAC_PKT1) >> 2;
397 dmae->src_addr_hi = 0;
398 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats) +
399 offsetof(struct nig_stats, egress_mac_pkt1_lo));
400 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats) +
401 offsetof(struct nig_stats, egress_mac_pkt1_lo));
402 dmae->len = (2*sizeof(u32)) >> 2;
403 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
404 dmae->comp_addr_hi = 0;
405 dmae->comp_val = 1;
406 }
407
408 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
409 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
410 true, DMAE_COMP_PCI);
411 dmae->src_addr_lo = (port ? NIG_REG_STAT1_BRB_DISCARD :
412 NIG_REG_STAT0_BRB_DISCARD) >> 2;
413 dmae->src_addr_hi = 0;
414 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, nig_stats));
415 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, nig_stats));
416 dmae->len = (sizeof(struct nig_stats) - 4*sizeof(u32)) >> 2;
417
418 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
419 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
420 dmae->comp_val = DMAE_COMP_VAL;
421
422 *stats_comp = 0;
423 }
424
425 static void bnx2x_func_stats_init(struct bnx2x *bp)
426 {
427 struct dmae_command *dmae = &bp->stats_dmae;
428 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
429
430 /* sanity */
431 if (!bp->func_stx) {
432 BNX2X_ERR("BUG!\n");
433 return;
434 }
435
436 bp->executer_idx = 0;
437 memset(dmae, 0, sizeof(struct dmae_command));
438
439 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
440 true, DMAE_COMP_PCI);
441 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
442 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
443 dmae->dst_addr_lo = bp->func_stx >> 2;
444 dmae->dst_addr_hi = 0;
445 dmae->len = sizeof(struct host_func_stats) >> 2;
446 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
447 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
448 dmae->comp_val = DMAE_COMP_VAL;
449
450 *stats_comp = 0;
451 }
452
453 static void bnx2x_stats_start(struct bnx2x *bp)
454 {
455 if (bp->port.pmf)
456 bnx2x_port_stats_init(bp);
457
458 else if (bp->func_stx)
459 bnx2x_func_stats_init(bp);
460
461 bnx2x_hw_stats_post(bp);
462 bnx2x_storm_stats_post(bp);
463 }
464
465 static void bnx2x_stats_pmf_start(struct bnx2x *bp)
466 {
467 bnx2x_stats_comp(bp);
468 bnx2x_stats_pmf_update(bp);
469 bnx2x_stats_start(bp);
470 }
471
472 static void bnx2x_stats_restart(struct bnx2x *bp)
473 {
474 bnx2x_stats_comp(bp);
475 bnx2x_stats_start(bp);
476 }
477
478 static void bnx2x_bmac_stats_update(struct bnx2x *bp)
479 {
480 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
481 struct bnx2x_eth_stats *estats = &bp->eth_stats;
482 struct {
483 u32 lo;
484 u32 hi;
485 } diff;
486
487 if (CHIP_IS_E1x(bp)) {
488 struct bmac1_stats *new = bnx2x_sp(bp, mac_stats.bmac1_stats);
489
490 /* the macros below will use "bmac1_stats" type */
491 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
492 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
493 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
494 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
495 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
496 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
497 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
498 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
499 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
500
501 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
502 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
503 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
504 UPDATE_STAT64(tx_stat_gt127,
505 tx_stat_etherstatspkts65octetsto127octets);
506 UPDATE_STAT64(tx_stat_gt255,
507 tx_stat_etherstatspkts128octetsto255octets);
508 UPDATE_STAT64(tx_stat_gt511,
509 tx_stat_etherstatspkts256octetsto511octets);
510 UPDATE_STAT64(tx_stat_gt1023,
511 tx_stat_etherstatspkts512octetsto1023octets);
512 UPDATE_STAT64(tx_stat_gt1518,
513 tx_stat_etherstatspkts1024octetsto1522octets);
514 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
515 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
516 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
517 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
518 UPDATE_STAT64(tx_stat_gterr,
519 tx_stat_dot3statsinternalmactransmiterrors);
520 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
521
522 } else {
523 struct bmac2_stats *new = bnx2x_sp(bp, mac_stats.bmac2_stats);
524
525 /* the macros below will use "bmac2_stats" type */
526 UPDATE_STAT64(rx_stat_grerb, rx_stat_ifhcinbadoctets);
527 UPDATE_STAT64(rx_stat_grfcs, rx_stat_dot3statsfcserrors);
528 UPDATE_STAT64(rx_stat_grund, rx_stat_etherstatsundersizepkts);
529 UPDATE_STAT64(rx_stat_grovr, rx_stat_dot3statsframestoolong);
530 UPDATE_STAT64(rx_stat_grfrg, rx_stat_etherstatsfragments);
531 UPDATE_STAT64(rx_stat_grjbr, rx_stat_etherstatsjabbers);
532 UPDATE_STAT64(rx_stat_grxcf, rx_stat_maccontrolframesreceived);
533 UPDATE_STAT64(rx_stat_grxpf, rx_stat_xoffstateentered);
534 UPDATE_STAT64(rx_stat_grxpf, rx_stat_mac_xpf);
535 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_outxoffsent);
536 UPDATE_STAT64(tx_stat_gtxpf, tx_stat_flowcontroldone);
537 UPDATE_STAT64(tx_stat_gt64, tx_stat_etherstatspkts64octets);
538 UPDATE_STAT64(tx_stat_gt127,
539 tx_stat_etherstatspkts65octetsto127octets);
540 UPDATE_STAT64(tx_stat_gt255,
541 tx_stat_etherstatspkts128octetsto255octets);
542 UPDATE_STAT64(tx_stat_gt511,
543 tx_stat_etherstatspkts256octetsto511octets);
544 UPDATE_STAT64(tx_stat_gt1023,
545 tx_stat_etherstatspkts512octetsto1023octets);
546 UPDATE_STAT64(tx_stat_gt1518,
547 tx_stat_etherstatspkts1024octetsto1522octets);
548 UPDATE_STAT64(tx_stat_gt2047, tx_stat_mac_2047);
549 UPDATE_STAT64(tx_stat_gt4095, tx_stat_mac_4095);
550 UPDATE_STAT64(tx_stat_gt9216, tx_stat_mac_9216);
551 UPDATE_STAT64(tx_stat_gt16383, tx_stat_mac_16383);
552 UPDATE_STAT64(tx_stat_gterr,
553 tx_stat_dot3statsinternalmactransmiterrors);
554 UPDATE_STAT64(tx_stat_gtufl, tx_stat_mac_ufl);
555
556 /* collect PFC stats */
557 DIFF_64(diff.hi, new->tx_stat_gtpp_hi,
558 pstats->pfc_frames_tx_hi,
559 diff.lo, new->tx_stat_gtpp_lo,
560 pstats->pfc_frames_tx_lo);
561 pstats->pfc_frames_tx_hi = new->tx_stat_gtpp_hi;
562 pstats->pfc_frames_tx_lo = new->tx_stat_gtpp_lo;
563 ADD_64(pstats->pfc_frames_tx_hi, diff.hi,
564 pstats->pfc_frames_tx_lo, diff.lo);
565
566 DIFF_64(diff.hi, new->rx_stat_grpp_hi,
567 pstats->pfc_frames_rx_hi,
568 diff.lo, new->rx_stat_grpp_lo,
569 pstats->pfc_frames_rx_lo);
570 pstats->pfc_frames_rx_hi = new->rx_stat_grpp_hi;
571 pstats->pfc_frames_rx_lo = new->rx_stat_grpp_lo;
572 ADD_64(pstats->pfc_frames_rx_hi, diff.hi,
573 pstats->pfc_frames_rx_lo, diff.lo);
574 }
575
576 estats->pause_frames_received_hi =
577 pstats->mac_stx[1].rx_stat_mac_xpf_hi;
578 estats->pause_frames_received_lo =
579 pstats->mac_stx[1].rx_stat_mac_xpf_lo;
580
581 estats->pause_frames_sent_hi =
582 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
583 estats->pause_frames_sent_lo =
584 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
585
586 estats->pfc_frames_received_hi =
587 pstats->pfc_frames_rx_hi;
588 estats->pfc_frames_received_lo =
589 pstats->pfc_frames_rx_lo;
590 estats->pfc_frames_sent_hi =
591 pstats->pfc_frames_tx_hi;
592 estats->pfc_frames_sent_lo =
593 pstats->pfc_frames_tx_lo;
594 }
595
596 static void bnx2x_mstat_stats_update(struct bnx2x *bp)
597 {
598 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
599 struct bnx2x_eth_stats *estats = &bp->eth_stats;
600
601 struct mstat_stats *new = bnx2x_sp(bp, mac_stats.mstat_stats);
602
603 ADD_STAT64(stats_rx.rx_grerb, rx_stat_ifhcinbadoctets);
604 ADD_STAT64(stats_rx.rx_grfcs, rx_stat_dot3statsfcserrors);
605 ADD_STAT64(stats_rx.rx_grund, rx_stat_etherstatsundersizepkts);
606 ADD_STAT64(stats_rx.rx_grovr, rx_stat_dot3statsframestoolong);
607 ADD_STAT64(stats_rx.rx_grfrg, rx_stat_etherstatsfragments);
608 ADD_STAT64(stats_rx.rx_grxcf, rx_stat_maccontrolframesreceived);
609 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_xoffstateentered);
610 ADD_STAT64(stats_rx.rx_grxpf, rx_stat_mac_xpf);
611 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_outxoffsent);
612 ADD_STAT64(stats_tx.tx_gtxpf, tx_stat_flowcontroldone);
613
614 /* collect pfc stats */
615 ADD_64(pstats->pfc_frames_tx_hi, new->stats_tx.tx_gtxpp_hi,
616 pstats->pfc_frames_tx_lo, new->stats_tx.tx_gtxpp_lo);
617 ADD_64(pstats->pfc_frames_rx_hi, new->stats_rx.rx_grxpp_hi,
618 pstats->pfc_frames_rx_lo, new->stats_rx.rx_grxpp_lo);
619
620 ADD_STAT64(stats_tx.tx_gt64, tx_stat_etherstatspkts64octets);
621 ADD_STAT64(stats_tx.tx_gt127,
622 tx_stat_etherstatspkts65octetsto127octets);
623 ADD_STAT64(stats_tx.tx_gt255,
624 tx_stat_etherstatspkts128octetsto255octets);
625 ADD_STAT64(stats_tx.tx_gt511,
626 tx_stat_etherstatspkts256octetsto511octets);
627 ADD_STAT64(stats_tx.tx_gt1023,
628 tx_stat_etherstatspkts512octetsto1023octets);
629 ADD_STAT64(stats_tx.tx_gt1518,
630 tx_stat_etherstatspkts1024octetsto1522octets);
631 ADD_STAT64(stats_tx.tx_gt2047, tx_stat_mac_2047);
632
633 ADD_STAT64(stats_tx.tx_gt4095, tx_stat_mac_4095);
634 ADD_STAT64(stats_tx.tx_gt9216, tx_stat_mac_9216);
635 ADD_STAT64(stats_tx.tx_gt16383, tx_stat_mac_16383);
636
637 ADD_STAT64(stats_tx.tx_gterr,
638 tx_stat_dot3statsinternalmactransmiterrors);
639 ADD_STAT64(stats_tx.tx_gtufl, tx_stat_mac_ufl);
640
641 estats->etherstatspkts1024octetsto1522octets_hi =
642 pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_hi;
643 estats->etherstatspkts1024octetsto1522octets_lo =
644 pstats->mac_stx[1].tx_stat_etherstatspkts1024octetsto1522octets_lo;
645
646 estats->etherstatspktsover1522octets_hi =
647 pstats->mac_stx[1].tx_stat_mac_2047_hi;
648 estats->etherstatspktsover1522octets_lo =
649 pstats->mac_stx[1].tx_stat_mac_2047_lo;
650
651 ADD_64(estats->etherstatspktsover1522octets_hi,
652 pstats->mac_stx[1].tx_stat_mac_4095_hi,
653 estats->etherstatspktsover1522octets_lo,
654 pstats->mac_stx[1].tx_stat_mac_4095_lo);
655
656 ADD_64(estats->etherstatspktsover1522octets_hi,
657 pstats->mac_stx[1].tx_stat_mac_9216_hi,
658 estats->etherstatspktsover1522octets_lo,
659 pstats->mac_stx[1].tx_stat_mac_9216_lo);
660
661 ADD_64(estats->etherstatspktsover1522octets_hi,
662 pstats->mac_stx[1].tx_stat_mac_16383_hi,
663 estats->etherstatspktsover1522octets_lo,
664 pstats->mac_stx[1].tx_stat_mac_16383_lo);
665
666 estats->pause_frames_received_hi =
667 pstats->mac_stx[1].rx_stat_mac_xpf_hi;
668 estats->pause_frames_received_lo =
669 pstats->mac_stx[1].rx_stat_mac_xpf_lo;
670
671 estats->pause_frames_sent_hi =
672 pstats->mac_stx[1].tx_stat_outxoffsent_hi;
673 estats->pause_frames_sent_lo =
674 pstats->mac_stx[1].tx_stat_outxoffsent_lo;
675
676 estats->pfc_frames_received_hi =
677 pstats->pfc_frames_rx_hi;
678 estats->pfc_frames_received_lo =
679 pstats->pfc_frames_rx_lo;
680 estats->pfc_frames_sent_hi =
681 pstats->pfc_frames_tx_hi;
682 estats->pfc_frames_sent_lo =
683 pstats->pfc_frames_tx_lo;
684 }
685
686 static void bnx2x_emac_stats_update(struct bnx2x *bp)
687 {
688 struct emac_stats *new = bnx2x_sp(bp, mac_stats.emac_stats);
689 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
690 struct bnx2x_eth_stats *estats = &bp->eth_stats;
691
692 UPDATE_EXTEND_STAT(rx_stat_ifhcinbadoctets);
693 UPDATE_EXTEND_STAT(tx_stat_ifhcoutbadoctets);
694 UPDATE_EXTEND_STAT(rx_stat_dot3statsfcserrors);
695 UPDATE_EXTEND_STAT(rx_stat_dot3statsalignmenterrors);
696 UPDATE_EXTEND_STAT(rx_stat_dot3statscarriersenseerrors);
697 UPDATE_EXTEND_STAT(rx_stat_falsecarriererrors);
698 UPDATE_EXTEND_STAT(rx_stat_etherstatsundersizepkts);
699 UPDATE_EXTEND_STAT(rx_stat_dot3statsframestoolong);
700 UPDATE_EXTEND_STAT(rx_stat_etherstatsfragments);
701 UPDATE_EXTEND_STAT(rx_stat_etherstatsjabbers);
702 UPDATE_EXTEND_STAT(rx_stat_maccontrolframesreceived);
703 UPDATE_EXTEND_STAT(rx_stat_xoffstateentered);
704 UPDATE_EXTEND_STAT(rx_stat_xonpauseframesreceived);
705 UPDATE_EXTEND_STAT(rx_stat_xoffpauseframesreceived);
706 UPDATE_EXTEND_STAT(tx_stat_outxonsent);
707 UPDATE_EXTEND_STAT(tx_stat_outxoffsent);
708 UPDATE_EXTEND_STAT(tx_stat_flowcontroldone);
709 UPDATE_EXTEND_STAT(tx_stat_etherstatscollisions);
710 UPDATE_EXTEND_STAT(tx_stat_dot3statssinglecollisionframes);
711 UPDATE_EXTEND_STAT(tx_stat_dot3statsmultiplecollisionframes);
712 UPDATE_EXTEND_STAT(tx_stat_dot3statsdeferredtransmissions);
713 UPDATE_EXTEND_STAT(tx_stat_dot3statsexcessivecollisions);
714 UPDATE_EXTEND_STAT(tx_stat_dot3statslatecollisions);
715 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts64octets);
716 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts65octetsto127octets);
717 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts128octetsto255octets);
718 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts256octetsto511octets);
719 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts512octetsto1023octets);
720 UPDATE_EXTEND_STAT(tx_stat_etherstatspkts1024octetsto1522octets);
721 UPDATE_EXTEND_STAT(tx_stat_etherstatspktsover1522octets);
722 UPDATE_EXTEND_STAT(tx_stat_dot3statsinternalmactransmiterrors);
723
724 estats->pause_frames_received_hi =
725 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_hi;
726 estats->pause_frames_received_lo =
727 pstats->mac_stx[1].rx_stat_xonpauseframesreceived_lo;
728 ADD_64(estats->pause_frames_received_hi,
729 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_hi,
730 estats->pause_frames_received_lo,
731 pstats->mac_stx[1].rx_stat_xoffpauseframesreceived_lo);
732
733 estats->pause_frames_sent_hi =
734 pstats->mac_stx[1].tx_stat_outxonsent_hi;
735 estats->pause_frames_sent_lo =
736 pstats->mac_stx[1].tx_stat_outxonsent_lo;
737 ADD_64(estats->pause_frames_sent_hi,
738 pstats->mac_stx[1].tx_stat_outxoffsent_hi,
739 estats->pause_frames_sent_lo,
740 pstats->mac_stx[1].tx_stat_outxoffsent_lo);
741 }
742
743 static int bnx2x_hw_stats_update(struct bnx2x *bp)
744 {
745 struct nig_stats *new = bnx2x_sp(bp, nig_stats);
746 struct nig_stats *old = &(bp->port.old_nig_stats);
747 struct host_port_stats *pstats = bnx2x_sp(bp, port_stats);
748 struct bnx2x_eth_stats *estats = &bp->eth_stats;
749 struct {
750 u32 lo;
751 u32 hi;
752 } diff;
753
754 switch (bp->link_vars.mac_type) {
755 case MAC_TYPE_BMAC:
756 bnx2x_bmac_stats_update(bp);
757 break;
758
759 case MAC_TYPE_EMAC:
760 bnx2x_emac_stats_update(bp);
761 break;
762
763 case MAC_TYPE_UMAC:
764 case MAC_TYPE_XMAC:
765 bnx2x_mstat_stats_update(bp);
766 break;
767
768 case MAC_TYPE_NONE: /* unreached */
769 DP(BNX2X_MSG_STATS,
770 "stats updated by DMAE but no MAC active\n");
771 return -1;
772
773 default: /* unreached */
774 BNX2X_ERR("Unknown MAC type\n");
775 }
776
777 ADD_EXTEND_64(pstats->brb_drop_hi, pstats->brb_drop_lo,
778 new->brb_discard - old->brb_discard);
779 ADD_EXTEND_64(estats->brb_truncate_hi, estats->brb_truncate_lo,
780 new->brb_truncate - old->brb_truncate);
781
782 if (!CHIP_IS_E3(bp)) {
783 UPDATE_STAT64_NIG(egress_mac_pkt0,
784 etherstatspkts1024octetsto1522octets);
785 UPDATE_STAT64_NIG(egress_mac_pkt1,
786 etherstatspktsover1522octets);
787 }
788
789 memcpy(old, new, sizeof(struct nig_stats));
790
791 memcpy(&(estats->rx_stat_ifhcinbadoctets_hi), &(pstats->mac_stx[1]),
792 sizeof(struct mac_stx));
793 estats->brb_drop_hi = pstats->brb_drop_hi;
794 estats->brb_drop_lo = pstats->brb_drop_lo;
795
796 pstats->host_port_stats_counter++;
797
798 if (!BP_NOMCP(bp)) {
799 u32 nig_timer_max =
800 SHMEM_RD(bp, port_mb[BP_PORT(bp)].stat_nig_timer);
801 if (nig_timer_max != estats->nig_timer_max) {
802 estats->nig_timer_max = nig_timer_max;
803 BNX2X_ERR("NIG timer max (%u)\n",
804 estats->nig_timer_max);
805 }
806 }
807
808 return 0;
809 }
810
811 static int bnx2x_storm_stats_update(struct bnx2x *bp)
812 {
813 struct tstorm_per_port_stats *tport =
814 &bp->fw_stats_data->port.tstorm_port_statistics;
815 struct tstorm_per_pf_stats *tfunc =
816 &bp->fw_stats_data->pf.tstorm_pf_statistics;
817 struct host_func_stats *fstats = bnx2x_sp(bp, func_stats);
818 struct bnx2x_eth_stats *estats = &bp->eth_stats;
819 struct bnx2x_eth_stats_old *estats_old = &bp->eth_stats_old;
820 struct stats_counter *counters = &bp->fw_stats_data->storm_counters;
821 int i;
822 u16 cur_stats_counter;
823
824 /* Make sure we use the value of the counter
825 * used for sending the last stats ramrod.
826 */
827 spin_lock_bh(&bp->stats_lock);
828 cur_stats_counter = bp->stats_counter - 1;
829 spin_unlock_bh(&bp->stats_lock);
830
831 /* are storm stats valid? */
832 if (le16_to_cpu(counters->xstats_counter) != cur_stats_counter) {
833 DP(BNX2X_MSG_STATS, "stats not updated by xstorm"
834 " xstorm counter (0x%x) != stats_counter (0x%x)\n",
835 le16_to_cpu(counters->xstats_counter), bp->stats_counter);
836 return -EAGAIN;
837 }
838
839 if (le16_to_cpu(counters->ustats_counter) != cur_stats_counter) {
840 DP(BNX2X_MSG_STATS, "stats not updated by ustorm"
841 " ustorm counter (0x%x) != stats_counter (0x%x)\n",
842 le16_to_cpu(counters->ustats_counter), bp->stats_counter);
843 return -EAGAIN;
844 }
845
846 if (le16_to_cpu(counters->cstats_counter) != cur_stats_counter) {
847 DP(BNX2X_MSG_STATS, "stats not updated by cstorm"
848 " cstorm counter (0x%x) != stats_counter (0x%x)\n",
849 le16_to_cpu(counters->cstats_counter), bp->stats_counter);
850 return -EAGAIN;
851 }
852
853 if (le16_to_cpu(counters->tstats_counter) != cur_stats_counter) {
854 DP(BNX2X_MSG_STATS, "stats not updated by tstorm"
855 " tstorm counter (0x%x) != stats_counter (0x%x)\n",
856 le16_to_cpu(counters->tstats_counter), bp->stats_counter);
857 return -EAGAIN;
858 }
859
860 estats->error_bytes_received_hi = 0;
861 estats->error_bytes_received_lo = 0;
862
863 for_each_eth_queue(bp, i) {
864 struct bnx2x_fastpath *fp = &bp->fp[i];
865 struct tstorm_per_queue_stats *tclient =
866 &bp->fw_stats_data->queue_stats[i].
867 tstorm_queue_statistics;
868 struct tstorm_per_queue_stats *old_tclient = &fp->old_tclient;
869 struct ustorm_per_queue_stats *uclient =
870 &bp->fw_stats_data->queue_stats[i].
871 ustorm_queue_statistics;
872 struct ustorm_per_queue_stats *old_uclient = &fp->old_uclient;
873 struct xstorm_per_queue_stats *xclient =
874 &bp->fw_stats_data->queue_stats[i].
875 xstorm_queue_statistics;
876 struct xstorm_per_queue_stats *old_xclient = &fp->old_xclient;
877 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
878 struct bnx2x_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;
879
880 u32 diff;
881
882 DP(BNX2X_MSG_STATS, "queue[%d]: ucast_sent 0x%x, "
883 "bcast_sent 0x%x mcast_sent 0x%x\n",
884 i, xclient->ucast_pkts_sent,
885 xclient->bcast_pkts_sent, xclient->mcast_pkts_sent);
886
887 DP(BNX2X_MSG_STATS, "---------------\n");
888
889 UPDATE_QSTAT(tclient->rcv_bcast_bytes,
890 total_broadcast_bytes_received);
891 UPDATE_QSTAT(tclient->rcv_mcast_bytes,
892 total_multicast_bytes_received);
893 UPDATE_QSTAT(tclient->rcv_ucast_bytes,
894 total_unicast_bytes_received);
895
896 /*
897 * sum to total_bytes_received all
898 * unicast/multicast/broadcast
899 */
900 qstats->total_bytes_received_hi =
901 qstats->total_broadcast_bytes_received_hi;
902 qstats->total_bytes_received_lo =
903 qstats->total_broadcast_bytes_received_lo;
904
905 ADD_64(qstats->total_bytes_received_hi,
906 qstats->total_multicast_bytes_received_hi,
907 qstats->total_bytes_received_lo,
908 qstats->total_multicast_bytes_received_lo);
909
910 ADD_64(qstats->total_bytes_received_hi,
911 qstats->total_unicast_bytes_received_hi,
912 qstats->total_bytes_received_lo,
913 qstats->total_unicast_bytes_received_lo);
914
915 qstats->valid_bytes_received_hi =
916 qstats->total_bytes_received_hi;
917 qstats->valid_bytes_received_lo =
918 qstats->total_bytes_received_lo;
919
920
921 UPDATE_EXTEND_TSTAT(rcv_ucast_pkts,
922 total_unicast_packets_received);
923 UPDATE_EXTEND_TSTAT(rcv_mcast_pkts,
924 total_multicast_packets_received);
925 UPDATE_EXTEND_TSTAT(rcv_bcast_pkts,
926 total_broadcast_packets_received);
927 UPDATE_EXTEND_E_TSTAT(pkts_too_big_discard,
928 etherstatsoverrsizepkts);
929 UPDATE_EXTEND_E_TSTAT(no_buff_discard, no_buff_discard);
930
931 SUB_EXTEND_USTAT(ucast_no_buff_pkts,
932 total_unicast_packets_received);
933 SUB_EXTEND_USTAT(mcast_no_buff_pkts,
934 total_multicast_packets_received);
935 SUB_EXTEND_USTAT(bcast_no_buff_pkts,
936 total_broadcast_packets_received);
937 UPDATE_EXTEND_E_USTAT(ucast_no_buff_pkts, no_buff_discard);
938 UPDATE_EXTEND_E_USTAT(mcast_no_buff_pkts, no_buff_discard);
939 UPDATE_EXTEND_E_USTAT(bcast_no_buff_pkts, no_buff_discard);
940
941 UPDATE_QSTAT(xclient->bcast_bytes_sent,
942 total_broadcast_bytes_transmitted);
943 UPDATE_QSTAT(xclient->mcast_bytes_sent,
944 total_multicast_bytes_transmitted);
945 UPDATE_QSTAT(xclient->ucast_bytes_sent,
946 total_unicast_bytes_transmitted);
947
948 /*
949 * sum to total_bytes_transmitted all
950 * unicast/multicast/broadcast
951 */
952 qstats->total_bytes_transmitted_hi =
953 qstats->total_unicast_bytes_transmitted_hi;
954 qstats->total_bytes_transmitted_lo =
955 qstats->total_unicast_bytes_transmitted_lo;
956
957 ADD_64(qstats->total_bytes_transmitted_hi,
958 qstats->total_broadcast_bytes_transmitted_hi,
959 qstats->total_bytes_transmitted_lo,
960 qstats->total_broadcast_bytes_transmitted_lo);
961
962 ADD_64(qstats->total_bytes_transmitted_hi,
963 qstats->total_multicast_bytes_transmitted_hi,
964 qstats->total_bytes_transmitted_lo,
965 qstats->total_multicast_bytes_transmitted_lo);
966
967 UPDATE_EXTEND_XSTAT(ucast_pkts_sent,
968 total_unicast_packets_transmitted);
969 UPDATE_EXTEND_XSTAT(mcast_pkts_sent,
970 total_multicast_packets_transmitted);
971 UPDATE_EXTEND_XSTAT(bcast_pkts_sent,
972 total_broadcast_packets_transmitted);
973
974 UPDATE_EXTEND_TSTAT(checksum_discard,
975 total_packets_received_checksum_discarded);
976 UPDATE_EXTEND_TSTAT(ttl0_discard,
977 total_packets_received_ttl0_discarded);
978
979 UPDATE_EXTEND_XSTAT(error_drop_pkts,
980 total_transmitted_dropped_packets_error);
981
982 /* TPA aggregations completed */
983 UPDATE_EXTEND_E_USTAT(coalesced_events, total_tpa_aggregations);
984 /* Number of network frames aggregated by TPA */
985 UPDATE_EXTEND_E_USTAT(coalesced_pkts,
986 total_tpa_aggregated_frames);
987 /* Total number of bytes in completed TPA aggregations */
988 UPDATE_QSTAT(uclient->coalesced_bytes, total_tpa_bytes);
989
990 UPDATE_ESTAT_QSTAT_64(total_tpa_bytes);
991
992 UPDATE_FSTAT_QSTAT(total_bytes_received);
993 UPDATE_FSTAT_QSTAT(total_bytes_transmitted);
994 UPDATE_FSTAT_QSTAT(total_unicast_packets_received);
995 UPDATE_FSTAT_QSTAT(total_multicast_packets_received);
996 UPDATE_FSTAT_QSTAT(total_broadcast_packets_received);
997 UPDATE_FSTAT_QSTAT(total_unicast_packets_transmitted);
998 UPDATE_FSTAT_QSTAT(total_multicast_packets_transmitted);
999 UPDATE_FSTAT_QSTAT(total_broadcast_packets_transmitted);
1000 UPDATE_FSTAT_QSTAT(valid_bytes_received);
1001 }
1002
1003 ADD_64(estats->total_bytes_received_hi,
1004 estats->rx_stat_ifhcinbadoctets_hi,
1005 estats->total_bytes_received_lo,
1006 estats->rx_stat_ifhcinbadoctets_lo);
1007
1008 ADD_64(estats->total_bytes_received_hi,
1009 le32_to_cpu(tfunc->rcv_error_bytes.hi),
1010 estats->total_bytes_received_lo,
1011 le32_to_cpu(tfunc->rcv_error_bytes.lo));
1012
1013 ADD_64(estats->error_bytes_received_hi,
1014 le32_to_cpu(tfunc->rcv_error_bytes.hi),
1015 estats->error_bytes_received_lo,
1016 le32_to_cpu(tfunc->rcv_error_bytes.lo));
1017
1018 UPDATE_ESTAT(etherstatsoverrsizepkts, rx_stat_dot3statsframestoolong);
1019
1020 ADD_64(estats->error_bytes_received_hi,
1021 estats->rx_stat_ifhcinbadoctets_hi,
1022 estats->error_bytes_received_lo,
1023 estats->rx_stat_ifhcinbadoctets_lo);
1024
1025 if (bp->port.pmf) {
1026 struct bnx2x_fw_port_stats_old *fwstats = &bp->fw_stats_old;
1027 UPDATE_FW_STAT(mac_filter_discard);
1028 UPDATE_FW_STAT(mf_tag_discard);
1029 UPDATE_FW_STAT(brb_truncate_discard);
1030 UPDATE_FW_STAT(mac_discard);
1031 }
1032
1033 fstats->host_func_stats_start = ++fstats->host_func_stats_end;
1034
1035 bp->stats_pending = 0;
1036
1037 return 0;
1038 }
1039
1040 static void bnx2x_net_stats_update(struct bnx2x *bp)
1041 {
1042 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1043 struct net_device_stats *nstats = &bp->dev->stats;
1044 unsigned long tmp;
1045 int i;
1046
1047 nstats->rx_packets =
1048 bnx2x_hilo(&estats->total_unicast_packets_received_hi) +
1049 bnx2x_hilo(&estats->total_multicast_packets_received_hi) +
1050 bnx2x_hilo(&estats->total_broadcast_packets_received_hi);
1051
1052 nstats->tx_packets =
1053 bnx2x_hilo(&estats->total_unicast_packets_transmitted_hi) +
1054 bnx2x_hilo(&estats->total_multicast_packets_transmitted_hi) +
1055 bnx2x_hilo(&estats->total_broadcast_packets_transmitted_hi);
1056
1057 nstats->rx_bytes = bnx2x_hilo(&estats->total_bytes_received_hi);
1058
1059 nstats->tx_bytes = bnx2x_hilo(&estats->total_bytes_transmitted_hi);
1060
1061 tmp = estats->mac_discard;
1062 for_each_rx_queue(bp, i)
1063 tmp += le32_to_cpu(bp->fp[i].old_tclient.checksum_discard);
1064 nstats->rx_dropped = tmp + bp->net_stats_old.rx_dropped;
1065
1066 nstats->tx_dropped = 0;
1067
1068 nstats->multicast =
1069 bnx2x_hilo(&estats->total_multicast_packets_received_hi);
1070
1071 nstats->collisions =
1072 bnx2x_hilo(&estats->tx_stat_etherstatscollisions_hi);
1073
1074 nstats->rx_length_errors =
1075 bnx2x_hilo(&estats->rx_stat_etherstatsundersizepkts_hi) +
1076 bnx2x_hilo(&estats->etherstatsoverrsizepkts_hi);
1077 nstats->rx_over_errors = bnx2x_hilo(&estats->brb_drop_hi) +
1078 bnx2x_hilo(&estats->brb_truncate_hi);
1079 nstats->rx_crc_errors =
1080 bnx2x_hilo(&estats->rx_stat_dot3statsfcserrors_hi);
1081 nstats->rx_frame_errors =
1082 bnx2x_hilo(&estats->rx_stat_dot3statsalignmenterrors_hi);
1083 nstats->rx_fifo_errors = bnx2x_hilo(&estats->no_buff_discard_hi);
1084 nstats->rx_missed_errors = 0;
1085
1086 nstats->rx_errors = nstats->rx_length_errors +
1087 nstats->rx_over_errors +
1088 nstats->rx_crc_errors +
1089 nstats->rx_frame_errors +
1090 nstats->rx_fifo_errors +
1091 nstats->rx_missed_errors;
1092
1093 nstats->tx_aborted_errors =
1094 bnx2x_hilo(&estats->tx_stat_dot3statslatecollisions_hi) +
1095 bnx2x_hilo(&estats->tx_stat_dot3statsexcessivecollisions_hi);
1096 nstats->tx_carrier_errors =
1097 bnx2x_hilo(&estats->rx_stat_dot3statscarriersenseerrors_hi);
1098 nstats->tx_fifo_errors = 0;
1099 nstats->tx_heartbeat_errors = 0;
1100 nstats->tx_window_errors = 0;
1101
1102 nstats->tx_errors = nstats->tx_aborted_errors +
1103 nstats->tx_carrier_errors +
1104 bnx2x_hilo(&estats->tx_stat_dot3statsinternalmactransmiterrors_hi);
1105 }
1106
1107 static void bnx2x_drv_stats_update(struct bnx2x *bp)
1108 {
1109 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1110 int i;
1111
1112 for_each_queue(bp, i) {
1113 struct bnx2x_eth_q_stats *qstats = &bp->fp[i].eth_q_stats;
1114 struct bnx2x_eth_q_stats_old *qstats_old =
1115 &bp->fp[i].eth_q_stats_old;
1116
1117 UPDATE_ESTAT_QSTAT(driver_xoff);
1118 UPDATE_ESTAT_QSTAT(rx_err_discard_pkt);
1119 UPDATE_ESTAT_QSTAT(rx_skb_alloc_failed);
1120 UPDATE_ESTAT_QSTAT(hw_csum_err);
1121 }
1122 }
1123
1124 static bool bnx2x_edebug_stats_stopped(struct bnx2x *bp)
1125 {
1126 u32 val;
1127
1128 if (SHMEM2_HAS(bp, edebug_driver_if[1])) {
1129 val = SHMEM2_RD(bp, edebug_driver_if[1]);
1130
1131 if (val == EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT)
1132 return true;
1133 }
1134
1135 return false;
1136 }
1137
1138 static void bnx2x_stats_update(struct bnx2x *bp)
1139 {
1140 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1141
1142 if (bnx2x_edebug_stats_stopped(bp))
1143 return;
1144
1145 if (*stats_comp != DMAE_COMP_VAL)
1146 return;
1147
1148 if (bp->port.pmf)
1149 bnx2x_hw_stats_update(bp);
1150
1151 if (bnx2x_storm_stats_update(bp) && (bp->stats_pending++ == 3)) {
1152 BNX2X_ERR("storm stats were not updated for 3 times\n");
1153 bnx2x_panic();
1154 return;
1155 }
1156
1157 bnx2x_net_stats_update(bp);
1158 bnx2x_drv_stats_update(bp);
1159
1160 if (netif_msg_timer(bp)) {
1161 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1162 int i, cos;
1163
1164 netdev_dbg(bp->dev, "brb drops %u brb truncate %u\n",
1165 estats->brb_drop_lo, estats->brb_truncate_lo);
1166
1167 for_each_eth_queue(bp, i) {
1168 struct bnx2x_fastpath *fp = &bp->fp[i];
1169 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1170
1171 pr_debug("%s: rx usage(%4u) *rx_cons_sb(%u) rx pkt(%lu) rx calls(%lu %lu)\n",
1172 fp->name, (le16_to_cpu(*fp->rx_cons_sb) -
1173 fp->rx_comp_cons),
1174 le16_to_cpu(*fp->rx_cons_sb),
1175 bnx2x_hilo(&qstats->
1176 total_unicast_packets_received_hi),
1177 fp->rx_calls, fp->rx_pkt);
1178 }
1179
1180 for_each_eth_queue(bp, i) {
1181 struct bnx2x_fastpath *fp = &bp->fp[i];
1182 struct bnx2x_fp_txdata *txdata;
1183 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1184 struct netdev_queue *txq;
1185
1186 pr_debug("%s: tx pkt(%lu) (Xoff events %u)",
1187 fp->name,
1188 bnx2x_hilo(
1189 &qstats->total_unicast_packets_transmitted_hi),
1190 qstats->driver_xoff);
1191
1192 for_each_cos_in_tx_queue(fp, cos) {
1193 txdata = &fp->txdata[cos];
1194 txq = netdev_get_tx_queue(bp->dev,
1195 FP_COS_TO_TXQ(fp, cos));
1196
1197 pr_debug("%d: tx avail(%4u) *tx_cons_sb(%u) tx calls (%lu) %s\n",
1198 cos,
1199 bnx2x_tx_avail(bp, txdata),
1200 le16_to_cpu(*txdata->tx_cons_sb),
1201 txdata->tx_pkt,
1202 (netif_tx_queue_stopped(txq) ?
1203 "Xoff" : "Xon")
1204 );
1205 }
1206 }
1207 }
1208
1209 bnx2x_hw_stats_post(bp);
1210 bnx2x_storm_stats_post(bp);
1211 }
1212
1213 static void bnx2x_port_stats_stop(struct bnx2x *bp)
1214 {
1215 struct dmae_command *dmae;
1216 u32 opcode;
1217 int loader_idx = PMF_DMAE_C(bp);
1218 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1219
1220 bp->executer_idx = 0;
1221
1222 opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC, false, 0);
1223
1224 if (bp->port.port_stx) {
1225
1226 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1227 if (bp->func_stx)
1228 dmae->opcode = bnx2x_dmae_opcode_add_comp(
1229 opcode, DMAE_COMP_GRC);
1230 else
1231 dmae->opcode = bnx2x_dmae_opcode_add_comp(
1232 opcode, DMAE_COMP_PCI);
1233
1234 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1235 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1236 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1237 dmae->dst_addr_hi = 0;
1238 dmae->len = bnx2x_get_port_stats_dma_len(bp);
1239 if (bp->func_stx) {
1240 dmae->comp_addr_lo = dmae_reg_go_c[loader_idx] >> 2;
1241 dmae->comp_addr_hi = 0;
1242 dmae->comp_val = 1;
1243 } else {
1244 dmae->comp_addr_lo =
1245 U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1246 dmae->comp_addr_hi =
1247 U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1248 dmae->comp_val = DMAE_COMP_VAL;
1249
1250 *stats_comp = 0;
1251 }
1252 }
1253
1254 if (bp->func_stx) {
1255
1256 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1257 dmae->opcode =
1258 bnx2x_dmae_opcode_add_comp(opcode, DMAE_COMP_PCI);
1259 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
1260 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
1261 dmae->dst_addr_lo = bp->func_stx >> 2;
1262 dmae->dst_addr_hi = 0;
1263 dmae->len = sizeof(struct host_func_stats) >> 2;
1264 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1265 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1266 dmae->comp_val = DMAE_COMP_VAL;
1267
1268 *stats_comp = 0;
1269 }
1270 }
1271
1272 static void bnx2x_stats_stop(struct bnx2x *bp)
1273 {
1274 int update = 0;
1275
1276 bnx2x_stats_comp(bp);
1277
1278 if (bp->port.pmf)
1279 update = (bnx2x_hw_stats_update(bp) == 0);
1280
1281 update |= (bnx2x_storm_stats_update(bp) == 0);
1282
1283 if (update) {
1284 bnx2x_net_stats_update(bp);
1285
1286 if (bp->port.pmf)
1287 bnx2x_port_stats_stop(bp);
1288
1289 bnx2x_hw_stats_post(bp);
1290 bnx2x_stats_comp(bp);
1291 }
1292 }
1293
1294 static void bnx2x_stats_do_nothing(struct bnx2x *bp)
1295 {
1296 }
1297
1298 static const struct {
1299 void (*action)(struct bnx2x *bp);
1300 enum bnx2x_stats_state next_state;
1301 } bnx2x_stats_stm[STATS_STATE_MAX][STATS_EVENT_MAX] = {
1302 /* state event */
1303 {
1304 /* DISABLED PMF */ {bnx2x_stats_pmf_update, STATS_STATE_DISABLED},
1305 /* LINK_UP */ {bnx2x_stats_start, STATS_STATE_ENABLED},
1306 /* UPDATE */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED},
1307 /* STOP */ {bnx2x_stats_do_nothing, STATS_STATE_DISABLED}
1308 },
1309 {
1310 /* ENABLED PMF */ {bnx2x_stats_pmf_start, STATS_STATE_ENABLED},
1311 /* LINK_UP */ {bnx2x_stats_restart, STATS_STATE_ENABLED},
1312 /* UPDATE */ {bnx2x_stats_update, STATS_STATE_ENABLED},
1313 /* STOP */ {bnx2x_stats_stop, STATS_STATE_DISABLED}
1314 }
1315 };
1316
1317 void bnx2x_stats_handle(struct bnx2x *bp, enum bnx2x_stats_event event)
1318 {
1319 enum bnx2x_stats_state state;
1320 if (unlikely(bp->panic))
1321 return;
1322
1323 spin_lock_bh(&bp->stats_lock);
1324 state = bp->stats_state;
1325 bp->stats_state = bnx2x_stats_stm[state][event].next_state;
1326 spin_unlock_bh(&bp->stats_lock);
1327
1328 bnx2x_stats_stm[state][event].action(bp);
1329
1330 if ((event != STATS_EVENT_UPDATE) || netif_msg_timer(bp))
1331 DP(BNX2X_MSG_STATS, "state %d -> event %d -> state %d\n",
1332 state, event, bp->stats_state);
1333 }
1334
1335 static void bnx2x_port_stats_base_init(struct bnx2x *bp)
1336 {
1337 struct dmae_command *dmae;
1338 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1339
1340 /* sanity */
1341 if (!bp->port.pmf || !bp->port.port_stx) {
1342 BNX2X_ERR("BUG!\n");
1343 return;
1344 }
1345
1346 bp->executer_idx = 0;
1347
1348 dmae = bnx2x_sp(bp, dmae[bp->executer_idx++]);
1349 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_PCI, DMAE_DST_GRC,
1350 true, DMAE_COMP_PCI);
1351 dmae->src_addr_lo = U64_LO(bnx2x_sp_mapping(bp, port_stats));
1352 dmae->src_addr_hi = U64_HI(bnx2x_sp_mapping(bp, port_stats));
1353 dmae->dst_addr_lo = bp->port.port_stx >> 2;
1354 dmae->dst_addr_hi = 0;
1355 dmae->len = bnx2x_get_port_stats_dma_len(bp);
1356 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1357 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1358 dmae->comp_val = DMAE_COMP_VAL;
1359
1360 *stats_comp = 0;
1361 bnx2x_hw_stats_post(bp);
1362 bnx2x_stats_comp(bp);
1363 }
1364
1365 static void bnx2x_func_stats_base_update(struct bnx2x *bp)
1366 {
1367 struct dmae_command *dmae = &bp->stats_dmae;
1368 u32 *stats_comp = bnx2x_sp(bp, stats_comp);
1369
1370 /* sanity */
1371 if (!bp->func_stx) {
1372 BNX2X_ERR("BUG!\n");
1373 return;
1374 }
1375
1376 bp->executer_idx = 0;
1377 memset(dmae, 0, sizeof(struct dmae_command));
1378
1379 dmae->opcode = bnx2x_dmae_opcode(bp, DMAE_SRC_GRC, DMAE_DST_PCI,
1380 true, DMAE_COMP_PCI);
1381 dmae->src_addr_lo = bp->func_stx >> 2;
1382 dmae->src_addr_hi = 0;
1383 dmae->dst_addr_lo = U64_LO(bnx2x_sp_mapping(bp, func_stats));
1384 dmae->dst_addr_hi = U64_HI(bnx2x_sp_mapping(bp, func_stats));
1385 dmae->len = sizeof(struct host_func_stats) >> 2;
1386 dmae->comp_addr_lo = U64_LO(bnx2x_sp_mapping(bp, stats_comp));
1387 dmae->comp_addr_hi = U64_HI(bnx2x_sp_mapping(bp, stats_comp));
1388 dmae->comp_val = DMAE_COMP_VAL;
1389
1390 *stats_comp = 0;
1391 bnx2x_hw_stats_post(bp);
1392 bnx2x_stats_comp(bp);
1393 }
1394
1395 /**
1396 * This function will prepare the statistics ramrod data the way
1397 * we will only have to increment the statistics counter and
1398 * send the ramrod each time we have to.
1399 *
1400 * @param bp
1401 */
1402 static inline void bnx2x_prep_fw_stats_req(struct bnx2x *bp)
1403 {
1404 int i;
1405 int first_queue_query_index;
1406 struct stats_query_header *stats_hdr = &bp->fw_stats_req->hdr;
1407
1408 dma_addr_t cur_data_offset;
1409 struct stats_query_entry *cur_query_entry;
1410
1411 stats_hdr->cmd_num = bp->fw_stats_num;
1412 stats_hdr->drv_stats_counter = 0;
1413
1414 /* storm_counters struct contains the counters of completed
1415 * statistics requests per storm which are incremented by FW
1416 * each time it completes hadning a statistics ramrod. We will
1417 * check these counters in the timer handler and discard a
1418 * (statistics) ramrod completion.
1419 */
1420 cur_data_offset = bp->fw_stats_data_mapping +
1421 offsetof(struct bnx2x_fw_stats_data, storm_counters);
1422
1423 stats_hdr->stats_counters_addrs.hi =
1424 cpu_to_le32(U64_HI(cur_data_offset));
1425 stats_hdr->stats_counters_addrs.lo =
1426 cpu_to_le32(U64_LO(cur_data_offset));
1427
1428 /* prepare to the first stats ramrod (will be completed with
1429 * the counters equal to zero) - init counters to somethig different.
1430 */
1431 memset(&bp->fw_stats_data->storm_counters, 0xff,
1432 sizeof(struct stats_counter));
1433
1434 /**** Port FW statistics data ****/
1435 cur_data_offset = bp->fw_stats_data_mapping +
1436 offsetof(struct bnx2x_fw_stats_data, port);
1437
1438 cur_query_entry = &bp->fw_stats_req->query[BNX2X_PORT_QUERY_IDX];
1439
1440 cur_query_entry->kind = STATS_TYPE_PORT;
1441 /* For port query index is a DONT CARE */
1442 cur_query_entry->index = BP_PORT(bp);
1443 /* For port query funcID is a DONT CARE */
1444 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1445 cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
1446 cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
1447
1448 /**** PF FW statistics data ****/
1449 cur_data_offset = bp->fw_stats_data_mapping +
1450 offsetof(struct bnx2x_fw_stats_data, pf);
1451
1452 cur_query_entry = &bp->fw_stats_req->query[BNX2X_PF_QUERY_IDX];
1453
1454 cur_query_entry->kind = STATS_TYPE_PF;
1455 /* For PF query index is a DONT CARE */
1456 cur_query_entry->index = BP_PORT(bp);
1457 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1458 cur_query_entry->address.hi = cpu_to_le32(U64_HI(cur_data_offset));
1459 cur_query_entry->address.lo = cpu_to_le32(U64_LO(cur_data_offset));
1460
1461 /**** FCoE FW statistics data ****/
1462 if (!NO_FCOE(bp)) {
1463 cur_data_offset = bp->fw_stats_data_mapping +
1464 offsetof(struct bnx2x_fw_stats_data, fcoe);
1465
1466 cur_query_entry =
1467 &bp->fw_stats_req->query[BNX2X_FCOE_QUERY_IDX];
1468
1469 cur_query_entry->kind = STATS_TYPE_FCOE;
1470 /* For FCoE query index is a DONT CARE */
1471 cur_query_entry->index = BP_PORT(bp);
1472 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1473 cur_query_entry->address.hi =
1474 cpu_to_le32(U64_HI(cur_data_offset));
1475 cur_query_entry->address.lo =
1476 cpu_to_le32(U64_LO(cur_data_offset));
1477 }
1478
1479 /**** Clients' queries ****/
1480 cur_data_offset = bp->fw_stats_data_mapping +
1481 offsetof(struct bnx2x_fw_stats_data, queue_stats);
1482
1483 /* first queue query index depends whether FCoE offloaded request will
1484 * be included in the ramrod
1485 */
1486 if (!NO_FCOE(bp))
1487 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX;
1488 else
1489 first_queue_query_index = BNX2X_FIRST_QUEUE_QUERY_IDX - 1;
1490
1491 for_each_eth_queue(bp, i) {
1492 cur_query_entry =
1493 &bp->fw_stats_req->
1494 query[first_queue_query_index + i];
1495
1496 cur_query_entry->kind = STATS_TYPE_QUEUE;
1497 cur_query_entry->index = bnx2x_stats_id(&bp->fp[i]);
1498 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1499 cur_query_entry->address.hi =
1500 cpu_to_le32(U64_HI(cur_data_offset));
1501 cur_query_entry->address.lo =
1502 cpu_to_le32(U64_LO(cur_data_offset));
1503
1504 cur_data_offset += sizeof(struct per_queue_stats);
1505 }
1506
1507 /* add FCoE queue query if needed */
1508 if (!NO_FCOE(bp)) {
1509 cur_query_entry =
1510 &bp->fw_stats_req->
1511 query[first_queue_query_index + i];
1512
1513 cur_query_entry->kind = STATS_TYPE_QUEUE;
1514 cur_query_entry->index = bnx2x_stats_id(&bp->fp[FCOE_IDX]);
1515 cur_query_entry->funcID = cpu_to_le16(BP_FUNC(bp));
1516 cur_query_entry->address.hi =
1517 cpu_to_le32(U64_HI(cur_data_offset));
1518 cur_query_entry->address.lo =
1519 cpu_to_le32(U64_LO(cur_data_offset));
1520 }
1521 }
1522
1523 void bnx2x_stats_init(struct bnx2x *bp)
1524 {
1525 int /*abs*/port = BP_PORT(bp);
1526 int mb_idx = BP_FW_MB_IDX(bp);
1527 int i;
1528
1529 bp->stats_pending = 0;
1530 bp->executer_idx = 0;
1531 bp->stats_counter = 0;
1532
1533 /* port and func stats for management */
1534 if (!BP_NOMCP(bp)) {
1535 bp->port.port_stx = SHMEM_RD(bp, port_mb[port].port_stx);
1536 bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
1537
1538 } else {
1539 bp->port.port_stx = 0;
1540 bp->func_stx = 0;
1541 }
1542 DP(BNX2X_MSG_STATS, "port_stx 0x%x func_stx 0x%x\n",
1543 bp->port.port_stx, bp->func_stx);
1544
1545 /* pmf should retrieve port statistics from SP on a non-init*/
1546 if (!bp->stats_init && bp->port.pmf && bp->port.port_stx)
1547 bnx2x_stats_handle(bp, STATS_EVENT_PMF);
1548
1549 port = BP_PORT(bp);
1550 /* port stats */
1551 memset(&(bp->port.old_nig_stats), 0, sizeof(struct nig_stats));
1552 bp->port.old_nig_stats.brb_discard =
1553 REG_RD(bp, NIG_REG_STAT0_BRB_DISCARD + port*0x38);
1554 bp->port.old_nig_stats.brb_truncate =
1555 REG_RD(bp, NIG_REG_STAT0_BRB_TRUNCATE + port*0x38);
1556 if (!CHIP_IS_E3(bp)) {
1557 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT0 + port*0x50,
1558 &(bp->port.old_nig_stats.egress_mac_pkt0_lo), 2);
1559 REG_RD_DMAE(bp, NIG_REG_STAT0_EGRESS_MAC_PKT1 + port*0x50,
1560 &(bp->port.old_nig_stats.egress_mac_pkt1_lo), 2);
1561 }
1562
1563 /* function stats */
1564 for_each_queue(bp, i) {
1565 struct bnx2x_fastpath *fp = &bp->fp[i];
1566
1567 memset(&fp->old_tclient, 0, sizeof(fp->old_tclient));
1568 memset(&fp->old_uclient, 0, sizeof(fp->old_uclient));
1569 memset(&fp->old_xclient, 0, sizeof(fp->old_xclient));
1570 if (bp->stats_init) {
1571 memset(&fp->eth_q_stats, 0, sizeof(fp->eth_q_stats));
1572 memset(&fp->eth_q_stats_old, 0,
1573 sizeof(fp->eth_q_stats_old));
1574 }
1575 }
1576
1577 /* Prepare statistics ramrod data */
1578 bnx2x_prep_fw_stats_req(bp);
1579
1580 memset(&bp->dev->stats, 0, sizeof(bp->dev->stats));
1581 if (bp->stats_init) {
1582 memset(&bp->net_stats_old, 0, sizeof(bp->net_stats_old));
1583 memset(&bp->fw_stats_old, 0, sizeof(bp->fw_stats_old));
1584 memset(&bp->eth_stats_old, 0, sizeof(bp->eth_stats_old));
1585 memset(&bp->eth_stats, 0, sizeof(bp->eth_stats));
1586
1587 /* Clean SP from previous statistics */
1588 if (bp->func_stx) {
1589 memset(bnx2x_sp(bp, func_stats), 0,
1590 sizeof(struct host_func_stats));
1591 bnx2x_func_stats_init(bp);
1592 bnx2x_hw_stats_post(bp);
1593 bnx2x_stats_comp(bp);
1594 }
1595 }
1596
1597 bp->stats_state = STATS_STATE_DISABLED;
1598
1599 if (bp->port.pmf && bp->port.port_stx)
1600 bnx2x_port_stats_base_init(bp);
1601
1602 /* On a non-init, retrieve previous statistics from SP */
1603 if (!bp->stats_init && bp->func_stx)
1604 bnx2x_func_stats_base_update(bp);
1605
1606 /* mark the end of statistics initializiation */
1607 bp->stats_init = false;
1608 }
1609
1610 void bnx2x_save_statistics(struct bnx2x *bp)
1611 {
1612 int i;
1613 struct net_device_stats *nstats = &bp->dev->stats;
1614
1615 /* save queue statistics */
1616 for_each_eth_queue(bp, i) {
1617 struct bnx2x_fastpath *fp = &bp->fp[i];
1618 struct bnx2x_eth_q_stats *qstats = &fp->eth_q_stats;
1619 struct bnx2x_eth_q_stats_old *qstats_old = &fp->eth_q_stats_old;
1620
1621 UPDATE_QSTAT_OLD(total_unicast_bytes_received_hi);
1622 UPDATE_QSTAT_OLD(total_unicast_bytes_received_lo);
1623 UPDATE_QSTAT_OLD(total_broadcast_bytes_received_hi);
1624 UPDATE_QSTAT_OLD(total_broadcast_bytes_received_lo);
1625 UPDATE_QSTAT_OLD(total_multicast_bytes_received_hi);
1626 UPDATE_QSTAT_OLD(total_multicast_bytes_received_lo);
1627 UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_hi);
1628 UPDATE_QSTAT_OLD(total_unicast_bytes_transmitted_lo);
1629 UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_hi);
1630 UPDATE_QSTAT_OLD(total_broadcast_bytes_transmitted_lo);
1631 UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_hi);
1632 UPDATE_QSTAT_OLD(total_multicast_bytes_transmitted_lo);
1633 UPDATE_QSTAT_OLD(total_tpa_bytes_hi);
1634 UPDATE_QSTAT_OLD(total_tpa_bytes_lo);
1635 }
1636
1637 /* save net_device_stats statistics */
1638 bp->net_stats_old.rx_dropped = nstats->rx_dropped;
1639
1640 /* store port firmware statistics */
1641 if (bp->port.pmf && IS_MF(bp)) {
1642 struct bnx2x_eth_stats *estats = &bp->eth_stats;
1643 struct bnx2x_fw_port_stats_old *fwstats = &bp->fw_stats_old;
1644 UPDATE_FW_STAT_OLD(mac_filter_discard);
1645 UPDATE_FW_STAT_OLD(mf_tag_discard);
1646 UPDATE_FW_STAT_OLD(brb_truncate_discard);
1647 UPDATE_FW_STAT_OLD(mac_discard);
1648 }
1649 }
Linux kernel - Deliverables
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