1 /* Broadcom NetXtreme-C/E network driver.
3 * Copyright (c) 2014-2015 Broadcom Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation.
10 #include <linux/module.h>
12 #include <linux/stringify.h>
13 #include <linux/kernel.h>
14 #include <linux/timer.h>
15 #include <linux/errno.h>
16 #include <linux/ioport.h>
17 #include <linux/slab.h>
18 #include <linux/vmalloc.h>
19 #include <linux/interrupt.h>
20 #include <linux/pci.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/bitops.h>
27 #include <linux/irq.h>
28 #include <linux/delay.h>
29 #include <asm/byteorder.h>
31 #include <linux/time.h>
32 #include <linux/mii.h>
34 #include <linux/if_vlan.h>
38 #include <net/checksum.h>
39 #include <net/ip6_checksum.h>
40 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
41 #include <net/vxlan.h>
43 #ifdef CONFIG_NET_RX_BUSY_POLL
44 #include <net/busy_poll.h>
46 #include <linux/workqueue.h>
47 #include <linux/prefetch.h>
48 #include <linux/cache.h>
49 #include <linux/log2.h>
50 #include <linux/aer.h>
51 #include <linux/bitmap.h>
52 #include <linux/cpu_rmap.h>
56 #include "bnxt_sriov.h"
57 #include "bnxt_ethtool.h"
59 #define BNXT_TX_TIMEOUT (5 * HZ)
61 static const char version
[] =
62 "Broadcom NetXtreme-C/E driver " DRV_MODULE_NAME
" v" DRV_MODULE_VERSION
"\n";
64 MODULE_LICENSE("GPL");
65 MODULE_DESCRIPTION("Broadcom BCM573xx network driver");
66 MODULE_VERSION(DRV_MODULE_VERSION
);
68 #define BNXT_RX_OFFSET (NET_SKB_PAD + NET_IP_ALIGN)
69 #define BNXT_RX_DMA_OFFSET NET_SKB_PAD
70 #define BNXT_RX_COPY_THRESH 256
72 #define BNXT_TX_PUSH_THRESH 92
85 /* indexed by enum above */
89 { "Broadcom BCM57301 NetXtreme-C Single-port 10Gb Ethernet" },
90 { "Broadcom BCM57302 NetXtreme-C Dual-port 10Gb/25Gb Ethernet" },
91 { "Broadcom BCM57304 NetXtreme-C Dual-port 10Gb/25Gb/40Gb/50Gb Ethernet" },
92 { "Broadcom BCM57402 NetXtreme-E Dual-port 10Gb Ethernet" },
93 { "Broadcom BCM57404 NetXtreme-E Dual-port 10Gb/25Gb Ethernet" },
94 { "Broadcom BCM57406 NetXtreme-E Dual-port 10GBase-T Ethernet" },
95 { "Broadcom BCM57304 NetXtreme-C Ethernet Virtual Function" },
96 { "Broadcom BCM57404 NetXtreme-E Ethernet Virtual Function" },
99 static const struct pci_device_id bnxt_pci_tbl
[] = {
100 { PCI_VDEVICE(BROADCOM
, 0x16c8), .driver_data
= BCM57301
},
101 { PCI_VDEVICE(BROADCOM
, 0x16c9), .driver_data
= BCM57302
},
102 { PCI_VDEVICE(BROADCOM
, 0x16ca), .driver_data
= BCM57304
},
103 { PCI_VDEVICE(BROADCOM
, 0x16d0), .driver_data
= BCM57402
},
104 { PCI_VDEVICE(BROADCOM
, 0x16d1), .driver_data
= BCM57404
},
105 { PCI_VDEVICE(BROADCOM
, 0x16d2), .driver_data
= BCM57406
},
106 #ifdef CONFIG_BNXT_SRIOV
107 { PCI_VDEVICE(BROADCOM
, 0x16cb), .driver_data
= BCM57304_VF
},
108 { PCI_VDEVICE(BROADCOM
, 0x16d3), .driver_data
= BCM57404_VF
},
113 MODULE_DEVICE_TABLE(pci
, bnxt_pci_tbl
);
115 static const u16 bnxt_vf_req_snif
[] = {
118 HWRM_CFA_L2_FILTER_ALLOC
,
121 static bool bnxt_vf_pciid(enum board_idx idx
)
123 return (idx
== BCM57304_VF
|| idx
== BCM57404_VF
);
126 #define DB_CP_REARM_FLAGS (DB_KEY_CP | DB_IDX_VALID)
127 #define DB_CP_FLAGS (DB_KEY_CP | DB_IDX_VALID | DB_IRQ_DIS)
128 #define DB_CP_IRQ_DIS_FLAGS (DB_KEY_CP | DB_IRQ_DIS)
130 #define BNXT_CP_DB_REARM(db, raw_cons) \
131 writel(DB_CP_REARM_FLAGS | RING_CMP(raw_cons), db)
133 #define BNXT_CP_DB(db, raw_cons) \
134 writel(DB_CP_FLAGS | RING_CMP(raw_cons), db)
136 #define BNXT_CP_DB_IRQ_DIS(db) \
137 writel(DB_CP_IRQ_DIS_FLAGS, db)
139 static inline u32
bnxt_tx_avail(struct bnxt
*bp
, struct bnxt_tx_ring_info
*txr
)
141 /* Tell compiler to fetch tx indices from memory. */
144 return bp
->tx_ring_size
-
145 ((txr
->tx_prod
- txr
->tx_cons
) & bp
->tx_ring_mask
);
148 static const u16 bnxt_lhint_arr
[] = {
149 TX_BD_FLAGS_LHINT_512_AND_SMALLER
,
150 TX_BD_FLAGS_LHINT_512_TO_1023
,
151 TX_BD_FLAGS_LHINT_1024_TO_2047
,
152 TX_BD_FLAGS_LHINT_1024_TO_2047
,
153 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
154 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
155 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
156 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
157 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
158 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
159 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
160 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
161 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
162 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
163 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
164 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
165 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
166 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
167 TX_BD_FLAGS_LHINT_2048_AND_LARGER
,
170 static netdev_tx_t
bnxt_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
172 struct bnxt
*bp
= netdev_priv(dev
);
174 struct tx_bd_ext
*txbd1
;
175 struct netdev_queue
*txq
;
178 unsigned int length
, pad
= 0;
179 u32 len
, free_size
, vlan_tag_flags
, cfa_action
, flags
;
181 struct pci_dev
*pdev
= bp
->pdev
;
182 struct bnxt_tx_ring_info
*txr
;
183 struct bnxt_sw_tx_bd
*tx_buf
;
185 i
= skb_get_queue_mapping(skb
);
186 if (unlikely(i
>= bp
->tx_nr_rings
)) {
187 dev_kfree_skb_any(skb
);
191 txr
= &bp
->tx_ring
[i
];
192 txq
= netdev_get_tx_queue(dev
, i
);
195 free_size
= bnxt_tx_avail(bp
, txr
);
196 if (unlikely(free_size
< skb_shinfo(skb
)->nr_frags
+ 2)) {
197 netif_tx_stop_queue(txq
);
198 return NETDEV_TX_BUSY
;
202 len
= skb_headlen(skb
);
203 last_frag
= skb_shinfo(skb
)->nr_frags
;
205 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
207 txbd
->tx_bd_opaque
= prod
;
209 tx_buf
= &txr
->tx_buf_ring
[prod
];
211 tx_buf
->nr_frags
= last_frag
;
215 if (skb_vlan_tag_present(skb
)) {
216 vlan_tag_flags
= TX_BD_CFA_META_KEY_VLAN
|
217 skb_vlan_tag_get(skb
);
218 /* Currently supports 8021Q, 8021AD vlan offloads
219 * QINQ1, QINQ2, QINQ3 vlan headers are deprecated
221 if (skb
->vlan_proto
== htons(ETH_P_8021Q
))
222 vlan_tag_flags
|= 1 << TX_BD_CFA_META_TPID_SHIFT
;
225 if (free_size
== bp
->tx_ring_size
&& length
<= bp
->tx_push_thresh
) {
226 struct tx_push_bd
*push
= txr
->tx_push
;
227 struct tx_bd
*tx_push
= &push
->txbd1
;
228 struct tx_bd_ext
*tx_push1
= &push
->txbd2
;
229 void *pdata
= tx_push1
+ 1;
232 /* Set COAL_NOW to be ready quickly for the next push */
233 tx_push
->tx_bd_len_flags_type
=
234 cpu_to_le32((length
<< TX_BD_LEN_SHIFT
) |
235 TX_BD_TYPE_LONG_TX_BD
|
236 TX_BD_FLAGS_LHINT_512_AND_SMALLER
|
237 TX_BD_FLAGS_COAL_NOW
|
238 TX_BD_FLAGS_PACKET_END
|
239 (2 << TX_BD_FLAGS_BD_CNT_SHIFT
));
241 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
242 tx_push1
->tx_bd_hsize_lflags
=
243 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
245 tx_push1
->tx_bd_hsize_lflags
= 0;
247 tx_push1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
248 tx_push1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
250 skb_copy_from_linear_data(skb
, pdata
, len
);
252 for (j
= 0; j
< last_frag
; j
++) {
253 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[j
];
256 fptr
= skb_frag_address_safe(frag
);
260 memcpy(pdata
, fptr
, skb_frag_size(frag
));
261 pdata
+= skb_frag_size(frag
);
264 memcpy(txbd
, tx_push
, sizeof(*txbd
));
265 prod
= NEXT_TX(prod
);
266 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
267 memcpy(txbd
, tx_push1
, sizeof(*txbd
));
268 prod
= NEXT_TX(prod
);
270 cpu_to_le32(DB_KEY_TX_PUSH
| DB_LONG_TX_PUSH
| prod
);
273 netdev_tx_sent_queue(txq
, skb
->len
);
275 __iowrite64_copy(txr
->tx_doorbell
, push
,
276 (length
+ sizeof(*push
) + 8) / 8);
284 if (length
< BNXT_MIN_PKT_SIZE
) {
285 pad
= BNXT_MIN_PKT_SIZE
- length
;
286 if (skb_pad(skb
, pad
)) {
287 /* SKB already freed. */
291 length
= BNXT_MIN_PKT_SIZE
;
294 mapping
= dma_map_single(&pdev
->dev
, skb
->data
, len
, DMA_TO_DEVICE
);
296 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
))) {
297 dev_kfree_skb_any(skb
);
302 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
303 flags
= (len
<< TX_BD_LEN_SHIFT
) | TX_BD_TYPE_LONG_TX_BD
|
304 ((last_frag
+ 2) << TX_BD_FLAGS_BD_CNT_SHIFT
);
306 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
308 prod
= NEXT_TX(prod
);
309 txbd1
= (struct tx_bd_ext
*)
310 &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
312 txbd1
->tx_bd_hsize_lflags
= 0;
313 if (skb_is_gso(skb
)) {
316 if (skb
->encapsulation
)
317 hdr_len
= skb_inner_network_offset(skb
) +
318 skb_inner_network_header_len(skb
) +
319 inner_tcp_hdrlen(skb
);
321 hdr_len
= skb_transport_offset(skb
) +
324 txbd1
->tx_bd_hsize_lflags
= cpu_to_le32(TX_BD_FLAGS_LSO
|
326 (hdr_len
<< (TX_BD_HSIZE_SHIFT
- 1)));
327 length
= skb_shinfo(skb
)->gso_size
;
328 txbd1
->tx_bd_mss
= cpu_to_le32(length
);
330 } else if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
331 txbd1
->tx_bd_hsize_lflags
=
332 cpu_to_le32(TX_BD_FLAGS_TCP_UDP_CHKSUM
);
333 txbd1
->tx_bd_mss
= 0;
337 flags
|= bnxt_lhint_arr
[length
];
338 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
340 txbd1
->tx_bd_cfa_meta
= cpu_to_le32(vlan_tag_flags
);
341 txbd1
->tx_bd_cfa_action
= cpu_to_le32(cfa_action
);
342 for (i
= 0; i
< last_frag
; i
++) {
343 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
345 prod
= NEXT_TX(prod
);
346 txbd
= &txr
->tx_desc_ring
[TX_RING(prod
)][TX_IDX(prod
)];
348 len
= skb_frag_size(frag
);
349 mapping
= skb_frag_dma_map(&pdev
->dev
, frag
, 0, len
,
352 if (unlikely(dma_mapping_error(&pdev
->dev
, mapping
)))
355 tx_buf
= &txr
->tx_buf_ring
[prod
];
356 dma_unmap_addr_set(tx_buf
, mapping
, mapping
);
358 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
360 flags
= len
<< TX_BD_LEN_SHIFT
;
361 txbd
->tx_bd_len_flags_type
= cpu_to_le32(flags
);
365 txbd
->tx_bd_len_flags_type
=
366 cpu_to_le32(((len
+ pad
) << TX_BD_LEN_SHIFT
) | flags
|
367 TX_BD_FLAGS_PACKET_END
);
369 netdev_tx_sent_queue(txq
, skb
->len
);
371 /* Sync BD data before updating doorbell */
374 prod
= NEXT_TX(prod
);
377 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
378 writel(DB_KEY_TX
| prod
, txr
->tx_doorbell
);
384 if (unlikely(bnxt_tx_avail(bp
, txr
) <= MAX_SKB_FRAGS
+ 1)) {
385 netif_tx_stop_queue(txq
);
387 /* netif_tx_stop_queue() must be done before checking
388 * tx index in bnxt_tx_avail() below, because in
389 * bnxt_tx_int(), we update tx index before checking for
390 * netif_tx_queue_stopped().
393 if (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)
394 netif_tx_wake_queue(txq
);
401 /* start back at beginning and unmap skb */
403 tx_buf
= &txr
->tx_buf_ring
[prod
];
405 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
406 skb_headlen(skb
), PCI_DMA_TODEVICE
);
407 prod
= NEXT_TX(prod
);
409 /* unmap remaining mapped pages */
410 for (i
= 0; i
< last_frag
; i
++) {
411 prod
= NEXT_TX(prod
);
412 tx_buf
= &txr
->tx_buf_ring
[prod
];
413 dma_unmap_page(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
414 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
418 dev_kfree_skb_any(skb
);
422 static void bnxt_tx_int(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int nr_pkts
)
424 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
425 int index
= txr
- &bp
->tx_ring
[0];
426 struct netdev_queue
*txq
= netdev_get_tx_queue(bp
->dev
, index
);
427 u16 cons
= txr
->tx_cons
;
428 struct pci_dev
*pdev
= bp
->pdev
;
430 unsigned int tx_bytes
= 0;
432 for (i
= 0; i
< nr_pkts
; i
++) {
433 struct bnxt_sw_tx_bd
*tx_buf
;
437 tx_buf
= &txr
->tx_buf_ring
[cons
];
438 cons
= NEXT_TX(cons
);
442 if (tx_buf
->is_push
) {
447 dma_unmap_single(&pdev
->dev
, dma_unmap_addr(tx_buf
, mapping
),
448 skb_headlen(skb
), PCI_DMA_TODEVICE
);
449 last
= tx_buf
->nr_frags
;
451 for (j
= 0; j
< last
; j
++) {
452 cons
= NEXT_TX(cons
);
453 tx_buf
= &txr
->tx_buf_ring
[cons
];
456 dma_unmap_addr(tx_buf
, mapping
),
457 skb_frag_size(&skb_shinfo(skb
)->frags
[j
]),
462 cons
= NEXT_TX(cons
);
464 tx_bytes
+= skb
->len
;
465 dev_kfree_skb_any(skb
);
468 netdev_tx_completed_queue(txq
, nr_pkts
, tx_bytes
);
471 /* Need to make the tx_cons update visible to bnxt_start_xmit()
472 * before checking for netif_tx_queue_stopped(). Without the
473 * memory barrier, there is a small possibility that bnxt_start_xmit()
474 * will miss it and cause the queue to be stopped forever.
478 if (unlikely(netif_tx_queue_stopped(txq
)) &&
479 (bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
)) {
480 __netif_tx_lock(txq
, smp_processor_id());
481 if (netif_tx_queue_stopped(txq
) &&
482 bnxt_tx_avail(bp
, txr
) > bp
->tx_wake_thresh
&&
483 txr
->dev_state
!= BNXT_DEV_STATE_CLOSING
)
484 netif_tx_wake_queue(txq
);
485 __netif_tx_unlock(txq
);
489 static inline u8
*__bnxt_alloc_rx_data(struct bnxt
*bp
, dma_addr_t
*mapping
,
493 struct pci_dev
*pdev
= bp
->pdev
;
495 data
= kmalloc(bp
->rx_buf_size
, gfp
);
499 *mapping
= dma_map_single(&pdev
->dev
, data
+ BNXT_RX_DMA_OFFSET
,
500 bp
->rx_buf_use_size
, PCI_DMA_FROMDEVICE
);
502 if (dma_mapping_error(&pdev
->dev
, *mapping
)) {
509 static inline int bnxt_alloc_rx_data(struct bnxt
*bp
,
510 struct bnxt_rx_ring_info
*rxr
,
513 struct rx_bd
*rxbd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
514 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[prod
];
518 data
= __bnxt_alloc_rx_data(bp
, &mapping
, gfp
);
523 dma_unmap_addr_set(rx_buf
, mapping
, mapping
);
525 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
530 static void bnxt_reuse_rx_data(struct bnxt_rx_ring_info
*rxr
, u16 cons
,
533 u16 prod
= rxr
->rx_prod
;
534 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
535 struct rx_bd
*cons_bd
, *prod_bd
;
537 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
538 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
540 prod_rx_buf
->data
= data
;
542 dma_unmap_addr_set(prod_rx_buf
, mapping
,
543 dma_unmap_addr(cons_rx_buf
, mapping
));
545 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
546 cons_bd
= &rxr
->rx_desc_ring
[RX_RING(cons
)][RX_IDX(cons
)];
548 prod_bd
->rx_bd_haddr
= cons_bd
->rx_bd_haddr
;
551 static inline u16
bnxt_find_next_agg_idx(struct bnxt_rx_ring_info
*rxr
, u16 idx
)
553 u16 next
, max
= rxr
->rx_agg_bmap_size
;
555 next
= find_next_zero_bit(rxr
->rx_agg_bmap
, max
, idx
);
557 next
= find_first_zero_bit(rxr
->rx_agg_bmap
, max
);
561 static inline int bnxt_alloc_rx_page(struct bnxt
*bp
,
562 struct bnxt_rx_ring_info
*rxr
,
566 &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
567 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
;
568 struct pci_dev
*pdev
= bp
->pdev
;
571 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
573 page
= alloc_page(gfp
);
577 mapping
= dma_map_page(&pdev
->dev
, page
, 0, PAGE_SIZE
,
579 if (dma_mapping_error(&pdev
->dev
, mapping
)) {
584 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
585 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
587 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
588 rx_agg_buf
= &rxr
->rx_agg_ring
[sw_prod
];
589 rxr
->rx_sw_agg_prod
= NEXT_RX_AGG(sw_prod
);
591 rx_agg_buf
->page
= page
;
592 rx_agg_buf
->mapping
= mapping
;
593 rxbd
->rx_bd_haddr
= cpu_to_le64(mapping
);
594 rxbd
->rx_bd_opaque
= sw_prod
;
598 static void bnxt_reuse_rx_agg_bufs(struct bnxt_napi
*bnapi
, u16 cp_cons
,
601 struct bnxt
*bp
= bnapi
->bp
;
602 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
603 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
604 u16 prod
= rxr
->rx_agg_prod
;
605 u16 sw_prod
= rxr
->rx_sw_agg_prod
;
608 for (i
= 0; i
< agg_bufs
; i
++) {
610 struct rx_agg_cmp
*agg
;
611 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
, *prod_rx_buf
;
612 struct rx_bd
*prod_bd
;
615 agg
= (struct rx_agg_cmp
*)
616 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
617 cons
= agg
->rx_agg_cmp_opaque
;
618 __clear_bit(cons
, rxr
->rx_agg_bmap
);
620 if (unlikely(test_bit(sw_prod
, rxr
->rx_agg_bmap
)))
621 sw_prod
= bnxt_find_next_agg_idx(rxr
, sw_prod
);
623 __set_bit(sw_prod
, rxr
->rx_agg_bmap
);
624 prod_rx_buf
= &rxr
->rx_agg_ring
[sw_prod
];
625 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
627 /* It is possible for sw_prod to be equal to cons, so
628 * set cons_rx_buf->page to NULL first.
630 page
= cons_rx_buf
->page
;
631 cons_rx_buf
->page
= NULL
;
632 prod_rx_buf
->page
= page
;
634 prod_rx_buf
->mapping
= cons_rx_buf
->mapping
;
636 prod_bd
= &rxr
->rx_agg_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
638 prod_bd
->rx_bd_haddr
= cpu_to_le64(cons_rx_buf
->mapping
);
639 prod_bd
->rx_bd_opaque
= sw_prod
;
641 prod
= NEXT_RX_AGG(prod
);
642 sw_prod
= NEXT_RX_AGG(sw_prod
);
643 cp_cons
= NEXT_CMP(cp_cons
);
645 rxr
->rx_agg_prod
= prod
;
646 rxr
->rx_sw_agg_prod
= sw_prod
;
649 static struct sk_buff
*bnxt_rx_skb(struct bnxt
*bp
,
650 struct bnxt_rx_ring_info
*rxr
, u16 cons
,
651 u16 prod
, u8
*data
, dma_addr_t dma_addr
,
657 err
= bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_ATOMIC
);
659 bnxt_reuse_rx_data(rxr
, cons
, data
);
663 skb
= build_skb(data
, 0);
664 dma_unmap_single(&bp
->pdev
->dev
, dma_addr
, bp
->rx_buf_use_size
,
671 skb_reserve(skb
, BNXT_RX_OFFSET
);
676 static struct sk_buff
*bnxt_rx_pages(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
677 struct sk_buff
*skb
, u16 cp_cons
,
680 struct pci_dev
*pdev
= bp
->pdev
;
681 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
682 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
683 u16 prod
= rxr
->rx_agg_prod
;
686 for (i
= 0; i
< agg_bufs
; i
++) {
688 struct rx_agg_cmp
*agg
;
689 struct bnxt_sw_rx_agg_bd
*cons_rx_buf
;
693 agg
= (struct rx_agg_cmp
*)
694 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
695 cons
= agg
->rx_agg_cmp_opaque
;
696 frag_len
= (le32_to_cpu(agg
->rx_agg_cmp_len_flags_type
) &
697 RX_AGG_CMP_LEN
) >> RX_AGG_CMP_LEN_SHIFT
;
699 cons_rx_buf
= &rxr
->rx_agg_ring
[cons
];
700 skb_fill_page_desc(skb
, i
, cons_rx_buf
->page
, 0, frag_len
);
701 __clear_bit(cons
, rxr
->rx_agg_bmap
);
703 /* It is possible for bnxt_alloc_rx_page() to allocate
704 * a sw_prod index that equals the cons index, so we
705 * need to clear the cons entry now.
707 mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
708 page
= cons_rx_buf
->page
;
709 cons_rx_buf
->page
= NULL
;
711 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_ATOMIC
) != 0) {
712 struct skb_shared_info
*shinfo
;
713 unsigned int nr_frags
;
715 shinfo
= skb_shinfo(skb
);
716 nr_frags
= --shinfo
->nr_frags
;
717 __skb_frag_set_page(&shinfo
->frags
[nr_frags
], NULL
);
721 cons_rx_buf
->page
= page
;
723 /* Update prod since possibly some pages have been
726 rxr
->rx_agg_prod
= prod
;
727 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
- i
);
731 dma_unmap_page(&pdev
->dev
, mapping
, PAGE_SIZE
,
734 skb
->data_len
+= frag_len
;
735 skb
->len
+= frag_len
;
736 skb
->truesize
+= PAGE_SIZE
;
738 prod
= NEXT_RX_AGG(prod
);
739 cp_cons
= NEXT_CMP(cp_cons
);
741 rxr
->rx_agg_prod
= prod
;
745 static int bnxt_agg_bufs_valid(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
,
746 u8 agg_bufs
, u32
*raw_cons
)
749 struct rx_agg_cmp
*agg
;
751 *raw_cons
= ADV_RAW_CMP(*raw_cons
, agg_bufs
);
752 last
= RING_CMP(*raw_cons
);
753 agg
= (struct rx_agg_cmp
*)
754 &cpr
->cp_desc_ring
[CP_RING(last
)][CP_IDX(last
)];
755 return RX_AGG_CMP_VALID(agg
, *raw_cons
);
758 static inline struct sk_buff
*bnxt_copy_skb(struct bnxt_napi
*bnapi
, u8
*data
,
762 struct bnxt
*bp
= bnapi
->bp
;
763 struct pci_dev
*pdev
= bp
->pdev
;
766 skb
= napi_alloc_skb(&bnapi
->napi
, len
);
770 dma_sync_single_for_cpu(&pdev
->dev
, mapping
,
771 bp
->rx_copy_thresh
, PCI_DMA_FROMDEVICE
);
773 memcpy(skb
->data
- BNXT_RX_OFFSET
, data
, len
+ BNXT_RX_OFFSET
);
775 dma_sync_single_for_device(&pdev
->dev
, mapping
,
783 static void bnxt_tpa_start(struct bnxt
*bp
, struct bnxt_rx_ring_info
*rxr
,
784 struct rx_tpa_start_cmp
*tpa_start
,
785 struct rx_tpa_start_cmp_ext
*tpa_start1
)
787 u8 agg_id
= TPA_START_AGG_ID(tpa_start
);
789 struct bnxt_tpa_info
*tpa_info
;
790 struct bnxt_sw_rx_bd
*cons_rx_buf
, *prod_rx_buf
;
791 struct rx_bd
*prod_bd
;
794 cons
= tpa_start
->rx_tpa_start_cmp_opaque
;
796 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
797 prod_rx_buf
= &rxr
->rx_buf_ring
[prod
];
798 tpa_info
= &rxr
->rx_tpa
[agg_id
];
800 prod_rx_buf
->data
= tpa_info
->data
;
802 mapping
= tpa_info
->mapping
;
803 dma_unmap_addr_set(prod_rx_buf
, mapping
, mapping
);
805 prod_bd
= &rxr
->rx_desc_ring
[RX_RING(prod
)][RX_IDX(prod
)];
807 prod_bd
->rx_bd_haddr
= cpu_to_le64(mapping
);
809 tpa_info
->data
= cons_rx_buf
->data
;
810 cons_rx_buf
->data
= NULL
;
811 tpa_info
->mapping
= dma_unmap_addr(cons_rx_buf
, mapping
);
814 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_len_flags_type
) >>
815 RX_TPA_START_CMP_LEN_SHIFT
;
816 if (likely(TPA_START_HASH_VALID(tpa_start
))) {
817 u32 hash_type
= TPA_START_HASH_TYPE(tpa_start
);
819 tpa_info
->hash_type
= PKT_HASH_TYPE_L4
;
820 tpa_info
->gso_type
= SKB_GSO_TCPV4
;
821 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
823 tpa_info
->gso_type
= SKB_GSO_TCPV6
;
825 le32_to_cpu(tpa_start
->rx_tpa_start_cmp_rss_hash
);
827 tpa_info
->hash_type
= PKT_HASH_TYPE_NONE
;
828 tpa_info
->gso_type
= 0;
829 if (netif_msg_rx_err(bp
))
830 netdev_warn(bp
->dev
, "TPA packet without valid hash\n");
832 tpa_info
->flags2
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_flags2
);
833 tpa_info
->metadata
= le32_to_cpu(tpa_start1
->rx_tpa_start_cmp_metadata
);
835 rxr
->rx_prod
= NEXT_RX(prod
);
836 cons
= NEXT_RX(cons
);
837 cons_rx_buf
= &rxr
->rx_buf_ring
[cons
];
839 bnxt_reuse_rx_data(rxr
, cons
, cons_rx_buf
->data
);
840 rxr
->rx_prod
= NEXT_RX(rxr
->rx_prod
);
841 cons_rx_buf
->data
= NULL
;
844 static void bnxt_abort_tpa(struct bnxt
*bp
, struct bnxt_napi
*bnapi
,
845 u16 cp_cons
, u32 agg_bufs
)
848 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
851 #define BNXT_IPV4_HDR_SIZE (sizeof(struct iphdr) + sizeof(struct tcphdr))
852 #define BNXT_IPV6_HDR_SIZE (sizeof(struct ipv6hdr) + sizeof(struct tcphdr))
854 static inline struct sk_buff
*bnxt_gro_skb(struct bnxt_tpa_info
*tpa_info
,
855 struct rx_tpa_end_cmp
*tpa_end
,
856 struct rx_tpa_end_cmp_ext
*tpa_end1
,
861 int payload_off
, tcp_opt_len
= 0;
865 segs
= TPA_END_TPA_SEGS(tpa_end
);
869 NAPI_GRO_CB(skb
)->count
= segs
;
870 skb_shinfo(skb
)->gso_size
=
871 le32_to_cpu(tpa_end1
->rx_tpa_end_cmp_seg_len
);
872 skb_shinfo(skb
)->gso_type
= tpa_info
->gso_type
;
873 payload_off
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
874 RX_TPA_END_CMP_PAYLOAD_OFFSET
) >>
875 RX_TPA_END_CMP_PAYLOAD_OFFSET_SHIFT
;
876 if (TPA_END_GRO_TS(tpa_end
))
879 if (tpa_info
->gso_type
== SKB_GSO_TCPV4
) {
882 nw_off
= payload_off
- BNXT_IPV4_HDR_SIZE
- tcp_opt_len
-
884 skb_set_network_header(skb
, nw_off
);
886 skb_set_transport_header(skb
, nw_off
+ sizeof(struct iphdr
));
887 len
= skb
->len
- skb_transport_offset(skb
);
889 th
->check
= ~tcp_v4_check(len
, iph
->saddr
, iph
->daddr
, 0);
890 } else if (tpa_info
->gso_type
== SKB_GSO_TCPV6
) {
893 nw_off
= payload_off
- BNXT_IPV6_HDR_SIZE
- tcp_opt_len
-
895 skb_set_network_header(skb
, nw_off
);
897 skb_set_transport_header(skb
, nw_off
+ sizeof(struct ipv6hdr
));
898 len
= skb
->len
- skb_transport_offset(skb
);
900 th
->check
= ~tcp_v6_check(len
, &iph
->saddr
, &iph
->daddr
, 0);
902 dev_kfree_skb_any(skb
);
905 tcp_gro_complete(skb
);
907 if (nw_off
) { /* tunnel */
908 struct udphdr
*uh
= NULL
;
910 if (skb
->protocol
== htons(ETH_P_IP
)) {
911 struct iphdr
*iph
= (struct iphdr
*)skb
->data
;
913 if (iph
->protocol
== IPPROTO_UDP
)
914 uh
= (struct udphdr
*)(iph
+ 1);
916 struct ipv6hdr
*iph
= (struct ipv6hdr
*)skb
->data
;
918 if (iph
->nexthdr
== IPPROTO_UDP
)
919 uh
= (struct udphdr
*)(iph
+ 1);
923 skb_shinfo(skb
)->gso_type
|=
924 SKB_GSO_UDP_TUNNEL_CSUM
;
926 skb_shinfo(skb
)->gso_type
|= SKB_GSO_UDP_TUNNEL
;
933 static inline struct sk_buff
*bnxt_tpa_end(struct bnxt
*bp
,
934 struct bnxt_napi
*bnapi
,
936 struct rx_tpa_end_cmp
*tpa_end
,
937 struct rx_tpa_end_cmp_ext
*tpa_end1
,
940 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
941 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
942 u8 agg_id
= TPA_END_AGG_ID(tpa_end
);
944 u16 cp_cons
= RING_CMP(*raw_cons
);
946 struct bnxt_tpa_info
*tpa_info
;
950 tpa_info
= &rxr
->rx_tpa
[agg_id
];
951 data
= tpa_info
->data
;
954 mapping
= tpa_info
->mapping
;
956 agg_bufs
= (le32_to_cpu(tpa_end
->rx_tpa_end_cmp_misc_v1
) &
957 RX_TPA_END_CMP_AGG_BUFS
) >> RX_TPA_END_CMP_AGG_BUFS_SHIFT
;
960 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, raw_cons
))
961 return ERR_PTR(-EBUSY
);
964 cp_cons
= NEXT_CMP(cp_cons
);
967 if (unlikely(agg_bufs
> MAX_SKB_FRAGS
)) {
968 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
969 netdev_warn(bp
->dev
, "TPA frags %d exceeded MAX_SKB_FRAGS %d\n",
970 agg_bufs
, (int)MAX_SKB_FRAGS
);
974 if (len
<= bp
->rx_copy_thresh
) {
975 skb
= bnxt_copy_skb(bnapi
, data
, len
, mapping
);
977 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
982 dma_addr_t new_mapping
;
984 new_data
= __bnxt_alloc_rx_data(bp
, &new_mapping
, GFP_ATOMIC
);
986 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
990 tpa_info
->data
= new_data
;
991 tpa_info
->mapping
= new_mapping
;
993 skb
= build_skb(data
, 0);
994 dma_unmap_single(&bp
->pdev
->dev
, mapping
, bp
->rx_buf_use_size
,
999 bnxt_abort_tpa(bp
, bnapi
, cp_cons
, agg_bufs
);
1002 skb_reserve(skb
, BNXT_RX_OFFSET
);
1007 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1009 /* Page reuse already handled by bnxt_rx_pages(). */
1013 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
1015 if (tpa_info
->hash_type
!= PKT_HASH_TYPE_NONE
)
1016 skb_set_hash(skb
, tpa_info
->rss_hash
, tpa_info
->hash_type
);
1018 if (tpa_info
->flags2
& RX_CMP_FLAGS2_META_FORMAT_VLAN
) {
1019 netdev_features_t features
= skb
->dev
->features
;
1020 u16 vlan_proto
= tpa_info
->metadata
>>
1021 RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1023 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1024 vlan_proto
== ETH_P_8021Q
) ||
1025 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1026 vlan_proto
== ETH_P_8021AD
)) {
1027 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1028 tpa_info
->metadata
&
1029 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1033 skb_checksum_none_assert(skb
);
1034 if (likely(tpa_info
->flags2
& RX_TPA_START_CMP_FLAGS2_L4_CS_CALC
)) {
1035 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1037 (tpa_info
->flags2
& RX_CMP_FLAGS2_T_L4_CS_CALC
) >> 3;
1040 if (TPA_END_GRO(tpa_end
))
1041 skb
= bnxt_gro_skb(tpa_info
, tpa_end
, tpa_end1
, skb
);
1046 /* returns the following:
1047 * 1 - 1 packet successfully received
1048 * 0 - successful TPA_START, packet not completed yet
1049 * -EBUSY - completion ring does not have all the agg buffers yet
1050 * -ENOMEM - packet aborted due to out of memory
1051 * -EIO - packet aborted due to hw error indicated in BD
1053 static int bnxt_rx_pkt(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, u32
*raw_cons
,
1056 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1057 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1058 struct net_device
*dev
= bp
->dev
;
1059 struct rx_cmp
*rxcmp
;
1060 struct rx_cmp_ext
*rxcmp1
;
1061 u32 tmp_raw_cons
= *raw_cons
;
1062 u16 cons
, prod
, cp_cons
= RING_CMP(tmp_raw_cons
);
1063 struct bnxt_sw_rx_bd
*rx_buf
;
1065 u8
*data
, agg_bufs
, cmp_type
;
1066 dma_addr_t dma_addr
;
1067 struct sk_buff
*skb
;
1070 rxcmp
= (struct rx_cmp
*)
1071 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1073 tmp_raw_cons
= NEXT_RAW_CMP(tmp_raw_cons
);
1074 cp_cons
= RING_CMP(tmp_raw_cons
);
1075 rxcmp1
= (struct rx_cmp_ext
*)
1076 &cpr
->cp_desc_ring
[CP_RING(cp_cons
)][CP_IDX(cp_cons
)];
1078 if (!RX_CMP_VALID(rxcmp1
, tmp_raw_cons
))
1081 cmp_type
= RX_CMP_TYPE(rxcmp
);
1083 prod
= rxr
->rx_prod
;
1085 if (cmp_type
== CMP_TYPE_RX_L2_TPA_START_CMP
) {
1086 bnxt_tpa_start(bp
, rxr
, (struct rx_tpa_start_cmp
*)rxcmp
,
1087 (struct rx_tpa_start_cmp_ext
*)rxcmp1
);
1089 goto next_rx_no_prod
;
1091 } else if (cmp_type
== CMP_TYPE_RX_L2_TPA_END_CMP
) {
1092 skb
= bnxt_tpa_end(bp
, bnapi
, &tmp_raw_cons
,
1093 (struct rx_tpa_end_cmp
*)rxcmp
,
1094 (struct rx_tpa_end_cmp_ext
*)rxcmp1
,
1097 if (unlikely(IS_ERR(skb
)))
1102 skb_record_rx_queue(skb
, bnapi
->index
);
1103 skb_mark_napi_id(skb
, &bnapi
->napi
);
1104 if (bnxt_busy_polling(bnapi
))
1105 netif_receive_skb(skb
);
1107 napi_gro_receive(&bnapi
->napi
, skb
);
1110 goto next_rx_no_prod
;
1113 cons
= rxcmp
->rx_cmp_opaque
;
1114 rx_buf
= &rxr
->rx_buf_ring
[cons
];
1115 data
= rx_buf
->data
;
1118 agg_bufs
= (le32_to_cpu(rxcmp
->rx_cmp_misc_v1
) & RX_CMP_AGG_BUFS
) >>
1119 RX_CMP_AGG_BUFS_SHIFT
;
1122 if (!bnxt_agg_bufs_valid(bp
, cpr
, agg_bufs
, &tmp_raw_cons
))
1125 cp_cons
= NEXT_CMP(cp_cons
);
1129 rx_buf
->data
= NULL
;
1130 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L2_ERRORS
) {
1131 bnxt_reuse_rx_data(rxr
, cons
, data
);
1133 bnxt_reuse_rx_agg_bufs(bnapi
, cp_cons
, agg_bufs
);
1139 len
= le32_to_cpu(rxcmp
->rx_cmp_len_flags_type
) >> RX_CMP_LEN_SHIFT
;
1140 dma_addr
= dma_unmap_addr(rx_buf
, mapping
);
1142 if (len
<= bp
->rx_copy_thresh
) {
1143 skb
= bnxt_copy_skb(bnapi
, data
, len
, dma_addr
);
1144 bnxt_reuse_rx_data(rxr
, cons
, data
);
1150 skb
= bnxt_rx_skb(bp
, rxr
, cons
, prod
, data
, dma_addr
, len
);
1158 skb
= bnxt_rx_pages(bp
, bnapi
, skb
, cp_cons
, agg_bufs
);
1165 if (RX_CMP_HASH_VALID(rxcmp
)) {
1166 u32 hash_type
= RX_CMP_HASH_TYPE(rxcmp
);
1167 enum pkt_hash_types type
= PKT_HASH_TYPE_L4
;
1169 /* RSS profiles 1 and 3 with extract code 0 for inner 4-tuple */
1170 if (hash_type
!= 1 && hash_type
!= 3)
1171 type
= PKT_HASH_TYPE_L3
;
1172 skb_set_hash(skb
, le32_to_cpu(rxcmp
->rx_cmp_rss_hash
), type
);
1175 skb
->protocol
= eth_type_trans(skb
, dev
);
1177 if (rxcmp1
->rx_cmp_flags2
&
1178 cpu_to_le32(RX_CMP_FLAGS2_META_FORMAT_VLAN
)) {
1179 netdev_features_t features
= skb
->dev
->features
;
1180 u32 meta_data
= le32_to_cpu(rxcmp1
->rx_cmp_meta_data
);
1181 u16 vlan_proto
= meta_data
>> RX_CMP_FLAGS2_METADATA_TPID_SFT
;
1183 if (((features
& NETIF_F_HW_VLAN_CTAG_RX
) &&
1184 vlan_proto
== ETH_P_8021Q
) ||
1185 ((features
& NETIF_F_HW_VLAN_STAG_RX
) &&
1186 vlan_proto
== ETH_P_8021AD
))
1187 __vlan_hwaccel_put_tag(skb
, htons(vlan_proto
),
1189 RX_CMP_FLAGS2_METADATA_VID_MASK
);
1192 skb_checksum_none_assert(skb
);
1193 if (RX_CMP_L4_CS_OK(rxcmp1
)) {
1194 if (dev
->features
& NETIF_F_RXCSUM
) {
1195 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1196 skb
->csum_level
= RX_CMP_ENCAP(rxcmp1
);
1199 if (rxcmp1
->rx_cmp_cfa_code_errors_v2
& RX_CMP_L4_CS_ERR_BITS
) {
1200 if (dev
->features
& NETIF_F_RXCSUM
)
1201 cpr
->rx_l4_csum_errors
++;
1205 skb_record_rx_queue(skb
, bnapi
->index
);
1206 skb_mark_napi_id(skb
, &bnapi
->napi
);
1207 if (bnxt_busy_polling(bnapi
))
1208 netif_receive_skb(skb
);
1210 napi_gro_receive(&bnapi
->napi
, skb
);
1214 rxr
->rx_prod
= NEXT_RX(prod
);
1217 *raw_cons
= tmp_raw_cons
;
1222 static int bnxt_async_event_process(struct bnxt
*bp
,
1223 struct hwrm_async_event_cmpl
*cmpl
)
1225 u16 event_id
= le16_to_cpu(cmpl
->event_id
);
1227 /* TODO CHIMP_FW: Define event id's for link change, error etc */
1229 case HWRM_ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE
:
1230 set_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
);
1231 schedule_work(&bp
->sp_task
);
1234 netdev_err(bp
->dev
, "unhandled ASYNC event (id 0x%x)\n",
1241 static int bnxt_hwrm_handler(struct bnxt
*bp
, struct tx_cmp
*txcmp
)
1243 u16 cmpl_type
= TX_CMP_TYPE(txcmp
), vf_id
, seq_id
;
1244 struct hwrm_cmpl
*h_cmpl
= (struct hwrm_cmpl
*)txcmp
;
1245 struct hwrm_fwd_req_cmpl
*fwd_req_cmpl
=
1246 (struct hwrm_fwd_req_cmpl
*)txcmp
;
1248 switch (cmpl_type
) {
1249 case CMPL_BASE_TYPE_HWRM_DONE
:
1250 seq_id
= le16_to_cpu(h_cmpl
->sequence_id
);
1251 if (seq_id
== bp
->hwrm_intr_seq_id
)
1252 bp
->hwrm_intr_seq_id
= HWRM_SEQ_ID_INVALID
;
1254 netdev_err(bp
->dev
, "Invalid hwrm seq id %d\n", seq_id
);
1257 case CMPL_BASE_TYPE_HWRM_FWD_REQ
:
1258 vf_id
= le16_to_cpu(fwd_req_cmpl
->source_id
);
1260 if ((vf_id
< bp
->pf
.first_vf_id
) ||
1261 (vf_id
>= bp
->pf
.first_vf_id
+ bp
->pf
.active_vfs
)) {
1262 netdev_err(bp
->dev
, "Msg contains invalid VF id %x\n",
1267 set_bit(vf_id
- bp
->pf
.first_vf_id
, bp
->pf
.vf_event_bmap
);
1268 set_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
);
1269 schedule_work(&bp
->sp_task
);
1272 case CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
:
1273 bnxt_async_event_process(bp
,
1274 (struct hwrm_async_event_cmpl
*)txcmp
);
1283 static irqreturn_t
bnxt_msix(int irq
, void *dev_instance
)
1285 struct bnxt_napi
*bnapi
= dev_instance
;
1286 struct bnxt
*bp
= bnapi
->bp
;
1287 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1288 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1290 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1291 napi_schedule(&bnapi
->napi
);
1295 static inline int bnxt_has_work(struct bnxt
*bp
, struct bnxt_cp_ring_info
*cpr
)
1297 u32 raw_cons
= cpr
->cp_raw_cons
;
1298 u16 cons
= RING_CMP(raw_cons
);
1299 struct tx_cmp
*txcmp
;
1301 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1303 return TX_CMP_VALID(txcmp
, raw_cons
);
1306 static irqreturn_t
bnxt_inta(int irq
, void *dev_instance
)
1308 struct bnxt_napi
*bnapi
= dev_instance
;
1309 struct bnxt
*bp
= bnapi
->bp
;
1310 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1311 u32 cons
= RING_CMP(cpr
->cp_raw_cons
);
1314 prefetch(&cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)]);
1316 if (!bnxt_has_work(bp
, cpr
)) {
1317 int_status
= readl(bp
->bar0
+ BNXT_CAG_REG_LEGACY_INT_STATUS
);
1318 /* return if erroneous interrupt */
1319 if (!(int_status
& (0x10000 << cpr
->cp_ring_struct
.fw_ring_id
)))
1323 /* disable ring IRQ */
1324 BNXT_CP_DB_IRQ_DIS(cpr
->cp_doorbell
);
1326 /* Return here if interrupt is shared and is disabled. */
1327 if (unlikely(atomic_read(&bp
->intr_sem
) != 0))
1330 napi_schedule(&bnapi
->napi
);
1334 static int bnxt_poll_work(struct bnxt
*bp
, struct bnxt_napi
*bnapi
, int budget
)
1336 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1337 u32 raw_cons
= cpr
->cp_raw_cons
;
1341 bool rx_event
= false;
1342 bool agg_event
= false;
1343 struct tx_cmp
*txcmp
;
1348 cons
= RING_CMP(raw_cons
);
1349 txcmp
= &cpr
->cp_desc_ring
[CP_RING(cons
)][CP_IDX(cons
)];
1351 if (!TX_CMP_VALID(txcmp
, raw_cons
))
1354 if (TX_CMP_TYPE(txcmp
) == CMP_TYPE_TX_L2_CMP
) {
1356 /* return full budget so NAPI will complete. */
1357 if (unlikely(tx_pkts
> bp
->tx_wake_thresh
))
1359 } else if ((TX_CMP_TYPE(txcmp
) & 0x30) == 0x10) {
1360 rc
= bnxt_rx_pkt(bp
, bnapi
, &raw_cons
, &agg_event
);
1361 if (likely(rc
>= 0))
1363 else if (rc
== -EBUSY
) /* partial completion */
1366 } else if (unlikely((TX_CMP_TYPE(txcmp
) ==
1367 CMPL_BASE_TYPE_HWRM_DONE
) ||
1368 (TX_CMP_TYPE(txcmp
) ==
1369 CMPL_BASE_TYPE_HWRM_FWD_REQ
) ||
1370 (TX_CMP_TYPE(txcmp
) ==
1371 CMPL_BASE_TYPE_HWRM_ASYNC_EVENT
))) {
1372 bnxt_hwrm_handler(bp
, txcmp
);
1374 raw_cons
= NEXT_RAW_CMP(raw_cons
);
1376 if (rx_pkts
== budget
)
1380 cpr
->cp_raw_cons
= raw_cons
;
1381 /* ACK completion ring before freeing tx ring and producing new
1382 * buffers in rx/agg rings to prevent overflowing the completion
1385 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1388 bnxt_tx_int(bp
, bnapi
, tx_pkts
);
1391 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
1393 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1394 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
1396 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1397 rxr
->rx_agg_doorbell
);
1398 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
1399 rxr
->rx_agg_doorbell
);
1405 static int bnxt_poll(struct napi_struct
*napi
, int budget
)
1407 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1408 struct bnxt
*bp
= bnapi
->bp
;
1409 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1412 if (!bnxt_lock_napi(bnapi
))
1416 work_done
+= bnxt_poll_work(bp
, bnapi
, budget
- work_done
);
1418 if (work_done
>= budget
)
1421 if (!bnxt_has_work(bp
, cpr
)) {
1422 napi_complete(napi
);
1423 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1428 bnxt_unlock_napi(bnapi
);
1432 #ifdef CONFIG_NET_RX_BUSY_POLL
1433 static int bnxt_busy_poll(struct napi_struct
*napi
)
1435 struct bnxt_napi
*bnapi
= container_of(napi
, struct bnxt_napi
, napi
);
1436 struct bnxt
*bp
= bnapi
->bp
;
1437 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
1438 int rx_work
, budget
= 4;
1440 if (atomic_read(&bp
->intr_sem
) != 0)
1441 return LL_FLUSH_FAILED
;
1443 if (!bnxt_lock_poll(bnapi
))
1444 return LL_FLUSH_BUSY
;
1446 rx_work
= bnxt_poll_work(bp
, bnapi
, budget
);
1448 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
1450 bnxt_unlock_poll(bnapi
);
1455 static void bnxt_free_tx_skbs(struct bnxt
*bp
)
1458 struct pci_dev
*pdev
= bp
->pdev
;
1463 max_idx
= bp
->tx_nr_pages
* TX_DESC_CNT
;
1464 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1465 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1468 for (j
= 0; j
< max_idx
;) {
1469 struct bnxt_sw_tx_bd
*tx_buf
= &txr
->tx_buf_ring
[j
];
1470 struct sk_buff
*skb
= tx_buf
->skb
;
1480 if (tx_buf
->is_push
) {
1486 dma_unmap_single(&pdev
->dev
,
1487 dma_unmap_addr(tx_buf
, mapping
),
1491 last
= tx_buf
->nr_frags
;
1493 for (k
= 0; k
< last
; k
++, j
++) {
1494 int ring_idx
= j
& bp
->tx_ring_mask
;
1495 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[k
];
1497 tx_buf
= &txr
->tx_buf_ring
[ring_idx
];
1500 dma_unmap_addr(tx_buf
, mapping
),
1501 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
1505 netdev_tx_reset_queue(netdev_get_tx_queue(bp
->dev
, i
));
1509 static void bnxt_free_rx_skbs(struct bnxt
*bp
)
1511 int i
, max_idx
, max_agg_idx
;
1512 struct pci_dev
*pdev
= bp
->pdev
;
1517 max_idx
= bp
->rx_nr_pages
* RX_DESC_CNT
;
1518 max_agg_idx
= bp
->rx_agg_nr_pages
* RX_DESC_CNT
;
1519 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1520 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1524 for (j
= 0; j
< MAX_TPA
; j
++) {
1525 struct bnxt_tpa_info
*tpa_info
=
1527 u8
*data
= tpa_info
->data
;
1534 dma_unmap_addr(tpa_info
, mapping
),
1535 bp
->rx_buf_use_size
,
1536 PCI_DMA_FROMDEVICE
);
1538 tpa_info
->data
= NULL
;
1544 for (j
= 0; j
< max_idx
; j
++) {
1545 struct bnxt_sw_rx_bd
*rx_buf
= &rxr
->rx_buf_ring
[j
];
1546 u8
*data
= rx_buf
->data
;
1551 dma_unmap_single(&pdev
->dev
,
1552 dma_unmap_addr(rx_buf
, mapping
),
1553 bp
->rx_buf_use_size
,
1554 PCI_DMA_FROMDEVICE
);
1556 rx_buf
->data
= NULL
;
1561 for (j
= 0; j
< max_agg_idx
; j
++) {
1562 struct bnxt_sw_rx_agg_bd
*rx_agg_buf
=
1563 &rxr
->rx_agg_ring
[j
];
1564 struct page
*page
= rx_agg_buf
->page
;
1569 dma_unmap_page(&pdev
->dev
,
1570 dma_unmap_addr(rx_agg_buf
, mapping
),
1571 PAGE_SIZE
, PCI_DMA_FROMDEVICE
);
1573 rx_agg_buf
->page
= NULL
;
1574 __clear_bit(j
, rxr
->rx_agg_bmap
);
1581 static void bnxt_free_skbs(struct bnxt
*bp
)
1583 bnxt_free_tx_skbs(bp
);
1584 bnxt_free_rx_skbs(bp
);
1587 static void bnxt_free_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1589 struct pci_dev
*pdev
= bp
->pdev
;
1592 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1593 if (!ring
->pg_arr
[i
])
1596 dma_free_coherent(&pdev
->dev
, ring
->page_size
,
1597 ring
->pg_arr
[i
], ring
->dma_arr
[i
]);
1599 ring
->pg_arr
[i
] = NULL
;
1602 dma_free_coherent(&pdev
->dev
, ring
->nr_pages
* 8,
1603 ring
->pg_tbl
, ring
->pg_tbl_map
);
1604 ring
->pg_tbl
= NULL
;
1606 if (ring
->vmem_size
&& *ring
->vmem
) {
1612 static int bnxt_alloc_ring(struct bnxt
*bp
, struct bnxt_ring_struct
*ring
)
1615 struct pci_dev
*pdev
= bp
->pdev
;
1617 if (ring
->nr_pages
> 1) {
1618 ring
->pg_tbl
= dma_alloc_coherent(&pdev
->dev
,
1626 for (i
= 0; i
< ring
->nr_pages
; i
++) {
1627 ring
->pg_arr
[i
] = dma_alloc_coherent(&pdev
->dev
,
1631 if (!ring
->pg_arr
[i
])
1634 if (ring
->nr_pages
> 1)
1635 ring
->pg_tbl
[i
] = cpu_to_le64(ring
->dma_arr
[i
]);
1638 if (ring
->vmem_size
) {
1639 *ring
->vmem
= vzalloc(ring
->vmem_size
);
1646 static void bnxt_free_rx_rings(struct bnxt
*bp
)
1653 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1654 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1655 struct bnxt_ring_struct
*ring
;
1660 kfree(rxr
->rx_agg_bmap
);
1661 rxr
->rx_agg_bmap
= NULL
;
1663 ring
= &rxr
->rx_ring_struct
;
1664 bnxt_free_ring(bp
, ring
);
1666 ring
= &rxr
->rx_agg_ring_struct
;
1667 bnxt_free_ring(bp
, ring
);
1671 static int bnxt_alloc_rx_rings(struct bnxt
*bp
)
1673 int i
, rc
, agg_rings
= 0, tpa_rings
= 0;
1678 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
1681 if (bp
->flags
& BNXT_FLAG_TPA
)
1684 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
1685 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
1686 struct bnxt_ring_struct
*ring
;
1688 ring
= &rxr
->rx_ring_struct
;
1690 rc
= bnxt_alloc_ring(bp
, ring
);
1697 ring
= &rxr
->rx_agg_ring_struct
;
1698 rc
= bnxt_alloc_ring(bp
, ring
);
1702 rxr
->rx_agg_bmap_size
= bp
->rx_agg_ring_mask
+ 1;
1703 mem_size
= rxr
->rx_agg_bmap_size
/ 8;
1704 rxr
->rx_agg_bmap
= kzalloc(mem_size
, GFP_KERNEL
);
1705 if (!rxr
->rx_agg_bmap
)
1709 rxr
->rx_tpa
= kcalloc(MAX_TPA
,
1710 sizeof(struct bnxt_tpa_info
),
1720 static void bnxt_free_tx_rings(struct bnxt
*bp
)
1723 struct pci_dev
*pdev
= bp
->pdev
;
1728 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
1729 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1730 struct bnxt_ring_struct
*ring
;
1733 dma_free_coherent(&pdev
->dev
, bp
->tx_push_size
,
1734 txr
->tx_push
, txr
->tx_push_mapping
);
1735 txr
->tx_push
= NULL
;
1738 ring
= &txr
->tx_ring_struct
;
1740 bnxt_free_ring(bp
, ring
);
1744 static int bnxt_alloc_tx_rings(struct bnxt
*bp
)
1747 struct pci_dev
*pdev
= bp
->pdev
;
1749 bp
->tx_push_size
= 0;
1750 if (bp
->tx_push_thresh
) {
1753 push_size
= L1_CACHE_ALIGN(sizeof(struct tx_push_bd
) +
1754 bp
->tx_push_thresh
);
1756 if (push_size
> 128) {
1758 bp
->tx_push_thresh
= 0;
1761 bp
->tx_push_size
= push_size
;
1764 for (i
= 0, j
= 0; i
< bp
->tx_nr_rings
; i
++) {
1765 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
1766 struct bnxt_ring_struct
*ring
;
1768 ring
= &txr
->tx_ring_struct
;
1770 rc
= bnxt_alloc_ring(bp
, ring
);
1774 if (bp
->tx_push_size
) {
1778 /* One pre-allocated DMA buffer to backup
1781 txr
->tx_push
= dma_alloc_coherent(&pdev
->dev
,
1783 &txr
->tx_push_mapping
,
1789 txbd
= &txr
->tx_push
->txbd1
;
1791 mapping
= txr
->tx_push_mapping
+
1792 sizeof(struct tx_push_bd
);
1793 txbd
->tx_bd_haddr
= cpu_to_le64(mapping
);
1795 memset(txbd
+ 1, 0, sizeof(struct tx_bd_ext
));
1797 ring
->queue_id
= bp
->q_info
[j
].queue_id
;
1798 if (i
% bp
->tx_nr_rings_per_tc
== (bp
->tx_nr_rings_per_tc
- 1))
1804 static void bnxt_free_cp_rings(struct bnxt
*bp
)
1811 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1812 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1813 struct bnxt_cp_ring_info
*cpr
;
1814 struct bnxt_ring_struct
*ring
;
1819 cpr
= &bnapi
->cp_ring
;
1820 ring
= &cpr
->cp_ring_struct
;
1822 bnxt_free_ring(bp
, ring
);
1826 static int bnxt_alloc_cp_rings(struct bnxt
*bp
)
1830 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1831 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1832 struct bnxt_cp_ring_info
*cpr
;
1833 struct bnxt_ring_struct
*ring
;
1838 cpr
= &bnapi
->cp_ring
;
1839 ring
= &cpr
->cp_ring_struct
;
1841 rc
= bnxt_alloc_ring(bp
, ring
);
1848 static void bnxt_init_ring_struct(struct bnxt
*bp
)
1852 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
1853 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
1854 struct bnxt_cp_ring_info
*cpr
;
1855 struct bnxt_rx_ring_info
*rxr
;
1856 struct bnxt_tx_ring_info
*txr
;
1857 struct bnxt_ring_struct
*ring
;
1862 cpr
= &bnapi
->cp_ring
;
1863 ring
= &cpr
->cp_ring_struct
;
1864 ring
->nr_pages
= bp
->cp_nr_pages
;
1865 ring
->page_size
= HW_CMPD_RING_SIZE
;
1866 ring
->pg_arr
= (void **)cpr
->cp_desc_ring
;
1867 ring
->dma_arr
= cpr
->cp_desc_mapping
;
1868 ring
->vmem_size
= 0;
1870 rxr
= bnapi
->rx_ring
;
1874 ring
= &rxr
->rx_ring_struct
;
1875 ring
->nr_pages
= bp
->rx_nr_pages
;
1876 ring
->page_size
= HW_RXBD_RING_SIZE
;
1877 ring
->pg_arr
= (void **)rxr
->rx_desc_ring
;
1878 ring
->dma_arr
= rxr
->rx_desc_mapping
;
1879 ring
->vmem_size
= SW_RXBD_RING_SIZE
* bp
->rx_nr_pages
;
1880 ring
->vmem
= (void **)&rxr
->rx_buf_ring
;
1882 ring
= &rxr
->rx_agg_ring_struct
;
1883 ring
->nr_pages
= bp
->rx_agg_nr_pages
;
1884 ring
->page_size
= HW_RXBD_RING_SIZE
;
1885 ring
->pg_arr
= (void **)rxr
->rx_agg_desc_ring
;
1886 ring
->dma_arr
= rxr
->rx_agg_desc_mapping
;
1887 ring
->vmem_size
= SW_RXBD_AGG_RING_SIZE
* bp
->rx_agg_nr_pages
;
1888 ring
->vmem
= (void **)&rxr
->rx_agg_ring
;
1891 txr
= bnapi
->tx_ring
;
1895 ring
= &txr
->tx_ring_struct
;
1896 ring
->nr_pages
= bp
->tx_nr_pages
;
1897 ring
->page_size
= HW_RXBD_RING_SIZE
;
1898 ring
->pg_arr
= (void **)txr
->tx_desc_ring
;
1899 ring
->dma_arr
= txr
->tx_desc_mapping
;
1900 ring
->vmem_size
= SW_TXBD_RING_SIZE
* bp
->tx_nr_pages
;
1901 ring
->vmem
= (void **)&txr
->tx_buf_ring
;
1905 static void bnxt_init_rxbd_pages(struct bnxt_ring_struct
*ring
, u32 type
)
1909 struct rx_bd
**rx_buf_ring
;
1911 rx_buf_ring
= (struct rx_bd
**)ring
->pg_arr
;
1912 for (i
= 0, prod
= 0; i
< ring
->nr_pages
; i
++) {
1916 rxbd
= rx_buf_ring
[i
];
1920 for (j
= 0; j
< RX_DESC_CNT
; j
++, rxbd
++, prod
++) {
1921 rxbd
->rx_bd_len_flags_type
= cpu_to_le32(type
);
1922 rxbd
->rx_bd_opaque
= prod
;
1927 static int bnxt_init_one_rx_ring(struct bnxt
*bp
, int ring_nr
)
1929 struct net_device
*dev
= bp
->dev
;
1930 struct bnxt_rx_ring_info
*rxr
;
1931 struct bnxt_ring_struct
*ring
;
1935 type
= (bp
->rx_buf_use_size
<< RX_BD_LEN_SHIFT
) |
1936 RX_BD_TYPE_RX_PACKET_BD
| RX_BD_FLAGS_EOP
;
1938 if (NET_IP_ALIGN
== 2)
1939 type
|= RX_BD_FLAGS_SOP
;
1941 rxr
= &bp
->rx_ring
[ring_nr
];
1942 ring
= &rxr
->rx_ring_struct
;
1943 bnxt_init_rxbd_pages(ring
, type
);
1945 prod
= rxr
->rx_prod
;
1946 for (i
= 0; i
< bp
->rx_ring_size
; i
++) {
1947 if (bnxt_alloc_rx_data(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1948 netdev_warn(dev
, "init'ed rx ring %d with %d/%d skbs only\n",
1949 ring_nr
, i
, bp
->rx_ring_size
);
1952 prod
= NEXT_RX(prod
);
1954 rxr
->rx_prod
= prod
;
1955 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1957 ring
= &rxr
->rx_agg_ring_struct
;
1958 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
1960 if (!(bp
->flags
& BNXT_FLAG_AGG_RINGS
))
1963 type
= ((u32
)PAGE_SIZE
<< RX_BD_LEN_SHIFT
) |
1964 RX_BD_TYPE_RX_AGG_BD
| RX_BD_FLAGS_SOP
;
1966 bnxt_init_rxbd_pages(ring
, type
);
1968 prod
= rxr
->rx_agg_prod
;
1969 for (i
= 0; i
< bp
->rx_agg_ring_size
; i
++) {
1970 if (bnxt_alloc_rx_page(bp
, rxr
, prod
, GFP_KERNEL
) != 0) {
1971 netdev_warn(dev
, "init'ed rx ring %d with %d/%d pages only\n",
1972 ring_nr
, i
, bp
->rx_ring_size
);
1975 prod
= NEXT_RX_AGG(prod
);
1977 rxr
->rx_agg_prod
= prod
;
1979 if (bp
->flags
& BNXT_FLAG_TPA
) {
1984 for (i
= 0; i
< MAX_TPA
; i
++) {
1985 data
= __bnxt_alloc_rx_data(bp
, &mapping
,
1990 rxr
->rx_tpa
[i
].data
= data
;
1991 rxr
->rx_tpa
[i
].mapping
= mapping
;
1994 netdev_err(bp
->dev
, "No resource allocated for LRO/GRO\n");
2002 static int bnxt_init_rx_rings(struct bnxt
*bp
)
2006 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2007 rc
= bnxt_init_one_rx_ring(bp
, i
);
2015 static int bnxt_init_tx_rings(struct bnxt
*bp
)
2019 bp
->tx_wake_thresh
= max_t(int, bp
->tx_ring_size
/ 2,
2022 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
2023 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
2024 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
2026 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
2032 static void bnxt_free_ring_grps(struct bnxt
*bp
)
2034 kfree(bp
->grp_info
);
2035 bp
->grp_info
= NULL
;
2038 static int bnxt_init_ring_grps(struct bnxt
*bp
, bool irq_re_init
)
2043 bp
->grp_info
= kcalloc(bp
->cp_nr_rings
,
2044 sizeof(struct bnxt_ring_grp_info
),
2049 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2051 bp
->grp_info
[i
].fw_stats_ctx
= INVALID_HW_RING_ID
;
2052 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
2053 bp
->grp_info
[i
].rx_fw_ring_id
= INVALID_HW_RING_ID
;
2054 bp
->grp_info
[i
].agg_fw_ring_id
= INVALID_HW_RING_ID
;
2055 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
2060 static void bnxt_free_vnics(struct bnxt
*bp
)
2062 kfree(bp
->vnic_info
);
2063 bp
->vnic_info
= NULL
;
2067 static int bnxt_alloc_vnics(struct bnxt
*bp
)
2071 #ifdef CONFIG_RFS_ACCEL
2072 if (bp
->flags
& BNXT_FLAG_RFS
)
2073 num_vnics
+= bp
->rx_nr_rings
;
2076 bp
->vnic_info
= kcalloc(num_vnics
, sizeof(struct bnxt_vnic_info
),
2081 bp
->nr_vnics
= num_vnics
;
2085 static void bnxt_init_vnics(struct bnxt
*bp
)
2089 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2090 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2092 vnic
->fw_vnic_id
= INVALID_HW_RING_ID
;
2093 vnic
->fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
2094 vnic
->fw_l2_ctx_id
= INVALID_HW_RING_ID
;
2096 if (bp
->vnic_info
[i
].rss_hash_key
) {
2098 prandom_bytes(vnic
->rss_hash_key
,
2101 memcpy(vnic
->rss_hash_key
,
2102 bp
->vnic_info
[0].rss_hash_key
,
2108 static int bnxt_calc_nr_ring_pages(u32 ring_size
, int desc_per_pg
)
2112 pages
= ring_size
/ desc_per_pg
;
2119 while (pages
& (pages
- 1))
2125 static void bnxt_set_tpa_flags(struct bnxt
*bp
)
2127 bp
->flags
&= ~BNXT_FLAG_TPA
;
2128 if (bp
->dev
->features
& NETIF_F_LRO
)
2129 bp
->flags
|= BNXT_FLAG_LRO
;
2130 if ((bp
->dev
->features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
2131 bp
->flags
|= BNXT_FLAG_GRO
;
2134 /* bp->rx_ring_size, bp->tx_ring_size, dev->mtu, BNXT_FLAG_{G|L}RO flags must
2137 void bnxt_set_ring_params(struct bnxt
*bp
)
2139 u32 ring_size
, rx_size
, rx_space
;
2140 u32 agg_factor
= 0, agg_ring_size
= 0;
2142 /* 8 for CRC and VLAN */
2143 rx_size
= SKB_DATA_ALIGN(bp
->dev
->mtu
+ ETH_HLEN
+ NET_IP_ALIGN
+ 8);
2145 rx_space
= rx_size
+ NET_SKB_PAD
+
2146 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2148 bp
->rx_copy_thresh
= BNXT_RX_COPY_THRESH
;
2149 ring_size
= bp
->rx_ring_size
;
2150 bp
->rx_agg_ring_size
= 0;
2151 bp
->rx_agg_nr_pages
= 0;
2153 if (bp
->flags
& BNXT_FLAG_TPA
)
2156 bp
->flags
&= ~BNXT_FLAG_JUMBO
;
2157 if (rx_space
> PAGE_SIZE
) {
2160 bp
->flags
|= BNXT_FLAG_JUMBO
;
2161 jumbo_factor
= PAGE_ALIGN(bp
->dev
->mtu
- 40) >> PAGE_SHIFT
;
2162 if (jumbo_factor
> agg_factor
)
2163 agg_factor
= jumbo_factor
;
2165 agg_ring_size
= ring_size
* agg_factor
;
2167 if (agg_ring_size
) {
2168 bp
->rx_agg_nr_pages
= bnxt_calc_nr_ring_pages(agg_ring_size
,
2170 if (bp
->rx_agg_nr_pages
> MAX_RX_AGG_PAGES
) {
2171 u32 tmp
= agg_ring_size
;
2173 bp
->rx_agg_nr_pages
= MAX_RX_AGG_PAGES
;
2174 agg_ring_size
= MAX_RX_AGG_PAGES
* RX_DESC_CNT
- 1;
2175 netdev_warn(bp
->dev
, "rx agg ring size %d reduced to %d.\n",
2176 tmp
, agg_ring_size
);
2178 bp
->rx_agg_ring_size
= agg_ring_size
;
2179 bp
->rx_agg_ring_mask
= (bp
->rx_agg_nr_pages
* RX_DESC_CNT
) - 1;
2180 rx_size
= SKB_DATA_ALIGN(BNXT_RX_COPY_THRESH
+ NET_IP_ALIGN
);
2181 rx_space
= rx_size
+ NET_SKB_PAD
+
2182 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
2185 bp
->rx_buf_use_size
= rx_size
;
2186 bp
->rx_buf_size
= rx_space
;
2188 bp
->rx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, RX_DESC_CNT
);
2189 bp
->rx_ring_mask
= (bp
->rx_nr_pages
* RX_DESC_CNT
) - 1;
2191 ring_size
= bp
->tx_ring_size
;
2192 bp
->tx_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, TX_DESC_CNT
);
2193 bp
->tx_ring_mask
= (bp
->tx_nr_pages
* TX_DESC_CNT
) - 1;
2195 ring_size
= bp
->rx_ring_size
* (2 + agg_factor
) + bp
->tx_ring_size
;
2196 bp
->cp_ring_size
= ring_size
;
2198 bp
->cp_nr_pages
= bnxt_calc_nr_ring_pages(ring_size
, CP_DESC_CNT
);
2199 if (bp
->cp_nr_pages
> MAX_CP_PAGES
) {
2200 bp
->cp_nr_pages
= MAX_CP_PAGES
;
2201 bp
->cp_ring_size
= MAX_CP_PAGES
* CP_DESC_CNT
- 1;
2202 netdev_warn(bp
->dev
, "completion ring size %d reduced to %d.\n",
2203 ring_size
, bp
->cp_ring_size
);
2205 bp
->cp_bit
= bp
->cp_nr_pages
* CP_DESC_CNT
;
2206 bp
->cp_ring_mask
= bp
->cp_bit
- 1;
2209 static void bnxt_free_vnic_attributes(struct bnxt
*bp
)
2212 struct bnxt_vnic_info
*vnic
;
2213 struct pci_dev
*pdev
= bp
->pdev
;
2218 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2219 vnic
= &bp
->vnic_info
[i
];
2221 kfree(vnic
->fw_grp_ids
);
2222 vnic
->fw_grp_ids
= NULL
;
2224 kfree(vnic
->uc_list
);
2225 vnic
->uc_list
= NULL
;
2227 if (vnic
->mc_list
) {
2228 dma_free_coherent(&pdev
->dev
, vnic
->mc_list_size
,
2229 vnic
->mc_list
, vnic
->mc_list_mapping
);
2230 vnic
->mc_list
= NULL
;
2233 if (vnic
->rss_table
) {
2234 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
,
2236 vnic
->rss_table_dma_addr
);
2237 vnic
->rss_table
= NULL
;
2240 vnic
->rss_hash_key
= NULL
;
2245 static int bnxt_alloc_vnic_attributes(struct bnxt
*bp
)
2247 int i
, rc
= 0, size
;
2248 struct bnxt_vnic_info
*vnic
;
2249 struct pci_dev
*pdev
= bp
->pdev
;
2252 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
2253 vnic
= &bp
->vnic_info
[i
];
2255 if (vnic
->flags
& BNXT_VNIC_UCAST_FLAG
) {
2256 int mem_size
= (BNXT_MAX_UC_ADDRS
- 1) * ETH_ALEN
;
2259 vnic
->uc_list
= kmalloc(mem_size
, GFP_KERNEL
);
2260 if (!vnic
->uc_list
) {
2267 if (vnic
->flags
& BNXT_VNIC_MCAST_FLAG
) {
2268 vnic
->mc_list_size
= BNXT_MAX_MC_ADDRS
* ETH_ALEN
;
2270 dma_alloc_coherent(&pdev
->dev
,
2272 &vnic
->mc_list_mapping
,
2274 if (!vnic
->mc_list
) {
2280 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
2281 max_rings
= bp
->rx_nr_rings
;
2285 vnic
->fw_grp_ids
= kcalloc(max_rings
, sizeof(u16
), GFP_KERNEL
);
2286 if (!vnic
->fw_grp_ids
) {
2291 /* Allocate rss table and hash key */
2292 vnic
->rss_table
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2293 &vnic
->rss_table_dma_addr
,
2295 if (!vnic
->rss_table
) {
2300 size
= L1_CACHE_ALIGN(HW_HASH_INDEX_SIZE
* sizeof(u16
));
2302 vnic
->rss_hash_key
= ((void *)vnic
->rss_table
) + size
;
2303 vnic
->rss_hash_key_dma_addr
= vnic
->rss_table_dma_addr
+ size
;
2311 static void bnxt_free_hwrm_resources(struct bnxt
*bp
)
2313 struct pci_dev
*pdev
= bp
->pdev
;
2315 dma_free_coherent(&pdev
->dev
, PAGE_SIZE
, bp
->hwrm_cmd_resp_addr
,
2316 bp
->hwrm_cmd_resp_dma_addr
);
2318 bp
->hwrm_cmd_resp_addr
= NULL
;
2319 if (bp
->hwrm_dbg_resp_addr
) {
2320 dma_free_coherent(&pdev
->dev
, HWRM_DBG_REG_BUF_SIZE
,
2321 bp
->hwrm_dbg_resp_addr
,
2322 bp
->hwrm_dbg_resp_dma_addr
);
2324 bp
->hwrm_dbg_resp_addr
= NULL
;
2328 static int bnxt_alloc_hwrm_resources(struct bnxt
*bp
)
2330 struct pci_dev
*pdev
= bp
->pdev
;
2332 bp
->hwrm_cmd_resp_addr
= dma_alloc_coherent(&pdev
->dev
, PAGE_SIZE
,
2333 &bp
->hwrm_cmd_resp_dma_addr
,
2335 if (!bp
->hwrm_cmd_resp_addr
)
2337 bp
->hwrm_dbg_resp_addr
= dma_alloc_coherent(&pdev
->dev
,
2338 HWRM_DBG_REG_BUF_SIZE
,
2339 &bp
->hwrm_dbg_resp_dma_addr
,
2341 if (!bp
->hwrm_dbg_resp_addr
)
2342 netdev_warn(bp
->dev
, "fail to alloc debug register dma mem\n");
2347 static void bnxt_free_stats(struct bnxt
*bp
)
2350 struct pci_dev
*pdev
= bp
->pdev
;
2355 size
= sizeof(struct ctx_hw_stats
);
2357 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2358 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2359 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2361 if (cpr
->hw_stats
) {
2362 dma_free_coherent(&pdev
->dev
, size
, cpr
->hw_stats
,
2364 cpr
->hw_stats
= NULL
;
2369 static int bnxt_alloc_stats(struct bnxt
*bp
)
2372 struct pci_dev
*pdev
= bp
->pdev
;
2374 size
= sizeof(struct ctx_hw_stats
);
2376 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2377 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2378 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
2380 cpr
->hw_stats
= dma_alloc_coherent(&pdev
->dev
, size
,
2386 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
2391 static void bnxt_clear_ring_indices(struct bnxt
*bp
)
2398 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
2399 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
2400 struct bnxt_cp_ring_info
*cpr
;
2401 struct bnxt_rx_ring_info
*rxr
;
2402 struct bnxt_tx_ring_info
*txr
;
2407 cpr
= &bnapi
->cp_ring
;
2408 cpr
->cp_raw_cons
= 0;
2410 txr
= bnapi
->tx_ring
;
2416 rxr
= bnapi
->rx_ring
;
2419 rxr
->rx_agg_prod
= 0;
2420 rxr
->rx_sw_agg_prod
= 0;
2425 static void bnxt_free_ntp_fltrs(struct bnxt
*bp
, bool irq_reinit
)
2427 #ifdef CONFIG_RFS_ACCEL
2430 /* Under rtnl_lock and all our NAPIs have been disabled. It's
2431 * safe to delete the hash table.
2433 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
2434 struct hlist_head
*head
;
2435 struct hlist_node
*tmp
;
2436 struct bnxt_ntuple_filter
*fltr
;
2438 head
= &bp
->ntp_fltr_hash_tbl
[i
];
2439 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
2440 hlist_del(&fltr
->hash
);
2445 kfree(bp
->ntp_fltr_bmap
);
2446 bp
->ntp_fltr_bmap
= NULL
;
2448 bp
->ntp_fltr_count
= 0;
2452 static int bnxt_alloc_ntp_fltrs(struct bnxt
*bp
)
2454 #ifdef CONFIG_RFS_ACCEL
2457 if (!(bp
->flags
& BNXT_FLAG_RFS
))
2460 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++)
2461 INIT_HLIST_HEAD(&bp
->ntp_fltr_hash_tbl
[i
]);
2463 bp
->ntp_fltr_count
= 0;
2464 bp
->ntp_fltr_bmap
= kzalloc(BITS_TO_LONGS(BNXT_NTP_FLTR_MAX_FLTR
),
2467 if (!bp
->ntp_fltr_bmap
)
2476 static void bnxt_free_mem(struct bnxt
*bp
, bool irq_re_init
)
2478 bnxt_free_vnic_attributes(bp
);
2479 bnxt_free_tx_rings(bp
);
2480 bnxt_free_rx_rings(bp
);
2481 bnxt_free_cp_rings(bp
);
2482 bnxt_free_ntp_fltrs(bp
, irq_re_init
);
2484 bnxt_free_stats(bp
);
2485 bnxt_free_ring_grps(bp
);
2486 bnxt_free_vnics(bp
);
2494 bnxt_clear_ring_indices(bp
);
2498 static int bnxt_alloc_mem(struct bnxt
*bp
, bool irq_re_init
)
2500 int i
, j
, rc
, size
, arr_size
;
2504 /* Allocate bnapi mem pointer array and mem block for
2507 arr_size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
*) *
2509 size
= L1_CACHE_ALIGN(sizeof(struct bnxt_napi
));
2510 bnapi
= kzalloc(arr_size
+ size
* bp
->cp_nr_rings
, GFP_KERNEL
);
2516 for (i
= 0; i
< bp
->cp_nr_rings
; i
++, bnapi
+= size
) {
2517 bp
->bnapi
[i
] = bnapi
;
2518 bp
->bnapi
[i
]->index
= i
;
2519 bp
->bnapi
[i
]->bp
= bp
;
2522 bp
->rx_ring
= kcalloc(bp
->rx_nr_rings
,
2523 sizeof(struct bnxt_rx_ring_info
),
2528 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
2529 bp
->rx_ring
[i
].bnapi
= bp
->bnapi
[i
];
2530 bp
->bnapi
[i
]->rx_ring
= &bp
->rx_ring
[i
];
2533 bp
->tx_ring
= kcalloc(bp
->tx_nr_rings
,
2534 sizeof(struct bnxt_tx_ring_info
),
2539 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
2542 j
= bp
->rx_nr_rings
;
2544 for (i
= 0; i
< bp
->tx_nr_rings
; i
++, j
++) {
2545 bp
->tx_ring
[i
].bnapi
= bp
->bnapi
[j
];
2546 bp
->bnapi
[j
]->tx_ring
= &bp
->tx_ring
[i
];
2549 rc
= bnxt_alloc_stats(bp
);
2553 rc
= bnxt_alloc_ntp_fltrs(bp
);
2557 rc
= bnxt_alloc_vnics(bp
);
2562 bnxt_init_ring_struct(bp
);
2564 rc
= bnxt_alloc_rx_rings(bp
);
2568 rc
= bnxt_alloc_tx_rings(bp
);
2572 rc
= bnxt_alloc_cp_rings(bp
);
2576 bp
->vnic_info
[0].flags
|= BNXT_VNIC_RSS_FLAG
| BNXT_VNIC_MCAST_FLAG
|
2577 BNXT_VNIC_UCAST_FLAG
;
2578 rc
= bnxt_alloc_vnic_attributes(bp
);
2584 bnxt_free_mem(bp
, true);
2588 void bnxt_hwrm_cmd_hdr_init(struct bnxt
*bp
, void *request
, u16 req_type
,
2589 u16 cmpl_ring
, u16 target_id
)
2591 struct hwrm_cmd_req_hdr
*req
= request
;
2593 req
->cmpl_ring_req_type
=
2594 cpu_to_le32(req_type
| (cmpl_ring
<< HWRM_CMPL_RING_SFT
));
2595 req
->target_id_seq_id
= cpu_to_le32(target_id
<< HWRM_TARGET_FID_SFT
);
2596 req
->resp_addr
= cpu_to_le64(bp
->hwrm_cmd_resp_dma_addr
);
2599 int _hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2601 int i
, intr_process
, rc
;
2602 struct hwrm_cmd_req_hdr
*req
= msg
;
2604 __le32
*resp_len
, *valid
;
2605 u16 cp_ring_id
, len
= 0;
2606 struct hwrm_err_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2608 req
->target_id_seq_id
|= cpu_to_le32(bp
->hwrm_cmd_seq
++);
2609 memset(resp
, 0, PAGE_SIZE
);
2610 cp_ring_id
= (le32_to_cpu(req
->cmpl_ring_req_type
) &
2611 HWRM_CMPL_RING_MASK
) >>
2613 intr_process
= (cp_ring_id
== INVALID_HW_RING_ID
) ? 0 : 1;
2615 /* Write request msg to hwrm channel */
2616 __iowrite32_copy(bp
->bar0
, data
, msg_len
/ 4);
2618 for (i
= msg_len
; i
< HWRM_MAX_REQ_LEN
; i
+= 4)
2619 writel(0, bp
->bar0
+ i
);
2621 /* currently supports only one outstanding message */
2623 bp
->hwrm_intr_seq_id
= le32_to_cpu(req
->target_id_seq_id
) &
2626 /* Ring channel doorbell */
2627 writel(1, bp
->bar0
+ 0x100);
2631 /* Wait until hwrm response cmpl interrupt is processed */
2632 while (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
&&
2634 usleep_range(600, 800);
2637 if (bp
->hwrm_intr_seq_id
!= HWRM_SEQ_ID_INVALID
) {
2638 netdev_err(bp
->dev
, "Resp cmpl intr err msg: 0x%x\n",
2639 req
->cmpl_ring_req_type
);
2643 /* Check if response len is updated */
2644 resp_len
= bp
->hwrm_cmd_resp_addr
+ HWRM_RESP_LEN_OFFSET
;
2645 for (i
= 0; i
< timeout
; i
++) {
2646 len
= (le32_to_cpu(*resp_len
) & HWRM_RESP_LEN_MASK
) >>
2650 usleep_range(600, 800);
2654 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d\n",
2655 timeout
, req
->cmpl_ring_req_type
,
2656 req
->target_id_seq_id
, *resp_len
);
2660 /* Last word of resp contains valid bit */
2661 valid
= bp
->hwrm_cmd_resp_addr
+ len
- 4;
2662 for (i
= 0; i
< timeout
; i
++) {
2663 if (le32_to_cpu(*valid
) & HWRM_RESP_VALID_MASK
)
2665 usleep_range(600, 800);
2669 netdev_err(bp
->dev
, "Error (timeout: %d) msg {0x%x 0x%x} len:%d v:%d\n",
2670 timeout
, req
->cmpl_ring_req_type
,
2671 req
->target_id_seq_id
, len
, *valid
);
2676 rc
= le16_to_cpu(resp
->error_code
);
2678 netdev_err(bp
->dev
, "hwrm req_type 0x%x seq id 0x%x error 0x%x\n",
2679 le16_to_cpu(resp
->req_type
),
2680 le16_to_cpu(resp
->seq_id
), rc
);
2686 int hwrm_send_message(struct bnxt
*bp
, void *msg
, u32 msg_len
, int timeout
)
2690 mutex_lock(&bp
->hwrm_cmd_lock
);
2691 rc
= _hwrm_send_message(bp
, msg
, msg_len
, timeout
);
2692 mutex_unlock(&bp
->hwrm_cmd_lock
);
2696 static int bnxt_hwrm_func_drv_rgtr(struct bnxt
*bp
)
2698 struct hwrm_func_drv_rgtr_input req
= {0};
2701 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_RGTR
, -1, -1);
2704 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE
|
2705 FUNC_DRV_RGTR_REQ_ENABLES_VER
|
2706 FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD
);
2708 /* TODO: current async event fwd bits are not defined and the firmware
2709 * only checks if it is non-zero to enable async event forwarding
2711 req
.async_event_fwd
[0] |= cpu_to_le32(1);
2712 req
.os_type
= cpu_to_le16(1);
2713 req
.ver_maj
= DRV_VER_MAJ
;
2714 req
.ver_min
= DRV_VER_MIN
;
2715 req
.ver_upd
= DRV_VER_UPD
;
2718 DECLARE_BITMAP(vf_req_snif_bmap
, 256);
2719 u32
*data
= (u32
*)vf_req_snif_bmap
;
2721 memset(vf_req_snif_bmap
, 0, sizeof(vf_req_snif_bmap
));
2722 for (i
= 0; i
< ARRAY_SIZE(bnxt_vf_req_snif
); i
++)
2723 __set_bit(bnxt_vf_req_snif
[i
], vf_req_snif_bmap
);
2725 for (i
= 0; i
< 8; i
++)
2726 req
.vf_req_fwd
[i
] = cpu_to_le32(data
[i
]);
2729 cpu_to_le32(FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD
);
2732 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2735 static int bnxt_hwrm_func_drv_unrgtr(struct bnxt
*bp
)
2737 struct hwrm_func_drv_unrgtr_input req
= {0};
2739 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_DRV_UNRGTR
, -1, -1);
2740 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2743 static int bnxt_hwrm_tunnel_dst_port_free(struct bnxt
*bp
, u8 tunnel_type
)
2746 struct hwrm_tunnel_dst_port_free_input req
= {0};
2748 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_FREE
, -1, -1);
2749 req
.tunnel_type
= tunnel_type
;
2751 switch (tunnel_type
) {
2752 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
:
2753 req
.tunnel_dst_port_id
= bp
->vxlan_fw_dst_port_id
;
2755 case TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
:
2756 req
.tunnel_dst_port_id
= bp
->nge_fw_dst_port_id
;
2762 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2764 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_free failed. rc:%d\n",
2769 static int bnxt_hwrm_tunnel_dst_port_alloc(struct bnxt
*bp
, __be16 port
,
2773 struct hwrm_tunnel_dst_port_alloc_input req
= {0};
2774 struct hwrm_tunnel_dst_port_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2776 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_TUNNEL_DST_PORT_ALLOC
, -1, -1);
2778 req
.tunnel_type
= tunnel_type
;
2779 req
.tunnel_dst_port_val
= port
;
2781 mutex_lock(&bp
->hwrm_cmd_lock
);
2782 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2784 netdev_err(bp
->dev
, "hwrm_tunnel_dst_port_alloc failed. rc:%d\n",
2789 if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN
)
2790 bp
->vxlan_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2792 else if (tunnel_type
& TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE
)
2793 bp
->nge_fw_dst_port_id
= resp
->tunnel_dst_port_id
;
2795 mutex_unlock(&bp
->hwrm_cmd_lock
);
2799 static int bnxt_hwrm_cfa_l2_set_rx_mask(struct bnxt
*bp
, u16 vnic_id
)
2801 struct hwrm_cfa_l2_set_rx_mask_input req
= {0};
2802 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2804 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_SET_RX_MASK
, -1, -1);
2805 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
2807 req
.num_mc_entries
= cpu_to_le32(vnic
->mc_list_count
);
2808 req
.mc_tbl_addr
= cpu_to_le64(vnic
->mc_list_mapping
);
2809 req
.mask
= cpu_to_le32(vnic
->rx_mask
);
2810 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2813 #ifdef CONFIG_RFS_ACCEL
2814 static int bnxt_hwrm_cfa_ntuple_filter_free(struct bnxt
*bp
,
2815 struct bnxt_ntuple_filter
*fltr
)
2817 struct hwrm_cfa_ntuple_filter_free_input req
= {0};
2819 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_FREE
, -1, -1);
2820 req
.ntuple_filter_id
= fltr
->filter_id
;
2821 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2824 #define BNXT_NTP_FLTR_FLAGS \
2825 (CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID | \
2826 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE | \
2827 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR | \
2828 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE | \
2829 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR | \
2830 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK | \
2831 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR | \
2832 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK | \
2833 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL | \
2834 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT | \
2835 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK | \
2836 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT | \
2837 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK | \
2838 CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID)
2840 static int bnxt_hwrm_cfa_ntuple_filter_alloc(struct bnxt
*bp
,
2841 struct bnxt_ntuple_filter
*fltr
)
2844 struct hwrm_cfa_ntuple_filter_alloc_input req
= {0};
2845 struct hwrm_cfa_ntuple_filter_alloc_output
*resp
=
2846 bp
->hwrm_cmd_resp_addr
;
2847 struct flow_keys
*keys
= &fltr
->fkeys
;
2848 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[fltr
->rxq
+ 1];
2850 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_NTUPLE_FILTER_ALLOC
, -1, -1);
2851 req
.l2_filter_id
= bp
->vnic_info
[0].fw_l2_filter_id
[0];
2853 req
.enables
= cpu_to_le32(BNXT_NTP_FLTR_FLAGS
);
2855 req
.ethertype
= htons(ETH_P_IP
);
2856 memcpy(req
.src_macaddr
, fltr
->src_mac_addr
, ETH_ALEN
);
2857 req
.ip_addr_type
= CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4
;
2858 req
.ip_protocol
= keys
->basic
.ip_proto
;
2860 req
.src_ipaddr
[0] = keys
->addrs
.v4addrs
.src
;
2861 req
.src_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2862 req
.dst_ipaddr
[0] = keys
->addrs
.v4addrs
.dst
;
2863 req
.dst_ipaddr_mask
[0] = cpu_to_be32(0xffffffff);
2865 req
.src_port
= keys
->ports
.src
;
2866 req
.src_port_mask
= cpu_to_be16(0xffff);
2867 req
.dst_port
= keys
->ports
.dst
;
2868 req
.dst_port_mask
= cpu_to_be16(0xffff);
2870 req
.dst_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2871 mutex_lock(&bp
->hwrm_cmd_lock
);
2872 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2874 fltr
->filter_id
= resp
->ntuple_filter_id
;
2875 mutex_unlock(&bp
->hwrm_cmd_lock
);
2880 static int bnxt_hwrm_set_vnic_filter(struct bnxt
*bp
, u16 vnic_id
, u16 idx
,
2884 struct hwrm_cfa_l2_filter_alloc_input req
= {0};
2885 struct hwrm_cfa_l2_filter_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
2887 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_ALLOC
, -1, -1);
2888 req
.flags
= cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX
|
2889 CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST
);
2890 req
.dst_id
= cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
2892 cpu_to_le32(CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR
|
2893 CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID
|
2894 CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK
);
2895 memcpy(req
.l2_addr
, mac_addr
, ETH_ALEN
);
2896 req
.l2_addr_mask
[0] = 0xff;
2897 req
.l2_addr_mask
[1] = 0xff;
2898 req
.l2_addr_mask
[2] = 0xff;
2899 req
.l2_addr_mask
[3] = 0xff;
2900 req
.l2_addr_mask
[4] = 0xff;
2901 req
.l2_addr_mask
[5] = 0xff;
2903 mutex_lock(&bp
->hwrm_cmd_lock
);
2904 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2906 bp
->vnic_info
[vnic_id
].fw_l2_filter_id
[idx
] =
2908 mutex_unlock(&bp
->hwrm_cmd_lock
);
2912 static int bnxt_hwrm_clear_vnic_filter(struct bnxt
*bp
)
2914 u16 i
, j
, num_of_vnics
= 1; /* only vnic 0 supported */
2917 /* Any associated ntuple filters will also be cleared by firmware. */
2918 mutex_lock(&bp
->hwrm_cmd_lock
);
2919 for (i
= 0; i
< num_of_vnics
; i
++) {
2920 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
2922 for (j
= 0; j
< vnic
->uc_filter_count
; j
++) {
2923 struct hwrm_cfa_l2_filter_free_input req
= {0};
2925 bnxt_hwrm_cmd_hdr_init(bp
, &req
,
2926 HWRM_CFA_L2_FILTER_FREE
, -1, -1);
2928 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[j
];
2930 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
2933 vnic
->uc_filter_count
= 0;
2935 mutex_unlock(&bp
->hwrm_cmd_lock
);
2940 static int bnxt_hwrm_vnic_set_tpa(struct bnxt
*bp
, u16 vnic_id
, u32 tpa_flags
)
2942 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2943 struct hwrm_vnic_tpa_cfg_input req
= {0};
2945 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_TPA_CFG
, -1, -1);
2948 u16 mss
= bp
->dev
->mtu
- 40;
2949 u32 nsegs
, n
, segs
= 0, flags
;
2951 flags
= VNIC_TPA_CFG_REQ_FLAGS_TPA
|
2952 VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA
|
2953 VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE
|
2954 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN
|
2955 VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ
;
2956 if (tpa_flags
& BNXT_FLAG_GRO
)
2957 flags
|= VNIC_TPA_CFG_REQ_FLAGS_GRO
;
2959 req
.flags
= cpu_to_le32(flags
);
2962 cpu_to_le32(VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS
|
2963 VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS
|
2964 VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN
);
2966 /* Number of segs are log2 units, and first packet is not
2967 * included as part of this units.
2969 if (mss
<= PAGE_SIZE
) {
2970 n
= PAGE_SIZE
/ mss
;
2971 nsegs
= (MAX_SKB_FRAGS
- 1) * n
;
2973 n
= mss
/ PAGE_SIZE
;
2974 if (mss
& (PAGE_SIZE
- 1))
2976 nsegs
= (MAX_SKB_FRAGS
- n
) / n
;
2979 segs
= ilog2(nsegs
);
2980 req
.max_agg_segs
= cpu_to_le16(segs
);
2981 req
.max_aggs
= cpu_to_le16(VNIC_TPA_CFG_REQ_MAX_AGGS_MAX
);
2983 req
.min_agg_len
= cpu_to_le32(512);
2985 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
2987 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
2990 static int bnxt_hwrm_vnic_set_rss(struct bnxt
*bp
, u16 vnic_id
, bool set_rss
)
2992 u32 i
, j
, max_rings
;
2993 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
2994 struct hwrm_vnic_rss_cfg_input req
= {0};
2996 if (vnic
->fw_rss_cos_lb_ctx
== INVALID_HW_RING_ID
)
2999 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_CFG
, -1, -1);
3001 vnic
->hash_type
= BNXT_RSS_HASH_TYPE_FLAG_IPV4
|
3002 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV4
|
3003 BNXT_RSS_HASH_TYPE_FLAG_IPV6
|
3004 BNXT_RSS_HASH_TYPE_FLAG_TCP_IPV6
;
3006 req
.hash_type
= cpu_to_le32(vnic
->hash_type
);
3008 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3009 max_rings
= bp
->rx_nr_rings
;
3013 /* Fill the RSS indirection table with ring group ids */
3014 for (i
= 0, j
= 0; i
< HW_HASH_INDEX_SIZE
; i
++, j
++) {
3017 vnic
->rss_table
[i
] = cpu_to_le16(vnic
->fw_grp_ids
[j
]);
3020 req
.ring_grp_tbl_addr
= cpu_to_le64(vnic
->rss_table_dma_addr
);
3021 req
.hash_key_tbl_addr
=
3022 cpu_to_le64(vnic
->rss_hash_key_dma_addr
);
3024 req
.rss_ctx_idx
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3025 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3028 static int bnxt_hwrm_vnic_set_hds(struct bnxt
*bp
, u16 vnic_id
)
3030 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3031 struct hwrm_vnic_plcmodes_cfg_input req
= {0};
3033 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_PLCMODES_CFG
, -1, -1);
3034 req
.flags
= cpu_to_le32(VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT
|
3035 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4
|
3036 VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6
);
3038 cpu_to_le32(VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID
|
3039 VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID
);
3040 /* thresholds not implemented in firmware yet */
3041 req
.jumbo_thresh
= cpu_to_le16(bp
->rx_copy_thresh
);
3042 req
.hds_threshold
= cpu_to_le16(bp
->rx_copy_thresh
);
3043 req
.vnic_id
= cpu_to_le32(vnic
->fw_vnic_id
);
3044 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3047 static void bnxt_hwrm_vnic_ctx_free_one(struct bnxt
*bp
, u16 vnic_id
)
3049 struct hwrm_vnic_rss_cos_lb_ctx_free_input req
= {0};
3051 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_FREE
, -1, -1);
3052 req
.rss_cos_lb_ctx_id
=
3053 cpu_to_le16(bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
);
3055 hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3056 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3059 static void bnxt_hwrm_vnic_ctx_free(struct bnxt
*bp
)
3063 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3064 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[i
];
3066 if (vnic
->fw_rss_cos_lb_ctx
!= INVALID_HW_RING_ID
)
3067 bnxt_hwrm_vnic_ctx_free_one(bp
, i
);
3069 bp
->rsscos_nr_ctxs
= 0;
3072 static int bnxt_hwrm_vnic_ctx_alloc(struct bnxt
*bp
, u16 vnic_id
)
3075 struct hwrm_vnic_rss_cos_lb_ctx_alloc_input req
= {0};
3076 struct hwrm_vnic_rss_cos_lb_ctx_alloc_output
*resp
=
3077 bp
->hwrm_cmd_resp_addr
;
3079 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_RSS_COS_LB_CTX_ALLOC
, -1,
3082 mutex_lock(&bp
->hwrm_cmd_lock
);
3083 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3085 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
=
3086 le16_to_cpu(resp
->rss_cos_lb_ctx_id
);
3087 mutex_unlock(&bp
->hwrm_cmd_lock
);
3092 static int bnxt_hwrm_vnic_cfg(struct bnxt
*bp
, u16 vnic_id
)
3094 unsigned int ring
= 0, grp_idx
;
3095 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[vnic_id
];
3096 struct hwrm_vnic_cfg_input req
= {0};
3098 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_CFG
, -1, -1);
3099 /* Only RSS support for now TBD: COS & LB */
3100 req
.enables
= cpu_to_le32(VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP
|
3101 VNIC_CFG_REQ_ENABLES_RSS_RULE
);
3102 req
.rss_rule
= cpu_to_le16(vnic
->fw_rss_cos_lb_ctx
);
3103 req
.cos_rule
= cpu_to_le16(0xffff);
3104 if (vnic
->flags
& BNXT_VNIC_RSS_FLAG
)
3106 else if (vnic
->flags
& BNXT_VNIC_RFS_FLAG
)
3109 grp_idx
= bp
->rx_ring
[ring
].bnapi
->index
;
3110 req
.vnic_id
= cpu_to_le16(vnic
->fw_vnic_id
);
3111 req
.dflt_ring_grp
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_grp_id
);
3113 req
.lb_rule
= cpu_to_le16(0xffff);
3114 req
.mru
= cpu_to_le16(bp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+
3117 if (bp
->flags
& BNXT_FLAG_STRIP_VLAN
)
3118 req
.flags
|= cpu_to_le32(VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE
);
3120 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3123 static int bnxt_hwrm_vnic_free_one(struct bnxt
*bp
, u16 vnic_id
)
3127 if (bp
->vnic_info
[vnic_id
].fw_vnic_id
!= INVALID_HW_RING_ID
) {
3128 struct hwrm_vnic_free_input req
= {0};
3130 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_FREE
, -1, -1);
3132 cpu_to_le32(bp
->vnic_info
[vnic_id
].fw_vnic_id
);
3134 rc
= hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3137 bp
->vnic_info
[vnic_id
].fw_vnic_id
= INVALID_HW_RING_ID
;
3142 static void bnxt_hwrm_vnic_free(struct bnxt
*bp
)
3146 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3147 bnxt_hwrm_vnic_free_one(bp
, i
);
3150 static int bnxt_hwrm_vnic_alloc(struct bnxt
*bp
, u16 vnic_id
,
3151 unsigned int start_rx_ring_idx
,
3152 unsigned int nr_rings
)
3155 unsigned int i
, j
, grp_idx
, end_idx
= start_rx_ring_idx
+ nr_rings
;
3156 struct hwrm_vnic_alloc_input req
= {0};
3157 struct hwrm_vnic_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3159 /* map ring groups to this vnic */
3160 for (i
= start_rx_ring_idx
, j
= 0; i
< end_idx
; i
++, j
++) {
3161 grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3162 if (bp
->grp_info
[grp_idx
].fw_grp_id
== INVALID_HW_RING_ID
) {
3163 netdev_err(bp
->dev
, "Not enough ring groups avail:%x req:%x\n",
3167 bp
->vnic_info
[vnic_id
].fw_grp_ids
[j
] =
3168 bp
->grp_info
[grp_idx
].fw_grp_id
;
3171 bp
->vnic_info
[vnic_id
].fw_rss_cos_lb_ctx
= INVALID_HW_RING_ID
;
3173 req
.flags
= cpu_to_le32(VNIC_ALLOC_REQ_FLAGS_DEFAULT
);
3175 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VNIC_ALLOC
, -1, -1);
3177 mutex_lock(&bp
->hwrm_cmd_lock
);
3178 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3180 bp
->vnic_info
[vnic_id
].fw_vnic_id
= le32_to_cpu(resp
->vnic_id
);
3181 mutex_unlock(&bp
->hwrm_cmd_lock
);
3185 static int bnxt_hwrm_ring_grp_alloc(struct bnxt
*bp
)
3190 mutex_lock(&bp
->hwrm_cmd_lock
);
3191 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3192 struct hwrm_ring_grp_alloc_input req
= {0};
3193 struct hwrm_ring_grp_alloc_output
*resp
=
3194 bp
->hwrm_cmd_resp_addr
;
3195 unsigned int grp_idx
= bp
->rx_ring
[i
].bnapi
->index
;
3197 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_ALLOC
, -1, -1);
3199 req
.cr
= cpu_to_le16(bp
->grp_info
[grp_idx
].cp_fw_ring_id
);
3200 req
.rr
= cpu_to_le16(bp
->grp_info
[grp_idx
].rx_fw_ring_id
);
3201 req
.ar
= cpu_to_le16(bp
->grp_info
[grp_idx
].agg_fw_ring_id
);
3202 req
.sc
= cpu_to_le16(bp
->grp_info
[grp_idx
].fw_stats_ctx
);
3204 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3209 bp
->grp_info
[grp_idx
].fw_grp_id
=
3210 le32_to_cpu(resp
->ring_group_id
);
3212 mutex_unlock(&bp
->hwrm_cmd_lock
);
3216 static int bnxt_hwrm_ring_grp_free(struct bnxt
*bp
)
3220 struct hwrm_ring_grp_free_input req
= {0};
3225 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_GRP_FREE
, -1, -1);
3227 mutex_lock(&bp
->hwrm_cmd_lock
);
3228 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3229 if (bp
->grp_info
[i
].fw_grp_id
== INVALID_HW_RING_ID
)
3232 cpu_to_le32(bp
->grp_info
[i
].fw_grp_id
);
3234 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3238 bp
->grp_info
[i
].fw_grp_id
= INVALID_HW_RING_ID
;
3240 mutex_unlock(&bp
->hwrm_cmd_lock
);
3244 static int hwrm_ring_alloc_send_msg(struct bnxt
*bp
,
3245 struct bnxt_ring_struct
*ring
,
3246 u32 ring_type
, u32 map_index
,
3249 int rc
= 0, err
= 0;
3250 struct hwrm_ring_alloc_input req
= {0};
3251 struct hwrm_ring_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3254 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_ALLOC
, -1, -1);
3257 if (ring
->nr_pages
> 1) {
3258 req
.page_tbl_addr
= cpu_to_le64(ring
->pg_tbl_map
);
3259 /* Page size is in log2 units */
3260 req
.page_size
= BNXT_PAGE_SHIFT
;
3261 req
.page_tbl_depth
= 1;
3263 req
.page_tbl_addr
= cpu_to_le64(ring
->dma_arr
[0]);
3266 /* Association of ring index with doorbell index and MSIX number */
3267 req
.logical_id
= cpu_to_le16(map_index
);
3269 switch (ring_type
) {
3270 case HWRM_RING_ALLOC_TX
:
3271 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_TX
;
3272 /* Association of transmit ring with completion ring */
3274 cpu_to_le16(bp
->grp_info
[map_index
].cp_fw_ring_id
);
3275 req
.length
= cpu_to_le32(bp
->tx_ring_mask
+ 1);
3276 req
.stat_ctx_id
= cpu_to_le32(stats_ctx_id
);
3277 req
.queue_id
= cpu_to_le16(ring
->queue_id
);
3279 case HWRM_RING_ALLOC_RX
:
3280 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3281 req
.length
= cpu_to_le32(bp
->rx_ring_mask
+ 1);
3283 case HWRM_RING_ALLOC_AGG
:
3284 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_RX
;
3285 req
.length
= cpu_to_le32(bp
->rx_agg_ring_mask
+ 1);
3287 case HWRM_RING_ALLOC_CMPL
:
3288 req
.ring_type
= RING_ALLOC_REQ_RING_TYPE_CMPL
;
3289 req
.length
= cpu_to_le32(bp
->cp_ring_mask
+ 1);
3290 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
3291 req
.int_mode
= RING_ALLOC_REQ_INT_MODE_MSIX
;
3294 netdev_err(bp
->dev
, "hwrm alloc invalid ring type %d\n",
3299 mutex_lock(&bp
->hwrm_cmd_lock
);
3300 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3301 err
= le16_to_cpu(resp
->error_code
);
3302 ring_id
= le16_to_cpu(resp
->ring_id
);
3303 mutex_unlock(&bp
->hwrm_cmd_lock
);
3306 switch (ring_type
) {
3307 case RING_FREE_REQ_RING_TYPE_CMPL
:
3308 netdev_err(bp
->dev
, "hwrm_ring_alloc cp failed. rc:%x err:%x\n",
3312 case RING_FREE_REQ_RING_TYPE_RX
:
3313 netdev_err(bp
->dev
, "hwrm_ring_alloc rx failed. rc:%x err:%x\n",
3317 case RING_FREE_REQ_RING_TYPE_TX
:
3318 netdev_err(bp
->dev
, "hwrm_ring_alloc tx failed. rc:%x err:%x\n",
3323 netdev_err(bp
->dev
, "Invalid ring\n");
3327 ring
->fw_ring_id
= ring_id
;
3331 static int bnxt_hwrm_ring_alloc(struct bnxt
*bp
)
3335 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3336 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3337 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3338 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3340 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_CMPL
, i
,
3341 INVALID_STATS_CTX_ID
);
3344 cpr
->cp_doorbell
= bp
->bar1
+ i
* 0x80;
3345 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
3346 bp
->grp_info
[i
].cp_fw_ring_id
= ring
->fw_ring_id
;
3349 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3350 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3351 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3352 u32 map_idx
= txr
->bnapi
->index
;
3353 u16 fw_stats_ctx
= bp
->grp_info
[map_idx
].fw_stats_ctx
;
3355 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_TX
,
3356 map_idx
, fw_stats_ctx
);
3359 txr
->tx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3362 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3363 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3364 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3365 u32 map_idx
= rxr
->bnapi
->index
;
3367 rc
= hwrm_ring_alloc_send_msg(bp
, ring
, HWRM_RING_ALLOC_RX
,
3368 map_idx
, INVALID_STATS_CTX_ID
);
3371 rxr
->rx_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3372 writel(DB_KEY_RX
| rxr
->rx_prod
, rxr
->rx_doorbell
);
3373 bp
->grp_info
[map_idx
].rx_fw_ring_id
= ring
->fw_ring_id
;
3376 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3377 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3378 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3379 struct bnxt_ring_struct
*ring
=
3380 &rxr
->rx_agg_ring_struct
;
3381 u32 grp_idx
= rxr
->bnapi
->index
;
3382 u32 map_idx
= grp_idx
+ bp
->rx_nr_rings
;
3384 rc
= hwrm_ring_alloc_send_msg(bp
, ring
,
3385 HWRM_RING_ALLOC_AGG
,
3387 INVALID_STATS_CTX_ID
);
3391 rxr
->rx_agg_doorbell
= bp
->bar1
+ map_idx
* 0x80;
3392 writel(DB_KEY_RX
| rxr
->rx_agg_prod
,
3393 rxr
->rx_agg_doorbell
);
3394 bp
->grp_info
[grp_idx
].agg_fw_ring_id
= ring
->fw_ring_id
;
3401 static int hwrm_ring_free_send_msg(struct bnxt
*bp
,
3402 struct bnxt_ring_struct
*ring
,
3403 u32 ring_type
, int cmpl_ring_id
)
3406 struct hwrm_ring_free_input req
= {0};
3407 struct hwrm_ring_free_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3410 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_FREE
, cmpl_ring_id
, -1);
3411 req
.ring_type
= ring_type
;
3412 req
.ring_id
= cpu_to_le16(ring
->fw_ring_id
);
3414 mutex_lock(&bp
->hwrm_cmd_lock
);
3415 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3416 error_code
= le16_to_cpu(resp
->error_code
);
3417 mutex_unlock(&bp
->hwrm_cmd_lock
);
3419 if (rc
|| error_code
) {
3420 switch (ring_type
) {
3421 case RING_FREE_REQ_RING_TYPE_CMPL
:
3422 netdev_err(bp
->dev
, "hwrm_ring_free cp failed. rc:%d\n",
3425 case RING_FREE_REQ_RING_TYPE_RX
:
3426 netdev_err(bp
->dev
, "hwrm_ring_free rx failed. rc:%d\n",
3429 case RING_FREE_REQ_RING_TYPE_TX
:
3430 netdev_err(bp
->dev
, "hwrm_ring_free tx failed. rc:%d\n",
3434 netdev_err(bp
->dev
, "Invalid ring\n");
3441 static void bnxt_hwrm_ring_free(struct bnxt
*bp
, bool close_path
)
3448 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
3449 struct bnxt_tx_ring_info
*txr
= &bp
->tx_ring
[i
];
3450 struct bnxt_ring_struct
*ring
= &txr
->tx_ring_struct
;
3451 u32 grp_idx
= txr
->bnapi
->index
;
3452 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3454 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3455 hwrm_ring_free_send_msg(bp
, ring
,
3456 RING_FREE_REQ_RING_TYPE_TX
,
3457 close_path
? cmpl_ring_id
:
3458 INVALID_HW_RING_ID
);
3459 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3463 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3464 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3465 struct bnxt_ring_struct
*ring
= &rxr
->rx_ring_struct
;
3466 u32 grp_idx
= rxr
->bnapi
->index
;
3467 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3469 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3470 hwrm_ring_free_send_msg(bp
, ring
,
3471 RING_FREE_REQ_RING_TYPE_RX
,
3472 close_path
? cmpl_ring_id
:
3473 INVALID_HW_RING_ID
);
3474 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3475 bp
->grp_info
[grp_idx
].rx_fw_ring_id
=
3480 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3481 struct bnxt_rx_ring_info
*rxr
= &bp
->rx_ring
[i
];
3482 struct bnxt_ring_struct
*ring
= &rxr
->rx_agg_ring_struct
;
3483 u32 grp_idx
= rxr
->bnapi
->index
;
3484 u32 cmpl_ring_id
= bp
->grp_info
[grp_idx
].cp_fw_ring_id
;
3486 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3487 hwrm_ring_free_send_msg(bp
, ring
,
3488 RING_FREE_REQ_RING_TYPE_RX
,
3489 close_path
? cmpl_ring_id
:
3490 INVALID_HW_RING_ID
);
3491 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3492 bp
->grp_info
[grp_idx
].agg_fw_ring_id
=
3497 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3498 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3499 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3500 struct bnxt_ring_struct
*ring
= &cpr
->cp_ring_struct
;
3502 if (ring
->fw_ring_id
!= INVALID_HW_RING_ID
) {
3503 hwrm_ring_free_send_msg(bp
, ring
,
3504 RING_FREE_REQ_RING_TYPE_CMPL
,
3505 INVALID_HW_RING_ID
);
3506 ring
->fw_ring_id
= INVALID_HW_RING_ID
;
3507 bp
->grp_info
[i
].cp_fw_ring_id
= INVALID_HW_RING_ID
;
3512 int bnxt_hwrm_set_coal(struct bnxt
*bp
)
3515 struct hwrm_ring_cmpl_ring_cfg_aggint_params_input req
= {0};
3516 u16 max_buf
, max_buf_irq
;
3517 u16 buf_tmr
, buf_tmr_irq
;
3520 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS
,
3523 /* Each rx completion (2 records) should be DMAed immediately */
3524 max_buf
= min_t(u16
, bp
->coal_bufs
/ 4, 2);
3525 /* max_buf must not be zero */
3526 max_buf
= clamp_t(u16
, max_buf
, 1, 63);
3527 max_buf_irq
= clamp_t(u16
, bp
->coal_bufs_irq
, 1, 63);
3528 buf_tmr
= max_t(u16
, bp
->coal_ticks
/ 4, 1);
3529 buf_tmr_irq
= max_t(u16
, bp
->coal_ticks_irq
, 1);
3531 flags
= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET
;
3533 /* RING_IDLE generates more IRQs for lower latency. Enable it only
3534 * if coal_ticks is less than 25 us.
3536 if (BNXT_COAL_TIMER_TO_USEC(bp
->coal_ticks
) < 25)
3537 flags
|= RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE
;
3539 req
.flags
= cpu_to_le16(flags
);
3540 req
.num_cmpl_dma_aggr
= cpu_to_le16(max_buf
);
3541 req
.num_cmpl_dma_aggr_during_int
= cpu_to_le16(max_buf_irq
);
3542 req
.cmpl_aggr_dma_tmr
= cpu_to_le16(buf_tmr
);
3543 req
.cmpl_aggr_dma_tmr_during_int
= cpu_to_le16(buf_tmr_irq
);
3544 req
.int_lat_tmr_min
= cpu_to_le16(buf_tmr
);
3545 req
.int_lat_tmr_max
= cpu_to_le16(bp
->coal_ticks
);
3546 req
.num_cmpl_aggr_int
= cpu_to_le16(bp
->coal_bufs
);
3548 mutex_lock(&bp
->hwrm_cmd_lock
);
3549 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3550 req
.ring_id
= cpu_to_le16(bp
->grp_info
[i
].cp_fw_ring_id
);
3552 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3557 mutex_unlock(&bp
->hwrm_cmd_lock
);
3561 static int bnxt_hwrm_stat_ctx_free(struct bnxt
*bp
)
3564 struct hwrm_stat_ctx_free_input req
= {0};
3569 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_FREE
, -1, -1);
3571 mutex_lock(&bp
->hwrm_cmd_lock
);
3572 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3573 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3574 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3576 if (cpr
->hw_stats_ctx_id
!= INVALID_STATS_CTX_ID
) {
3577 req
.stat_ctx_id
= cpu_to_le32(cpr
->hw_stats_ctx_id
);
3579 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3584 cpr
->hw_stats_ctx_id
= INVALID_STATS_CTX_ID
;
3587 mutex_unlock(&bp
->hwrm_cmd_lock
);
3591 static int bnxt_hwrm_stat_ctx_alloc(struct bnxt
*bp
)
3594 struct hwrm_stat_ctx_alloc_input req
= {0};
3595 struct hwrm_stat_ctx_alloc_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3597 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_STAT_CTX_ALLOC
, -1, -1);
3599 req
.update_period_ms
= cpu_to_le32(1000);
3601 mutex_lock(&bp
->hwrm_cmd_lock
);
3602 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
3603 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
3604 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
3606 req
.stats_dma_addr
= cpu_to_le64(cpr
->hw_stats_map
);
3608 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
3613 cpr
->hw_stats_ctx_id
= le32_to_cpu(resp
->stat_ctx_id
);
3615 bp
->grp_info
[i
].fw_stats_ctx
= cpr
->hw_stats_ctx_id
;
3617 mutex_unlock(&bp
->hwrm_cmd_lock
);
3621 int bnxt_hwrm_func_qcaps(struct bnxt
*bp
)
3624 struct hwrm_func_qcaps_input req
= {0};
3625 struct hwrm_func_qcaps_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3627 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_QCAPS
, -1, -1);
3628 req
.fid
= cpu_to_le16(0xffff);
3630 mutex_lock(&bp
->hwrm_cmd_lock
);
3631 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3633 goto hwrm_func_qcaps_exit
;
3636 struct bnxt_pf_info
*pf
= &bp
->pf
;
3638 pf
->fw_fid
= le16_to_cpu(resp
->fid
);
3639 pf
->port_id
= le16_to_cpu(resp
->port_id
);
3640 memcpy(pf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3641 memcpy(bp
->dev
->dev_addr
, pf
->mac_addr
, ETH_ALEN
);
3642 pf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3643 pf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3644 pf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3645 pf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3646 pf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3647 if (!pf
->max_hw_ring_grps
)
3648 pf
->max_hw_ring_grps
= pf
->max_tx_rings
;
3649 pf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3650 pf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3651 pf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3652 pf
->first_vf_id
= le16_to_cpu(resp
->first_vf_id
);
3653 pf
->max_vfs
= le16_to_cpu(resp
->max_vfs
);
3654 pf
->max_encap_records
= le32_to_cpu(resp
->max_encap_records
);
3655 pf
->max_decap_records
= le32_to_cpu(resp
->max_decap_records
);
3656 pf
->max_tx_em_flows
= le32_to_cpu(resp
->max_tx_em_flows
);
3657 pf
->max_tx_wm_flows
= le32_to_cpu(resp
->max_tx_wm_flows
);
3658 pf
->max_rx_em_flows
= le32_to_cpu(resp
->max_rx_em_flows
);
3659 pf
->max_rx_wm_flows
= le32_to_cpu(resp
->max_rx_wm_flows
);
3661 #ifdef CONFIG_BNXT_SRIOV
3662 struct bnxt_vf_info
*vf
= &bp
->vf
;
3664 vf
->fw_fid
= le16_to_cpu(resp
->fid
);
3665 memcpy(vf
->mac_addr
, resp
->perm_mac_address
, ETH_ALEN
);
3666 if (is_valid_ether_addr(vf
->mac_addr
))
3667 /* overwrite netdev dev_adr with admin VF MAC */
3668 memcpy(bp
->dev
->dev_addr
, vf
->mac_addr
, ETH_ALEN
);
3670 random_ether_addr(bp
->dev
->dev_addr
);
3672 vf
->max_rsscos_ctxs
= le16_to_cpu(resp
->max_rsscos_ctx
);
3673 vf
->max_cp_rings
= le16_to_cpu(resp
->max_cmpl_rings
);
3674 vf
->max_tx_rings
= le16_to_cpu(resp
->max_tx_rings
);
3675 vf
->max_rx_rings
= le16_to_cpu(resp
->max_rx_rings
);
3676 vf
->max_hw_ring_grps
= le32_to_cpu(resp
->max_hw_ring_grps
);
3677 if (!vf
->max_hw_ring_grps
)
3678 vf
->max_hw_ring_grps
= vf
->max_tx_rings
;
3679 vf
->max_l2_ctxs
= le16_to_cpu(resp
->max_l2_ctxs
);
3680 vf
->max_vnics
= le16_to_cpu(resp
->max_vnics
);
3681 vf
->max_stat_ctxs
= le16_to_cpu(resp
->max_stat_ctx
);
3685 bp
->tx_push_thresh
= 0;
3687 cpu_to_le32(FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED
))
3688 bp
->tx_push_thresh
= BNXT_TX_PUSH_THRESH
;
3690 hwrm_func_qcaps_exit
:
3691 mutex_unlock(&bp
->hwrm_cmd_lock
);
3695 static int bnxt_hwrm_func_reset(struct bnxt
*bp
)
3697 struct hwrm_func_reset_input req
= {0};
3699 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_FUNC_RESET
, -1, -1);
3702 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_RESET_TIMEOUT
);
3705 static int bnxt_hwrm_queue_qportcfg(struct bnxt
*bp
)
3708 struct hwrm_queue_qportcfg_input req
= {0};
3709 struct hwrm_queue_qportcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3712 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_QUEUE_QPORTCFG
, -1, -1);
3714 mutex_lock(&bp
->hwrm_cmd_lock
);
3715 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3719 if (!resp
->max_configurable_queues
) {
3723 bp
->max_tc
= resp
->max_configurable_queues
;
3724 if (bp
->max_tc
> BNXT_MAX_QUEUE
)
3725 bp
->max_tc
= BNXT_MAX_QUEUE
;
3727 qptr
= &resp
->queue_id0
;
3728 for (i
= 0; i
< bp
->max_tc
; i
++) {
3729 bp
->q_info
[i
].queue_id
= *qptr
++;
3730 bp
->q_info
[i
].queue_profile
= *qptr
++;
3734 mutex_unlock(&bp
->hwrm_cmd_lock
);
3738 static int bnxt_hwrm_ver_get(struct bnxt
*bp
)
3741 struct hwrm_ver_get_input req
= {0};
3742 struct hwrm_ver_get_output
*resp
= bp
->hwrm_cmd_resp_addr
;
3744 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_VER_GET
, -1, -1);
3745 req
.hwrm_intf_maj
= HWRM_VERSION_MAJOR
;
3746 req
.hwrm_intf_min
= HWRM_VERSION_MINOR
;
3747 req
.hwrm_intf_upd
= HWRM_VERSION_UPDATE
;
3748 mutex_lock(&bp
->hwrm_cmd_lock
);
3749 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
3751 goto hwrm_ver_get_exit
;
3753 memcpy(&bp
->ver_resp
, resp
, sizeof(struct hwrm_ver_get_output
));
3755 if (resp
->hwrm_intf_maj
< 1) {
3756 netdev_warn(bp
->dev
, "HWRM interface %d.%d.%d is older than 1.0.0.\n",
3757 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
,
3758 resp
->hwrm_intf_upd
);
3759 netdev_warn(bp
->dev
, "Please update firmware with HWRM interface 1.0.0 or newer.\n");
3761 snprintf(bp
->fw_ver_str
, BC_HWRM_STR_LEN
, "bc %d.%d.%d rm %d.%d.%d",
3762 resp
->hwrm_fw_maj
, resp
->hwrm_fw_min
, resp
->hwrm_fw_bld
,
3763 resp
->hwrm_intf_maj
, resp
->hwrm_intf_min
, resp
->hwrm_intf_upd
);
3766 mutex_unlock(&bp
->hwrm_cmd_lock
);
3770 static void bnxt_hwrm_free_tunnel_ports(struct bnxt
*bp
)
3772 if (bp
->vxlan_port_cnt
) {
3773 bnxt_hwrm_tunnel_dst_port_free(
3774 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
3776 bp
->vxlan_port_cnt
= 0;
3777 if (bp
->nge_port_cnt
) {
3778 bnxt_hwrm_tunnel_dst_port_free(
3779 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
);
3781 bp
->nge_port_cnt
= 0;
3784 static int bnxt_set_tpa(struct bnxt
*bp
, bool set_tpa
)
3790 tpa_flags
= bp
->flags
& BNXT_FLAG_TPA
;
3791 for (i
= 0; i
< bp
->nr_vnics
; i
++) {
3792 rc
= bnxt_hwrm_vnic_set_tpa(bp
, i
, tpa_flags
);
3794 netdev_err(bp
->dev
, "hwrm vnic set tpa failure rc for vnic %d: %x\n",
3802 static void bnxt_hwrm_clear_vnic_rss(struct bnxt
*bp
)
3806 for (i
= 0; i
< bp
->nr_vnics
; i
++)
3807 bnxt_hwrm_vnic_set_rss(bp
, i
, false);
3810 static void bnxt_hwrm_resource_free(struct bnxt
*bp
, bool close_path
,
3813 if (bp
->vnic_info
) {
3814 bnxt_hwrm_clear_vnic_filter(bp
);
3815 /* clear all RSS setting before free vnic ctx */
3816 bnxt_hwrm_clear_vnic_rss(bp
);
3817 bnxt_hwrm_vnic_ctx_free(bp
);
3818 /* before free the vnic, undo the vnic tpa settings */
3819 if (bp
->flags
& BNXT_FLAG_TPA
)
3820 bnxt_set_tpa(bp
, false);
3821 bnxt_hwrm_vnic_free(bp
);
3823 bnxt_hwrm_ring_free(bp
, close_path
);
3824 bnxt_hwrm_ring_grp_free(bp
);
3826 bnxt_hwrm_stat_ctx_free(bp
);
3827 bnxt_hwrm_free_tunnel_ports(bp
);
3831 static int bnxt_setup_vnic(struct bnxt
*bp
, u16 vnic_id
)
3835 /* allocate context for vnic */
3836 rc
= bnxt_hwrm_vnic_ctx_alloc(bp
, vnic_id
);
3838 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3840 goto vnic_setup_err
;
3842 bp
->rsscos_nr_ctxs
++;
3844 /* configure default vnic, ring grp */
3845 rc
= bnxt_hwrm_vnic_cfg(bp
, vnic_id
);
3847 netdev_err(bp
->dev
, "hwrm vnic %d cfg failure rc: %x\n",
3849 goto vnic_setup_err
;
3852 /* Enable RSS hashing on vnic */
3853 rc
= bnxt_hwrm_vnic_set_rss(bp
, vnic_id
, true);
3855 netdev_err(bp
->dev
, "hwrm vnic %d set rss failure rc: %x\n",
3857 goto vnic_setup_err
;
3860 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
) {
3861 rc
= bnxt_hwrm_vnic_set_hds(bp
, vnic_id
);
3863 netdev_err(bp
->dev
, "hwrm vnic %d set hds failure rc: %x\n",
3872 static int bnxt_alloc_rfs_vnics(struct bnxt
*bp
)
3874 #ifdef CONFIG_RFS_ACCEL
3877 for (i
= 0; i
< bp
->rx_nr_rings
; i
++) {
3878 u16 vnic_id
= i
+ 1;
3881 if (vnic_id
>= bp
->nr_vnics
)
3884 bp
->vnic_info
[vnic_id
].flags
|= BNXT_VNIC_RFS_FLAG
;
3885 rc
= bnxt_hwrm_vnic_alloc(bp
, vnic_id
, ring_id
, 1);
3887 netdev_err(bp
->dev
, "hwrm vnic %d alloc failure rc: %x\n",
3891 rc
= bnxt_setup_vnic(bp
, vnic_id
);
3901 static int bnxt_cfg_rx_mode(struct bnxt
*);
3903 static int bnxt_init_chip(struct bnxt
*bp
, bool irq_re_init
)
3908 rc
= bnxt_hwrm_stat_ctx_alloc(bp
);
3910 netdev_err(bp
->dev
, "hwrm stat ctx alloc failure rc: %x\n",
3916 rc
= bnxt_hwrm_ring_alloc(bp
);
3918 netdev_err(bp
->dev
, "hwrm ring alloc failure rc: %x\n", rc
);
3922 rc
= bnxt_hwrm_ring_grp_alloc(bp
);
3924 netdev_err(bp
->dev
, "hwrm_ring_grp alloc failure: %x\n", rc
);
3928 /* default vnic 0 */
3929 rc
= bnxt_hwrm_vnic_alloc(bp
, 0, 0, bp
->rx_nr_rings
);
3931 netdev_err(bp
->dev
, "hwrm vnic alloc failure rc: %x\n", rc
);
3935 rc
= bnxt_setup_vnic(bp
, 0);
3939 if (bp
->flags
& BNXT_FLAG_RFS
) {
3940 rc
= bnxt_alloc_rfs_vnics(bp
);
3945 if (bp
->flags
& BNXT_FLAG_TPA
) {
3946 rc
= bnxt_set_tpa(bp
, true);
3952 bnxt_update_vf_mac(bp
);
3954 /* Filter for default vnic 0 */
3955 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, 0, bp
->dev
->dev_addr
);
3957 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n", rc
);
3960 bp
->vnic_info
[0].uc_filter_count
= 1;
3962 bp
->vnic_info
[0].rx_mask
= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST
;
3964 if ((bp
->dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
3965 bp
->vnic_info
[0].rx_mask
|=
3966 CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
3968 rc
= bnxt_cfg_rx_mode(bp
);
3972 rc
= bnxt_hwrm_set_coal(bp
);
3974 netdev_warn(bp
->dev
, "HWRM set coalescing failure rc: %x\n",
3980 bnxt_hwrm_resource_free(bp
, 0, true);
3985 static int bnxt_shutdown_nic(struct bnxt
*bp
, bool irq_re_init
)
3987 bnxt_hwrm_resource_free(bp
, 1, irq_re_init
);
3991 static int bnxt_init_nic(struct bnxt
*bp
, bool irq_re_init
)
3993 bnxt_init_rx_rings(bp
);
3994 bnxt_init_tx_rings(bp
);
3995 bnxt_init_ring_grps(bp
, irq_re_init
);
3996 bnxt_init_vnics(bp
);
3998 return bnxt_init_chip(bp
, irq_re_init
);
4001 static void bnxt_disable_int(struct bnxt
*bp
)
4008 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4009 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4010 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4012 BNXT_CP_DB(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4016 static void bnxt_enable_int(struct bnxt
*bp
)
4020 atomic_set(&bp
->intr_sem
, 0);
4021 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4022 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4023 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4025 BNXT_CP_DB_REARM(cpr
->cp_doorbell
, cpr
->cp_raw_cons
);
4029 static int bnxt_set_real_num_queues(struct bnxt
*bp
)
4032 struct net_device
*dev
= bp
->dev
;
4034 rc
= netif_set_real_num_tx_queues(dev
, bp
->tx_nr_rings
);
4038 rc
= netif_set_real_num_rx_queues(dev
, bp
->rx_nr_rings
);
4042 #ifdef CONFIG_RFS_ACCEL
4043 if (bp
->flags
& BNXT_FLAG_RFS
)
4044 dev
->rx_cpu_rmap
= alloc_irq_cpu_rmap(bp
->rx_nr_rings
);
4050 static int bnxt_trim_rings(struct bnxt
*bp
, int *rx
, int *tx
, int max
,
4053 int _rx
= *rx
, _tx
= *tx
;
4056 *rx
= min_t(int, _rx
, max
);
4057 *tx
= min_t(int, _tx
, max
);
4062 while (_rx
+ _tx
> max
) {
4063 if (_rx
> _tx
&& _rx
> 1)
4074 static int bnxt_setup_msix(struct bnxt
*bp
)
4076 struct msix_entry
*msix_ent
;
4077 struct net_device
*dev
= bp
->dev
;
4078 int i
, total_vecs
, rc
= 0, min
= 1;
4079 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4081 bp
->flags
&= ~BNXT_FLAG_USING_MSIX
;
4082 total_vecs
= bp
->cp_nr_rings
;
4084 msix_ent
= kcalloc(total_vecs
, sizeof(struct msix_entry
), GFP_KERNEL
);
4088 for (i
= 0; i
< total_vecs
; i
++) {
4089 msix_ent
[i
].entry
= i
;
4090 msix_ent
[i
].vector
= 0;
4093 if (!(bp
->flags
& BNXT_FLAG_SHARED_RINGS
))
4096 total_vecs
= pci_enable_msix_range(bp
->pdev
, msix_ent
, min
, total_vecs
);
4097 if (total_vecs
< 0) {
4099 goto msix_setup_exit
;
4102 bp
->irq_tbl
= kcalloc(total_vecs
, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4106 /* Trim rings based upon num of vectors allocated */
4107 rc
= bnxt_trim_rings(bp
, &bp
->rx_nr_rings
, &bp
->tx_nr_rings
,
4108 total_vecs
, min
== 1);
4110 goto msix_setup_exit
;
4112 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4113 tcs
= netdev_get_num_tc(dev
);
4115 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
/ tcs
;
4116 if (bp
->tx_nr_rings_per_tc
== 0) {
4117 netdev_reset_tc(dev
);
4118 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4122 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tcs
;
4123 for (i
= 0; i
< tcs
; i
++) {
4124 count
= bp
->tx_nr_rings_per_tc
;
4126 netdev_set_tc_queue(dev
, i
, count
, off
);
4130 bp
->cp_nr_rings
= total_vecs
;
4132 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4135 bp
->irq_tbl
[i
].vector
= msix_ent
[i
].vector
;
4136 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
4138 else if (i
< bp
->rx_nr_rings
)
4143 snprintf(bp
->irq_tbl
[i
].name
, len
,
4144 "%s-%s-%d", dev
->name
, attr
, i
);
4145 bp
->irq_tbl
[i
].handler
= bnxt_msix
;
4147 rc
= bnxt_set_real_num_queues(bp
);
4149 goto msix_setup_exit
;
4152 goto msix_setup_exit
;
4154 bp
->flags
|= BNXT_FLAG_USING_MSIX
;
4159 netdev_err(bp
->dev
, "bnxt_setup_msix err: %x\n", rc
);
4160 pci_disable_msix(bp
->pdev
);
4165 static int bnxt_setup_inta(struct bnxt
*bp
)
4168 const int len
= sizeof(bp
->irq_tbl
[0].name
);
4170 if (netdev_get_num_tc(bp
->dev
))
4171 netdev_reset_tc(bp
->dev
);
4173 bp
->irq_tbl
= kcalloc(1, sizeof(struct bnxt_irq
), GFP_KERNEL
);
4178 bp
->rx_nr_rings
= 1;
4179 bp
->tx_nr_rings
= 1;
4180 bp
->cp_nr_rings
= 1;
4181 bp
->tx_nr_rings_per_tc
= bp
->tx_nr_rings
;
4182 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
4183 bp
->irq_tbl
[0].vector
= bp
->pdev
->irq
;
4184 snprintf(bp
->irq_tbl
[0].name
, len
,
4185 "%s-%s-%d", bp
->dev
->name
, "TxRx", 0);
4186 bp
->irq_tbl
[0].handler
= bnxt_inta
;
4187 rc
= bnxt_set_real_num_queues(bp
);
4191 static int bnxt_setup_int_mode(struct bnxt
*bp
)
4195 if (bp
->flags
& BNXT_FLAG_MSIX_CAP
)
4196 rc
= bnxt_setup_msix(bp
);
4198 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4199 /* fallback to INTA */
4200 rc
= bnxt_setup_inta(bp
);
4205 static void bnxt_free_irq(struct bnxt
*bp
)
4207 struct bnxt_irq
*irq
;
4210 #ifdef CONFIG_RFS_ACCEL
4211 free_irq_cpu_rmap(bp
->dev
->rx_cpu_rmap
);
4212 bp
->dev
->rx_cpu_rmap
= NULL
;
4217 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4218 irq
= &bp
->irq_tbl
[i
];
4220 free_irq(irq
->vector
, bp
->bnapi
[i
]);
4223 if (bp
->flags
& BNXT_FLAG_USING_MSIX
)
4224 pci_disable_msix(bp
->pdev
);
4229 static int bnxt_request_irq(struct bnxt
*bp
)
4232 unsigned long flags
= 0;
4233 #ifdef CONFIG_RFS_ACCEL
4234 struct cpu_rmap
*rmap
= bp
->dev
->rx_cpu_rmap
;
4237 if (!(bp
->flags
& BNXT_FLAG_USING_MSIX
))
4238 flags
= IRQF_SHARED
;
4240 for (i
= 0, j
= 0; i
< bp
->cp_nr_rings
; i
++) {
4241 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
4242 #ifdef CONFIG_RFS_ACCEL
4243 if (rmap
&& bp
->bnapi
[i
]->rx_ring
) {
4244 rc
= irq_cpu_rmap_add(rmap
, irq
->vector
);
4246 netdev_warn(bp
->dev
, "failed adding irq rmap for ring %d\n",
4251 rc
= request_irq(irq
->vector
, irq
->handler
, flags
, irq
->name
,
4261 static void bnxt_del_napi(struct bnxt
*bp
)
4268 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4269 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4271 napi_hash_del(&bnapi
->napi
);
4272 netif_napi_del(&bnapi
->napi
);
4276 static void bnxt_init_napi(struct bnxt
*bp
)
4279 struct bnxt_napi
*bnapi
;
4281 if (bp
->flags
& BNXT_FLAG_USING_MSIX
) {
4282 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4283 bnapi
= bp
->bnapi
[i
];
4284 netif_napi_add(bp
->dev
, &bnapi
->napi
,
4288 bnapi
= bp
->bnapi
[0];
4289 netif_napi_add(bp
->dev
, &bnapi
->napi
, bnxt_poll
, 64);
4293 static void bnxt_disable_napi(struct bnxt
*bp
)
4300 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4301 napi_disable(&bp
->bnapi
[i
]->napi
);
4302 bnxt_disable_poll(bp
->bnapi
[i
]);
4306 static void bnxt_enable_napi(struct bnxt
*bp
)
4310 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4311 bnxt_enable_poll(bp
->bnapi
[i
]);
4312 napi_enable(&bp
->bnapi
[i
]->napi
);
4316 static void bnxt_tx_disable(struct bnxt
*bp
)
4319 struct bnxt_tx_ring_info
*txr
;
4320 struct netdev_queue
*txq
;
4323 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4324 txr
= &bp
->tx_ring
[i
];
4325 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4326 __netif_tx_lock(txq
, smp_processor_id());
4327 txr
->dev_state
= BNXT_DEV_STATE_CLOSING
;
4328 __netif_tx_unlock(txq
);
4331 /* Stop all TX queues */
4332 netif_tx_disable(bp
->dev
);
4333 netif_carrier_off(bp
->dev
);
4336 static void bnxt_tx_enable(struct bnxt
*bp
)
4339 struct bnxt_tx_ring_info
*txr
;
4340 struct netdev_queue
*txq
;
4342 for (i
= 0; i
< bp
->tx_nr_rings
; i
++) {
4343 txr
= &bp
->tx_ring
[i
];
4344 txq
= netdev_get_tx_queue(bp
->dev
, i
);
4347 netif_tx_wake_all_queues(bp
->dev
);
4348 if (bp
->link_info
.link_up
)
4349 netif_carrier_on(bp
->dev
);
4352 static void bnxt_report_link(struct bnxt
*bp
)
4354 if (bp
->link_info
.link_up
) {
4356 const char *flow_ctrl
;
4359 netif_carrier_on(bp
->dev
);
4360 if (bp
->link_info
.duplex
== BNXT_LINK_DUPLEX_FULL
)
4364 if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_BOTH
)
4365 flow_ctrl
= "ON - receive & transmit";
4366 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_TX
)
4367 flow_ctrl
= "ON - transmit";
4368 else if (bp
->link_info
.pause
== BNXT_LINK_PAUSE_RX
)
4369 flow_ctrl
= "ON - receive";
4372 speed
= bnxt_fw_to_ethtool_speed(bp
->link_info
.link_speed
);
4373 netdev_info(bp
->dev
, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n",
4374 speed
, duplex
, flow_ctrl
);
4376 netif_carrier_off(bp
->dev
);
4377 netdev_err(bp
->dev
, "NIC Link is Down\n");
4381 static int bnxt_update_link(struct bnxt
*bp
, bool chng_link_state
)
4384 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4385 struct hwrm_port_phy_qcfg_input req
= {0};
4386 struct hwrm_port_phy_qcfg_output
*resp
= bp
->hwrm_cmd_resp_addr
;
4387 u8 link_up
= link_info
->link_up
;
4389 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_QCFG
, -1, -1);
4391 mutex_lock(&bp
->hwrm_cmd_lock
);
4392 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4394 mutex_unlock(&bp
->hwrm_cmd_lock
);
4398 memcpy(&link_info
->phy_qcfg_resp
, resp
, sizeof(*resp
));
4399 link_info
->phy_link_status
= resp
->link
;
4400 link_info
->duplex
= resp
->duplex
;
4401 link_info
->pause
= resp
->pause
;
4402 link_info
->auto_mode
= resp
->auto_mode
;
4403 link_info
->auto_pause_setting
= resp
->auto_pause
;
4404 link_info
->force_pause_setting
= resp
->force_pause
;
4405 link_info
->duplex_setting
= resp
->duplex
;
4406 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4407 link_info
->link_speed
= le16_to_cpu(resp
->link_speed
);
4409 link_info
->link_speed
= 0;
4410 link_info
->force_link_speed
= le16_to_cpu(resp
->force_link_speed
);
4411 link_info
->auto_link_speed
= le16_to_cpu(resp
->auto_link_speed
);
4412 link_info
->support_speeds
= le16_to_cpu(resp
->support_speeds
);
4413 link_info
->auto_link_speeds
= le16_to_cpu(resp
->auto_link_speed_mask
);
4414 link_info
->preemphasis
= le32_to_cpu(resp
->preemphasis
);
4415 link_info
->phy_ver
[0] = resp
->phy_maj
;
4416 link_info
->phy_ver
[1] = resp
->phy_min
;
4417 link_info
->phy_ver
[2] = resp
->phy_bld
;
4418 link_info
->media_type
= resp
->media_type
;
4419 link_info
->transceiver
= resp
->transceiver_type
;
4420 link_info
->phy_addr
= resp
->phy_addr
;
4422 /* TODO: need to add more logic to report VF link */
4423 if (chng_link_state
) {
4424 if (link_info
->phy_link_status
== BNXT_LINK_LINK
)
4425 link_info
->link_up
= 1;
4427 link_info
->link_up
= 0;
4428 if (link_up
!= link_info
->link_up
)
4429 bnxt_report_link(bp
);
4431 /* alwasy link down if not require to update link state */
4432 link_info
->link_up
= 0;
4434 mutex_unlock(&bp
->hwrm_cmd_lock
);
4439 bnxt_hwrm_set_pause_common(struct bnxt
*bp
, struct hwrm_port_phy_cfg_input
*req
)
4441 if (bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) {
4442 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4443 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4444 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4445 req
->auto_pause
|= PORT_PHY_CFG_REQ_AUTO_PAUSE_RX
;
4447 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE
);
4449 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_RX
)
4450 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_RX
;
4451 if (bp
->link_info
.req_flow_ctrl
& BNXT_LINK_PAUSE_TX
)
4452 req
->force_pause
|= PORT_PHY_CFG_REQ_FORCE_PAUSE_TX
;
4454 cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE
);
4458 static void bnxt_hwrm_set_link_common(struct bnxt
*bp
,
4459 struct hwrm_port_phy_cfg_input
*req
)
4461 u8 autoneg
= bp
->link_info
.autoneg
;
4462 u16 fw_link_speed
= bp
->link_info
.req_link_speed
;
4463 u32 advertising
= bp
->link_info
.advertising
;
4465 if (autoneg
& BNXT_AUTONEG_SPEED
) {
4467 PORT_PHY_CFG_REQ_AUTO_MODE_MASK
;
4469 req
->enables
|= cpu_to_le32(
4470 PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK
);
4471 req
->auto_link_speed_mask
= cpu_to_le16(advertising
);
4473 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE
);
4475 cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG
);
4477 req
->force_link_speed
= cpu_to_le16(fw_link_speed
);
4478 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_FORCE
);
4481 /* currently don't support half duplex */
4482 req
->auto_duplex
= PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL
;
4483 req
->enables
|= cpu_to_le32(PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX
);
4484 /* tell chimp that the setting takes effect immediately */
4485 req
->flags
|= cpu_to_le32(PORT_PHY_CFG_REQ_FLAGS_RESET_PHY
);
4488 int bnxt_hwrm_set_pause(struct bnxt
*bp
)
4490 struct hwrm_port_phy_cfg_input req
= {0};
4493 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4494 bnxt_hwrm_set_pause_common(bp
, &req
);
4496 if ((bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
) ||
4497 bp
->link_info
.force_link_chng
)
4498 bnxt_hwrm_set_link_common(bp
, &req
);
4500 mutex_lock(&bp
->hwrm_cmd_lock
);
4501 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4502 if (!rc
&& !(bp
->link_info
.autoneg
& BNXT_AUTONEG_FLOW_CTRL
)) {
4503 /* since changing of pause setting doesn't trigger any link
4504 * change event, the driver needs to update the current pause
4505 * result upon successfully return of the phy_cfg command
4507 bp
->link_info
.pause
=
4508 bp
->link_info
.force_pause_setting
= bp
->link_info
.req_flow_ctrl
;
4509 bp
->link_info
.auto_pause_setting
= 0;
4510 if (!bp
->link_info
.force_link_chng
)
4511 bnxt_report_link(bp
);
4513 bp
->link_info
.force_link_chng
= false;
4514 mutex_unlock(&bp
->hwrm_cmd_lock
);
4518 int bnxt_hwrm_set_link_setting(struct bnxt
*bp
, bool set_pause
)
4520 struct hwrm_port_phy_cfg_input req
= {0};
4522 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_PORT_PHY_CFG
, -1, -1);
4524 bnxt_hwrm_set_pause_common(bp
, &req
);
4526 bnxt_hwrm_set_link_common(bp
, &req
);
4527 return hwrm_send_message(bp
, &req
, sizeof(req
), HWRM_CMD_TIMEOUT
);
4530 static int bnxt_update_phy_setting(struct bnxt
*bp
)
4533 bool update_link
= false;
4534 bool update_pause
= false;
4535 struct bnxt_link_info
*link_info
= &bp
->link_info
;
4537 rc
= bnxt_update_link(bp
, true);
4539 netdev_err(bp
->dev
, "failed to update link (rc: %x)\n",
4543 if ((link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4544 link_info
->auto_pause_setting
!= link_info
->req_flow_ctrl
)
4545 update_pause
= true;
4546 if (!(link_info
->autoneg
& BNXT_AUTONEG_FLOW_CTRL
) &&
4547 link_info
->force_pause_setting
!= link_info
->req_flow_ctrl
)
4548 update_pause
= true;
4549 if (link_info
->req_duplex
!= link_info
->duplex_setting
)
4551 if (!(link_info
->autoneg
& BNXT_AUTONEG_SPEED
)) {
4552 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
4554 if (link_info
->req_link_speed
!= link_info
->force_link_speed
)
4557 if (link_info
->auto_mode
== BNXT_LINK_AUTO_NONE
)
4559 if (link_info
->advertising
!= link_info
->auto_link_speeds
)
4561 if (link_info
->req_link_speed
!= link_info
->auto_link_speed
)
4566 rc
= bnxt_hwrm_set_link_setting(bp
, update_pause
);
4567 else if (update_pause
)
4568 rc
= bnxt_hwrm_set_pause(bp
);
4570 netdev_err(bp
->dev
, "failed to update phy setting (rc: %x)\n",
4578 /* Common routine to pre-map certain register block to different GRC window.
4579 * A PF has 16 4K windows and a VF has 4 4K windows. However, only 15 windows
4580 * in PF and 3 windows in VF that can be customized to map in different
4583 static void bnxt_preset_reg_win(struct bnxt
*bp
)
4586 /* CAG registers map to GRC window #4 */
4587 writel(BNXT_CAG_REG_BASE
,
4588 bp
->bar0
+ BNXT_GRCPF_REG_WINDOW_BASE_OUT
+ 12);
4592 static int __bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4596 bnxt_preset_reg_win(bp
);
4597 netif_carrier_off(bp
->dev
);
4599 rc
= bnxt_setup_int_mode(bp
);
4601 netdev_err(bp
->dev
, "bnxt_setup_int_mode err: %x\n",
4606 if ((bp
->flags
& BNXT_FLAG_RFS
) &&
4607 !(bp
->flags
& BNXT_FLAG_USING_MSIX
)) {
4608 /* disable RFS if falling back to INTA */
4609 bp
->dev
->hw_features
&= ~NETIF_F_NTUPLE
;
4610 bp
->flags
&= ~BNXT_FLAG_RFS
;
4613 rc
= bnxt_alloc_mem(bp
, irq_re_init
);
4615 netdev_err(bp
->dev
, "bnxt_alloc_mem err: %x\n", rc
);
4616 goto open_err_free_mem
;
4621 rc
= bnxt_request_irq(bp
);
4623 netdev_err(bp
->dev
, "bnxt_request_irq err: %x\n", rc
);
4628 bnxt_enable_napi(bp
);
4630 rc
= bnxt_init_nic(bp
, irq_re_init
);
4632 netdev_err(bp
->dev
, "bnxt_init_nic err: %x\n", rc
);
4637 rc
= bnxt_update_phy_setting(bp
);
4643 #if defined(CONFIG_VXLAN) || defined(CONFIG_VXLAN_MODULE)
4644 vxlan_get_rx_port(bp
->dev
);
4646 if (!bnxt_hwrm_tunnel_dst_port_alloc(
4648 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE
))
4649 bp
->nge_port_cnt
= 1;
4652 set_bit(BNXT_STATE_OPEN
, &bp
->state
);
4653 bnxt_enable_int(bp
);
4654 /* Enable TX queues */
4656 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
4661 bnxt_disable_napi(bp
);
4667 bnxt_free_mem(bp
, true);
4671 /* rtnl_lock held */
4672 int bnxt_open_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4676 rc
= __bnxt_open_nic(bp
, irq_re_init
, link_re_init
);
4678 netdev_err(bp
->dev
, "nic open fail (rc: %x)\n", rc
);
4684 static int bnxt_open(struct net_device
*dev
)
4686 struct bnxt
*bp
= netdev_priv(dev
);
4689 rc
= bnxt_hwrm_func_reset(bp
);
4691 netdev_err(bp
->dev
, "hwrm chip reset failure rc: %x\n",
4696 return __bnxt_open_nic(bp
, true, true);
4699 static void bnxt_disable_int_sync(struct bnxt
*bp
)
4703 atomic_inc(&bp
->intr_sem
);
4704 if (!netif_running(bp
->dev
))
4707 bnxt_disable_int(bp
);
4708 for (i
= 0; i
< bp
->cp_nr_rings
; i
++)
4709 synchronize_irq(bp
->irq_tbl
[i
].vector
);
4712 int bnxt_close_nic(struct bnxt
*bp
, bool irq_re_init
, bool link_re_init
)
4716 #ifdef CONFIG_BNXT_SRIOV
4717 if (bp
->sriov_cfg
) {
4718 rc
= wait_event_interruptible_timeout(bp
->sriov_cfg_wait
,
4720 BNXT_SRIOV_CFG_WAIT_TMO
);
4722 netdev_warn(bp
->dev
, "timeout waiting for SRIOV config operation to complete!\n");
4725 /* Change device state to avoid TX queue wake up's */
4726 bnxt_tx_disable(bp
);
4728 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
4729 smp_mb__after_atomic();
4730 while (test_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
))
4733 /* Flush rings before disabling interrupts */
4734 bnxt_shutdown_nic(bp
, irq_re_init
);
4736 /* TODO CHIMP_FW: Link/PHY related cleanup if (link_re_init) */
4738 bnxt_disable_napi(bp
);
4739 bnxt_disable_int_sync(bp
);
4740 del_timer_sync(&bp
->timer
);
4747 bnxt_free_mem(bp
, irq_re_init
);
4751 static int bnxt_close(struct net_device
*dev
)
4753 struct bnxt
*bp
= netdev_priv(dev
);
4755 bnxt_close_nic(bp
, true, true);
4759 /* rtnl_lock held */
4760 static int bnxt_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
4766 if (!netif_running(dev
))
4773 if (!netif_running(dev
))
4785 static struct rtnl_link_stats64
*
4786 bnxt_get_stats64(struct net_device
*dev
, struct rtnl_link_stats64
*stats
)
4789 struct bnxt
*bp
= netdev_priv(dev
);
4791 memset(stats
, 0, sizeof(struct rtnl_link_stats64
));
4796 /* TODO check if we need to synchronize with bnxt_close path */
4797 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
4798 struct bnxt_napi
*bnapi
= bp
->bnapi
[i
];
4799 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
4800 struct ctx_hw_stats
*hw_stats
= cpr
->hw_stats
;
4802 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_ucast_pkts
);
4803 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4804 stats
->rx_packets
+= le64_to_cpu(hw_stats
->rx_bcast_pkts
);
4806 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_ucast_pkts
);
4807 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_mcast_pkts
);
4808 stats
->tx_packets
+= le64_to_cpu(hw_stats
->tx_bcast_pkts
);
4810 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_ucast_bytes
);
4811 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_mcast_bytes
);
4812 stats
->rx_bytes
+= le64_to_cpu(hw_stats
->rx_bcast_bytes
);
4814 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_ucast_bytes
);
4815 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_mcast_bytes
);
4816 stats
->tx_bytes
+= le64_to_cpu(hw_stats
->tx_bcast_bytes
);
4818 stats
->rx_missed_errors
+=
4819 le64_to_cpu(hw_stats
->rx_discard_pkts
);
4821 stats
->multicast
+= le64_to_cpu(hw_stats
->rx_mcast_pkts
);
4823 stats
->tx_dropped
+= le64_to_cpu(hw_stats
->tx_drop_pkts
);
4829 static bool bnxt_mc_list_updated(struct bnxt
*bp
, u32
*rx_mask
)
4831 struct net_device
*dev
= bp
->dev
;
4832 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4833 struct netdev_hw_addr
*ha
;
4836 bool update
= false;
4839 netdev_for_each_mc_addr(ha
, dev
) {
4840 if (mc_count
>= BNXT_MAX_MC_ADDRS
) {
4841 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4842 vnic
->mc_list_count
= 0;
4846 if (!ether_addr_equal(haddr
, vnic
->mc_list
+ off
)) {
4847 memcpy(vnic
->mc_list
+ off
, haddr
, ETH_ALEN
);
4854 *rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
;
4856 if (mc_count
!= vnic
->mc_list_count
) {
4857 vnic
->mc_list_count
= mc_count
;
4863 static bool bnxt_uc_list_updated(struct bnxt
*bp
)
4865 struct net_device
*dev
= bp
->dev
;
4866 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4867 struct netdev_hw_addr
*ha
;
4870 if (netdev_uc_count(dev
) != (vnic
->uc_filter_count
- 1))
4873 netdev_for_each_uc_addr(ha
, dev
) {
4874 if (!ether_addr_equal(ha
->addr
, vnic
->uc_list
+ off
))
4882 static void bnxt_set_rx_mode(struct net_device
*dev
)
4884 struct bnxt
*bp
= netdev_priv(dev
);
4885 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4886 u32 mask
= vnic
->rx_mask
;
4887 bool mc_update
= false;
4890 if (!netif_running(dev
))
4893 mask
&= ~(CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
|
4894 CFA_L2_SET_RX_MASK_REQ_MASK_MCAST
|
4895 CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
);
4897 /* Only allow PF to be in promiscuous mode */
4898 if ((dev
->flags
& IFF_PROMISC
) && BNXT_PF(bp
))
4899 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4901 uc_update
= bnxt_uc_list_updated(bp
);
4903 if (dev
->flags
& IFF_ALLMULTI
) {
4904 mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST
;
4905 vnic
->mc_list_count
= 0;
4907 mc_update
= bnxt_mc_list_updated(bp
, &mask
);
4910 if (mask
!= vnic
->rx_mask
|| uc_update
|| mc_update
) {
4911 vnic
->rx_mask
= mask
;
4913 set_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
);
4914 schedule_work(&bp
->sp_task
);
4918 static int bnxt_cfg_rx_mode(struct bnxt
*bp
)
4920 struct net_device
*dev
= bp
->dev
;
4921 struct bnxt_vnic_info
*vnic
= &bp
->vnic_info
[0];
4922 struct netdev_hw_addr
*ha
;
4926 netif_addr_lock_bh(dev
);
4927 uc_update
= bnxt_uc_list_updated(bp
);
4928 netif_addr_unlock_bh(dev
);
4933 mutex_lock(&bp
->hwrm_cmd_lock
);
4934 for (i
= 1; i
< vnic
->uc_filter_count
; i
++) {
4935 struct hwrm_cfa_l2_filter_free_input req
= {0};
4937 bnxt_hwrm_cmd_hdr_init(bp
, &req
, HWRM_CFA_L2_FILTER_FREE
, -1,
4940 req
.l2_filter_id
= vnic
->fw_l2_filter_id
[i
];
4942 rc
= _hwrm_send_message(bp
, &req
, sizeof(req
),
4945 mutex_unlock(&bp
->hwrm_cmd_lock
);
4947 vnic
->uc_filter_count
= 1;
4949 netif_addr_lock_bh(dev
);
4950 if (netdev_uc_count(dev
) > (BNXT_MAX_UC_ADDRS
- 1)) {
4951 vnic
->rx_mask
|= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS
;
4953 netdev_for_each_uc_addr(ha
, dev
) {
4954 memcpy(vnic
->uc_list
+ off
, ha
->addr
, ETH_ALEN
);
4956 vnic
->uc_filter_count
++;
4959 netif_addr_unlock_bh(dev
);
4961 for (i
= 1, off
= 0; i
< vnic
->uc_filter_count
; i
++, off
+= ETH_ALEN
) {
4962 rc
= bnxt_hwrm_set_vnic_filter(bp
, 0, i
, vnic
->uc_list
+ off
);
4964 netdev_err(bp
->dev
, "HWRM vnic filter failure rc: %x\n",
4966 vnic
->uc_filter_count
= i
;
4972 rc
= bnxt_hwrm_cfa_l2_set_rx_mask(bp
, 0);
4974 netdev_err(bp
->dev
, "HWRM cfa l2 rx mask failure rc: %x\n",
4980 static bool bnxt_rfs_capable(struct bnxt
*bp
)
4982 #ifdef CONFIG_RFS_ACCEL
4983 struct bnxt_pf_info
*pf
= &bp
->pf
;
4986 if (BNXT_VF(bp
) || !(bp
->flags
& BNXT_FLAG_MSIX_CAP
))
4989 vnics
= 1 + bp
->rx_nr_rings
;
4990 if (vnics
> pf
->max_rsscos_ctxs
|| vnics
> pf
->max_vnics
)
4999 static netdev_features_t
bnxt_fix_features(struct net_device
*dev
,
5000 netdev_features_t features
)
5002 struct bnxt
*bp
= netdev_priv(dev
);
5004 if (!bnxt_rfs_capable(bp
))
5005 features
&= ~NETIF_F_NTUPLE
;
5009 static int bnxt_set_features(struct net_device
*dev
, netdev_features_t features
)
5011 struct bnxt
*bp
= netdev_priv(dev
);
5012 u32 flags
= bp
->flags
;
5015 bool re_init
= false;
5016 bool update_tpa
= false;
5018 flags
&= ~BNXT_FLAG_ALL_CONFIG_FEATS
;
5019 if ((features
& NETIF_F_GRO
) && (bp
->pdev
->revision
> 0))
5020 flags
|= BNXT_FLAG_GRO
;
5021 if (features
& NETIF_F_LRO
)
5022 flags
|= BNXT_FLAG_LRO
;
5024 if (features
& NETIF_F_HW_VLAN_CTAG_RX
)
5025 flags
|= BNXT_FLAG_STRIP_VLAN
;
5027 if (features
& NETIF_F_NTUPLE
)
5028 flags
|= BNXT_FLAG_RFS
;
5030 changes
= flags
^ bp
->flags
;
5031 if (changes
& BNXT_FLAG_TPA
) {
5033 if ((bp
->flags
& BNXT_FLAG_TPA
) == 0 ||
5034 (flags
& BNXT_FLAG_TPA
) == 0)
5038 if (changes
& ~BNXT_FLAG_TPA
)
5041 if (flags
!= bp
->flags
) {
5042 u32 old_flags
= bp
->flags
;
5046 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5048 bnxt_set_ring_params(bp
);
5053 bnxt_close_nic(bp
, false, false);
5055 bnxt_set_ring_params(bp
);
5057 return bnxt_open_nic(bp
, false, false);
5060 rc
= bnxt_set_tpa(bp
,
5061 (flags
& BNXT_FLAG_TPA
) ?
5064 bp
->flags
= old_flags
;
5070 static void bnxt_dump_tx_sw_state(struct bnxt_napi
*bnapi
)
5072 struct bnxt_tx_ring_info
*txr
= bnapi
->tx_ring
;
5073 int i
= bnapi
->index
;
5078 netdev_info(bnapi
->bp
->dev
, "[%d]: tx{fw_ring: %d prod: %x cons: %x}\n",
5079 i
, txr
->tx_ring_struct
.fw_ring_id
, txr
->tx_prod
,
5083 static void bnxt_dump_rx_sw_state(struct bnxt_napi
*bnapi
)
5085 struct bnxt_rx_ring_info
*rxr
= bnapi
->rx_ring
;
5086 int i
= bnapi
->index
;
5091 netdev_info(bnapi
->bp
->dev
, "[%d]: rx{fw_ring: %d prod: %x} rx_agg{fw_ring: %d agg_prod: %x sw_agg_prod: %x}\n",
5092 i
, rxr
->rx_ring_struct
.fw_ring_id
, rxr
->rx_prod
,
5093 rxr
->rx_agg_ring_struct
.fw_ring_id
, rxr
->rx_agg_prod
,
5094 rxr
->rx_sw_agg_prod
);
5097 static void bnxt_dump_cp_sw_state(struct bnxt_napi
*bnapi
)
5099 struct bnxt_cp_ring_info
*cpr
= &bnapi
->cp_ring
;
5100 int i
= bnapi
->index
;
5102 netdev_info(bnapi
->bp
->dev
, "[%d]: cp{fw_ring: %d raw_cons: %x}\n",
5103 i
, cpr
->cp_ring_struct
.fw_ring_id
, cpr
->cp_raw_cons
);
5106 static void bnxt_dbg_dump_states(struct bnxt
*bp
)
5109 struct bnxt_napi
*bnapi
;
5111 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5112 bnapi
= bp
->bnapi
[i
];
5113 if (netif_msg_drv(bp
)) {
5114 bnxt_dump_tx_sw_state(bnapi
);
5115 bnxt_dump_rx_sw_state(bnapi
);
5116 bnxt_dump_cp_sw_state(bnapi
);
5121 static void bnxt_reset_task(struct bnxt
*bp
)
5123 bnxt_dbg_dump_states(bp
);
5124 if (netif_running(bp
->dev
)) {
5125 bnxt_close_nic(bp
, false, false);
5126 bnxt_open_nic(bp
, false, false);
5130 static void bnxt_tx_timeout(struct net_device
*dev
)
5132 struct bnxt
*bp
= netdev_priv(dev
);
5134 netdev_err(bp
->dev
, "TX timeout detected, starting reset task!\n");
5135 set_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
);
5136 schedule_work(&bp
->sp_task
);
5139 #ifdef CONFIG_NET_POLL_CONTROLLER
5140 static void bnxt_poll_controller(struct net_device
*dev
)
5142 struct bnxt
*bp
= netdev_priv(dev
);
5145 for (i
= 0; i
< bp
->cp_nr_rings
; i
++) {
5146 struct bnxt_irq
*irq
= &bp
->irq_tbl
[i
];
5148 disable_irq(irq
->vector
);
5149 irq
->handler(irq
->vector
, bp
->bnapi
[i
]);
5150 enable_irq(irq
->vector
);
5155 static void bnxt_timer(unsigned long data
)
5157 struct bnxt
*bp
= (struct bnxt
*)data
;
5158 struct net_device
*dev
= bp
->dev
;
5160 if (!netif_running(dev
))
5163 if (atomic_read(&bp
->intr_sem
) != 0)
5164 goto bnxt_restart_timer
;
5167 mod_timer(&bp
->timer
, jiffies
+ bp
->current_interval
);
5170 static void bnxt_cfg_ntp_filters(struct bnxt
*);
5172 static void bnxt_sp_task(struct work_struct
*work
)
5174 struct bnxt
*bp
= container_of(work
, struct bnxt
, sp_task
);
5177 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5178 smp_mb__after_atomic();
5179 if (!test_bit(BNXT_STATE_OPEN
, &bp
->state
)) {
5180 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5184 if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT
, &bp
->sp_event
))
5185 bnxt_cfg_rx_mode(bp
);
5187 if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
))
5188 bnxt_cfg_ntp_filters(bp
);
5189 if (test_and_clear_bit(BNXT_LINK_CHNG_SP_EVENT
, &bp
->sp_event
)) {
5190 rc
= bnxt_update_link(bp
, true);
5192 netdev_err(bp
->dev
, "SP task can't update link (rc: %x)\n",
5195 if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT
, &bp
->sp_event
))
5196 bnxt_hwrm_exec_fwd_req(bp
);
5197 if (test_and_clear_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
)) {
5198 bnxt_hwrm_tunnel_dst_port_alloc(
5200 TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5202 if (test_and_clear_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
)) {
5203 bnxt_hwrm_tunnel_dst_port_free(
5204 bp
, TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN
);
5206 if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT
, &bp
->sp_event
)) {
5207 /* bnxt_reset_task() calls bnxt_close_nic() which waits
5208 * for BNXT_STATE_IN_SP_TASK to clear.
5210 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5212 bnxt_reset_task(bp
);
5213 set_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5217 smp_mb__before_atomic();
5218 clear_bit(BNXT_STATE_IN_SP_TASK
, &bp
->state
);
5221 static int bnxt_init_board(struct pci_dev
*pdev
, struct net_device
*dev
)
5224 struct bnxt
*bp
= netdev_priv(dev
);
5226 SET_NETDEV_DEV(dev
, &pdev
->dev
);
5228 /* enable device (incl. PCI PM wakeup), and bus-mastering */
5229 rc
= pci_enable_device(pdev
);
5231 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
5235 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
5237 "Cannot find PCI device base address, aborting\n");
5239 goto init_err_disable
;
5242 rc
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
5244 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
5245 goto init_err_disable
;
5248 if (dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(64)) != 0 &&
5249 dma_set_mask_and_coherent(&pdev
->dev
, DMA_BIT_MASK(32)) != 0) {
5250 dev_err(&pdev
->dev
, "System does not support DMA, aborting\n");
5251 goto init_err_disable
;
5254 pci_set_master(pdev
);
5259 bp
->bar0
= pci_ioremap_bar(pdev
, 0);
5261 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
5263 goto init_err_release
;
5266 bp
->bar1
= pci_ioremap_bar(pdev
, 2);
5268 dev_err(&pdev
->dev
, "Cannot map doorbell registers, aborting\n");
5270 goto init_err_release
;
5273 bp
->bar2
= pci_ioremap_bar(pdev
, 4);
5275 dev_err(&pdev
->dev
, "Cannot map bar4 registers, aborting\n");
5277 goto init_err_release
;
5280 INIT_WORK(&bp
->sp_task
, bnxt_sp_task
);
5282 spin_lock_init(&bp
->ntp_fltr_lock
);
5284 bp
->rx_ring_size
= BNXT_DEFAULT_RX_RING_SIZE
;
5285 bp
->tx_ring_size
= BNXT_DEFAULT_TX_RING_SIZE
;
5287 bp
->coal_ticks
= BNXT_USEC_TO_COAL_TIMER(4);
5289 bp
->coal_ticks_irq
= BNXT_USEC_TO_COAL_TIMER(1);
5290 bp
->coal_bufs_irq
= 2;
5292 init_timer(&bp
->timer
);
5293 bp
->timer
.data
= (unsigned long)bp
;
5294 bp
->timer
.function
= bnxt_timer
;
5295 bp
->current_interval
= BNXT_TIMER_INTERVAL
;
5297 clear_bit(BNXT_STATE_OPEN
, &bp
->state
);
5303 pci_iounmap(pdev
, bp
->bar2
);
5308 pci_iounmap(pdev
, bp
->bar1
);
5313 pci_iounmap(pdev
, bp
->bar0
);
5317 pci_release_regions(pdev
);
5320 pci_disable_device(pdev
);
5326 /* rtnl_lock held */
5327 static int bnxt_change_mac_addr(struct net_device
*dev
, void *p
)
5329 struct sockaddr
*addr
= p
;
5330 struct bnxt
*bp
= netdev_priv(dev
);
5333 if (!is_valid_ether_addr(addr
->sa_data
))
5334 return -EADDRNOTAVAIL
;
5336 #ifdef CONFIG_BNXT_SRIOV
5337 if (BNXT_VF(bp
) && is_valid_ether_addr(bp
->vf
.mac_addr
))
5338 return -EADDRNOTAVAIL
;
5341 if (ether_addr_equal(addr
->sa_data
, dev
->dev_addr
))
5344 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
5345 if (netif_running(dev
)) {
5346 bnxt_close_nic(bp
, false, false);
5347 rc
= bnxt_open_nic(bp
, false, false);
5353 /* rtnl_lock held */
5354 static int bnxt_change_mtu(struct net_device
*dev
, int new_mtu
)
5356 struct bnxt
*bp
= netdev_priv(dev
);
5358 if (new_mtu
< 60 || new_mtu
> 9000)
5361 if (netif_running(dev
))
5362 bnxt_close_nic(bp
, false, false);
5365 bnxt_set_ring_params(bp
);
5367 if (netif_running(dev
))
5368 return bnxt_open_nic(bp
, false, false);
5373 static int bnxt_setup_tc(struct net_device
*dev
, u32 handle
, __be16 proto
,
5374 struct tc_to_netdev
*ntc
)
5376 struct bnxt
*bp
= netdev_priv(dev
);
5379 if (handle
!= TC_H_ROOT
|| ntc
->type
!= TC_SETUP_MQPRIO
)
5384 if (tc
> bp
->max_tc
) {
5385 netdev_err(dev
, "too many traffic classes requested: %d Max supported is %d\n",
5390 if (netdev_get_num_tc(dev
) == tc
)
5394 int max_rx_rings
, max_tx_rings
, rc
;
5397 if (bp
->flags
& BNXT_FLAG_SHARED_RINGS
)
5400 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5401 if (rc
|| bp
->tx_nr_rings_per_tc
* tc
> max_tx_rings
)
5405 /* Needs to close the device and do hw resource re-allocations */
5406 if (netif_running(bp
->dev
))
5407 bnxt_close_nic(bp
, true, false);
5410 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
* tc
;
5411 netdev_set_num_tc(dev
, tc
);
5413 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5414 netdev_reset_tc(dev
);
5416 bp
->cp_nr_rings
= max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
);
5417 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5419 if (netif_running(bp
->dev
))
5420 return bnxt_open_nic(bp
, true, false);
5425 #ifdef CONFIG_RFS_ACCEL
5426 static bool bnxt_fltr_match(struct bnxt_ntuple_filter
*f1
,
5427 struct bnxt_ntuple_filter
*f2
)
5429 struct flow_keys
*keys1
= &f1
->fkeys
;
5430 struct flow_keys
*keys2
= &f2
->fkeys
;
5432 if (keys1
->addrs
.v4addrs
.src
== keys2
->addrs
.v4addrs
.src
&&
5433 keys1
->addrs
.v4addrs
.dst
== keys2
->addrs
.v4addrs
.dst
&&
5434 keys1
->ports
.ports
== keys2
->ports
.ports
&&
5435 keys1
->basic
.ip_proto
== keys2
->basic
.ip_proto
&&
5436 keys1
->basic
.n_proto
== keys2
->basic
.n_proto
&&
5437 ether_addr_equal(f1
->src_mac_addr
, f2
->src_mac_addr
))
5443 static int bnxt_rx_flow_steer(struct net_device
*dev
, const struct sk_buff
*skb
,
5444 u16 rxq_index
, u32 flow_id
)
5446 struct bnxt
*bp
= netdev_priv(dev
);
5447 struct bnxt_ntuple_filter
*fltr
, *new_fltr
;
5448 struct flow_keys
*fkeys
;
5449 struct ethhdr
*eth
= (struct ethhdr
*)skb_mac_header(skb
);
5450 int rc
= 0, idx
, bit_id
;
5451 struct hlist_head
*head
;
5453 if (skb
->encapsulation
)
5454 return -EPROTONOSUPPORT
;
5456 new_fltr
= kzalloc(sizeof(*new_fltr
), GFP_ATOMIC
);
5460 fkeys
= &new_fltr
->fkeys
;
5461 if (!skb_flow_dissect_flow_keys(skb
, fkeys
, 0)) {
5462 rc
= -EPROTONOSUPPORT
;
5466 if ((fkeys
->basic
.n_proto
!= htons(ETH_P_IP
)) ||
5467 ((fkeys
->basic
.ip_proto
!= IPPROTO_TCP
) &&
5468 (fkeys
->basic
.ip_proto
!= IPPROTO_UDP
))) {
5469 rc
= -EPROTONOSUPPORT
;
5473 memcpy(new_fltr
->src_mac_addr
, eth
->h_source
, ETH_ALEN
);
5475 idx
= skb_get_hash_raw(skb
) & BNXT_NTP_FLTR_HASH_MASK
;
5476 head
= &bp
->ntp_fltr_hash_tbl
[idx
];
5478 hlist_for_each_entry_rcu(fltr
, head
, hash
) {
5479 if (bnxt_fltr_match(fltr
, new_fltr
)) {
5487 spin_lock_bh(&bp
->ntp_fltr_lock
);
5488 bit_id
= bitmap_find_free_region(bp
->ntp_fltr_bmap
,
5489 BNXT_NTP_FLTR_MAX_FLTR
, 0);
5491 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5496 new_fltr
->sw_id
= (u16
)bit_id
;
5497 new_fltr
->flow_id
= flow_id
;
5498 new_fltr
->rxq
= rxq_index
;
5499 hlist_add_head_rcu(&new_fltr
->hash
, head
);
5500 bp
->ntp_fltr_count
++;
5501 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5503 set_bit(BNXT_RX_NTP_FLTR_SP_EVENT
, &bp
->sp_event
);
5504 schedule_work(&bp
->sp_task
);
5506 return new_fltr
->sw_id
;
5513 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5517 for (i
= 0; i
< BNXT_NTP_FLTR_HASH_SIZE
; i
++) {
5518 struct hlist_head
*head
;
5519 struct hlist_node
*tmp
;
5520 struct bnxt_ntuple_filter
*fltr
;
5523 head
= &bp
->ntp_fltr_hash_tbl
[i
];
5524 hlist_for_each_entry_safe(fltr
, tmp
, head
, hash
) {
5527 if (test_bit(BNXT_FLTR_VALID
, &fltr
->state
)) {
5528 if (rps_may_expire_flow(bp
->dev
, fltr
->rxq
,
5531 bnxt_hwrm_cfa_ntuple_filter_free(bp
,
5536 rc
= bnxt_hwrm_cfa_ntuple_filter_alloc(bp
,
5541 set_bit(BNXT_FLTR_VALID
, &fltr
->state
);
5545 spin_lock_bh(&bp
->ntp_fltr_lock
);
5546 hlist_del_rcu(&fltr
->hash
);
5547 bp
->ntp_fltr_count
--;
5548 spin_unlock_bh(&bp
->ntp_fltr_lock
);
5550 clear_bit(fltr
->sw_id
, bp
->ntp_fltr_bmap
);
5559 static void bnxt_cfg_ntp_filters(struct bnxt
*bp
)
5563 #endif /* CONFIG_RFS_ACCEL */
5565 static void bnxt_add_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5568 struct bnxt
*bp
= netdev_priv(dev
);
5570 if (!netif_running(dev
))
5573 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5576 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
!= port
)
5579 bp
->vxlan_port_cnt
++;
5580 if (bp
->vxlan_port_cnt
== 1) {
5581 bp
->vxlan_port
= port
;
5582 set_bit(BNXT_VXLAN_ADD_PORT_SP_EVENT
, &bp
->sp_event
);
5583 schedule_work(&bp
->sp_task
);
5587 static void bnxt_del_vxlan_port(struct net_device
*dev
, sa_family_t sa_family
,
5590 struct bnxt
*bp
= netdev_priv(dev
);
5592 if (!netif_running(dev
))
5595 if (sa_family
!= AF_INET6
&& sa_family
!= AF_INET
)
5598 if (bp
->vxlan_port_cnt
&& bp
->vxlan_port
== port
) {
5599 bp
->vxlan_port_cnt
--;
5601 if (bp
->vxlan_port_cnt
== 0) {
5602 set_bit(BNXT_VXLAN_DEL_PORT_SP_EVENT
, &bp
->sp_event
);
5603 schedule_work(&bp
->sp_task
);
5608 static const struct net_device_ops bnxt_netdev_ops
= {
5609 .ndo_open
= bnxt_open
,
5610 .ndo_start_xmit
= bnxt_start_xmit
,
5611 .ndo_stop
= bnxt_close
,
5612 .ndo_get_stats64
= bnxt_get_stats64
,
5613 .ndo_set_rx_mode
= bnxt_set_rx_mode
,
5614 .ndo_do_ioctl
= bnxt_ioctl
,
5615 .ndo_validate_addr
= eth_validate_addr
,
5616 .ndo_set_mac_address
= bnxt_change_mac_addr
,
5617 .ndo_change_mtu
= bnxt_change_mtu
,
5618 .ndo_fix_features
= bnxt_fix_features
,
5619 .ndo_set_features
= bnxt_set_features
,
5620 .ndo_tx_timeout
= bnxt_tx_timeout
,
5621 #ifdef CONFIG_BNXT_SRIOV
5622 .ndo_get_vf_config
= bnxt_get_vf_config
,
5623 .ndo_set_vf_mac
= bnxt_set_vf_mac
,
5624 .ndo_set_vf_vlan
= bnxt_set_vf_vlan
,
5625 .ndo_set_vf_rate
= bnxt_set_vf_bw
,
5626 .ndo_set_vf_link_state
= bnxt_set_vf_link_state
,
5627 .ndo_set_vf_spoofchk
= bnxt_set_vf_spoofchk
,
5629 #ifdef CONFIG_NET_POLL_CONTROLLER
5630 .ndo_poll_controller
= bnxt_poll_controller
,
5632 .ndo_setup_tc
= bnxt_setup_tc
,
5633 #ifdef CONFIG_RFS_ACCEL
5634 .ndo_rx_flow_steer
= bnxt_rx_flow_steer
,
5636 .ndo_add_vxlan_port
= bnxt_add_vxlan_port
,
5637 .ndo_del_vxlan_port
= bnxt_del_vxlan_port
,
5638 #ifdef CONFIG_NET_RX_BUSY_POLL
5639 .ndo_busy_poll
= bnxt_busy_poll
,
5643 static void bnxt_remove_one(struct pci_dev
*pdev
)
5645 struct net_device
*dev
= pci_get_drvdata(pdev
);
5646 struct bnxt
*bp
= netdev_priv(dev
);
5649 bnxt_sriov_disable(bp
);
5651 unregister_netdev(dev
);
5652 cancel_work_sync(&bp
->sp_task
);
5655 bnxt_hwrm_func_drv_unrgtr(bp
);
5656 bnxt_free_hwrm_resources(bp
);
5657 pci_iounmap(pdev
, bp
->bar2
);
5658 pci_iounmap(pdev
, bp
->bar1
);
5659 pci_iounmap(pdev
, bp
->bar0
);
5662 pci_release_regions(pdev
);
5663 pci_disable_device(pdev
);
5666 static int bnxt_probe_phy(struct bnxt
*bp
)
5669 struct bnxt_link_info
*link_info
= &bp
->link_info
;
5670 char phy_ver
[PHY_VER_STR_LEN
];
5672 rc
= bnxt_update_link(bp
, false);
5674 netdev_err(bp
->dev
, "Probe phy can't update link (rc: %x)\n",
5679 /*initialize the ethool setting copy with NVM settings */
5680 if (BNXT_AUTO_MODE(link_info
->auto_mode
))
5681 link_info
->autoneg
|= BNXT_AUTONEG_SPEED
;
5683 if (link_info
->auto_pause_setting
& BNXT_LINK_PAUSE_BOTH
) {
5684 if (link_info
->auto_pause_setting
== BNXT_LINK_PAUSE_BOTH
)
5685 link_info
->autoneg
|= BNXT_AUTONEG_FLOW_CTRL
;
5686 link_info
->req_flow_ctrl
= link_info
->auto_pause_setting
;
5687 } else if (link_info
->force_pause_setting
& BNXT_LINK_PAUSE_BOTH
) {
5688 link_info
->req_flow_ctrl
= link_info
->force_pause_setting
;
5690 link_info
->req_duplex
= link_info
->duplex_setting
;
5691 if (link_info
->autoneg
& BNXT_AUTONEG_SPEED
)
5692 link_info
->req_link_speed
= link_info
->auto_link_speed
;
5694 link_info
->req_link_speed
= link_info
->force_link_speed
;
5695 link_info
->advertising
= link_info
->auto_link_speeds
;
5696 snprintf(phy_ver
, PHY_VER_STR_LEN
, " ph %d.%d.%d",
5697 link_info
->phy_ver
[0],
5698 link_info
->phy_ver
[1],
5699 link_info
->phy_ver
[2]);
5700 strcat(bp
->fw_ver_str
, phy_ver
);
5704 static int bnxt_get_max_irq(struct pci_dev
*pdev
)
5708 if (!pdev
->msix_cap
)
5711 pci_read_config_word(pdev
, pdev
->msix_cap
+ PCI_MSIX_FLAGS
, &ctrl
);
5712 return (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
5715 static void _bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
,
5718 int max_ring_grps
= 0;
5720 #ifdef CONFIG_BNXT_SRIOV
5722 *max_tx
= bp
->vf
.max_tx_rings
;
5723 *max_rx
= bp
->vf
.max_rx_rings
;
5724 *max_cp
= min_t(int, bp
->vf
.max_irqs
, bp
->vf
.max_cp_rings
);
5725 *max_cp
= min_t(int, *max_cp
, bp
->vf
.max_stat_ctxs
);
5726 max_ring_grps
= bp
->vf
.max_hw_ring_grps
;
5730 *max_tx
= bp
->pf
.max_tx_rings
;
5731 *max_rx
= bp
->pf
.max_rx_rings
;
5732 *max_cp
= min_t(int, bp
->pf
.max_irqs
, bp
->pf
.max_cp_rings
);
5733 *max_cp
= min_t(int, *max_cp
, bp
->pf
.max_stat_ctxs
);
5734 max_ring_grps
= bp
->pf
.max_hw_ring_grps
;
5737 if (bp
->flags
& BNXT_FLAG_AGG_RINGS
)
5739 *max_rx
= min_t(int, *max_rx
, max_ring_grps
);
5742 int bnxt_get_max_rings(struct bnxt
*bp
, int *max_rx
, int *max_tx
, bool shared
)
5746 _bnxt_get_max_rings(bp
, &rx
, &tx
, &cp
);
5747 if (!rx
|| !tx
|| !cp
)
5752 return bnxt_trim_rings(bp
, max_rx
, max_tx
, cp
, shared
);
5755 static int bnxt_set_dflt_rings(struct bnxt
*bp
)
5757 int dflt_rings
, max_rx_rings
, max_tx_rings
, rc
;
5761 bp
->flags
|= BNXT_FLAG_SHARED_RINGS
;
5762 dflt_rings
= netif_get_num_default_rss_queues();
5763 rc
= bnxt_get_max_rings(bp
, &max_rx_rings
, &max_tx_rings
, sh
);
5766 bp
->rx_nr_rings
= min_t(int, dflt_rings
, max_rx_rings
);
5767 bp
->tx_nr_rings_per_tc
= min_t(int, dflt_rings
, max_tx_rings
);
5768 bp
->tx_nr_rings
= bp
->tx_nr_rings_per_tc
;
5769 bp
->cp_nr_rings
= sh
? max_t(int, bp
->tx_nr_rings
, bp
->rx_nr_rings
) :
5770 bp
->tx_nr_rings
+ bp
->rx_nr_rings
;
5771 bp
->num_stat_ctxs
= bp
->cp_nr_rings
;
5775 static int bnxt_init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
5777 static int version_printed
;
5778 struct net_device
*dev
;
5782 if (version_printed
++ == 0)
5783 pr_info("%s", version
);
5785 max_irqs
= bnxt_get_max_irq(pdev
);
5786 dev
= alloc_etherdev_mq(sizeof(*bp
), max_irqs
);
5790 bp
= netdev_priv(dev
);
5792 if (bnxt_vf_pciid(ent
->driver_data
))
5793 bp
->flags
|= BNXT_FLAG_VF
;
5796 bp
->flags
|= BNXT_FLAG_MSIX_CAP
;
5798 rc
= bnxt_init_board(pdev
, dev
);
5802 dev
->netdev_ops
= &bnxt_netdev_ops
;
5803 dev
->watchdog_timeo
= BNXT_TX_TIMEOUT
;
5804 dev
->ethtool_ops
= &bnxt_ethtool_ops
;
5806 pci_set_drvdata(pdev
, dev
);
5808 dev
->hw_features
= NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5809 NETIF_F_TSO
| NETIF_F_TSO6
|
5810 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5811 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
|
5813 NETIF_F_RXCSUM
| NETIF_F_LRO
| NETIF_F_GRO
;
5815 dev
->hw_enc_features
=
5816 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
| NETIF_F_SG
|
5817 NETIF_F_TSO
| NETIF_F_TSO6
|
5818 NETIF_F_GSO_UDP_TUNNEL
| NETIF_F_GSO_GRE
|
5819 NETIF_F_GSO_IPIP
| NETIF_F_GSO_SIT
;
5820 dev
->vlan_features
= dev
->hw_features
| NETIF_F_HIGHDMA
;
5821 dev
->hw_features
|= NETIF_F_HW_VLAN_CTAG_RX
| NETIF_F_HW_VLAN_CTAG_TX
|
5822 NETIF_F_HW_VLAN_STAG_RX
| NETIF_F_HW_VLAN_STAG_TX
;
5823 dev
->features
|= dev
->hw_features
| NETIF_F_HIGHDMA
;
5824 dev
->priv_flags
|= IFF_UNICAST_FLT
;
5826 #ifdef CONFIG_BNXT_SRIOV
5827 init_waitqueue_head(&bp
->sriov_cfg_wait
);
5829 rc
= bnxt_alloc_hwrm_resources(bp
);
5833 mutex_init(&bp
->hwrm_cmd_lock
);
5834 bnxt_hwrm_ver_get(bp
);
5836 rc
= bnxt_hwrm_func_drv_rgtr(bp
);
5840 /* Get the MAX capabilities for this function */
5841 rc
= bnxt_hwrm_func_qcaps(bp
);
5843 netdev_err(bp
->dev
, "hwrm query capability failure rc: %x\n",
5849 rc
= bnxt_hwrm_queue_qportcfg(bp
);
5851 netdev_err(bp
->dev
, "hwrm query qportcfg failure rc: %x\n",
5857 bnxt_set_tpa_flags(bp
);
5858 bnxt_set_ring_params(bp
);
5860 bp
->pf
.max_irqs
= max_irqs
;
5861 #if defined(CONFIG_BNXT_SRIOV)
5863 bp
->vf
.max_irqs
= max_irqs
;
5865 bnxt_set_dflt_rings(bp
);
5868 dev
->hw_features
|= NETIF_F_NTUPLE
;
5869 if (bnxt_rfs_capable(bp
)) {
5870 bp
->flags
|= BNXT_FLAG_RFS
;
5871 dev
->features
|= NETIF_F_NTUPLE
;
5875 if (dev
->hw_features
& NETIF_F_HW_VLAN_CTAG_RX
)
5876 bp
->flags
|= BNXT_FLAG_STRIP_VLAN
;
5878 rc
= bnxt_probe_phy(bp
);
5882 rc
= register_netdev(dev
);
5886 netdev_info(dev
, "%s found at mem %lx, node addr %pM\n",
5887 board_info
[ent
->driver_data
].name
,
5888 (long)pci_resource_start(pdev
, 0), dev
->dev_addr
);
5893 pci_iounmap(pdev
, bp
->bar0
);
5894 pci_release_regions(pdev
);
5895 pci_disable_device(pdev
);
5902 static struct pci_driver bnxt_pci_driver
= {
5903 .name
= DRV_MODULE_NAME
,
5904 .id_table
= bnxt_pci_tbl
,
5905 .probe
= bnxt_init_one
,
5906 .remove
= bnxt_remove_one
,
5907 #if defined(CONFIG_BNXT_SRIOV)
5908 .sriov_configure
= bnxt_sriov_configure
,
5912 module_pci_driver(bnxt_pci_driver
);