projects / deliverable / linux.git / blob
? search:


5e3cd76cb69bd25c7f2fef3c778458c1b8966a63
[deliverable/linux.git] / drivers / net / ethernet / broadcom / genet / bcmgenet.c
1 /*
2 * Broadcom GENET (Gigabit Ethernet) controller driver
3 *
4 * Copyright (c) 2014 Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) "bcmgenet: " fmt
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/pm.h>
27 #include <linux/clk.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
33 #include <net/arp.h>
34
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
41 #include <linux/in.h>
42 #include <linux/ip.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
46
47 #include <asm/unaligned.h>
48
49 #include "bcmgenet.h"
50
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
53
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
56
57 #define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
59 #define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
61
62 #define RX_BUF_LENGTH 2048
63 #define SKB_ALIGNMENT 32
64
65 /* Tx/Rx DMA register offset, skip 256 descriptors */
66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
68
69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
71
72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
74
75 static inline void dmadesc_set_length_status(struct bcmgenet_priv *priv,
76 void __iomem *d, u32 value)
77 {
78 __raw_writel(value, d + DMA_DESC_LENGTH_STATUS);
79 }
80
81 static inline u32 dmadesc_get_length_status(struct bcmgenet_priv *priv,
82 void __iomem *d)
83 {
84 return __raw_readl(d + DMA_DESC_LENGTH_STATUS);
85 }
86
87 static inline void dmadesc_set_addr(struct bcmgenet_priv *priv,
88 void __iomem *d,
89 dma_addr_t addr)
90 {
91 __raw_writel(lower_32_bits(addr), d + DMA_DESC_ADDRESS_LO);
92
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
95 * the platform is explicitly configured for 64-bits/LPAE.
96 */
97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv->hw_params->flags & GENET_HAS_40BITS)
99 __raw_writel(upper_32_bits(addr), d + DMA_DESC_ADDRESS_HI);
100 #endif
101 }
102
103 /* Combined address + length/status setter */
104 static inline void dmadesc_set(struct bcmgenet_priv *priv,
105 void __iomem *d, dma_addr_t addr, u32 val)
106 {
107 dmadesc_set_length_status(priv, d, val);
108 dmadesc_set_addr(priv, d, addr);
109 }
110
111 static inline dma_addr_t dmadesc_get_addr(struct bcmgenet_priv *priv,
112 void __iomem *d)
113 {
114 dma_addr_t addr;
115
116 addr = __raw_readl(d + DMA_DESC_ADDRESS_LO);
117
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
120 * the platform is explicitly configured for 64-bits/LPAE.
121 */
122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv->hw_params->flags & GENET_HAS_40BITS)
124 addr |= (u64)__raw_readl(d + DMA_DESC_ADDRESS_HI) << 32;
125 #endif
126 return addr;
127 }
128
129 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
130
131 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 NETIF_MSG_LINK)
133
134 static inline u32 bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv *priv)
135 {
136 if (GENET_IS_V1(priv))
137 return bcmgenet_rbuf_readl(priv, RBUF_FLUSH_CTRL_V1);
138 else
139 return bcmgenet_sys_readl(priv, SYS_RBUF_FLUSH_CTRL);
140 }
141
142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
143 {
144 if (GENET_IS_V1(priv))
145 bcmgenet_rbuf_writel(priv, val, RBUF_FLUSH_CTRL_V1);
146 else
147 bcmgenet_sys_writel(priv, val, SYS_RBUF_FLUSH_CTRL);
148 }
149
150 /* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
153 */
154 static inline u32 bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv *priv)
155 {
156 if (GENET_IS_V1(priv))
157 return bcmgenet_rbuf_readl(priv, TBUF_CTRL_V1);
158 else
159 return __raw_readl(priv->base +
160 priv->hw_params->tbuf_offset + TBUF_CTRL);
161 }
162
163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv *priv, u32 val)
164 {
165 if (GENET_IS_V1(priv))
166 bcmgenet_rbuf_writel(priv, val, TBUF_CTRL_V1);
167 else
168 __raw_writel(val, priv->base +
169 priv->hw_params->tbuf_offset + TBUF_CTRL);
170 }
171
172 static inline u32 bcmgenet_bp_mc_get(struct bcmgenet_priv *priv)
173 {
174 if (GENET_IS_V1(priv))
175 return bcmgenet_rbuf_readl(priv, TBUF_BP_MC_V1);
176 else
177 return __raw_readl(priv->base +
178 priv->hw_params->tbuf_offset + TBUF_BP_MC);
179 }
180
181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv *priv, u32 val)
182 {
183 if (GENET_IS_V1(priv))
184 bcmgenet_rbuf_writel(priv, val, TBUF_BP_MC_V1);
185 else
186 __raw_writel(val, priv->base +
187 priv->hw_params->tbuf_offset + TBUF_BP_MC);
188 }
189
190 /* RX/TX DMA register accessors */
191 enum dma_reg {
192 DMA_RING_CFG = 0,
193 DMA_CTRL,
194 DMA_STATUS,
195 DMA_SCB_BURST_SIZE,
196 DMA_ARB_CTRL,
197 DMA_PRIORITY_0,
198 DMA_PRIORITY_1,
199 DMA_PRIORITY_2,
200 DMA_INDEX2RING_0,
201 DMA_INDEX2RING_1,
202 DMA_INDEX2RING_2,
203 DMA_INDEX2RING_3,
204 DMA_INDEX2RING_4,
205 DMA_INDEX2RING_5,
206 DMA_INDEX2RING_6,
207 DMA_INDEX2RING_7,
208 };
209
210 static const u8 bcmgenet_dma_regs_v3plus[] = {
211 [DMA_RING_CFG] = 0x00,
212 [DMA_CTRL] = 0x04,
213 [DMA_STATUS] = 0x08,
214 [DMA_SCB_BURST_SIZE] = 0x0C,
215 [DMA_ARB_CTRL] = 0x2C,
216 [DMA_PRIORITY_0] = 0x30,
217 [DMA_PRIORITY_1] = 0x34,
218 [DMA_PRIORITY_2] = 0x38,
219 [DMA_INDEX2RING_0] = 0x70,
220 [DMA_INDEX2RING_1] = 0x74,
221 [DMA_INDEX2RING_2] = 0x78,
222 [DMA_INDEX2RING_3] = 0x7C,
223 [DMA_INDEX2RING_4] = 0x80,
224 [DMA_INDEX2RING_5] = 0x84,
225 [DMA_INDEX2RING_6] = 0x88,
226 [DMA_INDEX2RING_7] = 0x8C,
227 };
228
229 static const u8 bcmgenet_dma_regs_v2[] = {
230 [DMA_RING_CFG] = 0x00,
231 [DMA_CTRL] = 0x04,
232 [DMA_STATUS] = 0x08,
233 [DMA_SCB_BURST_SIZE] = 0x0C,
234 [DMA_ARB_CTRL] = 0x30,
235 [DMA_PRIORITY_0] = 0x34,
236 [DMA_PRIORITY_1] = 0x38,
237 [DMA_PRIORITY_2] = 0x3C,
238 };
239
240 static const u8 bcmgenet_dma_regs_v1[] = {
241 [DMA_CTRL] = 0x00,
242 [DMA_STATUS] = 0x04,
243 [DMA_SCB_BURST_SIZE] = 0x0C,
244 [DMA_ARB_CTRL] = 0x30,
245 [DMA_PRIORITY_0] = 0x34,
246 [DMA_PRIORITY_1] = 0x38,
247 [DMA_PRIORITY_2] = 0x3C,
248 };
249
250 /* Set at runtime once bcmgenet version is known */
251 static const u8 *bcmgenet_dma_regs;
252
253 static inline struct bcmgenet_priv *dev_to_priv(struct device *dev)
254 {
255 return netdev_priv(dev_get_drvdata(dev));
256 }
257
258 static inline u32 bcmgenet_tdma_readl(struct bcmgenet_priv *priv,
259 enum dma_reg r)
260 {
261 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
262 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
263 }
264
265 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv *priv,
266 u32 val, enum dma_reg r)
267 {
268 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
269 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
270 }
271
272 static inline u32 bcmgenet_rdma_readl(struct bcmgenet_priv *priv,
273 enum dma_reg r)
274 {
275 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
276 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
277 }
278
279 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv *priv,
280 u32 val, enum dma_reg r)
281 {
282 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
283 DMA_RINGS_SIZE + bcmgenet_dma_regs[r]);
284 }
285
286 /* RDMA/TDMA ring registers and accessors
287 * we merge the common fields and just prefix with T/D the registers
288 * having different meaning depending on the direction
289 */
290 enum dma_ring_reg {
291 TDMA_READ_PTR = 0,
292 RDMA_WRITE_PTR = TDMA_READ_PTR,
293 TDMA_READ_PTR_HI,
294 RDMA_WRITE_PTR_HI = TDMA_READ_PTR_HI,
295 TDMA_CONS_INDEX,
296 RDMA_PROD_INDEX = TDMA_CONS_INDEX,
297 TDMA_PROD_INDEX,
298 RDMA_CONS_INDEX = TDMA_PROD_INDEX,
299 DMA_RING_BUF_SIZE,
300 DMA_START_ADDR,
301 DMA_START_ADDR_HI,
302 DMA_END_ADDR,
303 DMA_END_ADDR_HI,
304 DMA_MBUF_DONE_THRESH,
305 TDMA_FLOW_PERIOD,
306 RDMA_XON_XOFF_THRESH = TDMA_FLOW_PERIOD,
307 TDMA_WRITE_PTR,
308 RDMA_READ_PTR = TDMA_WRITE_PTR,
309 TDMA_WRITE_PTR_HI,
310 RDMA_READ_PTR_HI = TDMA_WRITE_PTR_HI
311 };
312
313 /* GENET v4 supports 40-bits pointer addressing
314 * for obvious reasons the LO and HI word parts
315 * are contiguous, but this offsets the other
316 * registers.
317 */
318 static const u8 genet_dma_ring_regs_v4[] = {
319 [TDMA_READ_PTR] = 0x00,
320 [TDMA_READ_PTR_HI] = 0x04,
321 [TDMA_CONS_INDEX] = 0x08,
322 [TDMA_PROD_INDEX] = 0x0C,
323 [DMA_RING_BUF_SIZE] = 0x10,
324 [DMA_START_ADDR] = 0x14,
325 [DMA_START_ADDR_HI] = 0x18,
326 [DMA_END_ADDR] = 0x1C,
327 [DMA_END_ADDR_HI] = 0x20,
328 [DMA_MBUF_DONE_THRESH] = 0x24,
329 [TDMA_FLOW_PERIOD] = 0x28,
330 [TDMA_WRITE_PTR] = 0x2C,
331 [TDMA_WRITE_PTR_HI] = 0x30,
332 };
333
334 static const u8 genet_dma_ring_regs_v123[] = {
335 [TDMA_READ_PTR] = 0x00,
336 [TDMA_CONS_INDEX] = 0x04,
337 [TDMA_PROD_INDEX] = 0x08,
338 [DMA_RING_BUF_SIZE] = 0x0C,
339 [DMA_START_ADDR] = 0x10,
340 [DMA_END_ADDR] = 0x14,
341 [DMA_MBUF_DONE_THRESH] = 0x18,
342 [TDMA_FLOW_PERIOD] = 0x1C,
343 [TDMA_WRITE_PTR] = 0x20,
344 };
345
346 /* Set at runtime once GENET version is known */
347 static const u8 *genet_dma_ring_regs;
348
349 static inline u32 bcmgenet_tdma_ring_readl(struct bcmgenet_priv *priv,
350 unsigned int ring,
351 enum dma_ring_reg r)
352 {
353 return __raw_readl(priv->base + GENET_TDMA_REG_OFF +
354 (DMA_RING_SIZE * ring) +
355 genet_dma_ring_regs[r]);
356 }
357
358 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv *priv,
359 unsigned int ring, u32 val,
360 enum dma_ring_reg r)
361 {
362 __raw_writel(val, priv->base + GENET_TDMA_REG_OFF +
363 (DMA_RING_SIZE * ring) +
364 genet_dma_ring_regs[r]);
365 }
366
367 static inline u32 bcmgenet_rdma_ring_readl(struct bcmgenet_priv *priv,
368 unsigned int ring,
369 enum dma_ring_reg r)
370 {
371 return __raw_readl(priv->base + GENET_RDMA_REG_OFF +
372 (DMA_RING_SIZE * ring) +
373 genet_dma_ring_regs[r]);
374 }
375
376 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv *priv,
377 unsigned int ring, u32 val,
378 enum dma_ring_reg r)
379 {
380 __raw_writel(val, priv->base + GENET_RDMA_REG_OFF +
381 (DMA_RING_SIZE * ring) +
382 genet_dma_ring_regs[r]);
383 }
384
385 static int bcmgenet_get_settings(struct net_device *dev,
386 struct ethtool_cmd *cmd)
387 {
388 struct bcmgenet_priv *priv = netdev_priv(dev);
389
390 if (!netif_running(dev))
391 return -EINVAL;
392
393 if (!priv->phydev)
394 return -ENODEV;
395
396 return phy_ethtool_gset(priv->phydev, cmd);
397 }
398
399 static int bcmgenet_set_settings(struct net_device *dev,
400 struct ethtool_cmd *cmd)
401 {
402 struct bcmgenet_priv *priv = netdev_priv(dev);
403
404 if (!netif_running(dev))
405 return -EINVAL;
406
407 if (!priv->phydev)
408 return -ENODEV;
409
410 return phy_ethtool_sset(priv->phydev, cmd);
411 }
412
413 static int bcmgenet_set_rx_csum(struct net_device *dev,
414 netdev_features_t wanted)
415 {
416 struct bcmgenet_priv *priv = netdev_priv(dev);
417 u32 rbuf_chk_ctrl;
418 bool rx_csum_en;
419
420 rx_csum_en = !!(wanted & NETIF_F_RXCSUM);
421
422 rbuf_chk_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CHK_CTRL);
423
424 /* enable rx checksumming */
425 if (rx_csum_en)
426 rbuf_chk_ctrl |= RBUF_RXCHK_EN;
427 else
428 rbuf_chk_ctrl &= ~RBUF_RXCHK_EN;
429 priv->desc_rxchk_en = rx_csum_en;
430
431 /* If UniMAC forwards CRC, we need to skip over it to get
432 * a valid CHK bit to be set in the per-packet status word
433 */
434 if (rx_csum_en && priv->crc_fwd_en)
435 rbuf_chk_ctrl |= RBUF_SKIP_FCS;
436 else
437 rbuf_chk_ctrl &= ~RBUF_SKIP_FCS;
438
439 bcmgenet_rbuf_writel(priv, rbuf_chk_ctrl, RBUF_CHK_CTRL);
440
441 return 0;
442 }
443
444 static int bcmgenet_set_tx_csum(struct net_device *dev,
445 netdev_features_t wanted)
446 {
447 struct bcmgenet_priv *priv = netdev_priv(dev);
448 bool desc_64b_en;
449 u32 tbuf_ctrl, rbuf_ctrl;
450
451 tbuf_ctrl = bcmgenet_tbuf_ctrl_get(priv);
452 rbuf_ctrl = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
453
454 desc_64b_en = !!(wanted & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM));
455
456 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
457 if (desc_64b_en) {
458 tbuf_ctrl |= RBUF_64B_EN;
459 rbuf_ctrl |= RBUF_64B_EN;
460 } else {
461 tbuf_ctrl &= ~RBUF_64B_EN;
462 rbuf_ctrl &= ~RBUF_64B_EN;
463 }
464 priv->desc_64b_en = desc_64b_en;
465
466 bcmgenet_tbuf_ctrl_set(priv, tbuf_ctrl);
467 bcmgenet_rbuf_writel(priv, rbuf_ctrl, RBUF_CTRL);
468
469 return 0;
470 }
471
472 static int bcmgenet_set_features(struct net_device *dev,
473 netdev_features_t features)
474 {
475 netdev_features_t changed = features ^ dev->features;
476 netdev_features_t wanted = dev->wanted_features;
477 int ret = 0;
478
479 if (changed & (NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM))
480 ret = bcmgenet_set_tx_csum(dev, wanted);
481 if (changed & (NETIF_F_RXCSUM))
482 ret = bcmgenet_set_rx_csum(dev, wanted);
483
484 return ret;
485 }
486
487 static u32 bcmgenet_get_msglevel(struct net_device *dev)
488 {
489 struct bcmgenet_priv *priv = netdev_priv(dev);
490
491 return priv->msg_enable;
492 }
493
494 static void bcmgenet_set_msglevel(struct net_device *dev, u32 level)
495 {
496 struct bcmgenet_priv *priv = netdev_priv(dev);
497
498 priv->msg_enable = level;
499 }
500
501 /* standard ethtool support functions. */
502 enum bcmgenet_stat_type {
503 BCMGENET_STAT_NETDEV = -1,
504 BCMGENET_STAT_MIB_RX,
505 BCMGENET_STAT_MIB_TX,
506 BCMGENET_STAT_RUNT,
507 BCMGENET_STAT_MISC,
508 BCMGENET_STAT_SOFT,
509 };
510
511 struct bcmgenet_stats {
512 char stat_string[ETH_GSTRING_LEN];
513 int stat_sizeof;
514 int stat_offset;
515 enum bcmgenet_stat_type type;
516 /* reg offset from UMAC base for misc counters */
517 u16 reg_offset;
518 };
519
520 #define STAT_NETDEV(m) { \
521 .stat_string = __stringify(m), \
522 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
523 .stat_offset = offsetof(struct net_device_stats, m), \
524 .type = BCMGENET_STAT_NETDEV, \
525 }
526
527 #define STAT_GENET_MIB(str, m, _type) { \
528 .stat_string = str, \
529 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
530 .stat_offset = offsetof(struct bcmgenet_priv, m), \
531 .type = _type, \
532 }
533
534 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
535 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
536 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
537 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
538
539 #define STAT_GENET_MISC(str, m, offset) { \
540 .stat_string = str, \
541 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
542 .stat_offset = offsetof(struct bcmgenet_priv, m), \
543 .type = BCMGENET_STAT_MISC, \
544 .reg_offset = offset, \
545 }
546
547
548 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
549 * between the end of TX stats and the beginning of the RX RUNT
550 */
551 #define BCMGENET_STAT_OFFSET 0xc
552
553 /* Hardware counters must be kept in sync because the order/offset
554 * is important here (order in structure declaration = order in hardware)
555 */
556 static const struct bcmgenet_stats bcmgenet_gstrings_stats[] = {
557 /* general stats */
558 STAT_NETDEV(rx_packets),
559 STAT_NETDEV(tx_packets),
560 STAT_NETDEV(rx_bytes),
561 STAT_NETDEV(tx_bytes),
562 STAT_NETDEV(rx_errors),
563 STAT_NETDEV(tx_errors),
564 STAT_NETDEV(rx_dropped),
565 STAT_NETDEV(tx_dropped),
566 STAT_NETDEV(multicast),
567 /* UniMAC RSV counters */
568 STAT_GENET_MIB_RX("rx_64_octets", mib.rx.pkt_cnt.cnt_64),
569 STAT_GENET_MIB_RX("rx_65_127_oct", mib.rx.pkt_cnt.cnt_127),
570 STAT_GENET_MIB_RX("rx_128_255_oct", mib.rx.pkt_cnt.cnt_255),
571 STAT_GENET_MIB_RX("rx_256_511_oct", mib.rx.pkt_cnt.cnt_511),
572 STAT_GENET_MIB_RX("rx_512_1023_oct", mib.rx.pkt_cnt.cnt_1023),
573 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib.rx.pkt_cnt.cnt_1518),
574 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib.rx.pkt_cnt.cnt_mgv),
575 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib.rx.pkt_cnt.cnt_2047),
576 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib.rx.pkt_cnt.cnt_4095),
577 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib.rx.pkt_cnt.cnt_9216),
578 STAT_GENET_MIB_RX("rx_pkts", mib.rx.pkt),
579 STAT_GENET_MIB_RX("rx_bytes", mib.rx.bytes),
580 STAT_GENET_MIB_RX("rx_multicast", mib.rx.mca),
581 STAT_GENET_MIB_RX("rx_broadcast", mib.rx.bca),
582 STAT_GENET_MIB_RX("rx_fcs", mib.rx.fcs),
583 STAT_GENET_MIB_RX("rx_control", mib.rx.cf),
584 STAT_GENET_MIB_RX("rx_pause", mib.rx.pf),
585 STAT_GENET_MIB_RX("rx_unknown", mib.rx.uo),
586 STAT_GENET_MIB_RX("rx_align", mib.rx.aln),
587 STAT_GENET_MIB_RX("rx_outrange", mib.rx.flr),
588 STAT_GENET_MIB_RX("rx_code", mib.rx.cde),
589 STAT_GENET_MIB_RX("rx_carrier", mib.rx.fcr),
590 STAT_GENET_MIB_RX("rx_oversize", mib.rx.ovr),
591 STAT_GENET_MIB_RX("rx_jabber", mib.rx.jbr),
592 STAT_GENET_MIB_RX("rx_mtu_err", mib.rx.mtue),
593 STAT_GENET_MIB_RX("rx_good_pkts", mib.rx.pok),
594 STAT_GENET_MIB_RX("rx_unicast", mib.rx.uc),
595 STAT_GENET_MIB_RX("rx_ppp", mib.rx.ppp),
596 STAT_GENET_MIB_RX("rx_crc", mib.rx.rcrc),
597 /* UniMAC TSV counters */
598 STAT_GENET_MIB_TX("tx_64_octets", mib.tx.pkt_cnt.cnt_64),
599 STAT_GENET_MIB_TX("tx_65_127_oct", mib.tx.pkt_cnt.cnt_127),
600 STAT_GENET_MIB_TX("tx_128_255_oct", mib.tx.pkt_cnt.cnt_255),
601 STAT_GENET_MIB_TX("tx_256_511_oct", mib.tx.pkt_cnt.cnt_511),
602 STAT_GENET_MIB_TX("tx_512_1023_oct", mib.tx.pkt_cnt.cnt_1023),
603 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib.tx.pkt_cnt.cnt_1518),
604 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib.tx.pkt_cnt.cnt_mgv),
605 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib.tx.pkt_cnt.cnt_2047),
606 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib.tx.pkt_cnt.cnt_4095),
607 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib.tx.pkt_cnt.cnt_9216),
608 STAT_GENET_MIB_TX("tx_pkts", mib.tx.pkts),
609 STAT_GENET_MIB_TX("tx_multicast", mib.tx.mca),
610 STAT_GENET_MIB_TX("tx_broadcast", mib.tx.bca),
611 STAT_GENET_MIB_TX("tx_pause", mib.tx.pf),
612 STAT_GENET_MIB_TX("tx_control", mib.tx.cf),
613 STAT_GENET_MIB_TX("tx_fcs_err", mib.tx.fcs),
614 STAT_GENET_MIB_TX("tx_oversize", mib.tx.ovr),
615 STAT_GENET_MIB_TX("tx_defer", mib.tx.drf),
616 STAT_GENET_MIB_TX("tx_excess_defer", mib.tx.edf),
617 STAT_GENET_MIB_TX("tx_single_col", mib.tx.scl),
618 STAT_GENET_MIB_TX("tx_multi_col", mib.tx.mcl),
619 STAT_GENET_MIB_TX("tx_late_col", mib.tx.lcl),
620 STAT_GENET_MIB_TX("tx_excess_col", mib.tx.ecl),
621 STAT_GENET_MIB_TX("tx_frags", mib.tx.frg),
622 STAT_GENET_MIB_TX("tx_total_col", mib.tx.ncl),
623 STAT_GENET_MIB_TX("tx_jabber", mib.tx.jbr),
624 STAT_GENET_MIB_TX("tx_bytes", mib.tx.bytes),
625 STAT_GENET_MIB_TX("tx_good_pkts", mib.tx.pok),
626 STAT_GENET_MIB_TX("tx_unicast", mib.tx.uc),
627 /* UniMAC RUNT counters */
628 STAT_GENET_RUNT("rx_runt_pkts", mib.rx_runt_cnt),
629 STAT_GENET_RUNT("rx_runt_valid_fcs", mib.rx_runt_fcs),
630 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib.rx_runt_fcs_align),
631 STAT_GENET_RUNT("rx_runt_bytes", mib.rx_runt_bytes),
632 /* Misc UniMAC counters */
633 STAT_GENET_MISC("rbuf_ovflow_cnt", mib.rbuf_ovflow_cnt,
634 UMAC_RBUF_OVFL_CNT),
635 STAT_GENET_MISC("rbuf_err_cnt", mib.rbuf_err_cnt, UMAC_RBUF_ERR_CNT),
636 STAT_GENET_MISC("mdf_err_cnt", mib.mdf_err_cnt, UMAC_MDF_ERR_CNT),
637 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib.alloc_rx_buff_failed),
638 STAT_GENET_SOFT_MIB("rx_dma_failed", mib.rx_dma_failed),
639 STAT_GENET_SOFT_MIB("tx_dma_failed", mib.tx_dma_failed),
640 };
641
642 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
643
644 static void bcmgenet_get_drvinfo(struct net_device *dev,
645 struct ethtool_drvinfo *info)
646 {
647 strlcpy(info->driver, "bcmgenet", sizeof(info->driver));
648 strlcpy(info->version, "v2.0", sizeof(info->version));
649 info->n_stats = BCMGENET_STATS_LEN;
650 }
651
652 static int bcmgenet_get_sset_count(struct net_device *dev, int string_set)
653 {
654 switch (string_set) {
655 case ETH_SS_STATS:
656 return BCMGENET_STATS_LEN;
657 default:
658 return -EOPNOTSUPP;
659 }
660 }
661
662 static void bcmgenet_get_strings(struct net_device *dev, u32 stringset,
663 u8 *data)
664 {
665 int i;
666
667 switch (stringset) {
668 case ETH_SS_STATS:
669 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
670 memcpy(data + i * ETH_GSTRING_LEN,
671 bcmgenet_gstrings_stats[i].stat_string,
672 ETH_GSTRING_LEN);
673 }
674 break;
675 }
676 }
677
678 static void bcmgenet_update_mib_counters(struct bcmgenet_priv *priv)
679 {
680 int i, j = 0;
681
682 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
683 const struct bcmgenet_stats *s;
684 u8 offset = 0;
685 u32 val = 0;
686 char *p;
687
688 s = &bcmgenet_gstrings_stats[i];
689 switch (s->type) {
690 case BCMGENET_STAT_NETDEV:
691 case BCMGENET_STAT_SOFT:
692 continue;
693 case BCMGENET_STAT_MIB_RX:
694 case BCMGENET_STAT_MIB_TX:
695 case BCMGENET_STAT_RUNT:
696 if (s->type != BCMGENET_STAT_MIB_RX)
697 offset = BCMGENET_STAT_OFFSET;
698 val = bcmgenet_umac_readl(priv,
699 UMAC_MIB_START + j + offset);
700 break;
701 case BCMGENET_STAT_MISC:
702 val = bcmgenet_umac_readl(priv, s->reg_offset);
703 /* clear if overflowed */
704 if (val == ~0)
705 bcmgenet_umac_writel(priv, 0, s->reg_offset);
706 break;
707 }
708
709 j += s->stat_sizeof;
710 p = (char *)priv + s->stat_offset;
711 *(u32 *)p = val;
712 }
713 }
714
715 static void bcmgenet_get_ethtool_stats(struct net_device *dev,
716 struct ethtool_stats *stats,
717 u64 *data)
718 {
719 struct bcmgenet_priv *priv = netdev_priv(dev);
720 int i;
721
722 if (netif_running(dev))
723 bcmgenet_update_mib_counters(priv);
724
725 for (i = 0; i < BCMGENET_STATS_LEN; i++) {
726 const struct bcmgenet_stats *s;
727 char *p;
728
729 s = &bcmgenet_gstrings_stats[i];
730 if (s->type == BCMGENET_STAT_NETDEV)
731 p = (char *)&dev->stats;
732 else
733 p = (char *)priv;
734 p += s->stat_offset;
735 data[i] = *(u32 *)p;
736 }
737 }
738
739 static void bcmgenet_eee_enable_set(struct net_device *dev, bool enable)
740 {
741 struct bcmgenet_priv *priv = netdev_priv(dev);
742 u32 off = priv->hw_params->tbuf_offset + TBUF_ENERGY_CTRL;
743 u32 reg;
744
745 if (enable && !priv->clk_eee_enabled) {
746 clk_prepare_enable(priv->clk_eee);
747 priv->clk_eee_enabled = true;
748 }
749
750 reg = bcmgenet_umac_readl(priv, UMAC_EEE_CTRL);
751 if (enable)
752 reg |= EEE_EN;
753 else
754 reg &= ~EEE_EN;
755 bcmgenet_umac_writel(priv, reg, UMAC_EEE_CTRL);
756
757 /* Enable EEE and switch to a 27Mhz clock automatically */
758 reg = __raw_readl(priv->base + off);
759 if (enable)
760 reg |= TBUF_EEE_EN | TBUF_PM_EN;
761 else
762 reg &= ~(TBUF_EEE_EN | TBUF_PM_EN);
763 __raw_writel(reg, priv->base + off);
764
765 /* Do the same for thing for RBUF */
766 reg = bcmgenet_rbuf_readl(priv, RBUF_ENERGY_CTRL);
767 if (enable)
768 reg |= RBUF_EEE_EN | RBUF_PM_EN;
769 else
770 reg &= ~(RBUF_EEE_EN | RBUF_PM_EN);
771 bcmgenet_rbuf_writel(priv, reg, RBUF_ENERGY_CTRL);
772
773 if (!enable && priv->clk_eee_enabled) {
774 clk_disable_unprepare(priv->clk_eee);
775 priv->clk_eee_enabled = false;
776 }
777
778 priv->eee.eee_enabled = enable;
779 priv->eee.eee_active = enable;
780 }
781
782 static int bcmgenet_get_eee(struct net_device *dev, struct ethtool_eee *e)
783 {
784 struct bcmgenet_priv *priv = netdev_priv(dev);
785 struct ethtool_eee *p = &priv->eee;
786
787 if (GENET_IS_V1(priv))
788 return -EOPNOTSUPP;
789
790 e->eee_enabled = p->eee_enabled;
791 e->eee_active = p->eee_active;
792 e->tx_lpi_timer = bcmgenet_umac_readl(priv, UMAC_EEE_LPI_TIMER);
793
794 return phy_ethtool_get_eee(priv->phydev, e);
795 }
796
797 static int bcmgenet_set_eee(struct net_device *dev, struct ethtool_eee *e)
798 {
799 struct bcmgenet_priv *priv = netdev_priv(dev);
800 struct ethtool_eee *p = &priv->eee;
801 int ret = 0;
802
803 if (GENET_IS_V1(priv))
804 return -EOPNOTSUPP;
805
806 p->eee_enabled = e->eee_enabled;
807
808 if (!p->eee_enabled) {
809 bcmgenet_eee_enable_set(dev, false);
810 } else {
811 ret = phy_init_eee(priv->phydev, 0);
812 if (ret) {
813 netif_err(priv, hw, dev, "EEE initialization failed\n");
814 return ret;
815 }
816
817 bcmgenet_umac_writel(priv, e->tx_lpi_timer, UMAC_EEE_LPI_TIMER);
818 bcmgenet_eee_enable_set(dev, true);
819 }
820
821 return phy_ethtool_set_eee(priv->phydev, e);
822 }
823
824 static int bcmgenet_nway_reset(struct net_device *dev)
825 {
826 struct bcmgenet_priv *priv = netdev_priv(dev);
827
828 return genphy_restart_aneg(priv->phydev);
829 }
830
831 /* standard ethtool support functions. */
832 static struct ethtool_ops bcmgenet_ethtool_ops = {
833 .get_strings = bcmgenet_get_strings,
834 .get_sset_count = bcmgenet_get_sset_count,
835 .get_ethtool_stats = bcmgenet_get_ethtool_stats,
836 .get_settings = bcmgenet_get_settings,
837 .set_settings = bcmgenet_set_settings,
838 .get_drvinfo = bcmgenet_get_drvinfo,
839 .get_link = ethtool_op_get_link,
840 .get_msglevel = bcmgenet_get_msglevel,
841 .set_msglevel = bcmgenet_set_msglevel,
842 .get_wol = bcmgenet_get_wol,
843 .set_wol = bcmgenet_set_wol,
844 .get_eee = bcmgenet_get_eee,
845 .set_eee = bcmgenet_set_eee,
846 .nway_reset = bcmgenet_nway_reset,
847 };
848
849 /* Power down the unimac, based on mode. */
850 static int bcmgenet_power_down(struct bcmgenet_priv *priv,
851 enum bcmgenet_power_mode mode)
852 {
853 int ret = 0;
854 u32 reg;
855
856 switch (mode) {
857 case GENET_POWER_CABLE_SENSE:
858 phy_detach(priv->phydev);
859 break;
860
861 case GENET_POWER_WOL_MAGIC:
862 ret = bcmgenet_wol_power_down_cfg(priv, mode);
863 break;
864
865 case GENET_POWER_PASSIVE:
866 /* Power down LED */
867 if (priv->hw_params->flags & GENET_HAS_EXT) {
868 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
869 reg |= (EXT_PWR_DOWN_PHY |
870 EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_BIAS);
871 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
872
873 bcmgenet_phy_power_set(priv->dev, false);
874 }
875 break;
876 default:
877 break;
878 }
879
880 return 0;
881 }
882
883 static void bcmgenet_power_up(struct bcmgenet_priv *priv,
884 enum bcmgenet_power_mode mode)
885 {
886 u32 reg;
887
888 if (!(priv->hw_params->flags & GENET_HAS_EXT))
889 return;
890
891 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
892
893 switch (mode) {
894 case GENET_POWER_PASSIVE:
895 reg &= ~(EXT_PWR_DOWN_DLL | EXT_PWR_DOWN_PHY |
896 EXT_PWR_DOWN_BIAS);
897 /* fallthrough */
898 case GENET_POWER_CABLE_SENSE:
899 /* enable APD */
900 reg |= EXT_PWR_DN_EN_LD;
901 break;
902 case GENET_POWER_WOL_MAGIC:
903 bcmgenet_wol_power_up_cfg(priv, mode);
904 return;
905 default:
906 break;
907 }
908
909 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
910 if (mode == GENET_POWER_PASSIVE) {
911 bcmgenet_phy_power_set(priv->dev, true);
912 bcmgenet_mii_reset(priv->dev);
913 }
914 }
915
916 /* ioctl handle special commands that are not present in ethtool. */
917 static int bcmgenet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
918 {
919 struct bcmgenet_priv *priv = netdev_priv(dev);
920 int val = 0;
921
922 if (!netif_running(dev))
923 return -EINVAL;
924
925 switch (cmd) {
926 case SIOCGMIIPHY:
927 case SIOCGMIIREG:
928 case SIOCSMIIREG:
929 if (!priv->phydev)
930 val = -ENODEV;
931 else
932 val = phy_mii_ioctl(priv->phydev, rq, cmd);
933 break;
934
935 default:
936 val = -EINVAL;
937 break;
938 }
939
940 return val;
941 }
942
943 static struct enet_cb *bcmgenet_get_txcb(struct bcmgenet_priv *priv,
944 struct bcmgenet_tx_ring *ring)
945 {
946 struct enet_cb *tx_cb_ptr;
947
948 tx_cb_ptr = ring->cbs;
949 tx_cb_ptr += ring->write_ptr - ring->cb_ptr;
950
951 /* Advancing local write pointer */
952 if (ring->write_ptr == ring->end_ptr)
953 ring->write_ptr = ring->cb_ptr;
954 else
955 ring->write_ptr++;
956
957 return tx_cb_ptr;
958 }
959
960 /* Simple helper to free a control block's resources */
961 static void bcmgenet_free_cb(struct enet_cb *cb)
962 {
963 dev_kfree_skb_any(cb->skb);
964 cb->skb = NULL;
965 dma_unmap_addr_set(cb, dma_addr, 0);
966 }
967
968 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring *ring)
969 {
970 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
971 INTRL2_CPU_MASK_SET);
972 }
973
974 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring *ring)
975 {
976 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_RXDMA_DONE,
977 INTRL2_CPU_MASK_CLEAR);
978 }
979
980 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring *ring)
981 {
982 bcmgenet_intrl2_1_writel(ring->priv,
983 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
984 INTRL2_CPU_MASK_SET);
985 }
986
987 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring *ring)
988 {
989 bcmgenet_intrl2_1_writel(ring->priv,
990 1 << (UMAC_IRQ1_RX_INTR_SHIFT + ring->index),
991 INTRL2_CPU_MASK_CLEAR);
992 }
993
994 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring *ring)
995 {
996 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
997 INTRL2_CPU_MASK_SET);
998 }
999
1000 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring *ring)
1001 {
1002 bcmgenet_intrl2_0_writel(ring->priv, UMAC_IRQ_TXDMA_DONE,
1003 INTRL2_CPU_MASK_CLEAR);
1004 }
1005
1006 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring *ring)
1007 {
1008 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1009 INTRL2_CPU_MASK_CLEAR);
1010 }
1011
1012 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring *ring)
1013 {
1014 bcmgenet_intrl2_1_writel(ring->priv, 1 << ring->index,
1015 INTRL2_CPU_MASK_SET);
1016 }
1017
1018 /* Unlocked version of the reclaim routine */
1019 static unsigned int __bcmgenet_tx_reclaim(struct net_device *dev,
1020 struct bcmgenet_tx_ring *ring)
1021 {
1022 struct bcmgenet_priv *priv = netdev_priv(dev);
1023 struct enet_cb *tx_cb_ptr;
1024 struct netdev_queue *txq;
1025 unsigned int pkts_compl = 0;
1026 unsigned int c_index;
1027 unsigned int txbds_ready;
1028 unsigned int txbds_processed = 0;
1029
1030 /* Compute how many buffers are transmitted since last xmit call */
1031 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
1032 c_index &= DMA_C_INDEX_MASK;
1033
1034 if (likely(c_index >= ring->c_index))
1035 txbds_ready = c_index - ring->c_index;
1036 else
1037 txbds_ready = (DMA_C_INDEX_MASK + 1) - ring->c_index + c_index;
1038
1039 netif_dbg(priv, tx_done, dev,
1040 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1041 __func__, ring->index, ring->c_index, c_index, txbds_ready);
1042
1043 /* Reclaim transmitted buffers */
1044 while (txbds_processed < txbds_ready) {
1045 tx_cb_ptr = &priv->tx_cbs[ring->clean_ptr];
1046 if (tx_cb_ptr->skb) {
1047 pkts_compl++;
1048 dev->stats.tx_packets++;
1049 dev->stats.tx_bytes += tx_cb_ptr->skb->len;
1050 dma_unmap_single(&dev->dev,
1051 dma_unmap_addr(tx_cb_ptr, dma_addr),
1052 tx_cb_ptr->skb->len,
1053 DMA_TO_DEVICE);
1054 bcmgenet_free_cb(tx_cb_ptr);
1055 } else if (dma_unmap_addr(tx_cb_ptr, dma_addr)) {
1056 dev->stats.tx_bytes +=
1057 dma_unmap_len(tx_cb_ptr, dma_len);
1058 dma_unmap_page(&dev->dev,
1059 dma_unmap_addr(tx_cb_ptr, dma_addr),
1060 dma_unmap_len(tx_cb_ptr, dma_len),
1061 DMA_TO_DEVICE);
1062 dma_unmap_addr_set(tx_cb_ptr, dma_addr, 0);
1063 }
1064
1065 txbds_processed++;
1066 if (likely(ring->clean_ptr < ring->end_ptr))
1067 ring->clean_ptr++;
1068 else
1069 ring->clean_ptr = ring->cb_ptr;
1070 }
1071
1072 ring->free_bds += txbds_processed;
1073 ring->c_index = (ring->c_index + txbds_processed) & DMA_C_INDEX_MASK;
1074
1075 if (ring->free_bds > (MAX_SKB_FRAGS + 1)) {
1076 txq = netdev_get_tx_queue(dev, ring->queue);
1077 if (netif_tx_queue_stopped(txq))
1078 netif_tx_wake_queue(txq);
1079 }
1080
1081 return pkts_compl;
1082 }
1083
1084 static unsigned int bcmgenet_tx_reclaim(struct net_device *dev,
1085 struct bcmgenet_tx_ring *ring)
1086 {
1087 unsigned int released;
1088 unsigned long flags;
1089
1090 spin_lock_irqsave(&ring->lock, flags);
1091 released = __bcmgenet_tx_reclaim(dev, ring);
1092 spin_unlock_irqrestore(&ring->lock, flags);
1093
1094 return released;
1095 }
1096
1097 static int bcmgenet_tx_poll(struct napi_struct *napi, int budget)
1098 {
1099 struct bcmgenet_tx_ring *ring =
1100 container_of(napi, struct bcmgenet_tx_ring, napi);
1101 unsigned int work_done = 0;
1102
1103 work_done = bcmgenet_tx_reclaim(ring->priv->dev, ring);
1104
1105 if (work_done == 0) {
1106 napi_complete(napi);
1107 ring->int_enable(ring);
1108
1109 return 0;
1110 }
1111
1112 return budget;
1113 }
1114
1115 static void bcmgenet_tx_reclaim_all(struct net_device *dev)
1116 {
1117 struct bcmgenet_priv *priv = netdev_priv(dev);
1118 int i;
1119
1120 if (netif_is_multiqueue(dev)) {
1121 for (i = 0; i < priv->hw_params->tx_queues; i++)
1122 bcmgenet_tx_reclaim(dev, &priv->tx_rings[i]);
1123 }
1124
1125 bcmgenet_tx_reclaim(dev, &priv->tx_rings[DESC_INDEX]);
1126 }
1127
1128 /* Transmits a single SKB (either head of a fragment or a single SKB)
1129 * caller must hold priv->lock
1130 */
1131 static int bcmgenet_xmit_single(struct net_device *dev,
1132 struct sk_buff *skb,
1133 u16 dma_desc_flags,
1134 struct bcmgenet_tx_ring *ring)
1135 {
1136 struct bcmgenet_priv *priv = netdev_priv(dev);
1137 struct device *kdev = &priv->pdev->dev;
1138 struct enet_cb *tx_cb_ptr;
1139 unsigned int skb_len;
1140 dma_addr_t mapping;
1141 u32 length_status;
1142 int ret;
1143
1144 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1145
1146 if (unlikely(!tx_cb_ptr))
1147 BUG();
1148
1149 tx_cb_ptr->skb = skb;
1150
1151 skb_len = skb_headlen(skb) < ETH_ZLEN ? ETH_ZLEN : skb_headlen(skb);
1152
1153 mapping = dma_map_single(kdev, skb->data, skb_len, DMA_TO_DEVICE);
1154 ret = dma_mapping_error(kdev, mapping);
1155 if (ret) {
1156 priv->mib.tx_dma_failed++;
1157 netif_err(priv, tx_err, dev, "Tx DMA map failed\n");
1158 dev_kfree_skb(skb);
1159 return ret;
1160 }
1161
1162 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1163 dma_unmap_len_set(tx_cb_ptr, dma_len, skb->len);
1164 length_status = (skb_len << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1165 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT) |
1166 DMA_TX_APPEND_CRC;
1167
1168 if (skb->ip_summed == CHECKSUM_PARTIAL)
1169 length_status |= DMA_TX_DO_CSUM;
1170
1171 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping, length_status);
1172
1173 return 0;
1174 }
1175
1176 /* Transmit a SKB fragment */
1177 static int bcmgenet_xmit_frag(struct net_device *dev,
1178 skb_frag_t *frag,
1179 u16 dma_desc_flags,
1180 struct bcmgenet_tx_ring *ring)
1181 {
1182 struct bcmgenet_priv *priv = netdev_priv(dev);
1183 struct device *kdev = &priv->pdev->dev;
1184 struct enet_cb *tx_cb_ptr;
1185 dma_addr_t mapping;
1186 int ret;
1187
1188 tx_cb_ptr = bcmgenet_get_txcb(priv, ring);
1189
1190 if (unlikely(!tx_cb_ptr))
1191 BUG();
1192 tx_cb_ptr->skb = NULL;
1193
1194 mapping = skb_frag_dma_map(kdev, frag, 0,
1195 skb_frag_size(frag), DMA_TO_DEVICE);
1196 ret = dma_mapping_error(kdev, mapping);
1197 if (ret) {
1198 priv->mib.tx_dma_failed++;
1199 netif_err(priv, tx_err, dev, "%s: Tx DMA map failed\n",
1200 __func__);
1201 return ret;
1202 }
1203
1204 dma_unmap_addr_set(tx_cb_ptr, dma_addr, mapping);
1205 dma_unmap_len_set(tx_cb_ptr, dma_len, frag->size);
1206
1207 dmadesc_set(priv, tx_cb_ptr->bd_addr, mapping,
1208 (frag->size << DMA_BUFLENGTH_SHIFT) | dma_desc_flags |
1209 (priv->hw_params->qtag_mask << DMA_TX_QTAG_SHIFT));
1210
1211 return 0;
1212 }
1213
1214 /* Reallocate the SKB to put enough headroom in front of it and insert
1215 * the transmit checksum offsets in the descriptors
1216 */
1217 static struct sk_buff *bcmgenet_put_tx_csum(struct net_device *dev,
1218 struct sk_buff *skb)
1219 {
1220 struct status_64 *status = NULL;
1221 struct sk_buff *new_skb;
1222 u16 offset;
1223 u8 ip_proto;
1224 u16 ip_ver;
1225 u32 tx_csum_info;
1226
1227 if (unlikely(skb_headroom(skb) < sizeof(*status))) {
1228 /* If 64 byte status block enabled, must make sure skb has
1229 * enough headroom for us to insert 64B status block.
1230 */
1231 new_skb = skb_realloc_headroom(skb, sizeof(*status));
1232 dev_kfree_skb(skb);
1233 if (!new_skb) {
1234 dev->stats.tx_dropped++;
1235 return NULL;
1236 }
1237 skb = new_skb;
1238 }
1239
1240 skb_push(skb, sizeof(*status));
1241 status = (struct status_64 *)skb->data;
1242
1243 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1244 ip_ver = htons(skb->protocol);
1245 switch (ip_ver) {
1246 case ETH_P_IP:
1247 ip_proto = ip_hdr(skb)->protocol;
1248 break;
1249 case ETH_P_IPV6:
1250 ip_proto = ipv6_hdr(skb)->nexthdr;
1251 break;
1252 default:
1253 return skb;
1254 }
1255
1256 offset = skb_checksum_start_offset(skb) - sizeof(*status);
1257 tx_csum_info = (offset << STATUS_TX_CSUM_START_SHIFT) |
1258 (offset + skb->csum_offset);
1259
1260 /* Set the length valid bit for TCP and UDP and just set
1261 * the special UDP flag for IPv4, else just set to 0.
1262 */
1263 if (ip_proto == IPPROTO_TCP || ip_proto == IPPROTO_UDP) {
1264 tx_csum_info |= STATUS_TX_CSUM_LV;
1265 if (ip_proto == IPPROTO_UDP && ip_ver == ETH_P_IP)
1266 tx_csum_info |= STATUS_TX_CSUM_PROTO_UDP;
1267 } else {
1268 tx_csum_info = 0;
1269 }
1270
1271 status->tx_csum_info = tx_csum_info;
1272 }
1273
1274 return skb;
1275 }
1276
1277 static netdev_tx_t bcmgenet_xmit(struct sk_buff *skb, struct net_device *dev)
1278 {
1279 struct bcmgenet_priv *priv = netdev_priv(dev);
1280 struct bcmgenet_tx_ring *ring = NULL;
1281 struct netdev_queue *txq;
1282 unsigned long flags = 0;
1283 int nr_frags, index;
1284 u16 dma_desc_flags;
1285 int ret;
1286 int i;
1287
1288 index = skb_get_queue_mapping(skb);
1289 /* Mapping strategy:
1290 * queue_mapping = 0, unclassified, packet xmited through ring16
1291 * queue_mapping = 1, goes to ring 0. (highest priority queue
1292 * queue_mapping = 2, goes to ring 1.
1293 * queue_mapping = 3, goes to ring 2.
1294 * queue_mapping = 4, goes to ring 3.
1295 */
1296 if (index == 0)
1297 index = DESC_INDEX;
1298 else
1299 index -= 1;
1300
1301 nr_frags = skb_shinfo(skb)->nr_frags;
1302 ring = &priv->tx_rings[index];
1303 txq = netdev_get_tx_queue(dev, ring->queue);
1304
1305 spin_lock_irqsave(&ring->lock, flags);
1306 if (ring->free_bds <= nr_frags + 1) {
1307 netif_tx_stop_queue(txq);
1308 netdev_err(dev, "%s: tx ring %d full when queue %d awake\n",
1309 __func__, index, ring->queue);
1310 ret = NETDEV_TX_BUSY;
1311 goto out;
1312 }
1313
1314 if (skb_padto(skb, ETH_ZLEN)) {
1315 ret = NETDEV_TX_OK;
1316 goto out;
1317 }
1318
1319 /* set the SKB transmit checksum */
1320 if (priv->desc_64b_en) {
1321 skb = bcmgenet_put_tx_csum(dev, skb);
1322 if (!skb) {
1323 ret = NETDEV_TX_OK;
1324 goto out;
1325 }
1326 }
1327
1328 dma_desc_flags = DMA_SOP;
1329 if (nr_frags == 0)
1330 dma_desc_flags |= DMA_EOP;
1331
1332 /* Transmit single SKB or head of fragment list */
1333 ret = bcmgenet_xmit_single(dev, skb, dma_desc_flags, ring);
1334 if (ret) {
1335 ret = NETDEV_TX_OK;
1336 goto out;
1337 }
1338
1339 /* xmit fragment */
1340 for (i = 0; i < nr_frags; i++) {
1341 ret = bcmgenet_xmit_frag(dev,
1342 &skb_shinfo(skb)->frags[i],
1343 (i == nr_frags - 1) ? DMA_EOP : 0,
1344 ring);
1345 if (ret) {
1346 ret = NETDEV_TX_OK;
1347 goto out;
1348 }
1349 }
1350
1351 skb_tx_timestamp(skb);
1352
1353 /* Decrement total BD count and advance our write pointer */
1354 ring->free_bds -= nr_frags + 1;
1355 ring->prod_index += nr_frags + 1;
1356 ring->prod_index &= DMA_P_INDEX_MASK;
1357
1358 if (ring->free_bds <= (MAX_SKB_FRAGS + 1))
1359 netif_tx_stop_queue(txq);
1360
1361 if (!skb->xmit_more || netif_xmit_stopped(txq))
1362 /* Packets are ready, update producer index */
1363 bcmgenet_tdma_ring_writel(priv, ring->index,
1364 ring->prod_index, TDMA_PROD_INDEX);
1365 out:
1366 spin_unlock_irqrestore(&ring->lock, flags);
1367
1368 return ret;
1369 }
1370
1371 static struct sk_buff *bcmgenet_rx_refill(struct bcmgenet_priv *priv,
1372 struct enet_cb *cb)
1373 {
1374 struct device *kdev = &priv->pdev->dev;
1375 struct sk_buff *skb;
1376 struct sk_buff *rx_skb;
1377 dma_addr_t mapping;
1378
1379 /* Allocate a new Rx skb */
1380 skb = netdev_alloc_skb(priv->dev, priv->rx_buf_len + SKB_ALIGNMENT);
1381 if (!skb) {
1382 priv->mib.alloc_rx_buff_failed++;
1383 netif_err(priv, rx_err, priv->dev,
1384 "%s: Rx skb allocation failed\n", __func__);
1385 return NULL;
1386 }
1387
1388 /* DMA-map the new Rx skb */
1389 mapping = dma_map_single(kdev, skb->data, priv->rx_buf_len,
1390 DMA_FROM_DEVICE);
1391 if (dma_mapping_error(kdev, mapping)) {
1392 priv->mib.rx_dma_failed++;
1393 dev_kfree_skb_any(skb);
1394 netif_err(priv, rx_err, priv->dev,
1395 "%s: Rx skb DMA mapping failed\n", __func__);
1396 return NULL;
1397 }
1398
1399 /* Grab the current Rx skb from the ring and DMA-unmap it */
1400 rx_skb = cb->skb;
1401 if (likely(rx_skb))
1402 dma_unmap_single(kdev, dma_unmap_addr(cb, dma_addr),
1403 priv->rx_buf_len, DMA_FROM_DEVICE);
1404
1405 /* Put the new Rx skb on the ring */
1406 cb->skb = skb;
1407 dma_unmap_addr_set(cb, dma_addr, mapping);
1408 dmadesc_set_addr(priv, cb->bd_addr, mapping);
1409
1410 /* Return the current Rx skb to caller */
1411 return rx_skb;
1412 }
1413
1414 /* bcmgenet_desc_rx - descriptor based rx process.
1415 * this could be called from bottom half, or from NAPI polling method.
1416 */
1417 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring *ring,
1418 unsigned int budget)
1419 {
1420 struct bcmgenet_priv *priv = ring->priv;
1421 struct net_device *dev = priv->dev;
1422 struct enet_cb *cb;
1423 struct sk_buff *skb;
1424 u32 dma_length_status;
1425 unsigned long dma_flag;
1426 int len;
1427 unsigned int rxpktprocessed = 0, rxpkttoprocess;
1428 unsigned int p_index;
1429 unsigned int discards;
1430 unsigned int chksum_ok = 0;
1431
1432 p_index = bcmgenet_rdma_ring_readl(priv, ring->index, RDMA_PROD_INDEX);
1433
1434 discards = (p_index >> DMA_P_INDEX_DISCARD_CNT_SHIFT) &
1435 DMA_P_INDEX_DISCARD_CNT_MASK;
1436 if (discards > ring->old_discards) {
1437 discards = discards - ring->old_discards;
1438 dev->stats.rx_missed_errors += discards;
1439 dev->stats.rx_errors += discards;
1440 ring->old_discards += discards;
1441
1442 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1443 if (ring->old_discards >= 0xC000) {
1444 ring->old_discards = 0;
1445 bcmgenet_rdma_ring_writel(priv, ring->index, 0,
1446 RDMA_PROD_INDEX);
1447 }
1448 }
1449
1450 p_index &= DMA_P_INDEX_MASK;
1451
1452 if (likely(p_index >= ring->c_index))
1453 rxpkttoprocess = p_index - ring->c_index;
1454 else
1455 rxpkttoprocess = (DMA_C_INDEX_MASK + 1) - ring->c_index +
1456 p_index;
1457
1458 netif_dbg(priv, rx_status, dev,
1459 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess);
1460
1461 while ((rxpktprocessed < rxpkttoprocess) &&
1462 (rxpktprocessed < budget)) {
1463 cb = &priv->rx_cbs[ring->read_ptr];
1464 skb = bcmgenet_rx_refill(priv, cb);
1465
1466 if (unlikely(!skb)) {
1467 dev->stats.rx_dropped++;
1468 goto next;
1469 }
1470
1471 if (!priv->desc_64b_en) {
1472 dma_length_status =
1473 dmadesc_get_length_status(priv, cb->bd_addr);
1474 } else {
1475 struct status_64 *status;
1476
1477 status = (struct status_64 *)skb->data;
1478 dma_length_status = status->length_status;
1479 }
1480
1481 /* DMA flags and length are still valid no matter how
1482 * we got the Receive Status Vector (64B RSB or register)
1483 */
1484 dma_flag = dma_length_status & 0xffff;
1485 len = dma_length_status >> DMA_BUFLENGTH_SHIFT;
1486
1487 netif_dbg(priv, rx_status, dev,
1488 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1489 __func__, p_index, ring->c_index,
1490 ring->read_ptr, dma_length_status);
1491
1492 if (unlikely(!(dma_flag & DMA_EOP) || !(dma_flag & DMA_SOP))) {
1493 netif_err(priv, rx_status, dev,
1494 "dropping fragmented packet!\n");
1495 dev->stats.rx_errors++;
1496 dev_kfree_skb_any(skb);
1497 goto next;
1498 }
1499
1500 /* report errors */
1501 if (unlikely(dma_flag & (DMA_RX_CRC_ERROR |
1502 DMA_RX_OV |
1503 DMA_RX_NO |
1504 DMA_RX_LG |
1505 DMA_RX_RXER))) {
1506 netif_err(priv, rx_status, dev, "dma_flag=0x%x\n",
1507 (unsigned int)dma_flag);
1508 if (dma_flag & DMA_RX_CRC_ERROR)
1509 dev->stats.rx_crc_errors++;
1510 if (dma_flag & DMA_RX_OV)
1511 dev->stats.rx_over_errors++;
1512 if (dma_flag & DMA_RX_NO)
1513 dev->stats.rx_frame_errors++;
1514 if (dma_flag & DMA_RX_LG)
1515 dev->stats.rx_length_errors++;
1516 dev->stats.rx_errors++;
1517 dev_kfree_skb_any(skb);
1518 goto next;
1519 } /* error packet */
1520
1521 chksum_ok = (dma_flag & priv->dma_rx_chk_bit) &&
1522 priv->desc_rxchk_en;
1523
1524 skb_put(skb, len);
1525 if (priv->desc_64b_en) {
1526 skb_pull(skb, 64);
1527 len -= 64;
1528 }
1529
1530 if (likely(chksum_ok))
1531 skb->ip_summed = CHECKSUM_UNNECESSARY;
1532
1533 /* remove hardware 2bytes added for IP alignment */
1534 skb_pull(skb, 2);
1535 len -= 2;
1536
1537 if (priv->crc_fwd_en) {
1538 skb_trim(skb, len - ETH_FCS_LEN);
1539 len -= ETH_FCS_LEN;
1540 }
1541
1542 /*Finish setting up the received SKB and send it to the kernel*/
1543 skb->protocol = eth_type_trans(skb, priv->dev);
1544 dev->stats.rx_packets++;
1545 dev->stats.rx_bytes += len;
1546 if (dma_flag & DMA_RX_MULT)
1547 dev->stats.multicast++;
1548
1549 /* Notify kernel */
1550 napi_gro_receive(&ring->napi, skb);
1551 netif_dbg(priv, rx_status, dev, "pushed up to kernel\n");
1552
1553 next:
1554 rxpktprocessed++;
1555 if (likely(ring->read_ptr < ring->end_ptr))
1556 ring->read_ptr++;
1557 else
1558 ring->read_ptr = ring->cb_ptr;
1559
1560 ring->c_index = (ring->c_index + 1) & DMA_C_INDEX_MASK;
1561 bcmgenet_rdma_ring_writel(priv, ring->index, ring->c_index, RDMA_CONS_INDEX);
1562 }
1563
1564 return rxpktprocessed;
1565 }
1566
1567 /* Rx NAPI polling method */
1568 static int bcmgenet_rx_poll(struct napi_struct *napi, int budget)
1569 {
1570 struct bcmgenet_rx_ring *ring = container_of(napi,
1571 struct bcmgenet_rx_ring, napi);
1572 unsigned int work_done;
1573
1574 work_done = bcmgenet_desc_rx(ring, budget);
1575
1576 if (work_done < budget) {
1577 napi_complete(napi);
1578 ring->int_enable(ring);
1579 }
1580
1581 return work_done;
1582 }
1583
1584 /* Assign skb to RX DMA descriptor. */
1585 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv *priv,
1586 struct bcmgenet_rx_ring *ring)
1587 {
1588 struct enet_cb *cb;
1589 struct sk_buff *skb;
1590 int i;
1591
1592 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
1593
1594 /* loop here for each buffer needing assign */
1595 for (i = 0; i < ring->size; i++) {
1596 cb = ring->cbs + i;
1597 skb = bcmgenet_rx_refill(priv, cb);
1598 if (skb)
1599 dev_kfree_skb_any(skb);
1600 if (!cb->skb)
1601 return -ENOMEM;
1602 }
1603
1604 return 0;
1605 }
1606
1607 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv *priv)
1608 {
1609 struct enet_cb *cb;
1610 int i;
1611
1612 for (i = 0; i < priv->num_rx_bds; i++) {
1613 cb = &priv->rx_cbs[i];
1614
1615 if (dma_unmap_addr(cb, dma_addr)) {
1616 dma_unmap_single(&priv->dev->dev,
1617 dma_unmap_addr(cb, dma_addr),
1618 priv->rx_buf_len, DMA_FROM_DEVICE);
1619 dma_unmap_addr_set(cb, dma_addr, 0);
1620 }
1621
1622 if (cb->skb)
1623 bcmgenet_free_cb(cb);
1624 }
1625 }
1626
1627 static void umac_enable_set(struct bcmgenet_priv *priv, u32 mask, bool enable)
1628 {
1629 u32 reg;
1630
1631 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1632 if (enable)
1633 reg |= mask;
1634 else
1635 reg &= ~mask;
1636 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
1637
1638 /* UniMAC stops on a packet boundary, wait for a full-size packet
1639 * to be processed
1640 */
1641 if (enable == 0)
1642 usleep_range(1000, 2000);
1643 }
1644
1645 static int reset_umac(struct bcmgenet_priv *priv)
1646 {
1647 struct device *kdev = &priv->pdev->dev;
1648 unsigned int timeout = 0;
1649 u32 reg;
1650
1651 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1652 bcmgenet_rbuf_ctrl_set(priv, 0);
1653 udelay(10);
1654
1655 /* disable MAC while updating its registers */
1656 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1657
1658 /* issue soft reset, wait for it to complete */
1659 bcmgenet_umac_writel(priv, CMD_SW_RESET, UMAC_CMD);
1660 while (timeout++ < 1000) {
1661 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
1662 if (!(reg & CMD_SW_RESET))
1663 return 0;
1664
1665 udelay(1);
1666 }
1667
1668 if (timeout == 1000) {
1669 dev_err(kdev,
1670 "timeout waiting for MAC to come out of reset\n");
1671 return -ETIMEDOUT;
1672 }
1673
1674 return 0;
1675 }
1676
1677 static void bcmgenet_intr_disable(struct bcmgenet_priv *priv)
1678 {
1679 /* Mask all interrupts.*/
1680 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1681 bcmgenet_intrl2_0_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1682 bcmgenet_intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1683 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_MASK_SET);
1684 bcmgenet_intrl2_1_writel(priv, 0xFFFFFFFF, INTRL2_CPU_CLEAR);
1685 bcmgenet_intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
1686 }
1687
1688 static void bcmgenet_link_intr_enable(struct bcmgenet_priv *priv)
1689 {
1690 u32 int0_enable = 0;
1691
1692 /* Monitor cable plug/unplugged event for internal PHY, external PHY
1693 * and MoCA PHY
1694 */
1695 if (priv->internal_phy) {
1696 int0_enable |= UMAC_IRQ_LINK_EVENT;
1697 } else if (priv->ext_phy) {
1698 int0_enable |= UMAC_IRQ_LINK_EVENT;
1699 } else if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1700 if (priv->hw_params->flags & GENET_HAS_MOCA_LINK_DET)
1701 int0_enable |= UMAC_IRQ_LINK_EVENT;
1702 }
1703 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1704 }
1705
1706 static int init_umac(struct bcmgenet_priv *priv)
1707 {
1708 struct device *kdev = &priv->pdev->dev;
1709 int ret;
1710 u32 reg;
1711 u32 int0_enable = 0;
1712 u32 int1_enable = 0;
1713 int i;
1714
1715 dev_dbg(&priv->pdev->dev, "bcmgenet: init_umac\n");
1716
1717 ret = reset_umac(priv);
1718 if (ret)
1719 return ret;
1720
1721 bcmgenet_umac_writel(priv, 0, UMAC_CMD);
1722 /* clear tx/rx counter */
1723 bcmgenet_umac_writel(priv,
1724 MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
1725 UMAC_MIB_CTRL);
1726 bcmgenet_umac_writel(priv, 0, UMAC_MIB_CTRL);
1727
1728 bcmgenet_umac_writel(priv, ENET_MAX_MTU_SIZE, UMAC_MAX_FRAME_LEN);
1729
1730 /* init rx registers, enable ip header optimization */
1731 reg = bcmgenet_rbuf_readl(priv, RBUF_CTRL);
1732 reg |= RBUF_ALIGN_2B;
1733 bcmgenet_rbuf_writel(priv, reg, RBUF_CTRL);
1734
1735 if (!GENET_IS_V1(priv) && !GENET_IS_V2(priv))
1736 bcmgenet_rbuf_writel(priv, 1, RBUF_TBUF_SIZE_CTRL);
1737
1738 bcmgenet_intr_disable(priv);
1739
1740 /* Enable Rx default queue 16 interrupts */
1741 int0_enable |= UMAC_IRQ_RXDMA_DONE;
1742
1743 /* Enable Tx default queue 16 interrupts */
1744 int0_enable |= UMAC_IRQ_TXDMA_DONE;
1745
1746 /* Configure backpressure vectors for MoCA */
1747 if (priv->phy_interface == PHY_INTERFACE_MODE_MOCA) {
1748 reg = bcmgenet_bp_mc_get(priv);
1749 reg |= BIT(priv->hw_params->bp_in_en_shift);
1750
1751 /* bp_mask: back pressure mask */
1752 if (netif_is_multiqueue(priv->dev))
1753 reg |= priv->hw_params->bp_in_mask;
1754 else
1755 reg &= ~priv->hw_params->bp_in_mask;
1756 bcmgenet_bp_mc_set(priv, reg);
1757 }
1758
1759 /* Enable MDIO interrupts on GENET v3+ */
1760 if (priv->hw_params->flags & GENET_HAS_MDIO_INTR)
1761 int0_enable |= (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
1762
1763 /* Enable Rx priority queue interrupts */
1764 for (i = 0; i < priv->hw_params->rx_queues; ++i)
1765 int1_enable |= (1 << (UMAC_IRQ1_RX_INTR_SHIFT + i));
1766
1767 /* Enable Tx priority queue interrupts */
1768 for (i = 0; i < priv->hw_params->tx_queues; ++i)
1769 int1_enable |= (1 << i);
1770
1771 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
1772 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
1773
1774 /* Enable rx/tx engine.*/
1775 dev_dbg(kdev, "done init umac\n");
1776
1777 return 0;
1778 }
1779
1780 /* Initialize a Tx ring along with corresponding hardware registers */
1781 static void bcmgenet_init_tx_ring(struct bcmgenet_priv *priv,
1782 unsigned int index, unsigned int size,
1783 unsigned int start_ptr, unsigned int end_ptr)
1784 {
1785 struct bcmgenet_tx_ring *ring = &priv->tx_rings[index];
1786 u32 words_per_bd = WORDS_PER_BD(priv);
1787 u32 flow_period_val = 0;
1788
1789 spin_lock_init(&ring->lock);
1790 ring->priv = priv;
1791 ring->index = index;
1792 if (index == DESC_INDEX) {
1793 ring->queue = 0;
1794 ring->int_enable = bcmgenet_tx_ring16_int_enable;
1795 ring->int_disable = bcmgenet_tx_ring16_int_disable;
1796 } else {
1797 ring->queue = index + 1;
1798 ring->int_enable = bcmgenet_tx_ring_int_enable;
1799 ring->int_disable = bcmgenet_tx_ring_int_disable;
1800 }
1801 ring->cbs = priv->tx_cbs + start_ptr;
1802 ring->size = size;
1803 ring->clean_ptr = start_ptr;
1804 ring->c_index = 0;
1805 ring->free_bds = size;
1806 ring->write_ptr = start_ptr;
1807 ring->cb_ptr = start_ptr;
1808 ring->end_ptr = end_ptr - 1;
1809 ring->prod_index = 0;
1810
1811 /* Set flow period for ring != 16 */
1812 if (index != DESC_INDEX)
1813 flow_period_val = ENET_MAX_MTU_SIZE << 16;
1814
1815 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_PROD_INDEX);
1816 bcmgenet_tdma_ring_writel(priv, index, 0, TDMA_CONS_INDEX);
1817 bcmgenet_tdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1818 /* Disable rate control for now */
1819 bcmgenet_tdma_ring_writel(priv, index, flow_period_val,
1820 TDMA_FLOW_PERIOD);
1821 bcmgenet_tdma_ring_writel(priv, index,
1822 ((size << DMA_RING_SIZE_SHIFT) |
1823 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1824
1825 /* Set start and end address, read and write pointers */
1826 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1827 DMA_START_ADDR);
1828 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1829 TDMA_READ_PTR);
1830 bcmgenet_tdma_ring_writel(priv, index, start_ptr * words_per_bd,
1831 TDMA_WRITE_PTR);
1832 bcmgenet_tdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1833 DMA_END_ADDR);
1834 }
1835
1836 /* Initialize a RDMA ring */
1837 static int bcmgenet_init_rx_ring(struct bcmgenet_priv *priv,
1838 unsigned int index, unsigned int size,
1839 unsigned int start_ptr, unsigned int end_ptr)
1840 {
1841 struct bcmgenet_rx_ring *ring = &priv->rx_rings[index];
1842 u32 words_per_bd = WORDS_PER_BD(priv);
1843 int ret;
1844
1845 ring->priv = priv;
1846 ring->index = index;
1847 if (index == DESC_INDEX) {
1848 ring->int_enable = bcmgenet_rx_ring16_int_enable;
1849 ring->int_disable = bcmgenet_rx_ring16_int_disable;
1850 } else {
1851 ring->int_enable = bcmgenet_rx_ring_int_enable;
1852 ring->int_disable = bcmgenet_rx_ring_int_disable;
1853 }
1854 ring->cbs = priv->rx_cbs + start_ptr;
1855 ring->size = size;
1856 ring->c_index = 0;
1857 ring->read_ptr = start_ptr;
1858 ring->cb_ptr = start_ptr;
1859 ring->end_ptr = end_ptr - 1;
1860
1861 ret = bcmgenet_alloc_rx_buffers(priv, ring);
1862 if (ret)
1863 return ret;
1864
1865 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_PROD_INDEX);
1866 bcmgenet_rdma_ring_writel(priv, index, 0, RDMA_CONS_INDEX);
1867 bcmgenet_rdma_ring_writel(priv, index, 1, DMA_MBUF_DONE_THRESH);
1868 bcmgenet_rdma_ring_writel(priv, index,
1869 ((size << DMA_RING_SIZE_SHIFT) |
1870 RX_BUF_LENGTH), DMA_RING_BUF_SIZE);
1871 bcmgenet_rdma_ring_writel(priv, index,
1872 (DMA_FC_THRESH_LO <<
1873 DMA_XOFF_THRESHOLD_SHIFT) |
1874 DMA_FC_THRESH_HI, RDMA_XON_XOFF_THRESH);
1875
1876 /* Set start and end address, read and write pointers */
1877 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1878 DMA_START_ADDR);
1879 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1880 RDMA_READ_PTR);
1881 bcmgenet_rdma_ring_writel(priv, index, start_ptr * words_per_bd,
1882 RDMA_WRITE_PTR);
1883 bcmgenet_rdma_ring_writel(priv, index, end_ptr * words_per_bd - 1,
1884 DMA_END_ADDR);
1885
1886 return ret;
1887 }
1888
1889 static void bcmgenet_init_tx_napi(struct bcmgenet_priv *priv)
1890 {
1891 unsigned int i;
1892 struct bcmgenet_tx_ring *ring;
1893
1894 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1895 ring = &priv->tx_rings[i];
1896 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1897 }
1898
1899 ring = &priv->tx_rings[DESC_INDEX];
1900 netif_napi_add(priv->dev, &ring->napi, bcmgenet_tx_poll, 64);
1901 }
1902
1903 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv *priv)
1904 {
1905 unsigned int i;
1906 struct bcmgenet_tx_ring *ring;
1907
1908 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1909 ring = &priv->tx_rings[i];
1910 napi_enable(&ring->napi);
1911 }
1912
1913 ring = &priv->tx_rings[DESC_INDEX];
1914 napi_enable(&ring->napi);
1915 }
1916
1917 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv *priv)
1918 {
1919 unsigned int i;
1920 struct bcmgenet_tx_ring *ring;
1921
1922 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1923 ring = &priv->tx_rings[i];
1924 napi_disable(&ring->napi);
1925 }
1926
1927 ring = &priv->tx_rings[DESC_INDEX];
1928 napi_disable(&ring->napi);
1929 }
1930
1931 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv *priv)
1932 {
1933 unsigned int i;
1934 struct bcmgenet_tx_ring *ring;
1935
1936 for (i = 0; i < priv->hw_params->tx_queues; ++i) {
1937 ring = &priv->tx_rings[i];
1938 netif_napi_del(&ring->napi);
1939 }
1940
1941 ring = &priv->tx_rings[DESC_INDEX];
1942 netif_napi_del(&ring->napi);
1943 }
1944
1945 /* Initialize Tx queues
1946 *
1947 * Queues 0-3 are priority-based, each one has 32 descriptors,
1948 * with queue 0 being the highest priority queue.
1949 *
1950 * Queue 16 is the default Tx queue with
1951 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1952 *
1953 * The transmit control block pool is then partitioned as follows:
1954 * - Tx queue 0 uses tx_cbs[0..31]
1955 * - Tx queue 1 uses tx_cbs[32..63]
1956 * - Tx queue 2 uses tx_cbs[64..95]
1957 * - Tx queue 3 uses tx_cbs[96..127]
1958 * - Tx queue 16 uses tx_cbs[128..255]
1959 */
1960 static void bcmgenet_init_tx_queues(struct net_device *dev)
1961 {
1962 struct bcmgenet_priv *priv = netdev_priv(dev);
1963 u32 i, dma_enable;
1964 u32 dma_ctrl, ring_cfg;
1965 u32 dma_priority[3] = {0, 0, 0};
1966
1967 dma_ctrl = bcmgenet_tdma_readl(priv, DMA_CTRL);
1968 dma_enable = dma_ctrl & DMA_EN;
1969 dma_ctrl &= ~DMA_EN;
1970 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
1971
1972 dma_ctrl = 0;
1973 ring_cfg = 0;
1974
1975 /* Enable strict priority arbiter mode */
1976 bcmgenet_tdma_writel(priv, DMA_ARBITER_SP, DMA_ARB_CTRL);
1977
1978 /* Initialize Tx priority queues */
1979 for (i = 0; i < priv->hw_params->tx_queues; i++) {
1980 bcmgenet_init_tx_ring(priv, i, priv->hw_params->tx_bds_per_q,
1981 i * priv->hw_params->tx_bds_per_q,
1982 (i + 1) * priv->hw_params->tx_bds_per_q);
1983 ring_cfg |= (1 << i);
1984 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
1985 dma_priority[DMA_PRIO_REG_INDEX(i)] |=
1986 ((GENET_Q0_PRIORITY + i) << DMA_PRIO_REG_SHIFT(i));
1987 }
1988
1989 /* Initialize Tx default queue 16 */
1990 bcmgenet_init_tx_ring(priv, DESC_INDEX, GENET_Q16_TX_BD_CNT,
1991 priv->hw_params->tx_queues *
1992 priv->hw_params->tx_bds_per_q,
1993 TOTAL_DESC);
1994 ring_cfg |= (1 << DESC_INDEX);
1995 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
1996 dma_priority[DMA_PRIO_REG_INDEX(DESC_INDEX)] |=
1997 ((GENET_Q0_PRIORITY + priv->hw_params->tx_queues) <<
1998 DMA_PRIO_REG_SHIFT(DESC_INDEX));
1999
2000 /* Set Tx queue priorities */
2001 bcmgenet_tdma_writel(priv, dma_priority[0], DMA_PRIORITY_0);
2002 bcmgenet_tdma_writel(priv, dma_priority[1], DMA_PRIORITY_1);
2003 bcmgenet_tdma_writel(priv, dma_priority[2], DMA_PRIORITY_2);
2004
2005 /* Initialize Tx NAPI */
2006 bcmgenet_init_tx_napi(priv);
2007
2008 /* Enable Tx queues */
2009 bcmgenet_tdma_writel(priv, ring_cfg, DMA_RING_CFG);
2010
2011 /* Enable Tx DMA */
2012 if (dma_enable)
2013 dma_ctrl |= DMA_EN;
2014 bcmgenet_tdma_writel(priv, dma_ctrl, DMA_CTRL);
2015 }
2016
2017 static void bcmgenet_init_rx_napi(struct bcmgenet_priv *priv)
2018 {
2019 unsigned int i;
2020 struct bcmgenet_rx_ring *ring;
2021
2022 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2023 ring = &priv->rx_rings[i];
2024 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2025 }
2026
2027 ring = &priv->rx_rings[DESC_INDEX];
2028 netif_napi_add(priv->dev, &ring->napi, bcmgenet_rx_poll, 64);
2029 }
2030
2031 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv *priv)
2032 {
2033 unsigned int i;
2034 struct bcmgenet_rx_ring *ring;
2035
2036 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2037 ring = &priv->rx_rings[i];
2038 napi_enable(&ring->napi);
2039 }
2040
2041 ring = &priv->rx_rings[DESC_INDEX];
2042 napi_enable(&ring->napi);
2043 }
2044
2045 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv *priv)
2046 {
2047 unsigned int i;
2048 struct bcmgenet_rx_ring *ring;
2049
2050 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2051 ring = &priv->rx_rings[i];
2052 napi_disable(&ring->napi);
2053 }
2054
2055 ring = &priv->rx_rings[DESC_INDEX];
2056 napi_disable(&ring->napi);
2057 }
2058
2059 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv *priv)
2060 {
2061 unsigned int i;
2062 struct bcmgenet_rx_ring *ring;
2063
2064 for (i = 0; i < priv->hw_params->rx_queues; ++i) {
2065 ring = &priv->rx_rings[i];
2066 netif_napi_del(&ring->napi);
2067 }
2068
2069 ring = &priv->rx_rings[DESC_INDEX];
2070 netif_napi_del(&ring->napi);
2071 }
2072
2073 /* Initialize Rx queues
2074 *
2075 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2076 * used to direct traffic to these queues.
2077 *
2078 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2079 */
2080 static int bcmgenet_init_rx_queues(struct net_device *dev)
2081 {
2082 struct bcmgenet_priv *priv = netdev_priv(dev);
2083 u32 i;
2084 u32 dma_enable;
2085 u32 dma_ctrl;
2086 u32 ring_cfg;
2087 int ret;
2088
2089 dma_ctrl = bcmgenet_rdma_readl(priv, DMA_CTRL);
2090 dma_enable = dma_ctrl & DMA_EN;
2091 dma_ctrl &= ~DMA_EN;
2092 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2093
2094 dma_ctrl = 0;
2095 ring_cfg = 0;
2096
2097 /* Initialize Rx priority queues */
2098 for (i = 0; i < priv->hw_params->rx_queues; i++) {
2099 ret = bcmgenet_init_rx_ring(priv, i,
2100 priv->hw_params->rx_bds_per_q,
2101 i * priv->hw_params->rx_bds_per_q,
2102 (i + 1) *
2103 priv->hw_params->rx_bds_per_q);
2104 if (ret)
2105 return ret;
2106
2107 ring_cfg |= (1 << i);
2108 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2109 }
2110
2111 /* Initialize Rx default queue 16 */
2112 ret = bcmgenet_init_rx_ring(priv, DESC_INDEX, GENET_Q16_RX_BD_CNT,
2113 priv->hw_params->rx_queues *
2114 priv->hw_params->rx_bds_per_q,
2115 TOTAL_DESC);
2116 if (ret)
2117 return ret;
2118
2119 ring_cfg |= (1 << DESC_INDEX);
2120 dma_ctrl |= (1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT));
2121
2122 /* Initialize Rx NAPI */
2123 bcmgenet_init_rx_napi(priv);
2124
2125 /* Enable rings */
2126 bcmgenet_rdma_writel(priv, ring_cfg, DMA_RING_CFG);
2127
2128 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2129 if (dma_enable)
2130 dma_ctrl |= DMA_EN;
2131 bcmgenet_rdma_writel(priv, dma_ctrl, DMA_CTRL);
2132
2133 return 0;
2134 }
2135
2136 static int bcmgenet_dma_teardown(struct bcmgenet_priv *priv)
2137 {
2138 int ret = 0;
2139 int timeout = 0;
2140 u32 reg;
2141 u32 dma_ctrl;
2142 int i;
2143
2144 /* Disable TDMA to stop add more frames in TX DMA */
2145 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2146 reg &= ~DMA_EN;
2147 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2148
2149 /* Check TDMA status register to confirm TDMA is disabled */
2150 while (timeout++ < DMA_TIMEOUT_VAL) {
2151 reg = bcmgenet_tdma_readl(priv, DMA_STATUS);
2152 if (reg & DMA_DISABLED)
2153 break;
2154
2155 udelay(1);
2156 }
2157
2158 if (timeout == DMA_TIMEOUT_VAL) {
2159 netdev_warn(priv->dev, "Timed out while disabling TX DMA\n");
2160 ret = -ETIMEDOUT;
2161 }
2162
2163 /* Wait 10ms for packet drain in both tx and rx dma */
2164 usleep_range(10000, 20000);
2165
2166 /* Disable RDMA */
2167 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2168 reg &= ~DMA_EN;
2169 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2170
2171 timeout = 0;
2172 /* Check RDMA status register to confirm RDMA is disabled */
2173 while (timeout++ < DMA_TIMEOUT_VAL) {
2174 reg = bcmgenet_rdma_readl(priv, DMA_STATUS);
2175 if (reg & DMA_DISABLED)
2176 break;
2177
2178 udelay(1);
2179 }
2180
2181 if (timeout == DMA_TIMEOUT_VAL) {
2182 netdev_warn(priv->dev, "Timed out while disabling RX DMA\n");
2183 ret = -ETIMEDOUT;
2184 }
2185
2186 dma_ctrl = 0;
2187 for (i = 0; i < priv->hw_params->rx_queues; i++)
2188 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2189 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2190 reg &= ~dma_ctrl;
2191 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2192
2193 dma_ctrl = 0;
2194 for (i = 0; i < priv->hw_params->tx_queues; i++)
2195 dma_ctrl |= (1 << (i + DMA_RING_BUF_EN_SHIFT));
2196 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2197 reg &= ~dma_ctrl;
2198 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2199
2200 return ret;
2201 }
2202
2203 static void bcmgenet_fini_dma(struct bcmgenet_priv *priv)
2204 {
2205 int i;
2206
2207 bcmgenet_fini_rx_napi(priv);
2208 bcmgenet_fini_tx_napi(priv);
2209
2210 /* disable DMA */
2211 bcmgenet_dma_teardown(priv);
2212
2213 for (i = 0; i < priv->num_tx_bds; i++) {
2214 if (priv->tx_cbs[i].skb != NULL) {
2215 dev_kfree_skb(priv->tx_cbs[i].skb);
2216 priv->tx_cbs[i].skb = NULL;
2217 }
2218 }
2219
2220 bcmgenet_free_rx_buffers(priv);
2221 kfree(priv->rx_cbs);
2222 kfree(priv->tx_cbs);
2223 }
2224
2225 /* init_edma: Initialize DMA control register */
2226 static int bcmgenet_init_dma(struct bcmgenet_priv *priv)
2227 {
2228 int ret;
2229 unsigned int i;
2230 struct enet_cb *cb;
2231
2232 netif_dbg(priv, hw, priv->dev, "%s\n", __func__);
2233
2234 /* Initialize common Rx ring structures */
2235 priv->rx_bds = priv->base + priv->hw_params->rdma_offset;
2236 priv->num_rx_bds = TOTAL_DESC;
2237 priv->rx_cbs = kcalloc(priv->num_rx_bds, sizeof(struct enet_cb),
2238 GFP_KERNEL);
2239 if (!priv->rx_cbs)
2240 return -ENOMEM;
2241
2242 for (i = 0; i < priv->num_rx_bds; i++) {
2243 cb = priv->rx_cbs + i;
2244 cb->bd_addr = priv->rx_bds + i * DMA_DESC_SIZE;
2245 }
2246
2247 /* Initialize common TX ring structures */
2248 priv->tx_bds = priv->base + priv->hw_params->tdma_offset;
2249 priv->num_tx_bds = TOTAL_DESC;
2250 priv->tx_cbs = kcalloc(priv->num_tx_bds, sizeof(struct enet_cb),
2251 GFP_KERNEL);
2252 if (!priv->tx_cbs) {
2253 kfree(priv->rx_cbs);
2254 return -ENOMEM;
2255 }
2256
2257 for (i = 0; i < priv->num_tx_bds; i++) {
2258 cb = priv->tx_cbs + i;
2259 cb->bd_addr = priv->tx_bds + i * DMA_DESC_SIZE;
2260 }
2261
2262 /* Init rDma */
2263 bcmgenet_rdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2264
2265 /* Initialize Rx queues */
2266 ret = bcmgenet_init_rx_queues(priv->dev);
2267 if (ret) {
2268 netdev_err(priv->dev, "failed to initialize Rx queues\n");
2269 bcmgenet_free_rx_buffers(priv);
2270 kfree(priv->rx_cbs);
2271 kfree(priv->tx_cbs);
2272 return ret;
2273 }
2274
2275 /* Init tDma */
2276 bcmgenet_tdma_writel(priv, DMA_MAX_BURST_LENGTH, DMA_SCB_BURST_SIZE);
2277
2278 /* Initialize Tx queues */
2279 bcmgenet_init_tx_queues(priv->dev);
2280
2281 return 0;
2282 }
2283
2284 /* Interrupt bottom half */
2285 static void bcmgenet_irq_task(struct work_struct *work)
2286 {
2287 struct bcmgenet_priv *priv = container_of(
2288 work, struct bcmgenet_priv, bcmgenet_irq_work);
2289
2290 netif_dbg(priv, intr, priv->dev, "%s\n", __func__);
2291
2292 if (priv->irq0_stat & UMAC_IRQ_MPD_R) {
2293 priv->irq0_stat &= ~UMAC_IRQ_MPD_R;
2294 netif_dbg(priv, wol, priv->dev,
2295 "magic packet detected, waking up\n");
2296 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
2297 }
2298
2299 /* Link UP/DOWN event */
2300 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2301 (priv->irq0_stat & UMAC_IRQ_LINK_EVENT)) {
2302 phy_mac_interrupt(priv->phydev,
2303 !!(priv->irq0_stat & UMAC_IRQ_LINK_UP));
2304 priv->irq0_stat &= ~UMAC_IRQ_LINK_EVENT;
2305 }
2306 }
2307
2308 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2309 static irqreturn_t bcmgenet_isr1(int irq, void *dev_id)
2310 {
2311 struct bcmgenet_priv *priv = dev_id;
2312 struct bcmgenet_rx_ring *rx_ring;
2313 struct bcmgenet_tx_ring *tx_ring;
2314 unsigned int index;
2315
2316 /* Save irq status for bottom-half processing. */
2317 priv->irq1_stat =
2318 bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_STAT) &
2319 ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2320
2321 /* clear interrupts */
2322 bcmgenet_intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
2323
2324 netif_dbg(priv, intr, priv->dev,
2325 "%s: IRQ=0x%x\n", __func__, priv->irq1_stat);
2326
2327 /* Check Rx priority queue interrupts */
2328 for (index = 0; index < priv->hw_params->rx_queues; index++) {
2329 if (!(priv->irq1_stat & BIT(UMAC_IRQ1_RX_INTR_SHIFT + index)))
2330 continue;
2331
2332 rx_ring = &priv->rx_rings[index];
2333
2334 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2335 rx_ring->int_disable(rx_ring);
2336 __napi_schedule(&rx_ring->napi);
2337 }
2338 }
2339
2340 /* Check Tx priority queue interrupts */
2341 for (index = 0; index < priv->hw_params->tx_queues; index++) {
2342 if (!(priv->irq1_stat & BIT(index)))
2343 continue;
2344
2345 tx_ring = &priv->tx_rings[index];
2346
2347 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2348 tx_ring->int_disable(tx_ring);
2349 __napi_schedule(&tx_ring->napi);
2350 }
2351 }
2352
2353 return IRQ_HANDLED;
2354 }
2355
2356 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2357 static irqreturn_t bcmgenet_isr0(int irq, void *dev_id)
2358 {
2359 struct bcmgenet_priv *priv = dev_id;
2360 struct bcmgenet_rx_ring *rx_ring;
2361 struct bcmgenet_tx_ring *tx_ring;
2362
2363 /* Save irq status for bottom-half processing. */
2364 priv->irq0_stat =
2365 bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_STAT) &
2366 ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2367
2368 /* clear interrupts */
2369 bcmgenet_intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
2370
2371 netif_dbg(priv, intr, priv->dev,
2372 "IRQ=0x%x\n", priv->irq0_stat);
2373
2374 if (priv->irq0_stat & UMAC_IRQ_RXDMA_DONE) {
2375 rx_ring = &priv->rx_rings[DESC_INDEX];
2376
2377 if (likely(napi_schedule_prep(&rx_ring->napi))) {
2378 rx_ring->int_disable(rx_ring);
2379 __napi_schedule(&rx_ring->napi);
2380 }
2381 }
2382
2383 if (priv->irq0_stat & UMAC_IRQ_TXDMA_DONE) {
2384 tx_ring = &priv->tx_rings[DESC_INDEX];
2385
2386 if (likely(napi_schedule_prep(&tx_ring->napi))) {
2387 tx_ring->int_disable(tx_ring);
2388 __napi_schedule(&tx_ring->napi);
2389 }
2390 }
2391
2392 if (priv->irq0_stat & (UMAC_IRQ_PHY_DET_R |
2393 UMAC_IRQ_PHY_DET_F |
2394 UMAC_IRQ_LINK_EVENT |
2395 UMAC_IRQ_HFB_SM |
2396 UMAC_IRQ_HFB_MM |
2397 UMAC_IRQ_MPD_R)) {
2398 /* all other interested interrupts handled in bottom half */
2399 schedule_work(&priv->bcmgenet_irq_work);
2400 }
2401
2402 if ((priv->hw_params->flags & GENET_HAS_MDIO_INTR) &&
2403 priv->irq0_stat & (UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR)) {
2404 priv->irq0_stat &= ~(UMAC_IRQ_MDIO_DONE | UMAC_IRQ_MDIO_ERROR);
2405 wake_up(&priv->wq);
2406 }
2407
2408 return IRQ_HANDLED;
2409 }
2410
2411 static irqreturn_t bcmgenet_wol_isr(int irq, void *dev_id)
2412 {
2413 struct bcmgenet_priv *priv = dev_id;
2414
2415 pm_wakeup_event(&priv->pdev->dev, 0);
2416
2417 return IRQ_HANDLED;
2418 }
2419
2420 #ifdef CONFIG_NET_POLL_CONTROLLER
2421 static void bcmgenet_poll_controller(struct net_device *dev)
2422 {
2423 struct bcmgenet_priv *priv = netdev_priv(dev);
2424
2425 /* Invoke the main RX/TX interrupt handler */
2426 disable_irq(priv->irq0);
2427 bcmgenet_isr0(priv->irq0, priv);
2428 enable_irq(priv->irq0);
2429
2430 /* And the interrupt handler for RX/TX priority queues */
2431 disable_irq(priv->irq1);
2432 bcmgenet_isr1(priv->irq1, priv);
2433 enable_irq(priv->irq1);
2434 }
2435 #endif
2436
2437 static void bcmgenet_umac_reset(struct bcmgenet_priv *priv)
2438 {
2439 u32 reg;
2440
2441 reg = bcmgenet_rbuf_ctrl_get(priv);
2442 reg |= BIT(1);
2443 bcmgenet_rbuf_ctrl_set(priv, reg);
2444 udelay(10);
2445
2446 reg &= ~BIT(1);
2447 bcmgenet_rbuf_ctrl_set(priv, reg);
2448 udelay(10);
2449 }
2450
2451 static void bcmgenet_set_hw_addr(struct bcmgenet_priv *priv,
2452 unsigned char *addr)
2453 {
2454 bcmgenet_umac_writel(priv, (addr[0] << 24) | (addr[1] << 16) |
2455 (addr[2] << 8) | addr[3], UMAC_MAC0);
2456 bcmgenet_umac_writel(priv, (addr[4] << 8) | addr[5], UMAC_MAC1);
2457 }
2458
2459 /* Returns a reusable dma control register value */
2460 static u32 bcmgenet_dma_disable(struct bcmgenet_priv *priv)
2461 {
2462 u32 reg;
2463 u32 dma_ctrl;
2464
2465 /* disable DMA */
2466 dma_ctrl = 1 << (DESC_INDEX + DMA_RING_BUF_EN_SHIFT) | DMA_EN;
2467 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2468 reg &= ~dma_ctrl;
2469 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2470
2471 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2472 reg &= ~dma_ctrl;
2473 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2474
2475 bcmgenet_umac_writel(priv, 1, UMAC_TX_FLUSH);
2476 udelay(10);
2477 bcmgenet_umac_writel(priv, 0, UMAC_TX_FLUSH);
2478
2479 return dma_ctrl;
2480 }
2481
2482 static void bcmgenet_enable_dma(struct bcmgenet_priv *priv, u32 dma_ctrl)
2483 {
2484 u32 reg;
2485
2486 reg = bcmgenet_rdma_readl(priv, DMA_CTRL);
2487 reg |= dma_ctrl;
2488 bcmgenet_rdma_writel(priv, reg, DMA_CTRL);
2489
2490 reg = bcmgenet_tdma_readl(priv, DMA_CTRL);
2491 reg |= dma_ctrl;
2492 bcmgenet_tdma_writel(priv, reg, DMA_CTRL);
2493 }
2494
2495 static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv *priv,
2496 u32 f_index)
2497 {
2498 u32 offset;
2499 u32 reg;
2500
2501 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2502 reg = bcmgenet_hfb_reg_readl(priv, offset);
2503 return !!(reg & (1 << (f_index % 32)));
2504 }
2505
2506 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv *priv, u32 f_index)
2507 {
2508 u32 offset;
2509 u32 reg;
2510
2511 offset = HFB_FLT_ENABLE_V3PLUS + (f_index < 32) * sizeof(u32);
2512 reg = bcmgenet_hfb_reg_readl(priv, offset);
2513 reg |= (1 << (f_index % 32));
2514 bcmgenet_hfb_reg_writel(priv, reg, offset);
2515 }
2516
2517 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv *priv,
2518 u32 f_index, u32 rx_queue)
2519 {
2520 u32 offset;
2521 u32 reg;
2522
2523 offset = f_index / 8;
2524 reg = bcmgenet_rdma_readl(priv, DMA_INDEX2RING_0 + offset);
2525 reg &= ~(0xF << (4 * (f_index % 8)));
2526 reg |= ((rx_queue & 0xF) << (4 * (f_index % 8)));
2527 bcmgenet_rdma_writel(priv, reg, DMA_INDEX2RING_0 + offset);
2528 }
2529
2530 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv *priv,
2531 u32 f_index, u32 f_length)
2532 {
2533 u32 offset;
2534 u32 reg;
2535
2536 offset = HFB_FLT_LEN_V3PLUS +
2537 ((priv->hw_params->hfb_filter_cnt - 1 - f_index) / 4) *
2538 sizeof(u32);
2539 reg = bcmgenet_hfb_reg_readl(priv, offset);
2540 reg &= ~(0xFF << (8 * (f_index % 4)));
2541 reg |= ((f_length & 0xFF) << (8 * (f_index % 4)));
2542 bcmgenet_hfb_reg_writel(priv, reg, offset);
2543 }
2544
2545 static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv *priv)
2546 {
2547 u32 f_index;
2548
2549 for (f_index = 0; f_index < priv->hw_params->hfb_filter_cnt; f_index++)
2550 if (!bcmgenet_hfb_is_filter_enabled(priv, f_index))
2551 return f_index;
2552
2553 return -ENOMEM;
2554 }
2555
2556 /* bcmgenet_hfb_add_filter
2557 *
2558 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2559 * desired Rx queue.
2560 *
2561 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2562 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2563 *
2564 * bits 31:20 - unused
2565 * bit 19 - nibble 0 match enable
2566 * bit 18 - nibble 1 match enable
2567 * bit 17 - nibble 2 match enable
2568 * bit 16 - nibble 3 match enable
2569 * bits 15:12 - nibble 0 data
2570 * bits 11:8 - nibble 1 data
2571 * bits 7:4 - nibble 2 data
2572 * bits 3:0 - nibble 3 data
2573 *
2574 * Example:
2575 * In order to match:
2576 * - Ethernet frame type = 0x0800 (IP)
2577 * - IP version field = 4
2578 * - IP protocol field = 0x11 (UDP)
2579 *
2580 * The following filter is needed:
2581 * u32 hfb_filter_ipv4_udp[] = {
2582 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2583 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2584 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2585 * };
2586 *
2587 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2588 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2589 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2590 */
2591 int bcmgenet_hfb_add_filter(struct bcmgenet_priv *priv, u32 *f_data,
2592 u32 f_length, u32 rx_queue)
2593 {
2594 int f_index;
2595 u32 i;
2596
2597 f_index = bcmgenet_hfb_find_unused_filter(priv);
2598 if (f_index < 0)
2599 return -ENOMEM;
2600
2601 if (f_length > priv->hw_params->hfb_filter_size)
2602 return -EINVAL;
2603
2604 for (i = 0; i < f_length; i++)
2605 bcmgenet_hfb_writel(priv, f_data[i],
2606 (f_index * priv->hw_params->hfb_filter_size + i) *
2607 sizeof(u32));
2608
2609 bcmgenet_hfb_set_filter_length(priv, f_index, 2 * f_length);
2610 bcmgenet_hfb_set_filter_rx_queue_mapping(priv, f_index, rx_queue);
2611 bcmgenet_hfb_enable_filter(priv, f_index);
2612 bcmgenet_hfb_reg_writel(priv, 0x1, HFB_CTRL);
2613
2614 return 0;
2615 }
2616
2617 /* bcmgenet_hfb_clear
2618 *
2619 * Clear Hardware Filter Block and disable all filtering.
2620 */
2621 static void bcmgenet_hfb_clear(struct bcmgenet_priv *priv)
2622 {
2623 u32 i;
2624
2625 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_CTRL);
2626 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS);
2627 bcmgenet_hfb_reg_writel(priv, 0x0, HFB_FLT_ENABLE_V3PLUS + 4);
2628
2629 for (i = DMA_INDEX2RING_0; i <= DMA_INDEX2RING_7; i++)
2630 bcmgenet_rdma_writel(priv, 0x0, i);
2631
2632 for (i = 0; i < (priv->hw_params->hfb_filter_cnt / 4); i++)
2633 bcmgenet_hfb_reg_writel(priv, 0x0,
2634 HFB_FLT_LEN_V3PLUS + i * sizeof(u32));
2635
2636 for (i = 0; i < priv->hw_params->hfb_filter_cnt *
2637 priv->hw_params->hfb_filter_size; i++)
2638 bcmgenet_hfb_writel(priv, 0x0, i * sizeof(u32));
2639 }
2640
2641 static void bcmgenet_hfb_init(struct bcmgenet_priv *priv)
2642 {
2643 if (GENET_IS_V1(priv) || GENET_IS_V2(priv))
2644 return;
2645
2646 bcmgenet_hfb_clear(priv);
2647 }
2648
2649 static void bcmgenet_netif_start(struct net_device *dev)
2650 {
2651 struct bcmgenet_priv *priv = netdev_priv(dev);
2652
2653 /* Start the network engine */
2654 bcmgenet_enable_rx_napi(priv);
2655 bcmgenet_enable_tx_napi(priv);
2656
2657 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, true);
2658
2659 netif_tx_start_all_queues(dev);
2660
2661 /* Monitor link interrupts now */
2662 bcmgenet_link_intr_enable(priv);
2663
2664 phy_start(priv->phydev);
2665 }
2666
2667 static int bcmgenet_open(struct net_device *dev)
2668 {
2669 struct bcmgenet_priv *priv = netdev_priv(dev);
2670 unsigned long dma_ctrl;
2671 u32 reg;
2672 int ret;
2673
2674 netif_dbg(priv, ifup, dev, "bcmgenet_open\n");
2675
2676 /* Turn on the clock */
2677 clk_prepare_enable(priv->clk);
2678
2679 /* If this is an internal GPHY, power it back on now, before UniMAC is
2680 * brought out of reset as absolutely no UniMAC activity is allowed
2681 */
2682 if (priv->internal_phy)
2683 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
2684
2685 /* take MAC out of reset */
2686 bcmgenet_umac_reset(priv);
2687
2688 ret = init_umac(priv);
2689 if (ret)
2690 goto err_clk_disable;
2691
2692 /* disable ethernet MAC while updating its registers */
2693 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
2694
2695 /* Make sure we reflect the value of CRC_CMD_FWD */
2696 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2697 priv->crc_fwd_en = !!(reg & CMD_CRC_FWD);
2698
2699 bcmgenet_set_hw_addr(priv, dev->dev_addr);
2700
2701 if (priv->internal_phy) {
2702 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
2703 reg |= EXT_ENERGY_DET_MASK;
2704 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
2705 }
2706
2707 /* Disable RX/TX DMA and flush TX queues */
2708 dma_ctrl = bcmgenet_dma_disable(priv);
2709
2710 /* Reinitialize TDMA and RDMA and SW housekeeping */
2711 ret = bcmgenet_init_dma(priv);
2712 if (ret) {
2713 netdev_err(dev, "failed to initialize DMA\n");
2714 goto err_clk_disable;
2715 }
2716
2717 /* Always enable ring 16 - descriptor ring */
2718 bcmgenet_enable_dma(priv, dma_ctrl);
2719
2720 /* HFB init */
2721 bcmgenet_hfb_init(priv);
2722
2723 ret = request_irq(priv->irq0, bcmgenet_isr0, IRQF_SHARED,
2724 dev->name, priv);
2725 if (ret < 0) {
2726 netdev_err(dev, "can't request IRQ %d\n", priv->irq0);
2727 goto err_fini_dma;
2728 }
2729
2730 ret = request_irq(priv->irq1, bcmgenet_isr1, IRQF_SHARED,
2731 dev->name, priv);
2732 if (ret < 0) {
2733 netdev_err(dev, "can't request IRQ %d\n", priv->irq1);
2734 goto err_irq0;
2735 }
2736
2737 ret = bcmgenet_mii_probe(dev);
2738 if (ret) {
2739 netdev_err(dev, "failed to connect to PHY\n");
2740 goto err_irq1;
2741 }
2742
2743 bcmgenet_netif_start(dev);
2744
2745 return 0;
2746
2747 err_irq1:
2748 free_irq(priv->irq1, priv);
2749 err_irq0:
2750 free_irq(priv->irq0, priv);
2751 err_fini_dma:
2752 bcmgenet_fini_dma(priv);
2753 err_clk_disable:
2754 clk_disable_unprepare(priv->clk);
2755 return ret;
2756 }
2757
2758 static void bcmgenet_netif_stop(struct net_device *dev)
2759 {
2760 struct bcmgenet_priv *priv = netdev_priv(dev);
2761
2762 netif_tx_stop_all_queues(dev);
2763 phy_stop(priv->phydev);
2764 bcmgenet_intr_disable(priv);
2765 bcmgenet_disable_rx_napi(priv);
2766 bcmgenet_disable_tx_napi(priv);
2767
2768 /* Wait for pending work items to complete. Since interrupts are
2769 * disabled no new work will be scheduled.
2770 */
2771 cancel_work_sync(&priv->bcmgenet_irq_work);
2772
2773 priv->old_link = -1;
2774 priv->old_speed = -1;
2775 priv->old_duplex = -1;
2776 priv->old_pause = -1;
2777 }
2778
2779 static int bcmgenet_close(struct net_device *dev)
2780 {
2781 struct bcmgenet_priv *priv = netdev_priv(dev);
2782 int ret;
2783
2784 netif_dbg(priv, ifdown, dev, "bcmgenet_close\n");
2785
2786 bcmgenet_netif_stop(dev);
2787
2788 /* Really kill the PHY state machine and disconnect from it */
2789 phy_disconnect(priv->phydev);
2790
2791 /* Disable MAC receive */
2792 umac_enable_set(priv, CMD_RX_EN, false);
2793
2794 ret = bcmgenet_dma_teardown(priv);
2795 if (ret)
2796 return ret;
2797
2798 /* Disable MAC transmit. TX DMA disabled have to done before this */
2799 umac_enable_set(priv, CMD_TX_EN, false);
2800
2801 /* tx reclaim */
2802 bcmgenet_tx_reclaim_all(dev);
2803 bcmgenet_fini_dma(priv);
2804
2805 free_irq(priv->irq0, priv);
2806 free_irq(priv->irq1, priv);
2807
2808 if (priv->internal_phy)
2809 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
2810
2811 clk_disable_unprepare(priv->clk);
2812
2813 return ret;
2814 }
2815
2816 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring *ring)
2817 {
2818 struct bcmgenet_priv *priv = ring->priv;
2819 u32 p_index, c_index, intsts, intmsk;
2820 struct netdev_queue *txq;
2821 unsigned int free_bds;
2822 unsigned long flags;
2823 bool txq_stopped;
2824
2825 if (!netif_msg_tx_err(priv))
2826 return;
2827
2828 txq = netdev_get_tx_queue(priv->dev, ring->queue);
2829
2830 spin_lock_irqsave(&ring->lock, flags);
2831 if (ring->index == DESC_INDEX) {
2832 intsts = ~bcmgenet_intrl2_0_readl(priv, INTRL2_CPU_MASK_STATUS);
2833 intmsk = UMAC_IRQ_TXDMA_DONE | UMAC_IRQ_TXDMA_MBDONE;
2834 } else {
2835 intsts = ~bcmgenet_intrl2_1_readl(priv, INTRL2_CPU_MASK_STATUS);
2836 intmsk = 1 << ring->index;
2837 }
2838 c_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_CONS_INDEX);
2839 p_index = bcmgenet_tdma_ring_readl(priv, ring->index, TDMA_PROD_INDEX);
2840 txq_stopped = netif_tx_queue_stopped(txq);
2841 free_bds = ring->free_bds;
2842 spin_unlock_irqrestore(&ring->lock, flags);
2843
2844 netif_err(priv, tx_err, priv->dev, "Ring %d queue %d status summary\n"
2845 "TX queue status: %s, interrupts: %s\n"
2846 "(sw)free_bds: %d (sw)size: %d\n"
2847 "(sw)p_index: %d (hw)p_index: %d\n"
2848 "(sw)c_index: %d (hw)c_index: %d\n"
2849 "(sw)clean_p: %d (sw)write_p: %d\n"
2850 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2851 ring->index, ring->queue,
2852 txq_stopped ? "stopped" : "active",
2853 intsts & intmsk ? "enabled" : "disabled",
2854 free_bds, ring->size,
2855 ring->prod_index, p_index & DMA_P_INDEX_MASK,
2856 ring->c_index, c_index & DMA_C_INDEX_MASK,
2857 ring->clean_ptr, ring->write_ptr,
2858 ring->cb_ptr, ring->end_ptr);
2859 }
2860
2861 static void bcmgenet_timeout(struct net_device *dev)
2862 {
2863 struct bcmgenet_priv *priv = netdev_priv(dev);
2864 u32 int0_enable = 0;
2865 u32 int1_enable = 0;
2866 unsigned int q;
2867
2868 netif_dbg(priv, tx_err, dev, "bcmgenet_timeout\n");
2869
2870 for (q = 0; q < priv->hw_params->tx_queues; q++)
2871 bcmgenet_dump_tx_queue(&priv->tx_rings[q]);
2872 bcmgenet_dump_tx_queue(&priv->tx_rings[DESC_INDEX]);
2873
2874 bcmgenet_tx_reclaim_all(dev);
2875
2876 for (q = 0; q < priv->hw_params->tx_queues; q++)
2877 int1_enable |= (1 << q);
2878
2879 int0_enable = UMAC_IRQ_TXDMA_DONE;
2880
2881 /* Re-enable TX interrupts if disabled */
2882 bcmgenet_intrl2_0_writel(priv, int0_enable, INTRL2_CPU_MASK_CLEAR);
2883 bcmgenet_intrl2_1_writel(priv, int1_enable, INTRL2_CPU_MASK_CLEAR);
2884
2885 dev->trans_start = jiffies;
2886
2887 dev->stats.tx_errors++;
2888
2889 netif_tx_wake_all_queues(dev);
2890 }
2891
2892 #define MAX_MC_COUNT 16
2893
2894 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv *priv,
2895 unsigned char *addr,
2896 int *i,
2897 int *mc)
2898 {
2899 u32 reg;
2900
2901 bcmgenet_umac_writel(priv, addr[0] << 8 | addr[1],
2902 UMAC_MDF_ADDR + (*i * 4));
2903 bcmgenet_umac_writel(priv, addr[2] << 24 | addr[3] << 16 |
2904 addr[4] << 8 | addr[5],
2905 UMAC_MDF_ADDR + ((*i + 1) * 4));
2906 reg = bcmgenet_umac_readl(priv, UMAC_MDF_CTRL);
2907 reg |= (1 << (MAX_MC_COUNT - *mc));
2908 bcmgenet_umac_writel(priv, reg, UMAC_MDF_CTRL);
2909 *i += 2;
2910 (*mc)++;
2911 }
2912
2913 static void bcmgenet_set_rx_mode(struct net_device *dev)
2914 {
2915 struct bcmgenet_priv *priv = netdev_priv(dev);
2916 struct netdev_hw_addr *ha;
2917 int i, mc;
2918 u32 reg;
2919
2920 netif_dbg(priv, hw, dev, "%s: %08X\n", __func__, dev->flags);
2921
2922 /* Promiscuous mode */
2923 reg = bcmgenet_umac_readl(priv, UMAC_CMD);
2924 if (dev->flags & IFF_PROMISC) {
2925 reg |= CMD_PROMISC;
2926 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2927 bcmgenet_umac_writel(priv, 0, UMAC_MDF_CTRL);
2928 return;
2929 } else {
2930 reg &= ~CMD_PROMISC;
2931 bcmgenet_umac_writel(priv, reg, UMAC_CMD);
2932 }
2933
2934 /* UniMac doesn't support ALLMULTI */
2935 if (dev->flags & IFF_ALLMULTI) {
2936 netdev_warn(dev, "ALLMULTI is not supported\n");
2937 return;
2938 }
2939
2940 /* update MDF filter */
2941 i = 0;
2942 mc = 0;
2943 /* Broadcast */
2944 bcmgenet_set_mdf_addr(priv, dev->broadcast, &i, &mc);
2945 /* my own address.*/
2946 bcmgenet_set_mdf_addr(priv, dev->dev_addr, &i, &mc);
2947 /* Unicast list*/
2948 if (netdev_uc_count(dev) > (MAX_MC_COUNT - mc))
2949 return;
2950
2951 if (!netdev_uc_empty(dev))
2952 netdev_for_each_uc_addr(ha, dev)
2953 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2954 /* Multicast */
2955 if (netdev_mc_empty(dev) || netdev_mc_count(dev) >= (MAX_MC_COUNT - mc))
2956 return;
2957
2958 netdev_for_each_mc_addr(ha, dev)
2959 bcmgenet_set_mdf_addr(priv, ha->addr, &i, &mc);
2960 }
2961
2962 /* Set the hardware MAC address. */
2963 static int bcmgenet_set_mac_addr(struct net_device *dev, void *p)
2964 {
2965 struct sockaddr *addr = p;
2966
2967 /* Setting the MAC address at the hardware level is not possible
2968 * without disabling the UniMAC RX/TX enable bits.
2969 */
2970 if (netif_running(dev))
2971 return -EBUSY;
2972
2973 ether_addr_copy(dev->dev_addr, addr->sa_data);
2974
2975 return 0;
2976 }
2977
2978 static const struct net_device_ops bcmgenet_netdev_ops = {
2979 .ndo_open = bcmgenet_open,
2980 .ndo_stop = bcmgenet_close,
2981 .ndo_start_xmit = bcmgenet_xmit,
2982 .ndo_tx_timeout = bcmgenet_timeout,
2983 .ndo_set_rx_mode = bcmgenet_set_rx_mode,
2984 .ndo_set_mac_address = bcmgenet_set_mac_addr,
2985 .ndo_do_ioctl = bcmgenet_ioctl,
2986 .ndo_set_features = bcmgenet_set_features,
2987 #ifdef CONFIG_NET_POLL_CONTROLLER
2988 .ndo_poll_controller = bcmgenet_poll_controller,
2989 #endif
2990 };
2991
2992 /* Array of GENET hardware parameters/characteristics */
2993 static struct bcmgenet_hw_params bcmgenet_hw_params[] = {
2994 [GENET_V1] = {
2995 .tx_queues = 0,
2996 .tx_bds_per_q = 0,
2997 .rx_queues = 0,
2998 .rx_bds_per_q = 0,
2999 .bp_in_en_shift = 16,
3000 .bp_in_mask = 0xffff,
3001 .hfb_filter_cnt = 16,
3002 .qtag_mask = 0x1F,
3003 .hfb_offset = 0x1000,
3004 .rdma_offset = 0x2000,
3005 .tdma_offset = 0x3000,
3006 .words_per_bd = 2,
3007 },
3008 [GENET_V2] = {
3009 .tx_queues = 4,
3010 .tx_bds_per_q = 32,
3011 .rx_queues = 0,
3012 .rx_bds_per_q = 0,
3013 .bp_in_en_shift = 16,
3014 .bp_in_mask = 0xffff,
3015 .hfb_filter_cnt = 16,
3016 .qtag_mask = 0x1F,
3017 .tbuf_offset = 0x0600,
3018 .hfb_offset = 0x1000,
3019 .hfb_reg_offset = 0x2000,
3020 .rdma_offset = 0x3000,
3021 .tdma_offset = 0x4000,
3022 .words_per_bd = 2,
3023 .flags = GENET_HAS_EXT,
3024 },
3025 [GENET_V3] = {
3026 .tx_queues = 4,
3027 .tx_bds_per_q = 32,
3028 .rx_queues = 0,
3029 .rx_bds_per_q = 0,
3030 .bp_in_en_shift = 17,
3031 .bp_in_mask = 0x1ffff,
3032 .hfb_filter_cnt = 48,
3033 .hfb_filter_size = 128,
3034 .qtag_mask = 0x3F,
3035 .tbuf_offset = 0x0600,
3036 .hfb_offset = 0x8000,
3037 .hfb_reg_offset = 0xfc00,
3038 .rdma_offset = 0x10000,
3039 .tdma_offset = 0x11000,
3040 .words_per_bd = 2,
3041 .flags = GENET_HAS_EXT | GENET_HAS_MDIO_INTR |
3042 GENET_HAS_MOCA_LINK_DET,
3043 },
3044 [GENET_V4] = {
3045 .tx_queues = 4,
3046 .tx_bds_per_q = 32,
3047 .rx_queues = 0,
3048 .rx_bds_per_q = 0,
3049 .bp_in_en_shift = 17,
3050 .bp_in_mask = 0x1ffff,
3051 .hfb_filter_cnt = 48,
3052 .hfb_filter_size = 128,
3053 .qtag_mask = 0x3F,
3054 .tbuf_offset = 0x0600,
3055 .hfb_offset = 0x8000,
3056 .hfb_reg_offset = 0xfc00,
3057 .rdma_offset = 0x2000,
3058 .tdma_offset = 0x4000,
3059 .words_per_bd = 3,
3060 .flags = GENET_HAS_40BITS | GENET_HAS_EXT |
3061 GENET_HAS_MDIO_INTR | GENET_HAS_MOCA_LINK_DET,
3062 },
3063 };
3064
3065 /* Infer hardware parameters from the detected GENET version */
3066 static void bcmgenet_set_hw_params(struct bcmgenet_priv *priv)
3067 {
3068 struct bcmgenet_hw_params *params;
3069 u32 reg;
3070 u8 major;
3071 u16 gphy_rev;
3072
3073 if (GENET_IS_V4(priv)) {
3074 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3075 genet_dma_ring_regs = genet_dma_ring_regs_v4;
3076 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3077 priv->version = GENET_V4;
3078 } else if (GENET_IS_V3(priv)) {
3079 bcmgenet_dma_regs = bcmgenet_dma_regs_v3plus;
3080 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3081 priv->dma_rx_chk_bit = DMA_RX_CHK_V3PLUS;
3082 priv->version = GENET_V3;
3083 } else if (GENET_IS_V2(priv)) {
3084 bcmgenet_dma_regs = bcmgenet_dma_regs_v2;
3085 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3086 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3087 priv->version = GENET_V2;
3088 } else if (GENET_IS_V1(priv)) {
3089 bcmgenet_dma_regs = bcmgenet_dma_regs_v1;
3090 genet_dma_ring_regs = genet_dma_ring_regs_v123;
3091 priv->dma_rx_chk_bit = DMA_RX_CHK_V12;
3092 priv->version = GENET_V1;
3093 }
3094
3095 /* enum genet_version starts at 1 */
3096 priv->hw_params = &bcmgenet_hw_params[priv->version];
3097 params = priv->hw_params;
3098
3099 /* Read GENET HW version */
3100 reg = bcmgenet_sys_readl(priv, SYS_REV_CTRL);
3101 major = (reg >> 24 & 0x0f);
3102 if (major == 5)
3103 major = 4;
3104 else if (major == 0)
3105 major = 1;
3106 if (major != priv->version) {
3107 dev_err(&priv->pdev->dev,
3108 "GENET version mismatch, got: %d, configured for: %d\n",
3109 major, priv->version);
3110 }
3111
3112 /* Print the GENET core version */
3113 dev_info(&priv->pdev->dev, "GENET " GENET_VER_FMT,
3114 major, (reg >> 16) & 0x0f, reg & 0xffff);
3115
3116 /* Store the integrated PHY revision for the MDIO probing function
3117 * to pass this information to the PHY driver. The PHY driver expects
3118 * to find the PHY major revision in bits 15:8 while the GENET register
3119 * stores that information in bits 7:0, account for that.
3120 *
3121 * On newer chips, starting with PHY revision G0, a new scheme is
3122 * deployed similar to the Starfighter 2 switch with GPHY major
3123 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3124 * is reserved as well as special value 0x01ff, we have a small
3125 * heuristic to check for the new GPHY revision and re-arrange things
3126 * so the GPHY driver is happy.
3127 */
3128 gphy_rev = reg & 0xffff;
3129
3130 /* This is the good old scheme, just GPHY major, no minor nor patch */
3131 if ((gphy_rev & 0xf0) != 0)
3132 priv->gphy_rev = gphy_rev << 8;
3133
3134 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3135 else if ((gphy_rev & 0xff00) != 0)
3136 priv->gphy_rev = gphy_rev;
3137
3138 /* This is reserved so should require special treatment */
3139 else if (gphy_rev == 0 || gphy_rev == 0x01ff) {
3140 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev);
3141 return;
3142 }
3143
3144 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3145 if (!(params->flags & GENET_HAS_40BITS))
3146 pr_warn("GENET does not support 40-bits PA\n");
3147 #endif
3148
3149 pr_debug("Configuration for version: %d\n"
3150 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3151 "BP << en: %2d, BP msk: 0x%05x\n"
3152 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3153 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3154 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3155 "Words/BD: %d\n",
3156 priv->version,
3157 params->tx_queues, params->tx_bds_per_q,
3158 params->rx_queues, params->rx_bds_per_q,
3159 params->bp_in_en_shift, params->bp_in_mask,
3160 params->hfb_filter_cnt, params->qtag_mask,
3161 params->tbuf_offset, params->hfb_offset,
3162 params->hfb_reg_offset,
3163 params->rdma_offset, params->tdma_offset,
3164 params->words_per_bd);
3165 }
3166
3167 static const struct of_device_id bcmgenet_match[] = {
3168 { .compatible = "brcm,genet-v1", .data = (void *)GENET_V1 },
3169 { .compatible = "brcm,genet-v2", .data = (void *)GENET_V2 },
3170 { .compatible = "brcm,genet-v3", .data = (void *)GENET_V3 },
3171 { .compatible = "brcm,genet-v4", .data = (void *)GENET_V4 },
3172 { },
3173 };
3174 MODULE_DEVICE_TABLE(of, bcmgenet_match);
3175
3176 static int bcmgenet_probe(struct platform_device *pdev)
3177 {
3178 struct bcmgenet_platform_data *pd = pdev->dev.platform_data;
3179 struct device_node *dn = pdev->dev.of_node;
3180 const struct of_device_id *of_id = NULL;
3181 struct bcmgenet_priv *priv;
3182 struct net_device *dev;
3183 const void *macaddr;
3184 struct resource *r;
3185 int err = -EIO;
3186
3187 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3188 dev = alloc_etherdev_mqs(sizeof(*priv), GENET_MAX_MQ_CNT + 1,
3189 GENET_MAX_MQ_CNT + 1);
3190 if (!dev) {
3191 dev_err(&pdev->dev, "can't allocate net device\n");
3192 return -ENOMEM;
3193 }
3194
3195 if (dn) {
3196 of_id = of_match_node(bcmgenet_match, dn);
3197 if (!of_id)
3198 return -EINVAL;
3199 }
3200
3201 priv = netdev_priv(dev);
3202 priv->irq0 = platform_get_irq(pdev, 0);
3203 priv->irq1 = platform_get_irq(pdev, 1);
3204 priv->wol_irq = platform_get_irq(pdev, 2);
3205 if (!priv->irq0 || !priv->irq1) {
3206 dev_err(&pdev->dev, "can't find IRQs\n");
3207 err = -EINVAL;
3208 goto err;
3209 }
3210
3211 if (dn) {
3212 macaddr = of_get_mac_address(dn);
3213 if (!macaddr) {
3214 dev_err(&pdev->dev, "can't find MAC address\n");
3215 err = -EINVAL;
3216 goto err;
3217 }
3218 } else {
3219 macaddr = pd->mac_address;
3220 }
3221
3222 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3223 priv->base = devm_ioremap_resource(&pdev->dev, r);
3224 if (IS_ERR(priv->base)) {
3225 err = PTR_ERR(priv->base);
3226 goto err;
3227 }
3228
3229 SET_NETDEV_DEV(dev, &pdev->dev);
3230 dev_set_drvdata(&pdev->dev, dev);
3231 ether_addr_copy(dev->dev_addr, macaddr);
3232 dev->watchdog_timeo = 2 * HZ;
3233 dev->ethtool_ops = &bcmgenet_ethtool_ops;
3234 dev->netdev_ops = &bcmgenet_netdev_ops;
3235
3236 priv->msg_enable = netif_msg_init(-1, GENET_MSG_DEFAULT);
3237
3238 /* Set hardware features */
3239 dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM |
3240 NETIF_F_IPV6_CSUM | NETIF_F_RXCSUM;
3241
3242 /* Request the WOL interrupt and advertise suspend if available */
3243 priv->wol_irq_disabled = true;
3244 err = devm_request_irq(&pdev->dev, priv->wol_irq, bcmgenet_wol_isr, 0,
3245 dev->name, priv);
3246 if (!err)
3247 device_set_wakeup_capable(&pdev->dev, 1);
3248
3249 /* Set the needed headroom to account for any possible
3250 * features enabling/disabling at runtime
3251 */
3252 dev->needed_headroom += 64;
3253
3254 netdev_boot_setup_check(dev);
3255
3256 priv->dev = dev;
3257 priv->pdev = pdev;
3258 if (of_id)
3259 priv->version = (enum bcmgenet_version)of_id->data;
3260 else
3261 priv->version = pd->genet_version;
3262
3263 priv->clk = devm_clk_get(&priv->pdev->dev, "enet");
3264 if (IS_ERR(priv->clk)) {
3265 dev_warn(&priv->pdev->dev, "failed to get enet clock\n");
3266 priv->clk = NULL;
3267 }
3268
3269 clk_prepare_enable(priv->clk);
3270
3271 bcmgenet_set_hw_params(priv);
3272
3273 /* Mii wait queue */
3274 init_waitqueue_head(&priv->wq);
3275 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3276 priv->rx_buf_len = RX_BUF_LENGTH;
3277 INIT_WORK(&priv->bcmgenet_irq_work, bcmgenet_irq_task);
3278
3279 priv->clk_wol = devm_clk_get(&priv->pdev->dev, "enet-wol");
3280 if (IS_ERR(priv->clk_wol)) {
3281 dev_warn(&priv->pdev->dev, "failed to get enet-wol clock\n");
3282 priv->clk_wol = NULL;
3283 }
3284
3285 priv->clk_eee = devm_clk_get(&priv->pdev->dev, "enet-eee");
3286 if (IS_ERR(priv->clk_eee)) {
3287 dev_warn(&priv->pdev->dev, "failed to get enet-eee clock\n");
3288 priv->clk_eee = NULL;
3289 }
3290
3291 err = reset_umac(priv);
3292 if (err)
3293 goto err_clk_disable;
3294
3295 err = bcmgenet_mii_init(dev);
3296 if (err)
3297 goto err_clk_disable;
3298
3299 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3300 * just the ring 16 descriptor based TX
3301 */
3302 netif_set_real_num_tx_queues(priv->dev, priv->hw_params->tx_queues + 1);
3303 netif_set_real_num_rx_queues(priv->dev, priv->hw_params->rx_queues + 1);
3304
3305 /* libphy will determine the link state */
3306 netif_carrier_off(dev);
3307
3308 /* Turn off the main clock, WOL clock is handled separately */
3309 clk_disable_unprepare(priv->clk);
3310
3311 err = register_netdev(dev);
3312 if (err)
3313 goto err;
3314
3315 return err;
3316
3317 err_clk_disable:
3318 clk_disable_unprepare(priv->clk);
3319 err:
3320 free_netdev(dev);
3321 return err;
3322 }
3323
3324 static int bcmgenet_remove(struct platform_device *pdev)
3325 {
3326 struct bcmgenet_priv *priv = dev_to_priv(&pdev->dev);
3327
3328 dev_set_drvdata(&pdev->dev, NULL);
3329 unregister_netdev(priv->dev);
3330 bcmgenet_mii_exit(priv->dev);
3331 free_netdev(priv->dev);
3332
3333 return 0;
3334 }
3335
3336 #ifdef CONFIG_PM_SLEEP
3337 static int bcmgenet_suspend(struct device *d)
3338 {
3339 struct net_device *dev = dev_get_drvdata(d);
3340 struct bcmgenet_priv *priv = netdev_priv(dev);
3341 int ret;
3342
3343 if (!netif_running(dev))
3344 return 0;
3345
3346 bcmgenet_netif_stop(dev);
3347
3348 phy_suspend(priv->phydev);
3349
3350 netif_device_detach(dev);
3351
3352 /* Disable MAC receive */
3353 umac_enable_set(priv, CMD_RX_EN, false);
3354
3355 ret = bcmgenet_dma_teardown(priv);
3356 if (ret)
3357 return ret;
3358
3359 /* Disable MAC transmit. TX DMA disabled have to done before this */
3360 umac_enable_set(priv, CMD_TX_EN, false);
3361
3362 /* tx reclaim */
3363 bcmgenet_tx_reclaim_all(dev);
3364 bcmgenet_fini_dma(priv);
3365
3366 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3367 if (device_may_wakeup(d) && priv->wolopts) {
3368 ret = bcmgenet_power_down(priv, GENET_POWER_WOL_MAGIC);
3369 clk_prepare_enable(priv->clk_wol);
3370 } else if (priv->internal_phy) {
3371 ret = bcmgenet_power_down(priv, GENET_POWER_PASSIVE);
3372 }
3373
3374 /* Turn off the clocks */
3375 clk_disable_unprepare(priv->clk);
3376
3377 return ret;
3378 }
3379
3380 static int bcmgenet_resume(struct device *d)
3381 {
3382 struct net_device *dev = dev_get_drvdata(d);
3383 struct bcmgenet_priv *priv = netdev_priv(dev);
3384 unsigned long dma_ctrl;
3385 int ret;
3386 u32 reg;
3387
3388 if (!netif_running(dev))
3389 return 0;
3390
3391 /* Turn on the clock */
3392 ret = clk_prepare_enable(priv->clk);
3393 if (ret)
3394 return ret;
3395
3396 /* If this is an internal GPHY, power it back on now, before UniMAC is
3397 * brought out of reset as absolutely no UniMAC activity is allowed
3398 */
3399 if (priv->internal_phy)
3400 bcmgenet_power_up(priv, GENET_POWER_PASSIVE);
3401
3402 bcmgenet_umac_reset(priv);
3403
3404 ret = init_umac(priv);
3405 if (ret)
3406 goto out_clk_disable;
3407
3408 /* From WOL-enabled suspend, switch to regular clock */
3409 if (priv->wolopts)
3410 clk_disable_unprepare(priv->clk_wol);
3411
3412 phy_init_hw(priv->phydev);
3413 /* Speed settings must be restored */
3414 bcmgenet_mii_config(priv->dev);
3415
3416 /* disable ethernet MAC while updating its registers */
3417 umac_enable_set(priv, CMD_TX_EN | CMD_RX_EN, false);
3418
3419 bcmgenet_set_hw_addr(priv, dev->dev_addr);
3420
3421 if (priv->internal_phy) {
3422 reg = bcmgenet_ext_readl(priv, EXT_EXT_PWR_MGMT);
3423 reg |= EXT_ENERGY_DET_MASK;
3424 bcmgenet_ext_writel(priv, reg, EXT_EXT_PWR_MGMT);
3425 }
3426
3427 if (priv->wolopts)
3428 bcmgenet_power_up(priv, GENET_POWER_WOL_MAGIC);
3429
3430 /* Disable RX/TX DMA and flush TX queues */
3431 dma_ctrl = bcmgenet_dma_disable(priv);
3432
3433 /* Reinitialize TDMA and RDMA and SW housekeeping */
3434 ret = bcmgenet_init_dma(priv);
3435 if (ret) {
3436 netdev_err(dev, "failed to initialize DMA\n");
3437 goto out_clk_disable;
3438 }
3439
3440 /* Always enable ring 16 - descriptor ring */
3441 bcmgenet_enable_dma(priv, dma_ctrl);
3442
3443 netif_device_attach(dev);
3444
3445 phy_resume(priv->phydev);
3446
3447 if (priv->eee.eee_enabled)
3448 bcmgenet_eee_enable_set(dev, true);
3449
3450 bcmgenet_netif_start(dev);
3451
3452 return 0;
3453
3454 out_clk_disable:
3455 clk_disable_unprepare(priv->clk);
3456 return ret;
3457 }
3458 #endif /* CONFIG_PM_SLEEP */
3459
3460 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops, bcmgenet_suspend, bcmgenet_resume);
3461
3462 static struct platform_driver bcmgenet_driver = {
3463 .probe = bcmgenet_probe,
3464 .remove = bcmgenet_remove,
3465 .driver = {
3466 .name = "bcmgenet",
3467 .of_match_table = bcmgenet_match,
3468 .pm = &bcmgenet_pm_ops,
3469 },
3470 };
3471 module_platform_driver(bcmgenet_driver);
3472
3473 MODULE_AUTHOR("Broadcom Corporation");
3474 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3475 MODULE_ALIAS("platform:bcmgenet");
3476 MODULE_LICENSE("GPL");
Linux kernel - Deliverables
This page took 0.103853 seconds and 5 git commands to generate.