2 * Broadcom GENET (Gigabit Ethernet) controller driver
4 * Copyright (c) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) "bcmgenet: " fmt
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/clk.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
47 #include <asm/unaligned.h>
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
57 #define GENET_Q16_RX_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->rx_queues * priv->hw_params->rx_bds_per_q)
59 #define GENET_Q16_TX_BD_CNT \
60 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->tx_bds_per_q)
62 #define RX_BUF_LENGTH 2048
63 #define SKB_ALIGNMENT 32
65 /* Tx/Rx DMA register offset, skip 256 descriptors */
66 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
67 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
69 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
70 TOTAL_DESC * DMA_DESC_SIZE)
72 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
73 TOTAL_DESC * DMA_DESC_SIZE)
75 static inline void dmadesc_set_length_status(struct bcmgenet_priv
*priv
,
76 void __iomem
*d
, u32 value
)
78 __raw_writel(value
, d
+ DMA_DESC_LENGTH_STATUS
);
81 static inline u32
dmadesc_get_length_status(struct bcmgenet_priv
*priv
,
84 return __raw_readl(d
+ DMA_DESC_LENGTH_STATUS
);
87 static inline void dmadesc_set_addr(struct bcmgenet_priv
*priv
,
91 __raw_writel(lower_32_bits(addr
), d
+ DMA_DESC_ADDRESS_LO
);
93 /* Register writes to GISB bus can take couple hundred nanoseconds
94 * and are done for each packet, save these expensive writes unless
95 * the platform is explicitly configured for 64-bits/LPAE.
97 #ifdef CONFIG_PHYS_ADDR_T_64BIT
98 if (priv
->hw_params
->flags
& GENET_HAS_40BITS
)
99 __raw_writel(upper_32_bits(addr
), d
+ DMA_DESC_ADDRESS_HI
);
103 /* Combined address + length/status setter */
104 static inline void dmadesc_set(struct bcmgenet_priv
*priv
,
105 void __iomem
*d
, dma_addr_t addr
, u32 val
)
107 dmadesc_set_length_status(priv
, d
, val
);
108 dmadesc_set_addr(priv
, d
, addr
);
111 static inline dma_addr_t
dmadesc_get_addr(struct bcmgenet_priv
*priv
,
116 addr
= __raw_readl(d
+ DMA_DESC_ADDRESS_LO
);
118 /* Register writes to GISB bus can take couple hundred nanoseconds
119 * and are done for each packet, save these expensive writes unless
120 * the platform is explicitly configured for 64-bits/LPAE.
122 #ifdef CONFIG_PHYS_ADDR_T_64BIT
123 if (priv
->hw_params
->flags
& GENET_HAS_40BITS
)
124 addr
|= (u64
)__raw_readl(d
+ DMA_DESC_ADDRESS_HI
) << 32;
129 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
131 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
134 static inline u32
bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv
*priv
)
136 if (GENET_IS_V1(priv
))
137 return bcmgenet_rbuf_readl(priv
, RBUF_FLUSH_CTRL_V1
);
139 return bcmgenet_sys_readl(priv
, SYS_RBUF_FLUSH_CTRL
);
142 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv
*priv
, u32 val
)
144 if (GENET_IS_V1(priv
))
145 bcmgenet_rbuf_writel(priv
, val
, RBUF_FLUSH_CTRL_V1
);
147 bcmgenet_sys_writel(priv
, val
, SYS_RBUF_FLUSH_CTRL
);
150 /* These macros are defined to deal with register map change
151 * between GENET1.1 and GENET2. Only those currently being used
152 * by driver are defined.
154 static inline u32
bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv
*priv
)
156 if (GENET_IS_V1(priv
))
157 return bcmgenet_rbuf_readl(priv
, TBUF_CTRL_V1
);
159 return __raw_readl(priv
->base
+
160 priv
->hw_params
->tbuf_offset
+ TBUF_CTRL
);
163 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv
*priv
, u32 val
)
165 if (GENET_IS_V1(priv
))
166 bcmgenet_rbuf_writel(priv
, val
, TBUF_CTRL_V1
);
168 __raw_writel(val
, priv
->base
+
169 priv
->hw_params
->tbuf_offset
+ TBUF_CTRL
);
172 static inline u32
bcmgenet_bp_mc_get(struct bcmgenet_priv
*priv
)
174 if (GENET_IS_V1(priv
))
175 return bcmgenet_rbuf_readl(priv
, TBUF_BP_MC_V1
);
177 return __raw_readl(priv
->base
+
178 priv
->hw_params
->tbuf_offset
+ TBUF_BP_MC
);
181 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv
*priv
, u32 val
)
183 if (GENET_IS_V1(priv
))
184 bcmgenet_rbuf_writel(priv
, val
, TBUF_BP_MC_V1
);
186 __raw_writel(val
, priv
->base
+
187 priv
->hw_params
->tbuf_offset
+ TBUF_BP_MC
);
190 /* RX/TX DMA register accessors */
210 static const u8 bcmgenet_dma_regs_v3plus
[] = {
211 [DMA_RING_CFG
] = 0x00,
214 [DMA_SCB_BURST_SIZE
] = 0x0C,
215 [DMA_ARB_CTRL
] = 0x2C,
216 [DMA_PRIORITY_0
] = 0x30,
217 [DMA_PRIORITY_1
] = 0x34,
218 [DMA_PRIORITY_2
] = 0x38,
219 [DMA_INDEX2RING_0
] = 0x70,
220 [DMA_INDEX2RING_1
] = 0x74,
221 [DMA_INDEX2RING_2
] = 0x78,
222 [DMA_INDEX2RING_3
] = 0x7C,
223 [DMA_INDEX2RING_4
] = 0x80,
224 [DMA_INDEX2RING_5
] = 0x84,
225 [DMA_INDEX2RING_6
] = 0x88,
226 [DMA_INDEX2RING_7
] = 0x8C,
229 static const u8 bcmgenet_dma_regs_v2
[] = {
230 [DMA_RING_CFG
] = 0x00,
233 [DMA_SCB_BURST_SIZE
] = 0x0C,
234 [DMA_ARB_CTRL
] = 0x30,
235 [DMA_PRIORITY_0
] = 0x34,
236 [DMA_PRIORITY_1
] = 0x38,
237 [DMA_PRIORITY_2
] = 0x3C,
240 static const u8 bcmgenet_dma_regs_v1
[] = {
243 [DMA_SCB_BURST_SIZE
] = 0x0C,
244 [DMA_ARB_CTRL
] = 0x30,
245 [DMA_PRIORITY_0
] = 0x34,
246 [DMA_PRIORITY_1
] = 0x38,
247 [DMA_PRIORITY_2
] = 0x3C,
250 /* Set at runtime once bcmgenet version is known */
251 static const u8
*bcmgenet_dma_regs
;
253 static inline struct bcmgenet_priv
*dev_to_priv(struct device
*dev
)
255 return netdev_priv(dev_get_drvdata(dev
));
258 static inline u32
bcmgenet_tdma_readl(struct bcmgenet_priv
*priv
,
261 return __raw_readl(priv
->base
+ GENET_TDMA_REG_OFF
+
262 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
265 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv
*priv
,
266 u32 val
, enum dma_reg r
)
268 __raw_writel(val
, priv
->base
+ GENET_TDMA_REG_OFF
+
269 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
272 static inline u32
bcmgenet_rdma_readl(struct bcmgenet_priv
*priv
,
275 return __raw_readl(priv
->base
+ GENET_RDMA_REG_OFF
+
276 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
279 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv
*priv
,
280 u32 val
, enum dma_reg r
)
282 __raw_writel(val
, priv
->base
+ GENET_RDMA_REG_OFF
+
283 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
286 /* RDMA/TDMA ring registers and accessors
287 * we merge the common fields and just prefix with T/D the registers
288 * having different meaning depending on the direction
292 RDMA_WRITE_PTR
= TDMA_READ_PTR
,
294 RDMA_WRITE_PTR_HI
= TDMA_READ_PTR_HI
,
296 RDMA_PROD_INDEX
= TDMA_CONS_INDEX
,
298 RDMA_CONS_INDEX
= TDMA_PROD_INDEX
,
304 DMA_MBUF_DONE_THRESH
,
306 RDMA_XON_XOFF_THRESH
= TDMA_FLOW_PERIOD
,
308 RDMA_READ_PTR
= TDMA_WRITE_PTR
,
310 RDMA_READ_PTR_HI
= TDMA_WRITE_PTR_HI
313 /* GENET v4 supports 40-bits pointer addressing
314 * for obvious reasons the LO and HI word parts
315 * are contiguous, but this offsets the other
318 static const u8 genet_dma_ring_regs_v4
[] = {
319 [TDMA_READ_PTR
] = 0x00,
320 [TDMA_READ_PTR_HI
] = 0x04,
321 [TDMA_CONS_INDEX
] = 0x08,
322 [TDMA_PROD_INDEX
] = 0x0C,
323 [DMA_RING_BUF_SIZE
] = 0x10,
324 [DMA_START_ADDR
] = 0x14,
325 [DMA_START_ADDR_HI
] = 0x18,
326 [DMA_END_ADDR
] = 0x1C,
327 [DMA_END_ADDR_HI
] = 0x20,
328 [DMA_MBUF_DONE_THRESH
] = 0x24,
329 [TDMA_FLOW_PERIOD
] = 0x28,
330 [TDMA_WRITE_PTR
] = 0x2C,
331 [TDMA_WRITE_PTR_HI
] = 0x30,
334 static const u8 genet_dma_ring_regs_v123
[] = {
335 [TDMA_READ_PTR
] = 0x00,
336 [TDMA_CONS_INDEX
] = 0x04,
337 [TDMA_PROD_INDEX
] = 0x08,
338 [DMA_RING_BUF_SIZE
] = 0x0C,
339 [DMA_START_ADDR
] = 0x10,
340 [DMA_END_ADDR
] = 0x14,
341 [DMA_MBUF_DONE_THRESH
] = 0x18,
342 [TDMA_FLOW_PERIOD
] = 0x1C,
343 [TDMA_WRITE_PTR
] = 0x20,
346 /* Set at runtime once GENET version is known */
347 static const u8
*genet_dma_ring_regs
;
349 static inline u32
bcmgenet_tdma_ring_readl(struct bcmgenet_priv
*priv
,
353 return __raw_readl(priv
->base
+ GENET_TDMA_REG_OFF
+
354 (DMA_RING_SIZE
* ring
) +
355 genet_dma_ring_regs
[r
]);
358 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv
*priv
,
359 unsigned int ring
, u32 val
,
362 __raw_writel(val
, priv
->base
+ GENET_TDMA_REG_OFF
+
363 (DMA_RING_SIZE
* ring
) +
364 genet_dma_ring_regs
[r
]);
367 static inline u32
bcmgenet_rdma_ring_readl(struct bcmgenet_priv
*priv
,
371 return __raw_readl(priv
->base
+ GENET_RDMA_REG_OFF
+
372 (DMA_RING_SIZE
* ring
) +
373 genet_dma_ring_regs
[r
]);
376 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv
*priv
,
377 unsigned int ring
, u32 val
,
380 __raw_writel(val
, priv
->base
+ GENET_RDMA_REG_OFF
+
381 (DMA_RING_SIZE
* ring
) +
382 genet_dma_ring_regs
[r
]);
385 static int bcmgenet_get_settings(struct net_device
*dev
,
386 struct ethtool_cmd
*cmd
)
388 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
390 if (!netif_running(dev
))
396 return phy_ethtool_gset(priv
->phydev
, cmd
);
399 static int bcmgenet_set_settings(struct net_device
*dev
,
400 struct ethtool_cmd
*cmd
)
402 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
404 if (!netif_running(dev
))
410 return phy_ethtool_sset(priv
->phydev
, cmd
);
413 static int bcmgenet_set_rx_csum(struct net_device
*dev
,
414 netdev_features_t wanted
)
416 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
420 rx_csum_en
= !!(wanted
& NETIF_F_RXCSUM
);
422 rbuf_chk_ctrl
= bcmgenet_rbuf_readl(priv
, RBUF_CHK_CTRL
);
424 /* enable rx checksumming */
426 rbuf_chk_ctrl
|= RBUF_RXCHK_EN
;
428 rbuf_chk_ctrl
&= ~RBUF_RXCHK_EN
;
429 priv
->desc_rxchk_en
= rx_csum_en
;
431 /* If UniMAC forwards CRC, we need to skip over it to get
432 * a valid CHK bit to be set in the per-packet status word
434 if (rx_csum_en
&& priv
->crc_fwd_en
)
435 rbuf_chk_ctrl
|= RBUF_SKIP_FCS
;
437 rbuf_chk_ctrl
&= ~RBUF_SKIP_FCS
;
439 bcmgenet_rbuf_writel(priv
, rbuf_chk_ctrl
, RBUF_CHK_CTRL
);
444 static int bcmgenet_set_tx_csum(struct net_device
*dev
,
445 netdev_features_t wanted
)
447 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
449 u32 tbuf_ctrl
, rbuf_ctrl
;
451 tbuf_ctrl
= bcmgenet_tbuf_ctrl_get(priv
);
452 rbuf_ctrl
= bcmgenet_rbuf_readl(priv
, RBUF_CTRL
);
454 desc_64b_en
= !!(wanted
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
));
456 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
458 tbuf_ctrl
|= RBUF_64B_EN
;
459 rbuf_ctrl
|= RBUF_64B_EN
;
461 tbuf_ctrl
&= ~RBUF_64B_EN
;
462 rbuf_ctrl
&= ~RBUF_64B_EN
;
464 priv
->desc_64b_en
= desc_64b_en
;
466 bcmgenet_tbuf_ctrl_set(priv
, tbuf_ctrl
);
467 bcmgenet_rbuf_writel(priv
, rbuf_ctrl
, RBUF_CTRL
);
472 static int bcmgenet_set_features(struct net_device
*dev
,
473 netdev_features_t features
)
475 netdev_features_t changed
= features
^ dev
->features
;
476 netdev_features_t wanted
= dev
->wanted_features
;
479 if (changed
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
))
480 ret
= bcmgenet_set_tx_csum(dev
, wanted
);
481 if (changed
& (NETIF_F_RXCSUM
))
482 ret
= bcmgenet_set_rx_csum(dev
, wanted
);
487 static u32
bcmgenet_get_msglevel(struct net_device
*dev
)
489 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
491 return priv
->msg_enable
;
494 static void bcmgenet_set_msglevel(struct net_device
*dev
, u32 level
)
496 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
498 priv
->msg_enable
= level
;
501 /* standard ethtool support functions. */
502 enum bcmgenet_stat_type
{
503 BCMGENET_STAT_NETDEV
= -1,
504 BCMGENET_STAT_MIB_RX
,
505 BCMGENET_STAT_MIB_TX
,
511 struct bcmgenet_stats
{
512 char stat_string
[ETH_GSTRING_LEN
];
515 enum bcmgenet_stat_type type
;
516 /* reg offset from UMAC base for misc counters */
520 #define STAT_NETDEV(m) { \
521 .stat_string = __stringify(m), \
522 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
523 .stat_offset = offsetof(struct net_device_stats, m), \
524 .type = BCMGENET_STAT_NETDEV, \
527 #define STAT_GENET_MIB(str, m, _type) { \
528 .stat_string = str, \
529 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
530 .stat_offset = offsetof(struct bcmgenet_priv, m), \
534 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
535 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
536 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
537 #define STAT_GENET_SOFT_MIB(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_SOFT)
539 #define STAT_GENET_MISC(str, m, offset) { \
540 .stat_string = str, \
541 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
542 .stat_offset = offsetof(struct bcmgenet_priv, m), \
543 .type = BCMGENET_STAT_MISC, \
544 .reg_offset = offset, \
548 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
549 * between the end of TX stats and the beginning of the RX RUNT
551 #define BCMGENET_STAT_OFFSET 0xc
553 /* Hardware counters must be kept in sync because the order/offset
554 * is important here (order in structure declaration = order in hardware)
556 static const struct bcmgenet_stats bcmgenet_gstrings_stats
[] = {
558 STAT_NETDEV(rx_packets
),
559 STAT_NETDEV(tx_packets
),
560 STAT_NETDEV(rx_bytes
),
561 STAT_NETDEV(tx_bytes
),
562 STAT_NETDEV(rx_errors
),
563 STAT_NETDEV(tx_errors
),
564 STAT_NETDEV(rx_dropped
),
565 STAT_NETDEV(tx_dropped
),
566 STAT_NETDEV(multicast
),
567 /* UniMAC RSV counters */
568 STAT_GENET_MIB_RX("rx_64_octets", mib
.rx
.pkt_cnt
.cnt_64
),
569 STAT_GENET_MIB_RX("rx_65_127_oct", mib
.rx
.pkt_cnt
.cnt_127
),
570 STAT_GENET_MIB_RX("rx_128_255_oct", mib
.rx
.pkt_cnt
.cnt_255
),
571 STAT_GENET_MIB_RX("rx_256_511_oct", mib
.rx
.pkt_cnt
.cnt_511
),
572 STAT_GENET_MIB_RX("rx_512_1023_oct", mib
.rx
.pkt_cnt
.cnt_1023
),
573 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib
.rx
.pkt_cnt
.cnt_1518
),
574 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib
.rx
.pkt_cnt
.cnt_mgv
),
575 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib
.rx
.pkt_cnt
.cnt_2047
),
576 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib
.rx
.pkt_cnt
.cnt_4095
),
577 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib
.rx
.pkt_cnt
.cnt_9216
),
578 STAT_GENET_MIB_RX("rx_pkts", mib
.rx
.pkt
),
579 STAT_GENET_MIB_RX("rx_bytes", mib
.rx
.bytes
),
580 STAT_GENET_MIB_RX("rx_multicast", mib
.rx
.mca
),
581 STAT_GENET_MIB_RX("rx_broadcast", mib
.rx
.bca
),
582 STAT_GENET_MIB_RX("rx_fcs", mib
.rx
.fcs
),
583 STAT_GENET_MIB_RX("rx_control", mib
.rx
.cf
),
584 STAT_GENET_MIB_RX("rx_pause", mib
.rx
.pf
),
585 STAT_GENET_MIB_RX("rx_unknown", mib
.rx
.uo
),
586 STAT_GENET_MIB_RX("rx_align", mib
.rx
.aln
),
587 STAT_GENET_MIB_RX("rx_outrange", mib
.rx
.flr
),
588 STAT_GENET_MIB_RX("rx_code", mib
.rx
.cde
),
589 STAT_GENET_MIB_RX("rx_carrier", mib
.rx
.fcr
),
590 STAT_GENET_MIB_RX("rx_oversize", mib
.rx
.ovr
),
591 STAT_GENET_MIB_RX("rx_jabber", mib
.rx
.jbr
),
592 STAT_GENET_MIB_RX("rx_mtu_err", mib
.rx
.mtue
),
593 STAT_GENET_MIB_RX("rx_good_pkts", mib
.rx
.pok
),
594 STAT_GENET_MIB_RX("rx_unicast", mib
.rx
.uc
),
595 STAT_GENET_MIB_RX("rx_ppp", mib
.rx
.ppp
),
596 STAT_GENET_MIB_RX("rx_crc", mib
.rx
.rcrc
),
597 /* UniMAC TSV counters */
598 STAT_GENET_MIB_TX("tx_64_octets", mib
.tx
.pkt_cnt
.cnt_64
),
599 STAT_GENET_MIB_TX("tx_65_127_oct", mib
.tx
.pkt_cnt
.cnt_127
),
600 STAT_GENET_MIB_TX("tx_128_255_oct", mib
.tx
.pkt_cnt
.cnt_255
),
601 STAT_GENET_MIB_TX("tx_256_511_oct", mib
.tx
.pkt_cnt
.cnt_511
),
602 STAT_GENET_MIB_TX("tx_512_1023_oct", mib
.tx
.pkt_cnt
.cnt_1023
),
603 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib
.tx
.pkt_cnt
.cnt_1518
),
604 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib
.tx
.pkt_cnt
.cnt_mgv
),
605 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib
.tx
.pkt_cnt
.cnt_2047
),
606 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib
.tx
.pkt_cnt
.cnt_4095
),
607 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib
.tx
.pkt_cnt
.cnt_9216
),
608 STAT_GENET_MIB_TX("tx_pkts", mib
.tx
.pkts
),
609 STAT_GENET_MIB_TX("tx_multicast", mib
.tx
.mca
),
610 STAT_GENET_MIB_TX("tx_broadcast", mib
.tx
.bca
),
611 STAT_GENET_MIB_TX("tx_pause", mib
.tx
.pf
),
612 STAT_GENET_MIB_TX("tx_control", mib
.tx
.cf
),
613 STAT_GENET_MIB_TX("tx_fcs_err", mib
.tx
.fcs
),
614 STAT_GENET_MIB_TX("tx_oversize", mib
.tx
.ovr
),
615 STAT_GENET_MIB_TX("tx_defer", mib
.tx
.drf
),
616 STAT_GENET_MIB_TX("tx_excess_defer", mib
.tx
.edf
),
617 STAT_GENET_MIB_TX("tx_single_col", mib
.tx
.scl
),
618 STAT_GENET_MIB_TX("tx_multi_col", mib
.tx
.mcl
),
619 STAT_GENET_MIB_TX("tx_late_col", mib
.tx
.lcl
),
620 STAT_GENET_MIB_TX("tx_excess_col", mib
.tx
.ecl
),
621 STAT_GENET_MIB_TX("tx_frags", mib
.tx
.frg
),
622 STAT_GENET_MIB_TX("tx_total_col", mib
.tx
.ncl
),
623 STAT_GENET_MIB_TX("tx_jabber", mib
.tx
.jbr
),
624 STAT_GENET_MIB_TX("tx_bytes", mib
.tx
.bytes
),
625 STAT_GENET_MIB_TX("tx_good_pkts", mib
.tx
.pok
),
626 STAT_GENET_MIB_TX("tx_unicast", mib
.tx
.uc
),
627 /* UniMAC RUNT counters */
628 STAT_GENET_RUNT("rx_runt_pkts", mib
.rx_runt_cnt
),
629 STAT_GENET_RUNT("rx_runt_valid_fcs", mib
.rx_runt_fcs
),
630 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib
.rx_runt_fcs_align
),
631 STAT_GENET_RUNT("rx_runt_bytes", mib
.rx_runt_bytes
),
632 /* Misc UniMAC counters */
633 STAT_GENET_MISC("rbuf_ovflow_cnt", mib
.rbuf_ovflow_cnt
,
635 STAT_GENET_MISC("rbuf_err_cnt", mib
.rbuf_err_cnt
, UMAC_RBUF_ERR_CNT
),
636 STAT_GENET_MISC("mdf_err_cnt", mib
.mdf_err_cnt
, UMAC_MDF_ERR_CNT
),
637 STAT_GENET_SOFT_MIB("alloc_rx_buff_failed", mib
.alloc_rx_buff_failed
),
638 STAT_GENET_SOFT_MIB("rx_dma_failed", mib
.rx_dma_failed
),
639 STAT_GENET_SOFT_MIB("tx_dma_failed", mib
.tx_dma_failed
),
642 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
644 static void bcmgenet_get_drvinfo(struct net_device
*dev
,
645 struct ethtool_drvinfo
*info
)
647 strlcpy(info
->driver
, "bcmgenet", sizeof(info
->driver
));
648 strlcpy(info
->version
, "v2.0", sizeof(info
->version
));
649 info
->n_stats
= BCMGENET_STATS_LEN
;
652 static int bcmgenet_get_sset_count(struct net_device
*dev
, int string_set
)
654 switch (string_set
) {
656 return BCMGENET_STATS_LEN
;
662 static void bcmgenet_get_strings(struct net_device
*dev
, u32 stringset
,
669 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
670 memcpy(data
+ i
* ETH_GSTRING_LEN
,
671 bcmgenet_gstrings_stats
[i
].stat_string
,
678 static void bcmgenet_update_mib_counters(struct bcmgenet_priv
*priv
)
682 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
683 const struct bcmgenet_stats
*s
;
688 s
= &bcmgenet_gstrings_stats
[i
];
690 case BCMGENET_STAT_NETDEV
:
691 case BCMGENET_STAT_SOFT
:
693 case BCMGENET_STAT_MIB_RX
:
694 case BCMGENET_STAT_MIB_TX
:
695 case BCMGENET_STAT_RUNT
:
696 if (s
->type
!= BCMGENET_STAT_MIB_RX
)
697 offset
= BCMGENET_STAT_OFFSET
;
698 val
= bcmgenet_umac_readl(priv
,
699 UMAC_MIB_START
+ j
+ offset
);
701 case BCMGENET_STAT_MISC
:
702 val
= bcmgenet_umac_readl(priv
, s
->reg_offset
);
703 /* clear if overflowed */
705 bcmgenet_umac_writel(priv
, 0, s
->reg_offset
);
710 p
= (char *)priv
+ s
->stat_offset
;
715 static void bcmgenet_get_ethtool_stats(struct net_device
*dev
,
716 struct ethtool_stats
*stats
,
719 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
722 if (netif_running(dev
))
723 bcmgenet_update_mib_counters(priv
);
725 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
726 const struct bcmgenet_stats
*s
;
729 s
= &bcmgenet_gstrings_stats
[i
];
730 if (s
->type
== BCMGENET_STAT_NETDEV
)
731 p
= (char *)&dev
->stats
;
739 static void bcmgenet_eee_enable_set(struct net_device
*dev
, bool enable
)
741 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
742 u32 off
= priv
->hw_params
->tbuf_offset
+ TBUF_ENERGY_CTRL
;
745 if (enable
&& !priv
->clk_eee_enabled
) {
746 clk_prepare_enable(priv
->clk_eee
);
747 priv
->clk_eee_enabled
= true;
750 reg
= bcmgenet_umac_readl(priv
, UMAC_EEE_CTRL
);
755 bcmgenet_umac_writel(priv
, reg
, UMAC_EEE_CTRL
);
757 /* Enable EEE and switch to a 27Mhz clock automatically */
758 reg
= __raw_readl(priv
->base
+ off
);
760 reg
|= TBUF_EEE_EN
| TBUF_PM_EN
;
762 reg
&= ~(TBUF_EEE_EN
| TBUF_PM_EN
);
763 __raw_writel(reg
, priv
->base
+ off
);
765 /* Do the same for thing for RBUF */
766 reg
= bcmgenet_rbuf_readl(priv
, RBUF_ENERGY_CTRL
);
768 reg
|= RBUF_EEE_EN
| RBUF_PM_EN
;
770 reg
&= ~(RBUF_EEE_EN
| RBUF_PM_EN
);
771 bcmgenet_rbuf_writel(priv
, reg
, RBUF_ENERGY_CTRL
);
773 if (!enable
&& priv
->clk_eee_enabled
) {
774 clk_disable_unprepare(priv
->clk_eee
);
775 priv
->clk_eee_enabled
= false;
778 priv
->eee
.eee_enabled
= enable
;
779 priv
->eee
.eee_active
= enable
;
782 static int bcmgenet_get_eee(struct net_device
*dev
, struct ethtool_eee
*e
)
784 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
785 struct ethtool_eee
*p
= &priv
->eee
;
787 if (GENET_IS_V1(priv
))
790 e
->eee_enabled
= p
->eee_enabled
;
791 e
->eee_active
= p
->eee_active
;
792 e
->tx_lpi_timer
= bcmgenet_umac_readl(priv
, UMAC_EEE_LPI_TIMER
);
794 return phy_ethtool_get_eee(priv
->phydev
, e
);
797 static int bcmgenet_set_eee(struct net_device
*dev
, struct ethtool_eee
*e
)
799 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
800 struct ethtool_eee
*p
= &priv
->eee
;
803 if (GENET_IS_V1(priv
))
806 p
->eee_enabled
= e
->eee_enabled
;
808 if (!p
->eee_enabled
) {
809 bcmgenet_eee_enable_set(dev
, false);
811 ret
= phy_init_eee(priv
->phydev
, 0);
813 netif_err(priv
, hw
, dev
, "EEE initialization failed\n");
817 bcmgenet_umac_writel(priv
, e
->tx_lpi_timer
, UMAC_EEE_LPI_TIMER
);
818 bcmgenet_eee_enable_set(dev
, true);
821 return phy_ethtool_set_eee(priv
->phydev
, e
);
824 static int bcmgenet_nway_reset(struct net_device
*dev
)
826 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
828 return genphy_restart_aneg(priv
->phydev
);
831 /* standard ethtool support functions. */
832 static struct ethtool_ops bcmgenet_ethtool_ops
= {
833 .get_strings
= bcmgenet_get_strings
,
834 .get_sset_count
= bcmgenet_get_sset_count
,
835 .get_ethtool_stats
= bcmgenet_get_ethtool_stats
,
836 .get_settings
= bcmgenet_get_settings
,
837 .set_settings
= bcmgenet_set_settings
,
838 .get_drvinfo
= bcmgenet_get_drvinfo
,
839 .get_link
= ethtool_op_get_link
,
840 .get_msglevel
= bcmgenet_get_msglevel
,
841 .set_msglevel
= bcmgenet_set_msglevel
,
842 .get_wol
= bcmgenet_get_wol
,
843 .set_wol
= bcmgenet_set_wol
,
844 .get_eee
= bcmgenet_get_eee
,
845 .set_eee
= bcmgenet_set_eee
,
846 .nway_reset
= bcmgenet_nway_reset
,
849 /* Power down the unimac, based on mode. */
850 static int bcmgenet_power_down(struct bcmgenet_priv
*priv
,
851 enum bcmgenet_power_mode mode
)
857 case GENET_POWER_CABLE_SENSE
:
858 phy_detach(priv
->phydev
);
861 case GENET_POWER_WOL_MAGIC
:
862 ret
= bcmgenet_wol_power_down_cfg(priv
, mode
);
865 case GENET_POWER_PASSIVE
:
867 if (priv
->hw_params
->flags
& GENET_HAS_EXT
) {
868 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
869 reg
|= (EXT_PWR_DOWN_PHY
|
870 EXT_PWR_DOWN_DLL
| EXT_PWR_DOWN_BIAS
);
871 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
873 bcmgenet_phy_power_set(priv
->dev
, false);
883 static void bcmgenet_power_up(struct bcmgenet_priv
*priv
,
884 enum bcmgenet_power_mode mode
)
888 if (!(priv
->hw_params
->flags
& GENET_HAS_EXT
))
891 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
894 case GENET_POWER_PASSIVE
:
895 reg
&= ~(EXT_PWR_DOWN_DLL
| EXT_PWR_DOWN_PHY
|
898 case GENET_POWER_CABLE_SENSE
:
900 reg
|= EXT_PWR_DN_EN_LD
;
902 case GENET_POWER_WOL_MAGIC
:
903 bcmgenet_wol_power_up_cfg(priv
, mode
);
909 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
911 if (mode
== GENET_POWER_PASSIVE
)
912 bcmgenet_mii_reset(priv
->dev
);
915 /* ioctl handle special commands that are not present in ethtool. */
916 static int bcmgenet_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
918 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
921 if (!netif_running(dev
))
931 val
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
942 static struct enet_cb
*bcmgenet_get_txcb(struct bcmgenet_priv
*priv
,
943 struct bcmgenet_tx_ring
*ring
)
945 struct enet_cb
*tx_cb_ptr
;
947 tx_cb_ptr
= ring
->cbs
;
948 tx_cb_ptr
+= ring
->write_ptr
- ring
->cb_ptr
;
950 /* Advancing local write pointer */
951 if (ring
->write_ptr
== ring
->end_ptr
)
952 ring
->write_ptr
= ring
->cb_ptr
;
959 /* Simple helper to free a control block's resources */
960 static void bcmgenet_free_cb(struct enet_cb
*cb
)
962 dev_kfree_skb_any(cb
->skb
);
964 dma_unmap_addr_set(cb
, dma_addr
, 0);
967 static inline void bcmgenet_rx_ring16_int_disable(struct bcmgenet_rx_ring
*ring
)
969 bcmgenet_intrl2_0_writel(ring
->priv
, UMAC_IRQ_RXDMA_DONE
,
970 INTRL2_CPU_MASK_SET
);
973 static inline void bcmgenet_rx_ring16_int_enable(struct bcmgenet_rx_ring
*ring
)
975 bcmgenet_intrl2_0_writel(ring
->priv
, UMAC_IRQ_RXDMA_DONE
,
976 INTRL2_CPU_MASK_CLEAR
);
979 static inline void bcmgenet_rx_ring_int_disable(struct bcmgenet_rx_ring
*ring
)
981 bcmgenet_intrl2_1_writel(ring
->priv
,
982 1 << (UMAC_IRQ1_RX_INTR_SHIFT
+ ring
->index
),
983 INTRL2_CPU_MASK_SET
);
986 static inline void bcmgenet_rx_ring_int_enable(struct bcmgenet_rx_ring
*ring
)
988 bcmgenet_intrl2_1_writel(ring
->priv
,
989 1 << (UMAC_IRQ1_RX_INTR_SHIFT
+ ring
->index
),
990 INTRL2_CPU_MASK_CLEAR
);
993 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_tx_ring
*ring
)
995 bcmgenet_intrl2_0_writel(ring
->priv
, UMAC_IRQ_TXDMA_DONE
,
996 INTRL2_CPU_MASK_SET
);
999 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_tx_ring
*ring
)
1001 bcmgenet_intrl2_0_writel(ring
->priv
, UMAC_IRQ_TXDMA_DONE
,
1002 INTRL2_CPU_MASK_CLEAR
);
1005 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_tx_ring
*ring
)
1007 bcmgenet_intrl2_1_writel(ring
->priv
, 1 << ring
->index
,
1008 INTRL2_CPU_MASK_CLEAR
);
1011 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_tx_ring
*ring
)
1013 bcmgenet_intrl2_1_writel(ring
->priv
, 1 << ring
->index
,
1014 INTRL2_CPU_MASK_SET
);
1017 /* Unlocked version of the reclaim routine */
1018 static unsigned int __bcmgenet_tx_reclaim(struct net_device
*dev
,
1019 struct bcmgenet_tx_ring
*ring
)
1021 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1022 struct enet_cb
*tx_cb_ptr
;
1023 struct netdev_queue
*txq
;
1024 unsigned int pkts_compl
= 0;
1025 unsigned int c_index
;
1026 unsigned int txbds_ready
;
1027 unsigned int txbds_processed
= 0;
1029 /* Compute how many buffers are transmitted since last xmit call */
1030 c_index
= bcmgenet_tdma_ring_readl(priv
, ring
->index
, TDMA_CONS_INDEX
);
1031 c_index
&= DMA_C_INDEX_MASK
;
1033 if (likely(c_index
>= ring
->c_index
))
1034 txbds_ready
= c_index
- ring
->c_index
;
1036 txbds_ready
= (DMA_C_INDEX_MASK
+ 1) - ring
->c_index
+ c_index
;
1038 netif_dbg(priv
, tx_done
, dev
,
1039 "%s ring=%d old_c_index=%u c_index=%u txbds_ready=%u\n",
1040 __func__
, ring
->index
, ring
->c_index
, c_index
, txbds_ready
);
1042 /* Reclaim transmitted buffers */
1043 while (txbds_processed
< txbds_ready
) {
1044 tx_cb_ptr
= &priv
->tx_cbs
[ring
->clean_ptr
];
1045 if (tx_cb_ptr
->skb
) {
1047 dev
->stats
.tx_packets
++;
1048 dev
->stats
.tx_bytes
+= tx_cb_ptr
->skb
->len
;
1049 dma_unmap_single(&dev
->dev
,
1050 dma_unmap_addr(tx_cb_ptr
, dma_addr
),
1051 tx_cb_ptr
->skb
->len
,
1053 bcmgenet_free_cb(tx_cb_ptr
);
1054 } else if (dma_unmap_addr(tx_cb_ptr
, dma_addr
)) {
1055 dev
->stats
.tx_bytes
+=
1056 dma_unmap_len(tx_cb_ptr
, dma_len
);
1057 dma_unmap_page(&dev
->dev
,
1058 dma_unmap_addr(tx_cb_ptr
, dma_addr
),
1059 dma_unmap_len(tx_cb_ptr
, dma_len
),
1061 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, 0);
1065 if (likely(ring
->clean_ptr
< ring
->end_ptr
))
1068 ring
->clean_ptr
= ring
->cb_ptr
;
1071 ring
->free_bds
+= txbds_processed
;
1072 ring
->c_index
= (ring
->c_index
+ txbds_processed
) & DMA_C_INDEX_MASK
;
1074 if (ring
->free_bds
> (MAX_SKB_FRAGS
+ 1)) {
1075 txq
= netdev_get_tx_queue(dev
, ring
->queue
);
1076 if (netif_tx_queue_stopped(txq
))
1077 netif_tx_wake_queue(txq
);
1083 static unsigned int bcmgenet_tx_reclaim(struct net_device
*dev
,
1084 struct bcmgenet_tx_ring
*ring
)
1086 unsigned int released
;
1087 unsigned long flags
;
1089 spin_lock_irqsave(&ring
->lock
, flags
);
1090 released
= __bcmgenet_tx_reclaim(dev
, ring
);
1091 spin_unlock_irqrestore(&ring
->lock
, flags
);
1096 static int bcmgenet_tx_poll(struct napi_struct
*napi
, int budget
)
1098 struct bcmgenet_tx_ring
*ring
=
1099 container_of(napi
, struct bcmgenet_tx_ring
, napi
);
1100 unsigned int work_done
= 0;
1102 work_done
= bcmgenet_tx_reclaim(ring
->priv
->dev
, ring
);
1104 if (work_done
== 0) {
1105 napi_complete(napi
);
1106 ring
->int_enable(ring
);
1114 static void bcmgenet_tx_reclaim_all(struct net_device
*dev
)
1116 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1119 if (netif_is_multiqueue(dev
)) {
1120 for (i
= 0; i
< priv
->hw_params
->tx_queues
; i
++)
1121 bcmgenet_tx_reclaim(dev
, &priv
->tx_rings
[i
]);
1124 bcmgenet_tx_reclaim(dev
, &priv
->tx_rings
[DESC_INDEX
]);
1127 /* Transmits a single SKB (either head of a fragment or a single SKB)
1128 * caller must hold priv->lock
1130 static int bcmgenet_xmit_single(struct net_device
*dev
,
1131 struct sk_buff
*skb
,
1133 struct bcmgenet_tx_ring
*ring
)
1135 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1136 struct device
*kdev
= &priv
->pdev
->dev
;
1137 struct enet_cb
*tx_cb_ptr
;
1138 unsigned int skb_len
;
1143 tx_cb_ptr
= bcmgenet_get_txcb(priv
, ring
);
1145 if (unlikely(!tx_cb_ptr
))
1148 tx_cb_ptr
->skb
= skb
;
1150 skb_len
= skb_headlen(skb
) < ETH_ZLEN
? ETH_ZLEN
: skb_headlen(skb
);
1152 mapping
= dma_map_single(kdev
, skb
->data
, skb_len
, DMA_TO_DEVICE
);
1153 ret
= dma_mapping_error(kdev
, mapping
);
1155 priv
->mib
.tx_dma_failed
++;
1156 netif_err(priv
, tx_err
, dev
, "Tx DMA map failed\n");
1161 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, mapping
);
1162 dma_unmap_len_set(tx_cb_ptr
, dma_len
, skb
->len
);
1163 length_status
= (skb_len
<< DMA_BUFLENGTH_SHIFT
) | dma_desc_flags
|
1164 (priv
->hw_params
->qtag_mask
<< DMA_TX_QTAG_SHIFT
) |
1167 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1168 length_status
|= DMA_TX_DO_CSUM
;
1170 dmadesc_set(priv
, tx_cb_ptr
->bd_addr
, mapping
, length_status
);
1175 /* Transmit a SKB fragment */
1176 static int bcmgenet_xmit_frag(struct net_device
*dev
,
1179 struct bcmgenet_tx_ring
*ring
)
1181 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1182 struct device
*kdev
= &priv
->pdev
->dev
;
1183 struct enet_cb
*tx_cb_ptr
;
1187 tx_cb_ptr
= bcmgenet_get_txcb(priv
, ring
);
1189 if (unlikely(!tx_cb_ptr
))
1191 tx_cb_ptr
->skb
= NULL
;
1193 mapping
= skb_frag_dma_map(kdev
, frag
, 0,
1194 skb_frag_size(frag
), DMA_TO_DEVICE
);
1195 ret
= dma_mapping_error(kdev
, mapping
);
1197 priv
->mib
.tx_dma_failed
++;
1198 netif_err(priv
, tx_err
, dev
, "%s: Tx DMA map failed\n",
1203 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, mapping
);
1204 dma_unmap_len_set(tx_cb_ptr
, dma_len
, frag
->size
);
1206 dmadesc_set(priv
, tx_cb_ptr
->bd_addr
, mapping
,
1207 (frag
->size
<< DMA_BUFLENGTH_SHIFT
) | dma_desc_flags
|
1208 (priv
->hw_params
->qtag_mask
<< DMA_TX_QTAG_SHIFT
));
1213 /* Reallocate the SKB to put enough headroom in front of it and insert
1214 * the transmit checksum offsets in the descriptors
1216 static struct sk_buff
*bcmgenet_put_tx_csum(struct net_device
*dev
,
1217 struct sk_buff
*skb
)
1219 struct status_64
*status
= NULL
;
1220 struct sk_buff
*new_skb
;
1226 if (unlikely(skb_headroom(skb
) < sizeof(*status
))) {
1227 /* If 64 byte status block enabled, must make sure skb has
1228 * enough headroom for us to insert 64B status block.
1230 new_skb
= skb_realloc_headroom(skb
, sizeof(*status
));
1233 dev
->stats
.tx_dropped
++;
1239 skb_push(skb
, sizeof(*status
));
1240 status
= (struct status_64
*)skb
->data
;
1242 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1243 ip_ver
= htons(skb
->protocol
);
1246 ip_proto
= ip_hdr(skb
)->protocol
;
1249 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
1255 offset
= skb_checksum_start_offset(skb
) - sizeof(*status
);
1256 tx_csum_info
= (offset
<< STATUS_TX_CSUM_START_SHIFT
) |
1257 (offset
+ skb
->csum_offset
);
1259 /* Set the length valid bit for TCP and UDP and just set
1260 * the special UDP flag for IPv4, else just set to 0.
1262 if (ip_proto
== IPPROTO_TCP
|| ip_proto
== IPPROTO_UDP
) {
1263 tx_csum_info
|= STATUS_TX_CSUM_LV
;
1264 if (ip_proto
== IPPROTO_UDP
&& ip_ver
== ETH_P_IP
)
1265 tx_csum_info
|= STATUS_TX_CSUM_PROTO_UDP
;
1270 status
->tx_csum_info
= tx_csum_info
;
1276 static netdev_tx_t
bcmgenet_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1278 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1279 struct bcmgenet_tx_ring
*ring
= NULL
;
1280 struct netdev_queue
*txq
;
1281 unsigned long flags
= 0;
1282 int nr_frags
, index
;
1287 index
= skb_get_queue_mapping(skb
);
1288 /* Mapping strategy:
1289 * queue_mapping = 0, unclassified, packet xmited through ring16
1290 * queue_mapping = 1, goes to ring 0. (highest priority queue
1291 * queue_mapping = 2, goes to ring 1.
1292 * queue_mapping = 3, goes to ring 2.
1293 * queue_mapping = 4, goes to ring 3.
1300 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1301 ring
= &priv
->tx_rings
[index
];
1302 txq
= netdev_get_tx_queue(dev
, ring
->queue
);
1304 spin_lock_irqsave(&ring
->lock
, flags
);
1305 if (ring
->free_bds
<= nr_frags
+ 1) {
1306 netif_tx_stop_queue(txq
);
1307 netdev_err(dev
, "%s: tx ring %d full when queue %d awake\n",
1308 __func__
, index
, ring
->queue
);
1309 ret
= NETDEV_TX_BUSY
;
1313 if (skb_padto(skb
, ETH_ZLEN
)) {
1318 /* set the SKB transmit checksum */
1319 if (priv
->desc_64b_en
) {
1320 skb
= bcmgenet_put_tx_csum(dev
, skb
);
1327 dma_desc_flags
= DMA_SOP
;
1329 dma_desc_flags
|= DMA_EOP
;
1331 /* Transmit single SKB or head of fragment list */
1332 ret
= bcmgenet_xmit_single(dev
, skb
, dma_desc_flags
, ring
);
1339 for (i
= 0; i
< nr_frags
; i
++) {
1340 ret
= bcmgenet_xmit_frag(dev
,
1341 &skb_shinfo(skb
)->frags
[i
],
1342 (i
== nr_frags
- 1) ? DMA_EOP
: 0,
1350 skb_tx_timestamp(skb
);
1352 /* Decrement total BD count and advance our write pointer */
1353 ring
->free_bds
-= nr_frags
+ 1;
1354 ring
->prod_index
+= nr_frags
+ 1;
1355 ring
->prod_index
&= DMA_P_INDEX_MASK
;
1357 if (ring
->free_bds
<= (MAX_SKB_FRAGS
+ 1))
1358 netif_tx_stop_queue(txq
);
1360 if (!skb
->xmit_more
|| netif_xmit_stopped(txq
))
1361 /* Packets are ready, update producer index */
1362 bcmgenet_tdma_ring_writel(priv
, ring
->index
,
1363 ring
->prod_index
, TDMA_PROD_INDEX
);
1365 spin_unlock_irqrestore(&ring
->lock
, flags
);
1370 static struct sk_buff
*bcmgenet_rx_refill(struct bcmgenet_priv
*priv
,
1373 struct device
*kdev
= &priv
->pdev
->dev
;
1374 struct sk_buff
*skb
;
1375 struct sk_buff
*rx_skb
;
1378 /* Allocate a new Rx skb */
1379 skb
= netdev_alloc_skb(priv
->dev
, priv
->rx_buf_len
+ SKB_ALIGNMENT
);
1381 priv
->mib
.alloc_rx_buff_failed
++;
1382 netif_err(priv
, rx_err
, priv
->dev
,
1383 "%s: Rx skb allocation failed\n", __func__
);
1387 /* DMA-map the new Rx skb */
1388 mapping
= dma_map_single(kdev
, skb
->data
, priv
->rx_buf_len
,
1390 if (dma_mapping_error(kdev
, mapping
)) {
1391 priv
->mib
.rx_dma_failed
++;
1392 dev_kfree_skb_any(skb
);
1393 netif_err(priv
, rx_err
, priv
->dev
,
1394 "%s: Rx skb DMA mapping failed\n", __func__
);
1398 /* Grab the current Rx skb from the ring and DMA-unmap it */
1401 dma_unmap_single(kdev
, dma_unmap_addr(cb
, dma_addr
),
1402 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1404 /* Put the new Rx skb on the ring */
1406 dma_unmap_addr_set(cb
, dma_addr
, mapping
);
1407 dmadesc_set_addr(priv
, cb
->bd_addr
, mapping
);
1409 /* Return the current Rx skb to caller */
1413 /* bcmgenet_desc_rx - descriptor based rx process.
1414 * this could be called from bottom half, or from NAPI polling method.
1416 static unsigned int bcmgenet_desc_rx(struct bcmgenet_rx_ring
*ring
,
1417 unsigned int budget
)
1419 struct bcmgenet_priv
*priv
= ring
->priv
;
1420 struct net_device
*dev
= priv
->dev
;
1422 struct sk_buff
*skb
;
1423 u32 dma_length_status
;
1424 unsigned long dma_flag
;
1426 unsigned int rxpktprocessed
= 0, rxpkttoprocess
;
1427 unsigned int p_index
;
1428 unsigned int discards
;
1429 unsigned int chksum_ok
= 0;
1431 p_index
= bcmgenet_rdma_ring_readl(priv
, ring
->index
, RDMA_PROD_INDEX
);
1433 discards
= (p_index
>> DMA_P_INDEX_DISCARD_CNT_SHIFT
) &
1434 DMA_P_INDEX_DISCARD_CNT_MASK
;
1435 if (discards
> ring
->old_discards
) {
1436 discards
= discards
- ring
->old_discards
;
1437 dev
->stats
.rx_missed_errors
+= discards
;
1438 dev
->stats
.rx_errors
+= discards
;
1439 ring
->old_discards
+= discards
;
1441 /* Clear HW register when we reach 75% of maximum 0xFFFF */
1442 if (ring
->old_discards
>= 0xC000) {
1443 ring
->old_discards
= 0;
1444 bcmgenet_rdma_ring_writel(priv
, ring
->index
, 0,
1449 p_index
&= DMA_P_INDEX_MASK
;
1451 if (likely(p_index
>= ring
->c_index
))
1452 rxpkttoprocess
= p_index
- ring
->c_index
;
1454 rxpkttoprocess
= (DMA_C_INDEX_MASK
+ 1) - ring
->c_index
+
1457 netif_dbg(priv
, rx_status
, dev
,
1458 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess
);
1460 while ((rxpktprocessed
< rxpkttoprocess
) &&
1461 (rxpktprocessed
< budget
)) {
1462 cb
= &priv
->rx_cbs
[ring
->read_ptr
];
1463 skb
= bcmgenet_rx_refill(priv
, cb
);
1465 if (unlikely(!skb
)) {
1466 dev
->stats
.rx_dropped
++;
1470 if (!priv
->desc_64b_en
) {
1472 dmadesc_get_length_status(priv
, cb
->bd_addr
);
1474 struct status_64
*status
;
1476 status
= (struct status_64
*)skb
->data
;
1477 dma_length_status
= status
->length_status
;
1480 /* DMA flags and length are still valid no matter how
1481 * we got the Receive Status Vector (64B RSB or register)
1483 dma_flag
= dma_length_status
& 0xffff;
1484 len
= dma_length_status
>> DMA_BUFLENGTH_SHIFT
;
1486 netif_dbg(priv
, rx_status
, dev
,
1487 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1488 __func__
, p_index
, ring
->c_index
,
1489 ring
->read_ptr
, dma_length_status
);
1491 if (unlikely(!(dma_flag
& DMA_EOP
) || !(dma_flag
& DMA_SOP
))) {
1492 netif_err(priv
, rx_status
, dev
,
1493 "dropping fragmented packet!\n");
1494 dev
->stats
.rx_errors
++;
1495 dev_kfree_skb_any(skb
);
1500 if (unlikely(dma_flag
& (DMA_RX_CRC_ERROR
|
1505 netif_err(priv
, rx_status
, dev
, "dma_flag=0x%x\n",
1506 (unsigned int)dma_flag
);
1507 if (dma_flag
& DMA_RX_CRC_ERROR
)
1508 dev
->stats
.rx_crc_errors
++;
1509 if (dma_flag
& DMA_RX_OV
)
1510 dev
->stats
.rx_over_errors
++;
1511 if (dma_flag
& DMA_RX_NO
)
1512 dev
->stats
.rx_frame_errors
++;
1513 if (dma_flag
& DMA_RX_LG
)
1514 dev
->stats
.rx_length_errors
++;
1515 dev
->stats
.rx_errors
++;
1516 dev_kfree_skb_any(skb
);
1518 } /* error packet */
1520 chksum_ok
= (dma_flag
& priv
->dma_rx_chk_bit
) &&
1521 priv
->desc_rxchk_en
;
1524 if (priv
->desc_64b_en
) {
1529 if (likely(chksum_ok
))
1530 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1532 /* remove hardware 2bytes added for IP alignment */
1536 if (priv
->crc_fwd_en
) {
1537 skb_trim(skb
, len
- ETH_FCS_LEN
);
1541 /*Finish setting up the received SKB and send it to the kernel*/
1542 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
1543 dev
->stats
.rx_packets
++;
1544 dev
->stats
.rx_bytes
+= len
;
1545 if (dma_flag
& DMA_RX_MULT
)
1546 dev
->stats
.multicast
++;
1549 napi_gro_receive(&ring
->napi
, skb
);
1550 netif_dbg(priv
, rx_status
, dev
, "pushed up to kernel\n");
1554 if (likely(ring
->read_ptr
< ring
->end_ptr
))
1557 ring
->read_ptr
= ring
->cb_ptr
;
1559 ring
->c_index
= (ring
->c_index
+ 1) & DMA_C_INDEX_MASK
;
1560 bcmgenet_rdma_ring_writel(priv
, ring
->index
, ring
->c_index
, RDMA_CONS_INDEX
);
1563 return rxpktprocessed
;
1566 /* Rx NAPI polling method */
1567 static int bcmgenet_rx_poll(struct napi_struct
*napi
, int budget
)
1569 struct bcmgenet_rx_ring
*ring
= container_of(napi
,
1570 struct bcmgenet_rx_ring
, napi
);
1571 unsigned int work_done
;
1573 work_done
= bcmgenet_desc_rx(ring
, budget
);
1575 if (work_done
< budget
) {
1576 napi_complete(napi
);
1577 ring
->int_enable(ring
);
1583 /* Assign skb to RX DMA descriptor. */
1584 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv
*priv
,
1585 struct bcmgenet_rx_ring
*ring
)
1588 struct sk_buff
*skb
;
1591 netif_dbg(priv
, hw
, priv
->dev
, "%s\n", __func__
);
1593 /* loop here for each buffer needing assign */
1594 for (i
= 0; i
< ring
->size
; i
++) {
1596 skb
= bcmgenet_rx_refill(priv
, cb
);
1598 dev_kfree_skb_any(skb
);
1606 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv
*priv
)
1611 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
1612 cb
= &priv
->rx_cbs
[i
];
1614 if (dma_unmap_addr(cb
, dma_addr
)) {
1615 dma_unmap_single(&priv
->dev
->dev
,
1616 dma_unmap_addr(cb
, dma_addr
),
1617 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1618 dma_unmap_addr_set(cb
, dma_addr
, 0);
1622 bcmgenet_free_cb(cb
);
1626 static void umac_enable_set(struct bcmgenet_priv
*priv
, u32 mask
, bool enable
)
1630 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
1635 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
1637 /* UniMAC stops on a packet boundary, wait for a full-size packet
1641 usleep_range(1000, 2000);
1644 static int reset_umac(struct bcmgenet_priv
*priv
)
1646 struct device
*kdev
= &priv
->pdev
->dev
;
1647 unsigned int timeout
= 0;
1650 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1651 bcmgenet_rbuf_ctrl_set(priv
, 0);
1654 /* disable MAC while updating its registers */
1655 bcmgenet_umac_writel(priv
, 0, UMAC_CMD
);
1657 /* issue soft reset, wait for it to complete */
1658 bcmgenet_umac_writel(priv
, CMD_SW_RESET
, UMAC_CMD
);
1659 while (timeout
++ < 1000) {
1660 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
1661 if (!(reg
& CMD_SW_RESET
))
1667 if (timeout
== 1000) {
1669 "timeout waiting for MAC to come out of reset\n");
1676 static void bcmgenet_intr_disable(struct bcmgenet_priv
*priv
)
1678 /* Mask all interrupts.*/
1679 bcmgenet_intrl2_0_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_MASK_SET
);
1680 bcmgenet_intrl2_0_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_CLEAR
);
1681 bcmgenet_intrl2_0_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1682 bcmgenet_intrl2_1_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_MASK_SET
);
1683 bcmgenet_intrl2_1_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_CLEAR
);
1684 bcmgenet_intrl2_1_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1687 static int init_umac(struct bcmgenet_priv
*priv
)
1689 struct device
*kdev
= &priv
->pdev
->dev
;
1692 u32 int0_enable
= 0;
1693 u32 int1_enable
= 0;
1696 dev_dbg(&priv
->pdev
->dev
, "bcmgenet: init_umac\n");
1698 ret
= reset_umac(priv
);
1702 bcmgenet_umac_writel(priv
, 0, UMAC_CMD
);
1703 /* clear tx/rx counter */
1704 bcmgenet_umac_writel(priv
,
1705 MIB_RESET_RX
| MIB_RESET_TX
| MIB_RESET_RUNT
,
1707 bcmgenet_umac_writel(priv
, 0, UMAC_MIB_CTRL
);
1709 bcmgenet_umac_writel(priv
, ENET_MAX_MTU_SIZE
, UMAC_MAX_FRAME_LEN
);
1711 /* init rx registers, enable ip header optimization */
1712 reg
= bcmgenet_rbuf_readl(priv
, RBUF_CTRL
);
1713 reg
|= RBUF_ALIGN_2B
;
1714 bcmgenet_rbuf_writel(priv
, reg
, RBUF_CTRL
);
1716 if (!GENET_IS_V1(priv
) && !GENET_IS_V2(priv
))
1717 bcmgenet_rbuf_writel(priv
, 1, RBUF_TBUF_SIZE_CTRL
);
1719 bcmgenet_intr_disable(priv
);
1721 /* Enable Rx default queue 16 interrupts */
1722 int0_enable
|= UMAC_IRQ_RXDMA_DONE
;
1724 /* Enable Tx default queue 16 interrupts */
1725 int0_enable
|= UMAC_IRQ_TXDMA_DONE
;
1727 /* Monitor cable plug/unplugged event for internal PHY */
1728 if (phy_is_internal(priv
->phydev
)) {
1729 int0_enable
|= UMAC_IRQ_LINK_EVENT
;
1730 } else if (priv
->ext_phy
) {
1731 int0_enable
|= UMAC_IRQ_LINK_EVENT
;
1732 } else if (priv
->phy_interface
== PHY_INTERFACE_MODE_MOCA
) {
1733 if (priv
->hw_params
->flags
& GENET_HAS_MOCA_LINK_DET
)
1734 int0_enable
|= UMAC_IRQ_LINK_EVENT
;
1736 reg
= bcmgenet_bp_mc_get(priv
);
1737 reg
|= BIT(priv
->hw_params
->bp_in_en_shift
);
1739 /* bp_mask: back pressure mask */
1740 if (netif_is_multiqueue(priv
->dev
))
1741 reg
|= priv
->hw_params
->bp_in_mask
;
1743 reg
&= ~priv
->hw_params
->bp_in_mask
;
1744 bcmgenet_bp_mc_set(priv
, reg
);
1747 /* Enable MDIO interrupts on GENET v3+ */
1748 if (priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
)
1749 int0_enable
|= (UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
);
1751 /* Enable Rx priority queue interrupts */
1752 for (i
= 0; i
< priv
->hw_params
->rx_queues
; ++i
)
1753 int1_enable
|= (1 << (UMAC_IRQ1_RX_INTR_SHIFT
+ i
));
1755 /* Enable Tx priority queue interrupts */
1756 for (i
= 0; i
< priv
->hw_params
->tx_queues
; ++i
)
1757 int1_enable
|= (1 << i
);
1759 bcmgenet_intrl2_0_writel(priv
, int0_enable
, INTRL2_CPU_MASK_CLEAR
);
1760 bcmgenet_intrl2_1_writel(priv
, int1_enable
, INTRL2_CPU_MASK_CLEAR
);
1762 /* Enable rx/tx engine.*/
1763 dev_dbg(kdev
, "done init umac\n");
1768 /* Initialize a Tx ring along with corresponding hardware registers */
1769 static void bcmgenet_init_tx_ring(struct bcmgenet_priv
*priv
,
1770 unsigned int index
, unsigned int size
,
1771 unsigned int start_ptr
, unsigned int end_ptr
)
1773 struct bcmgenet_tx_ring
*ring
= &priv
->tx_rings
[index
];
1774 u32 words_per_bd
= WORDS_PER_BD(priv
);
1775 u32 flow_period_val
= 0;
1777 spin_lock_init(&ring
->lock
);
1779 ring
->index
= index
;
1780 if (index
== DESC_INDEX
) {
1782 ring
->int_enable
= bcmgenet_tx_ring16_int_enable
;
1783 ring
->int_disable
= bcmgenet_tx_ring16_int_disable
;
1785 ring
->queue
= index
+ 1;
1786 ring
->int_enable
= bcmgenet_tx_ring_int_enable
;
1787 ring
->int_disable
= bcmgenet_tx_ring_int_disable
;
1789 ring
->cbs
= priv
->tx_cbs
+ start_ptr
;
1791 ring
->clean_ptr
= start_ptr
;
1793 ring
->free_bds
= size
;
1794 ring
->write_ptr
= start_ptr
;
1795 ring
->cb_ptr
= start_ptr
;
1796 ring
->end_ptr
= end_ptr
- 1;
1797 ring
->prod_index
= 0;
1799 /* Set flow period for ring != 16 */
1800 if (index
!= DESC_INDEX
)
1801 flow_period_val
= ENET_MAX_MTU_SIZE
<< 16;
1803 bcmgenet_tdma_ring_writel(priv
, index
, 0, TDMA_PROD_INDEX
);
1804 bcmgenet_tdma_ring_writel(priv
, index
, 0, TDMA_CONS_INDEX
);
1805 bcmgenet_tdma_ring_writel(priv
, index
, 1, DMA_MBUF_DONE_THRESH
);
1806 /* Disable rate control for now */
1807 bcmgenet_tdma_ring_writel(priv
, index
, flow_period_val
,
1809 bcmgenet_tdma_ring_writel(priv
, index
,
1810 ((size
<< DMA_RING_SIZE_SHIFT
) |
1811 RX_BUF_LENGTH
), DMA_RING_BUF_SIZE
);
1813 /* Set start and end address, read and write pointers */
1814 bcmgenet_tdma_ring_writel(priv
, index
, start_ptr
* words_per_bd
,
1816 bcmgenet_tdma_ring_writel(priv
, index
, start_ptr
* words_per_bd
,
1818 bcmgenet_tdma_ring_writel(priv
, index
, start_ptr
* words_per_bd
,
1820 bcmgenet_tdma_ring_writel(priv
, index
, end_ptr
* words_per_bd
- 1,
1824 /* Initialize a RDMA ring */
1825 static int bcmgenet_init_rx_ring(struct bcmgenet_priv
*priv
,
1826 unsigned int index
, unsigned int size
,
1827 unsigned int start_ptr
, unsigned int end_ptr
)
1829 struct bcmgenet_rx_ring
*ring
= &priv
->rx_rings
[index
];
1830 u32 words_per_bd
= WORDS_PER_BD(priv
);
1834 ring
->index
= index
;
1835 if (index
== DESC_INDEX
) {
1836 ring
->int_enable
= bcmgenet_rx_ring16_int_enable
;
1837 ring
->int_disable
= bcmgenet_rx_ring16_int_disable
;
1839 ring
->int_enable
= bcmgenet_rx_ring_int_enable
;
1840 ring
->int_disable
= bcmgenet_rx_ring_int_disable
;
1842 ring
->cbs
= priv
->rx_cbs
+ start_ptr
;
1845 ring
->read_ptr
= start_ptr
;
1846 ring
->cb_ptr
= start_ptr
;
1847 ring
->end_ptr
= end_ptr
- 1;
1849 ret
= bcmgenet_alloc_rx_buffers(priv
, ring
);
1853 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_PROD_INDEX
);
1854 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_CONS_INDEX
);
1855 bcmgenet_rdma_ring_writel(priv
, index
, 1, DMA_MBUF_DONE_THRESH
);
1856 bcmgenet_rdma_ring_writel(priv
, index
,
1857 ((size
<< DMA_RING_SIZE_SHIFT
) |
1858 RX_BUF_LENGTH
), DMA_RING_BUF_SIZE
);
1859 bcmgenet_rdma_ring_writel(priv
, index
,
1860 (DMA_FC_THRESH_LO
<<
1861 DMA_XOFF_THRESHOLD_SHIFT
) |
1862 DMA_FC_THRESH_HI
, RDMA_XON_XOFF_THRESH
);
1864 /* Set start and end address, read and write pointers */
1865 bcmgenet_rdma_ring_writel(priv
, index
, start_ptr
* words_per_bd
,
1867 bcmgenet_rdma_ring_writel(priv
, index
, start_ptr
* words_per_bd
,
1869 bcmgenet_rdma_ring_writel(priv
, index
, start_ptr
* words_per_bd
,
1871 bcmgenet_rdma_ring_writel(priv
, index
, end_ptr
* words_per_bd
- 1,
1877 static void bcmgenet_init_tx_napi(struct bcmgenet_priv
*priv
)
1880 struct bcmgenet_tx_ring
*ring
;
1882 for (i
= 0; i
< priv
->hw_params
->tx_queues
; ++i
) {
1883 ring
= &priv
->tx_rings
[i
];
1884 netif_napi_add(priv
->dev
, &ring
->napi
, bcmgenet_tx_poll
, 64);
1887 ring
= &priv
->tx_rings
[DESC_INDEX
];
1888 netif_napi_add(priv
->dev
, &ring
->napi
, bcmgenet_tx_poll
, 64);
1891 static void bcmgenet_enable_tx_napi(struct bcmgenet_priv
*priv
)
1894 struct bcmgenet_tx_ring
*ring
;
1896 for (i
= 0; i
< priv
->hw_params
->tx_queues
; ++i
) {
1897 ring
= &priv
->tx_rings
[i
];
1898 napi_enable(&ring
->napi
);
1901 ring
= &priv
->tx_rings
[DESC_INDEX
];
1902 napi_enable(&ring
->napi
);
1905 static void bcmgenet_disable_tx_napi(struct bcmgenet_priv
*priv
)
1908 struct bcmgenet_tx_ring
*ring
;
1910 for (i
= 0; i
< priv
->hw_params
->tx_queues
; ++i
) {
1911 ring
= &priv
->tx_rings
[i
];
1912 napi_disable(&ring
->napi
);
1915 ring
= &priv
->tx_rings
[DESC_INDEX
];
1916 napi_disable(&ring
->napi
);
1919 static void bcmgenet_fini_tx_napi(struct bcmgenet_priv
*priv
)
1922 struct bcmgenet_tx_ring
*ring
;
1924 for (i
= 0; i
< priv
->hw_params
->tx_queues
; ++i
) {
1925 ring
= &priv
->tx_rings
[i
];
1926 netif_napi_del(&ring
->napi
);
1929 ring
= &priv
->tx_rings
[DESC_INDEX
];
1930 netif_napi_del(&ring
->napi
);
1933 /* Initialize Tx queues
1935 * Queues 0-3 are priority-based, each one has 32 descriptors,
1936 * with queue 0 being the highest priority queue.
1938 * Queue 16 is the default Tx queue with
1939 * GENET_Q16_TX_BD_CNT = 256 - 4 * 32 = 128 descriptors.
1941 * The transmit control block pool is then partitioned as follows:
1942 * - Tx queue 0 uses tx_cbs[0..31]
1943 * - Tx queue 1 uses tx_cbs[32..63]
1944 * - Tx queue 2 uses tx_cbs[64..95]
1945 * - Tx queue 3 uses tx_cbs[96..127]
1946 * - Tx queue 16 uses tx_cbs[128..255]
1948 static void bcmgenet_init_tx_queues(struct net_device
*dev
)
1950 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1952 u32 dma_ctrl
, ring_cfg
;
1953 u32 dma_priority
[3] = {0, 0, 0};
1955 dma_ctrl
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1956 dma_enable
= dma_ctrl
& DMA_EN
;
1957 dma_ctrl
&= ~DMA_EN
;
1958 bcmgenet_tdma_writel(priv
, dma_ctrl
, DMA_CTRL
);
1963 /* Enable strict priority arbiter mode */
1964 bcmgenet_tdma_writel(priv
, DMA_ARBITER_SP
, DMA_ARB_CTRL
);
1966 /* Initialize Tx priority queues */
1967 for (i
= 0; i
< priv
->hw_params
->tx_queues
; i
++) {
1968 bcmgenet_init_tx_ring(priv
, i
, priv
->hw_params
->tx_bds_per_q
,
1969 i
* priv
->hw_params
->tx_bds_per_q
,
1970 (i
+ 1) * priv
->hw_params
->tx_bds_per_q
);
1971 ring_cfg
|= (1 << i
);
1972 dma_ctrl
|= (1 << (i
+ DMA_RING_BUF_EN_SHIFT
));
1973 dma_priority
[DMA_PRIO_REG_INDEX(i
)] |=
1974 ((GENET_Q0_PRIORITY
+ i
) << DMA_PRIO_REG_SHIFT(i
));
1977 /* Initialize Tx default queue 16 */
1978 bcmgenet_init_tx_ring(priv
, DESC_INDEX
, GENET_Q16_TX_BD_CNT
,
1979 priv
->hw_params
->tx_queues
*
1980 priv
->hw_params
->tx_bds_per_q
,
1982 ring_cfg
|= (1 << DESC_INDEX
);
1983 dma_ctrl
|= (1 << (DESC_INDEX
+ DMA_RING_BUF_EN_SHIFT
));
1984 dma_priority
[DMA_PRIO_REG_INDEX(DESC_INDEX
)] |=
1985 ((GENET_Q0_PRIORITY
+ priv
->hw_params
->tx_queues
) <<
1986 DMA_PRIO_REG_SHIFT(DESC_INDEX
));
1988 /* Set Tx queue priorities */
1989 bcmgenet_tdma_writel(priv
, dma_priority
[0], DMA_PRIORITY_0
);
1990 bcmgenet_tdma_writel(priv
, dma_priority
[1], DMA_PRIORITY_1
);
1991 bcmgenet_tdma_writel(priv
, dma_priority
[2], DMA_PRIORITY_2
);
1993 /* Initialize Tx NAPI */
1994 bcmgenet_init_tx_napi(priv
);
1996 /* Enable Tx queues */
1997 bcmgenet_tdma_writel(priv
, ring_cfg
, DMA_RING_CFG
);
2002 bcmgenet_tdma_writel(priv
, dma_ctrl
, DMA_CTRL
);
2005 static void bcmgenet_init_rx_napi(struct bcmgenet_priv
*priv
)
2008 struct bcmgenet_rx_ring
*ring
;
2010 for (i
= 0; i
< priv
->hw_params
->rx_queues
; ++i
) {
2011 ring
= &priv
->rx_rings
[i
];
2012 netif_napi_add(priv
->dev
, &ring
->napi
, bcmgenet_rx_poll
, 64);
2015 ring
= &priv
->rx_rings
[DESC_INDEX
];
2016 netif_napi_add(priv
->dev
, &ring
->napi
, bcmgenet_rx_poll
, 64);
2019 static void bcmgenet_enable_rx_napi(struct bcmgenet_priv
*priv
)
2022 struct bcmgenet_rx_ring
*ring
;
2024 for (i
= 0; i
< priv
->hw_params
->rx_queues
; ++i
) {
2025 ring
= &priv
->rx_rings
[i
];
2026 napi_enable(&ring
->napi
);
2029 ring
= &priv
->rx_rings
[DESC_INDEX
];
2030 napi_enable(&ring
->napi
);
2033 static void bcmgenet_disable_rx_napi(struct bcmgenet_priv
*priv
)
2036 struct bcmgenet_rx_ring
*ring
;
2038 for (i
= 0; i
< priv
->hw_params
->rx_queues
; ++i
) {
2039 ring
= &priv
->rx_rings
[i
];
2040 napi_disable(&ring
->napi
);
2043 ring
= &priv
->rx_rings
[DESC_INDEX
];
2044 napi_disable(&ring
->napi
);
2047 static void bcmgenet_fini_rx_napi(struct bcmgenet_priv
*priv
)
2050 struct bcmgenet_rx_ring
*ring
;
2052 for (i
= 0; i
< priv
->hw_params
->rx_queues
; ++i
) {
2053 ring
= &priv
->rx_rings
[i
];
2054 netif_napi_del(&ring
->napi
);
2057 ring
= &priv
->rx_rings
[DESC_INDEX
];
2058 netif_napi_del(&ring
->napi
);
2061 /* Initialize Rx queues
2063 * Queues 0-15 are priority queues. Hardware Filtering Block (HFB) can be
2064 * used to direct traffic to these queues.
2066 * Queue 16 is the default Rx queue with GENET_Q16_RX_BD_CNT descriptors.
2068 static int bcmgenet_init_rx_queues(struct net_device
*dev
)
2070 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2077 dma_ctrl
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2078 dma_enable
= dma_ctrl
& DMA_EN
;
2079 dma_ctrl
&= ~DMA_EN
;
2080 bcmgenet_rdma_writel(priv
, dma_ctrl
, DMA_CTRL
);
2085 /* Initialize Rx priority queues */
2086 for (i
= 0; i
< priv
->hw_params
->rx_queues
; i
++) {
2087 ret
= bcmgenet_init_rx_ring(priv
, i
,
2088 priv
->hw_params
->rx_bds_per_q
,
2089 i
* priv
->hw_params
->rx_bds_per_q
,
2091 priv
->hw_params
->rx_bds_per_q
);
2095 ring_cfg
|= (1 << i
);
2096 dma_ctrl
|= (1 << (i
+ DMA_RING_BUF_EN_SHIFT
));
2099 /* Initialize Rx default queue 16 */
2100 ret
= bcmgenet_init_rx_ring(priv
, DESC_INDEX
, GENET_Q16_RX_BD_CNT
,
2101 priv
->hw_params
->rx_queues
*
2102 priv
->hw_params
->rx_bds_per_q
,
2107 ring_cfg
|= (1 << DESC_INDEX
);
2108 dma_ctrl
|= (1 << (DESC_INDEX
+ DMA_RING_BUF_EN_SHIFT
));
2110 /* Initialize Rx NAPI */
2111 bcmgenet_init_rx_napi(priv
);
2114 bcmgenet_rdma_writel(priv
, ring_cfg
, DMA_RING_CFG
);
2116 /* Configure ring as descriptor ring and re-enable DMA if enabled */
2119 bcmgenet_rdma_writel(priv
, dma_ctrl
, DMA_CTRL
);
2124 static int bcmgenet_dma_teardown(struct bcmgenet_priv
*priv
)
2132 /* Disable TDMA to stop add more frames in TX DMA */
2133 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2135 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2137 /* Check TDMA status register to confirm TDMA is disabled */
2138 while (timeout
++ < DMA_TIMEOUT_VAL
) {
2139 reg
= bcmgenet_tdma_readl(priv
, DMA_STATUS
);
2140 if (reg
& DMA_DISABLED
)
2146 if (timeout
== DMA_TIMEOUT_VAL
) {
2147 netdev_warn(priv
->dev
, "Timed out while disabling TX DMA\n");
2151 /* Wait 10ms for packet drain in both tx and rx dma */
2152 usleep_range(10000, 20000);
2155 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2157 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2160 /* Check RDMA status register to confirm RDMA is disabled */
2161 while (timeout
++ < DMA_TIMEOUT_VAL
) {
2162 reg
= bcmgenet_rdma_readl(priv
, DMA_STATUS
);
2163 if (reg
& DMA_DISABLED
)
2169 if (timeout
== DMA_TIMEOUT_VAL
) {
2170 netdev_warn(priv
->dev
, "Timed out while disabling RX DMA\n");
2175 for (i
= 0; i
< priv
->hw_params
->rx_queues
; i
++)
2176 dma_ctrl
|= (1 << (i
+ DMA_RING_BUF_EN_SHIFT
));
2177 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2179 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2182 for (i
= 0; i
< priv
->hw_params
->tx_queues
; i
++)
2183 dma_ctrl
|= (1 << (i
+ DMA_RING_BUF_EN_SHIFT
));
2184 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2186 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2191 static void bcmgenet_fini_dma(struct bcmgenet_priv
*priv
)
2195 bcmgenet_fini_rx_napi(priv
);
2196 bcmgenet_fini_tx_napi(priv
);
2199 bcmgenet_dma_teardown(priv
);
2201 for (i
= 0; i
< priv
->num_tx_bds
; i
++) {
2202 if (priv
->tx_cbs
[i
].skb
!= NULL
) {
2203 dev_kfree_skb(priv
->tx_cbs
[i
].skb
);
2204 priv
->tx_cbs
[i
].skb
= NULL
;
2208 bcmgenet_free_rx_buffers(priv
);
2209 kfree(priv
->rx_cbs
);
2210 kfree(priv
->tx_cbs
);
2213 /* init_edma: Initialize DMA control register */
2214 static int bcmgenet_init_dma(struct bcmgenet_priv
*priv
)
2220 netif_dbg(priv
, hw
, priv
->dev
, "%s\n", __func__
);
2222 /* Initialize common Rx ring structures */
2223 priv
->rx_bds
= priv
->base
+ priv
->hw_params
->rdma_offset
;
2224 priv
->num_rx_bds
= TOTAL_DESC
;
2225 priv
->rx_cbs
= kcalloc(priv
->num_rx_bds
, sizeof(struct enet_cb
),
2230 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
2231 cb
= priv
->rx_cbs
+ i
;
2232 cb
->bd_addr
= priv
->rx_bds
+ i
* DMA_DESC_SIZE
;
2235 /* Initialize common TX ring structures */
2236 priv
->tx_bds
= priv
->base
+ priv
->hw_params
->tdma_offset
;
2237 priv
->num_tx_bds
= TOTAL_DESC
;
2238 priv
->tx_cbs
= kcalloc(priv
->num_tx_bds
, sizeof(struct enet_cb
),
2240 if (!priv
->tx_cbs
) {
2241 kfree(priv
->rx_cbs
);
2245 for (i
= 0; i
< priv
->num_tx_bds
; i
++) {
2246 cb
= priv
->tx_cbs
+ i
;
2247 cb
->bd_addr
= priv
->tx_bds
+ i
* DMA_DESC_SIZE
;
2251 bcmgenet_rdma_writel(priv
, DMA_MAX_BURST_LENGTH
, DMA_SCB_BURST_SIZE
);
2253 /* Initialize Rx queues */
2254 ret
= bcmgenet_init_rx_queues(priv
->dev
);
2256 netdev_err(priv
->dev
, "failed to initialize Rx queues\n");
2257 bcmgenet_free_rx_buffers(priv
);
2258 kfree(priv
->rx_cbs
);
2259 kfree(priv
->tx_cbs
);
2264 bcmgenet_tdma_writel(priv
, DMA_MAX_BURST_LENGTH
, DMA_SCB_BURST_SIZE
);
2266 /* Initialize Tx queues */
2267 bcmgenet_init_tx_queues(priv
->dev
);
2272 /* Interrupt bottom half */
2273 static void bcmgenet_irq_task(struct work_struct
*work
)
2275 struct bcmgenet_priv
*priv
= container_of(
2276 work
, struct bcmgenet_priv
, bcmgenet_irq_work
);
2278 netif_dbg(priv
, intr
, priv
->dev
, "%s\n", __func__
);
2280 if (priv
->irq0_stat
& UMAC_IRQ_MPD_R
) {
2281 priv
->irq0_stat
&= ~UMAC_IRQ_MPD_R
;
2282 netif_dbg(priv
, wol
, priv
->dev
,
2283 "magic packet detected, waking up\n");
2284 bcmgenet_power_up(priv
, GENET_POWER_WOL_MAGIC
);
2287 /* Link UP/DOWN event */
2288 if ((priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
) &&
2289 (priv
->irq0_stat
& UMAC_IRQ_LINK_EVENT
)) {
2290 phy_mac_interrupt(priv
->phydev
,
2291 !!(priv
->irq0_stat
& UMAC_IRQ_LINK_UP
));
2292 priv
->irq0_stat
&= ~UMAC_IRQ_LINK_EVENT
;
2296 /* bcmgenet_isr1: handle Rx and Tx priority queues */
2297 static irqreturn_t
bcmgenet_isr1(int irq
, void *dev_id
)
2299 struct bcmgenet_priv
*priv
= dev_id
;
2300 struct bcmgenet_rx_ring
*rx_ring
;
2301 struct bcmgenet_tx_ring
*tx_ring
;
2304 /* Save irq status for bottom-half processing. */
2306 bcmgenet_intrl2_1_readl(priv
, INTRL2_CPU_STAT
) &
2307 ~bcmgenet_intrl2_1_readl(priv
, INTRL2_CPU_MASK_STATUS
);
2309 /* clear interrupts */
2310 bcmgenet_intrl2_1_writel(priv
, priv
->irq1_stat
, INTRL2_CPU_CLEAR
);
2312 netif_dbg(priv
, intr
, priv
->dev
,
2313 "%s: IRQ=0x%x\n", __func__
, priv
->irq1_stat
);
2315 /* Check Rx priority queue interrupts */
2316 for (index
= 0; index
< priv
->hw_params
->rx_queues
; index
++) {
2317 if (!(priv
->irq1_stat
& BIT(UMAC_IRQ1_RX_INTR_SHIFT
+ index
)))
2320 rx_ring
= &priv
->rx_rings
[index
];
2322 if (likely(napi_schedule_prep(&rx_ring
->napi
))) {
2323 rx_ring
->int_disable(rx_ring
);
2324 __napi_schedule(&rx_ring
->napi
);
2328 /* Check Tx priority queue interrupts */
2329 for (index
= 0; index
< priv
->hw_params
->tx_queues
; index
++) {
2330 if (!(priv
->irq1_stat
& BIT(index
)))
2333 tx_ring
= &priv
->tx_rings
[index
];
2335 if (likely(napi_schedule_prep(&tx_ring
->napi
))) {
2336 tx_ring
->int_disable(tx_ring
);
2337 __napi_schedule(&tx_ring
->napi
);
2344 /* bcmgenet_isr0: handle Rx and Tx default queues + other stuff */
2345 static irqreturn_t
bcmgenet_isr0(int irq
, void *dev_id
)
2347 struct bcmgenet_priv
*priv
= dev_id
;
2348 struct bcmgenet_rx_ring
*rx_ring
;
2349 struct bcmgenet_tx_ring
*tx_ring
;
2351 /* Save irq status for bottom-half processing. */
2353 bcmgenet_intrl2_0_readl(priv
, INTRL2_CPU_STAT
) &
2354 ~bcmgenet_intrl2_0_readl(priv
, INTRL2_CPU_MASK_STATUS
);
2356 /* clear interrupts */
2357 bcmgenet_intrl2_0_writel(priv
, priv
->irq0_stat
, INTRL2_CPU_CLEAR
);
2359 netif_dbg(priv
, intr
, priv
->dev
,
2360 "IRQ=0x%x\n", priv
->irq0_stat
);
2362 if (priv
->irq0_stat
& UMAC_IRQ_RXDMA_DONE
) {
2363 rx_ring
= &priv
->rx_rings
[DESC_INDEX
];
2365 if (likely(napi_schedule_prep(&rx_ring
->napi
))) {
2366 rx_ring
->int_disable(rx_ring
);
2367 __napi_schedule(&rx_ring
->napi
);
2371 if (priv
->irq0_stat
& UMAC_IRQ_TXDMA_DONE
) {
2372 tx_ring
= &priv
->tx_rings
[DESC_INDEX
];
2374 if (likely(napi_schedule_prep(&tx_ring
->napi
))) {
2375 tx_ring
->int_disable(tx_ring
);
2376 __napi_schedule(&tx_ring
->napi
);
2380 if (priv
->irq0_stat
& (UMAC_IRQ_PHY_DET_R
|
2381 UMAC_IRQ_PHY_DET_F
|
2382 UMAC_IRQ_LINK_EVENT
|
2386 /* all other interested interrupts handled in bottom half */
2387 schedule_work(&priv
->bcmgenet_irq_work
);
2390 if ((priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
) &&
2391 priv
->irq0_stat
& (UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
)) {
2392 priv
->irq0_stat
&= ~(UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
);
2399 static irqreturn_t
bcmgenet_wol_isr(int irq
, void *dev_id
)
2401 struct bcmgenet_priv
*priv
= dev_id
;
2403 pm_wakeup_event(&priv
->pdev
->dev
, 0);
2408 static void bcmgenet_umac_reset(struct bcmgenet_priv
*priv
)
2412 reg
= bcmgenet_rbuf_ctrl_get(priv
);
2414 bcmgenet_rbuf_ctrl_set(priv
, reg
);
2418 bcmgenet_rbuf_ctrl_set(priv
, reg
);
2422 static void bcmgenet_set_hw_addr(struct bcmgenet_priv
*priv
,
2423 unsigned char *addr
)
2425 bcmgenet_umac_writel(priv
, (addr
[0] << 24) | (addr
[1] << 16) |
2426 (addr
[2] << 8) | addr
[3], UMAC_MAC0
);
2427 bcmgenet_umac_writel(priv
, (addr
[4] << 8) | addr
[5], UMAC_MAC1
);
2430 /* Returns a reusable dma control register value */
2431 static u32
bcmgenet_dma_disable(struct bcmgenet_priv
*priv
)
2437 dma_ctrl
= 1 << (DESC_INDEX
+ DMA_RING_BUF_EN_SHIFT
) | DMA_EN
;
2438 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2440 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2442 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2444 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2446 bcmgenet_umac_writel(priv
, 1, UMAC_TX_FLUSH
);
2448 bcmgenet_umac_writel(priv
, 0, UMAC_TX_FLUSH
);
2453 static void bcmgenet_enable_dma(struct bcmgenet_priv
*priv
, u32 dma_ctrl
)
2457 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2459 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2461 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2463 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2466 static bool bcmgenet_hfb_is_filter_enabled(struct bcmgenet_priv
*priv
,
2472 offset
= HFB_FLT_ENABLE_V3PLUS
+ (f_index
< 32) * sizeof(u32
);
2473 reg
= bcmgenet_hfb_reg_readl(priv
, offset
);
2474 return !!(reg
& (1 << (f_index
% 32)));
2477 static void bcmgenet_hfb_enable_filter(struct bcmgenet_priv
*priv
, u32 f_index
)
2482 offset
= HFB_FLT_ENABLE_V3PLUS
+ (f_index
< 32) * sizeof(u32
);
2483 reg
= bcmgenet_hfb_reg_readl(priv
, offset
);
2484 reg
|= (1 << (f_index
% 32));
2485 bcmgenet_hfb_reg_writel(priv
, reg
, offset
);
2488 static void bcmgenet_hfb_set_filter_rx_queue_mapping(struct bcmgenet_priv
*priv
,
2489 u32 f_index
, u32 rx_queue
)
2494 offset
= f_index
/ 8;
2495 reg
= bcmgenet_rdma_readl(priv
, DMA_INDEX2RING_0
+ offset
);
2496 reg
&= ~(0xF << (4 * (f_index
% 8)));
2497 reg
|= ((rx_queue
& 0xF) << (4 * (f_index
% 8)));
2498 bcmgenet_rdma_writel(priv
, reg
, DMA_INDEX2RING_0
+ offset
);
2501 static void bcmgenet_hfb_set_filter_length(struct bcmgenet_priv
*priv
,
2502 u32 f_index
, u32 f_length
)
2507 offset
= HFB_FLT_LEN_V3PLUS
+
2508 ((priv
->hw_params
->hfb_filter_cnt
- 1 - f_index
) / 4) *
2510 reg
= bcmgenet_hfb_reg_readl(priv
, offset
);
2511 reg
&= ~(0xFF << (8 * (f_index
% 4)));
2512 reg
|= ((f_length
& 0xFF) << (8 * (f_index
% 4)));
2513 bcmgenet_hfb_reg_writel(priv
, reg
, offset
);
2516 static int bcmgenet_hfb_find_unused_filter(struct bcmgenet_priv
*priv
)
2520 for (f_index
= 0; f_index
< priv
->hw_params
->hfb_filter_cnt
; f_index
++)
2521 if (!bcmgenet_hfb_is_filter_enabled(priv
, f_index
))
2527 /* bcmgenet_hfb_add_filter
2529 * Add new filter to Hardware Filter Block to match and direct Rx traffic to
2532 * f_data is an array of unsigned 32-bit integers where each 32-bit integer
2533 * provides filter data for 2 bytes (4 nibbles) of Rx frame:
2535 * bits 31:20 - unused
2536 * bit 19 - nibble 0 match enable
2537 * bit 18 - nibble 1 match enable
2538 * bit 17 - nibble 2 match enable
2539 * bit 16 - nibble 3 match enable
2540 * bits 15:12 - nibble 0 data
2541 * bits 11:8 - nibble 1 data
2542 * bits 7:4 - nibble 2 data
2543 * bits 3:0 - nibble 3 data
2546 * In order to match:
2547 * - Ethernet frame type = 0x0800 (IP)
2548 * - IP version field = 4
2549 * - IP protocol field = 0x11 (UDP)
2551 * The following filter is needed:
2552 * u32 hfb_filter_ipv4_udp[] = {
2553 * Rx frame offset 0x00: 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2554 * Rx frame offset 0x08: 0x00000000, 0x00000000, 0x000F0800, 0x00084000,
2555 * Rx frame offset 0x10: 0x00000000, 0x00000000, 0x00000000, 0x00030011,
2558 * To add the filter to HFB and direct the traffic to Rx queue 0, call:
2559 * bcmgenet_hfb_add_filter(priv, hfb_filter_ipv4_udp,
2560 * ARRAY_SIZE(hfb_filter_ipv4_udp), 0);
2562 int bcmgenet_hfb_add_filter(struct bcmgenet_priv
*priv
, u32
*f_data
,
2563 u32 f_length
, u32 rx_queue
)
2568 f_index
= bcmgenet_hfb_find_unused_filter(priv
);
2572 if (f_length
> priv
->hw_params
->hfb_filter_size
)
2575 for (i
= 0; i
< f_length
; i
++)
2576 bcmgenet_hfb_writel(priv
, f_data
[i
],
2577 (f_index
* priv
->hw_params
->hfb_filter_size
+ i
) *
2580 bcmgenet_hfb_set_filter_length(priv
, f_index
, 2 * f_length
);
2581 bcmgenet_hfb_set_filter_rx_queue_mapping(priv
, f_index
, rx_queue
);
2582 bcmgenet_hfb_enable_filter(priv
, f_index
);
2583 bcmgenet_hfb_reg_writel(priv
, 0x1, HFB_CTRL
);
2588 /* bcmgenet_hfb_clear
2590 * Clear Hardware Filter Block and disable all filtering.
2592 static void bcmgenet_hfb_clear(struct bcmgenet_priv
*priv
)
2596 bcmgenet_hfb_reg_writel(priv
, 0x0, HFB_CTRL
);
2597 bcmgenet_hfb_reg_writel(priv
, 0x0, HFB_FLT_ENABLE_V3PLUS
);
2598 bcmgenet_hfb_reg_writel(priv
, 0x0, HFB_FLT_ENABLE_V3PLUS
+ 4);
2600 for (i
= DMA_INDEX2RING_0
; i
<= DMA_INDEX2RING_7
; i
++)
2601 bcmgenet_rdma_writel(priv
, 0x0, i
);
2603 for (i
= 0; i
< (priv
->hw_params
->hfb_filter_cnt
/ 4); i
++)
2604 bcmgenet_hfb_reg_writel(priv
, 0x0,
2605 HFB_FLT_LEN_V3PLUS
+ i
* sizeof(u32
));
2607 for (i
= 0; i
< priv
->hw_params
->hfb_filter_cnt
*
2608 priv
->hw_params
->hfb_filter_size
; i
++)
2609 bcmgenet_hfb_writel(priv
, 0x0, i
* sizeof(u32
));
2612 static void bcmgenet_hfb_init(struct bcmgenet_priv
*priv
)
2614 if (GENET_IS_V1(priv
) || GENET_IS_V2(priv
))
2617 bcmgenet_hfb_clear(priv
);
2620 static void bcmgenet_netif_start(struct net_device
*dev
)
2622 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2624 /* Start the network engine */
2625 bcmgenet_enable_rx_napi(priv
);
2626 bcmgenet_enable_tx_napi(priv
);
2628 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, true);
2630 netif_tx_start_all_queues(dev
);
2632 phy_start(priv
->phydev
);
2635 static int bcmgenet_open(struct net_device
*dev
)
2637 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2638 unsigned long dma_ctrl
;
2642 netif_dbg(priv
, ifup
, dev
, "bcmgenet_open\n");
2644 /* Turn on the clock */
2645 if (!IS_ERR(priv
->clk
))
2646 clk_prepare_enable(priv
->clk
);
2648 /* If this is an internal GPHY, power it back on now, before UniMAC is
2649 * brought out of reset as absolutely no UniMAC activity is allowed
2651 if (phy_is_internal(priv
->phydev
))
2652 bcmgenet_power_up(priv
, GENET_POWER_PASSIVE
);
2654 /* take MAC out of reset */
2655 bcmgenet_umac_reset(priv
);
2657 ret
= init_umac(priv
);
2659 goto err_clk_disable
;
2661 /* disable ethernet MAC while updating its registers */
2662 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, false);
2664 /* Make sure we reflect the value of CRC_CMD_FWD */
2665 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
2666 priv
->crc_fwd_en
= !!(reg
& CMD_CRC_FWD
);
2668 bcmgenet_set_hw_addr(priv
, dev
->dev_addr
);
2670 if (phy_is_internal(priv
->phydev
)) {
2671 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
2672 reg
|= EXT_ENERGY_DET_MASK
;
2673 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
2676 /* Disable RX/TX DMA and flush TX queues */
2677 dma_ctrl
= bcmgenet_dma_disable(priv
);
2679 /* Reinitialize TDMA and RDMA and SW housekeeping */
2680 ret
= bcmgenet_init_dma(priv
);
2682 netdev_err(dev
, "failed to initialize DMA\n");
2683 goto err_clk_disable
;
2686 /* Always enable ring 16 - descriptor ring */
2687 bcmgenet_enable_dma(priv
, dma_ctrl
);
2690 bcmgenet_hfb_init(priv
);
2692 ret
= request_irq(priv
->irq0
, bcmgenet_isr0
, IRQF_SHARED
,
2695 netdev_err(dev
, "can't request IRQ %d\n", priv
->irq0
);
2699 ret
= request_irq(priv
->irq1
, bcmgenet_isr1
, IRQF_SHARED
,
2702 netdev_err(dev
, "can't request IRQ %d\n", priv
->irq1
);
2706 /* Re-configure the port multiplexer towards the PHY device */
2707 bcmgenet_mii_config(priv
->dev
, false);
2709 phy_connect_direct(dev
, priv
->phydev
, bcmgenet_mii_setup
,
2710 priv
->phy_interface
);
2712 bcmgenet_netif_start(dev
);
2717 free_irq(priv
->irq0
, dev
);
2719 bcmgenet_fini_dma(priv
);
2721 if (!IS_ERR(priv
->clk
))
2722 clk_disable_unprepare(priv
->clk
);
2726 static void bcmgenet_netif_stop(struct net_device
*dev
)
2728 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2730 netif_tx_stop_all_queues(dev
);
2731 phy_stop(priv
->phydev
);
2732 bcmgenet_intr_disable(priv
);
2733 bcmgenet_disable_rx_napi(priv
);
2734 bcmgenet_disable_tx_napi(priv
);
2736 /* Wait for pending work items to complete. Since interrupts are
2737 * disabled no new work will be scheduled.
2739 cancel_work_sync(&priv
->bcmgenet_irq_work
);
2741 priv
->old_link
= -1;
2742 priv
->old_speed
= -1;
2743 priv
->old_duplex
= -1;
2744 priv
->old_pause
= -1;
2747 static int bcmgenet_close(struct net_device
*dev
)
2749 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2752 netif_dbg(priv
, ifdown
, dev
, "bcmgenet_close\n");
2754 bcmgenet_netif_stop(dev
);
2756 /* Really kill the PHY state machine and disconnect from it */
2757 phy_disconnect(priv
->phydev
);
2759 /* Disable MAC receive */
2760 umac_enable_set(priv
, CMD_RX_EN
, false);
2762 ret
= bcmgenet_dma_teardown(priv
);
2766 /* Disable MAC transmit. TX DMA disabled have to done before this */
2767 umac_enable_set(priv
, CMD_TX_EN
, false);
2770 bcmgenet_tx_reclaim_all(dev
);
2771 bcmgenet_fini_dma(priv
);
2773 free_irq(priv
->irq0
, priv
);
2774 free_irq(priv
->irq1
, priv
);
2776 if (phy_is_internal(priv
->phydev
))
2777 ret
= bcmgenet_power_down(priv
, GENET_POWER_PASSIVE
);
2779 if (!IS_ERR(priv
->clk
))
2780 clk_disable_unprepare(priv
->clk
);
2785 static void bcmgenet_dump_tx_queue(struct bcmgenet_tx_ring
*ring
)
2787 struct bcmgenet_priv
*priv
= ring
->priv
;
2788 u32 p_index
, c_index
, intsts
, intmsk
;
2789 struct netdev_queue
*txq
;
2790 unsigned int free_bds
;
2791 unsigned long flags
;
2794 if (!netif_msg_tx_err(priv
))
2797 txq
= netdev_get_tx_queue(priv
->dev
, ring
->queue
);
2799 spin_lock_irqsave(&ring
->lock
, flags
);
2800 if (ring
->index
== DESC_INDEX
) {
2801 intsts
= ~bcmgenet_intrl2_0_readl(priv
, INTRL2_CPU_MASK_STATUS
);
2802 intmsk
= UMAC_IRQ_TXDMA_DONE
| UMAC_IRQ_TXDMA_MBDONE
;
2804 intsts
= ~bcmgenet_intrl2_1_readl(priv
, INTRL2_CPU_MASK_STATUS
);
2805 intmsk
= 1 << ring
->index
;
2807 c_index
= bcmgenet_tdma_ring_readl(priv
, ring
->index
, TDMA_CONS_INDEX
);
2808 p_index
= bcmgenet_tdma_ring_readl(priv
, ring
->index
, TDMA_PROD_INDEX
);
2809 txq_stopped
= netif_tx_queue_stopped(txq
);
2810 free_bds
= ring
->free_bds
;
2811 spin_unlock_irqrestore(&ring
->lock
, flags
);
2813 netif_err(priv
, tx_err
, priv
->dev
, "Ring %d queue %d status summary\n"
2814 "TX queue status: %s, interrupts: %s\n"
2815 "(sw)free_bds: %d (sw)size: %d\n"
2816 "(sw)p_index: %d (hw)p_index: %d\n"
2817 "(sw)c_index: %d (hw)c_index: %d\n"
2818 "(sw)clean_p: %d (sw)write_p: %d\n"
2819 "(sw)cb_ptr: %d (sw)end_ptr: %d\n",
2820 ring
->index
, ring
->queue
,
2821 txq_stopped
? "stopped" : "active",
2822 intsts
& intmsk
? "enabled" : "disabled",
2823 free_bds
, ring
->size
,
2824 ring
->prod_index
, p_index
& DMA_P_INDEX_MASK
,
2825 ring
->c_index
, c_index
& DMA_C_INDEX_MASK
,
2826 ring
->clean_ptr
, ring
->write_ptr
,
2827 ring
->cb_ptr
, ring
->end_ptr
);
2830 static void bcmgenet_timeout(struct net_device
*dev
)
2832 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2833 u32 int0_enable
= 0;
2834 u32 int1_enable
= 0;
2837 netif_dbg(priv
, tx_err
, dev
, "bcmgenet_timeout\n");
2839 for (q
= 0; q
< priv
->hw_params
->tx_queues
; q
++)
2840 bcmgenet_dump_tx_queue(&priv
->tx_rings
[q
]);
2841 bcmgenet_dump_tx_queue(&priv
->tx_rings
[DESC_INDEX
]);
2843 bcmgenet_tx_reclaim_all(dev
);
2845 for (q
= 0; q
< priv
->hw_params
->tx_queues
; q
++)
2846 int1_enable
|= (1 << q
);
2848 int0_enable
= UMAC_IRQ_TXDMA_DONE
;
2850 /* Re-enable TX interrupts if disabled */
2851 bcmgenet_intrl2_0_writel(priv
, int0_enable
, INTRL2_CPU_MASK_CLEAR
);
2852 bcmgenet_intrl2_1_writel(priv
, int1_enable
, INTRL2_CPU_MASK_CLEAR
);
2854 dev
->trans_start
= jiffies
;
2856 dev
->stats
.tx_errors
++;
2858 netif_tx_wake_all_queues(dev
);
2861 #define MAX_MC_COUNT 16
2863 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv
*priv
,
2864 unsigned char *addr
,
2870 bcmgenet_umac_writel(priv
, addr
[0] << 8 | addr
[1],
2871 UMAC_MDF_ADDR
+ (*i
* 4));
2872 bcmgenet_umac_writel(priv
, addr
[2] << 24 | addr
[3] << 16 |
2873 addr
[4] << 8 | addr
[5],
2874 UMAC_MDF_ADDR
+ ((*i
+ 1) * 4));
2875 reg
= bcmgenet_umac_readl(priv
, UMAC_MDF_CTRL
);
2876 reg
|= (1 << (MAX_MC_COUNT
- *mc
));
2877 bcmgenet_umac_writel(priv
, reg
, UMAC_MDF_CTRL
);
2882 static void bcmgenet_set_rx_mode(struct net_device
*dev
)
2884 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2885 struct netdev_hw_addr
*ha
;
2889 netif_dbg(priv
, hw
, dev
, "%s: %08X\n", __func__
, dev
->flags
);
2891 /* Promiscuous mode */
2892 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
2893 if (dev
->flags
& IFF_PROMISC
) {
2895 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
2896 bcmgenet_umac_writel(priv
, 0, UMAC_MDF_CTRL
);
2899 reg
&= ~CMD_PROMISC
;
2900 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
2903 /* UniMac doesn't support ALLMULTI */
2904 if (dev
->flags
& IFF_ALLMULTI
) {
2905 netdev_warn(dev
, "ALLMULTI is not supported\n");
2909 /* update MDF filter */
2913 bcmgenet_set_mdf_addr(priv
, dev
->broadcast
, &i
, &mc
);
2914 /* my own address.*/
2915 bcmgenet_set_mdf_addr(priv
, dev
->dev_addr
, &i
, &mc
);
2917 if (netdev_uc_count(dev
) > (MAX_MC_COUNT
- mc
))
2920 if (!netdev_uc_empty(dev
))
2921 netdev_for_each_uc_addr(ha
, dev
)
2922 bcmgenet_set_mdf_addr(priv
, ha
->addr
, &i
, &mc
);
2924 if (netdev_mc_empty(dev
) || netdev_mc_count(dev
) >= (MAX_MC_COUNT
- mc
))
2927 netdev_for_each_mc_addr(ha
, dev
)
2928 bcmgenet_set_mdf_addr(priv
, ha
->addr
, &i
, &mc
);
2931 /* Set the hardware MAC address. */
2932 static int bcmgenet_set_mac_addr(struct net_device
*dev
, void *p
)
2934 struct sockaddr
*addr
= p
;
2936 /* Setting the MAC address at the hardware level is not possible
2937 * without disabling the UniMAC RX/TX enable bits.
2939 if (netif_running(dev
))
2942 ether_addr_copy(dev
->dev_addr
, addr
->sa_data
);
2947 static const struct net_device_ops bcmgenet_netdev_ops
= {
2948 .ndo_open
= bcmgenet_open
,
2949 .ndo_stop
= bcmgenet_close
,
2950 .ndo_start_xmit
= bcmgenet_xmit
,
2951 .ndo_tx_timeout
= bcmgenet_timeout
,
2952 .ndo_set_rx_mode
= bcmgenet_set_rx_mode
,
2953 .ndo_set_mac_address
= bcmgenet_set_mac_addr
,
2954 .ndo_do_ioctl
= bcmgenet_ioctl
,
2955 .ndo_set_features
= bcmgenet_set_features
,
2958 /* Array of GENET hardware parameters/characteristics */
2959 static struct bcmgenet_hw_params bcmgenet_hw_params
[] = {
2965 .bp_in_en_shift
= 16,
2966 .bp_in_mask
= 0xffff,
2967 .hfb_filter_cnt
= 16,
2969 .hfb_offset
= 0x1000,
2970 .rdma_offset
= 0x2000,
2971 .tdma_offset
= 0x3000,
2979 .bp_in_en_shift
= 16,
2980 .bp_in_mask
= 0xffff,
2981 .hfb_filter_cnt
= 16,
2983 .tbuf_offset
= 0x0600,
2984 .hfb_offset
= 0x1000,
2985 .hfb_reg_offset
= 0x2000,
2986 .rdma_offset
= 0x3000,
2987 .tdma_offset
= 0x4000,
2989 .flags
= GENET_HAS_EXT
,
2996 .bp_in_en_shift
= 17,
2997 .bp_in_mask
= 0x1ffff,
2998 .hfb_filter_cnt
= 48,
2999 .hfb_filter_size
= 128,
3001 .tbuf_offset
= 0x0600,
3002 .hfb_offset
= 0x8000,
3003 .hfb_reg_offset
= 0xfc00,
3004 .rdma_offset
= 0x10000,
3005 .tdma_offset
= 0x11000,
3007 .flags
= GENET_HAS_EXT
| GENET_HAS_MDIO_INTR
|
3008 GENET_HAS_MOCA_LINK_DET
,
3015 .bp_in_en_shift
= 17,
3016 .bp_in_mask
= 0x1ffff,
3017 .hfb_filter_cnt
= 48,
3018 .hfb_filter_size
= 128,
3020 .tbuf_offset
= 0x0600,
3021 .hfb_offset
= 0x8000,
3022 .hfb_reg_offset
= 0xfc00,
3023 .rdma_offset
= 0x2000,
3024 .tdma_offset
= 0x4000,
3026 .flags
= GENET_HAS_40BITS
| GENET_HAS_EXT
|
3027 GENET_HAS_MDIO_INTR
| GENET_HAS_MOCA_LINK_DET
,
3031 /* Infer hardware parameters from the detected GENET version */
3032 static void bcmgenet_set_hw_params(struct bcmgenet_priv
*priv
)
3034 struct bcmgenet_hw_params
*params
;
3039 if (GENET_IS_V4(priv
)) {
3040 bcmgenet_dma_regs
= bcmgenet_dma_regs_v3plus
;
3041 genet_dma_ring_regs
= genet_dma_ring_regs_v4
;
3042 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V3PLUS
;
3043 priv
->version
= GENET_V4
;
3044 } else if (GENET_IS_V3(priv
)) {
3045 bcmgenet_dma_regs
= bcmgenet_dma_regs_v3plus
;
3046 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
3047 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V3PLUS
;
3048 priv
->version
= GENET_V3
;
3049 } else if (GENET_IS_V2(priv
)) {
3050 bcmgenet_dma_regs
= bcmgenet_dma_regs_v2
;
3051 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
3052 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V12
;
3053 priv
->version
= GENET_V2
;
3054 } else if (GENET_IS_V1(priv
)) {
3055 bcmgenet_dma_regs
= bcmgenet_dma_regs_v1
;
3056 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
3057 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V12
;
3058 priv
->version
= GENET_V1
;
3061 /* enum genet_version starts at 1 */
3062 priv
->hw_params
= &bcmgenet_hw_params
[priv
->version
];
3063 params
= priv
->hw_params
;
3065 /* Read GENET HW version */
3066 reg
= bcmgenet_sys_readl(priv
, SYS_REV_CTRL
);
3067 major
= (reg
>> 24 & 0x0f);
3070 else if (major
== 0)
3072 if (major
!= priv
->version
) {
3073 dev_err(&priv
->pdev
->dev
,
3074 "GENET version mismatch, got: %d, configured for: %d\n",
3075 major
, priv
->version
);
3078 /* Print the GENET core version */
3079 dev_info(&priv
->pdev
->dev
, "GENET " GENET_VER_FMT
,
3080 major
, (reg
>> 16) & 0x0f, reg
& 0xffff);
3082 /* Store the integrated PHY revision for the MDIO probing function
3083 * to pass this information to the PHY driver. The PHY driver expects
3084 * to find the PHY major revision in bits 15:8 while the GENET register
3085 * stores that information in bits 7:0, account for that.
3087 * On newer chips, starting with PHY revision G0, a new scheme is
3088 * deployed similar to the Starfighter 2 switch with GPHY major
3089 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
3090 * is reserved as well as special value 0x01ff, we have a small
3091 * heuristic to check for the new GPHY revision and re-arrange things
3092 * so the GPHY driver is happy.
3094 gphy_rev
= reg
& 0xffff;
3096 /* This is the good old scheme, just GPHY major, no minor nor patch */
3097 if ((gphy_rev
& 0xf0) != 0)
3098 priv
->gphy_rev
= gphy_rev
<< 8;
3100 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
3101 else if ((gphy_rev
& 0xff00) != 0)
3102 priv
->gphy_rev
= gphy_rev
;
3104 /* This is reserved so should require special treatment */
3105 else if (gphy_rev
== 0 || gphy_rev
== 0x01ff) {
3106 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev
);
3110 #ifdef CONFIG_PHYS_ADDR_T_64BIT
3111 if (!(params
->flags
& GENET_HAS_40BITS
))
3112 pr_warn("GENET does not support 40-bits PA\n");
3115 pr_debug("Configuration for version: %d\n"
3116 "TXq: %1d, TXqBDs: %1d, RXq: %1d, RXqBDs: %1d\n"
3117 "BP << en: %2d, BP msk: 0x%05x\n"
3118 "HFB count: %2d, QTAQ msk: 0x%05x\n"
3119 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
3120 "RDMA: 0x%05x, TDMA: 0x%05x\n"
3123 params
->tx_queues
, params
->tx_bds_per_q
,
3124 params
->rx_queues
, params
->rx_bds_per_q
,
3125 params
->bp_in_en_shift
, params
->bp_in_mask
,
3126 params
->hfb_filter_cnt
, params
->qtag_mask
,
3127 params
->tbuf_offset
, params
->hfb_offset
,
3128 params
->hfb_reg_offset
,
3129 params
->rdma_offset
, params
->tdma_offset
,
3130 params
->words_per_bd
);
3133 static const struct of_device_id bcmgenet_match
[] = {
3134 { .compatible
= "brcm,genet-v1", .data
= (void *)GENET_V1
},
3135 { .compatible
= "brcm,genet-v2", .data
= (void *)GENET_V2
},
3136 { .compatible
= "brcm,genet-v3", .data
= (void *)GENET_V3
},
3137 { .compatible
= "brcm,genet-v4", .data
= (void *)GENET_V4
},
3141 static int bcmgenet_probe(struct platform_device
*pdev
)
3143 struct bcmgenet_platform_data
*pd
= pdev
->dev
.platform_data
;
3144 struct device_node
*dn
= pdev
->dev
.of_node
;
3145 const struct of_device_id
*of_id
= NULL
;
3146 struct bcmgenet_priv
*priv
;
3147 struct net_device
*dev
;
3148 const void *macaddr
;
3152 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and RX queues */
3153 dev
= alloc_etherdev_mqs(sizeof(*priv
), GENET_MAX_MQ_CNT
+ 1,
3154 GENET_MAX_MQ_CNT
+ 1);
3156 dev_err(&pdev
->dev
, "can't allocate net device\n");
3161 of_id
= of_match_node(bcmgenet_match
, dn
);
3166 priv
= netdev_priv(dev
);
3167 priv
->irq0
= platform_get_irq(pdev
, 0);
3168 priv
->irq1
= platform_get_irq(pdev
, 1);
3169 priv
->wol_irq
= platform_get_irq(pdev
, 2);
3170 if (!priv
->irq0
|| !priv
->irq1
) {
3171 dev_err(&pdev
->dev
, "can't find IRQs\n");
3177 macaddr
= of_get_mac_address(dn
);
3179 dev_err(&pdev
->dev
, "can't find MAC address\n");
3184 macaddr
= pd
->mac_address
;
3187 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
3188 priv
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
3189 if (IS_ERR(priv
->base
)) {
3190 err
= PTR_ERR(priv
->base
);
3194 SET_NETDEV_DEV(dev
, &pdev
->dev
);
3195 dev_set_drvdata(&pdev
->dev
, dev
);
3196 ether_addr_copy(dev
->dev_addr
, macaddr
);
3197 dev
->watchdog_timeo
= 2 * HZ
;
3198 dev
->ethtool_ops
= &bcmgenet_ethtool_ops
;
3199 dev
->netdev_ops
= &bcmgenet_netdev_ops
;
3201 priv
->msg_enable
= netif_msg_init(-1, GENET_MSG_DEFAULT
);
3203 /* Set hardware features */
3204 dev
->hw_features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
|
3205 NETIF_F_IPV6_CSUM
| NETIF_F_RXCSUM
;
3207 /* Request the WOL interrupt and advertise suspend if available */
3208 priv
->wol_irq_disabled
= true;
3209 err
= devm_request_irq(&pdev
->dev
, priv
->wol_irq
, bcmgenet_wol_isr
, 0,
3212 device_set_wakeup_capable(&pdev
->dev
, 1);
3214 /* Set the needed headroom to account for any possible
3215 * features enabling/disabling at runtime
3217 dev
->needed_headroom
+= 64;
3219 netdev_boot_setup_check(dev
);
3224 priv
->version
= (enum bcmgenet_version
)of_id
->data
;
3226 priv
->version
= pd
->genet_version
;
3228 priv
->clk
= devm_clk_get(&priv
->pdev
->dev
, "enet");
3229 if (IS_ERR(priv
->clk
))
3230 dev_warn(&priv
->pdev
->dev
, "failed to get enet clock\n");
3232 if (!IS_ERR(priv
->clk
))
3233 clk_prepare_enable(priv
->clk
);
3235 bcmgenet_set_hw_params(priv
);
3237 /* Mii wait queue */
3238 init_waitqueue_head(&priv
->wq
);
3239 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
3240 priv
->rx_buf_len
= RX_BUF_LENGTH
;
3241 INIT_WORK(&priv
->bcmgenet_irq_work
, bcmgenet_irq_task
);
3243 priv
->clk_wol
= devm_clk_get(&priv
->pdev
->dev
, "enet-wol");
3244 if (IS_ERR(priv
->clk_wol
))
3245 dev_warn(&priv
->pdev
->dev
, "failed to get enet-wol clock\n");
3247 priv
->clk_eee
= devm_clk_get(&priv
->pdev
->dev
, "enet-eee");
3248 if (IS_ERR(priv
->clk_eee
)) {
3249 dev_warn(&priv
->pdev
->dev
, "failed to get enet-eee clock\n");
3250 priv
->clk_eee
= NULL
;
3253 err
= reset_umac(priv
);
3255 goto err_clk_disable
;
3257 err
= bcmgenet_mii_init(dev
);
3259 goto err_clk_disable
;
3261 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
3262 * just the ring 16 descriptor based TX
3264 netif_set_real_num_tx_queues(priv
->dev
, priv
->hw_params
->tx_queues
+ 1);
3265 netif_set_real_num_rx_queues(priv
->dev
, priv
->hw_params
->rx_queues
+ 1);
3267 /* libphy will determine the link state */
3268 netif_carrier_off(dev
);
3270 /* Turn off the main clock, WOL clock is handled separately */
3271 if (!IS_ERR(priv
->clk
))
3272 clk_disable_unprepare(priv
->clk
);
3274 err
= register_netdev(dev
);
3281 if (!IS_ERR(priv
->clk
))
3282 clk_disable_unprepare(priv
->clk
);
3288 static int bcmgenet_remove(struct platform_device
*pdev
)
3290 struct bcmgenet_priv
*priv
= dev_to_priv(&pdev
->dev
);
3292 dev_set_drvdata(&pdev
->dev
, NULL
);
3293 unregister_netdev(priv
->dev
);
3294 bcmgenet_mii_exit(priv
->dev
);
3295 free_netdev(priv
->dev
);
3300 #ifdef CONFIG_PM_SLEEP
3301 static int bcmgenet_suspend(struct device
*d
)
3303 struct net_device
*dev
= dev_get_drvdata(d
);
3304 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
3307 if (!netif_running(dev
))
3310 bcmgenet_netif_stop(dev
);
3312 phy_suspend(priv
->phydev
);
3314 netif_device_detach(dev
);
3316 /* Disable MAC receive */
3317 umac_enable_set(priv
, CMD_RX_EN
, false);
3319 ret
= bcmgenet_dma_teardown(priv
);
3323 /* Disable MAC transmit. TX DMA disabled have to done before this */
3324 umac_enable_set(priv
, CMD_TX_EN
, false);
3327 bcmgenet_tx_reclaim_all(dev
);
3328 bcmgenet_fini_dma(priv
);
3330 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
3331 if (device_may_wakeup(d
) && priv
->wolopts
) {
3332 ret
= bcmgenet_power_down(priv
, GENET_POWER_WOL_MAGIC
);
3333 clk_prepare_enable(priv
->clk_wol
);
3334 } else if (phy_is_internal(priv
->phydev
)) {
3335 ret
= bcmgenet_power_down(priv
, GENET_POWER_PASSIVE
);
3338 /* Turn off the clocks */
3339 clk_disable_unprepare(priv
->clk
);
3344 static int bcmgenet_resume(struct device
*d
)
3346 struct net_device
*dev
= dev_get_drvdata(d
);
3347 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
3348 unsigned long dma_ctrl
;
3352 if (!netif_running(dev
))
3355 /* Turn on the clock */
3356 ret
= clk_prepare_enable(priv
->clk
);
3360 /* If this is an internal GPHY, power it back on now, before UniMAC is
3361 * brought out of reset as absolutely no UniMAC activity is allowed
3363 if (phy_is_internal(priv
->phydev
))
3364 bcmgenet_power_up(priv
, GENET_POWER_PASSIVE
);
3366 bcmgenet_umac_reset(priv
);
3368 ret
= init_umac(priv
);
3370 goto out_clk_disable
;
3372 /* From WOL-enabled suspend, switch to regular clock */
3374 clk_disable_unprepare(priv
->clk_wol
);
3376 phy_init_hw(priv
->phydev
);
3377 /* Speed settings must be restored */
3378 bcmgenet_mii_config(priv
->dev
, false);
3380 /* disable ethernet MAC while updating its registers */
3381 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, false);
3383 bcmgenet_set_hw_addr(priv
, dev
->dev_addr
);
3385 if (phy_is_internal(priv
->phydev
)) {
3386 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
3387 reg
|= EXT_ENERGY_DET_MASK
;
3388 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
3392 bcmgenet_power_up(priv
, GENET_POWER_WOL_MAGIC
);
3394 /* Disable RX/TX DMA and flush TX queues */
3395 dma_ctrl
= bcmgenet_dma_disable(priv
);
3397 /* Reinitialize TDMA and RDMA and SW housekeeping */
3398 ret
= bcmgenet_init_dma(priv
);
3400 netdev_err(dev
, "failed to initialize DMA\n");
3401 goto out_clk_disable
;
3404 /* Always enable ring 16 - descriptor ring */
3405 bcmgenet_enable_dma(priv
, dma_ctrl
);
3407 netif_device_attach(dev
);
3409 phy_resume(priv
->phydev
);
3411 if (priv
->eee
.eee_enabled
)
3412 bcmgenet_eee_enable_set(dev
, true);
3414 bcmgenet_netif_start(dev
);
3419 clk_disable_unprepare(priv
->clk
);
3422 #endif /* CONFIG_PM_SLEEP */
3424 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops
, bcmgenet_suspend
, bcmgenet_resume
);
3426 static struct platform_driver bcmgenet_driver
= {
3427 .probe
= bcmgenet_probe
,
3428 .remove
= bcmgenet_remove
,
3431 .of_match_table
= bcmgenet_match
,
3432 .pm
= &bcmgenet_pm_ops
,
3435 module_platform_driver(bcmgenet_driver
);
3437 MODULE_AUTHOR("Broadcom Corporation");
3438 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
3439 MODULE_ALIAS("platform:bcmgenet");
3440 MODULE_LICENSE("GPL");