2 * Broadcom GENET (Gigabit Ethernet) controller driver
4 * Copyright (c) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
11 #define pr_fmt(fmt) "bcmgenet: " fmt
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/types.h>
17 #include <linux/fcntl.h>
18 #include <linux/interrupt.h>
19 #include <linux/string.h>
20 #include <linux/if_ether.h>
21 #include <linux/init.h>
22 #include <linux/errno.h>
23 #include <linux/delay.h>
24 #include <linux/platform_device.h>
25 #include <linux/dma-mapping.h>
27 #include <linux/clk.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_net.h>
32 #include <linux/of_platform.h>
35 #include <linux/mii.h>
36 #include <linux/ethtool.h>
37 #include <linux/netdevice.h>
38 #include <linux/inetdevice.h>
39 #include <linux/etherdevice.h>
40 #include <linux/skbuff.h>
43 #include <linux/ipv6.h>
44 #include <linux/phy.h>
45 #include <linux/platform_data/bcmgenet.h>
47 #include <asm/unaligned.h>
51 /* Maximum number of hardware queues, downsized if needed */
52 #define GENET_MAX_MQ_CNT 4
54 /* Default highest priority queue for multi queue support */
55 #define GENET_Q0_PRIORITY 0
57 #define GENET_DEFAULT_BD_CNT \
58 (TOTAL_DESC - priv->hw_params->tx_queues * priv->hw_params->bds_cnt)
60 #define RX_BUF_LENGTH 2048
61 #define SKB_ALIGNMENT 32
63 /* Tx/Rx DMA register offset, skip 256 descriptors */
64 #define WORDS_PER_BD(p) (p->hw_params->words_per_bd)
65 #define DMA_DESC_SIZE (WORDS_PER_BD(priv) * sizeof(u32))
67 #define GENET_TDMA_REG_OFF (priv->hw_params->tdma_offset + \
68 TOTAL_DESC * DMA_DESC_SIZE)
70 #define GENET_RDMA_REG_OFF (priv->hw_params->rdma_offset + \
71 TOTAL_DESC * DMA_DESC_SIZE)
73 static inline void dmadesc_set_length_status(struct bcmgenet_priv
*priv
,
74 void __iomem
*d
, u32 value
)
76 __raw_writel(value
, d
+ DMA_DESC_LENGTH_STATUS
);
79 static inline u32
dmadesc_get_length_status(struct bcmgenet_priv
*priv
,
82 return __raw_readl(d
+ DMA_DESC_LENGTH_STATUS
);
85 static inline void dmadesc_set_addr(struct bcmgenet_priv
*priv
,
89 __raw_writel(lower_32_bits(addr
), d
+ DMA_DESC_ADDRESS_LO
);
91 /* Register writes to GISB bus can take couple hundred nanoseconds
92 * and are done for each packet, save these expensive writes unless
93 * the platform is explicitly configured for 64-bits/LPAE.
95 #ifdef CONFIG_PHYS_ADDR_T_64BIT
96 if (priv
->hw_params
->flags
& GENET_HAS_40BITS
)
97 __raw_writel(upper_32_bits(addr
), d
+ DMA_DESC_ADDRESS_HI
);
101 /* Combined address + length/status setter */
102 static inline void dmadesc_set(struct bcmgenet_priv
*priv
,
103 void __iomem
*d
, dma_addr_t addr
, u32 val
)
105 dmadesc_set_length_status(priv
, d
, val
);
106 dmadesc_set_addr(priv
, d
, addr
);
109 static inline dma_addr_t
dmadesc_get_addr(struct bcmgenet_priv
*priv
,
114 addr
= __raw_readl(d
+ DMA_DESC_ADDRESS_LO
);
116 /* Register writes to GISB bus can take couple hundred nanoseconds
117 * and are done for each packet, save these expensive writes unless
118 * the platform is explicitly configured for 64-bits/LPAE.
120 #ifdef CONFIG_PHYS_ADDR_T_64BIT
121 if (priv
->hw_params
->flags
& GENET_HAS_40BITS
)
122 addr
|= (u64
)__raw_readl(d
+ DMA_DESC_ADDRESS_HI
) << 32;
127 #define GENET_VER_FMT "%1d.%1d EPHY: 0x%04x"
129 #define GENET_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | \
132 static inline u32
bcmgenet_rbuf_ctrl_get(struct bcmgenet_priv
*priv
)
134 if (GENET_IS_V1(priv
))
135 return bcmgenet_rbuf_readl(priv
, RBUF_FLUSH_CTRL_V1
);
137 return bcmgenet_sys_readl(priv
, SYS_RBUF_FLUSH_CTRL
);
140 static inline void bcmgenet_rbuf_ctrl_set(struct bcmgenet_priv
*priv
, u32 val
)
142 if (GENET_IS_V1(priv
))
143 bcmgenet_rbuf_writel(priv
, val
, RBUF_FLUSH_CTRL_V1
);
145 bcmgenet_sys_writel(priv
, val
, SYS_RBUF_FLUSH_CTRL
);
148 /* These macros are defined to deal with register map change
149 * between GENET1.1 and GENET2. Only those currently being used
150 * by driver are defined.
152 static inline u32
bcmgenet_tbuf_ctrl_get(struct bcmgenet_priv
*priv
)
154 if (GENET_IS_V1(priv
))
155 return bcmgenet_rbuf_readl(priv
, TBUF_CTRL_V1
);
157 return __raw_readl(priv
->base
+
158 priv
->hw_params
->tbuf_offset
+ TBUF_CTRL
);
161 static inline void bcmgenet_tbuf_ctrl_set(struct bcmgenet_priv
*priv
, u32 val
)
163 if (GENET_IS_V1(priv
))
164 bcmgenet_rbuf_writel(priv
, val
, TBUF_CTRL_V1
);
166 __raw_writel(val
, priv
->base
+
167 priv
->hw_params
->tbuf_offset
+ TBUF_CTRL
);
170 static inline u32
bcmgenet_bp_mc_get(struct bcmgenet_priv
*priv
)
172 if (GENET_IS_V1(priv
))
173 return bcmgenet_rbuf_readl(priv
, TBUF_BP_MC_V1
);
175 return __raw_readl(priv
->base
+
176 priv
->hw_params
->tbuf_offset
+ TBUF_BP_MC
);
179 static inline void bcmgenet_bp_mc_set(struct bcmgenet_priv
*priv
, u32 val
)
181 if (GENET_IS_V1(priv
))
182 bcmgenet_rbuf_writel(priv
, val
, TBUF_BP_MC_V1
);
184 __raw_writel(val
, priv
->base
+
185 priv
->hw_params
->tbuf_offset
+ TBUF_BP_MC
);
188 /* RX/TX DMA register accessors */
200 static const u8 bcmgenet_dma_regs_v3plus
[] = {
201 [DMA_RING_CFG
] = 0x00,
204 [DMA_SCB_BURST_SIZE
] = 0x0C,
205 [DMA_ARB_CTRL
] = 0x2C,
206 [DMA_PRIORITY_0
] = 0x30,
207 [DMA_PRIORITY_1
] = 0x34,
208 [DMA_PRIORITY_2
] = 0x38,
211 static const u8 bcmgenet_dma_regs_v2
[] = {
212 [DMA_RING_CFG
] = 0x00,
215 [DMA_SCB_BURST_SIZE
] = 0x0C,
216 [DMA_ARB_CTRL
] = 0x30,
217 [DMA_PRIORITY_0
] = 0x34,
218 [DMA_PRIORITY_1
] = 0x38,
219 [DMA_PRIORITY_2
] = 0x3C,
222 static const u8 bcmgenet_dma_regs_v1
[] = {
225 [DMA_SCB_BURST_SIZE
] = 0x0C,
226 [DMA_ARB_CTRL
] = 0x30,
227 [DMA_PRIORITY_0
] = 0x34,
228 [DMA_PRIORITY_1
] = 0x38,
229 [DMA_PRIORITY_2
] = 0x3C,
232 /* Set at runtime once bcmgenet version is known */
233 static const u8
*bcmgenet_dma_regs
;
235 static inline struct bcmgenet_priv
*dev_to_priv(struct device
*dev
)
237 return netdev_priv(dev_get_drvdata(dev
));
240 static inline u32
bcmgenet_tdma_readl(struct bcmgenet_priv
*priv
,
243 return __raw_readl(priv
->base
+ GENET_TDMA_REG_OFF
+
244 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
247 static inline void bcmgenet_tdma_writel(struct bcmgenet_priv
*priv
,
248 u32 val
, enum dma_reg r
)
250 __raw_writel(val
, priv
->base
+ GENET_TDMA_REG_OFF
+
251 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
254 static inline u32
bcmgenet_rdma_readl(struct bcmgenet_priv
*priv
,
257 return __raw_readl(priv
->base
+ GENET_RDMA_REG_OFF
+
258 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
261 static inline void bcmgenet_rdma_writel(struct bcmgenet_priv
*priv
,
262 u32 val
, enum dma_reg r
)
264 __raw_writel(val
, priv
->base
+ GENET_RDMA_REG_OFF
+
265 DMA_RINGS_SIZE
+ bcmgenet_dma_regs
[r
]);
268 /* RDMA/TDMA ring registers and accessors
269 * we merge the common fields and just prefix with T/D the registers
270 * having different meaning depending on the direction
274 RDMA_WRITE_PTR
= TDMA_READ_PTR
,
276 RDMA_WRITE_PTR_HI
= TDMA_READ_PTR_HI
,
278 RDMA_PROD_INDEX
= TDMA_CONS_INDEX
,
280 RDMA_CONS_INDEX
= TDMA_PROD_INDEX
,
286 DMA_MBUF_DONE_THRESH
,
288 RDMA_XON_XOFF_THRESH
= TDMA_FLOW_PERIOD
,
290 RDMA_READ_PTR
= TDMA_WRITE_PTR
,
292 RDMA_READ_PTR_HI
= TDMA_WRITE_PTR_HI
295 /* GENET v4 supports 40-bits pointer addressing
296 * for obvious reasons the LO and HI word parts
297 * are contiguous, but this offsets the other
300 static const u8 genet_dma_ring_regs_v4
[] = {
301 [TDMA_READ_PTR
] = 0x00,
302 [TDMA_READ_PTR_HI
] = 0x04,
303 [TDMA_CONS_INDEX
] = 0x08,
304 [TDMA_PROD_INDEX
] = 0x0C,
305 [DMA_RING_BUF_SIZE
] = 0x10,
306 [DMA_START_ADDR
] = 0x14,
307 [DMA_START_ADDR_HI
] = 0x18,
308 [DMA_END_ADDR
] = 0x1C,
309 [DMA_END_ADDR_HI
] = 0x20,
310 [DMA_MBUF_DONE_THRESH
] = 0x24,
311 [TDMA_FLOW_PERIOD
] = 0x28,
312 [TDMA_WRITE_PTR
] = 0x2C,
313 [TDMA_WRITE_PTR_HI
] = 0x30,
316 static const u8 genet_dma_ring_regs_v123
[] = {
317 [TDMA_READ_PTR
] = 0x00,
318 [TDMA_CONS_INDEX
] = 0x04,
319 [TDMA_PROD_INDEX
] = 0x08,
320 [DMA_RING_BUF_SIZE
] = 0x0C,
321 [DMA_START_ADDR
] = 0x10,
322 [DMA_END_ADDR
] = 0x14,
323 [DMA_MBUF_DONE_THRESH
] = 0x18,
324 [TDMA_FLOW_PERIOD
] = 0x1C,
325 [TDMA_WRITE_PTR
] = 0x20,
328 /* Set at runtime once GENET version is known */
329 static const u8
*genet_dma_ring_regs
;
331 static inline u32
bcmgenet_tdma_ring_readl(struct bcmgenet_priv
*priv
,
335 return __raw_readl(priv
->base
+ GENET_TDMA_REG_OFF
+
336 (DMA_RING_SIZE
* ring
) +
337 genet_dma_ring_regs
[r
]);
340 static inline void bcmgenet_tdma_ring_writel(struct bcmgenet_priv
*priv
,
341 unsigned int ring
, u32 val
,
344 __raw_writel(val
, priv
->base
+ GENET_TDMA_REG_OFF
+
345 (DMA_RING_SIZE
* ring
) +
346 genet_dma_ring_regs
[r
]);
349 static inline u32
bcmgenet_rdma_ring_readl(struct bcmgenet_priv
*priv
,
353 return __raw_readl(priv
->base
+ GENET_RDMA_REG_OFF
+
354 (DMA_RING_SIZE
* ring
) +
355 genet_dma_ring_regs
[r
]);
358 static inline void bcmgenet_rdma_ring_writel(struct bcmgenet_priv
*priv
,
359 unsigned int ring
, u32 val
,
362 __raw_writel(val
, priv
->base
+ GENET_RDMA_REG_OFF
+
363 (DMA_RING_SIZE
* ring
) +
364 genet_dma_ring_regs
[r
]);
367 static int bcmgenet_get_settings(struct net_device
*dev
,
368 struct ethtool_cmd
*cmd
)
370 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
372 if (!netif_running(dev
))
378 return phy_ethtool_gset(priv
->phydev
, cmd
);
381 static int bcmgenet_set_settings(struct net_device
*dev
,
382 struct ethtool_cmd
*cmd
)
384 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
386 if (!netif_running(dev
))
392 return phy_ethtool_sset(priv
->phydev
, cmd
);
395 static int bcmgenet_set_rx_csum(struct net_device
*dev
,
396 netdev_features_t wanted
)
398 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
402 rx_csum_en
= !!(wanted
& NETIF_F_RXCSUM
);
404 rbuf_chk_ctrl
= bcmgenet_rbuf_readl(priv
, RBUF_CHK_CTRL
);
406 /* enable rx checksumming */
408 rbuf_chk_ctrl
|= RBUF_RXCHK_EN
;
410 rbuf_chk_ctrl
&= ~RBUF_RXCHK_EN
;
411 priv
->desc_rxchk_en
= rx_csum_en
;
413 /* If UniMAC forwards CRC, we need to skip over it to get
414 * a valid CHK bit to be set in the per-packet status word
416 if (rx_csum_en
&& priv
->crc_fwd_en
)
417 rbuf_chk_ctrl
|= RBUF_SKIP_FCS
;
419 rbuf_chk_ctrl
&= ~RBUF_SKIP_FCS
;
421 bcmgenet_rbuf_writel(priv
, rbuf_chk_ctrl
, RBUF_CHK_CTRL
);
426 static int bcmgenet_set_tx_csum(struct net_device
*dev
,
427 netdev_features_t wanted
)
429 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
431 u32 tbuf_ctrl
, rbuf_ctrl
;
433 tbuf_ctrl
= bcmgenet_tbuf_ctrl_get(priv
);
434 rbuf_ctrl
= bcmgenet_rbuf_readl(priv
, RBUF_CTRL
);
436 desc_64b_en
= !!(wanted
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
));
438 /* enable 64 bytes descriptor in both directions (RBUF and TBUF) */
440 tbuf_ctrl
|= RBUF_64B_EN
;
441 rbuf_ctrl
|= RBUF_64B_EN
;
443 tbuf_ctrl
&= ~RBUF_64B_EN
;
444 rbuf_ctrl
&= ~RBUF_64B_EN
;
446 priv
->desc_64b_en
= desc_64b_en
;
448 bcmgenet_tbuf_ctrl_set(priv
, tbuf_ctrl
);
449 bcmgenet_rbuf_writel(priv
, rbuf_ctrl
, RBUF_CTRL
);
454 static int bcmgenet_set_features(struct net_device
*dev
,
455 netdev_features_t features
)
457 netdev_features_t changed
= features
^ dev
->features
;
458 netdev_features_t wanted
= dev
->wanted_features
;
461 if (changed
& (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
))
462 ret
= bcmgenet_set_tx_csum(dev
, wanted
);
463 if (changed
& (NETIF_F_RXCSUM
))
464 ret
= bcmgenet_set_rx_csum(dev
, wanted
);
469 static u32
bcmgenet_get_msglevel(struct net_device
*dev
)
471 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
473 return priv
->msg_enable
;
476 static void bcmgenet_set_msglevel(struct net_device
*dev
, u32 level
)
478 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
480 priv
->msg_enable
= level
;
483 /* standard ethtool support functions. */
484 enum bcmgenet_stat_type
{
485 BCMGENET_STAT_NETDEV
= -1,
486 BCMGENET_STAT_MIB_RX
,
487 BCMGENET_STAT_MIB_TX
,
492 struct bcmgenet_stats
{
493 char stat_string
[ETH_GSTRING_LEN
];
496 enum bcmgenet_stat_type type
;
497 /* reg offset from UMAC base for misc counters */
501 #define STAT_NETDEV(m) { \
502 .stat_string = __stringify(m), \
503 .stat_sizeof = sizeof(((struct net_device_stats *)0)->m), \
504 .stat_offset = offsetof(struct net_device_stats, m), \
505 .type = BCMGENET_STAT_NETDEV, \
508 #define STAT_GENET_MIB(str, m, _type) { \
509 .stat_string = str, \
510 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
511 .stat_offset = offsetof(struct bcmgenet_priv, m), \
515 #define STAT_GENET_MIB_RX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_RX)
516 #define STAT_GENET_MIB_TX(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_MIB_TX)
517 #define STAT_GENET_RUNT(str, m) STAT_GENET_MIB(str, m, BCMGENET_STAT_RUNT)
519 #define STAT_GENET_MISC(str, m, offset) { \
520 .stat_string = str, \
521 .stat_sizeof = sizeof(((struct bcmgenet_priv *)0)->m), \
522 .stat_offset = offsetof(struct bcmgenet_priv, m), \
523 .type = BCMGENET_STAT_MISC, \
524 .reg_offset = offset, \
528 /* There is a 0xC gap between the end of RX and beginning of TX stats and then
529 * between the end of TX stats and the beginning of the RX RUNT
531 #define BCMGENET_STAT_OFFSET 0xc
533 /* Hardware counters must be kept in sync because the order/offset
534 * is important here (order in structure declaration = order in hardware)
536 static const struct bcmgenet_stats bcmgenet_gstrings_stats
[] = {
538 STAT_NETDEV(rx_packets
),
539 STAT_NETDEV(tx_packets
),
540 STAT_NETDEV(rx_bytes
),
541 STAT_NETDEV(tx_bytes
),
542 STAT_NETDEV(rx_errors
),
543 STAT_NETDEV(tx_errors
),
544 STAT_NETDEV(rx_dropped
),
545 STAT_NETDEV(tx_dropped
),
546 STAT_NETDEV(multicast
),
547 /* UniMAC RSV counters */
548 STAT_GENET_MIB_RX("rx_64_octets", mib
.rx
.pkt_cnt
.cnt_64
),
549 STAT_GENET_MIB_RX("rx_65_127_oct", mib
.rx
.pkt_cnt
.cnt_127
),
550 STAT_GENET_MIB_RX("rx_128_255_oct", mib
.rx
.pkt_cnt
.cnt_255
),
551 STAT_GENET_MIB_RX("rx_256_511_oct", mib
.rx
.pkt_cnt
.cnt_511
),
552 STAT_GENET_MIB_RX("rx_512_1023_oct", mib
.rx
.pkt_cnt
.cnt_1023
),
553 STAT_GENET_MIB_RX("rx_1024_1518_oct", mib
.rx
.pkt_cnt
.cnt_1518
),
554 STAT_GENET_MIB_RX("rx_vlan_1519_1522_oct", mib
.rx
.pkt_cnt
.cnt_mgv
),
555 STAT_GENET_MIB_RX("rx_1522_2047_oct", mib
.rx
.pkt_cnt
.cnt_2047
),
556 STAT_GENET_MIB_RX("rx_2048_4095_oct", mib
.rx
.pkt_cnt
.cnt_4095
),
557 STAT_GENET_MIB_RX("rx_4096_9216_oct", mib
.rx
.pkt_cnt
.cnt_9216
),
558 STAT_GENET_MIB_RX("rx_pkts", mib
.rx
.pkt
),
559 STAT_GENET_MIB_RX("rx_bytes", mib
.rx
.bytes
),
560 STAT_GENET_MIB_RX("rx_multicast", mib
.rx
.mca
),
561 STAT_GENET_MIB_RX("rx_broadcast", mib
.rx
.bca
),
562 STAT_GENET_MIB_RX("rx_fcs", mib
.rx
.fcs
),
563 STAT_GENET_MIB_RX("rx_control", mib
.rx
.cf
),
564 STAT_GENET_MIB_RX("rx_pause", mib
.rx
.pf
),
565 STAT_GENET_MIB_RX("rx_unknown", mib
.rx
.uo
),
566 STAT_GENET_MIB_RX("rx_align", mib
.rx
.aln
),
567 STAT_GENET_MIB_RX("rx_outrange", mib
.rx
.flr
),
568 STAT_GENET_MIB_RX("rx_code", mib
.rx
.cde
),
569 STAT_GENET_MIB_RX("rx_carrier", mib
.rx
.fcr
),
570 STAT_GENET_MIB_RX("rx_oversize", mib
.rx
.ovr
),
571 STAT_GENET_MIB_RX("rx_jabber", mib
.rx
.jbr
),
572 STAT_GENET_MIB_RX("rx_mtu_err", mib
.rx
.mtue
),
573 STAT_GENET_MIB_RX("rx_good_pkts", mib
.rx
.pok
),
574 STAT_GENET_MIB_RX("rx_unicast", mib
.rx
.uc
),
575 STAT_GENET_MIB_RX("rx_ppp", mib
.rx
.ppp
),
576 STAT_GENET_MIB_RX("rx_crc", mib
.rx
.rcrc
),
577 /* UniMAC TSV counters */
578 STAT_GENET_MIB_TX("tx_64_octets", mib
.tx
.pkt_cnt
.cnt_64
),
579 STAT_GENET_MIB_TX("tx_65_127_oct", mib
.tx
.pkt_cnt
.cnt_127
),
580 STAT_GENET_MIB_TX("tx_128_255_oct", mib
.tx
.pkt_cnt
.cnt_255
),
581 STAT_GENET_MIB_TX("tx_256_511_oct", mib
.tx
.pkt_cnt
.cnt_511
),
582 STAT_GENET_MIB_TX("tx_512_1023_oct", mib
.tx
.pkt_cnt
.cnt_1023
),
583 STAT_GENET_MIB_TX("tx_1024_1518_oct", mib
.tx
.pkt_cnt
.cnt_1518
),
584 STAT_GENET_MIB_TX("tx_vlan_1519_1522_oct", mib
.tx
.pkt_cnt
.cnt_mgv
),
585 STAT_GENET_MIB_TX("tx_1522_2047_oct", mib
.tx
.pkt_cnt
.cnt_2047
),
586 STAT_GENET_MIB_TX("tx_2048_4095_oct", mib
.tx
.pkt_cnt
.cnt_4095
),
587 STAT_GENET_MIB_TX("tx_4096_9216_oct", mib
.tx
.pkt_cnt
.cnt_9216
),
588 STAT_GENET_MIB_TX("tx_pkts", mib
.tx
.pkts
),
589 STAT_GENET_MIB_TX("tx_multicast", mib
.tx
.mca
),
590 STAT_GENET_MIB_TX("tx_broadcast", mib
.tx
.bca
),
591 STAT_GENET_MIB_TX("tx_pause", mib
.tx
.pf
),
592 STAT_GENET_MIB_TX("tx_control", mib
.tx
.cf
),
593 STAT_GENET_MIB_TX("tx_fcs_err", mib
.tx
.fcs
),
594 STAT_GENET_MIB_TX("tx_oversize", mib
.tx
.ovr
),
595 STAT_GENET_MIB_TX("tx_defer", mib
.tx
.drf
),
596 STAT_GENET_MIB_TX("tx_excess_defer", mib
.tx
.edf
),
597 STAT_GENET_MIB_TX("tx_single_col", mib
.tx
.scl
),
598 STAT_GENET_MIB_TX("tx_multi_col", mib
.tx
.mcl
),
599 STAT_GENET_MIB_TX("tx_late_col", mib
.tx
.lcl
),
600 STAT_GENET_MIB_TX("tx_excess_col", mib
.tx
.ecl
),
601 STAT_GENET_MIB_TX("tx_frags", mib
.tx
.frg
),
602 STAT_GENET_MIB_TX("tx_total_col", mib
.tx
.ncl
),
603 STAT_GENET_MIB_TX("tx_jabber", mib
.tx
.jbr
),
604 STAT_GENET_MIB_TX("tx_bytes", mib
.tx
.bytes
),
605 STAT_GENET_MIB_TX("tx_good_pkts", mib
.tx
.pok
),
606 STAT_GENET_MIB_TX("tx_unicast", mib
.tx
.uc
),
607 /* UniMAC RUNT counters */
608 STAT_GENET_RUNT("rx_runt_pkts", mib
.rx_runt_cnt
),
609 STAT_GENET_RUNT("rx_runt_valid_fcs", mib
.rx_runt_fcs
),
610 STAT_GENET_RUNT("rx_runt_inval_fcs_align", mib
.rx_runt_fcs_align
),
611 STAT_GENET_RUNT("rx_runt_bytes", mib
.rx_runt_bytes
),
612 /* Misc UniMAC counters */
613 STAT_GENET_MISC("rbuf_ovflow_cnt", mib
.rbuf_ovflow_cnt
,
615 STAT_GENET_MISC("rbuf_err_cnt", mib
.rbuf_err_cnt
, UMAC_RBUF_ERR_CNT
),
616 STAT_GENET_MISC("mdf_err_cnt", mib
.mdf_err_cnt
, UMAC_MDF_ERR_CNT
),
617 STAT_GENET_MIB_RX("alloc_rx_buff_failed", mib
.alloc_rx_buff_failed
),
618 STAT_GENET_MIB_RX("rx_dma_failed", mib
.rx_dma_failed
),
619 STAT_GENET_MIB_TX("tx_dma_failed", mib
.tx_dma_failed
),
622 #define BCMGENET_STATS_LEN ARRAY_SIZE(bcmgenet_gstrings_stats)
624 static void bcmgenet_get_drvinfo(struct net_device
*dev
,
625 struct ethtool_drvinfo
*info
)
627 strlcpy(info
->driver
, "bcmgenet", sizeof(info
->driver
));
628 strlcpy(info
->version
, "v2.0", sizeof(info
->version
));
629 info
->n_stats
= BCMGENET_STATS_LEN
;
632 static int bcmgenet_get_sset_count(struct net_device
*dev
, int string_set
)
634 switch (string_set
) {
636 return BCMGENET_STATS_LEN
;
642 static void bcmgenet_get_strings(struct net_device
*dev
, u32 stringset
,
649 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
650 memcpy(data
+ i
* ETH_GSTRING_LEN
,
651 bcmgenet_gstrings_stats
[i
].stat_string
,
658 static void bcmgenet_update_mib_counters(struct bcmgenet_priv
*priv
)
662 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
663 const struct bcmgenet_stats
*s
;
668 s
= &bcmgenet_gstrings_stats
[i
];
670 case BCMGENET_STAT_NETDEV
:
672 case BCMGENET_STAT_MIB_RX
:
673 case BCMGENET_STAT_MIB_TX
:
674 case BCMGENET_STAT_RUNT
:
675 if (s
->type
!= BCMGENET_STAT_MIB_RX
)
676 offset
= BCMGENET_STAT_OFFSET
;
677 val
= bcmgenet_umac_readl(priv
,
678 UMAC_MIB_START
+ j
+ offset
);
680 case BCMGENET_STAT_MISC
:
681 val
= bcmgenet_umac_readl(priv
, s
->reg_offset
);
682 /* clear if overflowed */
684 bcmgenet_umac_writel(priv
, 0, s
->reg_offset
);
689 p
= (char *)priv
+ s
->stat_offset
;
694 static void bcmgenet_get_ethtool_stats(struct net_device
*dev
,
695 struct ethtool_stats
*stats
,
698 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
701 if (netif_running(dev
))
702 bcmgenet_update_mib_counters(priv
);
704 for (i
= 0; i
< BCMGENET_STATS_LEN
; i
++) {
705 const struct bcmgenet_stats
*s
;
708 s
= &bcmgenet_gstrings_stats
[i
];
709 if (s
->type
== BCMGENET_STAT_NETDEV
)
710 p
= (char *)&dev
->stats
;
718 static void bcmgenet_eee_enable_set(struct net_device
*dev
, bool enable
)
720 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
721 u32 off
= priv
->hw_params
->tbuf_offset
+ TBUF_ENERGY_CTRL
;
724 if (enable
&& !priv
->clk_eee_enabled
) {
725 clk_prepare_enable(priv
->clk_eee
);
726 priv
->clk_eee_enabled
= true;
729 reg
= bcmgenet_umac_readl(priv
, UMAC_EEE_CTRL
);
734 bcmgenet_umac_writel(priv
, reg
, UMAC_EEE_CTRL
);
736 /* Enable EEE and switch to a 27Mhz clock automatically */
737 reg
= __raw_readl(priv
->base
+ off
);
739 reg
|= TBUF_EEE_EN
| TBUF_PM_EN
;
741 reg
&= ~(TBUF_EEE_EN
| TBUF_PM_EN
);
742 __raw_writel(reg
, priv
->base
+ off
);
744 /* Do the same for thing for RBUF */
745 reg
= bcmgenet_rbuf_readl(priv
, RBUF_ENERGY_CTRL
);
747 reg
|= RBUF_EEE_EN
| RBUF_PM_EN
;
749 reg
&= ~(RBUF_EEE_EN
| RBUF_PM_EN
);
750 bcmgenet_rbuf_writel(priv
, reg
, RBUF_ENERGY_CTRL
);
752 if (!enable
&& priv
->clk_eee_enabled
) {
753 clk_disable_unprepare(priv
->clk_eee
);
754 priv
->clk_eee_enabled
= false;
757 priv
->eee
.eee_enabled
= enable
;
758 priv
->eee
.eee_active
= enable
;
761 static int bcmgenet_get_eee(struct net_device
*dev
, struct ethtool_eee
*e
)
763 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
764 struct ethtool_eee
*p
= &priv
->eee
;
766 if (GENET_IS_V1(priv
))
769 e
->eee_enabled
= p
->eee_enabled
;
770 e
->eee_active
= p
->eee_active
;
771 e
->tx_lpi_timer
= bcmgenet_umac_readl(priv
, UMAC_EEE_LPI_TIMER
);
773 return phy_ethtool_get_eee(priv
->phydev
, e
);
776 static int bcmgenet_set_eee(struct net_device
*dev
, struct ethtool_eee
*e
)
778 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
779 struct ethtool_eee
*p
= &priv
->eee
;
782 if (GENET_IS_V1(priv
))
785 p
->eee_enabled
= e
->eee_enabled
;
787 if (!p
->eee_enabled
) {
788 bcmgenet_eee_enable_set(dev
, false);
790 ret
= phy_init_eee(priv
->phydev
, 0);
792 netif_err(priv
, hw
, dev
, "EEE initialization failed\n");
796 bcmgenet_umac_writel(priv
, e
->tx_lpi_timer
, UMAC_EEE_LPI_TIMER
);
797 bcmgenet_eee_enable_set(dev
, true);
800 return phy_ethtool_set_eee(priv
->phydev
, e
);
803 static int bcmgenet_nway_reset(struct net_device
*dev
)
805 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
807 return genphy_restart_aneg(priv
->phydev
);
810 /* standard ethtool support functions. */
811 static struct ethtool_ops bcmgenet_ethtool_ops
= {
812 .get_strings
= bcmgenet_get_strings
,
813 .get_sset_count
= bcmgenet_get_sset_count
,
814 .get_ethtool_stats
= bcmgenet_get_ethtool_stats
,
815 .get_settings
= bcmgenet_get_settings
,
816 .set_settings
= bcmgenet_set_settings
,
817 .get_drvinfo
= bcmgenet_get_drvinfo
,
818 .get_link
= ethtool_op_get_link
,
819 .get_msglevel
= bcmgenet_get_msglevel
,
820 .set_msglevel
= bcmgenet_set_msglevel
,
821 .get_wol
= bcmgenet_get_wol
,
822 .set_wol
= bcmgenet_set_wol
,
823 .get_eee
= bcmgenet_get_eee
,
824 .set_eee
= bcmgenet_set_eee
,
825 .nway_reset
= bcmgenet_nway_reset
,
828 /* Power down the unimac, based on mode. */
829 static void bcmgenet_power_down(struct bcmgenet_priv
*priv
,
830 enum bcmgenet_power_mode mode
)
835 case GENET_POWER_CABLE_SENSE
:
836 phy_detach(priv
->phydev
);
839 case GENET_POWER_WOL_MAGIC
:
840 bcmgenet_wol_power_down_cfg(priv
, mode
);
843 case GENET_POWER_PASSIVE
:
845 if (priv
->hw_params
->flags
& GENET_HAS_EXT
) {
846 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
847 reg
|= (EXT_PWR_DOWN_PHY
|
848 EXT_PWR_DOWN_DLL
| EXT_PWR_DOWN_BIAS
);
849 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
857 static void bcmgenet_power_up(struct bcmgenet_priv
*priv
,
858 enum bcmgenet_power_mode mode
)
862 if (!(priv
->hw_params
->flags
& GENET_HAS_EXT
))
865 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
868 case GENET_POWER_PASSIVE
:
869 reg
&= ~(EXT_PWR_DOWN_DLL
| EXT_PWR_DOWN_PHY
|
872 case GENET_POWER_CABLE_SENSE
:
874 reg
|= EXT_PWR_DN_EN_LD
;
876 case GENET_POWER_WOL_MAGIC
:
877 bcmgenet_wol_power_up_cfg(priv
, mode
);
883 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
885 if (mode
== GENET_POWER_PASSIVE
)
886 bcmgenet_mii_reset(priv
->dev
);
889 /* ioctl handle special commands that are not present in ethtool. */
890 static int bcmgenet_ioctl(struct net_device
*dev
, struct ifreq
*rq
, int cmd
)
892 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
895 if (!netif_running(dev
))
905 val
= phy_mii_ioctl(priv
->phydev
, rq
, cmd
);
916 static struct enet_cb
*bcmgenet_get_txcb(struct bcmgenet_priv
*priv
,
917 struct bcmgenet_tx_ring
*ring
)
919 struct enet_cb
*tx_cb_ptr
;
921 tx_cb_ptr
= ring
->cbs
;
922 tx_cb_ptr
+= ring
->write_ptr
- ring
->cb_ptr
;
923 tx_cb_ptr
->bd_addr
= priv
->tx_bds
+ ring
->write_ptr
* DMA_DESC_SIZE
;
924 /* Advancing local write pointer */
925 if (ring
->write_ptr
== ring
->end_ptr
)
926 ring
->write_ptr
= ring
->cb_ptr
;
933 /* Simple helper to free a control block's resources */
934 static void bcmgenet_free_cb(struct enet_cb
*cb
)
936 dev_kfree_skb_any(cb
->skb
);
938 dma_unmap_addr_set(cb
, dma_addr
, 0);
941 static inline void bcmgenet_tx_ring16_int_disable(struct bcmgenet_priv
*priv
,
942 struct bcmgenet_tx_ring
*ring
)
944 bcmgenet_intrl2_0_writel(priv
,
945 UMAC_IRQ_TXDMA_BDONE
| UMAC_IRQ_TXDMA_PDONE
,
946 INTRL2_CPU_MASK_SET
);
949 static inline void bcmgenet_tx_ring16_int_enable(struct bcmgenet_priv
*priv
,
950 struct bcmgenet_tx_ring
*ring
)
952 bcmgenet_intrl2_0_writel(priv
,
953 UMAC_IRQ_TXDMA_BDONE
| UMAC_IRQ_TXDMA_PDONE
,
954 INTRL2_CPU_MASK_CLEAR
);
957 static inline void bcmgenet_tx_ring_int_enable(struct bcmgenet_priv
*priv
,
958 struct bcmgenet_tx_ring
*ring
)
960 bcmgenet_intrl2_1_writel(priv
, (1 << ring
->index
),
961 INTRL2_CPU_MASK_CLEAR
);
962 priv
->int1_mask
&= ~(1 << ring
->index
);
965 static inline void bcmgenet_tx_ring_int_disable(struct bcmgenet_priv
*priv
,
966 struct bcmgenet_tx_ring
*ring
)
968 bcmgenet_intrl2_1_writel(priv
, (1 << ring
->index
),
969 INTRL2_CPU_MASK_SET
);
970 priv
->int1_mask
|= (1 << ring
->index
);
973 /* Unlocked version of the reclaim routine */
974 static void __bcmgenet_tx_reclaim(struct net_device
*dev
,
975 struct bcmgenet_tx_ring
*ring
)
977 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
978 int last_tx_cn
, last_c_index
, num_tx_bds
;
979 struct enet_cb
*tx_cb_ptr
;
980 struct netdev_queue
*txq
;
981 unsigned int bds_compl
;
982 unsigned int c_index
;
984 /* Compute how many buffers are transmitted since last xmit call */
985 c_index
= bcmgenet_tdma_ring_readl(priv
, ring
->index
, TDMA_CONS_INDEX
);
986 txq
= netdev_get_tx_queue(dev
, ring
->queue
);
988 last_c_index
= ring
->c_index
;
989 num_tx_bds
= ring
->size
;
991 c_index
&= (num_tx_bds
- 1);
993 if (c_index
>= last_c_index
)
994 last_tx_cn
= c_index
- last_c_index
;
996 last_tx_cn
= num_tx_bds
- last_c_index
+ c_index
;
998 netif_dbg(priv
, tx_done
, dev
,
999 "%s ring=%d index=%d last_tx_cn=%d last_index=%d\n",
1000 __func__
, ring
->index
,
1001 c_index
, last_tx_cn
, last_c_index
);
1003 /* Reclaim transmitted buffers */
1004 while (last_tx_cn
-- > 0) {
1005 tx_cb_ptr
= ring
->cbs
+ last_c_index
;
1007 if (tx_cb_ptr
->skb
) {
1008 bds_compl
= skb_shinfo(tx_cb_ptr
->skb
)->nr_frags
+ 1;
1009 dev
->stats
.tx_bytes
+= tx_cb_ptr
->skb
->len
;
1010 dma_unmap_single(&dev
->dev
,
1011 dma_unmap_addr(tx_cb_ptr
, dma_addr
),
1012 tx_cb_ptr
->skb
->len
,
1014 bcmgenet_free_cb(tx_cb_ptr
);
1015 } else if (dma_unmap_addr(tx_cb_ptr
, dma_addr
)) {
1016 dev
->stats
.tx_bytes
+=
1017 dma_unmap_len(tx_cb_ptr
, dma_len
);
1018 dma_unmap_page(&dev
->dev
,
1019 dma_unmap_addr(tx_cb_ptr
, dma_addr
),
1020 dma_unmap_len(tx_cb_ptr
, dma_len
),
1022 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, 0);
1024 dev
->stats
.tx_packets
++;
1025 ring
->free_bds
+= bds_compl
;
1028 last_c_index
&= (num_tx_bds
- 1);
1031 if (ring
->free_bds
> (MAX_SKB_FRAGS
+ 1))
1032 ring
->int_disable(priv
, ring
);
1034 if (netif_tx_queue_stopped(txq
))
1035 netif_tx_wake_queue(txq
);
1037 ring
->c_index
= c_index
;
1040 static void bcmgenet_tx_reclaim(struct net_device
*dev
,
1041 struct bcmgenet_tx_ring
*ring
)
1043 unsigned long flags
;
1045 spin_lock_irqsave(&ring
->lock
, flags
);
1046 __bcmgenet_tx_reclaim(dev
, ring
);
1047 spin_unlock_irqrestore(&ring
->lock
, flags
);
1050 static void bcmgenet_tx_reclaim_all(struct net_device
*dev
)
1052 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1055 if (netif_is_multiqueue(dev
)) {
1056 for (i
= 0; i
< priv
->hw_params
->tx_queues
; i
++)
1057 bcmgenet_tx_reclaim(dev
, &priv
->tx_rings
[i
]);
1060 bcmgenet_tx_reclaim(dev
, &priv
->tx_rings
[DESC_INDEX
]);
1063 /* Transmits a single SKB (either head of a fragment or a single SKB)
1064 * caller must hold priv->lock
1066 static int bcmgenet_xmit_single(struct net_device
*dev
,
1067 struct sk_buff
*skb
,
1069 struct bcmgenet_tx_ring
*ring
)
1071 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1072 struct device
*kdev
= &priv
->pdev
->dev
;
1073 struct enet_cb
*tx_cb_ptr
;
1074 unsigned int skb_len
;
1079 tx_cb_ptr
= bcmgenet_get_txcb(priv
, ring
);
1081 if (unlikely(!tx_cb_ptr
))
1084 tx_cb_ptr
->skb
= skb
;
1086 skb_len
= skb_headlen(skb
) < ETH_ZLEN
? ETH_ZLEN
: skb_headlen(skb
);
1088 mapping
= dma_map_single(kdev
, skb
->data
, skb_len
, DMA_TO_DEVICE
);
1089 ret
= dma_mapping_error(kdev
, mapping
);
1091 priv
->mib
.tx_dma_failed
++;
1092 netif_err(priv
, tx_err
, dev
, "Tx DMA map failed\n");
1097 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, mapping
);
1098 dma_unmap_len_set(tx_cb_ptr
, dma_len
, skb
->len
);
1099 length_status
= (skb_len
<< DMA_BUFLENGTH_SHIFT
) | dma_desc_flags
|
1100 (priv
->hw_params
->qtag_mask
<< DMA_TX_QTAG_SHIFT
) |
1103 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1104 length_status
|= DMA_TX_DO_CSUM
;
1106 dmadesc_set(priv
, tx_cb_ptr
->bd_addr
, mapping
, length_status
);
1108 /* Decrement total BD count and advance our write pointer */
1109 ring
->free_bds
-= 1;
1110 ring
->prod_index
+= 1;
1111 ring
->prod_index
&= DMA_P_INDEX_MASK
;
1116 /* Transmit a SKB fragment */
1117 static int bcmgenet_xmit_frag(struct net_device
*dev
,
1120 struct bcmgenet_tx_ring
*ring
)
1122 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1123 struct device
*kdev
= &priv
->pdev
->dev
;
1124 struct enet_cb
*tx_cb_ptr
;
1128 tx_cb_ptr
= bcmgenet_get_txcb(priv
, ring
);
1130 if (unlikely(!tx_cb_ptr
))
1132 tx_cb_ptr
->skb
= NULL
;
1134 mapping
= skb_frag_dma_map(kdev
, frag
, 0,
1135 skb_frag_size(frag
), DMA_TO_DEVICE
);
1136 ret
= dma_mapping_error(kdev
, mapping
);
1138 priv
->mib
.tx_dma_failed
++;
1139 netif_err(priv
, tx_err
, dev
, "%s: Tx DMA map failed\n",
1144 dma_unmap_addr_set(tx_cb_ptr
, dma_addr
, mapping
);
1145 dma_unmap_len_set(tx_cb_ptr
, dma_len
, frag
->size
);
1147 dmadesc_set(priv
, tx_cb_ptr
->bd_addr
, mapping
,
1148 (frag
->size
<< DMA_BUFLENGTH_SHIFT
) | dma_desc_flags
|
1149 (priv
->hw_params
->qtag_mask
<< DMA_TX_QTAG_SHIFT
));
1152 ring
->free_bds
-= 1;
1153 ring
->prod_index
+= 1;
1154 ring
->prod_index
&= DMA_P_INDEX_MASK
;
1159 /* Reallocate the SKB to put enough headroom in front of it and insert
1160 * the transmit checksum offsets in the descriptors
1162 static struct sk_buff
*bcmgenet_put_tx_csum(struct net_device
*dev
,
1163 struct sk_buff
*skb
)
1165 struct status_64
*status
= NULL
;
1166 struct sk_buff
*new_skb
;
1172 if (unlikely(skb_headroom(skb
) < sizeof(*status
))) {
1173 /* If 64 byte status block enabled, must make sure skb has
1174 * enough headroom for us to insert 64B status block.
1176 new_skb
= skb_realloc_headroom(skb
, sizeof(*status
));
1179 dev
->stats
.tx_errors
++;
1180 dev
->stats
.tx_dropped
++;
1186 skb_push(skb
, sizeof(*status
));
1187 status
= (struct status_64
*)skb
->data
;
1189 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1190 ip_ver
= htons(skb
->protocol
);
1193 ip_proto
= ip_hdr(skb
)->protocol
;
1196 ip_proto
= ipv6_hdr(skb
)->nexthdr
;
1202 offset
= skb_checksum_start_offset(skb
) - sizeof(*status
);
1203 tx_csum_info
= (offset
<< STATUS_TX_CSUM_START_SHIFT
) |
1204 (offset
+ skb
->csum_offset
);
1206 /* Set the length valid bit for TCP and UDP and just set
1207 * the special UDP flag for IPv4, else just set to 0.
1209 if (ip_proto
== IPPROTO_TCP
|| ip_proto
== IPPROTO_UDP
) {
1210 tx_csum_info
|= STATUS_TX_CSUM_LV
;
1211 if (ip_proto
== IPPROTO_UDP
&& ip_ver
== ETH_P_IP
)
1212 tx_csum_info
|= STATUS_TX_CSUM_PROTO_UDP
;
1217 status
->tx_csum_info
= tx_csum_info
;
1223 static netdev_tx_t
bcmgenet_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
1225 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1226 struct bcmgenet_tx_ring
*ring
= NULL
;
1227 struct netdev_queue
*txq
;
1228 unsigned long flags
= 0;
1229 int nr_frags
, index
;
1234 index
= skb_get_queue_mapping(skb
);
1235 /* Mapping strategy:
1236 * queue_mapping = 0, unclassified, packet xmited through ring16
1237 * queue_mapping = 1, goes to ring 0. (highest priority queue
1238 * queue_mapping = 2, goes to ring 1.
1239 * queue_mapping = 3, goes to ring 2.
1240 * queue_mapping = 4, goes to ring 3.
1247 nr_frags
= skb_shinfo(skb
)->nr_frags
;
1248 ring
= &priv
->tx_rings
[index
];
1249 txq
= netdev_get_tx_queue(dev
, ring
->queue
);
1251 spin_lock_irqsave(&ring
->lock
, flags
);
1252 if (ring
->free_bds
<= nr_frags
+ 1) {
1253 netif_tx_stop_queue(txq
);
1254 netdev_err(dev
, "%s: tx ring %d full when queue %d awake\n",
1255 __func__
, index
, ring
->queue
);
1256 ret
= NETDEV_TX_BUSY
;
1260 if (skb_padto(skb
, ETH_ZLEN
)) {
1265 /* set the SKB transmit checksum */
1266 if (priv
->desc_64b_en
) {
1267 skb
= bcmgenet_put_tx_csum(dev
, skb
);
1274 dma_desc_flags
= DMA_SOP
;
1276 dma_desc_flags
|= DMA_EOP
;
1278 /* Transmit single SKB or head of fragment list */
1279 ret
= bcmgenet_xmit_single(dev
, skb
, dma_desc_flags
, ring
);
1286 for (i
= 0; i
< nr_frags
; i
++) {
1287 ret
= bcmgenet_xmit_frag(dev
,
1288 &skb_shinfo(skb
)->frags
[i
],
1289 (i
== nr_frags
- 1) ? DMA_EOP
: 0,
1297 skb_tx_timestamp(skb
);
1299 /* we kept a software copy of how much we should advance the TDMA
1300 * producer index, now write it down to the hardware
1302 bcmgenet_tdma_ring_writel(priv
, ring
->index
,
1303 ring
->prod_index
, TDMA_PROD_INDEX
);
1305 if (ring
->free_bds
<= (MAX_SKB_FRAGS
+ 1)) {
1306 netif_tx_stop_queue(txq
);
1307 ring
->int_enable(priv
, ring
);
1311 spin_unlock_irqrestore(&ring
->lock
, flags
);
1317 static int bcmgenet_rx_refill(struct bcmgenet_priv
*priv
, struct enet_cb
*cb
)
1319 struct device
*kdev
= &priv
->pdev
->dev
;
1320 struct sk_buff
*skb
;
1324 skb
= netdev_alloc_skb(priv
->dev
, priv
->rx_buf_len
+ SKB_ALIGNMENT
);
1328 /* a caller did not release this control block */
1329 WARN_ON(cb
->skb
!= NULL
);
1331 mapping
= dma_map_single(kdev
, skb
->data
,
1332 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1333 ret
= dma_mapping_error(kdev
, mapping
);
1335 priv
->mib
.rx_dma_failed
++;
1336 bcmgenet_free_cb(cb
);
1337 netif_err(priv
, rx_err
, priv
->dev
,
1338 "%s DMA map failed\n", __func__
);
1342 dma_unmap_addr_set(cb
, dma_addr
, mapping
);
1343 /* assign packet, prepare descriptor, and advance pointer */
1345 dmadesc_set_addr(priv
, priv
->rx_bd_assign_ptr
, mapping
);
1347 /* turn on the newly assigned BD for DMA to use */
1348 priv
->rx_bd_assign_index
++;
1349 priv
->rx_bd_assign_index
&= (priv
->num_rx_bds
- 1);
1351 priv
->rx_bd_assign_ptr
= priv
->rx_bds
+
1352 (priv
->rx_bd_assign_index
* DMA_DESC_SIZE
);
1357 /* bcmgenet_desc_rx - descriptor based rx process.
1358 * this could be called from bottom half, or from NAPI polling method.
1360 static unsigned int bcmgenet_desc_rx(struct bcmgenet_priv
*priv
,
1361 unsigned int budget
)
1363 struct net_device
*dev
= priv
->dev
;
1365 struct sk_buff
*skb
;
1366 u32 dma_length_status
;
1367 unsigned long dma_flag
;
1369 unsigned int rxpktprocessed
= 0, rxpkttoprocess
;
1370 unsigned int p_index
;
1371 unsigned int chksum_ok
= 0;
1373 p_index
= bcmgenet_rdma_ring_readl(priv
, DESC_INDEX
, RDMA_PROD_INDEX
);
1374 p_index
&= DMA_P_INDEX_MASK
;
1376 if (p_index
< priv
->rx_c_index
)
1377 rxpkttoprocess
= (DMA_C_INDEX_MASK
+ 1) -
1378 priv
->rx_c_index
+ p_index
;
1380 rxpkttoprocess
= p_index
- priv
->rx_c_index
;
1382 netif_dbg(priv
, rx_status
, dev
,
1383 "RDMA: rxpkttoprocess=%d\n", rxpkttoprocess
);
1385 while ((rxpktprocessed
< rxpkttoprocess
) &&
1386 (rxpktprocessed
< budget
)) {
1387 cb
= &priv
->rx_cbs
[priv
->rx_read_ptr
];
1390 /* We do not have a backing SKB, so we do not have a
1391 * corresponding DMA mapping for this incoming packet since
1392 * bcmgenet_rx_refill always either has both skb and mapping or
1395 if (unlikely(!skb
)) {
1396 dev
->stats
.rx_dropped
++;
1397 dev
->stats
.rx_errors
++;
1401 /* Unmap the packet contents such that we can use the
1402 * RSV from the 64 bytes descriptor when enabled and save
1403 * a 32-bits register read
1405 dma_unmap_single(&dev
->dev
, dma_unmap_addr(cb
, dma_addr
),
1406 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1408 if (!priv
->desc_64b_en
) {
1410 dmadesc_get_length_status(priv
,
1412 (priv
->rx_read_ptr
*
1415 struct status_64
*status
;
1417 status
= (struct status_64
*)skb
->data
;
1418 dma_length_status
= status
->length_status
;
1421 /* DMA flags and length are still valid no matter how
1422 * we got the Receive Status Vector (64B RSB or register)
1424 dma_flag
= dma_length_status
& 0xffff;
1425 len
= dma_length_status
>> DMA_BUFLENGTH_SHIFT
;
1427 netif_dbg(priv
, rx_status
, dev
,
1428 "%s:p_ind=%d c_ind=%d read_ptr=%d len_stat=0x%08x\n",
1429 __func__
, p_index
, priv
->rx_c_index
,
1430 priv
->rx_read_ptr
, dma_length_status
);
1432 if (unlikely(!(dma_flag
& DMA_EOP
) || !(dma_flag
& DMA_SOP
))) {
1433 netif_err(priv
, rx_status
, dev
,
1434 "dropping fragmented packet!\n");
1435 dev
->stats
.rx_dropped
++;
1436 dev
->stats
.rx_errors
++;
1437 dev_kfree_skb_any(cb
->skb
);
1442 if (unlikely(dma_flag
& (DMA_RX_CRC_ERROR
|
1447 netif_err(priv
, rx_status
, dev
, "dma_flag=0x%x\n",
1448 (unsigned int)dma_flag
);
1449 if (dma_flag
& DMA_RX_CRC_ERROR
)
1450 dev
->stats
.rx_crc_errors
++;
1451 if (dma_flag
& DMA_RX_OV
)
1452 dev
->stats
.rx_over_errors
++;
1453 if (dma_flag
& DMA_RX_NO
)
1454 dev
->stats
.rx_frame_errors
++;
1455 if (dma_flag
& DMA_RX_LG
)
1456 dev
->stats
.rx_length_errors
++;
1457 dev
->stats
.rx_dropped
++;
1458 dev
->stats
.rx_errors
++;
1460 /* discard the packet and advance consumer index.*/
1461 dev_kfree_skb_any(cb
->skb
);
1464 } /* error packet */
1466 chksum_ok
= (dma_flag
& priv
->dma_rx_chk_bit
) &&
1467 priv
->desc_rxchk_en
;
1470 if (priv
->desc_64b_en
) {
1475 if (likely(chksum_ok
))
1476 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
1478 /* remove hardware 2bytes added for IP alignment */
1482 if (priv
->crc_fwd_en
) {
1483 skb_trim(skb
, len
- ETH_FCS_LEN
);
1487 /*Finish setting up the received SKB and send it to the kernel*/
1488 skb
->protocol
= eth_type_trans(skb
, priv
->dev
);
1489 dev
->stats
.rx_packets
++;
1490 dev
->stats
.rx_bytes
+= len
;
1491 if (dma_flag
& DMA_RX_MULT
)
1492 dev
->stats
.multicast
++;
1495 napi_gro_receive(&priv
->napi
, skb
);
1497 netif_dbg(priv
, rx_status
, dev
, "pushed up to kernel\n");
1499 /* refill RX path on the current control block */
1501 err
= bcmgenet_rx_refill(priv
, cb
);
1503 priv
->mib
.alloc_rx_buff_failed
++;
1504 netif_err(priv
, rx_err
, dev
, "Rx refill failed\n");
1508 priv
->rx_read_ptr
++;
1509 priv
->rx_read_ptr
&= (priv
->num_rx_bds
- 1);
1512 return rxpktprocessed
;
1515 /* Assign skb to RX DMA descriptor. */
1516 static int bcmgenet_alloc_rx_buffers(struct bcmgenet_priv
*priv
)
1522 netif_dbg(priv
, hw
, priv
->dev
, "%s:\n", __func__
);
1524 /* loop here for each buffer needing assign */
1525 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
1526 cb
= &priv
->rx_cbs
[priv
->rx_bd_assign_index
];
1530 ret
= bcmgenet_rx_refill(priv
, cb
);
1538 static void bcmgenet_free_rx_buffers(struct bcmgenet_priv
*priv
)
1543 for (i
= 0; i
< priv
->num_rx_bds
; i
++) {
1544 cb
= &priv
->rx_cbs
[i
];
1546 if (dma_unmap_addr(cb
, dma_addr
)) {
1547 dma_unmap_single(&priv
->dev
->dev
,
1548 dma_unmap_addr(cb
, dma_addr
),
1549 priv
->rx_buf_len
, DMA_FROM_DEVICE
);
1550 dma_unmap_addr_set(cb
, dma_addr
, 0);
1554 bcmgenet_free_cb(cb
);
1558 static void umac_enable_set(struct bcmgenet_priv
*priv
, u32 mask
, bool enable
)
1562 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
1567 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
1569 /* UniMAC stops on a packet boundary, wait for a full-size packet
1573 usleep_range(1000, 2000);
1576 static int reset_umac(struct bcmgenet_priv
*priv
)
1578 struct device
*kdev
= &priv
->pdev
->dev
;
1579 unsigned int timeout
= 0;
1582 /* 7358a0/7552a0: bad default in RBUF_FLUSH_CTRL.umac_sw_rst */
1583 bcmgenet_rbuf_ctrl_set(priv
, 0);
1586 /* disable MAC while updating its registers */
1587 bcmgenet_umac_writel(priv
, 0, UMAC_CMD
);
1589 /* issue soft reset, wait for it to complete */
1590 bcmgenet_umac_writel(priv
, CMD_SW_RESET
, UMAC_CMD
);
1591 while (timeout
++ < 1000) {
1592 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
1593 if (!(reg
& CMD_SW_RESET
))
1599 if (timeout
== 1000) {
1601 "timeout waiting for MAC to come out of reset\n");
1608 static void bcmgenet_intr_disable(struct bcmgenet_priv
*priv
)
1610 /* Mask all interrupts.*/
1611 bcmgenet_intrl2_0_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_MASK_SET
);
1612 bcmgenet_intrl2_0_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_CLEAR
);
1613 bcmgenet_intrl2_0_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1614 bcmgenet_intrl2_1_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_MASK_SET
);
1615 bcmgenet_intrl2_1_writel(priv
, 0xFFFFFFFF, INTRL2_CPU_CLEAR
);
1616 bcmgenet_intrl2_1_writel(priv
, 0, INTRL2_CPU_MASK_CLEAR
);
1619 static int init_umac(struct bcmgenet_priv
*priv
)
1621 struct device
*kdev
= &priv
->pdev
->dev
;
1623 u32 reg
, cpu_mask_clear
;
1625 dev_dbg(&priv
->pdev
->dev
, "bcmgenet: init_umac\n");
1627 ret
= reset_umac(priv
);
1631 bcmgenet_umac_writel(priv
, 0, UMAC_CMD
);
1632 /* clear tx/rx counter */
1633 bcmgenet_umac_writel(priv
,
1634 MIB_RESET_RX
| MIB_RESET_TX
| MIB_RESET_RUNT
,
1636 bcmgenet_umac_writel(priv
, 0, UMAC_MIB_CTRL
);
1638 bcmgenet_umac_writel(priv
, ENET_MAX_MTU_SIZE
, UMAC_MAX_FRAME_LEN
);
1640 /* init rx registers, enable ip header optimization */
1641 reg
= bcmgenet_rbuf_readl(priv
, RBUF_CTRL
);
1642 reg
|= RBUF_ALIGN_2B
;
1643 bcmgenet_rbuf_writel(priv
, reg
, RBUF_CTRL
);
1645 if (!GENET_IS_V1(priv
) && !GENET_IS_V2(priv
))
1646 bcmgenet_rbuf_writel(priv
, 1, RBUF_TBUF_SIZE_CTRL
);
1648 bcmgenet_intr_disable(priv
);
1650 cpu_mask_clear
= UMAC_IRQ_RXDMA_BDONE
;
1652 dev_dbg(kdev
, "%s:Enabling RXDMA_BDONE interrupt\n", __func__
);
1654 /* Monitor cable plug/unplugged event for internal PHY */
1655 if (phy_is_internal(priv
->phydev
)) {
1656 cpu_mask_clear
|= (UMAC_IRQ_LINK_DOWN
| UMAC_IRQ_LINK_UP
);
1657 } else if (priv
->ext_phy
) {
1658 cpu_mask_clear
|= (UMAC_IRQ_LINK_DOWN
| UMAC_IRQ_LINK_UP
);
1659 } else if (priv
->phy_interface
== PHY_INTERFACE_MODE_MOCA
) {
1660 reg
= bcmgenet_bp_mc_get(priv
);
1661 reg
|= BIT(priv
->hw_params
->bp_in_en_shift
);
1663 /* bp_mask: back pressure mask */
1664 if (netif_is_multiqueue(priv
->dev
))
1665 reg
|= priv
->hw_params
->bp_in_mask
;
1667 reg
&= ~priv
->hw_params
->bp_in_mask
;
1668 bcmgenet_bp_mc_set(priv
, reg
);
1671 /* Enable MDIO interrupts on GENET v3+ */
1672 if (priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
)
1673 cpu_mask_clear
|= UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
;
1675 bcmgenet_intrl2_0_writel(priv
, cpu_mask_clear
, INTRL2_CPU_MASK_CLEAR
);
1677 /* Enable rx/tx engine.*/
1678 dev_dbg(kdev
, "done init umac\n");
1683 /* Initialize all house-keeping variables for a TX ring, along
1684 * with corresponding hardware registers
1686 static void bcmgenet_init_tx_ring(struct bcmgenet_priv
*priv
,
1687 unsigned int index
, unsigned int size
,
1688 unsigned int write_ptr
, unsigned int end_ptr
)
1690 struct bcmgenet_tx_ring
*ring
= &priv
->tx_rings
[index
];
1691 u32 words_per_bd
= WORDS_PER_BD(priv
);
1692 u32 flow_period_val
= 0;
1693 unsigned int first_bd
;
1695 spin_lock_init(&ring
->lock
);
1696 ring
->index
= index
;
1697 if (index
== DESC_INDEX
) {
1699 ring
->int_enable
= bcmgenet_tx_ring16_int_enable
;
1700 ring
->int_disable
= bcmgenet_tx_ring16_int_disable
;
1702 ring
->queue
= index
+ 1;
1703 ring
->int_enable
= bcmgenet_tx_ring_int_enable
;
1704 ring
->int_disable
= bcmgenet_tx_ring_int_disable
;
1706 ring
->cbs
= priv
->tx_cbs
+ write_ptr
;
1709 ring
->free_bds
= size
;
1710 ring
->write_ptr
= write_ptr
;
1711 ring
->cb_ptr
= write_ptr
;
1712 ring
->end_ptr
= end_ptr
- 1;
1713 ring
->prod_index
= 0;
1715 /* Set flow period for ring != 16 */
1716 if (index
!= DESC_INDEX
)
1717 flow_period_val
= ENET_MAX_MTU_SIZE
<< 16;
1719 bcmgenet_tdma_ring_writel(priv
, index
, 0, TDMA_PROD_INDEX
);
1720 bcmgenet_tdma_ring_writel(priv
, index
, 0, TDMA_CONS_INDEX
);
1721 bcmgenet_tdma_ring_writel(priv
, index
, 1, DMA_MBUF_DONE_THRESH
);
1722 /* Disable rate control for now */
1723 bcmgenet_tdma_ring_writel(priv
, index
, flow_period_val
,
1725 /* Unclassified traffic goes to ring 16 */
1726 bcmgenet_tdma_ring_writel(priv
, index
,
1727 ((size
<< DMA_RING_SIZE_SHIFT
) |
1728 RX_BUF_LENGTH
), DMA_RING_BUF_SIZE
);
1730 first_bd
= write_ptr
;
1732 /* Set start and end address, read and write pointers */
1733 bcmgenet_tdma_ring_writel(priv
, index
, first_bd
* words_per_bd
,
1735 bcmgenet_tdma_ring_writel(priv
, index
, first_bd
* words_per_bd
,
1737 bcmgenet_tdma_ring_writel(priv
, index
, first_bd
,
1739 bcmgenet_tdma_ring_writel(priv
, index
, end_ptr
* words_per_bd
- 1,
1743 /* Initialize a RDMA ring */
1744 static int bcmgenet_init_rx_ring(struct bcmgenet_priv
*priv
,
1745 unsigned int index
, unsigned int size
)
1747 u32 words_per_bd
= WORDS_PER_BD(priv
);
1750 priv
->num_rx_bds
= TOTAL_DESC
;
1751 priv
->rx_bds
= priv
->base
+ priv
->hw_params
->rdma_offset
;
1752 priv
->rx_bd_assign_ptr
= priv
->rx_bds
;
1753 priv
->rx_bd_assign_index
= 0;
1754 priv
->rx_c_index
= 0;
1755 priv
->rx_read_ptr
= 0;
1756 priv
->rx_cbs
= kcalloc(priv
->num_rx_bds
, sizeof(struct enet_cb
),
1761 ret
= bcmgenet_alloc_rx_buffers(priv
);
1763 kfree(priv
->rx_cbs
);
1767 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_WRITE_PTR
);
1768 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_PROD_INDEX
);
1769 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_CONS_INDEX
);
1770 bcmgenet_rdma_ring_writel(priv
, index
,
1771 ((size
<< DMA_RING_SIZE_SHIFT
) |
1772 RX_BUF_LENGTH
), DMA_RING_BUF_SIZE
);
1773 bcmgenet_rdma_ring_writel(priv
, index
, 0, DMA_START_ADDR
);
1774 bcmgenet_rdma_ring_writel(priv
, index
,
1775 words_per_bd
* size
- 1, DMA_END_ADDR
);
1776 bcmgenet_rdma_ring_writel(priv
, index
,
1777 (DMA_FC_THRESH_LO
<<
1778 DMA_XOFF_THRESHOLD_SHIFT
) |
1779 DMA_FC_THRESH_HI
, RDMA_XON_XOFF_THRESH
);
1780 bcmgenet_rdma_ring_writel(priv
, index
, 0, RDMA_READ_PTR
);
1785 /* init multi xmit queues, only available for GENET2+
1786 * the queue is partitioned as follows:
1788 * queue 0 - 3 is priority based, each one has 32 descriptors,
1789 * with queue 0 being the highest priority queue.
1791 * queue 16 is the default tx queue with GENET_DEFAULT_BD_CNT
1792 * descriptors: 256 - (number of tx queues * bds per queues) = 128
1795 * The transmit control block pool is then partitioned as following:
1796 * - tx_cbs[0...127] are for queue 16
1797 * - tx_ring_cbs[0] points to tx_cbs[128..159]
1798 * - tx_ring_cbs[1] points to tx_cbs[160..191]
1799 * - tx_ring_cbs[2] points to tx_cbs[192..223]
1800 * - tx_ring_cbs[3] points to tx_cbs[224..255]
1802 static void bcmgenet_init_multiq(struct net_device
*dev
)
1804 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
1805 unsigned int i
, dma_enable
;
1806 u32 reg
, dma_ctrl
, ring_cfg
= 0;
1807 u32 dma_priority
[3] = {0, 0, 0};
1809 if (!netif_is_multiqueue(dev
)) {
1810 netdev_warn(dev
, "called with non multi queue aware HW\n");
1814 dma_ctrl
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1815 dma_enable
= dma_ctrl
& DMA_EN
;
1816 dma_ctrl
&= ~DMA_EN
;
1817 bcmgenet_tdma_writel(priv
, dma_ctrl
, DMA_CTRL
);
1819 /* Enable strict priority arbiter mode */
1820 bcmgenet_tdma_writel(priv
, DMA_ARBITER_SP
, DMA_ARB_CTRL
);
1822 for (i
= 0; i
< priv
->hw_params
->tx_queues
; i
++) {
1823 /* first 64 tx_cbs are reserved for default tx queue
1826 bcmgenet_init_tx_ring(priv
, i
, priv
->hw_params
->bds_cnt
,
1827 i
* priv
->hw_params
->bds_cnt
,
1828 (i
+ 1) * priv
->hw_params
->bds_cnt
);
1830 /* Configure ring as descriptor ring and setup priority */
1832 dma_ctrl
|= 1 << (i
+ DMA_RING_BUF_EN_SHIFT
);
1834 dma_priority
[DMA_PRIO_REG_INDEX(i
)] |=
1835 ((GENET_Q0_PRIORITY
+ i
) << DMA_PRIO_REG_SHIFT(i
));
1838 /* Set ring 16 priority and program the hardware registers */
1839 dma_priority
[DMA_PRIO_REG_INDEX(DESC_INDEX
)] |=
1840 ((GENET_Q0_PRIORITY
+ priv
->hw_params
->tx_queues
) <<
1841 DMA_PRIO_REG_SHIFT(DESC_INDEX
));
1842 bcmgenet_tdma_writel(priv
, dma_priority
[0], DMA_PRIORITY_0
);
1843 bcmgenet_tdma_writel(priv
, dma_priority
[1], DMA_PRIORITY_1
);
1844 bcmgenet_tdma_writel(priv
, dma_priority
[2], DMA_PRIORITY_2
);
1847 reg
= bcmgenet_tdma_readl(priv
, DMA_RING_CFG
);
1849 bcmgenet_tdma_writel(priv
, reg
, DMA_RING_CFG
);
1851 /* Configure ring as descriptor ring and re-enable DMA if enabled */
1852 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1856 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
1859 static int bcmgenet_dma_teardown(struct bcmgenet_priv
*priv
)
1865 /* Disable TDMA to stop add more frames in TX DMA */
1866 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
1868 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
1870 /* Check TDMA status register to confirm TDMA is disabled */
1871 while (timeout
++ < DMA_TIMEOUT_VAL
) {
1872 reg
= bcmgenet_tdma_readl(priv
, DMA_STATUS
);
1873 if (reg
& DMA_DISABLED
)
1879 if (timeout
== DMA_TIMEOUT_VAL
) {
1880 netdev_warn(priv
->dev
, "Timed out while disabling TX DMA\n");
1884 /* Wait 10ms for packet drain in both tx and rx dma */
1885 usleep_range(10000, 20000);
1888 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
1890 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
1893 /* Check RDMA status register to confirm RDMA is disabled */
1894 while (timeout
++ < DMA_TIMEOUT_VAL
) {
1895 reg
= bcmgenet_rdma_readl(priv
, DMA_STATUS
);
1896 if (reg
& DMA_DISABLED
)
1902 if (timeout
== DMA_TIMEOUT_VAL
) {
1903 netdev_warn(priv
->dev
, "Timed out while disabling RX DMA\n");
1910 static void bcmgenet_fini_dma(struct bcmgenet_priv
*priv
)
1915 bcmgenet_dma_teardown(priv
);
1917 for (i
= 0; i
< priv
->num_tx_bds
; i
++) {
1918 if (priv
->tx_cbs
[i
].skb
!= NULL
) {
1919 dev_kfree_skb(priv
->tx_cbs
[i
].skb
);
1920 priv
->tx_cbs
[i
].skb
= NULL
;
1924 bcmgenet_free_rx_buffers(priv
);
1925 kfree(priv
->rx_cbs
);
1926 kfree(priv
->tx_cbs
);
1929 /* init_edma: Initialize DMA control register */
1930 static int bcmgenet_init_dma(struct bcmgenet_priv
*priv
)
1934 netif_dbg(priv
, hw
, priv
->dev
, "bcmgenet: init_edma\n");
1936 /* by default, enable ring 16 (descriptor based) */
1937 ret
= bcmgenet_init_rx_ring(priv
, DESC_INDEX
, TOTAL_DESC
);
1939 netdev_err(priv
->dev
, "failed to initialize RX ring\n");
1944 bcmgenet_rdma_writel(priv
, DMA_MAX_BURST_LENGTH
, DMA_SCB_BURST_SIZE
);
1947 bcmgenet_tdma_writel(priv
, DMA_MAX_BURST_LENGTH
, DMA_SCB_BURST_SIZE
);
1949 /* Initialize common TX ring structures */
1950 priv
->tx_bds
= priv
->base
+ priv
->hw_params
->tdma_offset
;
1951 priv
->num_tx_bds
= TOTAL_DESC
;
1952 priv
->tx_cbs
= kcalloc(priv
->num_tx_bds
, sizeof(struct enet_cb
),
1954 if (!priv
->tx_cbs
) {
1955 bcmgenet_fini_dma(priv
);
1959 /* initialize multi xmit queue */
1960 bcmgenet_init_multiq(priv
->dev
);
1962 /* initialize special ring 16 */
1963 bcmgenet_init_tx_ring(priv
, DESC_INDEX
, GENET_DEFAULT_BD_CNT
,
1964 priv
->hw_params
->tx_queues
*
1965 priv
->hw_params
->bds_cnt
,
1971 /* NAPI polling method*/
1972 static int bcmgenet_poll(struct napi_struct
*napi
, int budget
)
1974 struct bcmgenet_priv
*priv
= container_of(napi
,
1975 struct bcmgenet_priv
, napi
);
1976 unsigned int work_done
;
1979 bcmgenet_tx_reclaim(priv
->dev
, &priv
->tx_rings
[DESC_INDEX
]);
1981 work_done
= bcmgenet_desc_rx(priv
, budget
);
1983 /* Advancing our consumer index*/
1984 priv
->rx_c_index
+= work_done
;
1985 priv
->rx_c_index
&= DMA_C_INDEX_MASK
;
1986 bcmgenet_rdma_ring_writel(priv
, DESC_INDEX
,
1987 priv
->rx_c_index
, RDMA_CONS_INDEX
);
1988 if (work_done
< budget
) {
1989 napi_complete(napi
);
1990 bcmgenet_intrl2_0_writel(priv
, UMAC_IRQ_RXDMA_BDONE
,
1991 INTRL2_CPU_MASK_CLEAR
);
1997 /* Interrupt bottom half */
1998 static void bcmgenet_irq_task(struct work_struct
*work
)
2000 struct bcmgenet_priv
*priv
= container_of(
2001 work
, struct bcmgenet_priv
, bcmgenet_irq_work
);
2003 netif_dbg(priv
, intr
, priv
->dev
, "%s\n", __func__
);
2005 if (priv
->irq0_stat
& UMAC_IRQ_MPD_R
) {
2006 priv
->irq0_stat
&= ~UMAC_IRQ_MPD_R
;
2007 netif_dbg(priv
, wol
, priv
->dev
,
2008 "magic packet detected, waking up\n");
2009 bcmgenet_power_up(priv
, GENET_POWER_WOL_MAGIC
);
2012 /* Link UP/DOWN event */
2013 if ((priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
) &&
2014 (priv
->irq0_stat
& (UMAC_IRQ_LINK_UP
|UMAC_IRQ_LINK_DOWN
))) {
2015 phy_mac_interrupt(priv
->phydev
,
2016 priv
->irq0_stat
& UMAC_IRQ_LINK_UP
);
2017 priv
->irq0_stat
&= ~(UMAC_IRQ_LINK_UP
|UMAC_IRQ_LINK_DOWN
);
2021 /* bcmgenet_isr1: interrupt handler for ring buffer. */
2022 static irqreturn_t
bcmgenet_isr1(int irq
, void *dev_id
)
2024 struct bcmgenet_priv
*priv
= dev_id
;
2027 /* Save irq status for bottom-half processing. */
2029 bcmgenet_intrl2_1_readl(priv
, INTRL2_CPU_STAT
) &
2031 /* clear interrupts */
2032 bcmgenet_intrl2_1_writel(priv
, priv
->irq1_stat
, INTRL2_CPU_CLEAR
);
2034 netif_dbg(priv
, intr
, priv
->dev
,
2035 "%s: IRQ=0x%x\n", __func__
, priv
->irq1_stat
);
2036 /* Check the MBDONE interrupts.
2037 * packet is done, reclaim descriptors
2039 if (priv
->irq1_stat
& 0x0000ffff) {
2041 for (index
= 0; index
< 16; index
++) {
2042 if (priv
->irq1_stat
& (1 << index
))
2043 bcmgenet_tx_reclaim(priv
->dev
,
2044 &priv
->tx_rings
[index
]);
2050 /* bcmgenet_isr0: Handle various interrupts. */
2051 static irqreturn_t
bcmgenet_isr0(int irq
, void *dev_id
)
2053 struct bcmgenet_priv
*priv
= dev_id
;
2055 /* Save irq status for bottom-half processing. */
2057 bcmgenet_intrl2_0_readl(priv
, INTRL2_CPU_STAT
) &
2058 ~bcmgenet_intrl2_0_readl(priv
, INTRL2_CPU_MASK_STATUS
);
2059 /* clear interrupts */
2060 bcmgenet_intrl2_0_writel(priv
, priv
->irq0_stat
, INTRL2_CPU_CLEAR
);
2062 netif_dbg(priv
, intr
, priv
->dev
,
2063 "IRQ=0x%x\n", priv
->irq0_stat
);
2065 if (priv
->irq0_stat
& (UMAC_IRQ_RXDMA_BDONE
| UMAC_IRQ_RXDMA_PDONE
)) {
2066 /* We use NAPI(software interrupt throttling, if
2067 * Rx Descriptor throttling is not used.
2068 * Disable interrupt, will be enabled in the poll method.
2070 if (likely(napi_schedule_prep(&priv
->napi
))) {
2071 bcmgenet_intrl2_0_writel(priv
, UMAC_IRQ_RXDMA_BDONE
,
2072 INTRL2_CPU_MASK_SET
);
2073 __napi_schedule(&priv
->napi
);
2076 if (priv
->irq0_stat
&
2077 (UMAC_IRQ_TXDMA_BDONE
| UMAC_IRQ_TXDMA_PDONE
)) {
2079 bcmgenet_tx_reclaim(priv
->dev
, &priv
->tx_rings
[DESC_INDEX
]);
2081 if (priv
->irq0_stat
& (UMAC_IRQ_PHY_DET_R
|
2082 UMAC_IRQ_PHY_DET_F
|
2084 UMAC_IRQ_LINK_DOWN
|
2088 /* all other interested interrupts handled in bottom half */
2089 schedule_work(&priv
->bcmgenet_irq_work
);
2092 if ((priv
->hw_params
->flags
& GENET_HAS_MDIO_INTR
) &&
2093 priv
->irq0_stat
& (UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
)) {
2094 priv
->irq0_stat
&= ~(UMAC_IRQ_MDIO_DONE
| UMAC_IRQ_MDIO_ERROR
);
2101 static irqreturn_t
bcmgenet_wol_isr(int irq
, void *dev_id
)
2103 struct bcmgenet_priv
*priv
= dev_id
;
2105 pm_wakeup_event(&priv
->pdev
->dev
, 0);
2110 static void bcmgenet_umac_reset(struct bcmgenet_priv
*priv
)
2114 reg
= bcmgenet_rbuf_ctrl_get(priv
);
2116 bcmgenet_rbuf_ctrl_set(priv
, reg
);
2120 bcmgenet_rbuf_ctrl_set(priv
, reg
);
2124 static void bcmgenet_set_hw_addr(struct bcmgenet_priv
*priv
,
2125 unsigned char *addr
)
2127 bcmgenet_umac_writel(priv
, (addr
[0] << 24) | (addr
[1] << 16) |
2128 (addr
[2] << 8) | addr
[3], UMAC_MAC0
);
2129 bcmgenet_umac_writel(priv
, (addr
[4] << 8) | addr
[5], UMAC_MAC1
);
2132 /* Returns a reusable dma control register value */
2133 static u32
bcmgenet_dma_disable(struct bcmgenet_priv
*priv
)
2139 dma_ctrl
= 1 << (DESC_INDEX
+ DMA_RING_BUF_EN_SHIFT
) | DMA_EN
;
2140 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2142 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2144 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2146 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2148 bcmgenet_umac_writel(priv
, 1, UMAC_TX_FLUSH
);
2150 bcmgenet_umac_writel(priv
, 0, UMAC_TX_FLUSH
);
2155 static void bcmgenet_enable_dma(struct bcmgenet_priv
*priv
, u32 dma_ctrl
)
2159 reg
= bcmgenet_rdma_readl(priv
, DMA_CTRL
);
2161 bcmgenet_rdma_writel(priv
, reg
, DMA_CTRL
);
2163 reg
= bcmgenet_tdma_readl(priv
, DMA_CTRL
);
2165 bcmgenet_tdma_writel(priv
, reg
, DMA_CTRL
);
2168 static void bcmgenet_netif_start(struct net_device
*dev
)
2170 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2172 /* Start the network engine */
2173 napi_enable(&priv
->napi
);
2175 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, true);
2177 if (phy_is_internal(priv
->phydev
))
2178 bcmgenet_power_up(priv
, GENET_POWER_PASSIVE
);
2180 netif_tx_start_all_queues(dev
);
2182 phy_start(priv
->phydev
);
2185 static int bcmgenet_open(struct net_device
*dev
)
2187 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2188 unsigned long dma_ctrl
;
2192 netif_dbg(priv
, ifup
, dev
, "bcmgenet_open\n");
2194 /* Turn on the clock */
2195 if (!IS_ERR(priv
->clk
))
2196 clk_prepare_enable(priv
->clk
);
2198 /* take MAC out of reset */
2199 bcmgenet_umac_reset(priv
);
2201 ret
= init_umac(priv
);
2203 goto err_clk_disable
;
2205 /* disable ethernet MAC while updating its registers */
2206 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, false);
2208 /* Make sure we reflect the value of CRC_CMD_FWD */
2209 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
2210 priv
->crc_fwd_en
= !!(reg
& CMD_CRC_FWD
);
2212 bcmgenet_set_hw_addr(priv
, dev
->dev_addr
);
2214 if (phy_is_internal(priv
->phydev
)) {
2215 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
2216 reg
|= EXT_ENERGY_DET_MASK
;
2217 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
2220 /* Disable RX/TX DMA and flush TX queues */
2221 dma_ctrl
= bcmgenet_dma_disable(priv
);
2223 /* Reinitialize TDMA and RDMA and SW housekeeping */
2224 ret
= bcmgenet_init_dma(priv
);
2226 netdev_err(dev
, "failed to initialize DMA\n");
2230 /* Always enable ring 16 - descriptor ring */
2231 bcmgenet_enable_dma(priv
, dma_ctrl
);
2233 ret
= request_irq(priv
->irq0
, bcmgenet_isr0
, IRQF_SHARED
,
2236 netdev_err(dev
, "can't request IRQ %d\n", priv
->irq0
);
2240 ret
= request_irq(priv
->irq1
, bcmgenet_isr1
, IRQF_SHARED
,
2243 netdev_err(dev
, "can't request IRQ %d\n", priv
->irq1
);
2247 /* Re-configure the port multiplexer towards the PHY device */
2248 bcmgenet_mii_config(priv
->dev
, false);
2250 phy_connect_direct(dev
, priv
->phydev
, bcmgenet_mii_setup
,
2251 priv
->phy_interface
);
2253 bcmgenet_netif_start(dev
);
2258 free_irq(priv
->irq0
, dev
);
2260 bcmgenet_fini_dma(priv
);
2262 if (!IS_ERR(priv
->clk
))
2263 clk_disable_unprepare(priv
->clk
);
2267 static void bcmgenet_netif_stop(struct net_device
*dev
)
2269 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2271 netif_tx_stop_all_queues(dev
);
2272 napi_disable(&priv
->napi
);
2273 phy_stop(priv
->phydev
);
2275 bcmgenet_intr_disable(priv
);
2277 /* Wait for pending work items to complete. Since interrupts are
2278 * disabled no new work will be scheduled.
2280 cancel_work_sync(&priv
->bcmgenet_irq_work
);
2282 priv
->old_link
= -1;
2283 priv
->old_speed
= -1;
2284 priv
->old_duplex
= -1;
2285 priv
->old_pause
= -1;
2288 static int bcmgenet_close(struct net_device
*dev
)
2290 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2293 netif_dbg(priv
, ifdown
, dev
, "bcmgenet_close\n");
2295 bcmgenet_netif_stop(dev
);
2297 /* Really kill the PHY state machine and disconnect from it */
2298 phy_disconnect(priv
->phydev
);
2300 /* Disable MAC receive */
2301 umac_enable_set(priv
, CMD_RX_EN
, false);
2303 ret
= bcmgenet_dma_teardown(priv
);
2307 /* Disable MAC transmit. TX DMA disabled have to done before this */
2308 umac_enable_set(priv
, CMD_TX_EN
, false);
2311 bcmgenet_tx_reclaim_all(dev
);
2312 bcmgenet_fini_dma(priv
);
2314 free_irq(priv
->irq0
, priv
);
2315 free_irq(priv
->irq1
, priv
);
2317 if (phy_is_internal(priv
->phydev
))
2318 bcmgenet_power_down(priv
, GENET_POWER_PASSIVE
);
2320 if (!IS_ERR(priv
->clk
))
2321 clk_disable_unprepare(priv
->clk
);
2326 static void bcmgenet_timeout(struct net_device
*dev
)
2328 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2330 netif_dbg(priv
, tx_err
, dev
, "bcmgenet_timeout\n");
2332 dev
->trans_start
= jiffies
;
2334 dev
->stats
.tx_errors
++;
2336 netif_tx_wake_all_queues(dev
);
2339 #define MAX_MC_COUNT 16
2341 static inline void bcmgenet_set_mdf_addr(struct bcmgenet_priv
*priv
,
2342 unsigned char *addr
,
2348 bcmgenet_umac_writel(priv
, addr
[0] << 8 | addr
[1],
2349 UMAC_MDF_ADDR
+ (*i
* 4));
2350 bcmgenet_umac_writel(priv
, addr
[2] << 24 | addr
[3] << 16 |
2351 addr
[4] << 8 | addr
[5],
2352 UMAC_MDF_ADDR
+ ((*i
+ 1) * 4));
2353 reg
= bcmgenet_umac_readl(priv
, UMAC_MDF_CTRL
);
2354 reg
|= (1 << (MAX_MC_COUNT
- *mc
));
2355 bcmgenet_umac_writel(priv
, reg
, UMAC_MDF_CTRL
);
2360 static void bcmgenet_set_rx_mode(struct net_device
*dev
)
2362 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2363 struct netdev_hw_addr
*ha
;
2367 netif_dbg(priv
, hw
, dev
, "%s: %08X\n", __func__
, dev
->flags
);
2369 /* Promiscuous mode */
2370 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
2371 if (dev
->flags
& IFF_PROMISC
) {
2373 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
2374 bcmgenet_umac_writel(priv
, 0, UMAC_MDF_CTRL
);
2377 reg
&= ~CMD_PROMISC
;
2378 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
2381 /* UniMac doesn't support ALLMULTI */
2382 if (dev
->flags
& IFF_ALLMULTI
) {
2383 netdev_warn(dev
, "ALLMULTI is not supported\n");
2387 /* update MDF filter */
2391 bcmgenet_set_mdf_addr(priv
, dev
->broadcast
, &i
, &mc
);
2392 /* my own address.*/
2393 bcmgenet_set_mdf_addr(priv
, dev
->dev_addr
, &i
, &mc
);
2395 if (netdev_uc_count(dev
) > (MAX_MC_COUNT
- mc
))
2398 if (!netdev_uc_empty(dev
))
2399 netdev_for_each_uc_addr(ha
, dev
)
2400 bcmgenet_set_mdf_addr(priv
, ha
->addr
, &i
, &mc
);
2402 if (netdev_mc_empty(dev
) || netdev_mc_count(dev
) >= (MAX_MC_COUNT
- mc
))
2405 netdev_for_each_mc_addr(ha
, dev
)
2406 bcmgenet_set_mdf_addr(priv
, ha
->addr
, &i
, &mc
);
2409 /* Set the hardware MAC address. */
2410 static int bcmgenet_set_mac_addr(struct net_device
*dev
, void *p
)
2412 struct sockaddr
*addr
= p
;
2414 /* Setting the MAC address at the hardware level is not possible
2415 * without disabling the UniMAC RX/TX enable bits.
2417 if (netif_running(dev
))
2420 ether_addr_copy(dev
->dev_addr
, addr
->sa_data
);
2425 static const struct net_device_ops bcmgenet_netdev_ops
= {
2426 .ndo_open
= bcmgenet_open
,
2427 .ndo_stop
= bcmgenet_close
,
2428 .ndo_start_xmit
= bcmgenet_xmit
,
2429 .ndo_tx_timeout
= bcmgenet_timeout
,
2430 .ndo_set_rx_mode
= bcmgenet_set_rx_mode
,
2431 .ndo_set_mac_address
= bcmgenet_set_mac_addr
,
2432 .ndo_do_ioctl
= bcmgenet_ioctl
,
2433 .ndo_set_features
= bcmgenet_set_features
,
2436 /* Array of GENET hardware parameters/characteristics */
2437 static struct bcmgenet_hw_params bcmgenet_hw_params
[] = {
2442 .bp_in_en_shift
= 16,
2443 .bp_in_mask
= 0xffff,
2444 .hfb_filter_cnt
= 16,
2446 .hfb_offset
= 0x1000,
2447 .rdma_offset
= 0x2000,
2448 .tdma_offset
= 0x3000,
2455 .bp_in_en_shift
= 16,
2456 .bp_in_mask
= 0xffff,
2457 .hfb_filter_cnt
= 16,
2459 .tbuf_offset
= 0x0600,
2460 .hfb_offset
= 0x1000,
2461 .hfb_reg_offset
= 0x2000,
2462 .rdma_offset
= 0x3000,
2463 .tdma_offset
= 0x4000,
2465 .flags
= GENET_HAS_EXT
,
2471 .bp_in_en_shift
= 17,
2472 .bp_in_mask
= 0x1ffff,
2473 .hfb_filter_cnt
= 48,
2475 .tbuf_offset
= 0x0600,
2476 .hfb_offset
= 0x8000,
2477 .hfb_reg_offset
= 0xfc00,
2478 .rdma_offset
= 0x10000,
2479 .tdma_offset
= 0x11000,
2481 .flags
= GENET_HAS_EXT
| GENET_HAS_MDIO_INTR
,
2487 .bp_in_en_shift
= 17,
2488 .bp_in_mask
= 0x1ffff,
2489 .hfb_filter_cnt
= 48,
2491 .tbuf_offset
= 0x0600,
2492 .hfb_offset
= 0x8000,
2493 .hfb_reg_offset
= 0xfc00,
2494 .rdma_offset
= 0x2000,
2495 .tdma_offset
= 0x4000,
2497 .flags
= GENET_HAS_40BITS
| GENET_HAS_EXT
| GENET_HAS_MDIO_INTR
,
2501 /* Infer hardware parameters from the detected GENET version */
2502 static void bcmgenet_set_hw_params(struct bcmgenet_priv
*priv
)
2504 struct bcmgenet_hw_params
*params
;
2509 if (GENET_IS_V4(priv
)) {
2510 bcmgenet_dma_regs
= bcmgenet_dma_regs_v3plus
;
2511 genet_dma_ring_regs
= genet_dma_ring_regs_v4
;
2512 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V3PLUS
;
2513 priv
->version
= GENET_V4
;
2514 } else if (GENET_IS_V3(priv
)) {
2515 bcmgenet_dma_regs
= bcmgenet_dma_regs_v3plus
;
2516 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
2517 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V3PLUS
;
2518 priv
->version
= GENET_V3
;
2519 } else if (GENET_IS_V2(priv
)) {
2520 bcmgenet_dma_regs
= bcmgenet_dma_regs_v2
;
2521 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
2522 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V12
;
2523 priv
->version
= GENET_V2
;
2524 } else if (GENET_IS_V1(priv
)) {
2525 bcmgenet_dma_regs
= bcmgenet_dma_regs_v1
;
2526 genet_dma_ring_regs
= genet_dma_ring_regs_v123
;
2527 priv
->dma_rx_chk_bit
= DMA_RX_CHK_V12
;
2528 priv
->version
= GENET_V1
;
2531 /* enum genet_version starts at 1 */
2532 priv
->hw_params
= &bcmgenet_hw_params
[priv
->version
];
2533 params
= priv
->hw_params
;
2535 /* Read GENET HW version */
2536 reg
= bcmgenet_sys_readl(priv
, SYS_REV_CTRL
);
2537 major
= (reg
>> 24 & 0x0f);
2540 else if (major
== 0)
2542 if (major
!= priv
->version
) {
2543 dev_err(&priv
->pdev
->dev
,
2544 "GENET version mismatch, got: %d, configured for: %d\n",
2545 major
, priv
->version
);
2548 /* Print the GENET core version */
2549 dev_info(&priv
->pdev
->dev
, "GENET " GENET_VER_FMT
,
2550 major
, (reg
>> 16) & 0x0f, reg
& 0xffff);
2552 /* Store the integrated PHY revision for the MDIO probing function
2553 * to pass this information to the PHY driver. The PHY driver expects
2554 * to find the PHY major revision in bits 15:8 while the GENET register
2555 * stores that information in bits 7:0, account for that.
2557 * On newer chips, starting with PHY revision G0, a new scheme is
2558 * deployed similar to the Starfighter 2 switch with GPHY major
2559 * revision in bits 15:8 and patch level in bits 7:0. Major revision 0
2560 * is reserved as well as special value 0x01ff, we have a small
2561 * heuristic to check for the new GPHY revision and re-arrange things
2562 * so the GPHY driver is happy.
2564 gphy_rev
= reg
& 0xffff;
2566 /* This is the good old scheme, just GPHY major, no minor nor patch */
2567 if ((gphy_rev
& 0xf0) != 0)
2568 priv
->gphy_rev
= gphy_rev
<< 8;
2570 /* This is the new scheme, GPHY major rolls over with 0x10 = rev G0 */
2571 else if ((gphy_rev
& 0xff00) != 0)
2572 priv
->gphy_rev
= gphy_rev
;
2574 /* This is reserved so should require special treatment */
2575 else if (gphy_rev
== 0 || gphy_rev
== 0x01ff) {
2576 pr_warn("Invalid GPHY revision detected: 0x%04x\n", gphy_rev
);
2580 #ifdef CONFIG_PHYS_ADDR_T_64BIT
2581 if (!(params
->flags
& GENET_HAS_40BITS
))
2582 pr_warn("GENET does not support 40-bits PA\n");
2585 pr_debug("Configuration for version: %d\n"
2586 "TXq: %1d, RXq: %1d, BDs: %1d\n"
2587 "BP << en: %2d, BP msk: 0x%05x\n"
2588 "HFB count: %2d, QTAQ msk: 0x%05x\n"
2589 "TBUF: 0x%04x, HFB: 0x%04x, HFBreg: 0x%04x\n"
2590 "RDMA: 0x%05x, TDMA: 0x%05x\n"
2593 params
->tx_queues
, params
->rx_queues
, params
->bds_cnt
,
2594 params
->bp_in_en_shift
, params
->bp_in_mask
,
2595 params
->hfb_filter_cnt
, params
->qtag_mask
,
2596 params
->tbuf_offset
, params
->hfb_offset
,
2597 params
->hfb_reg_offset
,
2598 params
->rdma_offset
, params
->tdma_offset
,
2599 params
->words_per_bd
);
2602 static const struct of_device_id bcmgenet_match
[] = {
2603 { .compatible
= "brcm,genet-v1", .data
= (void *)GENET_V1
},
2604 { .compatible
= "brcm,genet-v2", .data
= (void *)GENET_V2
},
2605 { .compatible
= "brcm,genet-v3", .data
= (void *)GENET_V3
},
2606 { .compatible
= "brcm,genet-v4", .data
= (void *)GENET_V4
},
2610 static int bcmgenet_probe(struct platform_device
*pdev
)
2612 struct bcmgenet_platform_data
*pd
= pdev
->dev
.platform_data
;
2613 struct device_node
*dn
= pdev
->dev
.of_node
;
2614 const struct of_device_id
*of_id
= NULL
;
2615 struct bcmgenet_priv
*priv
;
2616 struct net_device
*dev
;
2617 const void *macaddr
;
2621 /* Up to GENET_MAX_MQ_CNT + 1 TX queues and a single RX queue */
2622 dev
= alloc_etherdev_mqs(sizeof(*priv
), GENET_MAX_MQ_CNT
+ 1, 1);
2624 dev_err(&pdev
->dev
, "can't allocate net device\n");
2629 of_id
= of_match_node(bcmgenet_match
, dn
);
2634 priv
= netdev_priv(dev
);
2635 priv
->irq0
= platform_get_irq(pdev
, 0);
2636 priv
->irq1
= platform_get_irq(pdev
, 1);
2637 priv
->wol_irq
= platform_get_irq(pdev
, 2);
2638 if (!priv
->irq0
|| !priv
->irq1
) {
2639 dev_err(&pdev
->dev
, "can't find IRQs\n");
2645 macaddr
= of_get_mac_address(dn
);
2647 dev_err(&pdev
->dev
, "can't find MAC address\n");
2652 macaddr
= pd
->mac_address
;
2655 r
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
2656 priv
->base
= devm_ioremap_resource(&pdev
->dev
, r
);
2657 if (IS_ERR(priv
->base
)) {
2658 err
= PTR_ERR(priv
->base
);
2662 SET_NETDEV_DEV(dev
, &pdev
->dev
);
2663 dev_set_drvdata(&pdev
->dev
, dev
);
2664 ether_addr_copy(dev
->dev_addr
, macaddr
);
2665 dev
->watchdog_timeo
= 2 * HZ
;
2666 dev
->ethtool_ops
= &bcmgenet_ethtool_ops
;
2667 dev
->netdev_ops
= &bcmgenet_netdev_ops
;
2668 netif_napi_add(dev
, &priv
->napi
, bcmgenet_poll
, 64);
2670 priv
->msg_enable
= netif_msg_init(-1, GENET_MSG_DEFAULT
);
2672 /* Set hardware features */
2673 dev
->hw_features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
|
2674 NETIF_F_IPV6_CSUM
| NETIF_F_RXCSUM
;
2676 /* Request the WOL interrupt and advertise suspend if available */
2677 priv
->wol_irq_disabled
= true;
2678 err
= devm_request_irq(&pdev
->dev
, priv
->wol_irq
, bcmgenet_wol_isr
, 0,
2681 device_set_wakeup_capable(&pdev
->dev
, 1);
2683 /* Set the needed headroom to account for any possible
2684 * features enabling/disabling at runtime
2686 dev
->needed_headroom
+= 64;
2688 netdev_boot_setup_check(dev
);
2693 priv
->version
= (enum bcmgenet_version
)of_id
->data
;
2695 priv
->version
= pd
->genet_version
;
2697 priv
->clk
= devm_clk_get(&priv
->pdev
->dev
, "enet");
2698 if (IS_ERR(priv
->clk
))
2699 dev_warn(&priv
->pdev
->dev
, "failed to get enet clock\n");
2701 if (!IS_ERR(priv
->clk
))
2702 clk_prepare_enable(priv
->clk
);
2704 bcmgenet_set_hw_params(priv
);
2706 /* Mii wait queue */
2707 init_waitqueue_head(&priv
->wq
);
2708 /* Always use RX_BUF_LENGTH (2KB) buffer for all chips */
2709 priv
->rx_buf_len
= RX_BUF_LENGTH
;
2710 INIT_WORK(&priv
->bcmgenet_irq_work
, bcmgenet_irq_task
);
2712 priv
->clk_wol
= devm_clk_get(&priv
->pdev
->dev
, "enet-wol");
2713 if (IS_ERR(priv
->clk_wol
))
2714 dev_warn(&priv
->pdev
->dev
, "failed to get enet-wol clock\n");
2716 priv
->clk_eee
= devm_clk_get(&priv
->pdev
->dev
, "enet-eee");
2717 if (IS_ERR(priv
->clk_eee
)) {
2718 dev_warn(&priv
->pdev
->dev
, "failed to get enet-eee clock\n");
2719 priv
->clk_eee
= NULL
;
2722 err
= reset_umac(priv
);
2724 goto err_clk_disable
;
2726 err
= bcmgenet_mii_init(dev
);
2728 goto err_clk_disable
;
2730 /* setup number of real queues + 1 (GENET_V1 has 0 hardware queues
2731 * just the ring 16 descriptor based TX
2733 netif_set_real_num_tx_queues(priv
->dev
, priv
->hw_params
->tx_queues
+ 1);
2734 netif_set_real_num_rx_queues(priv
->dev
, priv
->hw_params
->rx_queues
+ 1);
2736 /* libphy will determine the link state */
2737 netif_carrier_off(dev
);
2739 /* Turn off the main clock, WOL clock is handled separately */
2740 if (!IS_ERR(priv
->clk
))
2741 clk_disable_unprepare(priv
->clk
);
2743 err
= register_netdev(dev
);
2750 if (!IS_ERR(priv
->clk
))
2751 clk_disable_unprepare(priv
->clk
);
2757 static int bcmgenet_remove(struct platform_device
*pdev
)
2759 struct bcmgenet_priv
*priv
= dev_to_priv(&pdev
->dev
);
2761 dev_set_drvdata(&pdev
->dev
, NULL
);
2762 unregister_netdev(priv
->dev
);
2763 bcmgenet_mii_exit(priv
->dev
);
2764 free_netdev(priv
->dev
);
2769 #ifdef CONFIG_PM_SLEEP
2770 static int bcmgenet_suspend(struct device
*d
)
2772 struct net_device
*dev
= dev_get_drvdata(d
);
2773 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2776 if (!netif_running(dev
))
2779 bcmgenet_netif_stop(dev
);
2781 phy_suspend(priv
->phydev
);
2783 netif_device_detach(dev
);
2785 /* Disable MAC receive */
2786 umac_enable_set(priv
, CMD_RX_EN
, false);
2788 ret
= bcmgenet_dma_teardown(priv
);
2792 /* Disable MAC transmit. TX DMA disabled have to done before this */
2793 umac_enable_set(priv
, CMD_TX_EN
, false);
2796 bcmgenet_tx_reclaim_all(dev
);
2797 bcmgenet_fini_dma(priv
);
2799 /* Prepare the device for Wake-on-LAN and switch to the slow clock */
2800 if (device_may_wakeup(d
) && priv
->wolopts
) {
2801 bcmgenet_power_down(priv
, GENET_POWER_WOL_MAGIC
);
2802 clk_prepare_enable(priv
->clk_wol
);
2805 /* Turn off the clocks */
2806 clk_disable_unprepare(priv
->clk
);
2811 static int bcmgenet_resume(struct device
*d
)
2813 struct net_device
*dev
= dev_get_drvdata(d
);
2814 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
2815 unsigned long dma_ctrl
;
2819 if (!netif_running(dev
))
2822 /* Turn on the clock */
2823 ret
= clk_prepare_enable(priv
->clk
);
2827 bcmgenet_umac_reset(priv
);
2829 ret
= init_umac(priv
);
2831 goto out_clk_disable
;
2833 /* From WOL-enabled suspend, switch to regular clock */
2835 clk_disable_unprepare(priv
->clk_wol
);
2837 phy_init_hw(priv
->phydev
);
2838 /* Speed settings must be restored */
2839 bcmgenet_mii_config(priv
->dev
, false);
2841 /* disable ethernet MAC while updating its registers */
2842 umac_enable_set(priv
, CMD_TX_EN
| CMD_RX_EN
, false);
2844 bcmgenet_set_hw_addr(priv
, dev
->dev_addr
);
2846 if (phy_is_internal(priv
->phydev
)) {
2847 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
2848 reg
|= EXT_ENERGY_DET_MASK
;
2849 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
2853 bcmgenet_power_up(priv
, GENET_POWER_WOL_MAGIC
);
2855 /* Disable RX/TX DMA and flush TX queues */
2856 dma_ctrl
= bcmgenet_dma_disable(priv
);
2858 /* Reinitialize TDMA and RDMA and SW housekeeping */
2859 ret
= bcmgenet_init_dma(priv
);
2861 netdev_err(dev
, "failed to initialize DMA\n");
2862 goto out_clk_disable
;
2865 /* Always enable ring 16 - descriptor ring */
2866 bcmgenet_enable_dma(priv
, dma_ctrl
);
2868 netif_device_attach(dev
);
2870 phy_resume(priv
->phydev
);
2872 if (priv
->eee
.eee_enabled
)
2873 bcmgenet_eee_enable_set(dev
, true);
2875 bcmgenet_netif_start(dev
);
2880 clk_disable_unprepare(priv
->clk
);
2883 #endif /* CONFIG_PM_SLEEP */
2885 static SIMPLE_DEV_PM_OPS(bcmgenet_pm_ops
, bcmgenet_suspend
, bcmgenet_resume
);
2887 static struct platform_driver bcmgenet_driver
= {
2888 .probe
= bcmgenet_probe
,
2889 .remove
= bcmgenet_remove
,
2892 .of_match_table
= bcmgenet_match
,
2893 .pm
= &bcmgenet_pm_ops
,
2896 module_platform_driver(bcmgenet_driver
);
2898 MODULE_AUTHOR("Broadcom Corporation");
2899 MODULE_DESCRIPTION("Broadcom GENET Ethernet controller driver");
2900 MODULE_ALIAS("platform:bcmgenet");
2901 MODULE_LICENSE("GPL");