drivers/net/ethernet/broadcom/genet/bcmgenet.h

   1 /*
   2  * Copyright (c) 2014 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #ifndef __BCMGENET_H__
  10 #define __BCMGENET_H__
  11
  12 #include <linux/skbuff.h>
  13 #include <linux/netdevice.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/clk.h>
  16 #include <linux/mii.h>
  17 #include <linux/if_vlan.h>
  18 #include <linux/phy.h>
  19
  20 /* total number of Buffer Descriptors, same for Rx/Tx */
  21 #define TOTAL_DESC                              256
  22
  23 /* which ring is descriptor based */
  24 #define DESC_INDEX                              16
  25
  26 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
  27  * 1536 is multiple of 256 bytes
  28  */
  29 #define ENET_BRCM_TAG_LEN       6
  30 #define ENET_PAD                8
  31 #define ENET_MAX_MTU_SIZE       (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \
  32                                  ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD)
  33 #define DMA_MAX_BURST_LENGTH    0x10
  34
  35 /* misc. configuration */
  36 #define CLEAR_ALL_HFB                   0xFF
  37 #define DMA_FC_THRESH_HI                (TOTAL_DESC >> 4)
  38 #define DMA_FC_THRESH_LO                5
  39
  40 /* 64B receive/transmit status block */
  41 struct status_64 {
  42         u32     length_status;          /* length and peripheral status */
  43         u32     ext_status;             /* Extended status*/
  44         u32     rx_csum;                /* partial rx checksum */
  45         u32     unused1[9];             /* unused */
  46         u32     tx_csum_info;           /* Tx checksum info. */
  47         u32     unused2[3];             /* unused */
  48 };
  49
  50 /* Rx status bits */
  51 #define STATUS_RX_EXT_MASK              0x1FFFFF
  52 #define STATUS_RX_CSUM_MASK             0xFFFF
  53 #define STATUS_RX_CSUM_OK               0x10000
  54 #define STATUS_RX_CSUM_FR               0x20000
  55 #define STATUS_RX_PROTO_TCP             0
  56 #define STATUS_RX_PROTO_UDP             1
  57 #define STATUS_RX_PROTO_ICMP            2
  58 #define STATUS_RX_PROTO_OTHER           3
  59 #define STATUS_RX_PROTO_MASK            3
  60 #define STATUS_RX_PROTO_SHIFT           18
  61 #define STATUS_FILTER_INDEX_MASK        0xFFFF
  62 /* Tx status bits */
  63 #define STATUS_TX_CSUM_START_MASK       0X7FFF
  64 #define STATUS_TX_CSUM_START_SHIFT      16
  65 #define STATUS_TX_CSUM_PROTO_UDP        0x8000
  66 #define STATUS_TX_CSUM_OFFSET_MASK      0x7FFF
  67 #define STATUS_TX_CSUM_LV               0x80000000
  68
  69 /* DMA Descriptor */
  70 #define DMA_DESC_LENGTH_STATUS  0x00    /* in bytes of data in buffer */
  71 #define DMA_DESC_ADDRESS_LO     0x04    /* lower bits of PA */
  72 #define DMA_DESC_ADDRESS_HI     0x08    /* upper 32 bits of PA, GENETv4+ */
  73
  74 /* Rx/Tx common counter group */
  75 struct bcmgenet_pkt_counters {
  76         u32     cnt_64;         /* RO Received/Transmited 64 bytes packet */
  77         u32     cnt_127;        /* RO Rx/Tx 127 bytes packet */
  78         u32     cnt_255;        /* RO Rx/Tx 65-255 bytes packet */
  79         u32     cnt_511;        /* RO Rx/Tx 256-511 bytes packet */
  80         u32     cnt_1023;       /* RO Rx/Tx 512-1023 bytes packet */
  81         u32     cnt_1518;       /* RO Rx/Tx 1024-1518 bytes packet */
  82         u32     cnt_mgv;        /* RO Rx/Tx 1519-1522 good VLAN packet */
  83         u32     cnt_2047;       /* RO Rx/Tx 1522-2047 bytes packet*/
  84         u32     cnt_4095;       /* RO Rx/Tx 2048-4095 bytes packet*/
  85         u32     cnt_9216;       /* RO Rx/Tx 4096-9216 bytes packet*/
  86 };
  87
  88 /* RSV, Receive Status Vector */
  89 struct bcmgenet_rx_counters {
  90         struct  bcmgenet_pkt_counters pkt_cnt;
  91         u32     pkt;            /* RO (0x428) Received pkt count*/
  92         u32     bytes;          /* RO Received byte count */
  93         u32     mca;            /* RO # of Received multicast pkt */
  94         u32     bca;            /* RO # of Receive broadcast pkt */
  95         u32     fcs;            /* RO # of Received FCS error  */
  96         u32     cf;             /* RO # of Received control frame pkt*/
  97         u32     pf;             /* RO # of Received pause frame pkt */
  98         u32     uo;             /* RO # of unknown op code pkt */
  99         u32     aln;            /* RO # of alignment error count */
 100         u32     flr;            /* RO # of frame length out of range count */
 101         u32     cde;            /* RO # of code error pkt */
 102         u32     fcr;            /* RO # of carrier sense error pkt */
 103         u32     ovr;            /* RO # of oversize pkt*/
 104         u32     jbr;            /* RO # of jabber count */
 105         u32     mtue;           /* RO # of MTU error pkt*/
 106         u32     pok;            /* RO # of Received good pkt */
 107         u32     uc;             /* RO # of unicast pkt */
 108         u32     ppp;            /* RO # of PPP pkt */
 109         u32     rcrc;           /* RO (0x470),# of CRC match pkt */
 110 };
 111
 112 /* TSV, Transmit Status Vector */
 113 struct bcmgenet_tx_counters {
 114         struct bcmgenet_pkt_counters pkt_cnt;
 115         u32     pkts;           /* RO (0x4a8) Transmited pkt */
 116         u32     mca;            /* RO # of xmited multicast pkt */
 117         u32     bca;            /* RO # of xmited broadcast pkt */
 118         u32     pf;             /* RO # of xmited pause frame count */
 119         u32     cf;             /* RO # of xmited control frame count */
 120         u32     fcs;            /* RO # of xmited FCS error count */
 121         u32     ovr;            /* RO # of xmited oversize pkt */
 122         u32     drf;            /* RO # of xmited deferral pkt */
 123         u32     edf;            /* RO # of xmited Excessive deferral pkt*/
 124         u32     scl;            /* RO # of xmited single collision pkt */
 125         u32     mcl;            /* RO # of xmited multiple collision pkt*/
 126         u32     lcl;            /* RO # of xmited late collision pkt */
 127         u32     ecl;            /* RO # of xmited excessive collision pkt*/
 128         u32     frg;            /* RO # of xmited fragments pkt*/
 129         u32     ncl;            /* RO # of xmited total collision count */
 130         u32     jbr;            /* RO # of xmited jabber count*/
 131         u32     bytes;          /* RO # of xmited byte count */
 132         u32     pok;            /* RO # of xmited good pkt */
 133         u32     uc;             /* RO (0x0x4f0)# of xmited unitcast pkt */
 134 };
 135
 136 struct bcmgenet_mib_counters {
 137         struct bcmgenet_rx_counters rx;
 138         struct bcmgenet_tx_counters tx;
 139         u32     rx_runt_cnt;
 140         u32     rx_runt_fcs;
 141         u32     rx_runt_fcs_align;
 142         u32     rx_runt_bytes;
 143         u32     rbuf_ovflow_cnt;
 144         u32     rbuf_err_cnt;
 145         u32     mdf_err_cnt;
 146         u32     alloc_rx_buff_failed;
 147         u32     rx_dma_failed;
 148         u32     tx_dma_failed;
 149 };
 150
 151 #define UMAC_HD_BKP_CTRL                0x004
 152 #define  HD_FC_EN                       (1 << 0)
 153 #define  HD_FC_BKOFF_OK                 (1 << 1)
 154 #define  IPG_CONFIG_RX_SHIFT            2
 155 #define  IPG_CONFIG_RX_MASK             0x1F
 156
 157 #define UMAC_CMD                        0x008
 158 #define  CMD_TX_EN                      (1 << 0)
 159 #define  CMD_RX_EN                      (1 << 1)
 160 #define  UMAC_SPEED_10                  0
 161 #define  UMAC_SPEED_100                 1
 162 #define  UMAC_SPEED_1000                2
 163 #define  UMAC_SPEED_2500                3
 164 #define  CMD_SPEED_SHIFT                2
 165 #define  CMD_SPEED_MASK                 3
 166 #define  CMD_PROMISC                    (1 << 4)
 167 #define  CMD_PAD_EN                     (1 << 5)
 168 #define  CMD_CRC_FWD                    (1 << 6)
 169 #define  CMD_PAUSE_FWD                  (1 << 7)
 170 #define  CMD_RX_PAUSE_IGNORE            (1 << 8)
 171 #define  CMD_TX_ADDR_INS                (1 << 9)
 172 #define  CMD_HD_EN                      (1 << 10)
 173 #define  CMD_SW_RESET                   (1 << 13)
 174 #define  CMD_LCL_LOOP_EN                (1 << 15)
 175 #define  CMD_AUTO_CONFIG                (1 << 22)
 176 #define  CMD_CNTL_FRM_EN                (1 << 23)
 177 #define  CMD_NO_LEN_CHK                 (1 << 24)
 178 #define  CMD_RMT_LOOP_EN                (1 << 25)
 179 #define  CMD_PRBL_EN                    (1 << 27)
 180 #define  CMD_TX_PAUSE_IGNORE            (1 << 28)
 181 #define  CMD_TX_RX_EN                   (1 << 29)
 182 #define  CMD_RUNT_FILTER_DIS            (1 << 30)
 183
 184 #define UMAC_MAC0                       0x00C
 185 #define UMAC_MAC1                       0x010
 186 #define UMAC_MAX_FRAME_LEN              0x014
 187
 188 #define UMAC_TX_FLUSH                   0x334
 189
 190 #define UMAC_MIB_START                  0x400
 191
 192 #define UMAC_MDIO_CMD                   0x614
 193 #define  MDIO_START_BUSY                (1 << 29)
 194 #define  MDIO_READ_FAIL                 (1 << 28)
 195 #define  MDIO_RD                        (2 << 26)
 196 #define  MDIO_WR                        (1 << 26)
 197 #define  MDIO_PMD_SHIFT                 21
 198 #define  MDIO_PMD_MASK                  0x1F
 199 #define  MDIO_REG_SHIFT                 16
 200 #define  MDIO_REG_MASK                  0x1F
 201
 202 #define UMAC_RBUF_OVFL_CNT              0x61C
 203
 204 #define UMAC_MPD_CTRL                   0x620
 205 #define  MPD_EN                         (1 << 0)
 206 #define  MPD_PW_EN                      (1 << 27)
 207 #define  MPD_MSEQ_LEN_SHIFT             16
 208 #define  MPD_MSEQ_LEN_MASK              0xFF
 209
 210 #define UMAC_MPD_PW_MS                  0x624
 211 #define UMAC_MPD_PW_LS                  0x628
 212 #define UMAC_RBUF_ERR_CNT               0x634
 213 #define UMAC_MDF_ERR_CNT                0x638
 214 #define UMAC_MDF_CTRL                   0x650
 215 #define UMAC_MDF_ADDR                   0x654
 216 #define UMAC_MIB_CTRL                   0x580
 217 #define  MIB_RESET_RX                   (1 << 0)
 218 #define  MIB_RESET_RUNT                 (1 << 1)
 219 #define  MIB_RESET_TX                   (1 << 2)
 220
 221 #define RBUF_CTRL                       0x00
 222 #define  RBUF_64B_EN                    (1 << 0)
 223 #define  RBUF_ALIGN_2B                  (1 << 1)
 224 #define  RBUF_BAD_DIS                   (1 << 2)
 225
 226 #define RBUF_STATUS                     0x0C
 227 #define  RBUF_STATUS_WOL                (1 << 0)
 228 #define  RBUF_STATUS_MPD_INTR_ACTIVE    (1 << 1)
 229 #define  RBUF_STATUS_ACPI_INTR_ACTIVE   (1 << 2)
 230
 231 #define RBUF_CHK_CTRL                   0x14
 232 #define  RBUF_RXCHK_EN                  (1 << 0)
 233 #define  RBUF_SKIP_FCS                  (1 << 4)
 234
 235 #define RBUF_TBUF_SIZE_CTRL             0xb4
 236
 237 #define RBUF_HFB_CTRL_V1                0x38
 238 #define  RBUF_HFB_FILTER_EN_SHIFT       16
 239 #define  RBUF_HFB_FILTER_EN_MASK        0xffff0000
 240 #define  RBUF_HFB_EN                    (1 << 0)
 241 #define  RBUF_HFB_256B                  (1 << 1)
 242 #define  RBUF_ACPI_EN                   (1 << 2)
 243
 244 #define RBUF_HFB_LEN_V1                 0x3C
 245 #define  RBUF_FLTR_LEN_MASK             0xFF
 246 #define  RBUF_FLTR_LEN_SHIFT            8
 247
 248 #define TBUF_CTRL                       0x00
 249 #define TBUF_BP_MC                      0x0C
 250
 251 #define TBUF_CTRL_V1                    0x80
 252 #define TBUF_BP_MC_V1                   0xA0
 253
 254 #define HFB_CTRL                        0x00
 255 #define HFB_FLT_ENABLE_V3PLUS           0x04
 256 #define HFB_FLT_LEN_V2                  0x04
 257 #define HFB_FLT_LEN_V3PLUS              0x1C
 258
 259 /* uniMac intrl2 registers */
 260 #define INTRL2_CPU_STAT                 0x00
 261 #define INTRL2_CPU_SET                  0x04
 262 #define INTRL2_CPU_CLEAR                0x08
 263 #define INTRL2_CPU_MASK_STATUS          0x0C
 264 #define INTRL2_CPU_MASK_SET             0x10
 265 #define INTRL2_CPU_MASK_CLEAR           0x14
 266
 267 /* INTRL2 instance 0 definitions */
 268 #define UMAC_IRQ_SCB                    (1 << 0)
 269 #define UMAC_IRQ_EPHY                   (1 << 1)
 270 #define UMAC_IRQ_PHY_DET_R              (1 << 2)
 271 #define UMAC_IRQ_PHY_DET_F              (1 << 3)
 272 #define UMAC_IRQ_LINK_UP                (1 << 4)
 273 #define UMAC_IRQ_LINK_DOWN              (1 << 5)
 274 #define UMAC_IRQ_UMAC                   (1 << 6)
 275 #define UMAC_IRQ_UMAC_TSV               (1 << 7)
 276 #define UMAC_IRQ_TBUF_UNDERRUN          (1 << 8)
 277 #define UMAC_IRQ_RBUF_OVERFLOW          (1 << 9)
 278 #define UMAC_IRQ_HFB_SM                 (1 << 10)
 279 #define UMAC_IRQ_HFB_MM                 (1 << 11)
 280 #define UMAC_IRQ_MPD_R                  (1 << 12)
 281 #define UMAC_IRQ_RXDMA_MBDONE           (1 << 13)
 282 #define UMAC_IRQ_RXDMA_PDONE            (1 << 14)
 283 #define UMAC_IRQ_RXDMA_BDONE            (1 << 15)
 284 #define UMAC_IRQ_TXDMA_MBDONE           (1 << 16)
 285 #define UMAC_IRQ_TXDMA_PDONE            (1 << 17)
 286 #define UMAC_IRQ_TXDMA_BDONE            (1 << 18)
 287 /* Only valid for GENETv3+ */
 288 #define UMAC_IRQ_MDIO_DONE              (1 << 23)
 289 #define UMAC_IRQ_MDIO_ERROR             (1 << 24)
 290
 291 /* Register block offsets */
 292 #define GENET_SYS_OFF                   0x0000
 293 #define GENET_GR_BRIDGE_OFF             0x0040
 294 #define GENET_EXT_OFF                   0x0080
 295 #define GENET_INTRL2_0_OFF              0x0200
 296 #define GENET_INTRL2_1_OFF              0x0240
 297 #define GENET_RBUF_OFF                  0x0300
 298 #define GENET_UMAC_OFF                  0x0800
 299
 300 /* SYS block offsets and register definitions */
 301 #define SYS_REV_CTRL                    0x00
 302 #define SYS_PORT_CTRL                   0x04
 303 #define  PORT_MODE_INT_EPHY             0
 304 #define  PORT_MODE_INT_GPHY             1
 305 #define  PORT_MODE_EXT_EPHY             2
 306 #define  PORT_MODE_EXT_GPHY             3
 307 #define  PORT_MODE_EXT_RVMII_25         (4 | BIT(4))
 308 #define  PORT_MODE_EXT_RVMII_50         4
 309 #define  LED_ACT_SOURCE_MAC             (1 << 9)
 310
 311 #define SYS_RBUF_FLUSH_CTRL             0x08
 312 #define SYS_TBUF_FLUSH_CTRL             0x0C
 313 #define RBUF_FLUSH_CTRL_V1              0x04
 314
 315 /* Ext block register offsets and definitions */
 316 #define EXT_EXT_PWR_MGMT                0x00
 317 #define  EXT_PWR_DOWN_BIAS              (1 << 0)
 318 #define  EXT_PWR_DOWN_DLL               (1 << 1)
 319 #define  EXT_PWR_DOWN_PHY               (1 << 2)
 320 #define  EXT_PWR_DN_EN_LD               (1 << 3)
 321 #define  EXT_ENERGY_DET                 (1 << 4)
 322 #define  EXT_IDDQ_FROM_PHY              (1 << 5)
 323 #define  EXT_PHY_RESET                  (1 << 8)
 324 #define  EXT_ENERGY_DET_MASK            (1 << 12)
 325
 326 #define EXT_RGMII_OOB_CTRL              0x0C
 327 #define  RGMII_LINK                     (1 << 4)
 328 #define  OOB_DISABLE                    (1 << 5)
 329 #define  RGMII_MODE_EN                  (1 << 6)
 330 #define  ID_MODE_DIS                    (1 << 16)
 331
 332 #define EXT_GPHY_CTRL                   0x1C
 333 #define  EXT_CFG_IDDQ_BIAS              (1 << 0)
 334 #define  EXT_CFG_PWR_DOWN               (1 << 1)
 335 #define  EXT_GPHY_RESET                 (1 << 5)
 336
 337 /* DMA rings size */
 338 #define DMA_RING_SIZE                   (0x40)
 339 #define DMA_RINGS_SIZE                  (DMA_RING_SIZE * (DESC_INDEX + 1))
 340
 341 /* DMA registers common definitions */
 342 #define DMA_RW_POINTER_MASK             0x1FF
 343 #define DMA_P_INDEX_DISCARD_CNT_MASK    0xFFFF
 344 #define DMA_P_INDEX_DISCARD_CNT_SHIFT   16
 345 #define DMA_BUFFER_DONE_CNT_MASK        0xFFFF
 346 #define DMA_BUFFER_DONE_CNT_SHIFT       16
 347 #define DMA_P_INDEX_MASK                0xFFFF
 348 #define DMA_C_INDEX_MASK                0xFFFF
 349
 350 /* DMA ring size register */
 351 #define DMA_RING_SIZE_MASK              0xFFFF
 352 #define DMA_RING_SIZE_SHIFT             16
 353 #define DMA_RING_BUFFER_SIZE_MASK       0xFFFF
 354
 355 /* DMA interrupt threshold register */
 356 #define DMA_INTR_THRESHOLD_MASK         0x00FF
 357
 358 /* DMA XON/XOFF register */
 359 #define DMA_XON_THREHOLD_MASK           0xFFFF
 360 #define DMA_XOFF_THRESHOLD_MASK         0xFFFF
 361 #define DMA_XOFF_THRESHOLD_SHIFT        16
 362
 363 /* DMA flow period register */
 364 #define DMA_FLOW_PERIOD_MASK            0xFFFF
 365 #define DMA_MAX_PKT_SIZE_MASK           0xFFFF
 366 #define DMA_MAX_PKT_SIZE_SHIFT          16
 367
 368
 369 /* DMA control register */
 370 #define DMA_EN                          (1 << 0)
 371 #define DMA_RING_BUF_EN_SHIFT           0x01
 372 #define DMA_RING_BUF_EN_MASK            0xFFFF
 373 #define DMA_TSB_SWAP_EN                 (1 << 20)
 374
 375 /* DMA status register */
 376 #define DMA_DISABLED                    (1 << 0)
 377 #define DMA_DESC_RAM_INIT_BUSY          (1 << 1)
 378
 379 /* DMA SCB burst size register */
 380 #define DMA_SCB_BURST_SIZE_MASK         0x1F
 381
 382 /* DMA activity vector register */
 383 #define DMA_ACTIVITY_VECTOR_MASK        0x1FFFF
 384
 385 /* DMA backpressure mask register */
 386 #define DMA_BACKPRESSURE_MASK           0x1FFFF
 387 #define DMA_PFC_ENABLE                  (1 << 31)
 388
 389 /* DMA backpressure status register */
 390 #define DMA_BACKPRESSURE_STATUS_MASK    0x1FFFF
 391
 392 /* DMA override register */
 393 #define DMA_LITTLE_ENDIAN_MODE          (1 << 0)
 394 #define DMA_REGISTER_MODE               (1 << 1)
 395
 396 /* DMA timeout register */
 397 #define DMA_TIMEOUT_MASK                0xFFFF
 398 #define DMA_TIMEOUT_VAL                 5000    /* micro seconds */
 399
 400 /* TDMA rate limiting control register */
 401 #define DMA_RATE_LIMIT_EN_MASK          0xFFFF
 402
 403 /* TDMA arbitration control register */
 404 #define DMA_ARBITER_MODE_MASK           0x03
 405 #define DMA_RING_BUF_PRIORITY_MASK      0x1F
 406 #define DMA_RING_BUF_PRIORITY_SHIFT     5
 407 #define DMA_PRIO_REG_INDEX(q)           ((q) / 6)
 408 #define DMA_PRIO_REG_SHIFT(q)           (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT)
 409 #define DMA_RATE_ADJ_MASK               0xFF
 410
 411 /* Tx/Rx Dma Descriptor common bits*/
 412 #define DMA_BUFLENGTH_MASK              0x0fff
 413 #define DMA_BUFLENGTH_SHIFT             16
 414 #define DMA_OWN                         0x8000
 415 #define DMA_EOP                         0x4000
 416 #define DMA_SOP                         0x2000
 417 #define DMA_WRAP                        0x1000
 418 /* Tx specific Dma descriptor bits */
 419 #define DMA_TX_UNDERRUN                 0x0200
 420 #define DMA_TX_APPEND_CRC               0x0040
 421 #define DMA_TX_OW_CRC                   0x0020
 422 #define DMA_TX_DO_CSUM                  0x0010
 423 #define DMA_TX_QTAG_SHIFT               7
 424
 425 /* Rx Specific Dma descriptor bits */
 426 #define DMA_RX_CHK_V3PLUS               0x8000
 427 #define DMA_RX_CHK_V12                  0x1000
 428 #define DMA_RX_BRDCAST                  0x0040
 429 #define DMA_RX_MULT                     0x0020
 430 #define DMA_RX_LG                       0x0010
 431 #define DMA_RX_NO                       0x0008
 432 #define DMA_RX_RXER                     0x0004
 433 #define DMA_RX_CRC_ERROR                0x0002
 434 #define DMA_RX_OV                       0x0001
 435 #define DMA_RX_FI_MASK                  0x001F
 436 #define DMA_RX_FI_SHIFT                 0x0007
 437 #define DMA_DESC_ALLOC_MASK             0x00FF
 438
 439 #define DMA_ARBITER_RR                  0x00
 440 #define DMA_ARBITER_WRR                 0x01
 441 #define DMA_ARBITER_SP                  0x02
 442
 443 struct enet_cb {
 444         struct sk_buff      *skb;
 445         void __iomem *bd_addr;
 446         DEFINE_DMA_UNMAP_ADDR(dma_addr);
 447         DEFINE_DMA_UNMAP_LEN(dma_len);
 448 };
 449
 450 /* power management mode */
 451 enum bcmgenet_power_mode {
 452         GENET_POWER_CABLE_SENSE = 0,
 453         GENET_POWER_PASSIVE,
 454         GENET_POWER_WOL_MAGIC,
 455 };
 456
 457 struct bcmgenet_priv;
 458
 459 /* We support both runtime GENET detection and compile-time
 460  * to optimize code-paths for a given hardware
 461  */
 462 enum bcmgenet_version {
 463         GENET_V1 = 1,
 464         GENET_V2,
 465         GENET_V3,
 466         GENET_V4
 467 };
 468
 469 #define GENET_IS_V1(p)  ((p)->version == GENET_V1)
 470 #define GENET_IS_V2(p)  ((p)->version == GENET_V2)
 471 #define GENET_IS_V3(p)  ((p)->version == GENET_V3)
 472 #define GENET_IS_V4(p)  ((p)->version == GENET_V4)
 473
 474 /* Hardware flags */
 475 #define GENET_HAS_40BITS        (1 << 0)
 476 #define GENET_HAS_EXT           (1 << 1)
 477 #define GENET_HAS_MDIO_INTR     (1 << 2)
 478
 479 /* BCMGENET hardware parameters, keep this structure nicely aligned
 480  * since it is going to be used in hot paths
 481  */
 482 struct bcmgenet_hw_params {
 483         u8              tx_queues;
 484         u8              rx_queues;
 485         u8              bds_cnt;
 486         u8              bp_in_en_shift;
 487         u32             bp_in_mask;
 488         u8              hfb_filter_cnt;
 489         u8              qtag_mask;
 490         u16             tbuf_offset;
 491         u32             hfb_offset;
 492         u32             hfb_reg_offset;
 493         u32             rdma_offset;
 494         u32             tdma_offset;
 495         u32             words_per_bd;
 496         u32             flags;
 497 };
 498
 499 struct bcmgenet_tx_ring {
 500         spinlock_t      lock;           /* ring lock */
 501         unsigned int    index;          /* ring index */
 502         unsigned int    queue;          /* queue index */
 503         struct enet_cb  *cbs;           /* tx ring buffer control block*/
 504         unsigned int    size;           /* size of each tx ring */
 505         unsigned int    c_index;        /* last consumer index of each ring*/
 506         unsigned int    free_bds;       /* # of free bds for each ring */
 507         unsigned int    write_ptr;      /* Tx ring write pointer SW copy */
 508         unsigned int    prod_index;     /* Tx ring producer index SW copy */
 509         unsigned int    cb_ptr;         /* Tx ring initial CB ptr */
 510         unsigned int    end_ptr;        /* Tx ring end CB ptr */
 511         void (*int_enable)(struct bcmgenet_priv *priv,
 512                            struct bcmgenet_tx_ring *);
 513         void (*int_disable)(struct bcmgenet_priv *priv,
 514                             struct bcmgenet_tx_ring *);
 515 };
 516
 517 /* device context */
 518 struct bcmgenet_priv {
 519         void __iomem *base;
 520         enum bcmgenet_version version;
 521         struct net_device *dev;
 522         u32 int0_mask;
 523         u32 int1_mask;
 524
 525         /* NAPI for descriptor based rx */
 526         struct napi_struct napi ____cacheline_aligned;
 527
 528         /* transmit variables */
 529         void __iomem *tx_bds;
 530         struct enet_cb *tx_cbs;
 531         unsigned int num_tx_bds;
 532
 533         struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1];
 534
 535         /* receive variables */
 536         void __iomem *rx_bds;
 537         void __iomem *rx_bd_assign_ptr;
 538         int rx_bd_assign_index;
 539         struct enet_cb *rx_cbs;
 540         unsigned int num_rx_bds;
 541         unsigned int rx_buf_len;
 542         unsigned int rx_read_ptr;
 543         unsigned int rx_c_index;
 544
 545         /* other misc variables */
 546         struct bcmgenet_hw_params *hw_params;
 547
 548         /* MDIO bus variables */
 549         wait_queue_head_t wq;
 550         struct phy_device *phydev;
 551         struct device_node *phy_dn;
 552         struct mii_bus *mii_bus;
 553         u16 gphy_rev;
 554
 555         /* PHY device variables */
 556         int old_link;
 557         int old_speed;
 558         int old_duplex;
 559         int old_pause;
 560         phy_interface_t phy_interface;
 561         int phy_addr;
 562         int ext_phy;
 563
 564         /* Interrupt variables */
 565         struct work_struct bcmgenet_irq_work;
 566         int irq0;
 567         int irq1;
 568         unsigned int irq0_stat;
 569         unsigned int irq1_stat;
 570         int wol_irq;
 571         bool wol_irq_disabled;
 572
 573         /* HW descriptors/checksum variables */
 574         bool desc_64b_en;
 575         bool desc_rxchk_en;
 576         bool crc_fwd_en;
 577
 578         unsigned int dma_rx_chk_bit;
 579
 580         u32 msg_enable;
 581
 582         struct clk *clk;
 583         struct platform_device *pdev;
 584
 585         /* WOL */
 586         struct clk *clk_wol;
 587         u32 wolopts;
 588
 589         struct bcmgenet_mib_counters mib;
 590 };
 591
 592 #define GENET_IO_MACRO(name, offset)                                    \
 593 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv,   \
 594                                         u32 off)                        \
 595 {                                                                       \
 596         return __raw_readl(priv->base + offset + off);                  \
 597 }                                                                       \
 598 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \
 599                                         u32 val, u32 off)               \
 600 {                                                                       \
 601         __raw_writel(val, priv->base + offset + off);                   \
 602 }
 603
 604 GENET_IO_MACRO(ext, GENET_EXT_OFF);
 605 GENET_IO_MACRO(umac, GENET_UMAC_OFF);
 606 GENET_IO_MACRO(sys, GENET_SYS_OFF);
 607
 608 /* interrupt l2 registers accessors */
 609 GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF);
 610 GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF);
 611
 612 /* HFB register accessors  */
 613 GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset);
 614
 615 /* GENET v2+ HFB control and filter len helpers */
 616 GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset);
 617
 618 /* RBUF register accessors */
 619 GENET_IO_MACRO(rbuf, GENET_RBUF_OFF);
 620
 621 /* MDIO routines */
 622 int bcmgenet_mii_init(struct net_device *dev);
 623 int bcmgenet_mii_config(struct net_device *dev, bool init);
 624 void bcmgenet_mii_exit(struct net_device *dev);
 625 void bcmgenet_mii_reset(struct net_device *dev);
 626 void bcmgenet_mii_setup(struct net_device *dev);
 627
 628 /* Wake-on-LAN routines */
 629 void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
 630 int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol);
 631 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv,
 632                                 enum bcmgenet_power_mode mode);
 633 void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv,
 634                                enum bcmgenet_power_mode mode);
 635
 636 #endif /* __BCMGENET_H__ */