2 * Broadcom GENET MDIO routines
4 * Copyright (c) 2014 Broadcom Corporation
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
12 #include <linux/types.h>
13 #include <linux/delay.h>
14 #include <linux/wait.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/bitops.h>
18 #include <linux/netdevice.h>
19 #include <linux/platform_device.h>
20 #include <linux/phy.h>
21 #include <linux/phy_fixed.h>
22 #include <linux/brcmphy.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
26 #include <linux/platform_data/bcmgenet.h>
30 /* read a value from the MII */
31 static int bcmgenet_mii_read(struct mii_bus
*bus
, int phy_id
, int location
)
34 struct net_device
*dev
= bus
->priv
;
35 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
38 bcmgenet_umac_writel(priv
, (MDIO_RD
| (phy_id
<< MDIO_PMD_SHIFT
) |
39 (location
<< MDIO_REG_SHIFT
)), UMAC_MDIO_CMD
);
40 /* Start MDIO transaction*/
41 reg
= bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
);
42 reg
|= MDIO_START_BUSY
;
43 bcmgenet_umac_writel(priv
, reg
, UMAC_MDIO_CMD
);
44 wait_event_timeout(priv
->wq
,
45 !(bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
)
48 ret
= bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
);
50 /* Some broken devices are known not to release the line during
51 * turn-around, e.g: Broadcom BCM53125 external switches, so check for
52 * that condition here and ignore the MDIO controller read failure
55 if (!(bus
->phy_ignore_ta_mask
& 1 << phy_id
) && (ret
& MDIO_READ_FAIL
))
61 /* write a value to the MII */
62 static int bcmgenet_mii_write(struct mii_bus
*bus
, int phy_id
,
63 int location
, u16 val
)
65 struct net_device
*dev
= bus
->priv
;
66 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
69 bcmgenet_umac_writel(priv
, (MDIO_WR
| (phy_id
<< MDIO_PMD_SHIFT
) |
70 (location
<< MDIO_REG_SHIFT
) | (0xffff & val
)),
72 reg
= bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
);
73 reg
|= MDIO_START_BUSY
;
74 bcmgenet_umac_writel(priv
, reg
, UMAC_MDIO_CMD
);
75 wait_event_timeout(priv
->wq
,
76 !(bcmgenet_umac_readl(priv
, UMAC_MDIO_CMD
) &
83 /* setup netdev link state when PHY link status change and
84 * update UMAC and RGMII block when link up
86 void bcmgenet_mii_setup(struct net_device
*dev
)
88 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
89 struct phy_device
*phydev
= priv
->phydev
;
90 u32 reg
, cmd_bits
= 0;
91 bool status_changed
= false;
93 if (priv
->old_link
!= phydev
->link
) {
94 status_changed
= true;
95 priv
->old_link
= phydev
->link
;
99 /* check speed/duplex/pause changes */
100 if (priv
->old_speed
!= phydev
->speed
) {
101 status_changed
= true;
102 priv
->old_speed
= phydev
->speed
;
105 if (priv
->old_duplex
!= phydev
->duplex
) {
106 status_changed
= true;
107 priv
->old_duplex
= phydev
->duplex
;
110 if (priv
->old_pause
!= phydev
->pause
) {
111 status_changed
= true;
112 priv
->old_pause
= phydev
->pause
;
115 /* done if nothing has changed */
120 if (phydev
->speed
== SPEED_1000
)
121 cmd_bits
= UMAC_SPEED_1000
;
122 else if (phydev
->speed
== SPEED_100
)
123 cmd_bits
= UMAC_SPEED_100
;
125 cmd_bits
= UMAC_SPEED_10
;
126 cmd_bits
<<= CMD_SPEED_SHIFT
;
129 if (phydev
->duplex
!= DUPLEX_FULL
)
130 cmd_bits
|= CMD_HD_EN
;
132 /* pause capability */
134 cmd_bits
|= CMD_RX_PAUSE_IGNORE
| CMD_TX_PAUSE_IGNORE
;
137 * Program UMAC and RGMII block based on established
138 * link speed, duplex, and pause. The speed set in
139 * umac->cmd tell RGMII block which clock to use for
140 * transmit -- 25MHz(100Mbps) or 125MHz(1Gbps).
141 * Receive clock is provided by the PHY.
143 reg
= bcmgenet_ext_readl(priv
, EXT_RGMII_OOB_CTRL
);
146 bcmgenet_ext_writel(priv
, reg
, EXT_RGMII_OOB_CTRL
);
148 reg
= bcmgenet_umac_readl(priv
, UMAC_CMD
);
149 reg
&= ~((CMD_SPEED_MASK
<< CMD_SPEED_SHIFT
) |
151 CMD_RX_PAUSE_IGNORE
| CMD_TX_PAUSE_IGNORE
);
153 bcmgenet_umac_writel(priv
, reg
, UMAC_CMD
);
155 /* done if nothing has changed */
159 /* needed for MoCA fixed PHY to reflect correct link status */
160 netif_carrier_off(dev
);
163 phy_print_status(phydev
);
166 void bcmgenet_mii_reset(struct net_device
*dev
)
168 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
171 phy_init_hw(priv
->phydev
);
172 phy_start_aneg(priv
->phydev
);
176 void bcmgenet_phy_power_set(struct net_device
*dev
, bool enable
)
178 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
181 /* EXT_GPHY_CTRL is only valid for GENETv4 and onward */
182 if (!GENET_IS_V4(priv
))
185 reg
= bcmgenet_ext_readl(priv
, EXT_GPHY_CTRL
);
187 reg
&= ~EXT_CK25_DIS
;
188 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
191 reg
&= ~(EXT_CFG_IDDQ_BIAS
| EXT_CFG_PWR_DOWN
);
192 reg
|= EXT_GPHY_RESET
;
193 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
196 reg
&= ~EXT_GPHY_RESET
;
198 reg
|= EXT_CFG_IDDQ_BIAS
| EXT_CFG_PWR_DOWN
| EXT_GPHY_RESET
;
199 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
203 bcmgenet_ext_writel(priv
, reg
, EXT_GPHY_CTRL
);
207 static void bcmgenet_internal_phy_setup(struct net_device
*dev
)
209 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
213 bcmgenet_phy_power_set(dev
, true);
215 reg
= bcmgenet_ext_readl(priv
, EXT_EXT_PWR_MGMT
);
216 reg
|= EXT_PWR_DN_EN_LD
;
217 bcmgenet_ext_writel(priv
, reg
, EXT_EXT_PWR_MGMT
);
218 bcmgenet_mii_reset(dev
);
221 static void bcmgenet_moca_phy_setup(struct bcmgenet_priv
*priv
)
225 /* Speed settings are set in bcmgenet_mii_setup() */
226 reg
= bcmgenet_sys_readl(priv
, SYS_PORT_CTRL
);
227 reg
|= LED_ACT_SOURCE_MAC
;
228 bcmgenet_sys_writel(priv
, reg
, SYS_PORT_CTRL
);
231 int bcmgenet_mii_config(struct net_device
*dev
, bool init
)
233 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
234 struct phy_device
*phydev
= priv
->phydev
;
235 struct device
*kdev
= &priv
->pdev
->dev
;
236 const char *phy_name
= NULL
;
241 priv
->ext_phy
= !phy_is_internal(priv
->phydev
) &&
242 (priv
->phy_interface
!= PHY_INTERFACE_MODE_MOCA
);
244 if (phy_is_internal(priv
->phydev
))
245 priv
->phy_interface
= PHY_INTERFACE_MODE_NA
;
247 switch (priv
->phy_interface
) {
248 case PHY_INTERFACE_MODE_NA
:
249 case PHY_INTERFACE_MODE_MOCA
:
250 /* Irrespective of the actually configured PHY speed (100 or
251 * 1000) GENETv4 only has an internal GPHY so we will just end
252 * up masking the Gigabit features from what we support, not
253 * switching to the EPHY
255 if (GENET_IS_V4(priv
))
256 port_ctrl
= PORT_MODE_INT_GPHY
;
258 port_ctrl
= PORT_MODE_INT_EPHY
;
260 bcmgenet_sys_writel(priv
, port_ctrl
, SYS_PORT_CTRL
);
262 if (phy_is_internal(priv
->phydev
)) {
263 phy_name
= "internal PHY";
264 bcmgenet_internal_phy_setup(dev
);
265 } else if (priv
->phy_interface
== PHY_INTERFACE_MODE_MOCA
) {
267 bcmgenet_moca_phy_setup(priv
);
271 case PHY_INTERFACE_MODE_MII
:
272 phy_name
= "external MII";
273 phydev
->supported
&= PHY_BASIC_FEATURES
;
274 bcmgenet_sys_writel(priv
,
275 PORT_MODE_EXT_EPHY
, SYS_PORT_CTRL
);
278 case PHY_INTERFACE_MODE_REVMII
:
279 phy_name
= "external RvMII";
280 /* of_mdiobus_register took care of reading the 'max-speed'
281 * PHY property for us, effectively limiting the PHY supported
282 * capabilities, use that knowledge to also configure the
283 * Reverse MII interface correctly.
285 if ((priv
->phydev
->supported
& PHY_BASIC_FEATURES
) ==
287 port_ctrl
= PORT_MODE_EXT_RVMII_25
;
289 port_ctrl
= PORT_MODE_EXT_RVMII_50
;
290 bcmgenet_sys_writel(priv
, port_ctrl
, SYS_PORT_CTRL
);
293 case PHY_INTERFACE_MODE_RGMII
:
294 /* RGMII_NO_ID: TXC transitions at the same time as TXD
295 * (requires PCB or receiver-side delay)
296 * RGMII: Add 2ns delay on TXC (90 degree shift)
298 * ID is implicitly disabled for 100Mbps (RG)MII operation.
300 id_mode_dis
= BIT(16);
302 case PHY_INTERFACE_MODE_RGMII_TXID
:
304 phy_name
= "external RGMII (no delay)";
306 phy_name
= "external RGMII (TX delay)";
307 bcmgenet_sys_writel(priv
,
308 PORT_MODE_EXT_GPHY
, SYS_PORT_CTRL
);
311 dev_err(kdev
, "unknown phy mode: %d\n", priv
->phy_interface
);
315 /* This is an external PHY (xMII), so we need to enable the RGMII
316 * block for the interface to work
319 reg
= bcmgenet_ext_readl(priv
, EXT_RGMII_OOB_CTRL
);
320 reg
|= RGMII_MODE_EN
| id_mode_dis
;
321 bcmgenet_ext_writel(priv
, reg
, EXT_RGMII_OOB_CTRL
);
325 dev_info(kdev
, "configuring instance for %s\n", phy_name
);
330 static int bcmgenet_mii_probe(struct net_device
*dev
)
332 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
333 struct device_node
*dn
= priv
->pdev
->dev
.of_node
;
334 struct phy_device
*phydev
;
338 /* Communicate the integrated PHY revision */
339 phy_flags
= priv
->gphy_rev
;
341 /* Initialize link state variables that bcmgenet_mii_setup() uses */
343 priv
->old_speed
= -1;
344 priv
->old_duplex
= -1;
345 priv
->old_pause
= -1;
349 pr_info("PHY already attached\n");
353 /* In the case of a fixed PHY, the DT node associated
354 * to the PHY is the Ethernet MAC DT node.
356 if (!priv
->phy_dn
&& of_phy_is_fixed_link(dn
)) {
357 ret
= of_phy_register_fixed_link(dn
);
361 priv
->phy_dn
= of_node_get(dn
);
364 phydev
= of_phy_connect(dev
, priv
->phy_dn
, bcmgenet_mii_setup
,
365 phy_flags
, priv
->phy_interface
);
367 pr_err("could not attach to PHY\n");
371 phydev
= priv
->phydev
;
372 phydev
->dev_flags
= phy_flags
;
374 ret
= phy_connect_direct(dev
, phydev
, bcmgenet_mii_setup
,
375 priv
->phy_interface
);
377 pr_err("could not attach to PHY\n");
382 priv
->phydev
= phydev
;
384 /* Configure port multiplexer based on what the probed PHY device since
385 * reading the 'max-speed' property determines the maximum supported
386 * PHY speed which is needed for bcmgenet_mii_config() to configure
387 * things appropriately.
389 ret
= bcmgenet_mii_config(dev
, true);
391 phy_disconnect(priv
->phydev
);
395 phydev
->advertising
= phydev
->supported
;
397 /* The internal PHY has its link interrupts routed to the
400 if (phy_is_internal(priv
->phydev
))
401 priv
->mii_bus
->irq
[phydev
->addr
] = PHY_IGNORE_INTERRUPT
;
403 priv
->mii_bus
->irq
[phydev
->addr
] = PHY_POLL
;
405 pr_info("attached PHY at address %d [%s]\n",
406 phydev
->addr
, phydev
->drv
->name
);
411 /* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
412 * their internal MDIO management controller making them fail to successfully
413 * be read from or written to for the first transaction. We insert a dummy
414 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
415 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
416 * PHY device for this peripheral.
418 * Once the PHY driver is registered, we can workaround subsequent reads from
419 * there (e.g: during system-wide power management).
421 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
422 * therefore the right location to stick that workaround. Since we do not want
423 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
424 * Device Tree scan to limit the search area.
426 static int bcmgenet_mii_bus_reset(struct mii_bus
*bus
)
428 struct net_device
*dev
= bus
->priv
;
429 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
430 struct device_node
*np
= priv
->mdio_dn
;
431 struct device_node
*child
= NULL
;
436 read_mask
= 1 << priv
->phy_addr
;
438 for_each_available_child_of_node(np
, child
) {
439 addr
= of_mdio_parse_addr(&dev
->dev
, child
);
443 read_mask
|= 1 << addr
;
447 for (addr
= 0; addr
< PHY_MAX_ADDR
; addr
++) {
448 if (read_mask
& 1 << addr
) {
449 dev_dbg(&dev
->dev
, "Workaround for PHY @ %d\n", addr
);
450 mdiobus_read(bus
, addr
, MII_BMSR
);
457 static int bcmgenet_mii_alloc(struct bcmgenet_priv
*priv
)
464 priv
->mii_bus
= mdiobus_alloc();
465 if (!priv
->mii_bus
) {
466 pr_err("failed to allocate\n");
471 bus
->priv
= priv
->dev
;
472 bus
->name
= "bcmgenet MII bus";
473 bus
->parent
= &priv
->pdev
->dev
;
474 bus
->read
= bcmgenet_mii_read
;
475 bus
->write
= bcmgenet_mii_write
;
476 bus
->reset
= bcmgenet_mii_bus_reset
;
477 snprintf(bus
->id
, MII_BUS_ID_SIZE
, "%s-%d",
478 priv
->pdev
->name
, priv
->pdev
->id
);
480 bus
->irq
= kcalloc(PHY_MAX_ADDR
, sizeof(int), GFP_KERNEL
);
482 mdiobus_free(priv
->mii_bus
);
489 static int bcmgenet_mii_of_init(struct bcmgenet_priv
*priv
)
491 struct device_node
*dn
= priv
->pdev
->dev
.of_node
;
492 struct device
*kdev
= &priv
->pdev
->dev
;
496 compat
= kasprintf(GFP_KERNEL
, "brcm,genet-mdio-v%d", priv
->version
);
500 priv
->mdio_dn
= of_find_compatible_node(dn
, NULL
, compat
);
502 if (!priv
->mdio_dn
) {
503 dev_err(kdev
, "unable to find MDIO bus node\n");
507 ret
= of_mdiobus_register(priv
->mii_bus
, priv
->mdio_dn
);
509 dev_err(kdev
, "failed to register MDIO bus\n");
513 /* Fetch the PHY phandle */
514 priv
->phy_dn
= of_parse_phandle(dn
, "phy-handle", 0);
516 /* Get the link mode */
517 priv
->phy_interface
= of_get_phy_mode(dn
);
522 static int bcmgenet_fixed_phy_link_update(struct net_device
*dev
,
523 struct fixed_phy_status
*status
)
525 if (dev
&& dev
->phydev
&& status
)
526 status
->link
= dev
->phydev
->link
;
531 static int bcmgenet_mii_pd_init(struct bcmgenet_priv
*priv
)
533 struct device
*kdev
= &priv
->pdev
->dev
;
534 struct bcmgenet_platform_data
*pd
= kdev
->platform_data
;
535 struct mii_bus
*mdio
= priv
->mii_bus
;
536 struct phy_device
*phydev
;
539 if (pd
->phy_interface
!= PHY_INTERFACE_MODE_MOCA
&& pd
->mdio_enabled
) {
541 * Internal or external PHY with MDIO access
543 if (pd
->phy_address
>= 0 && pd
->phy_address
< PHY_MAX_ADDR
)
544 mdio
->phy_mask
= ~(1 << pd
->phy_address
);
548 ret
= mdiobus_register(mdio
);
550 dev_err(kdev
, "failed to register MDIO bus\n");
554 if (pd
->phy_address
>= 0 && pd
->phy_address
< PHY_MAX_ADDR
)
555 phydev
= mdio
->phy_map
[pd
->phy_address
];
557 phydev
= phy_find_first(mdio
);
560 dev_err(kdev
, "failed to register PHY device\n");
561 mdiobus_unregister(mdio
);
566 * MoCA port or no MDIO access.
567 * Use fixed PHY to represent the link layer.
569 struct fixed_phy_status fphy_status
= {
571 .speed
= pd
->phy_speed
,
572 .duplex
= pd
->phy_duplex
,
577 phydev
= fixed_phy_register(PHY_POLL
, &fphy_status
, NULL
);
578 if (!phydev
|| IS_ERR(phydev
)) {
579 dev_err(kdev
, "failed to register fixed PHY device\n");
583 if (priv
->hw_params
->flags
& GENET_HAS_MOCA_LINK_DET
) {
584 ret
= fixed_phy_set_link_update(
585 phydev
, bcmgenet_fixed_phy_link_update
);
591 priv
->phydev
= phydev
;
592 priv
->phy_interface
= pd
->phy_interface
;
597 static int bcmgenet_mii_bus_init(struct bcmgenet_priv
*priv
)
599 struct device_node
*dn
= priv
->pdev
->dev
.of_node
;
602 return bcmgenet_mii_of_init(priv
);
604 return bcmgenet_mii_pd_init(priv
);
607 int bcmgenet_mii_init(struct net_device
*dev
)
609 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
612 ret
= bcmgenet_mii_alloc(priv
);
616 ret
= bcmgenet_mii_bus_init(priv
);
620 ret
= bcmgenet_mii_probe(dev
);
627 of_node_put(priv
->phy_dn
);
628 mdiobus_unregister(priv
->mii_bus
);
630 kfree(priv
->mii_bus
->irq
);
631 mdiobus_free(priv
->mii_bus
);
635 void bcmgenet_mii_exit(struct net_device
*dev
)
637 struct bcmgenet_priv
*priv
= netdev_priv(dev
);
639 of_node_put(priv
->phy_dn
);
640 mdiobus_unregister(priv
->mii_bus
);
641 kfree(priv
->mii_bus
->irq
);
642 mdiobus_free(priv
->mii_bus
);