2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2013 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/stringify.h>
22 #include <linux/kernel.h>
23 #include <linux/types.h>
24 #include <linux/compiler.h>
25 #include <linux/slab.h>
26 #include <linux/delay.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/ioport.h>
31 #include <linux/pci.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
35 #include <linux/ethtool.h>
36 #include <linux/mdio.h>
37 #include <linux/mii.h>
38 #include <linux/phy.h>
39 #include <linux/brcmphy.h>
40 #include <linux/if_vlan.h>
42 #include <linux/tcp.h>
43 #include <linux/workqueue.h>
44 #include <linux/prefetch.h>
45 #include <linux/dma-mapping.h>
46 #include <linux/firmware.h>
47 #include <linux/ssb/ssb_driver_gige.h>
48 #include <linux/hwmon.h>
49 #include <linux/hwmon-sysfs.h>
51 #include <net/checksum.h>
55 #include <asm/byteorder.h>
56 #include <linux/uaccess.h>
58 #include <uapi/linux/net_tstamp.h>
59 #include <linux/ptp_clock_kernel.h>
62 #include <asm/idprom.h>
71 /* Functions & macros to verify TG3_FLAGS types */
73 static inline int _tg3_flag(enum TG3_FLAGS flag
, unsigned long *bits
)
75 return test_bit(flag
, bits
);
78 static inline void _tg3_flag_set(enum TG3_FLAGS flag
, unsigned long *bits
)
83 static inline void _tg3_flag_clear(enum TG3_FLAGS flag
, unsigned long *bits
)
85 clear_bit(flag
, bits
);
88 #define tg3_flag(tp, flag) \
89 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
90 #define tg3_flag_set(tp, flag) \
91 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
92 #define tg3_flag_clear(tp, flag) \
93 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
95 #define DRV_MODULE_NAME "tg3"
97 #define TG3_MIN_NUM 131
98 #define DRV_MODULE_VERSION \
99 __stringify(TG3_MAJ_NUM) "." __stringify(TG3_MIN_NUM)
100 #define DRV_MODULE_RELDATE "April 09, 2013"
102 #define RESET_KIND_SHUTDOWN 0
103 #define RESET_KIND_INIT 1
104 #define RESET_KIND_SUSPEND 2
106 #define TG3_DEF_RX_MODE 0
107 #define TG3_DEF_TX_MODE 0
108 #define TG3_DEF_MSG_ENABLE \
118 #define TG3_GRC_LCLCTL_PWRSW_DELAY 100
120 /* length of time before we decide the hardware is borked,
121 * and dev->tx_timeout() should be called to fix the problem
124 #define TG3_TX_TIMEOUT (5 * HZ)
126 /* hardware minimum and maximum for a single frame's data payload */
127 #define TG3_MIN_MTU 60
128 #define TG3_MAX_MTU(tp) \
129 (tg3_flag(tp, JUMBO_CAPABLE) ? 9000 : 1500)
131 /* These numbers seem to be hard coded in the NIC firmware somehow.
132 * You can't change the ring sizes, but you can change where you place
133 * them in the NIC onboard memory.
135 #define TG3_RX_STD_RING_SIZE(tp) \
136 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
137 TG3_RX_STD_MAX_SIZE_5717 : TG3_RX_STD_MAX_SIZE_5700)
138 #define TG3_DEF_RX_RING_PENDING 200
139 #define TG3_RX_JMB_RING_SIZE(tp) \
140 (tg3_flag(tp, LRG_PROD_RING_CAP) ? \
141 TG3_RX_JMB_MAX_SIZE_5717 : TG3_RX_JMB_MAX_SIZE_5700)
142 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
144 /* Do not place this n-ring entries value into the tp struct itself,
145 * we really want to expose these constants to GCC so that modulo et
146 * al. operations are done with shifts and masks instead of with
147 * hw multiply/modulo instructions. Another solution would be to
148 * replace things like '% foo' with '& (foo - 1)'.
151 #define TG3_TX_RING_SIZE 512
152 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
154 #define TG3_RX_STD_RING_BYTES(tp) \
155 (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_STD_RING_SIZE(tp))
156 #define TG3_RX_JMB_RING_BYTES(tp) \
157 (sizeof(struct tg3_ext_rx_buffer_desc) * TG3_RX_JMB_RING_SIZE(tp))
158 #define TG3_RX_RCB_RING_BYTES(tp) \
159 (sizeof(struct tg3_rx_buffer_desc) * (tp->rx_ret_ring_mask + 1))
160 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
162 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
164 #define TG3_DMA_BYTE_ENAB 64
166 #define TG3_RX_STD_DMA_SZ 1536
167 #define TG3_RX_JMB_DMA_SZ 9046
169 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
171 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
172 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
174 #define TG3_RX_STD_BUFF_RING_SIZE(tp) \
175 (sizeof(struct ring_info) * TG3_RX_STD_RING_SIZE(tp))
177 #define TG3_RX_JMB_BUFF_RING_SIZE(tp) \
178 (sizeof(struct ring_info) * TG3_RX_JMB_RING_SIZE(tp))
180 /* Due to a hardware bug, the 5701 can only DMA to memory addresses
181 * that are at least dword aligned when used in PCIX mode. The driver
182 * works around this bug by double copying the packet. This workaround
183 * is built into the normal double copy length check for efficiency.
185 * However, the double copy is only necessary on those architectures
186 * where unaligned memory accesses are inefficient. For those architectures
187 * where unaligned memory accesses incur little penalty, we can reintegrate
188 * the 5701 in the normal rx path. Doing so saves a device structure
189 * dereference by hardcoding the double copy threshold in place.
191 #define TG3_RX_COPY_THRESHOLD 256
192 #if NET_IP_ALIGN == 0 || defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS)
193 #define TG3_RX_COPY_THRESH(tp) TG3_RX_COPY_THRESHOLD
195 #define TG3_RX_COPY_THRESH(tp) ((tp)->rx_copy_thresh)
198 #if (NET_IP_ALIGN != 0)
199 #define TG3_RX_OFFSET(tp) ((tp)->rx_offset)
201 #define TG3_RX_OFFSET(tp) (NET_SKB_PAD)
204 /* minimum number of free TX descriptors required to wake up TX process */
205 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
206 #define TG3_TX_BD_DMA_MAX_2K 2048
207 #define TG3_TX_BD_DMA_MAX_4K 4096
209 #define TG3_RAW_IP_ALIGN 2
211 #define TG3_FW_UPDATE_TIMEOUT_SEC 5
212 #define TG3_FW_UPDATE_FREQ_SEC (TG3_FW_UPDATE_TIMEOUT_SEC / 2)
214 #define FIRMWARE_TG3 "tigon/tg3.bin"
215 #define FIRMWARE_TG357766 "tigon/tg357766.bin"
216 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
217 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
219 static char version
[] =
220 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")";
222 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
223 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
224 MODULE_LICENSE("GPL");
225 MODULE_VERSION(DRV_MODULE_VERSION
);
226 MODULE_FIRMWARE(FIRMWARE_TG3
);
227 MODULE_FIRMWARE(FIRMWARE_TG3TSO
);
228 MODULE_FIRMWARE(FIRMWARE_TG3TSO5
);
230 static int tg3_debug
= -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
231 module_param(tg3_debug
, int, 0);
232 MODULE_PARM_DESC(tg3_debug
, "Tigon3 bitmapped debugging message enable value");
234 #define TG3_DRV_DATA_FLAG_10_100_ONLY 0x0001
235 #define TG3_DRV_DATA_FLAG_5705_10_100 0x0002
237 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl
) = {
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5700
)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5701
)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702
)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703
)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704
)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702FE
)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705
)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705_2
)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M
)},
247 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705M_2
)},
248 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702X
)},
249 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703X
)},
250 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S
)},
251 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5702A3
)},
252 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5703A3
)},
253 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5782
)},
254 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5788
)},
255 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5789
)},
256 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901
),
257 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
|
258 TG3_DRV_DATA_FLAG_5705_10_100
},
259 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5901_2
),
260 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
|
261 TG3_DRV_DATA_FLAG_5705_10_100
},
262 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5704S_2
)},
263 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5705F
),
264 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
|
265 TG3_DRV_DATA_FLAG_5705_10_100
},
266 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5721
)},
267 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5722
)},
268 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5750
)},
269 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751
)},
270 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751M
)},
271 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5751F
),
272 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
273 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752
)},
274 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5752M
)},
275 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753
)},
276 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753M
)},
277 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5753F
),
278 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
279 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754
)},
280 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5754M
)},
281 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755
)},
282 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5755M
)},
283 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5756
)},
284 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5786
)},
285 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787
)},
286 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5787M
,
287 PCI_VENDOR_ID_LENOVO
,
288 TG3PCI_SUBDEVICE_ID_LENOVO_5787M
),
289 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
290 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787M
)},
291 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5787F
),
292 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
293 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714
)},
294 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5714S
)},
295 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715
)},
296 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5715S
)},
297 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780
)},
298 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5780S
)},
299 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5781
)},
300 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906
)},
301 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5906M
)},
302 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5784
)},
303 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5764
)},
304 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5723
)},
305 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761
)},
306 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_TIGON3_5761E
)},
307 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761S
)},
308 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5761SE
)},
309 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_G
)},
310 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5785_F
)},
311 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
,
312 PCI_VENDOR_ID_AI
, TG3PCI_SUBDEVICE_ID_ACER_57780_A
),
313 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
314 {PCI_DEVICE_SUB(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
,
315 PCI_VENDOR_ID_AI
, TG3PCI_SUBDEVICE_ID_ACER_57780_B
),
316 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
317 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57780
)},
318 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57760
)},
319 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57790
),
320 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
321 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57788
)},
322 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717
)},
323 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5717_C
)},
324 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5718
)},
325 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57781
)},
326 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57785
)},
327 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57761
)},
328 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57765
)},
329 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57791
),
330 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
331 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57795
),
332 .driver_data
= TG3_DRV_DATA_FLAG_10_100_ONLY
},
333 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5719
)},
334 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5720
)},
335 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57762
)},
336 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_57766
)},
337 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5762
)},
338 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5725
)},
339 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, TG3PCI_DEVICE_TIGON3_5727
)},
340 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9DXX
)},
341 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, PCI_DEVICE_ID_SYSKONNECT_9MXX
)},
342 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1000
)},
343 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1001
)},
344 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC1003
)},
345 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA
, PCI_DEVICE_ID_ALTIMA_AC9100
)},
346 {PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_TIGON3
)},
347 {PCI_DEVICE(0x10cf, 0x11a2)}, /* Fujitsu 1000base-SX with BCM5703SKHB */
351 MODULE_DEVICE_TABLE(pci
, tg3_pci_tbl
);
353 static const struct {
354 const char string
[ETH_GSTRING_LEN
];
355 } ethtool_stats_keys
[] = {
358 { "rx_ucast_packets" },
359 { "rx_mcast_packets" },
360 { "rx_bcast_packets" },
362 { "rx_align_errors" },
363 { "rx_xon_pause_rcvd" },
364 { "rx_xoff_pause_rcvd" },
365 { "rx_mac_ctrl_rcvd" },
366 { "rx_xoff_entered" },
367 { "rx_frame_too_long_errors" },
369 { "rx_undersize_packets" },
370 { "rx_in_length_errors" },
371 { "rx_out_length_errors" },
372 { "rx_64_or_less_octet_packets" },
373 { "rx_65_to_127_octet_packets" },
374 { "rx_128_to_255_octet_packets" },
375 { "rx_256_to_511_octet_packets" },
376 { "rx_512_to_1023_octet_packets" },
377 { "rx_1024_to_1522_octet_packets" },
378 { "rx_1523_to_2047_octet_packets" },
379 { "rx_2048_to_4095_octet_packets" },
380 { "rx_4096_to_8191_octet_packets" },
381 { "rx_8192_to_9022_octet_packets" },
388 { "tx_flow_control" },
390 { "tx_single_collisions" },
391 { "tx_mult_collisions" },
393 { "tx_excessive_collisions" },
394 { "tx_late_collisions" },
395 { "tx_collide_2times" },
396 { "tx_collide_3times" },
397 { "tx_collide_4times" },
398 { "tx_collide_5times" },
399 { "tx_collide_6times" },
400 { "tx_collide_7times" },
401 { "tx_collide_8times" },
402 { "tx_collide_9times" },
403 { "tx_collide_10times" },
404 { "tx_collide_11times" },
405 { "tx_collide_12times" },
406 { "tx_collide_13times" },
407 { "tx_collide_14times" },
408 { "tx_collide_15times" },
409 { "tx_ucast_packets" },
410 { "tx_mcast_packets" },
411 { "tx_bcast_packets" },
412 { "tx_carrier_sense_errors" },
416 { "dma_writeq_full" },
417 { "dma_write_prioq_full" },
421 { "rx_threshold_hit" },
423 { "dma_readq_full" },
424 { "dma_read_prioq_full" },
425 { "tx_comp_queue_full" },
427 { "ring_set_send_prod_index" },
428 { "ring_status_update" },
430 { "nic_avoided_irqs" },
431 { "nic_tx_threshold_hit" },
433 { "mbuf_lwm_thresh_hit" },
436 #define TG3_NUM_STATS ARRAY_SIZE(ethtool_stats_keys)
437 #define TG3_NVRAM_TEST 0
438 #define TG3_LINK_TEST 1
439 #define TG3_REGISTER_TEST 2
440 #define TG3_MEMORY_TEST 3
441 #define TG3_MAC_LOOPB_TEST 4
442 #define TG3_PHY_LOOPB_TEST 5
443 #define TG3_EXT_LOOPB_TEST 6
444 #define TG3_INTERRUPT_TEST 7
447 static const struct {
448 const char string
[ETH_GSTRING_LEN
];
449 } ethtool_test_keys
[] = {
450 [TG3_NVRAM_TEST
] = { "nvram test (online) " },
451 [TG3_LINK_TEST
] = { "link test (online) " },
452 [TG3_REGISTER_TEST
] = { "register test (offline)" },
453 [TG3_MEMORY_TEST
] = { "memory test (offline)" },
454 [TG3_MAC_LOOPB_TEST
] = { "mac loopback test (offline)" },
455 [TG3_PHY_LOOPB_TEST
] = { "phy loopback test (offline)" },
456 [TG3_EXT_LOOPB_TEST
] = { "ext loopback test (offline)" },
457 [TG3_INTERRUPT_TEST
] = { "interrupt test (offline)" },
460 #define TG3_NUM_TEST ARRAY_SIZE(ethtool_test_keys)
463 static void tg3_write32(struct tg3
*tp
, u32 off
, u32 val
)
465 writel(val
, tp
->regs
+ off
);
468 static u32
tg3_read32(struct tg3
*tp
, u32 off
)
470 return readl(tp
->regs
+ off
);
473 static void tg3_ape_write32(struct tg3
*tp
, u32 off
, u32 val
)
475 writel(val
, tp
->aperegs
+ off
);
478 static u32
tg3_ape_read32(struct tg3
*tp
, u32 off
)
480 return readl(tp
->aperegs
+ off
);
483 static void tg3_write_indirect_reg32(struct tg3
*tp
, u32 off
, u32 val
)
487 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
488 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
489 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
490 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
493 static void tg3_write_flush_reg32(struct tg3
*tp
, u32 off
, u32 val
)
495 writel(val
, tp
->regs
+ off
);
496 readl(tp
->regs
+ off
);
499 static u32
tg3_read_indirect_reg32(struct tg3
*tp
, u32 off
)
504 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
505 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
);
506 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
507 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
511 static void tg3_write_indirect_mbox(struct tg3
*tp
, u32 off
, u32 val
)
515 if (off
== (MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
)) {
516 pci_write_config_dword(tp
->pdev
, TG3PCI_RCV_RET_RING_CON_IDX
+
517 TG3_64BIT_REG_LOW
, val
);
520 if (off
== TG3_RX_STD_PROD_IDX_REG
) {
521 pci_write_config_dword(tp
->pdev
, TG3PCI_STD_RING_PROD_IDX
+
522 TG3_64BIT_REG_LOW
, val
);
526 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
527 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
528 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, val
);
529 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
531 /* In indirect mode when disabling interrupts, we also need
532 * to clear the interrupt bit in the GRC local ctrl register.
534 if ((off
== (MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
)) &&
536 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_LOCAL_CTRL
,
537 tp
->grc_local_ctrl
|GRC_LCLCTRL_CLEARINT
);
541 static u32
tg3_read_indirect_mbox(struct tg3
*tp
, u32 off
)
546 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
547 pci_write_config_dword(tp
->pdev
, TG3PCI_REG_BASE_ADDR
, off
+ 0x5600);
548 pci_read_config_dword(tp
->pdev
, TG3PCI_REG_DATA
, &val
);
549 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
553 /* usec_wait specifies the wait time in usec when writing to certain registers
554 * where it is unsafe to read back the register without some delay.
555 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
556 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
558 static void _tw32_flush(struct tg3
*tp
, u32 off
, u32 val
, u32 usec_wait
)
560 if (tg3_flag(tp
, PCIX_TARGET_HWBUG
) || tg3_flag(tp
, ICH_WORKAROUND
))
561 /* Non-posted methods */
562 tp
->write32(tp
, off
, val
);
565 tg3_write32(tp
, off
, val
);
570 /* Wait again after the read for the posted method to guarantee that
571 * the wait time is met.
577 static inline void tw32_mailbox_flush(struct tg3
*tp
, u32 off
, u32 val
)
579 tp
->write32_mbox(tp
, off
, val
);
580 if (tg3_flag(tp
, FLUSH_POSTED_WRITES
) ||
581 (!tg3_flag(tp
, MBOX_WRITE_REORDER
) &&
582 !tg3_flag(tp
, ICH_WORKAROUND
)))
583 tp
->read32_mbox(tp
, off
);
586 static void tg3_write32_tx_mbox(struct tg3
*tp
, u32 off
, u32 val
)
588 void __iomem
*mbox
= tp
->regs
+ off
;
590 if (tg3_flag(tp
, TXD_MBOX_HWBUG
))
592 if (tg3_flag(tp
, MBOX_WRITE_REORDER
) ||
593 tg3_flag(tp
, FLUSH_POSTED_WRITES
))
597 static u32
tg3_read32_mbox_5906(struct tg3
*tp
, u32 off
)
599 return readl(tp
->regs
+ off
+ GRCMBOX_BASE
);
602 static void tg3_write32_mbox_5906(struct tg3
*tp
, u32 off
, u32 val
)
604 writel(val
, tp
->regs
+ off
+ GRCMBOX_BASE
);
607 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
608 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
609 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
610 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
611 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
613 #define tw32(reg, val) tp->write32(tp, reg, val)
614 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
615 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
616 #define tr32(reg) tp->read32(tp, reg)
618 static void tg3_write_mem(struct tg3
*tp
, u32 off
, u32 val
)
622 if (tg3_asic_rev(tp
) == ASIC_REV_5906
&&
623 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
))
626 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
627 if (tg3_flag(tp
, SRAM_USE_CONFIG
)) {
628 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
629 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
631 /* Always leave this as zero. */
632 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
634 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
635 tw32_f(TG3PCI_MEM_WIN_DATA
, val
);
637 /* Always leave this as zero. */
638 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
640 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
643 static void tg3_read_mem(struct tg3
*tp
, u32 off
, u32
*val
)
647 if (tg3_asic_rev(tp
) == ASIC_REV_5906
&&
648 (off
>= NIC_SRAM_STATS_BLK
) && (off
< NIC_SRAM_TX_BUFFER_DESC
)) {
653 spin_lock_irqsave(&tp
->indirect_lock
, flags
);
654 if (tg3_flag(tp
, SRAM_USE_CONFIG
)) {
655 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, off
);
656 pci_read_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
658 /* Always leave this as zero. */
659 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
661 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, off
);
662 *val
= tr32(TG3PCI_MEM_WIN_DATA
);
664 /* Always leave this as zero. */
665 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
667 spin_unlock_irqrestore(&tp
->indirect_lock
, flags
);
670 static void tg3_ape_lock_init(struct tg3
*tp
)
675 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
676 regbase
= TG3_APE_LOCK_GRANT
;
678 regbase
= TG3_APE_PER_LOCK_GRANT
;
680 /* Make sure the driver hasn't any stale locks. */
681 for (i
= TG3_APE_LOCK_PHY0
; i
<= TG3_APE_LOCK_GPIO
; i
++) {
683 case TG3_APE_LOCK_PHY0
:
684 case TG3_APE_LOCK_PHY1
:
685 case TG3_APE_LOCK_PHY2
:
686 case TG3_APE_LOCK_PHY3
:
687 bit
= APE_LOCK_GRANT_DRIVER
;
691 bit
= APE_LOCK_GRANT_DRIVER
;
693 bit
= 1 << tp
->pci_fn
;
695 tg3_ape_write32(tp
, regbase
+ 4 * i
, bit
);
700 static int tg3_ape_lock(struct tg3
*tp
, int locknum
)
704 u32 status
, req
, gnt
, bit
;
706 if (!tg3_flag(tp
, ENABLE_APE
))
710 case TG3_APE_LOCK_GPIO
:
711 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
713 case TG3_APE_LOCK_GRC
:
714 case TG3_APE_LOCK_MEM
:
716 bit
= APE_LOCK_REQ_DRIVER
;
718 bit
= 1 << tp
->pci_fn
;
720 case TG3_APE_LOCK_PHY0
:
721 case TG3_APE_LOCK_PHY1
:
722 case TG3_APE_LOCK_PHY2
:
723 case TG3_APE_LOCK_PHY3
:
724 bit
= APE_LOCK_REQ_DRIVER
;
730 if (tg3_asic_rev(tp
) == ASIC_REV_5761
) {
731 req
= TG3_APE_LOCK_REQ
;
732 gnt
= TG3_APE_LOCK_GRANT
;
734 req
= TG3_APE_PER_LOCK_REQ
;
735 gnt
= TG3_APE_PER_LOCK_GRANT
;
740 tg3_ape_write32(tp
, req
+ off
, bit
);
742 /* Wait for up to 1 millisecond to acquire lock. */
743 for (i
= 0; i
< 100; i
++) {
744 status
= tg3_ape_read32(tp
, gnt
+ off
);
751 /* Revoke the lock request. */
752 tg3_ape_write32(tp
, gnt
+ off
, bit
);
759 static void tg3_ape_unlock(struct tg3
*tp
, int locknum
)
763 if (!tg3_flag(tp
, ENABLE_APE
))
767 case TG3_APE_LOCK_GPIO
:
768 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
770 case TG3_APE_LOCK_GRC
:
771 case TG3_APE_LOCK_MEM
:
773 bit
= APE_LOCK_GRANT_DRIVER
;
775 bit
= 1 << tp
->pci_fn
;
777 case TG3_APE_LOCK_PHY0
:
778 case TG3_APE_LOCK_PHY1
:
779 case TG3_APE_LOCK_PHY2
:
780 case TG3_APE_LOCK_PHY3
:
781 bit
= APE_LOCK_GRANT_DRIVER
;
787 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
788 gnt
= TG3_APE_LOCK_GRANT
;
790 gnt
= TG3_APE_PER_LOCK_GRANT
;
792 tg3_ape_write32(tp
, gnt
+ 4 * locknum
, bit
);
795 static int tg3_ape_event_lock(struct tg3
*tp
, u32 timeout_us
)
800 if (tg3_ape_lock(tp
, TG3_APE_LOCK_MEM
))
803 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
804 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
807 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
810 timeout_us
-= (timeout_us
> 10) ? 10 : timeout_us
;
813 return timeout_us
? 0 : -EBUSY
;
816 static int tg3_ape_wait_for_event(struct tg3
*tp
, u32 timeout_us
)
820 for (i
= 0; i
< timeout_us
/ 10; i
++) {
821 apedata
= tg3_ape_read32(tp
, TG3_APE_EVENT_STATUS
);
823 if (!(apedata
& APE_EVENT_STATUS_EVENT_PENDING
))
829 return i
== timeout_us
/ 10;
832 static int tg3_ape_scratchpad_read(struct tg3
*tp
, u32
*data
, u32 base_off
,
836 u32 i
, bufoff
, msgoff
, maxlen
, apedata
;
838 if (!tg3_flag(tp
, APE_HAS_NCSI
))
841 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
842 if (apedata
!= APE_SEG_SIG_MAGIC
)
845 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
846 if (!(apedata
& APE_FW_STATUS_READY
))
849 bufoff
= tg3_ape_read32(tp
, TG3_APE_SEG_MSG_BUF_OFF
) +
851 msgoff
= bufoff
+ 2 * sizeof(u32
);
852 maxlen
= tg3_ape_read32(tp
, TG3_APE_SEG_MSG_BUF_LEN
);
857 /* Cap xfer sizes to scratchpad limits. */
858 length
= (len
> maxlen
) ? maxlen
: len
;
861 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
862 if (!(apedata
& APE_FW_STATUS_READY
))
865 /* Wait for up to 1 msec for APE to service previous event. */
866 err
= tg3_ape_event_lock(tp
, 1000);
870 apedata
= APE_EVENT_STATUS_DRIVER_EVNT
|
871 APE_EVENT_STATUS_SCRTCHPD_READ
|
872 APE_EVENT_STATUS_EVENT_PENDING
;
873 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
, apedata
);
875 tg3_ape_write32(tp
, bufoff
, base_off
);
876 tg3_ape_write32(tp
, bufoff
+ sizeof(u32
), length
);
878 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
879 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
883 if (tg3_ape_wait_for_event(tp
, 30000))
886 for (i
= 0; length
; i
+= 4, length
-= 4) {
887 u32 val
= tg3_ape_read32(tp
, msgoff
+ i
);
888 memcpy(data
, &val
, sizeof(u32
));
896 static int tg3_ape_send_event(struct tg3
*tp
, u32 event
)
901 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
902 if (apedata
!= APE_SEG_SIG_MAGIC
)
905 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
906 if (!(apedata
& APE_FW_STATUS_READY
))
909 /* Wait for up to 1 millisecond for APE to service previous event. */
910 err
= tg3_ape_event_lock(tp
, 1000);
914 tg3_ape_write32(tp
, TG3_APE_EVENT_STATUS
,
915 event
| APE_EVENT_STATUS_EVENT_PENDING
);
917 tg3_ape_unlock(tp
, TG3_APE_LOCK_MEM
);
918 tg3_ape_write32(tp
, TG3_APE_EVENT
, APE_EVENT_1
);
923 static void tg3_ape_driver_state_change(struct tg3
*tp
, int kind
)
928 if (!tg3_flag(tp
, ENABLE_APE
))
932 case RESET_KIND_INIT
:
933 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
,
934 APE_HOST_SEG_SIG_MAGIC
);
935 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_LEN
,
936 APE_HOST_SEG_LEN_MAGIC
);
937 apedata
= tg3_ape_read32(tp
, TG3_APE_HOST_INIT_COUNT
);
938 tg3_ape_write32(tp
, TG3_APE_HOST_INIT_COUNT
, ++apedata
);
939 tg3_ape_write32(tp
, TG3_APE_HOST_DRIVER_ID
,
940 APE_HOST_DRIVER_ID_MAGIC(TG3_MAJ_NUM
, TG3_MIN_NUM
));
941 tg3_ape_write32(tp
, TG3_APE_HOST_BEHAVIOR
,
942 APE_HOST_BEHAV_NO_PHYLOCK
);
943 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
,
944 TG3_APE_HOST_DRVR_STATE_START
);
946 event
= APE_EVENT_STATUS_STATE_START
;
948 case RESET_KIND_SHUTDOWN
:
949 /* With the interface we are currently using,
950 * APE does not track driver state. Wiping
951 * out the HOST SEGMENT SIGNATURE forces
952 * the APE to assume OS absent status.
954 tg3_ape_write32(tp
, TG3_APE_HOST_SEG_SIG
, 0x0);
956 if (device_may_wakeup(&tp
->pdev
->dev
) &&
957 tg3_flag(tp
, WOL_ENABLE
)) {
958 tg3_ape_write32(tp
, TG3_APE_HOST_WOL_SPEED
,
959 TG3_APE_HOST_WOL_SPEED_AUTO
);
960 apedata
= TG3_APE_HOST_DRVR_STATE_WOL
;
962 apedata
= TG3_APE_HOST_DRVR_STATE_UNLOAD
;
964 tg3_ape_write32(tp
, TG3_APE_HOST_DRVR_STATE
, apedata
);
966 event
= APE_EVENT_STATUS_STATE_UNLOAD
;
968 case RESET_KIND_SUSPEND
:
969 event
= APE_EVENT_STATUS_STATE_SUSPEND
;
975 event
|= APE_EVENT_STATUS_DRIVER_EVNT
| APE_EVENT_STATUS_STATE_CHNGE
;
977 tg3_ape_send_event(tp
, event
);
980 static void tg3_disable_ints(struct tg3
*tp
)
984 tw32(TG3PCI_MISC_HOST_CTRL
,
985 (tp
->misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
));
986 for (i
= 0; i
< tp
->irq_max
; i
++)
987 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 0x00000001);
990 static void tg3_enable_ints(struct tg3
*tp
)
997 tw32(TG3PCI_MISC_HOST_CTRL
,
998 (tp
->misc_host_ctrl
& ~MISC_HOST_CTRL_MASK_PCI_INT
));
1000 tp
->coal_now
= tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
;
1001 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
1002 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
1004 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
1005 if (tg3_flag(tp
, 1SHOT_MSI
))
1006 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
1008 tp
->coal_now
|= tnapi
->coal_now
;
1011 /* Force an initial interrupt */
1012 if (!tg3_flag(tp
, TAGGED_STATUS
) &&
1013 (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
))
1014 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
1016 tw32(HOSTCC_MODE
, tp
->coal_now
);
1018 tp
->coal_now
&= ~(tp
->napi
[0].coal_now
| tp
->napi
[1].coal_now
);
1021 static inline unsigned int tg3_has_work(struct tg3_napi
*tnapi
)
1023 struct tg3
*tp
= tnapi
->tp
;
1024 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
1025 unsigned int work_exists
= 0;
1027 /* check for phy events */
1028 if (!(tg3_flag(tp
, USE_LINKCHG_REG
) || tg3_flag(tp
, POLL_SERDES
))) {
1029 if (sblk
->status
& SD_STATUS_LINK_CHG
)
1033 /* check for TX work to do */
1034 if (sblk
->idx
[0].tx_consumer
!= tnapi
->tx_cons
)
1037 /* check for RX work to do */
1038 if (tnapi
->rx_rcb_prod_idx
&&
1039 *(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
1046 * similar to tg3_enable_ints, but it accurately determines whether there
1047 * is new work pending and can return without flushing the PIO write
1048 * which reenables interrupts
1050 static void tg3_int_reenable(struct tg3_napi
*tnapi
)
1052 struct tg3
*tp
= tnapi
->tp
;
1054 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
1057 /* When doing tagged status, this work check is unnecessary.
1058 * The last_tag we write above tells the chip which piece of
1059 * work we've completed.
1061 if (!tg3_flag(tp
, TAGGED_STATUS
) && tg3_has_work(tnapi
))
1062 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
1063 HOSTCC_MODE_ENABLE
| tnapi
->coal_now
);
1066 static void tg3_switch_clocks(struct tg3
*tp
)
1069 u32 orig_clock_ctrl
;
1071 if (tg3_flag(tp
, CPMU_PRESENT
) || tg3_flag(tp
, 5780_CLASS
))
1074 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
);
1076 orig_clock_ctrl
= clock_ctrl
;
1077 clock_ctrl
&= (CLOCK_CTRL_FORCE_CLKRUN
|
1078 CLOCK_CTRL_CLKRUN_OENABLE
|
1080 tp
->pci_clock_ctrl
= clock_ctrl
;
1082 if (tg3_flag(tp
, 5705_PLUS
)) {
1083 if (orig_clock_ctrl
& CLOCK_CTRL_625_CORE
) {
1084 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
1085 clock_ctrl
| CLOCK_CTRL_625_CORE
, 40);
1087 } else if ((orig_clock_ctrl
& CLOCK_CTRL_44MHZ_CORE
) != 0) {
1088 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
1090 (CLOCK_CTRL_44MHZ_CORE
| CLOCK_CTRL_ALTCLK
),
1092 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
1093 clock_ctrl
| (CLOCK_CTRL_ALTCLK
),
1096 tw32_wait_f(TG3PCI_CLOCK_CTRL
, clock_ctrl
, 40);
1099 #define PHY_BUSY_LOOPS 5000
1101 static int __tg3_readphy(struct tg3
*tp
, unsigned int phy_addr
, int reg
,
1108 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
1110 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
1114 tg3_ape_lock(tp
, tp
->phy_ape_lock
);
1118 frame_val
= ((phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
1119 MI_COM_PHY_ADDR_MASK
);
1120 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
1121 MI_COM_REG_ADDR_MASK
);
1122 frame_val
|= (MI_COM_CMD_READ
| MI_COM_START
);
1124 tw32_f(MAC_MI_COM
, frame_val
);
1126 loops
= PHY_BUSY_LOOPS
;
1127 while (loops
!= 0) {
1129 frame_val
= tr32(MAC_MI_COM
);
1131 if ((frame_val
& MI_COM_BUSY
) == 0) {
1133 frame_val
= tr32(MAC_MI_COM
);
1141 *val
= frame_val
& MI_COM_DATA_MASK
;
1145 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
1146 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1150 tg3_ape_unlock(tp
, tp
->phy_ape_lock
);
1155 static int tg3_readphy(struct tg3
*tp
, int reg
, u32
*val
)
1157 return __tg3_readphy(tp
, tp
->phy_addr
, reg
, val
);
1160 static int __tg3_writephy(struct tg3
*tp
, unsigned int phy_addr
, int reg
,
1167 if ((tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
1168 (reg
== MII_CTRL1000
|| reg
== MII_TG3_AUX_CTRL
))
1171 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
1173 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
1177 tg3_ape_lock(tp
, tp
->phy_ape_lock
);
1179 frame_val
= ((phy_addr
<< MI_COM_PHY_ADDR_SHIFT
) &
1180 MI_COM_PHY_ADDR_MASK
);
1181 frame_val
|= ((reg
<< MI_COM_REG_ADDR_SHIFT
) &
1182 MI_COM_REG_ADDR_MASK
);
1183 frame_val
|= (val
& MI_COM_DATA_MASK
);
1184 frame_val
|= (MI_COM_CMD_WRITE
| MI_COM_START
);
1186 tw32_f(MAC_MI_COM
, frame_val
);
1188 loops
= PHY_BUSY_LOOPS
;
1189 while (loops
!= 0) {
1191 frame_val
= tr32(MAC_MI_COM
);
1192 if ((frame_val
& MI_COM_BUSY
) == 0) {
1194 frame_val
= tr32(MAC_MI_COM
);
1204 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
1205 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1209 tg3_ape_unlock(tp
, tp
->phy_ape_lock
);
1214 static int tg3_writephy(struct tg3
*tp
, int reg
, u32 val
)
1216 return __tg3_writephy(tp
, tp
->phy_addr
, reg
, val
);
1219 static int tg3_phy_cl45_write(struct tg3
*tp
, u32 devad
, u32 addr
, u32 val
)
1223 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
, devad
);
1227 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, addr
);
1231 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
,
1232 MII_TG3_MMD_CTRL_DATA_NOINC
| devad
);
1236 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, val
);
1242 static int tg3_phy_cl45_read(struct tg3
*tp
, u32 devad
, u32 addr
, u32
*val
)
1246 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
, devad
);
1250 err
= tg3_writephy(tp
, MII_TG3_MMD_ADDRESS
, addr
);
1254 err
= tg3_writephy(tp
, MII_TG3_MMD_CTRL
,
1255 MII_TG3_MMD_CTRL_DATA_NOINC
| devad
);
1259 err
= tg3_readphy(tp
, MII_TG3_MMD_ADDRESS
, val
);
1265 static int tg3_phydsp_read(struct tg3
*tp
, u32 reg
, u32
*val
)
1269 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1271 err
= tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1276 static int tg3_phydsp_write(struct tg3
*tp
, u32 reg
, u32 val
)
1280 err
= tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, reg
);
1282 err
= tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, val
);
1287 static int tg3_phy_auxctl_read(struct tg3
*tp
, int reg
, u32
*val
)
1291 err
= tg3_writephy(tp
, MII_TG3_AUX_CTRL
,
1292 (reg
<< MII_TG3_AUXCTL_MISC_RDSEL_SHIFT
) |
1293 MII_TG3_AUXCTL_SHDWSEL_MISC
);
1295 err
= tg3_readphy(tp
, MII_TG3_AUX_CTRL
, val
);
1300 static int tg3_phy_auxctl_write(struct tg3
*tp
, int reg
, u32 set
)
1302 if (reg
== MII_TG3_AUXCTL_SHDWSEL_MISC
)
1303 set
|= MII_TG3_AUXCTL_MISC_WREN
;
1305 return tg3_writephy(tp
, MII_TG3_AUX_CTRL
, set
| reg
);
1308 static int tg3_phy_toggle_auxctl_smdsp(struct tg3
*tp
, bool enable
)
1313 err
= tg3_phy_auxctl_read(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, &val
);
1319 val
|= MII_TG3_AUXCTL_ACTL_SMDSP_ENA
;
1321 val
&= ~MII_TG3_AUXCTL_ACTL_SMDSP_ENA
;
1323 err
= tg3_phy_auxctl_write((tp
), MII_TG3_AUXCTL_SHDWSEL_AUXCTL
,
1324 val
| MII_TG3_AUXCTL_ACTL_TX_6DB
);
1329 static int tg3_bmcr_reset(struct tg3
*tp
)
1334 /* OK, reset it, and poll the BMCR_RESET bit until it
1335 * clears or we time out.
1337 phy_control
= BMCR_RESET
;
1338 err
= tg3_writephy(tp
, MII_BMCR
, phy_control
);
1344 err
= tg3_readphy(tp
, MII_BMCR
, &phy_control
);
1348 if ((phy_control
& BMCR_RESET
) == 0) {
1360 static int tg3_mdio_read(struct mii_bus
*bp
, int mii_id
, int reg
)
1362 struct tg3
*tp
= bp
->priv
;
1365 spin_lock_bh(&tp
->lock
);
1367 if (tg3_readphy(tp
, reg
, &val
))
1370 spin_unlock_bh(&tp
->lock
);
1375 static int tg3_mdio_write(struct mii_bus
*bp
, int mii_id
, int reg
, u16 val
)
1377 struct tg3
*tp
= bp
->priv
;
1380 spin_lock_bh(&tp
->lock
);
1382 if (tg3_writephy(tp
, reg
, val
))
1385 spin_unlock_bh(&tp
->lock
);
1390 static int tg3_mdio_reset(struct mii_bus
*bp
)
1395 static void tg3_mdio_config_5785(struct tg3
*tp
)
1398 struct phy_device
*phydev
;
1400 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1401 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1402 case PHY_ID_BCM50610
:
1403 case PHY_ID_BCM50610M
:
1404 val
= MAC_PHYCFG2_50610_LED_MODES
;
1406 case PHY_ID_BCMAC131
:
1407 val
= MAC_PHYCFG2_AC131_LED_MODES
;
1409 case PHY_ID_RTL8211C
:
1410 val
= MAC_PHYCFG2_RTL8211C_LED_MODES
;
1412 case PHY_ID_RTL8201E
:
1413 val
= MAC_PHYCFG2_RTL8201E_LED_MODES
;
1419 if (phydev
->interface
!= PHY_INTERFACE_MODE_RGMII
) {
1420 tw32(MAC_PHYCFG2
, val
);
1422 val
= tr32(MAC_PHYCFG1
);
1423 val
&= ~(MAC_PHYCFG1_RGMII_INT
|
1424 MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
);
1425 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
;
1426 tw32(MAC_PHYCFG1
, val
);
1431 if (!tg3_flag(tp
, RGMII_INBAND_DISABLE
))
1432 val
|= MAC_PHYCFG2_EMODE_MASK_MASK
|
1433 MAC_PHYCFG2_FMODE_MASK_MASK
|
1434 MAC_PHYCFG2_GMODE_MASK_MASK
|
1435 MAC_PHYCFG2_ACT_MASK_MASK
|
1436 MAC_PHYCFG2_QUAL_MASK_MASK
|
1437 MAC_PHYCFG2_INBAND_ENABLE
;
1439 tw32(MAC_PHYCFG2
, val
);
1441 val
= tr32(MAC_PHYCFG1
);
1442 val
&= ~(MAC_PHYCFG1_RXCLK_TO_MASK
| MAC_PHYCFG1_TXCLK_TO_MASK
|
1443 MAC_PHYCFG1_RGMII_EXT_RX_DEC
| MAC_PHYCFG1_RGMII_SND_STAT_EN
);
1444 if (!tg3_flag(tp
, RGMII_INBAND_DISABLE
)) {
1445 if (tg3_flag(tp
, RGMII_EXT_IBND_RX_EN
))
1446 val
|= MAC_PHYCFG1_RGMII_EXT_RX_DEC
;
1447 if (tg3_flag(tp
, RGMII_EXT_IBND_TX_EN
))
1448 val
|= MAC_PHYCFG1_RGMII_SND_STAT_EN
;
1450 val
|= MAC_PHYCFG1_RXCLK_TIMEOUT
| MAC_PHYCFG1_TXCLK_TIMEOUT
|
1451 MAC_PHYCFG1_RGMII_INT
| MAC_PHYCFG1_TXC_DRV
;
1452 tw32(MAC_PHYCFG1
, val
);
1454 val
= tr32(MAC_EXT_RGMII_MODE
);
1455 val
&= ~(MAC_RGMII_MODE_RX_INT_B
|
1456 MAC_RGMII_MODE_RX_QUALITY
|
1457 MAC_RGMII_MODE_RX_ACTIVITY
|
1458 MAC_RGMII_MODE_RX_ENG_DET
|
1459 MAC_RGMII_MODE_TX_ENABLE
|
1460 MAC_RGMII_MODE_TX_LOWPWR
|
1461 MAC_RGMII_MODE_TX_RESET
);
1462 if (!tg3_flag(tp
, RGMII_INBAND_DISABLE
)) {
1463 if (tg3_flag(tp
, RGMII_EXT_IBND_RX_EN
))
1464 val
|= MAC_RGMII_MODE_RX_INT_B
|
1465 MAC_RGMII_MODE_RX_QUALITY
|
1466 MAC_RGMII_MODE_RX_ACTIVITY
|
1467 MAC_RGMII_MODE_RX_ENG_DET
;
1468 if (tg3_flag(tp
, RGMII_EXT_IBND_TX_EN
))
1469 val
|= MAC_RGMII_MODE_TX_ENABLE
|
1470 MAC_RGMII_MODE_TX_LOWPWR
|
1471 MAC_RGMII_MODE_TX_RESET
;
1473 tw32(MAC_EXT_RGMII_MODE
, val
);
1476 static void tg3_mdio_start(struct tg3
*tp
)
1478 tp
->mi_mode
&= ~MAC_MI_MODE_AUTO_POLL
;
1479 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
1482 if (tg3_flag(tp
, MDIOBUS_INITED
) &&
1483 tg3_asic_rev(tp
) == ASIC_REV_5785
)
1484 tg3_mdio_config_5785(tp
);
1487 static int tg3_mdio_init(struct tg3
*tp
)
1491 struct phy_device
*phydev
;
1493 if (tg3_flag(tp
, 5717_PLUS
)) {
1496 tp
->phy_addr
= tp
->pci_fn
+ 1;
1498 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5717_A0
)
1499 is_serdes
= tr32(SG_DIG_STATUS
) & SG_DIG_IS_SERDES
;
1501 is_serdes
= tr32(TG3_CPMU_PHY_STRAP
) &
1502 TG3_CPMU_PHY_STRAP_IS_SERDES
;
1506 tp
->phy_addr
= TG3_PHY_MII_ADDR
;
1510 if (!tg3_flag(tp
, USE_PHYLIB
) || tg3_flag(tp
, MDIOBUS_INITED
))
1513 tp
->mdio_bus
= mdiobus_alloc();
1514 if (tp
->mdio_bus
== NULL
)
1517 tp
->mdio_bus
->name
= "tg3 mdio bus";
1518 snprintf(tp
->mdio_bus
->id
, MII_BUS_ID_SIZE
, "%x",
1519 (tp
->pdev
->bus
->number
<< 8) | tp
->pdev
->devfn
);
1520 tp
->mdio_bus
->priv
= tp
;
1521 tp
->mdio_bus
->parent
= &tp
->pdev
->dev
;
1522 tp
->mdio_bus
->read
= &tg3_mdio_read
;
1523 tp
->mdio_bus
->write
= &tg3_mdio_write
;
1524 tp
->mdio_bus
->reset
= &tg3_mdio_reset
;
1525 tp
->mdio_bus
->phy_mask
= ~(1 << TG3_PHY_MII_ADDR
);
1526 tp
->mdio_bus
->irq
= &tp
->mdio_irq
[0];
1528 for (i
= 0; i
< PHY_MAX_ADDR
; i
++)
1529 tp
->mdio_bus
->irq
[i
] = PHY_POLL
;
1531 /* The bus registration will look for all the PHYs on the mdio bus.
1532 * Unfortunately, it does not ensure the PHY is powered up before
1533 * accessing the PHY ID registers. A chip reset is the
1534 * quickest way to bring the device back to an operational state..
1536 if (tg3_readphy(tp
, MII_BMCR
, ®
) || (reg
& BMCR_PDOWN
))
1539 i
= mdiobus_register(tp
->mdio_bus
);
1541 dev_warn(&tp
->pdev
->dev
, "mdiobus_reg failed (0x%x)\n", i
);
1542 mdiobus_free(tp
->mdio_bus
);
1546 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1548 if (!phydev
|| !phydev
->drv
) {
1549 dev_warn(&tp
->pdev
->dev
, "No PHY devices\n");
1550 mdiobus_unregister(tp
->mdio_bus
);
1551 mdiobus_free(tp
->mdio_bus
);
1555 switch (phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
) {
1556 case PHY_ID_BCM57780
:
1557 phydev
->interface
= PHY_INTERFACE_MODE_GMII
;
1558 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1560 case PHY_ID_BCM50610
:
1561 case PHY_ID_BCM50610M
:
1562 phydev
->dev_flags
|= PHY_BRCM_CLEAR_RGMII_MODE
|
1563 PHY_BRCM_RX_REFCLK_UNUSED
|
1564 PHY_BRCM_DIS_TXCRXC_NOENRGY
|
1565 PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1566 if (tg3_flag(tp
, RGMII_INBAND_DISABLE
))
1567 phydev
->dev_flags
|= PHY_BRCM_STD_IBND_DISABLE
;
1568 if (tg3_flag(tp
, RGMII_EXT_IBND_RX_EN
))
1569 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_RX_ENABLE
;
1570 if (tg3_flag(tp
, RGMII_EXT_IBND_TX_EN
))
1571 phydev
->dev_flags
|= PHY_BRCM_EXT_IBND_TX_ENABLE
;
1573 case PHY_ID_RTL8211C
:
1574 phydev
->interface
= PHY_INTERFACE_MODE_RGMII
;
1576 case PHY_ID_RTL8201E
:
1577 case PHY_ID_BCMAC131
:
1578 phydev
->interface
= PHY_INTERFACE_MODE_MII
;
1579 phydev
->dev_flags
|= PHY_BRCM_AUTO_PWRDWN_ENABLE
;
1580 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
1584 tg3_flag_set(tp
, MDIOBUS_INITED
);
1586 if (tg3_asic_rev(tp
) == ASIC_REV_5785
)
1587 tg3_mdio_config_5785(tp
);
1592 static void tg3_mdio_fini(struct tg3
*tp
)
1594 if (tg3_flag(tp
, MDIOBUS_INITED
)) {
1595 tg3_flag_clear(tp
, MDIOBUS_INITED
);
1596 mdiobus_unregister(tp
->mdio_bus
);
1597 mdiobus_free(tp
->mdio_bus
);
1601 /* tp->lock is held. */
1602 static inline void tg3_generate_fw_event(struct tg3
*tp
)
1606 val
= tr32(GRC_RX_CPU_EVENT
);
1607 val
|= GRC_RX_CPU_DRIVER_EVENT
;
1608 tw32_f(GRC_RX_CPU_EVENT
, val
);
1610 tp
->last_event_jiffies
= jiffies
;
1613 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1615 /* tp->lock is held. */
1616 static void tg3_wait_for_event_ack(struct tg3
*tp
)
1619 unsigned int delay_cnt
;
1622 /* If enough time has passed, no wait is necessary. */
1623 time_remain
= (long)(tp
->last_event_jiffies
+ 1 +
1624 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC
)) -
1626 if (time_remain
< 0)
1629 /* Check if we can shorten the wait time. */
1630 delay_cnt
= jiffies_to_usecs(time_remain
);
1631 if (delay_cnt
> TG3_FW_EVENT_TIMEOUT_USEC
)
1632 delay_cnt
= TG3_FW_EVENT_TIMEOUT_USEC
;
1633 delay_cnt
= (delay_cnt
>> 3) + 1;
1635 for (i
= 0; i
< delay_cnt
; i
++) {
1636 if (!(tr32(GRC_RX_CPU_EVENT
) & GRC_RX_CPU_DRIVER_EVENT
))
1642 /* tp->lock is held. */
1643 static void tg3_phy_gather_ump_data(struct tg3
*tp
, u32
*data
)
1648 if (!tg3_readphy(tp
, MII_BMCR
, ®
))
1650 if (!tg3_readphy(tp
, MII_BMSR
, ®
))
1651 val
|= (reg
& 0xffff);
1655 if (!tg3_readphy(tp
, MII_ADVERTISE
, ®
))
1657 if (!tg3_readphy(tp
, MII_LPA
, ®
))
1658 val
|= (reg
& 0xffff);
1662 if (!(tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)) {
1663 if (!tg3_readphy(tp
, MII_CTRL1000
, ®
))
1665 if (!tg3_readphy(tp
, MII_STAT1000
, ®
))
1666 val
|= (reg
& 0xffff);
1670 if (!tg3_readphy(tp
, MII_PHYADDR
, ®
))
1677 /* tp->lock is held. */
1678 static void tg3_ump_link_report(struct tg3
*tp
)
1682 if (!tg3_flag(tp
, 5780_CLASS
) || !tg3_flag(tp
, ENABLE_ASF
))
1685 tg3_phy_gather_ump_data(tp
, data
);
1687 tg3_wait_for_event_ack(tp
);
1689 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_LINK_UPDATE
);
1690 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 14);
1691 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 0x0, data
[0]);
1692 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 0x4, data
[1]);
1693 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 0x8, data
[2]);
1694 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
+ 0xc, data
[3]);
1696 tg3_generate_fw_event(tp
);
1699 /* tp->lock is held. */
1700 static void tg3_stop_fw(struct tg3
*tp
)
1702 if (tg3_flag(tp
, ENABLE_ASF
) && !tg3_flag(tp
, ENABLE_APE
)) {
1703 /* Wait for RX cpu to ACK the previous event. */
1704 tg3_wait_for_event_ack(tp
);
1706 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
, FWCMD_NICDRV_PAUSE_FW
);
1708 tg3_generate_fw_event(tp
);
1710 /* Wait for RX cpu to ACK this event. */
1711 tg3_wait_for_event_ack(tp
);
1715 /* tp->lock is held. */
1716 static void tg3_write_sig_pre_reset(struct tg3
*tp
, int kind
)
1718 tg3_write_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
,
1719 NIC_SRAM_FIRMWARE_MBOX_MAGIC1
);
1721 if (tg3_flag(tp
, ASF_NEW_HANDSHAKE
)) {
1723 case RESET_KIND_INIT
:
1724 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1728 case RESET_KIND_SHUTDOWN
:
1729 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1733 case RESET_KIND_SUSPEND
:
1734 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1743 if (kind
== RESET_KIND_INIT
||
1744 kind
== RESET_KIND_SUSPEND
)
1745 tg3_ape_driver_state_change(tp
, kind
);
1748 /* tp->lock is held. */
1749 static void tg3_write_sig_post_reset(struct tg3
*tp
, int kind
)
1751 if (tg3_flag(tp
, ASF_NEW_HANDSHAKE
)) {
1753 case RESET_KIND_INIT
:
1754 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1755 DRV_STATE_START_DONE
);
1758 case RESET_KIND_SHUTDOWN
:
1759 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1760 DRV_STATE_UNLOAD_DONE
);
1768 if (kind
== RESET_KIND_SHUTDOWN
)
1769 tg3_ape_driver_state_change(tp
, kind
);
1772 /* tp->lock is held. */
1773 static void tg3_write_sig_legacy(struct tg3
*tp
, int kind
)
1775 if (tg3_flag(tp
, ENABLE_ASF
)) {
1777 case RESET_KIND_INIT
:
1778 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1782 case RESET_KIND_SHUTDOWN
:
1783 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1787 case RESET_KIND_SUSPEND
:
1788 tg3_write_mem(tp
, NIC_SRAM_FW_DRV_STATE_MBOX
,
1798 static int tg3_poll_fw(struct tg3
*tp
)
1803 if (tg3_flag(tp
, IS_SSB_CORE
)) {
1804 /* We don't use firmware. */
1808 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
1809 /* Wait up to 20ms for init done. */
1810 for (i
= 0; i
< 200; i
++) {
1811 if (tr32(VCPU_STATUS
) & VCPU_STATUS_INIT_DONE
)
1818 /* Wait for firmware initialization to complete. */
1819 for (i
= 0; i
< 100000; i
++) {
1820 tg3_read_mem(tp
, NIC_SRAM_FIRMWARE_MBOX
, &val
);
1821 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
1826 /* Chip might not be fitted with firmware. Some Sun onboard
1827 * parts are configured like that. So don't signal the timeout
1828 * of the above loop as an error, but do report the lack of
1829 * running firmware once.
1831 if (i
>= 100000 && !tg3_flag(tp
, NO_FWARE_REPORTED
)) {
1832 tg3_flag_set(tp
, NO_FWARE_REPORTED
);
1834 netdev_info(tp
->dev
, "No firmware running\n");
1837 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_57765_A0
) {
1838 /* The 57765 A0 needs a little more
1839 * time to do some important work.
1847 static void tg3_link_report(struct tg3
*tp
)
1849 if (!netif_carrier_ok(tp
->dev
)) {
1850 netif_info(tp
, link
, tp
->dev
, "Link is down\n");
1851 tg3_ump_link_report(tp
);
1852 } else if (netif_msg_link(tp
)) {
1853 netdev_info(tp
->dev
, "Link is up at %d Mbps, %s duplex\n",
1854 (tp
->link_config
.active_speed
== SPEED_1000
?
1856 (tp
->link_config
.active_speed
== SPEED_100
?
1858 (tp
->link_config
.active_duplex
== DUPLEX_FULL
?
1861 netdev_info(tp
->dev
, "Flow control is %s for TX and %s for RX\n",
1862 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_TX
) ?
1864 (tp
->link_config
.active_flowctrl
& FLOW_CTRL_RX
) ?
1867 if (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
)
1868 netdev_info(tp
->dev
, "EEE is %s\n",
1869 tp
->setlpicnt
? "enabled" : "disabled");
1871 tg3_ump_link_report(tp
);
1874 tp
->link_up
= netif_carrier_ok(tp
->dev
);
1877 static u32
tg3_decode_flowctrl_1000T(u32 adv
)
1881 if (adv
& ADVERTISE_PAUSE_CAP
) {
1882 flowctrl
|= FLOW_CTRL_RX
;
1883 if (!(adv
& ADVERTISE_PAUSE_ASYM
))
1884 flowctrl
|= FLOW_CTRL_TX
;
1885 } else if (adv
& ADVERTISE_PAUSE_ASYM
)
1886 flowctrl
|= FLOW_CTRL_TX
;
1891 static u16
tg3_advert_flowctrl_1000X(u8 flow_ctrl
)
1895 if ((flow_ctrl
& FLOW_CTRL_TX
) && (flow_ctrl
& FLOW_CTRL_RX
))
1896 miireg
= ADVERTISE_1000XPAUSE
;
1897 else if (flow_ctrl
& FLOW_CTRL_TX
)
1898 miireg
= ADVERTISE_1000XPSE_ASYM
;
1899 else if (flow_ctrl
& FLOW_CTRL_RX
)
1900 miireg
= ADVERTISE_1000XPAUSE
| ADVERTISE_1000XPSE_ASYM
;
1907 static u32
tg3_decode_flowctrl_1000X(u32 adv
)
1911 if (adv
& ADVERTISE_1000XPAUSE
) {
1912 flowctrl
|= FLOW_CTRL_RX
;
1913 if (!(adv
& ADVERTISE_1000XPSE_ASYM
))
1914 flowctrl
|= FLOW_CTRL_TX
;
1915 } else if (adv
& ADVERTISE_1000XPSE_ASYM
)
1916 flowctrl
|= FLOW_CTRL_TX
;
1921 static u8
tg3_resolve_flowctrl_1000X(u16 lcladv
, u16 rmtadv
)
1925 if (lcladv
& rmtadv
& ADVERTISE_1000XPAUSE
) {
1926 cap
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
1927 } else if (lcladv
& rmtadv
& ADVERTISE_1000XPSE_ASYM
) {
1928 if (lcladv
& ADVERTISE_1000XPAUSE
)
1930 if (rmtadv
& ADVERTISE_1000XPAUSE
)
1937 static void tg3_setup_flow_control(struct tg3
*tp
, u32 lcladv
, u32 rmtadv
)
1941 u32 old_rx_mode
= tp
->rx_mode
;
1942 u32 old_tx_mode
= tp
->tx_mode
;
1944 if (tg3_flag(tp
, USE_PHYLIB
))
1945 autoneg
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]->autoneg
;
1947 autoneg
= tp
->link_config
.autoneg
;
1949 if (autoneg
== AUTONEG_ENABLE
&& tg3_flag(tp
, PAUSE_AUTONEG
)) {
1950 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
1951 flowctrl
= tg3_resolve_flowctrl_1000X(lcladv
, rmtadv
);
1953 flowctrl
= mii_resolve_flowctrl_fdx(lcladv
, rmtadv
);
1955 flowctrl
= tp
->link_config
.flowctrl
;
1957 tp
->link_config
.active_flowctrl
= flowctrl
;
1959 if (flowctrl
& FLOW_CTRL_RX
)
1960 tp
->rx_mode
|= RX_MODE_FLOW_CTRL_ENABLE
;
1962 tp
->rx_mode
&= ~RX_MODE_FLOW_CTRL_ENABLE
;
1964 if (old_rx_mode
!= tp
->rx_mode
)
1965 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
1967 if (flowctrl
& FLOW_CTRL_TX
)
1968 tp
->tx_mode
|= TX_MODE_FLOW_CTRL_ENABLE
;
1970 tp
->tx_mode
&= ~TX_MODE_FLOW_CTRL_ENABLE
;
1972 if (old_tx_mode
!= tp
->tx_mode
)
1973 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
1976 static void tg3_adjust_link(struct net_device
*dev
)
1978 u8 oldflowctrl
, linkmesg
= 0;
1979 u32 mac_mode
, lcl_adv
, rmt_adv
;
1980 struct tg3
*tp
= netdev_priv(dev
);
1981 struct phy_device
*phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
1983 spin_lock_bh(&tp
->lock
);
1985 mac_mode
= tp
->mac_mode
& ~(MAC_MODE_PORT_MODE_MASK
|
1986 MAC_MODE_HALF_DUPLEX
);
1988 oldflowctrl
= tp
->link_config
.active_flowctrl
;
1994 if (phydev
->speed
== SPEED_100
|| phydev
->speed
== SPEED_10
)
1995 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
1996 else if (phydev
->speed
== SPEED_1000
||
1997 tg3_asic_rev(tp
) != ASIC_REV_5785
)
1998 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
2000 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
2002 if (phydev
->duplex
== DUPLEX_HALF
)
2003 mac_mode
|= MAC_MODE_HALF_DUPLEX
;
2005 lcl_adv
= mii_advertise_flowctrl(
2006 tp
->link_config
.flowctrl
);
2009 rmt_adv
= LPA_PAUSE_CAP
;
2010 if (phydev
->asym_pause
)
2011 rmt_adv
|= LPA_PAUSE_ASYM
;
2014 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
2016 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
2018 if (mac_mode
!= tp
->mac_mode
) {
2019 tp
->mac_mode
= mac_mode
;
2020 tw32_f(MAC_MODE
, tp
->mac_mode
);
2024 if (tg3_asic_rev(tp
) == ASIC_REV_5785
) {
2025 if (phydev
->speed
== SPEED_10
)
2027 MAC_MI_STAT_10MBPS_MODE
|
2028 MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
2030 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
2033 if (phydev
->speed
== SPEED_1000
&& phydev
->duplex
== DUPLEX_HALF
)
2034 tw32(MAC_TX_LENGTHS
,
2035 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
2036 (6 << TX_LENGTHS_IPG_SHIFT
) |
2037 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
)));
2039 tw32(MAC_TX_LENGTHS
,
2040 ((2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
2041 (6 << TX_LENGTHS_IPG_SHIFT
) |
2042 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
)));
2044 if (phydev
->link
!= tp
->old_link
||
2045 phydev
->speed
!= tp
->link_config
.active_speed
||
2046 phydev
->duplex
!= tp
->link_config
.active_duplex
||
2047 oldflowctrl
!= tp
->link_config
.active_flowctrl
)
2050 tp
->old_link
= phydev
->link
;
2051 tp
->link_config
.active_speed
= phydev
->speed
;
2052 tp
->link_config
.active_duplex
= phydev
->duplex
;
2054 spin_unlock_bh(&tp
->lock
);
2057 tg3_link_report(tp
);
2060 static int tg3_phy_init(struct tg3
*tp
)
2062 struct phy_device
*phydev
;
2064 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
)
2067 /* Bring the PHY back to a known state. */
2070 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2072 /* Attach the MAC to the PHY. */
2073 phydev
= phy_connect(tp
->dev
, dev_name(&phydev
->dev
),
2074 tg3_adjust_link
, phydev
->interface
);
2075 if (IS_ERR(phydev
)) {
2076 dev_err(&tp
->pdev
->dev
, "Could not attach to PHY\n");
2077 return PTR_ERR(phydev
);
2080 /* Mask with MAC supported features. */
2081 switch (phydev
->interface
) {
2082 case PHY_INTERFACE_MODE_GMII
:
2083 case PHY_INTERFACE_MODE_RGMII
:
2084 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
2085 phydev
->supported
&= (PHY_GBIT_FEATURES
|
2087 SUPPORTED_Asym_Pause
);
2091 case PHY_INTERFACE_MODE_MII
:
2092 phydev
->supported
&= (PHY_BASIC_FEATURES
|
2094 SUPPORTED_Asym_Pause
);
2097 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
2101 tp
->phy_flags
|= TG3_PHYFLG_IS_CONNECTED
;
2103 phydev
->advertising
= phydev
->supported
;
2108 static void tg3_phy_start(struct tg3
*tp
)
2110 struct phy_device
*phydev
;
2112 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
2115 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
2117 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) {
2118 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
2119 phydev
->speed
= tp
->link_config
.speed
;
2120 phydev
->duplex
= tp
->link_config
.duplex
;
2121 phydev
->autoneg
= tp
->link_config
.autoneg
;
2122 phydev
->advertising
= tp
->link_config
.advertising
;
2127 phy_start_aneg(phydev
);
2130 static void tg3_phy_stop(struct tg3
*tp
)
2132 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
2135 phy_stop(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
2138 static void tg3_phy_fini(struct tg3
*tp
)
2140 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
2141 phy_disconnect(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
2142 tp
->phy_flags
&= ~TG3_PHYFLG_IS_CONNECTED
;
2146 static int tg3_phy_set_extloopbk(struct tg3
*tp
)
2151 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
2154 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2155 /* Cannot do read-modify-write on 5401 */
2156 err
= tg3_phy_auxctl_write(tp
,
2157 MII_TG3_AUXCTL_SHDWSEL_AUXCTL
,
2158 MII_TG3_AUXCTL_ACTL_EXTLOOPBK
|
2163 err
= tg3_phy_auxctl_read(tp
,
2164 MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, &val
);
2168 val
|= MII_TG3_AUXCTL_ACTL_EXTLOOPBK
;
2169 err
= tg3_phy_auxctl_write(tp
,
2170 MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, val
);
2176 static void tg3_phy_fet_toggle_apd(struct tg3
*tp
, bool enable
)
2180 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
2183 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2184 phytest
| MII_TG3_FET_SHADOW_EN
);
2185 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, &phy
)) {
2187 phy
|= MII_TG3_FET_SHDW_AUXSTAT2_APD
;
2189 phy
&= ~MII_TG3_FET_SHDW_AUXSTAT2_APD
;
2190 tg3_writephy(tp
, MII_TG3_FET_SHDW_AUXSTAT2
, phy
);
2192 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
2196 static void tg3_phy_toggle_apd(struct tg3
*tp
, bool enable
)
2200 if (!tg3_flag(tp
, 5705_PLUS
) ||
2201 (tg3_flag(tp
, 5717_PLUS
) &&
2202 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)))
2205 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2206 tg3_phy_fet_toggle_apd(tp
, enable
);
2210 reg
= MII_TG3_MISC_SHDW_WREN
|
2211 MII_TG3_MISC_SHDW_SCR5_SEL
|
2212 MII_TG3_MISC_SHDW_SCR5_LPED
|
2213 MII_TG3_MISC_SHDW_SCR5_DLPTLM
|
2214 MII_TG3_MISC_SHDW_SCR5_SDTL
|
2215 MII_TG3_MISC_SHDW_SCR5_C125OE
;
2216 if (tg3_asic_rev(tp
) != ASIC_REV_5784
|| !enable
)
2217 reg
|= MII_TG3_MISC_SHDW_SCR5_DLLAPD
;
2219 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
2222 reg
= MII_TG3_MISC_SHDW_WREN
|
2223 MII_TG3_MISC_SHDW_APD_SEL
|
2224 MII_TG3_MISC_SHDW_APD_WKTM_84MS
;
2226 reg
|= MII_TG3_MISC_SHDW_APD_ENABLE
;
2228 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, reg
);
2231 static void tg3_phy_toggle_automdix(struct tg3
*tp
, bool enable
)
2235 if (!tg3_flag(tp
, 5705_PLUS
) ||
2236 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
2239 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
2242 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &ephy
)) {
2243 u32 reg
= MII_TG3_FET_SHDW_MISCCTRL
;
2245 tg3_writephy(tp
, MII_TG3_FET_TEST
,
2246 ephy
| MII_TG3_FET_SHADOW_EN
);
2247 if (!tg3_readphy(tp
, reg
, &phy
)) {
2249 phy
|= MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
2251 phy
&= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX
;
2252 tg3_writephy(tp
, reg
, phy
);
2254 tg3_writephy(tp
, MII_TG3_FET_TEST
, ephy
);
2259 ret
= tg3_phy_auxctl_read(tp
,
2260 MII_TG3_AUXCTL_SHDWSEL_MISC
, &phy
);
2263 phy
|= MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
2265 phy
&= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX
;
2266 tg3_phy_auxctl_write(tp
,
2267 MII_TG3_AUXCTL_SHDWSEL_MISC
, phy
);
2272 static void tg3_phy_set_wirespeed(struct tg3
*tp
)
2277 if (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
)
2280 ret
= tg3_phy_auxctl_read(tp
, MII_TG3_AUXCTL_SHDWSEL_MISC
, &val
);
2282 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_MISC
,
2283 val
| MII_TG3_AUXCTL_MISC_WIRESPD_EN
);
2286 static void tg3_phy_apply_otp(struct tg3
*tp
)
2295 if (tg3_phy_toggle_auxctl_smdsp(tp
, true))
2298 phy
= ((otp
& TG3_OTP_AGCTGT_MASK
) >> TG3_OTP_AGCTGT_SHIFT
);
2299 phy
|= MII_TG3_DSP_TAP1_AGCTGT_DFLT
;
2300 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP1
, phy
);
2302 phy
= ((otp
& TG3_OTP_HPFFLTR_MASK
) >> TG3_OTP_HPFFLTR_SHIFT
) |
2303 ((otp
& TG3_OTP_HPFOVER_MASK
) >> TG3_OTP_HPFOVER_SHIFT
);
2304 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH0
, phy
);
2306 phy
= ((otp
& TG3_OTP_LPFDIS_MASK
) >> TG3_OTP_LPFDIS_SHIFT
);
2307 phy
|= MII_TG3_DSP_AADJ1CH3_ADCCKADJ
;
2308 tg3_phydsp_write(tp
, MII_TG3_DSP_AADJ1CH3
, phy
);
2310 phy
= ((otp
& TG3_OTP_VDAC_MASK
) >> TG3_OTP_VDAC_SHIFT
);
2311 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP75
, phy
);
2313 phy
= ((otp
& TG3_OTP_10BTAMP_MASK
) >> TG3_OTP_10BTAMP_SHIFT
);
2314 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP96
, phy
);
2316 phy
= ((otp
& TG3_OTP_ROFF_MASK
) >> TG3_OTP_ROFF_SHIFT
) |
2317 ((otp
& TG3_OTP_RCOFF_MASK
) >> TG3_OTP_RCOFF_SHIFT
);
2318 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP97
, phy
);
2320 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2323 static void tg3_eee_pull_config(struct tg3
*tp
, struct ethtool_eee
*eee
)
2326 struct ethtool_eee
*dest
= &tp
->eee
;
2328 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
2334 if (tg3_phy_cl45_read(tp
, MDIO_MMD_AN
, TG3_CL45_D7_EEERES_STAT
, &val
))
2337 /* Pull eee_active */
2338 if (val
== TG3_CL45_D7_EEERES_STAT_LP_1000T
||
2339 val
== TG3_CL45_D7_EEERES_STAT_LP_100TX
) {
2340 dest
->eee_active
= 1;
2342 dest
->eee_active
= 0;
2344 /* Pull lp advertised settings */
2345 if (tg3_phy_cl45_read(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_LPABLE
, &val
))
2347 dest
->lp_advertised
= mmd_eee_adv_to_ethtool_adv_t(val
);
2349 /* Pull advertised and eee_enabled settings */
2350 if (tg3_phy_cl45_read(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, &val
))
2352 dest
->eee_enabled
= !!val
;
2353 dest
->advertised
= mmd_eee_adv_to_ethtool_adv_t(val
);
2355 /* Pull tx_lpi_enabled */
2356 val
= tr32(TG3_CPMU_EEE_MODE
);
2357 dest
->tx_lpi_enabled
= !!(val
& TG3_CPMU_EEEMD_LPI_IN_TX
);
2359 /* Pull lpi timer value */
2360 dest
->tx_lpi_timer
= tr32(TG3_CPMU_EEE_DBTMR1
) & 0xffff;
2363 static void tg3_phy_eee_adjust(struct tg3
*tp
, bool current_link_up
)
2367 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
2372 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
2374 tp
->link_config
.active_duplex
== DUPLEX_FULL
&&
2375 (tp
->link_config
.active_speed
== SPEED_100
||
2376 tp
->link_config
.active_speed
== SPEED_1000
)) {
2379 if (tp
->link_config
.active_speed
== SPEED_1000
)
2380 eeectl
= TG3_CPMU_EEE_CTRL_EXIT_16_5_US
;
2382 eeectl
= TG3_CPMU_EEE_CTRL_EXIT_36_US
;
2384 tw32(TG3_CPMU_EEE_CTRL
, eeectl
);
2386 tg3_eee_pull_config(tp
, NULL
);
2387 if (tp
->eee
.eee_active
)
2391 if (!tp
->setlpicnt
) {
2392 if (current_link_up
&&
2393 !tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2394 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, 0x0000);
2395 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2398 val
= tr32(TG3_CPMU_EEE_MODE
);
2399 tw32(TG3_CPMU_EEE_MODE
, val
& ~TG3_CPMU_EEEMD_LPI_ENABLE
);
2403 static void tg3_phy_eee_enable(struct tg3
*tp
)
2407 if (tp
->link_config
.active_speed
== SPEED_1000
&&
2408 (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2409 tg3_asic_rev(tp
) == ASIC_REV_5719
||
2410 tg3_flag(tp
, 57765_CLASS
)) &&
2411 !tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2412 val
= MII_TG3_DSP_TAP26_ALNOKO
|
2413 MII_TG3_DSP_TAP26_RMRXSTO
;
2414 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, val
);
2415 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2418 val
= tr32(TG3_CPMU_EEE_MODE
);
2419 tw32(TG3_CPMU_EEE_MODE
, val
| TG3_CPMU_EEEMD_LPI_ENABLE
);
2422 static int tg3_wait_macro_done(struct tg3
*tp
)
2429 if (!tg3_readphy(tp
, MII_TG3_DSP_CONTROL
, &tmp32
)) {
2430 if ((tmp32
& 0x1000) == 0)
2440 static int tg3_phy_write_and_check_testpat(struct tg3
*tp
, int *resetp
)
2442 static const u32 test_pat
[4][6] = {
2443 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
2444 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
2445 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
2446 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
2450 for (chan
= 0; chan
< 4; chan
++) {
2453 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
2454 (chan
* 0x2000) | 0x0200);
2455 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
2457 for (i
= 0; i
< 6; i
++)
2458 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
,
2461 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
2462 if (tg3_wait_macro_done(tp
)) {
2467 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
2468 (chan
* 0x2000) | 0x0200);
2469 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0082);
2470 if (tg3_wait_macro_done(tp
)) {
2475 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0802);
2476 if (tg3_wait_macro_done(tp
)) {
2481 for (i
= 0; i
< 6; i
+= 2) {
2484 if (tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &low
) ||
2485 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &high
) ||
2486 tg3_wait_macro_done(tp
)) {
2492 if (low
!= test_pat
[chan
][i
] ||
2493 high
!= test_pat
[chan
][i
+1]) {
2494 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000b);
2495 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4001);
2496 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x4005);
2506 static int tg3_phy_reset_chanpat(struct tg3
*tp
)
2510 for (chan
= 0; chan
< 4; chan
++) {
2513 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
2514 (chan
* 0x2000) | 0x0200);
2515 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0002);
2516 for (i
= 0; i
< 6; i
++)
2517 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x000);
2518 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0202);
2519 if (tg3_wait_macro_done(tp
))
2526 static int tg3_phy_reset_5703_4_5(struct tg3
*tp
)
2528 u32 reg32
, phy9_orig
;
2529 int retries
, do_phy_reset
, err
;
2535 err
= tg3_bmcr_reset(tp
);
2541 /* Disable transmitter and interrupt. */
2542 if (tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
))
2546 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
2548 /* Set full-duplex, 1000 mbps. */
2549 tg3_writephy(tp
, MII_BMCR
,
2550 BMCR_FULLDPLX
| BMCR_SPEED1000
);
2552 /* Set to master mode. */
2553 if (tg3_readphy(tp
, MII_CTRL1000
, &phy9_orig
))
2556 tg3_writephy(tp
, MII_CTRL1000
,
2557 CTL1000_AS_MASTER
| CTL1000_ENABLE_MASTER
);
2559 err
= tg3_phy_toggle_auxctl_smdsp(tp
, true);
2563 /* Block the PHY control access. */
2564 tg3_phydsp_write(tp
, 0x8005, 0x0800);
2566 err
= tg3_phy_write_and_check_testpat(tp
, &do_phy_reset
);
2569 } while (--retries
);
2571 err
= tg3_phy_reset_chanpat(tp
);
2575 tg3_phydsp_write(tp
, 0x8005, 0x0000);
2577 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x8200);
2578 tg3_writephy(tp
, MII_TG3_DSP_CONTROL
, 0x0000);
2580 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2582 tg3_writephy(tp
, MII_CTRL1000
, phy9_orig
);
2584 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, ®32
)) {
2586 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, reg32
);
2593 static void tg3_carrier_off(struct tg3
*tp
)
2595 netif_carrier_off(tp
->dev
);
2596 tp
->link_up
= false;
2599 static void tg3_warn_mgmt_link_flap(struct tg3
*tp
)
2601 if (tg3_flag(tp
, ENABLE_ASF
))
2602 netdev_warn(tp
->dev
,
2603 "Management side-band traffic will be interrupted during phy settings change\n");
2606 /* This will reset the tigon3 PHY if there is no valid
2607 * link unless the FORCE argument is non-zero.
2609 static int tg3_phy_reset(struct tg3
*tp
)
2614 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
2615 val
= tr32(GRC_MISC_CFG
);
2616 tw32_f(GRC_MISC_CFG
, val
& ~GRC_MISC_CFG_EPHY_IDDQ
);
2619 err
= tg3_readphy(tp
, MII_BMSR
, &val
);
2620 err
|= tg3_readphy(tp
, MII_BMSR
, &val
);
2624 if (netif_running(tp
->dev
) && tp
->link_up
) {
2625 netif_carrier_off(tp
->dev
);
2626 tg3_link_report(tp
);
2629 if (tg3_asic_rev(tp
) == ASIC_REV_5703
||
2630 tg3_asic_rev(tp
) == ASIC_REV_5704
||
2631 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
2632 err
= tg3_phy_reset_5703_4_5(tp
);
2639 if (tg3_asic_rev(tp
) == ASIC_REV_5784
&&
2640 tg3_chip_rev(tp
) != CHIPREV_5784_AX
) {
2641 cpmuctrl
= tr32(TG3_CPMU_CTRL
);
2642 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
)
2644 cpmuctrl
& ~CPMU_CTRL_GPHY_10MB_RXONLY
);
2647 err
= tg3_bmcr_reset(tp
);
2651 if (cpmuctrl
& CPMU_CTRL_GPHY_10MB_RXONLY
) {
2652 val
= MII_TG3_DSP_EXP8_AEDW
| MII_TG3_DSP_EXP8_REJ2MHz
;
2653 tg3_phydsp_write(tp
, MII_TG3_DSP_EXP8
, val
);
2655 tw32(TG3_CPMU_CTRL
, cpmuctrl
);
2658 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
||
2659 tg3_chip_rev(tp
) == CHIPREV_5761_AX
) {
2660 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
2661 if ((val
& CPMU_LSPD_1000MB_MACCLK_MASK
) ==
2662 CPMU_LSPD_1000MB_MACCLK_12_5
) {
2663 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
2665 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
2669 if (tg3_flag(tp
, 5717_PLUS
) &&
2670 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
))
2673 tg3_phy_apply_otp(tp
);
2675 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
2676 tg3_phy_toggle_apd(tp
, true);
2678 tg3_phy_toggle_apd(tp
, false);
2681 if ((tp
->phy_flags
& TG3_PHYFLG_ADC_BUG
) &&
2682 !tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2683 tg3_phydsp_write(tp
, 0x201f, 0x2aaa);
2684 tg3_phydsp_write(tp
, 0x000a, 0x0323);
2685 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2688 if (tp
->phy_flags
& TG3_PHYFLG_5704_A0_BUG
) {
2689 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2690 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
2693 if (tp
->phy_flags
& TG3_PHYFLG_BER_BUG
) {
2694 if (!tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2695 tg3_phydsp_write(tp
, 0x000a, 0x310b);
2696 tg3_phydsp_write(tp
, 0x201f, 0x9506);
2697 tg3_phydsp_write(tp
, 0x401f, 0x14e2);
2698 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2700 } else if (tp
->phy_flags
& TG3_PHYFLG_JITTER_BUG
) {
2701 if (!tg3_phy_toggle_auxctl_smdsp(tp
, true)) {
2702 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
, 0x000a);
2703 if (tp
->phy_flags
& TG3_PHYFLG_ADJUST_TRIM
) {
2704 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x110b);
2705 tg3_writephy(tp
, MII_TG3_TEST1
,
2706 MII_TG3_TEST1_TRIM_EN
| 0x4);
2708 tg3_writephy(tp
, MII_TG3_DSP_RW_PORT
, 0x010b);
2710 tg3_phy_toggle_auxctl_smdsp(tp
, false);
2714 /* Set Extended packet length bit (bit 14) on all chips that */
2715 /* support jumbo frames */
2716 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
2717 /* Cannot do read-modify-write on 5401 */
2718 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, 0x4c20);
2719 } else if (tg3_flag(tp
, JUMBO_CAPABLE
)) {
2720 /* Set bit 14 with read-modify-write to preserve other bits */
2721 err
= tg3_phy_auxctl_read(tp
,
2722 MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, &val
);
2724 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
,
2725 val
| MII_TG3_AUXCTL_ACTL_EXTPKTLEN
);
2728 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2729 * jumbo frames transmission.
2731 if (tg3_flag(tp
, JUMBO_CAPABLE
)) {
2732 if (!tg3_readphy(tp
, MII_TG3_EXT_CTRL
, &val
))
2733 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
2734 val
| MII_TG3_EXT_CTRL_FIFO_ELASTIC
);
2737 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
2738 /* adjust output voltage */
2739 tg3_writephy(tp
, MII_TG3_FET_PTEST
, 0x12);
2742 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5762_A0
)
2743 tg3_phydsp_write(tp
, 0xffb, 0x4000);
2745 tg3_phy_toggle_automdix(tp
, true);
2746 tg3_phy_set_wirespeed(tp
);
2750 #define TG3_GPIO_MSG_DRVR_PRES 0x00000001
2751 #define TG3_GPIO_MSG_NEED_VAUX 0x00000002
2752 #define TG3_GPIO_MSG_MASK (TG3_GPIO_MSG_DRVR_PRES | \
2753 TG3_GPIO_MSG_NEED_VAUX)
2754 #define TG3_GPIO_MSG_ALL_DRVR_PRES_MASK \
2755 ((TG3_GPIO_MSG_DRVR_PRES << 0) | \
2756 (TG3_GPIO_MSG_DRVR_PRES << 4) | \
2757 (TG3_GPIO_MSG_DRVR_PRES << 8) | \
2758 (TG3_GPIO_MSG_DRVR_PRES << 12))
2760 #define TG3_GPIO_MSG_ALL_NEED_VAUX_MASK \
2761 ((TG3_GPIO_MSG_NEED_VAUX << 0) | \
2762 (TG3_GPIO_MSG_NEED_VAUX << 4) | \
2763 (TG3_GPIO_MSG_NEED_VAUX << 8) | \
2764 (TG3_GPIO_MSG_NEED_VAUX << 12))
2766 static inline u32
tg3_set_function_status(struct tg3
*tp
, u32 newstat
)
2770 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2771 tg3_asic_rev(tp
) == ASIC_REV_5719
)
2772 status
= tg3_ape_read32(tp
, TG3_APE_GPIO_MSG
);
2774 status
= tr32(TG3_CPMU_DRV_STATUS
);
2776 shift
= TG3_APE_GPIO_MSG_SHIFT
+ 4 * tp
->pci_fn
;
2777 status
&= ~(TG3_GPIO_MSG_MASK
<< shift
);
2778 status
|= (newstat
<< shift
);
2780 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2781 tg3_asic_rev(tp
) == ASIC_REV_5719
)
2782 tg3_ape_write32(tp
, TG3_APE_GPIO_MSG
, status
);
2784 tw32(TG3_CPMU_DRV_STATUS
, status
);
2786 return status
>> TG3_APE_GPIO_MSG_SHIFT
;
2789 static inline int tg3_pwrsrc_switch_to_vmain(struct tg3
*tp
)
2791 if (!tg3_flag(tp
, IS_NIC
))
2794 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2795 tg3_asic_rev(tp
) == ASIC_REV_5719
||
2796 tg3_asic_rev(tp
) == ASIC_REV_5720
) {
2797 if (tg3_ape_lock(tp
, TG3_APE_LOCK_GPIO
))
2800 tg3_set_function_status(tp
, TG3_GPIO_MSG_DRVR_PRES
);
2802 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
,
2803 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2805 tg3_ape_unlock(tp
, TG3_APE_LOCK_GPIO
);
2807 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
,
2808 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2814 static void tg3_pwrsrc_die_with_vmain(struct tg3
*tp
)
2818 if (!tg3_flag(tp
, IS_NIC
) ||
2819 tg3_asic_rev(tp
) == ASIC_REV_5700
||
2820 tg3_asic_rev(tp
) == ASIC_REV_5701
)
2823 grc_local_ctrl
= tp
->grc_local_ctrl
| GRC_LCLCTRL_GPIO_OE1
;
2825 tw32_wait_f(GRC_LOCAL_CTRL
,
2826 grc_local_ctrl
| GRC_LCLCTRL_GPIO_OUTPUT1
,
2827 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2829 tw32_wait_f(GRC_LOCAL_CTRL
,
2831 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2833 tw32_wait_f(GRC_LOCAL_CTRL
,
2834 grc_local_ctrl
| GRC_LCLCTRL_GPIO_OUTPUT1
,
2835 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2838 static void tg3_pwrsrc_switch_to_vaux(struct tg3
*tp
)
2840 if (!tg3_flag(tp
, IS_NIC
))
2843 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
2844 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
2845 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2846 (GRC_LCLCTRL_GPIO_OE0
|
2847 GRC_LCLCTRL_GPIO_OE1
|
2848 GRC_LCLCTRL_GPIO_OE2
|
2849 GRC_LCLCTRL_GPIO_OUTPUT0
|
2850 GRC_LCLCTRL_GPIO_OUTPUT1
),
2851 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2852 } else if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
2853 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
2854 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2855 u32 grc_local_ctrl
= GRC_LCLCTRL_GPIO_OE0
|
2856 GRC_LCLCTRL_GPIO_OE1
|
2857 GRC_LCLCTRL_GPIO_OE2
|
2858 GRC_LCLCTRL_GPIO_OUTPUT0
|
2859 GRC_LCLCTRL_GPIO_OUTPUT1
|
2861 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
,
2862 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2864 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT2
;
2865 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
,
2866 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2868 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT0
;
2869 tw32_wait_f(GRC_LOCAL_CTRL
, grc_local_ctrl
,
2870 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2873 u32 grc_local_ctrl
= 0;
2875 /* Workaround to prevent overdrawing Amps. */
2876 if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
2877 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
2878 tw32_wait_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
|
2880 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2883 /* On 5753 and variants, GPIO2 cannot be used. */
2884 no_gpio2
= tp
->nic_sram_data_cfg
&
2885 NIC_SRAM_DATA_CFG_NO_GPIO2
;
2887 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
2888 GRC_LCLCTRL_GPIO_OE1
|
2889 GRC_LCLCTRL_GPIO_OE2
|
2890 GRC_LCLCTRL_GPIO_OUTPUT1
|
2891 GRC_LCLCTRL_GPIO_OUTPUT2
;
2893 grc_local_ctrl
&= ~(GRC_LCLCTRL_GPIO_OE2
|
2894 GRC_LCLCTRL_GPIO_OUTPUT2
);
2896 tw32_wait_f(GRC_LOCAL_CTRL
,
2897 tp
->grc_local_ctrl
| grc_local_ctrl
,
2898 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2900 grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OUTPUT0
;
2902 tw32_wait_f(GRC_LOCAL_CTRL
,
2903 tp
->grc_local_ctrl
| grc_local_ctrl
,
2904 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2907 grc_local_ctrl
&= ~GRC_LCLCTRL_GPIO_OUTPUT2
;
2908 tw32_wait_f(GRC_LOCAL_CTRL
,
2909 tp
->grc_local_ctrl
| grc_local_ctrl
,
2910 TG3_GRC_LCLCTL_PWRSW_DELAY
);
2915 static void tg3_frob_aux_power_5717(struct tg3
*tp
, bool wol_enable
)
2919 /* Serialize power state transitions */
2920 if (tg3_ape_lock(tp
, TG3_APE_LOCK_GPIO
))
2923 if (tg3_flag(tp
, ENABLE_ASF
) || tg3_flag(tp
, ENABLE_APE
) || wol_enable
)
2924 msg
= TG3_GPIO_MSG_NEED_VAUX
;
2926 msg
= tg3_set_function_status(tp
, msg
);
2928 if (msg
& TG3_GPIO_MSG_ALL_DRVR_PRES_MASK
)
2931 if (msg
& TG3_GPIO_MSG_ALL_NEED_VAUX_MASK
)
2932 tg3_pwrsrc_switch_to_vaux(tp
);
2934 tg3_pwrsrc_die_with_vmain(tp
);
2937 tg3_ape_unlock(tp
, TG3_APE_LOCK_GPIO
);
2940 static void tg3_frob_aux_power(struct tg3
*tp
, bool include_wol
)
2942 bool need_vaux
= false;
2944 /* The GPIOs do something completely different on 57765. */
2945 if (!tg3_flag(tp
, IS_NIC
) || tg3_flag(tp
, 57765_CLASS
))
2948 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
2949 tg3_asic_rev(tp
) == ASIC_REV_5719
||
2950 tg3_asic_rev(tp
) == ASIC_REV_5720
) {
2951 tg3_frob_aux_power_5717(tp
, include_wol
?
2952 tg3_flag(tp
, WOL_ENABLE
) != 0 : 0);
2956 if (tp
->pdev_peer
&& tp
->pdev_peer
!= tp
->pdev
) {
2957 struct net_device
*dev_peer
;
2959 dev_peer
= pci_get_drvdata(tp
->pdev_peer
);
2961 /* remove_one() may have been run on the peer. */
2963 struct tg3
*tp_peer
= netdev_priv(dev_peer
);
2965 if (tg3_flag(tp_peer
, INIT_COMPLETE
))
2968 if ((include_wol
&& tg3_flag(tp_peer
, WOL_ENABLE
)) ||
2969 tg3_flag(tp_peer
, ENABLE_ASF
))
2974 if ((include_wol
&& tg3_flag(tp
, WOL_ENABLE
)) ||
2975 tg3_flag(tp
, ENABLE_ASF
))
2979 tg3_pwrsrc_switch_to_vaux(tp
);
2981 tg3_pwrsrc_die_with_vmain(tp
);
2984 static int tg3_5700_link_polarity(struct tg3
*tp
, u32 speed
)
2986 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_2
)
2988 else if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
) {
2989 if (speed
!= SPEED_10
)
2991 } else if (speed
== SPEED_10
)
2997 static void tg3_power_down_phy(struct tg3
*tp
, bool do_low_power
)
3001 if (tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
)
3004 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
3005 if (tg3_asic_rev(tp
) == ASIC_REV_5704
) {
3006 u32 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
3007 u32 serdes_cfg
= tr32(MAC_SERDES_CFG
);
3010 SG_DIG_USING_HW_AUTONEG
| SG_DIG_SOFT_RESET
;
3011 tw32(SG_DIG_CTRL
, sg_dig_ctrl
);
3012 tw32(MAC_SERDES_CFG
, serdes_cfg
| (1 << 15));
3017 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
3019 val
= tr32(GRC_MISC_CFG
);
3020 tw32_f(GRC_MISC_CFG
, val
| GRC_MISC_CFG_EPHY_IDDQ
);
3023 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
3025 if (!tg3_readphy(tp
, MII_TG3_FET_TEST
, &phytest
)) {
3028 tg3_writephy(tp
, MII_ADVERTISE
, 0);
3029 tg3_writephy(tp
, MII_BMCR
,
3030 BMCR_ANENABLE
| BMCR_ANRESTART
);
3032 tg3_writephy(tp
, MII_TG3_FET_TEST
,
3033 phytest
| MII_TG3_FET_SHADOW_EN
);
3034 if (!tg3_readphy(tp
, MII_TG3_FET_SHDW_AUXMODE4
, &phy
)) {
3035 phy
|= MII_TG3_FET_SHDW_AUXMODE4_SBPD
;
3037 MII_TG3_FET_SHDW_AUXMODE4
,
3040 tg3_writephy(tp
, MII_TG3_FET_TEST
, phytest
);
3043 } else if (do_low_power
) {
3044 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
3045 MII_TG3_EXT_CTRL_FORCE_LED_OFF
);
3047 val
= MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
3048 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE
|
3049 MII_TG3_AUXCTL_PCTL_VREG_11V
;
3050 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_PWRCTL
, val
);
3053 /* The PHY should not be powered down on some chips because
3056 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
3057 tg3_asic_rev(tp
) == ASIC_REV_5704
||
3058 (tg3_asic_rev(tp
) == ASIC_REV_5780
&&
3059 (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)) ||
3060 (tg3_asic_rev(tp
) == ASIC_REV_5717
&&
3064 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
||
3065 tg3_chip_rev(tp
) == CHIPREV_5761_AX
) {
3066 val
= tr32(TG3_CPMU_LSPD_1000MB_CLK
);
3067 val
&= ~CPMU_LSPD_1000MB_MACCLK_MASK
;
3068 val
|= CPMU_LSPD_1000MB_MACCLK_12_5
;
3069 tw32_f(TG3_CPMU_LSPD_1000MB_CLK
, val
);
3072 tg3_writephy(tp
, MII_BMCR
, BMCR_PDOWN
);
3075 /* tp->lock is held. */
3076 static int tg3_nvram_lock(struct tg3
*tp
)
3078 if (tg3_flag(tp
, NVRAM
)) {
3081 if (tp
->nvram_lock_cnt
== 0) {
3082 tw32(NVRAM_SWARB
, SWARB_REQ_SET1
);
3083 for (i
= 0; i
< 8000; i
++) {
3084 if (tr32(NVRAM_SWARB
) & SWARB_GNT1
)
3089 tw32(NVRAM_SWARB
, SWARB_REQ_CLR1
);
3093 tp
->nvram_lock_cnt
++;
3098 /* tp->lock is held. */
3099 static void tg3_nvram_unlock(struct tg3
*tp
)
3101 if (tg3_flag(tp
, NVRAM
)) {
3102 if (tp
->nvram_lock_cnt
> 0)
3103 tp
->nvram_lock_cnt
--;
3104 if (tp
->nvram_lock_cnt
== 0)
3105 tw32_f(NVRAM_SWARB
, SWARB_REQ_CLR1
);
3109 /* tp->lock is held. */
3110 static void tg3_enable_nvram_access(struct tg3
*tp
)
3112 if (tg3_flag(tp
, 5750_PLUS
) && !tg3_flag(tp
, PROTECTED_NVRAM
)) {
3113 u32 nvaccess
= tr32(NVRAM_ACCESS
);
3115 tw32(NVRAM_ACCESS
, nvaccess
| ACCESS_ENABLE
);
3119 /* tp->lock is held. */
3120 static void tg3_disable_nvram_access(struct tg3
*tp
)
3122 if (tg3_flag(tp
, 5750_PLUS
) && !tg3_flag(tp
, PROTECTED_NVRAM
)) {
3123 u32 nvaccess
= tr32(NVRAM_ACCESS
);
3125 tw32(NVRAM_ACCESS
, nvaccess
& ~ACCESS_ENABLE
);
3129 static int tg3_nvram_read_using_eeprom(struct tg3
*tp
,
3130 u32 offset
, u32
*val
)
3135 if (offset
> EEPROM_ADDR_ADDR_MASK
|| (offset
% 4) != 0)
3138 tmp
= tr32(GRC_EEPROM_ADDR
) & ~(EEPROM_ADDR_ADDR_MASK
|
3139 EEPROM_ADDR_DEVID_MASK
|
3141 tw32(GRC_EEPROM_ADDR
,
3143 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
3144 ((offset
<< EEPROM_ADDR_ADDR_SHIFT
) &
3145 EEPROM_ADDR_ADDR_MASK
) |
3146 EEPROM_ADDR_READ
| EEPROM_ADDR_START
);
3148 for (i
= 0; i
< 1000; i
++) {
3149 tmp
= tr32(GRC_EEPROM_ADDR
);
3151 if (tmp
& EEPROM_ADDR_COMPLETE
)
3155 if (!(tmp
& EEPROM_ADDR_COMPLETE
))
3158 tmp
= tr32(GRC_EEPROM_DATA
);
3161 * The data will always be opposite the native endian
3162 * format. Perform a blind byteswap to compensate.
3169 #define NVRAM_CMD_TIMEOUT 10000
3171 static int tg3_nvram_exec_cmd(struct tg3
*tp
, u32 nvram_cmd
)
3175 tw32(NVRAM_CMD
, nvram_cmd
);
3176 for (i
= 0; i
< NVRAM_CMD_TIMEOUT
; i
++) {
3178 if (tr32(NVRAM_CMD
) & NVRAM_CMD_DONE
) {
3184 if (i
== NVRAM_CMD_TIMEOUT
)
3190 static u32
tg3_nvram_phys_addr(struct tg3
*tp
, u32 addr
)
3192 if (tg3_flag(tp
, NVRAM
) &&
3193 tg3_flag(tp
, NVRAM_BUFFERED
) &&
3194 tg3_flag(tp
, FLASH
) &&
3195 !tg3_flag(tp
, NO_NVRAM_ADDR_TRANS
) &&
3196 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
3198 addr
= ((addr
/ tp
->nvram_pagesize
) <<
3199 ATMEL_AT45DB0X1B_PAGE_POS
) +
3200 (addr
% tp
->nvram_pagesize
);
3205 static u32
tg3_nvram_logical_addr(struct tg3
*tp
, u32 addr
)
3207 if (tg3_flag(tp
, NVRAM
) &&
3208 tg3_flag(tp
, NVRAM_BUFFERED
) &&
3209 tg3_flag(tp
, FLASH
) &&
3210 !tg3_flag(tp
, NO_NVRAM_ADDR_TRANS
) &&
3211 (tp
->nvram_jedecnum
== JEDEC_ATMEL
))
3213 addr
= ((addr
>> ATMEL_AT45DB0X1B_PAGE_POS
) *
3214 tp
->nvram_pagesize
) +
3215 (addr
& ((1 << ATMEL_AT45DB0X1B_PAGE_POS
) - 1));
3220 /* NOTE: Data read in from NVRAM is byteswapped according to
3221 * the byteswapping settings for all other register accesses.
3222 * tg3 devices are BE devices, so on a BE machine, the data
3223 * returned will be exactly as it is seen in NVRAM. On a LE
3224 * machine, the 32-bit value will be byteswapped.
3226 static int tg3_nvram_read(struct tg3
*tp
, u32 offset
, u32
*val
)
3230 if (!tg3_flag(tp
, NVRAM
))
3231 return tg3_nvram_read_using_eeprom(tp
, offset
, val
);
3233 offset
= tg3_nvram_phys_addr(tp
, offset
);
3235 if (offset
> NVRAM_ADDR_MSK
)
3238 ret
= tg3_nvram_lock(tp
);
3242 tg3_enable_nvram_access(tp
);
3244 tw32(NVRAM_ADDR
, offset
);
3245 ret
= tg3_nvram_exec_cmd(tp
, NVRAM_CMD_RD
| NVRAM_CMD_GO
|
3246 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_DONE
);
3249 *val
= tr32(NVRAM_RDDATA
);
3251 tg3_disable_nvram_access(tp
);
3253 tg3_nvram_unlock(tp
);
3258 /* Ensures NVRAM data is in bytestream format. */
3259 static int tg3_nvram_read_be32(struct tg3
*tp
, u32 offset
, __be32
*val
)
3262 int res
= tg3_nvram_read(tp
, offset
, &v
);
3264 *val
= cpu_to_be32(v
);
3268 static int tg3_nvram_write_block_using_eeprom(struct tg3
*tp
,
3269 u32 offset
, u32 len
, u8
*buf
)
3274 for (i
= 0; i
< len
; i
+= 4) {
3280 memcpy(&data
, buf
+ i
, 4);
3283 * The SEEPROM interface expects the data to always be opposite
3284 * the native endian format. We accomplish this by reversing
3285 * all the operations that would have been performed on the
3286 * data from a call to tg3_nvram_read_be32().
3288 tw32(GRC_EEPROM_DATA
, swab32(be32_to_cpu(data
)));
3290 val
= tr32(GRC_EEPROM_ADDR
);
3291 tw32(GRC_EEPROM_ADDR
, val
| EEPROM_ADDR_COMPLETE
);
3293 val
&= ~(EEPROM_ADDR_ADDR_MASK
| EEPROM_ADDR_DEVID_MASK
|
3295 tw32(GRC_EEPROM_ADDR
, val
|
3296 (0 << EEPROM_ADDR_DEVID_SHIFT
) |
3297 (addr
& EEPROM_ADDR_ADDR_MASK
) |
3301 for (j
= 0; j
< 1000; j
++) {
3302 val
= tr32(GRC_EEPROM_ADDR
);
3304 if (val
& EEPROM_ADDR_COMPLETE
)
3308 if (!(val
& EEPROM_ADDR_COMPLETE
)) {
3317 /* offset and length are dword aligned */
3318 static int tg3_nvram_write_block_unbuffered(struct tg3
*tp
, u32 offset
, u32 len
,
3322 u32 pagesize
= tp
->nvram_pagesize
;
3323 u32 pagemask
= pagesize
- 1;
3327 tmp
= kmalloc(pagesize
, GFP_KERNEL
);
3333 u32 phy_addr
, page_off
, size
;
3335 phy_addr
= offset
& ~pagemask
;
3337 for (j
= 0; j
< pagesize
; j
+= 4) {
3338 ret
= tg3_nvram_read_be32(tp
, phy_addr
+ j
,
3339 (__be32
*) (tmp
+ j
));
3346 page_off
= offset
& pagemask
;
3353 memcpy(tmp
+ page_off
, buf
, size
);
3355 offset
= offset
+ (pagesize
- page_off
);
3357 tg3_enable_nvram_access(tp
);
3360 * Before we can erase the flash page, we need
3361 * to issue a special "write enable" command.
3363 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
3365 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
3368 /* Erase the target page */
3369 tw32(NVRAM_ADDR
, phy_addr
);
3371 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
|
3372 NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
| NVRAM_CMD_ERASE
;
3374 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
3377 /* Issue another write enable to start the write. */
3378 nvram_cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
3380 if (tg3_nvram_exec_cmd(tp
, nvram_cmd
))
3383 for (j
= 0; j
< pagesize
; j
+= 4) {
3386 data
= *((__be32
*) (tmp
+ j
));
3388 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
3390 tw32(NVRAM_ADDR
, phy_addr
+ j
);
3392 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
|
3396 nvram_cmd
|= NVRAM_CMD_FIRST
;
3397 else if (j
== (pagesize
- 4))
3398 nvram_cmd
|= NVRAM_CMD_LAST
;
3400 ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
);
3408 nvram_cmd
= NVRAM_CMD_WRDI
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
3409 tg3_nvram_exec_cmd(tp
, nvram_cmd
);
3416 /* offset and length are dword aligned */
3417 static int tg3_nvram_write_block_buffered(struct tg3
*tp
, u32 offset
, u32 len
,
3422 for (i
= 0; i
< len
; i
+= 4, offset
+= 4) {
3423 u32 page_off
, phy_addr
, nvram_cmd
;
3426 memcpy(&data
, buf
+ i
, 4);
3427 tw32(NVRAM_WRDATA
, be32_to_cpu(data
));
3429 page_off
= offset
% tp
->nvram_pagesize
;
3431 phy_addr
= tg3_nvram_phys_addr(tp
, offset
);
3433 nvram_cmd
= NVRAM_CMD_GO
| NVRAM_CMD_DONE
| NVRAM_CMD_WR
;
3435 if (page_off
== 0 || i
== 0)
3436 nvram_cmd
|= NVRAM_CMD_FIRST
;
3437 if (page_off
== (tp
->nvram_pagesize
- 4))
3438 nvram_cmd
|= NVRAM_CMD_LAST
;
3441 nvram_cmd
|= NVRAM_CMD_LAST
;
3443 if ((nvram_cmd
& NVRAM_CMD_FIRST
) ||
3444 !tg3_flag(tp
, FLASH
) ||
3445 !tg3_flag(tp
, 57765_PLUS
))
3446 tw32(NVRAM_ADDR
, phy_addr
);
3448 if (tg3_asic_rev(tp
) != ASIC_REV_5752
&&
3449 !tg3_flag(tp
, 5755_PLUS
) &&
3450 (tp
->nvram_jedecnum
== JEDEC_ST
) &&
3451 (nvram_cmd
& NVRAM_CMD_FIRST
)) {
3454 cmd
= NVRAM_CMD_WREN
| NVRAM_CMD_GO
| NVRAM_CMD_DONE
;
3455 ret
= tg3_nvram_exec_cmd(tp
, cmd
);
3459 if (!tg3_flag(tp
, FLASH
)) {
3460 /* We always do complete word writes to eeprom. */
3461 nvram_cmd
|= (NVRAM_CMD_FIRST
| NVRAM_CMD_LAST
);
3464 ret
= tg3_nvram_exec_cmd(tp
, nvram_cmd
);
3471 /* offset and length are dword aligned */
3472 static int tg3_nvram_write_block(struct tg3
*tp
, u32 offset
, u32 len
, u8
*buf
)
3476 if (tg3_flag(tp
, EEPROM_WRITE_PROT
)) {
3477 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
&
3478 ~GRC_LCLCTRL_GPIO_OUTPUT1
);
3482 if (!tg3_flag(tp
, NVRAM
)) {
3483 ret
= tg3_nvram_write_block_using_eeprom(tp
, offset
, len
, buf
);
3487 ret
= tg3_nvram_lock(tp
);
3491 tg3_enable_nvram_access(tp
);
3492 if (tg3_flag(tp
, 5750_PLUS
) && !tg3_flag(tp
, PROTECTED_NVRAM
))
3493 tw32(NVRAM_WRITE1
, 0x406);
3495 grc_mode
= tr32(GRC_MODE
);
3496 tw32(GRC_MODE
, grc_mode
| GRC_MODE_NVRAM_WR_ENABLE
);
3498 if (tg3_flag(tp
, NVRAM_BUFFERED
) || !tg3_flag(tp
, FLASH
)) {
3499 ret
= tg3_nvram_write_block_buffered(tp
, offset
, len
,
3502 ret
= tg3_nvram_write_block_unbuffered(tp
, offset
, len
,
3506 grc_mode
= tr32(GRC_MODE
);
3507 tw32(GRC_MODE
, grc_mode
& ~GRC_MODE_NVRAM_WR_ENABLE
);
3509 tg3_disable_nvram_access(tp
);
3510 tg3_nvram_unlock(tp
);
3513 if (tg3_flag(tp
, EEPROM_WRITE_PROT
)) {
3514 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
3521 #define RX_CPU_SCRATCH_BASE 0x30000
3522 #define RX_CPU_SCRATCH_SIZE 0x04000
3523 #define TX_CPU_SCRATCH_BASE 0x34000
3524 #define TX_CPU_SCRATCH_SIZE 0x04000
3526 /* tp->lock is held. */
3527 static int tg3_pause_cpu(struct tg3
*tp
, u32 cpu_base
)
3530 const int iters
= 10000;
3532 for (i
= 0; i
< iters
; i
++) {
3533 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3534 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
3535 if (tr32(cpu_base
+ CPU_MODE
) & CPU_MODE_HALT
)
3539 return (i
== iters
) ? -EBUSY
: 0;
3542 /* tp->lock is held. */
3543 static int tg3_rxcpu_pause(struct tg3
*tp
)
3545 int rc
= tg3_pause_cpu(tp
, RX_CPU_BASE
);
3547 tw32(RX_CPU_BASE
+ CPU_STATE
, 0xffffffff);
3548 tw32_f(RX_CPU_BASE
+ CPU_MODE
, CPU_MODE_HALT
);
3554 /* tp->lock is held. */
3555 static int tg3_txcpu_pause(struct tg3
*tp
)
3557 return tg3_pause_cpu(tp
, TX_CPU_BASE
);
3560 /* tp->lock is held. */
3561 static void tg3_resume_cpu(struct tg3
*tp
, u32 cpu_base
)
3563 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3564 tw32_f(cpu_base
+ CPU_MODE
, 0x00000000);
3567 /* tp->lock is held. */
3568 static void tg3_rxcpu_resume(struct tg3
*tp
)
3570 tg3_resume_cpu(tp
, RX_CPU_BASE
);
3573 /* tp->lock is held. */
3574 static int tg3_halt_cpu(struct tg3
*tp
, u32 cpu_base
)
3578 BUG_ON(cpu_base
== TX_CPU_BASE
&& tg3_flag(tp
, 5705_PLUS
));
3580 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
3581 u32 val
= tr32(GRC_VCPU_EXT_CTRL
);
3583 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_HALT_CPU
);
3586 if (cpu_base
== RX_CPU_BASE
) {
3587 rc
= tg3_rxcpu_pause(tp
);
3590 * There is only an Rx CPU for the 5750 derivative in the
3593 if (tg3_flag(tp
, IS_SSB_CORE
))
3596 rc
= tg3_txcpu_pause(tp
);
3600 netdev_err(tp
->dev
, "%s timed out, %s CPU\n",
3601 __func__
, cpu_base
== RX_CPU_BASE
? "RX" : "TX");
3605 /* Clear firmware's nvram arbitration. */
3606 if (tg3_flag(tp
, NVRAM
))
3607 tw32(NVRAM_SWARB
, SWARB_REQ_CLR0
);
3611 static int tg3_fw_data_len(struct tg3
*tp
,
3612 const struct tg3_firmware_hdr
*fw_hdr
)
3616 /* Non fragmented firmware have one firmware header followed by a
3617 * contiguous chunk of data to be written. The length field in that
3618 * header is not the length of data to be written but the complete
3619 * length of the bss. The data length is determined based on
3620 * tp->fw->size minus headers.
3622 * Fragmented firmware have a main header followed by multiple
3623 * fragments. Each fragment is identical to non fragmented firmware
3624 * with a firmware header followed by a contiguous chunk of data. In
3625 * the main header, the length field is unused and set to 0xffffffff.
3626 * In each fragment header the length is the entire size of that
3627 * fragment i.e. fragment data + header length. Data length is
3628 * therefore length field in the header minus TG3_FW_HDR_LEN.
3630 if (tp
->fw_len
== 0xffffffff)
3631 fw_len
= be32_to_cpu(fw_hdr
->len
);
3633 fw_len
= tp
->fw
->size
;
3635 return (fw_len
- TG3_FW_HDR_LEN
) / sizeof(u32
);
3638 /* tp->lock is held. */
3639 static int tg3_load_firmware_cpu(struct tg3
*tp
, u32 cpu_base
,
3640 u32 cpu_scratch_base
, int cpu_scratch_size
,
3641 const struct tg3_firmware_hdr
*fw_hdr
)
3644 void (*write_op
)(struct tg3
*, u32
, u32
);
3645 int total_len
= tp
->fw
->size
;
3647 if (cpu_base
== TX_CPU_BASE
&& tg3_flag(tp
, 5705_PLUS
)) {
3649 "%s: Trying to load TX cpu firmware which is 5705\n",
3654 if (tg3_flag(tp
, 5705_PLUS
) && tg3_asic_rev(tp
) != ASIC_REV_57766
)
3655 write_op
= tg3_write_mem
;
3657 write_op
= tg3_write_indirect_reg32
;
3659 if (tg3_asic_rev(tp
) != ASIC_REV_57766
) {
3660 /* It is possible that bootcode is still loading at this point.
3661 * Get the nvram lock first before halting the cpu.
3663 int lock_err
= tg3_nvram_lock(tp
);
3664 err
= tg3_halt_cpu(tp
, cpu_base
);
3666 tg3_nvram_unlock(tp
);
3670 for (i
= 0; i
< cpu_scratch_size
; i
+= sizeof(u32
))
3671 write_op(tp
, cpu_scratch_base
+ i
, 0);
3672 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3673 tw32(cpu_base
+ CPU_MODE
,
3674 tr32(cpu_base
+ CPU_MODE
) | CPU_MODE_HALT
);
3676 /* Subtract additional main header for fragmented firmware and
3677 * advance to the first fragment
3679 total_len
-= TG3_FW_HDR_LEN
;
3684 u32
*fw_data
= (u32
*)(fw_hdr
+ 1);
3685 for (i
= 0; i
< tg3_fw_data_len(tp
, fw_hdr
); i
++)
3686 write_op(tp
, cpu_scratch_base
+
3687 (be32_to_cpu(fw_hdr
->base_addr
) & 0xffff) +
3689 be32_to_cpu(fw_data
[i
]));
3691 total_len
-= be32_to_cpu(fw_hdr
->len
);
3693 /* Advance to next fragment */
3694 fw_hdr
= (struct tg3_firmware_hdr
*)
3695 ((void *)fw_hdr
+ be32_to_cpu(fw_hdr
->len
));
3696 } while (total_len
> 0);
3704 /* tp->lock is held. */
3705 static int tg3_pause_cpu_and_set_pc(struct tg3
*tp
, u32 cpu_base
, u32 pc
)
3708 const int iters
= 5;
3710 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3711 tw32_f(cpu_base
+ CPU_PC
, pc
);
3713 for (i
= 0; i
< iters
; i
++) {
3714 if (tr32(cpu_base
+ CPU_PC
) == pc
)
3716 tw32(cpu_base
+ CPU_STATE
, 0xffffffff);
3717 tw32(cpu_base
+ CPU_MODE
, CPU_MODE_HALT
);
3718 tw32_f(cpu_base
+ CPU_PC
, pc
);
3722 return (i
== iters
) ? -EBUSY
: 0;
3725 /* tp->lock is held. */
3726 static int tg3_load_5701_a0_firmware_fix(struct tg3
*tp
)
3728 const struct tg3_firmware_hdr
*fw_hdr
;
3731 fw_hdr
= (struct tg3_firmware_hdr
*)tp
->fw
->data
;
3733 /* Firmware blob starts with version numbers, followed by
3734 start address and length. We are setting complete length.
3735 length = end_address_of_bss - start_address_of_text.
3736 Remainder is the blob to be loaded contiguously
3737 from start address. */
3739 err
= tg3_load_firmware_cpu(tp
, RX_CPU_BASE
,
3740 RX_CPU_SCRATCH_BASE
, RX_CPU_SCRATCH_SIZE
,
3745 err
= tg3_load_firmware_cpu(tp
, TX_CPU_BASE
,
3746 TX_CPU_SCRATCH_BASE
, TX_CPU_SCRATCH_SIZE
,
3751 /* Now startup only the RX cpu. */
3752 err
= tg3_pause_cpu_and_set_pc(tp
, RX_CPU_BASE
,
3753 be32_to_cpu(fw_hdr
->base_addr
));
3755 netdev_err(tp
->dev
, "%s fails to set RX CPU PC, is %08x "
3756 "should be %08x\n", __func__
,
3757 tr32(RX_CPU_BASE
+ CPU_PC
),
3758 be32_to_cpu(fw_hdr
->base_addr
));
3762 tg3_rxcpu_resume(tp
);
3767 static int tg3_validate_rxcpu_state(struct tg3
*tp
)
3769 const int iters
= 1000;
3773 /* Wait for boot code to complete initialization and enter service
3774 * loop. It is then safe to download service patches
3776 for (i
= 0; i
< iters
; i
++) {
3777 if (tr32(RX_CPU_HWBKPT
) == TG3_SBROM_IN_SERVICE_LOOP
)
3784 netdev_err(tp
->dev
, "Boot code not ready for service patches\n");
3788 val
= tg3_read_indirect_reg32(tp
, TG3_57766_FW_HANDSHAKE
);
3790 netdev_warn(tp
->dev
,
3791 "Other patches exist. Not downloading EEE patch\n");
3798 /* tp->lock is held. */
3799 static void tg3_load_57766_firmware(struct tg3
*tp
)
3801 struct tg3_firmware_hdr
*fw_hdr
;
3803 if (!tg3_flag(tp
, NO_NVRAM
))
3806 if (tg3_validate_rxcpu_state(tp
))
3812 /* This firmware blob has a different format than older firmware
3813 * releases as given below. The main difference is we have fragmented
3814 * data to be written to non-contiguous locations.
3816 * In the beginning we have a firmware header identical to other
3817 * firmware which consists of version, base addr and length. The length
3818 * here is unused and set to 0xffffffff.
3820 * This is followed by a series of firmware fragments which are
3821 * individually identical to previous firmware. i.e. they have the
3822 * firmware header and followed by data for that fragment. The version
3823 * field of the individual fragment header is unused.
3826 fw_hdr
= (struct tg3_firmware_hdr
*)tp
->fw
->data
;
3827 if (be32_to_cpu(fw_hdr
->base_addr
) != TG3_57766_FW_BASE_ADDR
)
3830 if (tg3_rxcpu_pause(tp
))
3833 /* tg3_load_firmware_cpu() will always succeed for the 57766 */
3834 tg3_load_firmware_cpu(tp
, 0, TG3_57766_FW_BASE_ADDR
, 0, fw_hdr
);
3836 tg3_rxcpu_resume(tp
);
3839 /* tp->lock is held. */
3840 static int tg3_load_tso_firmware(struct tg3
*tp
)
3842 const struct tg3_firmware_hdr
*fw_hdr
;
3843 unsigned long cpu_base
, cpu_scratch_base
, cpu_scratch_size
;
3846 if (!tg3_flag(tp
, FW_TSO
))
3849 fw_hdr
= (struct tg3_firmware_hdr
*)tp
->fw
->data
;
3851 /* Firmware blob starts with version numbers, followed by
3852 start address and length. We are setting complete length.
3853 length = end_address_of_bss - start_address_of_text.
3854 Remainder is the blob to be loaded contiguously
3855 from start address. */
3857 cpu_scratch_size
= tp
->fw_len
;
3859 if (tg3_asic_rev(tp
) == ASIC_REV_5705
) {
3860 cpu_base
= RX_CPU_BASE
;
3861 cpu_scratch_base
= NIC_SRAM_MBUF_POOL_BASE5705
;
3863 cpu_base
= TX_CPU_BASE
;
3864 cpu_scratch_base
= TX_CPU_SCRATCH_BASE
;
3865 cpu_scratch_size
= TX_CPU_SCRATCH_SIZE
;
3868 err
= tg3_load_firmware_cpu(tp
, cpu_base
,
3869 cpu_scratch_base
, cpu_scratch_size
,
3874 /* Now startup the cpu. */
3875 err
= tg3_pause_cpu_and_set_pc(tp
, cpu_base
,
3876 be32_to_cpu(fw_hdr
->base_addr
));
3879 "%s fails to set CPU PC, is %08x should be %08x\n",
3880 __func__
, tr32(cpu_base
+ CPU_PC
),
3881 be32_to_cpu(fw_hdr
->base_addr
));
3885 tg3_resume_cpu(tp
, cpu_base
);
3890 /* tp->lock is held. */
3891 static void __tg3_set_mac_addr(struct tg3
*tp
, bool skip_mac_1
)
3893 u32 addr_high
, addr_low
;
3896 addr_high
= ((tp
->dev
->dev_addr
[0] << 8) |
3897 tp
->dev
->dev_addr
[1]);
3898 addr_low
= ((tp
->dev
->dev_addr
[2] << 24) |
3899 (tp
->dev
->dev_addr
[3] << 16) |
3900 (tp
->dev
->dev_addr
[4] << 8) |
3901 (tp
->dev
->dev_addr
[5] << 0));
3902 for (i
= 0; i
< 4; i
++) {
3903 if (i
== 1 && skip_mac_1
)
3905 tw32(MAC_ADDR_0_HIGH
+ (i
* 8), addr_high
);
3906 tw32(MAC_ADDR_0_LOW
+ (i
* 8), addr_low
);
3909 if (tg3_asic_rev(tp
) == ASIC_REV_5703
||
3910 tg3_asic_rev(tp
) == ASIC_REV_5704
) {
3911 for (i
= 0; i
< 12; i
++) {
3912 tw32(MAC_EXTADDR_0_HIGH
+ (i
* 8), addr_high
);
3913 tw32(MAC_EXTADDR_0_LOW
+ (i
* 8), addr_low
);
3917 addr_high
= (tp
->dev
->dev_addr
[0] +
3918 tp
->dev
->dev_addr
[1] +
3919 tp
->dev
->dev_addr
[2] +
3920 tp
->dev
->dev_addr
[3] +
3921 tp
->dev
->dev_addr
[4] +
3922 tp
->dev
->dev_addr
[5]) &
3923 TX_BACKOFF_SEED_MASK
;
3924 tw32(MAC_TX_BACKOFF_SEED
, addr_high
);
3927 static void tg3_enable_register_access(struct tg3
*tp
)
3930 * Make sure register accesses (indirect or otherwise) will function
3933 pci_write_config_dword(tp
->pdev
,
3934 TG3PCI_MISC_HOST_CTRL
, tp
->misc_host_ctrl
);
3937 static int tg3_power_up(struct tg3
*tp
)
3941 tg3_enable_register_access(tp
);
3943 err
= pci_set_power_state(tp
->pdev
, PCI_D0
);
3945 /* Switch out of Vaux if it is a NIC */
3946 tg3_pwrsrc_switch_to_vmain(tp
);
3948 netdev_err(tp
->dev
, "Transition to D0 failed\n");
3954 static int tg3_setup_phy(struct tg3
*, bool);
3956 static int tg3_power_down_prepare(struct tg3
*tp
)
3959 bool device_should_wake
, do_low_power
;
3961 tg3_enable_register_access(tp
);
3963 /* Restore the CLKREQ setting. */
3964 if (tg3_flag(tp
, CLKREQ_BUG
))
3965 pcie_capability_set_word(tp
->pdev
, PCI_EXP_LNKCTL
,
3966 PCI_EXP_LNKCTL_CLKREQ_EN
);
3968 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
3969 tw32(TG3PCI_MISC_HOST_CTRL
,
3970 misc_host_ctrl
| MISC_HOST_CTRL_MASK_PCI_INT
);
3972 device_should_wake
= device_may_wakeup(&tp
->pdev
->dev
) &&
3973 tg3_flag(tp
, WOL_ENABLE
);
3975 if (tg3_flag(tp
, USE_PHYLIB
)) {
3976 do_low_power
= false;
3977 if ((tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) &&
3978 !(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
3979 struct phy_device
*phydev
;
3980 u32 phyid
, advertising
;
3982 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
3984 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
3986 tp
->link_config
.speed
= phydev
->speed
;
3987 tp
->link_config
.duplex
= phydev
->duplex
;
3988 tp
->link_config
.autoneg
= phydev
->autoneg
;
3989 tp
->link_config
.advertising
= phydev
->advertising
;
3991 advertising
= ADVERTISED_TP
|
3993 ADVERTISED_Autoneg
|
3994 ADVERTISED_10baseT_Half
;
3996 if (tg3_flag(tp
, ENABLE_ASF
) || device_should_wake
) {
3997 if (tg3_flag(tp
, WOL_SPEED_100MB
))
3999 ADVERTISED_100baseT_Half
|
4000 ADVERTISED_100baseT_Full
|
4001 ADVERTISED_10baseT_Full
;
4003 advertising
|= ADVERTISED_10baseT_Full
;
4006 phydev
->advertising
= advertising
;
4008 phy_start_aneg(phydev
);
4010 phyid
= phydev
->drv
->phy_id
& phydev
->drv
->phy_id_mask
;
4011 if (phyid
!= PHY_ID_BCMAC131
) {
4012 phyid
&= PHY_BCM_OUI_MASK
;
4013 if (phyid
== PHY_BCM_OUI_1
||
4014 phyid
== PHY_BCM_OUI_2
||
4015 phyid
== PHY_BCM_OUI_3
)
4016 do_low_power
= true;
4020 do_low_power
= true;
4022 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
))
4023 tp
->phy_flags
|= TG3_PHYFLG_IS_LOW_POWER
;
4025 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
4026 tg3_setup_phy(tp
, false);
4029 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
4032 val
= tr32(GRC_VCPU_EXT_CTRL
);
4033 tw32(GRC_VCPU_EXT_CTRL
, val
| GRC_VCPU_EXT_CTRL_DISABLE_WOL
);
4034 } else if (!tg3_flag(tp
, ENABLE_ASF
)) {
4038 for (i
= 0; i
< 200; i
++) {
4039 tg3_read_mem(tp
, NIC_SRAM_FW_ASF_STATUS_MBOX
, &val
);
4040 if (val
== ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1
)
4045 if (tg3_flag(tp
, WOL_CAP
))
4046 tg3_write_mem(tp
, NIC_SRAM_WOL_MBOX
, WOL_SIGNATURE
|
4047 WOL_DRV_STATE_SHUTDOWN
|
4051 if (device_should_wake
) {
4054 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
4056 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
4057 tg3_phy_auxctl_write(tp
,
4058 MII_TG3_AUXCTL_SHDWSEL_PWRCTL
,
4059 MII_TG3_AUXCTL_PCTL_WOL_EN
|
4060 MII_TG3_AUXCTL_PCTL_100TX_LPWR
|
4061 MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC
);
4065 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
4066 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
4067 else if (tp
->phy_flags
&
4068 TG3_PHYFLG_KEEP_LINK_ON_PWRDN
) {
4069 if (tp
->link_config
.active_speed
== SPEED_1000
)
4070 mac_mode
= MAC_MODE_PORT_MODE_GMII
;
4072 mac_mode
= MAC_MODE_PORT_MODE_MII
;
4074 mac_mode
= MAC_MODE_PORT_MODE_MII
;
4076 mac_mode
|= tp
->mac_mode
& MAC_MODE_LINK_POLARITY
;
4077 if (tg3_asic_rev(tp
) == ASIC_REV_5700
) {
4078 u32 speed
= tg3_flag(tp
, WOL_SPEED_100MB
) ?
4079 SPEED_100
: SPEED_10
;
4080 if (tg3_5700_link_polarity(tp
, speed
))
4081 mac_mode
|= MAC_MODE_LINK_POLARITY
;
4083 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
4086 mac_mode
= MAC_MODE_PORT_MODE_TBI
;
4089 if (!tg3_flag(tp
, 5750_PLUS
))
4090 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
4092 mac_mode
|= MAC_MODE_MAGIC_PKT_ENABLE
;
4093 if ((tg3_flag(tp
, 5705_PLUS
) && !tg3_flag(tp
, 5780_CLASS
)) &&
4094 (tg3_flag(tp
, ENABLE_ASF
) || tg3_flag(tp
, ENABLE_APE
)))
4095 mac_mode
|= MAC_MODE_KEEP_FRAME_IN_WOL
;
4097 if (tg3_flag(tp
, ENABLE_APE
))
4098 mac_mode
|= MAC_MODE_APE_TX_EN
|
4099 MAC_MODE_APE_RX_EN
|
4100 MAC_MODE_TDE_ENABLE
;
4102 tw32_f(MAC_MODE
, mac_mode
);
4105 tw32_f(MAC_RX_MODE
, RX_MODE_ENABLE
);
4109 if (!tg3_flag(tp
, WOL_SPEED_100MB
) &&
4110 (tg3_asic_rev(tp
) == ASIC_REV_5700
||
4111 tg3_asic_rev(tp
) == ASIC_REV_5701
)) {
4114 base_val
= tp
->pci_clock_ctrl
;
4115 base_val
|= (CLOCK_CTRL_RXCLK_DISABLE
|
4116 CLOCK_CTRL_TXCLK_DISABLE
);
4118 tw32_wait_f(TG3PCI_CLOCK_CTRL
, base_val
| CLOCK_CTRL_ALTCLK
|
4119 CLOCK_CTRL_PWRDOWN_PLL133
, 40);
4120 } else if (tg3_flag(tp
, 5780_CLASS
) ||
4121 tg3_flag(tp
, CPMU_PRESENT
) ||
4122 tg3_asic_rev(tp
) == ASIC_REV_5906
) {
4124 } else if (!(tg3_flag(tp
, 5750_PLUS
) && tg3_flag(tp
, ENABLE_ASF
))) {
4125 u32 newbits1
, newbits2
;
4127 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
4128 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
4129 newbits1
= (CLOCK_CTRL_RXCLK_DISABLE
|
4130 CLOCK_CTRL_TXCLK_DISABLE
|
4132 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
4133 } else if (tg3_flag(tp
, 5705_PLUS
)) {
4134 newbits1
= CLOCK_CTRL_625_CORE
;
4135 newbits2
= newbits1
| CLOCK_CTRL_ALTCLK
;
4137 newbits1
= CLOCK_CTRL_ALTCLK
;
4138 newbits2
= newbits1
| CLOCK_CTRL_44MHZ_CORE
;
4141 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits1
,
4144 tw32_wait_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
| newbits2
,
4147 if (!tg3_flag(tp
, 5705_PLUS
)) {
4150 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
4151 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
4152 newbits3
= (CLOCK_CTRL_RXCLK_DISABLE
|
4153 CLOCK_CTRL_TXCLK_DISABLE
|
4154 CLOCK_CTRL_44MHZ_CORE
);
4156 newbits3
= CLOCK_CTRL_44MHZ_CORE
;
4159 tw32_wait_f(TG3PCI_CLOCK_CTRL
,
4160 tp
->pci_clock_ctrl
| newbits3
, 40);
4164 if (!(device_should_wake
) && !tg3_flag(tp
, ENABLE_ASF
))
4165 tg3_power_down_phy(tp
, do_low_power
);
4167 tg3_frob_aux_power(tp
, true);
4169 /* Workaround for unstable PLL clock */
4170 if ((!tg3_flag(tp
, IS_SSB_CORE
)) &&
4171 ((tg3_chip_rev(tp
) == CHIPREV_5750_AX
) ||
4172 (tg3_chip_rev(tp
) == CHIPREV_5750_BX
))) {
4173 u32 val
= tr32(0x7d00);
4175 val
&= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
4177 if (!tg3_flag(tp
, ENABLE_ASF
)) {
4180 err
= tg3_nvram_lock(tp
);
4181 tg3_halt_cpu(tp
, RX_CPU_BASE
);
4183 tg3_nvram_unlock(tp
);
4187 tg3_write_sig_post_reset(tp
, RESET_KIND_SHUTDOWN
);
4192 static void tg3_power_down(struct tg3
*tp
)
4194 tg3_power_down_prepare(tp
);
4196 pci_wake_from_d3(tp
->pdev
, tg3_flag(tp
, WOL_ENABLE
));
4197 pci_set_power_state(tp
->pdev
, PCI_D3hot
);
4200 static void tg3_aux_stat_to_speed_duplex(struct tg3
*tp
, u32 val
, u16
*speed
, u8
*duplex
)
4202 switch (val
& MII_TG3_AUX_STAT_SPDMASK
) {
4203 case MII_TG3_AUX_STAT_10HALF
:
4205 *duplex
= DUPLEX_HALF
;
4208 case MII_TG3_AUX_STAT_10FULL
:
4210 *duplex
= DUPLEX_FULL
;
4213 case MII_TG3_AUX_STAT_100HALF
:
4215 *duplex
= DUPLEX_HALF
;
4218 case MII_TG3_AUX_STAT_100FULL
:
4220 *duplex
= DUPLEX_FULL
;
4223 case MII_TG3_AUX_STAT_1000HALF
:
4224 *speed
= SPEED_1000
;
4225 *duplex
= DUPLEX_HALF
;
4228 case MII_TG3_AUX_STAT_1000FULL
:
4229 *speed
= SPEED_1000
;
4230 *duplex
= DUPLEX_FULL
;
4234 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
4235 *speed
= (val
& MII_TG3_AUX_STAT_100
) ? SPEED_100
:
4237 *duplex
= (val
& MII_TG3_AUX_STAT_FULL
) ? DUPLEX_FULL
:
4241 *speed
= SPEED_UNKNOWN
;
4242 *duplex
= DUPLEX_UNKNOWN
;
4247 static int tg3_phy_autoneg_cfg(struct tg3
*tp
, u32 advertise
, u32 flowctrl
)
4252 new_adv
= ADVERTISE_CSMA
;
4253 new_adv
|= ethtool_adv_to_mii_adv_t(advertise
) & ADVERTISE_ALL
;
4254 new_adv
|= mii_advertise_flowctrl(flowctrl
);
4256 err
= tg3_writephy(tp
, MII_ADVERTISE
, new_adv
);
4260 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4261 new_adv
= ethtool_adv_to_mii_ctrl1000_t(advertise
);
4263 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
4264 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
)
4265 new_adv
|= CTL1000_AS_MASTER
| CTL1000_ENABLE_MASTER
;
4267 err
= tg3_writephy(tp
, MII_CTRL1000
, new_adv
);
4272 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
4275 tw32(TG3_CPMU_EEE_MODE
,
4276 tr32(TG3_CPMU_EEE_MODE
) & ~TG3_CPMU_EEEMD_LPI_ENABLE
);
4278 err
= tg3_phy_toggle_auxctl_smdsp(tp
, true);
4283 /* Advertise 100-BaseTX EEE ability */
4284 if (advertise
& ADVERTISED_100baseT_Full
)
4285 val
|= MDIO_AN_EEE_ADV_100TX
;
4286 /* Advertise 1000-BaseT EEE ability */
4287 if (advertise
& ADVERTISED_1000baseT_Full
)
4288 val
|= MDIO_AN_EEE_ADV_1000T
;
4290 if (!tp
->eee
.eee_enabled
) {
4292 tp
->eee
.advertised
= 0;
4294 tp
->eee
.advertised
= advertise
&
4295 (ADVERTISED_100baseT_Full
|
4296 ADVERTISED_1000baseT_Full
);
4299 err
= tg3_phy_cl45_write(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, val
);
4303 switch (tg3_asic_rev(tp
)) {
4305 case ASIC_REV_57765
:
4306 case ASIC_REV_57766
:
4308 /* If we advertised any eee advertisements above... */
4310 val
= MII_TG3_DSP_TAP26_ALNOKO
|
4311 MII_TG3_DSP_TAP26_RMRXSTO
|
4312 MII_TG3_DSP_TAP26_OPCSINPT
;
4313 tg3_phydsp_write(tp
, MII_TG3_DSP_TAP26
, val
);
4317 if (!tg3_phydsp_read(tp
, MII_TG3_DSP_CH34TP2
, &val
))
4318 tg3_phydsp_write(tp
, MII_TG3_DSP_CH34TP2
, val
|
4319 MII_TG3_DSP_CH34TP2_HIBW01
);
4322 err2
= tg3_phy_toggle_auxctl_smdsp(tp
, false);
4331 static void tg3_phy_copper_begin(struct tg3
*tp
)
4333 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
||
4334 (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
4337 if ((tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) &&
4338 !(tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
)) {
4339 adv
= ADVERTISED_10baseT_Half
|
4340 ADVERTISED_10baseT_Full
;
4341 if (tg3_flag(tp
, WOL_SPEED_100MB
))
4342 adv
|= ADVERTISED_100baseT_Half
|
4343 ADVERTISED_100baseT_Full
;
4344 if (tp
->phy_flags
& TG3_PHYFLG_1G_ON_VAUX_OK
)
4345 adv
|= ADVERTISED_1000baseT_Half
|
4346 ADVERTISED_1000baseT_Full
;
4348 fc
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
4350 adv
= tp
->link_config
.advertising
;
4351 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
4352 adv
&= ~(ADVERTISED_1000baseT_Half
|
4353 ADVERTISED_1000baseT_Full
);
4355 fc
= tp
->link_config
.flowctrl
;
4358 tg3_phy_autoneg_cfg(tp
, adv
, fc
);
4360 if ((tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) &&
4361 (tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
)) {
4362 /* Normally during power down we want to autonegotiate
4363 * the lowest possible speed for WOL. However, to avoid
4364 * link flap, we leave it untouched.
4369 tg3_writephy(tp
, MII_BMCR
,
4370 BMCR_ANENABLE
| BMCR_ANRESTART
);
4373 u32 bmcr
, orig_bmcr
;
4375 tp
->link_config
.active_speed
= tp
->link_config
.speed
;
4376 tp
->link_config
.active_duplex
= tp
->link_config
.duplex
;
4378 if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
4379 /* With autoneg disabled, 5715 only links up when the
4380 * advertisement register has the configured speed
4383 tg3_writephy(tp
, MII_ADVERTISE
, ADVERTISE_ALL
);
4387 switch (tp
->link_config
.speed
) {
4393 bmcr
|= BMCR_SPEED100
;
4397 bmcr
|= BMCR_SPEED1000
;
4401 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
4402 bmcr
|= BMCR_FULLDPLX
;
4404 if (!tg3_readphy(tp
, MII_BMCR
, &orig_bmcr
) &&
4405 (bmcr
!= orig_bmcr
)) {
4406 tg3_writephy(tp
, MII_BMCR
, BMCR_LOOPBACK
);
4407 for (i
= 0; i
< 1500; i
++) {
4411 if (tg3_readphy(tp
, MII_BMSR
, &tmp
) ||
4412 tg3_readphy(tp
, MII_BMSR
, &tmp
))
4414 if (!(tmp
& BMSR_LSTATUS
)) {
4419 tg3_writephy(tp
, MII_BMCR
, bmcr
);
4425 static int tg3_phy_pull_config(struct tg3
*tp
)
4430 err
= tg3_readphy(tp
, MII_BMCR
, &val
);
4434 if (!(val
& BMCR_ANENABLE
)) {
4435 tp
->link_config
.autoneg
= AUTONEG_DISABLE
;
4436 tp
->link_config
.advertising
= 0;
4437 tg3_flag_clear(tp
, PAUSE_AUTONEG
);
4441 switch (val
& (BMCR_SPEED1000
| BMCR_SPEED100
)) {
4443 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
4446 tp
->link_config
.speed
= SPEED_10
;
4449 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
4452 tp
->link_config
.speed
= SPEED_100
;
4454 case BMCR_SPEED1000
:
4455 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4456 tp
->link_config
.speed
= SPEED_1000
;
4464 if (val
& BMCR_FULLDPLX
)
4465 tp
->link_config
.duplex
= DUPLEX_FULL
;
4467 tp
->link_config
.duplex
= DUPLEX_HALF
;
4469 tp
->link_config
.flowctrl
= FLOW_CTRL_RX
| FLOW_CTRL_TX
;
4475 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
4476 tp
->link_config
.advertising
= ADVERTISED_Autoneg
;
4477 tg3_flag_set(tp
, PAUSE_AUTONEG
);
4479 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
4482 err
= tg3_readphy(tp
, MII_ADVERTISE
, &val
);
4486 adv
= mii_adv_to_ethtool_adv_t(val
& ADVERTISE_ALL
);
4487 tp
->link_config
.advertising
|= adv
| ADVERTISED_TP
;
4489 tp
->link_config
.flowctrl
= tg3_decode_flowctrl_1000T(val
);
4491 tp
->link_config
.advertising
|= ADVERTISED_FIBRE
;
4494 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4497 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
4498 err
= tg3_readphy(tp
, MII_CTRL1000
, &val
);
4502 adv
= mii_ctrl1000_to_ethtool_adv_t(val
);
4504 err
= tg3_readphy(tp
, MII_ADVERTISE
, &val
);
4508 adv
= tg3_decode_flowctrl_1000X(val
);
4509 tp
->link_config
.flowctrl
= adv
;
4511 val
&= (ADVERTISE_1000XHALF
| ADVERTISE_1000XFULL
);
4512 adv
= mii_adv_to_ethtool_adv_x(val
);
4515 tp
->link_config
.advertising
|= adv
;
4522 static int tg3_init_5401phy_dsp(struct tg3
*tp
)
4526 /* Turn off tap power management. */
4527 /* Set Extended packet length bit */
4528 err
= tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_AUXCTL
, 0x4c20);
4530 err
|= tg3_phydsp_write(tp
, 0x0012, 0x1804);
4531 err
|= tg3_phydsp_write(tp
, 0x0013, 0x1204);
4532 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0132);
4533 err
|= tg3_phydsp_write(tp
, 0x8006, 0x0232);
4534 err
|= tg3_phydsp_write(tp
, 0x201f, 0x0a20);
4541 static bool tg3_phy_eee_config_ok(struct tg3
*tp
)
4545 u32 advertising
= tp
->link_config
.advertising
;
4547 if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
))
4550 if (tg3_phy_cl45_read(tp
, MDIO_MMD_AN
, MDIO_AN_EEE_ADV
, &val
))
4553 val
&= (MDIO_AN_EEE_ADV_100TX
| MDIO_AN_EEE_ADV_1000T
);
4556 if (advertising
& ADVERTISED_100baseT_Full
)
4557 tgtadv
|= MDIO_AN_EEE_ADV_100TX
;
4558 if (advertising
& ADVERTISED_1000baseT_Full
)
4559 tgtadv
|= MDIO_AN_EEE_ADV_1000T
;
4567 static bool tg3_phy_copper_an_config_ok(struct tg3
*tp
, u32
*lcladv
)
4569 u32 advmsk
, tgtadv
, advertising
;
4571 advertising
= tp
->link_config
.advertising
;
4572 tgtadv
= ethtool_adv_to_mii_adv_t(advertising
) & ADVERTISE_ALL
;
4574 advmsk
= ADVERTISE_ALL
;
4575 if (tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
4576 tgtadv
|= mii_advertise_flowctrl(tp
->link_config
.flowctrl
);
4577 advmsk
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
4580 if (tg3_readphy(tp
, MII_ADVERTISE
, lcladv
))
4583 if ((*lcladv
& advmsk
) != tgtadv
)
4586 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4589 tgtadv
= ethtool_adv_to_mii_ctrl1000_t(advertising
);
4591 if (tg3_readphy(tp
, MII_CTRL1000
, &tg3_ctrl
))
4595 (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
4596 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
)) {
4597 tgtadv
|= CTL1000_AS_MASTER
| CTL1000_ENABLE_MASTER
;
4598 tg3_ctrl
&= (ADVERTISE_1000HALF
| ADVERTISE_1000FULL
|
4599 CTL1000_AS_MASTER
| CTL1000_ENABLE_MASTER
);
4601 tg3_ctrl
&= (ADVERTISE_1000HALF
| ADVERTISE_1000FULL
);
4604 if (tg3_ctrl
!= tgtadv
)
4611 static bool tg3_phy_copper_fetch_rmtadv(struct tg3
*tp
, u32
*rmtadv
)
4615 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)) {
4618 if (tg3_readphy(tp
, MII_STAT1000
, &val
))
4621 lpeth
= mii_stat1000_to_ethtool_lpa_t(val
);
4624 if (tg3_readphy(tp
, MII_LPA
, rmtadv
))
4627 lpeth
|= mii_lpa_to_ethtool_lpa_t(*rmtadv
);
4628 tp
->link_config
.rmt_adv
= lpeth
;
4633 static bool tg3_test_and_report_link_chg(struct tg3
*tp
, bool curr_link_up
)
4635 if (curr_link_up
!= tp
->link_up
) {
4637 netif_carrier_on(tp
->dev
);
4639 netif_carrier_off(tp
->dev
);
4640 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
4641 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
4644 tg3_link_report(tp
);
4651 static void tg3_clear_mac_status(struct tg3
*tp
)
4656 MAC_STATUS_SYNC_CHANGED
|
4657 MAC_STATUS_CFG_CHANGED
|
4658 MAC_STATUS_MI_COMPLETION
|
4659 MAC_STATUS_LNKSTATE_CHANGED
);
4663 static void tg3_setup_eee(struct tg3
*tp
)
4667 val
= TG3_CPMU_EEE_LNKIDL_PCIE_NL0
|
4668 TG3_CPMU_EEE_LNKIDL_UART_IDL
;
4669 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_57765_A0
)
4670 val
|= TG3_CPMU_EEE_LNKIDL_APE_TX_MT
;
4672 tw32_f(TG3_CPMU_EEE_LNKIDL_CTRL
, val
);
4674 tw32_f(TG3_CPMU_EEE_CTRL
,
4675 TG3_CPMU_EEE_CTRL_EXIT_20_1_US
);
4677 val
= TG3_CPMU_EEEMD_ERLY_L1_XIT_DET
|
4678 (tp
->eee
.tx_lpi_enabled
? TG3_CPMU_EEEMD_LPI_IN_TX
: 0) |
4679 TG3_CPMU_EEEMD_LPI_IN_RX
|
4680 TG3_CPMU_EEEMD_EEE_ENABLE
;
4682 if (tg3_asic_rev(tp
) != ASIC_REV_5717
)
4683 val
|= TG3_CPMU_EEEMD_SND_IDX_DET_EN
;
4685 if (tg3_flag(tp
, ENABLE_APE
))
4686 val
|= TG3_CPMU_EEEMD_APE_TX_DET_EN
;
4688 tw32_f(TG3_CPMU_EEE_MODE
, tp
->eee
.eee_enabled
? val
: 0);
4690 tw32_f(TG3_CPMU_EEE_DBTMR1
,
4691 TG3_CPMU_DBTMR1_PCIEXIT_2047US
|
4692 (tp
->eee
.tx_lpi_timer
& 0xffff));
4694 tw32_f(TG3_CPMU_EEE_DBTMR2
,
4695 TG3_CPMU_DBTMR2_APE_TX_2047US
|
4696 TG3_CPMU_DBTMR2_TXIDXEQ_2047US
);
4699 static int tg3_setup_copper_phy(struct tg3
*tp
, bool force_reset
)
4701 bool current_link_up
;
4703 u32 lcl_adv
, rmt_adv
;
4708 tg3_clear_mac_status(tp
);
4710 if ((tp
->mi_mode
& MAC_MI_MODE_AUTO_POLL
) != 0) {
4712 (tp
->mi_mode
& ~MAC_MI_MODE_AUTO_POLL
));
4716 tg3_phy_auxctl_write(tp
, MII_TG3_AUXCTL_SHDWSEL_PWRCTL
, 0);
4718 /* Some third-party PHYs need to be reset on link going
4721 if ((tg3_asic_rev(tp
) == ASIC_REV_5703
||
4722 tg3_asic_rev(tp
) == ASIC_REV_5704
||
4723 tg3_asic_rev(tp
) == ASIC_REV_5705
) &&
4725 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4726 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
4727 !(bmsr
& BMSR_LSTATUS
))
4733 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
4734 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4735 if (tg3_readphy(tp
, MII_BMSR
, &bmsr
) ||
4736 !tg3_flag(tp
, INIT_COMPLETE
))
4739 if (!(bmsr
& BMSR_LSTATUS
)) {
4740 err
= tg3_init_5401phy_dsp(tp
);
4744 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4745 for (i
= 0; i
< 1000; i
++) {
4747 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
4748 (bmsr
& BMSR_LSTATUS
)) {
4754 if ((tp
->phy_id
& TG3_PHY_ID_REV_MASK
) ==
4755 TG3_PHY_REV_BCM5401_B0
&&
4756 !(bmsr
& BMSR_LSTATUS
) &&
4757 tp
->link_config
.active_speed
== SPEED_1000
) {
4758 err
= tg3_phy_reset(tp
);
4760 err
= tg3_init_5401phy_dsp(tp
);
4765 } else if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
4766 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
) {
4767 /* 5701 {A0,B0} CRC bug workaround */
4768 tg3_writephy(tp
, 0x15, 0x0a75);
4769 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
4770 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8d68);
4771 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x8c68);
4774 /* Clear pending interrupts... */
4775 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
4776 tg3_readphy(tp
, MII_TG3_ISTAT
, &val
);
4778 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
)
4779 tg3_writephy(tp
, MII_TG3_IMASK
, ~MII_TG3_INT_LINKCHG
);
4780 else if (!(tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
4781 tg3_writephy(tp
, MII_TG3_IMASK
, ~0);
4783 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
4784 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
4785 if (tp
->led_ctrl
== LED_CTRL_MODE_PHY_1
)
4786 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
4787 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
4789 tg3_writephy(tp
, MII_TG3_EXT_CTRL
, 0);
4792 current_link_up
= false;
4793 current_speed
= SPEED_UNKNOWN
;
4794 current_duplex
= DUPLEX_UNKNOWN
;
4795 tp
->phy_flags
&= ~TG3_PHYFLG_MDIX_STATE
;
4796 tp
->link_config
.rmt_adv
= 0;
4798 if (tp
->phy_flags
& TG3_PHYFLG_CAPACITIVE_COUPLING
) {
4799 err
= tg3_phy_auxctl_read(tp
,
4800 MII_TG3_AUXCTL_SHDWSEL_MISCTEST
,
4802 if (!err
&& !(val
& (1 << 10))) {
4803 tg3_phy_auxctl_write(tp
,
4804 MII_TG3_AUXCTL_SHDWSEL_MISCTEST
,
4811 for (i
= 0; i
< 100; i
++) {
4812 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4813 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
4814 (bmsr
& BMSR_LSTATUS
))
4819 if (bmsr
& BMSR_LSTATUS
) {
4822 tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
);
4823 for (i
= 0; i
< 2000; i
++) {
4825 if (!tg3_readphy(tp
, MII_TG3_AUX_STAT
, &aux_stat
) &&
4830 tg3_aux_stat_to_speed_duplex(tp
, aux_stat
,
4835 for (i
= 0; i
< 200; i
++) {
4836 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
4837 if (tg3_readphy(tp
, MII_BMCR
, &bmcr
))
4839 if (bmcr
&& bmcr
!= 0x7fff)
4847 tp
->link_config
.active_speed
= current_speed
;
4848 tp
->link_config
.active_duplex
= current_duplex
;
4850 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
4851 bool eee_config_ok
= tg3_phy_eee_config_ok(tp
);
4853 if ((bmcr
& BMCR_ANENABLE
) &&
4855 tg3_phy_copper_an_config_ok(tp
, &lcl_adv
) &&
4856 tg3_phy_copper_fetch_rmtadv(tp
, &rmt_adv
))
4857 current_link_up
= true;
4859 /* EEE settings changes take effect only after a phy
4860 * reset. If we have skipped a reset due to Link Flap
4861 * Avoidance being enabled, do it now.
4863 if (!eee_config_ok
&&
4864 (tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
) &&
4868 if (!(bmcr
& BMCR_ANENABLE
) &&
4869 tp
->link_config
.speed
== current_speed
&&
4870 tp
->link_config
.duplex
== current_duplex
) {
4871 current_link_up
= true;
4875 if (current_link_up
&&
4876 tp
->link_config
.active_duplex
== DUPLEX_FULL
) {
4879 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
4880 reg
= MII_TG3_FET_GEN_STAT
;
4881 bit
= MII_TG3_FET_GEN_STAT_MDIXSTAT
;
4883 reg
= MII_TG3_EXT_STAT
;
4884 bit
= MII_TG3_EXT_STAT_MDIX
;
4887 if (!tg3_readphy(tp
, reg
, &val
) && (val
& bit
))
4888 tp
->phy_flags
|= TG3_PHYFLG_MDIX_STATE
;
4890 tg3_setup_flow_control(tp
, lcl_adv
, rmt_adv
);
4895 if (!current_link_up
|| (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)) {
4896 tg3_phy_copper_begin(tp
);
4898 if (tg3_flag(tp
, ROBOSWITCH
)) {
4899 current_link_up
= true;
4900 /* FIXME: when BCM5325 switch is used use 100 MBit/s */
4901 current_speed
= SPEED_1000
;
4902 current_duplex
= DUPLEX_FULL
;
4903 tp
->link_config
.active_speed
= current_speed
;
4904 tp
->link_config
.active_duplex
= current_duplex
;
4907 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
4908 if ((!tg3_readphy(tp
, MII_BMSR
, &bmsr
) && (bmsr
& BMSR_LSTATUS
)) ||
4909 (tp
->mac_mode
& MAC_MODE_PORT_INT_LPBACK
))
4910 current_link_up
= true;
4913 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
4914 if (current_link_up
) {
4915 if (tp
->link_config
.active_speed
== SPEED_100
||
4916 tp
->link_config
.active_speed
== SPEED_10
)
4917 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
4919 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4920 } else if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
4921 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
4923 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
4925 /* In order for the 5750 core in BCM4785 chip to work properly
4926 * in RGMII mode, the Led Control Register must be set up.
4928 if (tg3_flag(tp
, RGMII_MODE
)) {
4929 u32 led_ctrl
= tr32(MAC_LED_CTRL
);
4930 led_ctrl
&= ~(LED_CTRL_1000MBPS_ON
| LED_CTRL_100MBPS_ON
);
4932 if (tp
->link_config
.active_speed
== SPEED_10
)
4933 led_ctrl
|= LED_CTRL_LNKLED_OVERRIDE
;
4934 else if (tp
->link_config
.active_speed
== SPEED_100
)
4935 led_ctrl
|= (LED_CTRL_LNKLED_OVERRIDE
|
4936 LED_CTRL_100MBPS_ON
);
4937 else if (tp
->link_config
.active_speed
== SPEED_1000
)
4938 led_ctrl
|= (LED_CTRL_LNKLED_OVERRIDE
|
4939 LED_CTRL_1000MBPS_ON
);
4941 tw32(MAC_LED_CTRL
, led_ctrl
);
4945 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
4946 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
4947 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
4949 if (tg3_asic_rev(tp
) == ASIC_REV_5700
) {
4950 if (current_link_up
&&
4951 tg3_5700_link_polarity(tp
, tp
->link_config
.active_speed
))
4952 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
4954 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
4957 /* ??? Without this setting Netgear GA302T PHY does not
4958 * ??? send/receive packets...
4960 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5411
&&
4961 tg3_chip_rev_id(tp
) == CHIPREV_ID_5700_ALTIMA
) {
4962 tp
->mi_mode
|= MAC_MI_MODE_AUTO_POLL
;
4963 tw32_f(MAC_MI_MODE
, tp
->mi_mode
);
4967 tw32_f(MAC_MODE
, tp
->mac_mode
);
4970 tg3_phy_eee_adjust(tp
, current_link_up
);
4972 if (tg3_flag(tp
, USE_LINKCHG_REG
)) {
4973 /* Polled via timer. */
4974 tw32_f(MAC_EVENT
, 0);
4976 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
4980 if (tg3_asic_rev(tp
) == ASIC_REV_5700
&&
4982 tp
->link_config
.active_speed
== SPEED_1000
&&
4983 (tg3_flag(tp
, PCIX_MODE
) || tg3_flag(tp
, PCI_HIGH_SPEED
))) {
4986 (MAC_STATUS_SYNC_CHANGED
|
4987 MAC_STATUS_CFG_CHANGED
));
4990 NIC_SRAM_FIRMWARE_MBOX
,
4991 NIC_SRAM_FIRMWARE_MBOX_MAGIC2
);
4994 /* Prevent send BD corruption. */
4995 if (tg3_flag(tp
, CLKREQ_BUG
)) {
4996 if (tp
->link_config
.active_speed
== SPEED_100
||
4997 tp
->link_config
.active_speed
== SPEED_10
)
4998 pcie_capability_clear_word(tp
->pdev
, PCI_EXP_LNKCTL
,
4999 PCI_EXP_LNKCTL_CLKREQ_EN
);
5001 pcie_capability_set_word(tp
->pdev
, PCI_EXP_LNKCTL
,
5002 PCI_EXP_LNKCTL_CLKREQ_EN
);
5005 tg3_test_and_report_link_chg(tp
, current_link_up
);
5010 struct tg3_fiber_aneginfo
{
5012 #define ANEG_STATE_UNKNOWN 0
5013 #define ANEG_STATE_AN_ENABLE 1
5014 #define ANEG_STATE_RESTART_INIT 2
5015 #define ANEG_STATE_RESTART 3
5016 #define ANEG_STATE_DISABLE_LINK_OK 4
5017 #define ANEG_STATE_ABILITY_DETECT_INIT 5
5018 #define ANEG_STATE_ABILITY_DETECT 6
5019 #define ANEG_STATE_ACK_DETECT_INIT 7
5020 #define ANEG_STATE_ACK_DETECT 8
5021 #define ANEG_STATE_COMPLETE_ACK_INIT 9
5022 #define ANEG_STATE_COMPLETE_ACK 10
5023 #define ANEG_STATE_IDLE_DETECT_INIT 11
5024 #define ANEG_STATE_IDLE_DETECT 12
5025 #define ANEG_STATE_LINK_OK 13
5026 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
5027 #define ANEG_STATE_NEXT_PAGE_WAIT 15
5030 #define MR_AN_ENABLE 0x00000001
5031 #define MR_RESTART_AN 0x00000002
5032 #define MR_AN_COMPLETE 0x00000004
5033 #define MR_PAGE_RX 0x00000008
5034 #define MR_NP_LOADED 0x00000010
5035 #define MR_TOGGLE_TX 0x00000020
5036 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
5037 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
5038 #define MR_LP_ADV_SYM_PAUSE 0x00000100
5039 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
5040 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
5041 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
5042 #define MR_LP_ADV_NEXT_PAGE 0x00001000
5043 #define MR_TOGGLE_RX 0x00002000
5044 #define MR_NP_RX 0x00004000
5046 #define MR_LINK_OK 0x80000000
5048 unsigned long link_time
, cur_time
;
5050 u32 ability_match_cfg
;
5051 int ability_match_count
;
5053 char ability_match
, idle_match
, ack_match
;
5055 u32 txconfig
, rxconfig
;
5056 #define ANEG_CFG_NP 0x00000080
5057 #define ANEG_CFG_ACK 0x00000040
5058 #define ANEG_CFG_RF2 0x00000020
5059 #define ANEG_CFG_RF1 0x00000010
5060 #define ANEG_CFG_PS2 0x00000001
5061 #define ANEG_CFG_PS1 0x00008000
5062 #define ANEG_CFG_HD 0x00004000
5063 #define ANEG_CFG_FD 0x00002000
5064 #define ANEG_CFG_INVAL 0x00001f06
5069 #define ANEG_TIMER_ENAB 2
5070 #define ANEG_FAILED -1
5072 #define ANEG_STATE_SETTLE_TIME 10000
5074 static int tg3_fiber_aneg_smachine(struct tg3
*tp
,
5075 struct tg3_fiber_aneginfo
*ap
)
5078 unsigned long delta
;
5082 if (ap
->state
== ANEG_STATE_UNKNOWN
) {
5086 ap
->ability_match_cfg
= 0;
5087 ap
->ability_match_count
= 0;
5088 ap
->ability_match
= 0;
5094 if (tr32(MAC_STATUS
) & MAC_STATUS_RCVD_CFG
) {
5095 rx_cfg_reg
= tr32(MAC_RX_AUTO_NEG
);
5097 if (rx_cfg_reg
!= ap
->ability_match_cfg
) {
5098 ap
->ability_match_cfg
= rx_cfg_reg
;
5099 ap
->ability_match
= 0;
5100 ap
->ability_match_count
= 0;
5102 if (++ap
->ability_match_count
> 1) {
5103 ap
->ability_match
= 1;
5104 ap
->ability_match_cfg
= rx_cfg_reg
;
5107 if (rx_cfg_reg
& ANEG_CFG_ACK
)
5115 ap
->ability_match_cfg
= 0;
5116 ap
->ability_match_count
= 0;
5117 ap
->ability_match
= 0;
5123 ap
->rxconfig
= rx_cfg_reg
;
5126 switch (ap
->state
) {
5127 case ANEG_STATE_UNKNOWN
:
5128 if (ap
->flags
& (MR_AN_ENABLE
| MR_RESTART_AN
))
5129 ap
->state
= ANEG_STATE_AN_ENABLE
;
5132 case ANEG_STATE_AN_ENABLE
:
5133 ap
->flags
&= ~(MR_AN_COMPLETE
| MR_PAGE_RX
);
5134 if (ap
->flags
& MR_AN_ENABLE
) {
5137 ap
->ability_match_cfg
= 0;
5138 ap
->ability_match_count
= 0;
5139 ap
->ability_match
= 0;
5143 ap
->state
= ANEG_STATE_RESTART_INIT
;
5145 ap
->state
= ANEG_STATE_DISABLE_LINK_OK
;
5149 case ANEG_STATE_RESTART_INIT
:
5150 ap
->link_time
= ap
->cur_time
;
5151 ap
->flags
&= ~(MR_NP_LOADED
);
5153 tw32(MAC_TX_AUTO_NEG
, 0);
5154 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
5155 tw32_f(MAC_MODE
, tp
->mac_mode
);
5158 ret
= ANEG_TIMER_ENAB
;
5159 ap
->state
= ANEG_STATE_RESTART
;
5162 case ANEG_STATE_RESTART
:
5163 delta
= ap
->cur_time
- ap
->link_time
;
5164 if (delta
> ANEG_STATE_SETTLE_TIME
)
5165 ap
->state
= ANEG_STATE_ABILITY_DETECT_INIT
;
5167 ret
= ANEG_TIMER_ENAB
;
5170 case ANEG_STATE_DISABLE_LINK_OK
:
5174 case ANEG_STATE_ABILITY_DETECT_INIT
:
5175 ap
->flags
&= ~(MR_TOGGLE_TX
);
5176 ap
->txconfig
= ANEG_CFG_FD
;
5177 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
5178 if (flowctrl
& ADVERTISE_1000XPAUSE
)
5179 ap
->txconfig
|= ANEG_CFG_PS1
;
5180 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
5181 ap
->txconfig
|= ANEG_CFG_PS2
;
5182 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
5183 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
5184 tw32_f(MAC_MODE
, tp
->mac_mode
);
5187 ap
->state
= ANEG_STATE_ABILITY_DETECT
;
5190 case ANEG_STATE_ABILITY_DETECT
:
5191 if (ap
->ability_match
!= 0 && ap
->rxconfig
!= 0)
5192 ap
->state
= ANEG_STATE_ACK_DETECT_INIT
;
5195 case ANEG_STATE_ACK_DETECT_INIT
:
5196 ap
->txconfig
|= ANEG_CFG_ACK
;
5197 tw32(MAC_TX_AUTO_NEG
, ap
->txconfig
);
5198 tp
->mac_mode
|= MAC_MODE_SEND_CONFIGS
;
5199 tw32_f(MAC_MODE
, tp
->mac_mode
);
5202 ap
->state
= ANEG_STATE_ACK_DETECT
;
5205 case ANEG_STATE_ACK_DETECT
:
5206 if (ap
->ack_match
!= 0) {
5207 if ((ap
->rxconfig
& ~ANEG_CFG_ACK
) ==
5208 (ap
->ability_match_cfg
& ~ANEG_CFG_ACK
)) {
5209 ap
->state
= ANEG_STATE_COMPLETE_ACK_INIT
;
5211 ap
->state
= ANEG_STATE_AN_ENABLE
;
5213 } else if (ap
->ability_match
!= 0 &&
5214 ap
->rxconfig
== 0) {
5215 ap
->state
= ANEG_STATE_AN_ENABLE
;
5219 case ANEG_STATE_COMPLETE_ACK_INIT
:
5220 if (ap
->rxconfig
& ANEG_CFG_INVAL
) {
5224 ap
->flags
&= ~(MR_LP_ADV_FULL_DUPLEX
|
5225 MR_LP_ADV_HALF_DUPLEX
|
5226 MR_LP_ADV_SYM_PAUSE
|
5227 MR_LP_ADV_ASYM_PAUSE
|
5228 MR_LP_ADV_REMOTE_FAULT1
|
5229 MR_LP_ADV_REMOTE_FAULT2
|
5230 MR_LP_ADV_NEXT_PAGE
|
5233 if (ap
->rxconfig
& ANEG_CFG_FD
)
5234 ap
->flags
|= MR_LP_ADV_FULL_DUPLEX
;
5235 if (ap
->rxconfig
& ANEG_CFG_HD
)
5236 ap
->flags
|= MR_LP_ADV_HALF_DUPLEX
;
5237 if (ap
->rxconfig
& ANEG_CFG_PS1
)
5238 ap
->flags
|= MR_LP_ADV_SYM_PAUSE
;
5239 if (ap
->rxconfig
& ANEG_CFG_PS2
)
5240 ap
->flags
|= MR_LP_ADV_ASYM_PAUSE
;
5241 if (ap
->rxconfig
& ANEG_CFG_RF1
)
5242 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT1
;
5243 if (ap
->rxconfig
& ANEG_CFG_RF2
)
5244 ap
->flags
|= MR_LP_ADV_REMOTE_FAULT2
;
5245 if (ap
->rxconfig
& ANEG_CFG_NP
)
5246 ap
->flags
|= MR_LP_ADV_NEXT_PAGE
;
5248 ap
->link_time
= ap
->cur_time
;
5250 ap
->flags
^= (MR_TOGGLE_TX
);
5251 if (ap
->rxconfig
& 0x0008)
5252 ap
->flags
|= MR_TOGGLE_RX
;
5253 if (ap
->rxconfig
& ANEG_CFG_NP
)
5254 ap
->flags
|= MR_NP_RX
;
5255 ap
->flags
|= MR_PAGE_RX
;
5257 ap
->state
= ANEG_STATE_COMPLETE_ACK
;
5258 ret
= ANEG_TIMER_ENAB
;
5261 case ANEG_STATE_COMPLETE_ACK
:
5262 if (ap
->ability_match
!= 0 &&
5263 ap
->rxconfig
== 0) {
5264 ap
->state
= ANEG_STATE_AN_ENABLE
;
5267 delta
= ap
->cur_time
- ap
->link_time
;
5268 if (delta
> ANEG_STATE_SETTLE_TIME
) {
5269 if (!(ap
->flags
& (MR_LP_ADV_NEXT_PAGE
))) {
5270 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
5272 if ((ap
->txconfig
& ANEG_CFG_NP
) == 0 &&
5273 !(ap
->flags
& MR_NP_RX
)) {
5274 ap
->state
= ANEG_STATE_IDLE_DETECT_INIT
;
5282 case ANEG_STATE_IDLE_DETECT_INIT
:
5283 ap
->link_time
= ap
->cur_time
;
5284 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
5285 tw32_f(MAC_MODE
, tp
->mac_mode
);
5288 ap
->state
= ANEG_STATE_IDLE_DETECT
;
5289 ret
= ANEG_TIMER_ENAB
;
5292 case ANEG_STATE_IDLE_DETECT
:
5293 if (ap
->ability_match
!= 0 &&
5294 ap
->rxconfig
== 0) {
5295 ap
->state
= ANEG_STATE_AN_ENABLE
;
5298 delta
= ap
->cur_time
- ap
->link_time
;
5299 if (delta
> ANEG_STATE_SETTLE_TIME
) {
5300 /* XXX another gem from the Broadcom driver :( */
5301 ap
->state
= ANEG_STATE_LINK_OK
;
5305 case ANEG_STATE_LINK_OK
:
5306 ap
->flags
|= (MR_AN_COMPLETE
| MR_LINK_OK
);
5310 case ANEG_STATE_NEXT_PAGE_WAIT_INIT
:
5311 /* ??? unimplemented */
5314 case ANEG_STATE_NEXT_PAGE_WAIT
:
5315 /* ??? unimplemented */
5326 static int fiber_autoneg(struct tg3
*tp
, u32
*txflags
, u32
*rxflags
)
5329 struct tg3_fiber_aneginfo aninfo
;
5330 int status
= ANEG_FAILED
;
5334 tw32_f(MAC_TX_AUTO_NEG
, 0);
5336 tmp
= tp
->mac_mode
& ~MAC_MODE_PORT_MODE_MASK
;
5337 tw32_f(MAC_MODE
, tmp
| MAC_MODE_PORT_MODE_GMII
);
5340 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
);
5343 memset(&aninfo
, 0, sizeof(aninfo
));
5344 aninfo
.flags
|= MR_AN_ENABLE
;
5345 aninfo
.state
= ANEG_STATE_UNKNOWN
;
5346 aninfo
.cur_time
= 0;
5348 while (++tick
< 195000) {
5349 status
= tg3_fiber_aneg_smachine(tp
, &aninfo
);
5350 if (status
== ANEG_DONE
|| status
== ANEG_FAILED
)
5356 tp
->mac_mode
&= ~MAC_MODE_SEND_CONFIGS
;
5357 tw32_f(MAC_MODE
, tp
->mac_mode
);
5360 *txflags
= aninfo
.txconfig
;
5361 *rxflags
= aninfo
.flags
;
5363 if (status
== ANEG_DONE
&&
5364 (aninfo
.flags
& (MR_AN_COMPLETE
| MR_LINK_OK
|
5365 MR_LP_ADV_FULL_DUPLEX
)))
5371 static void tg3_init_bcm8002(struct tg3
*tp
)
5373 u32 mac_status
= tr32(MAC_STATUS
);
5376 /* Reset when initting first time or we have a link. */
5377 if (tg3_flag(tp
, INIT_COMPLETE
) &&
5378 !(mac_status
& MAC_STATUS_PCS_SYNCED
))
5381 /* Set PLL lock range. */
5382 tg3_writephy(tp
, 0x16, 0x8007);
5385 tg3_writephy(tp
, MII_BMCR
, BMCR_RESET
);
5387 /* Wait for reset to complete. */
5388 /* XXX schedule_timeout() ... */
5389 for (i
= 0; i
< 500; i
++)
5392 /* Config mode; select PMA/Ch 1 regs. */
5393 tg3_writephy(tp
, 0x10, 0x8411);
5395 /* Enable auto-lock and comdet, select txclk for tx. */
5396 tg3_writephy(tp
, 0x11, 0x0a10);
5398 tg3_writephy(tp
, 0x18, 0x00a0);
5399 tg3_writephy(tp
, 0x16, 0x41ff);
5401 /* Assert and deassert POR. */
5402 tg3_writephy(tp
, 0x13, 0x0400);
5404 tg3_writephy(tp
, 0x13, 0x0000);
5406 tg3_writephy(tp
, 0x11, 0x0a50);
5408 tg3_writephy(tp
, 0x11, 0x0a10);
5410 /* Wait for signal to stabilize */
5411 /* XXX schedule_timeout() ... */
5412 for (i
= 0; i
< 15000; i
++)
5415 /* Deselect the channel register so we can read the PHYID
5418 tg3_writephy(tp
, 0x10, 0x8011);
5421 static bool tg3_setup_fiber_hw_autoneg(struct tg3
*tp
, u32 mac_status
)
5424 bool current_link_up
;
5425 u32 sg_dig_ctrl
, sg_dig_status
;
5426 u32 serdes_cfg
, expected_sg_dig_ctrl
;
5427 int workaround
, port_a
;
5430 expected_sg_dig_ctrl
= 0;
5433 current_link_up
= false;
5435 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5704_A0
&&
5436 tg3_chip_rev_id(tp
) != CHIPREV_ID_5704_A1
) {
5438 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
5441 /* preserve bits 0-11,13,14 for signal pre-emphasis */
5442 /* preserve bits 20-23 for voltage regulator */
5443 serdes_cfg
= tr32(MAC_SERDES_CFG
) & 0x00f06fff;
5446 sg_dig_ctrl
= tr32(SG_DIG_CTRL
);
5448 if (tp
->link_config
.autoneg
!= AUTONEG_ENABLE
) {
5449 if (sg_dig_ctrl
& SG_DIG_USING_HW_AUTONEG
) {
5451 u32 val
= serdes_cfg
;
5457 tw32_f(MAC_SERDES_CFG
, val
);
5460 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
5462 if (mac_status
& MAC_STATUS_PCS_SYNCED
) {
5463 tg3_setup_flow_control(tp
, 0, 0);
5464 current_link_up
= true;
5469 /* Want auto-negotiation. */
5470 expected_sg_dig_ctrl
= SG_DIG_USING_HW_AUTONEG
| SG_DIG_COMMON_SETUP
;
5472 flowctrl
= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
5473 if (flowctrl
& ADVERTISE_1000XPAUSE
)
5474 expected_sg_dig_ctrl
|= SG_DIG_PAUSE_CAP
;
5475 if (flowctrl
& ADVERTISE_1000XPSE_ASYM
)
5476 expected_sg_dig_ctrl
|= SG_DIG_ASYM_PAUSE
;
5478 if (sg_dig_ctrl
!= expected_sg_dig_ctrl
) {
5479 if ((tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
) &&
5480 tp
->serdes_counter
&&
5481 ((mac_status
& (MAC_STATUS_PCS_SYNCED
|
5482 MAC_STATUS_RCVD_CFG
)) ==
5483 MAC_STATUS_PCS_SYNCED
)) {
5484 tp
->serdes_counter
--;
5485 current_link_up
= true;
5490 tw32_f(MAC_SERDES_CFG
, serdes_cfg
| 0xc011000);
5491 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
| SG_DIG_SOFT_RESET
);
5493 tw32_f(SG_DIG_CTRL
, expected_sg_dig_ctrl
);
5495 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
5496 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5497 } else if (mac_status
& (MAC_STATUS_PCS_SYNCED
|
5498 MAC_STATUS_SIGNAL_DET
)) {
5499 sg_dig_status
= tr32(SG_DIG_STATUS
);
5500 mac_status
= tr32(MAC_STATUS
);
5502 if ((sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
) &&
5503 (mac_status
& MAC_STATUS_PCS_SYNCED
)) {
5504 u32 local_adv
= 0, remote_adv
= 0;
5506 if (sg_dig_ctrl
& SG_DIG_PAUSE_CAP
)
5507 local_adv
|= ADVERTISE_1000XPAUSE
;
5508 if (sg_dig_ctrl
& SG_DIG_ASYM_PAUSE
)
5509 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
5511 if (sg_dig_status
& SG_DIG_PARTNER_PAUSE_CAPABLE
)
5512 remote_adv
|= LPA_1000XPAUSE
;
5513 if (sg_dig_status
& SG_DIG_PARTNER_ASYM_PAUSE
)
5514 remote_adv
|= LPA_1000XPAUSE_ASYM
;
5516 tp
->link_config
.rmt_adv
=
5517 mii_adv_to_ethtool_adv_x(remote_adv
);
5519 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
5520 current_link_up
= true;
5521 tp
->serdes_counter
= 0;
5522 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5523 } else if (!(sg_dig_status
& SG_DIG_AUTONEG_COMPLETE
)) {
5524 if (tp
->serdes_counter
)
5525 tp
->serdes_counter
--;
5528 u32 val
= serdes_cfg
;
5535 tw32_f(MAC_SERDES_CFG
, val
);
5538 tw32_f(SG_DIG_CTRL
, SG_DIG_COMMON_SETUP
);
5541 /* Link parallel detection - link is up */
5542 /* only if we have PCS_SYNC and not */
5543 /* receiving config code words */
5544 mac_status
= tr32(MAC_STATUS
);
5545 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) &&
5546 !(mac_status
& MAC_STATUS_RCVD_CFG
)) {
5547 tg3_setup_flow_control(tp
, 0, 0);
5548 current_link_up
= true;
5550 TG3_PHYFLG_PARALLEL_DETECT
;
5551 tp
->serdes_counter
=
5552 SERDES_PARALLEL_DET_TIMEOUT
;
5554 goto restart_autoneg
;
5558 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5704S
;
5559 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5563 return current_link_up
;
5566 static bool tg3_setup_fiber_by_hand(struct tg3
*tp
, u32 mac_status
)
5568 bool current_link_up
= false;
5570 if (!(mac_status
& MAC_STATUS_PCS_SYNCED
))
5573 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
5574 u32 txflags
, rxflags
;
5577 if (fiber_autoneg(tp
, &txflags
, &rxflags
)) {
5578 u32 local_adv
= 0, remote_adv
= 0;
5580 if (txflags
& ANEG_CFG_PS1
)
5581 local_adv
|= ADVERTISE_1000XPAUSE
;
5582 if (txflags
& ANEG_CFG_PS2
)
5583 local_adv
|= ADVERTISE_1000XPSE_ASYM
;
5585 if (rxflags
& MR_LP_ADV_SYM_PAUSE
)
5586 remote_adv
|= LPA_1000XPAUSE
;
5587 if (rxflags
& MR_LP_ADV_ASYM_PAUSE
)
5588 remote_adv
|= LPA_1000XPAUSE_ASYM
;
5590 tp
->link_config
.rmt_adv
=
5591 mii_adv_to_ethtool_adv_x(remote_adv
);
5593 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
5595 current_link_up
= true;
5597 for (i
= 0; i
< 30; i
++) {
5600 (MAC_STATUS_SYNC_CHANGED
|
5601 MAC_STATUS_CFG_CHANGED
));
5603 if ((tr32(MAC_STATUS
) &
5604 (MAC_STATUS_SYNC_CHANGED
|
5605 MAC_STATUS_CFG_CHANGED
)) == 0)
5609 mac_status
= tr32(MAC_STATUS
);
5610 if (!current_link_up
&&
5611 (mac_status
& MAC_STATUS_PCS_SYNCED
) &&
5612 !(mac_status
& MAC_STATUS_RCVD_CFG
))
5613 current_link_up
= true;
5615 tg3_setup_flow_control(tp
, 0, 0);
5617 /* Forcing 1000FD link up. */
5618 current_link_up
= true;
5620 tw32_f(MAC_MODE
, (tp
->mac_mode
| MAC_MODE_SEND_CONFIGS
));
5623 tw32_f(MAC_MODE
, tp
->mac_mode
);
5628 return current_link_up
;
5631 static int tg3_setup_fiber_phy(struct tg3
*tp
, bool force_reset
)
5634 u16 orig_active_speed
;
5635 u8 orig_active_duplex
;
5637 bool current_link_up
;
5640 orig_pause_cfg
= tp
->link_config
.active_flowctrl
;
5641 orig_active_speed
= tp
->link_config
.active_speed
;
5642 orig_active_duplex
= tp
->link_config
.active_duplex
;
5644 if (!tg3_flag(tp
, HW_AUTONEG
) &&
5646 tg3_flag(tp
, INIT_COMPLETE
)) {
5647 mac_status
= tr32(MAC_STATUS
);
5648 mac_status
&= (MAC_STATUS_PCS_SYNCED
|
5649 MAC_STATUS_SIGNAL_DET
|
5650 MAC_STATUS_CFG_CHANGED
|
5651 MAC_STATUS_RCVD_CFG
);
5652 if (mac_status
== (MAC_STATUS_PCS_SYNCED
|
5653 MAC_STATUS_SIGNAL_DET
)) {
5654 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
5655 MAC_STATUS_CFG_CHANGED
));
5660 tw32_f(MAC_TX_AUTO_NEG
, 0);
5662 tp
->mac_mode
&= ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
5663 tp
->mac_mode
|= MAC_MODE_PORT_MODE_TBI
;
5664 tw32_f(MAC_MODE
, tp
->mac_mode
);
5667 if (tp
->phy_id
== TG3_PHY_ID_BCM8002
)
5668 tg3_init_bcm8002(tp
);
5670 /* Enable link change event even when serdes polling. */
5671 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
5674 current_link_up
= false;
5675 tp
->link_config
.rmt_adv
= 0;
5676 mac_status
= tr32(MAC_STATUS
);
5678 if (tg3_flag(tp
, HW_AUTONEG
))
5679 current_link_up
= tg3_setup_fiber_hw_autoneg(tp
, mac_status
);
5681 current_link_up
= tg3_setup_fiber_by_hand(tp
, mac_status
);
5683 tp
->napi
[0].hw_status
->status
=
5684 (SD_STATUS_UPDATED
|
5685 (tp
->napi
[0].hw_status
->status
& ~SD_STATUS_LINK_CHG
));
5687 for (i
= 0; i
< 100; i
++) {
5688 tw32_f(MAC_STATUS
, (MAC_STATUS_SYNC_CHANGED
|
5689 MAC_STATUS_CFG_CHANGED
));
5691 if ((tr32(MAC_STATUS
) & (MAC_STATUS_SYNC_CHANGED
|
5692 MAC_STATUS_CFG_CHANGED
|
5693 MAC_STATUS_LNKSTATE_CHANGED
)) == 0)
5697 mac_status
= tr32(MAC_STATUS
);
5698 if ((mac_status
& MAC_STATUS_PCS_SYNCED
) == 0) {
5699 current_link_up
= false;
5700 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
&&
5701 tp
->serdes_counter
== 0) {
5702 tw32_f(MAC_MODE
, (tp
->mac_mode
|
5703 MAC_MODE_SEND_CONFIGS
));
5705 tw32_f(MAC_MODE
, tp
->mac_mode
);
5709 if (current_link_up
) {
5710 tp
->link_config
.active_speed
= SPEED_1000
;
5711 tp
->link_config
.active_duplex
= DUPLEX_FULL
;
5712 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
5713 LED_CTRL_LNKLED_OVERRIDE
|
5714 LED_CTRL_1000MBPS_ON
));
5716 tp
->link_config
.active_speed
= SPEED_UNKNOWN
;
5717 tp
->link_config
.active_duplex
= DUPLEX_UNKNOWN
;
5718 tw32(MAC_LED_CTRL
, (tp
->led_ctrl
|
5719 LED_CTRL_LNKLED_OVERRIDE
|
5720 LED_CTRL_TRAFFIC_OVERRIDE
));
5723 if (!tg3_test_and_report_link_chg(tp
, current_link_up
)) {
5724 u32 now_pause_cfg
= tp
->link_config
.active_flowctrl
;
5725 if (orig_pause_cfg
!= now_pause_cfg
||
5726 orig_active_speed
!= tp
->link_config
.active_speed
||
5727 orig_active_duplex
!= tp
->link_config
.active_duplex
)
5728 tg3_link_report(tp
);
5734 static int tg3_setup_fiber_mii_phy(struct tg3
*tp
, bool force_reset
)
5738 u16 current_speed
= SPEED_UNKNOWN
;
5739 u8 current_duplex
= DUPLEX_UNKNOWN
;
5740 bool current_link_up
= false;
5741 u32 local_adv
, remote_adv
, sgsr
;
5743 if ((tg3_asic_rev(tp
) == ASIC_REV_5719
||
5744 tg3_asic_rev(tp
) == ASIC_REV_5720
) &&
5745 !tg3_readphy(tp
, SERDES_TG3_1000X_STATUS
, &sgsr
) &&
5746 (sgsr
& SERDES_TG3_SGMII_MODE
)) {
5751 tp
->mac_mode
&= ~MAC_MODE_PORT_MODE_MASK
;
5753 if (!(sgsr
& SERDES_TG3_LINK_UP
)) {
5754 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
5756 current_link_up
= true;
5757 if (sgsr
& SERDES_TG3_SPEED_1000
) {
5758 current_speed
= SPEED_1000
;
5759 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
5760 } else if (sgsr
& SERDES_TG3_SPEED_100
) {
5761 current_speed
= SPEED_100
;
5762 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
5764 current_speed
= SPEED_10
;
5765 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
5768 if (sgsr
& SERDES_TG3_FULL_DUPLEX
)
5769 current_duplex
= DUPLEX_FULL
;
5771 current_duplex
= DUPLEX_HALF
;
5774 tw32_f(MAC_MODE
, tp
->mac_mode
);
5777 tg3_clear_mac_status(tp
);
5779 goto fiber_setup_done
;
5782 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
5783 tw32_f(MAC_MODE
, tp
->mac_mode
);
5786 tg3_clear_mac_status(tp
);
5791 tp
->link_config
.rmt_adv
= 0;
5793 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
5794 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
5795 if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
5796 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
5797 bmsr
|= BMSR_LSTATUS
;
5799 bmsr
&= ~BMSR_LSTATUS
;
5802 err
|= tg3_readphy(tp
, MII_BMCR
, &bmcr
);
5804 if ((tp
->link_config
.autoneg
== AUTONEG_ENABLE
) && !force_reset
&&
5805 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
5806 /* do nothing, just check for link up at the end */
5807 } else if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) {
5810 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
5811 newadv
= adv
& ~(ADVERTISE_1000XFULL
| ADVERTISE_1000XHALF
|
5812 ADVERTISE_1000XPAUSE
|
5813 ADVERTISE_1000XPSE_ASYM
|
5816 newadv
|= tg3_advert_flowctrl_1000X(tp
->link_config
.flowctrl
);
5817 newadv
|= ethtool_adv_to_mii_adv_x(tp
->link_config
.advertising
);
5819 if ((newadv
!= adv
) || !(bmcr
& BMCR_ANENABLE
)) {
5820 tg3_writephy(tp
, MII_ADVERTISE
, newadv
);
5821 bmcr
|= BMCR_ANENABLE
| BMCR_ANRESTART
;
5822 tg3_writephy(tp
, MII_BMCR
, bmcr
);
5824 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
5825 tp
->serdes_counter
= SERDES_AN_TIMEOUT_5714S
;
5826 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5833 bmcr
&= ~BMCR_SPEED1000
;
5834 new_bmcr
= bmcr
& ~(BMCR_ANENABLE
| BMCR_FULLDPLX
);
5836 if (tp
->link_config
.duplex
== DUPLEX_FULL
)
5837 new_bmcr
|= BMCR_FULLDPLX
;
5839 if (new_bmcr
!= bmcr
) {
5840 /* BMCR_SPEED1000 is a reserved bit that needs
5841 * to be set on write.
5843 new_bmcr
|= BMCR_SPEED1000
;
5845 /* Force a linkdown */
5849 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &adv
);
5850 adv
&= ~(ADVERTISE_1000XFULL
|
5851 ADVERTISE_1000XHALF
|
5853 tg3_writephy(tp
, MII_ADVERTISE
, adv
);
5854 tg3_writephy(tp
, MII_BMCR
, bmcr
|
5858 tg3_carrier_off(tp
);
5860 tg3_writephy(tp
, MII_BMCR
, new_bmcr
);
5862 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
5863 err
|= tg3_readphy(tp
, MII_BMSR
, &bmsr
);
5864 if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
5865 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
5866 bmsr
|= BMSR_LSTATUS
;
5868 bmsr
&= ~BMSR_LSTATUS
;
5870 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5874 if (bmsr
& BMSR_LSTATUS
) {
5875 current_speed
= SPEED_1000
;
5876 current_link_up
= true;
5877 if (bmcr
& BMCR_FULLDPLX
)
5878 current_duplex
= DUPLEX_FULL
;
5880 current_duplex
= DUPLEX_HALF
;
5885 if (bmcr
& BMCR_ANENABLE
) {
5888 err
|= tg3_readphy(tp
, MII_ADVERTISE
, &local_adv
);
5889 err
|= tg3_readphy(tp
, MII_LPA
, &remote_adv
);
5890 common
= local_adv
& remote_adv
;
5891 if (common
& (ADVERTISE_1000XHALF
|
5892 ADVERTISE_1000XFULL
)) {
5893 if (common
& ADVERTISE_1000XFULL
)
5894 current_duplex
= DUPLEX_FULL
;
5896 current_duplex
= DUPLEX_HALF
;
5898 tp
->link_config
.rmt_adv
=
5899 mii_adv_to_ethtool_adv_x(remote_adv
);
5900 } else if (!tg3_flag(tp
, 5780_CLASS
)) {
5901 /* Link is up via parallel detect */
5903 current_link_up
= false;
5909 if (current_link_up
&& current_duplex
== DUPLEX_FULL
)
5910 tg3_setup_flow_control(tp
, local_adv
, remote_adv
);
5912 tp
->mac_mode
&= ~MAC_MODE_HALF_DUPLEX
;
5913 if (tp
->link_config
.active_duplex
== DUPLEX_HALF
)
5914 tp
->mac_mode
|= MAC_MODE_HALF_DUPLEX
;
5916 tw32_f(MAC_MODE
, tp
->mac_mode
);
5919 tw32_f(MAC_EVENT
, MAC_EVENT_LNKSTATE_CHANGED
);
5921 tp
->link_config
.active_speed
= current_speed
;
5922 tp
->link_config
.active_duplex
= current_duplex
;
5924 tg3_test_and_report_link_chg(tp
, current_link_up
);
5928 static void tg3_serdes_parallel_detect(struct tg3
*tp
)
5930 if (tp
->serdes_counter
) {
5931 /* Give autoneg time to complete. */
5932 tp
->serdes_counter
--;
5937 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)) {
5940 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
5941 if (bmcr
& BMCR_ANENABLE
) {
5944 /* Select shadow register 0x1f */
5945 tg3_writephy(tp
, MII_TG3_MISC_SHDW
, 0x7c00);
5946 tg3_readphy(tp
, MII_TG3_MISC_SHDW
, &phy1
);
5948 /* Select expansion interrupt status register */
5949 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
5950 MII_TG3_DSP_EXP1_INT_STAT
);
5951 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
5952 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
5954 if ((phy1
& 0x10) && !(phy2
& 0x20)) {
5955 /* We have signal detect and not receiving
5956 * config code words, link is up by parallel
5960 bmcr
&= ~BMCR_ANENABLE
;
5961 bmcr
|= BMCR_SPEED1000
| BMCR_FULLDPLX
;
5962 tg3_writephy(tp
, MII_BMCR
, bmcr
);
5963 tp
->phy_flags
|= TG3_PHYFLG_PARALLEL_DETECT
;
5966 } else if (tp
->link_up
&&
5967 (tp
->link_config
.autoneg
== AUTONEG_ENABLE
) &&
5968 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
)) {
5971 /* Select expansion interrupt status register */
5972 tg3_writephy(tp
, MII_TG3_DSP_ADDRESS
,
5973 MII_TG3_DSP_EXP1_INT_STAT
);
5974 tg3_readphy(tp
, MII_TG3_DSP_RW_PORT
, &phy2
);
5978 /* Config code words received, turn on autoneg. */
5979 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
5980 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANENABLE
);
5982 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
5988 static int tg3_setup_phy(struct tg3
*tp
, bool force_reset
)
5993 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
5994 err
= tg3_setup_fiber_phy(tp
, force_reset
);
5995 else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
5996 err
= tg3_setup_fiber_mii_phy(tp
, force_reset
);
5998 err
= tg3_setup_copper_phy(tp
, force_reset
);
6000 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
) {
6003 val
= tr32(TG3_CPMU_CLCK_STAT
) & CPMU_CLCK_STAT_MAC_CLCK_MASK
;
6004 if (val
== CPMU_CLCK_STAT_MAC_CLCK_62_5
)
6006 else if (val
== CPMU_CLCK_STAT_MAC_CLCK_6_25
)
6011 val
= tr32(GRC_MISC_CFG
) & ~GRC_MISC_CFG_PRESCALAR_MASK
;
6012 val
|= (scale
<< GRC_MISC_CFG_PRESCALAR_SHIFT
);
6013 tw32(GRC_MISC_CFG
, val
);
6016 val
= (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
6017 (6 << TX_LENGTHS_IPG_SHIFT
);
6018 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
6019 tg3_asic_rev(tp
) == ASIC_REV_5762
)
6020 val
|= tr32(MAC_TX_LENGTHS
) &
6021 (TX_LENGTHS_JMB_FRM_LEN_MSK
|
6022 TX_LENGTHS_CNT_DWN_VAL_MSK
);
6024 if (tp
->link_config
.active_speed
== SPEED_1000
&&
6025 tp
->link_config
.active_duplex
== DUPLEX_HALF
)
6026 tw32(MAC_TX_LENGTHS
, val
|
6027 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT
));
6029 tw32(MAC_TX_LENGTHS
, val
|
6030 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
));
6032 if (!tg3_flag(tp
, 5705_PLUS
)) {
6034 tw32(HOSTCC_STAT_COAL_TICKS
,
6035 tp
->coal
.stats_block_coalesce_usecs
);
6037 tw32(HOSTCC_STAT_COAL_TICKS
, 0);
6041 if (tg3_flag(tp
, ASPM_WORKAROUND
)) {
6042 val
= tr32(PCIE_PWR_MGMT_THRESH
);
6044 val
= (val
& ~PCIE_PWR_MGMT_L1_THRESH_MSK
) |
6047 val
|= PCIE_PWR_MGMT_L1_THRESH_MSK
;
6048 tw32(PCIE_PWR_MGMT_THRESH
, val
);
6054 /* tp->lock must be held */
6055 static u64
tg3_refclk_read(struct tg3
*tp
)
6057 u64 stamp
= tr32(TG3_EAV_REF_CLCK_LSB
);
6058 return stamp
| (u64
)tr32(TG3_EAV_REF_CLCK_MSB
) << 32;
6061 /* tp->lock must be held */
6062 static void tg3_refclk_write(struct tg3
*tp
, u64 newval
)
6064 tw32(TG3_EAV_REF_CLCK_CTL
, TG3_EAV_REF_CLCK_CTL_STOP
);
6065 tw32(TG3_EAV_REF_CLCK_LSB
, newval
& 0xffffffff);
6066 tw32(TG3_EAV_REF_CLCK_MSB
, newval
>> 32);
6067 tw32_f(TG3_EAV_REF_CLCK_CTL
, TG3_EAV_REF_CLCK_CTL_RESUME
);
6070 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
);
6071 static inline void tg3_full_unlock(struct tg3
*tp
);
6072 static int tg3_get_ts_info(struct net_device
*dev
, struct ethtool_ts_info
*info
)
6074 struct tg3
*tp
= netdev_priv(dev
);
6076 info
->so_timestamping
= SOF_TIMESTAMPING_TX_SOFTWARE
|
6077 SOF_TIMESTAMPING_RX_SOFTWARE
|
6078 SOF_TIMESTAMPING_SOFTWARE
;
6080 if (tg3_flag(tp
, PTP_CAPABLE
)) {
6081 info
->so_timestamping
|= SOF_TIMESTAMPING_TX_HARDWARE
|
6082 SOF_TIMESTAMPING_RX_HARDWARE
|
6083 SOF_TIMESTAMPING_RAW_HARDWARE
;
6087 info
->phc_index
= ptp_clock_index(tp
->ptp_clock
);
6089 info
->phc_index
= -1;
6091 info
->tx_types
= (1 << HWTSTAMP_TX_OFF
) | (1 << HWTSTAMP_TX_ON
);
6093 info
->rx_filters
= (1 << HWTSTAMP_FILTER_NONE
) |
6094 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT
) |
6095 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT
) |
6096 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT
);
6100 static int tg3_ptp_adjfreq(struct ptp_clock_info
*ptp
, s32 ppb
)
6102 struct tg3
*tp
= container_of(ptp
, struct tg3
, ptp_info
);
6103 bool neg_adj
= false;
6111 /* Frequency adjustment is performed using hardware with a 24 bit
6112 * accumulator and a programmable correction value. On each clk, the
6113 * correction value gets added to the accumulator and when it
6114 * overflows, the time counter is incremented/decremented.
6116 * So conversion from ppb to correction value is
6117 * ppb * (1 << 24) / 1000000000
6119 correction
= div_u64((u64
)ppb
* (1 << 24), 1000000000ULL) &
6120 TG3_EAV_REF_CLK_CORRECT_MASK
;
6122 tg3_full_lock(tp
, 0);
6125 tw32(TG3_EAV_REF_CLK_CORRECT_CTL
,
6126 TG3_EAV_REF_CLK_CORRECT_EN
|
6127 (neg_adj
? TG3_EAV_REF_CLK_CORRECT_NEG
: 0) | correction
);
6129 tw32(TG3_EAV_REF_CLK_CORRECT_CTL
, 0);
6131 tg3_full_unlock(tp
);
6136 static int tg3_ptp_adjtime(struct ptp_clock_info
*ptp
, s64 delta
)
6138 struct tg3
*tp
= container_of(ptp
, struct tg3
, ptp_info
);
6140 tg3_full_lock(tp
, 0);
6141 tp
->ptp_adjust
+= delta
;
6142 tg3_full_unlock(tp
);
6147 static int tg3_ptp_gettime(struct ptp_clock_info
*ptp
, struct timespec
*ts
)
6151 struct tg3
*tp
= container_of(ptp
, struct tg3
, ptp_info
);
6153 tg3_full_lock(tp
, 0);
6154 ns
= tg3_refclk_read(tp
);
6155 ns
+= tp
->ptp_adjust
;
6156 tg3_full_unlock(tp
);
6158 ts
->tv_sec
= div_u64_rem(ns
, 1000000000, &remainder
);
6159 ts
->tv_nsec
= remainder
;
6164 static int tg3_ptp_settime(struct ptp_clock_info
*ptp
,
6165 const struct timespec
*ts
)
6168 struct tg3
*tp
= container_of(ptp
, struct tg3
, ptp_info
);
6170 ns
= timespec_to_ns(ts
);
6172 tg3_full_lock(tp
, 0);
6173 tg3_refclk_write(tp
, ns
);
6175 tg3_full_unlock(tp
);
6180 static int tg3_ptp_enable(struct ptp_clock_info
*ptp
,
6181 struct ptp_clock_request
*rq
, int on
)
6186 static const struct ptp_clock_info tg3_ptp_caps
= {
6187 .owner
= THIS_MODULE
,
6188 .name
= "tg3 clock",
6189 .max_adj
= 250000000,
6194 .adjfreq
= tg3_ptp_adjfreq
,
6195 .adjtime
= tg3_ptp_adjtime
,
6196 .gettime
= tg3_ptp_gettime
,
6197 .settime
= tg3_ptp_settime
,
6198 .enable
= tg3_ptp_enable
,
6201 static void tg3_hwclock_to_timestamp(struct tg3
*tp
, u64 hwclock
,
6202 struct skb_shared_hwtstamps
*timestamp
)
6204 memset(timestamp
, 0, sizeof(struct skb_shared_hwtstamps
));
6205 timestamp
->hwtstamp
= ns_to_ktime((hwclock
& TG3_TSTAMP_MASK
) +
6209 /* tp->lock must be held */
6210 static void tg3_ptp_init(struct tg3
*tp
)
6212 if (!tg3_flag(tp
, PTP_CAPABLE
))
6215 /* Initialize the hardware clock to the system time. */
6216 tg3_refclk_write(tp
, ktime_to_ns(ktime_get_real()));
6218 tp
->ptp_info
= tg3_ptp_caps
;
6221 /* tp->lock must be held */
6222 static void tg3_ptp_resume(struct tg3
*tp
)
6224 if (!tg3_flag(tp
, PTP_CAPABLE
))
6227 tg3_refclk_write(tp
, ktime_to_ns(ktime_get_real()) + tp
->ptp_adjust
);
6231 static void tg3_ptp_fini(struct tg3
*tp
)
6233 if (!tg3_flag(tp
, PTP_CAPABLE
) || !tp
->ptp_clock
)
6236 ptp_clock_unregister(tp
->ptp_clock
);
6237 tp
->ptp_clock
= NULL
;
6241 static inline int tg3_irq_sync(struct tg3
*tp
)
6243 return tp
->irq_sync
;
6246 static inline void tg3_rd32_loop(struct tg3
*tp
, u32
*dst
, u32 off
, u32 len
)
6250 dst
= (u32
*)((u8
*)dst
+ off
);
6251 for (i
= 0; i
< len
; i
+= sizeof(u32
))
6252 *dst
++ = tr32(off
+ i
);
6255 static void tg3_dump_legacy_regs(struct tg3
*tp
, u32
*regs
)
6257 tg3_rd32_loop(tp
, regs
, TG3PCI_VENDOR
, 0xb0);
6258 tg3_rd32_loop(tp
, regs
, MAILBOX_INTERRUPT_0
, 0x200);
6259 tg3_rd32_loop(tp
, regs
, MAC_MODE
, 0x4f0);
6260 tg3_rd32_loop(tp
, regs
, SNDDATAI_MODE
, 0xe0);
6261 tg3_rd32_loop(tp
, regs
, SNDDATAC_MODE
, 0x04);
6262 tg3_rd32_loop(tp
, regs
, SNDBDS_MODE
, 0x80);
6263 tg3_rd32_loop(tp
, regs
, SNDBDI_MODE
, 0x48);
6264 tg3_rd32_loop(tp
, regs
, SNDBDC_MODE
, 0x04);
6265 tg3_rd32_loop(tp
, regs
, RCVLPC_MODE
, 0x20);
6266 tg3_rd32_loop(tp
, regs
, RCVLPC_SELLST_BASE
, 0x15c);
6267 tg3_rd32_loop(tp
, regs
, RCVDBDI_MODE
, 0x0c);
6268 tg3_rd32_loop(tp
, regs
, RCVDBDI_JUMBO_BD
, 0x3c);
6269 tg3_rd32_loop(tp
, regs
, RCVDBDI_BD_PROD_IDX_0
, 0x44);
6270 tg3_rd32_loop(tp
, regs
, RCVDCC_MODE
, 0x04);
6271 tg3_rd32_loop(tp
, regs
, RCVBDI_MODE
, 0x20);
6272 tg3_rd32_loop(tp
, regs
, RCVCC_MODE
, 0x14);
6273 tg3_rd32_loop(tp
, regs
, RCVLSC_MODE
, 0x08);
6274 tg3_rd32_loop(tp
, regs
, MBFREE_MODE
, 0x08);
6275 tg3_rd32_loop(tp
, regs
, HOSTCC_MODE
, 0x100);
6277 if (tg3_flag(tp
, SUPPORT_MSIX
))
6278 tg3_rd32_loop(tp
, regs
, HOSTCC_RXCOL_TICKS_VEC1
, 0x180);
6280 tg3_rd32_loop(tp
, regs
, MEMARB_MODE
, 0x10);
6281 tg3_rd32_loop(tp
, regs
, BUFMGR_MODE
, 0x58);
6282 tg3_rd32_loop(tp
, regs
, RDMAC_MODE
, 0x08);
6283 tg3_rd32_loop(tp
, regs
, WDMAC_MODE
, 0x08);
6284 tg3_rd32_loop(tp
, regs
, RX_CPU_MODE
, 0x04);
6285 tg3_rd32_loop(tp
, regs
, RX_CPU_STATE
, 0x04);
6286 tg3_rd32_loop(tp
, regs
, RX_CPU_PGMCTR
, 0x04);
6287 tg3_rd32_loop(tp
, regs
, RX_CPU_HWBKPT
, 0x04);
6289 if (!tg3_flag(tp
, 5705_PLUS
)) {
6290 tg3_rd32_loop(tp
, regs
, TX_CPU_MODE
, 0x04);
6291 tg3_rd32_loop(tp
, regs
, TX_CPU_STATE
, 0x04);
6292 tg3_rd32_loop(tp
, regs
, TX_CPU_PGMCTR
, 0x04);
6295 tg3_rd32_loop(tp
, regs
, GRCMBOX_INTERRUPT_0
, 0x110);
6296 tg3_rd32_loop(tp
, regs
, FTQ_RESET
, 0x120);
6297 tg3_rd32_loop(tp
, regs
, MSGINT_MODE
, 0x0c);
6298 tg3_rd32_loop(tp
, regs
, DMAC_MODE
, 0x04);
6299 tg3_rd32_loop(tp
, regs
, GRC_MODE
, 0x4c);
6301 if (tg3_flag(tp
, NVRAM
))
6302 tg3_rd32_loop(tp
, regs
, NVRAM_CMD
, 0x24);
6305 static void tg3_dump_state(struct tg3
*tp
)
6310 regs
= kzalloc(TG3_REG_BLK_SIZE
, GFP_ATOMIC
);
6314 if (tg3_flag(tp
, PCI_EXPRESS
)) {
6315 /* Read up to but not including private PCI registers */
6316 for (i
= 0; i
< TG3_PCIE_TLDLPL_PORT
; i
+= sizeof(u32
))
6317 regs
[i
/ sizeof(u32
)] = tr32(i
);
6319 tg3_dump_legacy_regs(tp
, regs
);
6321 for (i
= 0; i
< TG3_REG_BLK_SIZE
/ sizeof(u32
); i
+= 4) {
6322 if (!regs
[i
+ 0] && !regs
[i
+ 1] &&
6323 !regs
[i
+ 2] && !regs
[i
+ 3])
6326 netdev_err(tp
->dev
, "0x%08x: 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
6328 regs
[i
+ 0], regs
[i
+ 1], regs
[i
+ 2], regs
[i
+ 3]);
6333 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
6334 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
6336 /* SW status block */
6338 "%d: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
6340 tnapi
->hw_status
->status
,
6341 tnapi
->hw_status
->status_tag
,
6342 tnapi
->hw_status
->rx_jumbo_consumer
,
6343 tnapi
->hw_status
->rx_consumer
,
6344 tnapi
->hw_status
->rx_mini_consumer
,
6345 tnapi
->hw_status
->idx
[0].rx_producer
,
6346 tnapi
->hw_status
->idx
[0].tx_consumer
);
6349 "%d: NAPI info [%08x:%08x:(%04x:%04x:%04x):%04x:(%04x:%04x:%04x:%04x)]\n",
6351 tnapi
->last_tag
, tnapi
->last_irq_tag
,
6352 tnapi
->tx_prod
, tnapi
->tx_cons
, tnapi
->tx_pending
,
6354 tnapi
->prodring
.rx_std_prod_idx
,
6355 tnapi
->prodring
.rx_std_cons_idx
,
6356 tnapi
->prodring
.rx_jmb_prod_idx
,
6357 tnapi
->prodring
.rx_jmb_cons_idx
);
6361 /* This is called whenever we suspect that the system chipset is re-
6362 * ordering the sequence of MMIO to the tx send mailbox. The symptom
6363 * is bogus tx completions. We try to recover by setting the
6364 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
6367 static void tg3_tx_recover(struct tg3
*tp
)
6369 BUG_ON(tg3_flag(tp
, MBOX_WRITE_REORDER
) ||
6370 tp
->write32_tx_mbox
== tg3_write_indirect_mbox
);
6372 netdev_warn(tp
->dev
,
6373 "The system may be re-ordering memory-mapped I/O "
6374 "cycles to the network device, attempting to recover. "
6375 "Please report the problem to the driver maintainer "
6376 "and include system chipset information.\n");
6378 spin_lock(&tp
->lock
);
6379 tg3_flag_set(tp
, TX_RECOVERY_PENDING
);
6380 spin_unlock(&tp
->lock
);
6383 static inline u32
tg3_tx_avail(struct tg3_napi
*tnapi
)
6385 /* Tell compiler to fetch tx indices from memory. */
6387 return tnapi
->tx_pending
-
6388 ((tnapi
->tx_prod
- tnapi
->tx_cons
) & (TG3_TX_RING_SIZE
- 1));
6391 /* Tigon3 never reports partial packet sends. So we do not
6392 * need special logic to handle SKBs that have not had all
6393 * of their frags sent yet, like SunGEM does.
6395 static void tg3_tx(struct tg3_napi
*tnapi
)
6397 struct tg3
*tp
= tnapi
->tp
;
6398 u32 hw_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
6399 u32 sw_idx
= tnapi
->tx_cons
;
6400 struct netdev_queue
*txq
;
6401 int index
= tnapi
- tp
->napi
;
6402 unsigned int pkts_compl
= 0, bytes_compl
= 0;
6404 if (tg3_flag(tp
, ENABLE_TSS
))
6407 txq
= netdev_get_tx_queue(tp
->dev
, index
);
6409 while (sw_idx
!= hw_idx
) {
6410 struct tg3_tx_ring_info
*ri
= &tnapi
->tx_buffers
[sw_idx
];
6411 struct sk_buff
*skb
= ri
->skb
;
6414 if (unlikely(skb
== NULL
)) {
6419 if (tnapi
->tx_ring
[sw_idx
].len_flags
& TXD_FLAG_HWTSTAMP
) {
6420 struct skb_shared_hwtstamps timestamp
;
6421 u64 hwclock
= tr32(TG3_TX_TSTAMP_LSB
);
6422 hwclock
|= (u64
)tr32(TG3_TX_TSTAMP_MSB
) << 32;
6424 tg3_hwclock_to_timestamp(tp
, hwclock
, ×tamp
);
6426 skb_tstamp_tx(skb
, ×tamp
);
6429 pci_unmap_single(tp
->pdev
,
6430 dma_unmap_addr(ri
, mapping
),
6436 while (ri
->fragmented
) {
6437 ri
->fragmented
= false;
6438 sw_idx
= NEXT_TX(sw_idx
);
6439 ri
= &tnapi
->tx_buffers
[sw_idx
];
6442 sw_idx
= NEXT_TX(sw_idx
);
6444 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
6445 ri
= &tnapi
->tx_buffers
[sw_idx
];
6446 if (unlikely(ri
->skb
!= NULL
|| sw_idx
== hw_idx
))
6449 pci_unmap_page(tp
->pdev
,
6450 dma_unmap_addr(ri
, mapping
),
6451 skb_frag_size(&skb_shinfo(skb
)->frags
[i
]),
6454 while (ri
->fragmented
) {
6455 ri
->fragmented
= false;
6456 sw_idx
= NEXT_TX(sw_idx
);
6457 ri
= &tnapi
->tx_buffers
[sw_idx
];
6460 sw_idx
= NEXT_TX(sw_idx
);
6464 bytes_compl
+= skb
->len
;
6468 if (unlikely(tx_bug
)) {
6474 netdev_tx_completed_queue(txq
, pkts_compl
, bytes_compl
);
6476 tnapi
->tx_cons
= sw_idx
;
6478 /* Need to make the tx_cons update visible to tg3_start_xmit()
6479 * before checking for netif_queue_stopped(). Without the
6480 * memory barrier, there is a small possibility that tg3_start_xmit()
6481 * will miss it and cause the queue to be stopped forever.
6485 if (unlikely(netif_tx_queue_stopped(txq
) &&
6486 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))) {
6487 __netif_tx_lock(txq
, smp_processor_id());
6488 if (netif_tx_queue_stopped(txq
) &&
6489 (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
)))
6490 netif_tx_wake_queue(txq
);
6491 __netif_tx_unlock(txq
);
6495 static void tg3_frag_free(bool is_frag
, void *data
)
6498 put_page(virt_to_head_page(data
));
6503 static void tg3_rx_data_free(struct tg3
*tp
, struct ring_info
*ri
, u32 map_sz
)
6505 unsigned int skb_size
= SKB_DATA_ALIGN(map_sz
+ TG3_RX_OFFSET(tp
)) +
6506 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
6511 pci_unmap_single(tp
->pdev
, dma_unmap_addr(ri
, mapping
),
6512 map_sz
, PCI_DMA_FROMDEVICE
);
6513 tg3_frag_free(skb_size
<= PAGE_SIZE
, ri
->data
);
6518 /* Returns size of skb allocated or < 0 on error.
6520 * We only need to fill in the address because the other members
6521 * of the RX descriptor are invariant, see tg3_init_rings.
6523 * Note the purposeful assymetry of cpu vs. chip accesses. For
6524 * posting buffers we only dirty the first cache line of the RX
6525 * descriptor (containing the address). Whereas for the RX status
6526 * buffers the cpu only reads the last cacheline of the RX descriptor
6527 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
6529 static int tg3_alloc_rx_data(struct tg3
*tp
, struct tg3_rx_prodring_set
*tpr
,
6530 u32 opaque_key
, u32 dest_idx_unmasked
,
6531 unsigned int *frag_size
)
6533 struct tg3_rx_buffer_desc
*desc
;
6534 struct ring_info
*map
;
6537 int skb_size
, data_size
, dest_idx
;
6539 switch (opaque_key
) {
6540 case RXD_OPAQUE_RING_STD
:
6541 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
6542 desc
= &tpr
->rx_std
[dest_idx
];
6543 map
= &tpr
->rx_std_buffers
[dest_idx
];
6544 data_size
= tp
->rx_pkt_map_sz
;
6547 case RXD_OPAQUE_RING_JUMBO
:
6548 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
6549 desc
= &tpr
->rx_jmb
[dest_idx
].std
;
6550 map
= &tpr
->rx_jmb_buffers
[dest_idx
];
6551 data_size
= TG3_RX_JMB_MAP_SZ
;
6558 /* Do not overwrite any of the map or rp information
6559 * until we are sure we can commit to a new buffer.
6561 * Callers depend upon this behavior and assume that
6562 * we leave everything unchanged if we fail.
6564 skb_size
= SKB_DATA_ALIGN(data_size
+ TG3_RX_OFFSET(tp
)) +
6565 SKB_DATA_ALIGN(sizeof(struct skb_shared_info
));
6566 if (skb_size
<= PAGE_SIZE
) {
6567 data
= netdev_alloc_frag(skb_size
);
6568 *frag_size
= skb_size
;
6570 data
= kmalloc(skb_size
, GFP_ATOMIC
);
6576 mapping
= pci_map_single(tp
->pdev
,
6577 data
+ TG3_RX_OFFSET(tp
),
6579 PCI_DMA_FROMDEVICE
);
6580 if (unlikely(pci_dma_mapping_error(tp
->pdev
, mapping
))) {
6581 tg3_frag_free(skb_size
<= PAGE_SIZE
, data
);
6586 dma_unmap_addr_set(map
, mapping
, mapping
);
6588 desc
->addr_hi
= ((u64
)mapping
>> 32);
6589 desc
->addr_lo
= ((u64
)mapping
& 0xffffffff);
6594 /* We only need to move over in the address because the other
6595 * members of the RX descriptor are invariant. See notes above
6596 * tg3_alloc_rx_data for full details.
6598 static void tg3_recycle_rx(struct tg3_napi
*tnapi
,
6599 struct tg3_rx_prodring_set
*dpr
,
6600 u32 opaque_key
, int src_idx
,
6601 u32 dest_idx_unmasked
)
6603 struct tg3
*tp
= tnapi
->tp
;
6604 struct tg3_rx_buffer_desc
*src_desc
, *dest_desc
;
6605 struct ring_info
*src_map
, *dest_map
;
6606 struct tg3_rx_prodring_set
*spr
= &tp
->napi
[0].prodring
;
6609 switch (opaque_key
) {
6610 case RXD_OPAQUE_RING_STD
:
6611 dest_idx
= dest_idx_unmasked
& tp
->rx_std_ring_mask
;
6612 dest_desc
= &dpr
->rx_std
[dest_idx
];
6613 dest_map
= &dpr
->rx_std_buffers
[dest_idx
];
6614 src_desc
= &spr
->rx_std
[src_idx
];
6615 src_map
= &spr
->rx_std_buffers
[src_idx
];
6618 case RXD_OPAQUE_RING_JUMBO
:
6619 dest_idx
= dest_idx_unmasked
& tp
->rx_jmb_ring_mask
;
6620 dest_desc
= &dpr
->rx_jmb
[dest_idx
].std
;
6621 dest_map
= &dpr
->rx_jmb_buffers
[dest_idx
];
6622 src_desc
= &spr
->rx_jmb
[src_idx
].std
;
6623 src_map
= &spr
->rx_jmb_buffers
[src_idx
];
6630 dest_map
->data
= src_map
->data
;
6631 dma_unmap_addr_set(dest_map
, mapping
,
6632 dma_unmap_addr(src_map
, mapping
));
6633 dest_desc
->addr_hi
= src_desc
->addr_hi
;
6634 dest_desc
->addr_lo
= src_desc
->addr_lo
;
6636 /* Ensure that the update to the skb happens after the physical
6637 * addresses have been transferred to the new BD location.
6641 src_map
->data
= NULL
;
6644 /* The RX ring scheme is composed of multiple rings which post fresh
6645 * buffers to the chip, and one special ring the chip uses to report
6646 * status back to the host.
6648 * The special ring reports the status of received packets to the
6649 * host. The chip does not write into the original descriptor the
6650 * RX buffer was obtained from. The chip simply takes the original
6651 * descriptor as provided by the host, updates the status and length
6652 * field, then writes this into the next status ring entry.
6654 * Each ring the host uses to post buffers to the chip is described
6655 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
6656 * it is first placed into the on-chip ram. When the packet's length
6657 * is known, it walks down the TG3_BDINFO entries to select the ring.
6658 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
6659 * which is within the range of the new packet's length is chosen.
6661 * The "separate ring for rx status" scheme may sound queer, but it makes
6662 * sense from a cache coherency perspective. If only the host writes
6663 * to the buffer post rings, and only the chip writes to the rx status
6664 * rings, then cache lines never move beyond shared-modified state.
6665 * If both the host and chip were to write into the same ring, cache line
6666 * eviction could occur since both entities want it in an exclusive state.
6668 static int tg3_rx(struct tg3_napi
*tnapi
, int budget
)
6670 struct tg3
*tp
= tnapi
->tp
;
6671 u32 work_mask
, rx_std_posted
= 0;
6672 u32 std_prod_idx
, jmb_prod_idx
;
6673 u32 sw_idx
= tnapi
->rx_rcb_ptr
;
6676 struct tg3_rx_prodring_set
*tpr
= &tnapi
->prodring
;
6678 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
6680 * We need to order the read of hw_idx and the read of
6681 * the opaque cookie.
6686 std_prod_idx
= tpr
->rx_std_prod_idx
;
6687 jmb_prod_idx
= tpr
->rx_jmb_prod_idx
;
6688 while (sw_idx
!= hw_idx
&& budget
> 0) {
6689 struct ring_info
*ri
;
6690 struct tg3_rx_buffer_desc
*desc
= &tnapi
->rx_rcb
[sw_idx
];
6692 struct sk_buff
*skb
;
6693 dma_addr_t dma_addr
;
6694 u32 opaque_key
, desc_idx
, *post_ptr
;
6698 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
6699 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
6700 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
6701 ri
= &tp
->napi
[0].prodring
.rx_std_buffers
[desc_idx
];
6702 dma_addr
= dma_unmap_addr(ri
, mapping
);
6704 post_ptr
= &std_prod_idx
;
6706 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
6707 ri
= &tp
->napi
[0].prodring
.rx_jmb_buffers
[desc_idx
];
6708 dma_addr
= dma_unmap_addr(ri
, mapping
);
6710 post_ptr
= &jmb_prod_idx
;
6712 goto next_pkt_nopost
;
6714 work_mask
|= opaque_key
;
6716 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
6717 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
)) {
6719 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
6720 desc_idx
, *post_ptr
);
6722 /* Other statistics kept track of by card. */
6727 prefetch(data
+ TG3_RX_OFFSET(tp
));
6728 len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
) -
6731 if ((desc
->type_flags
& RXD_FLAG_PTPSTAT_MASK
) ==
6732 RXD_FLAG_PTPSTAT_PTPV1
||
6733 (desc
->type_flags
& RXD_FLAG_PTPSTAT_MASK
) ==
6734 RXD_FLAG_PTPSTAT_PTPV2
) {
6735 tstamp
= tr32(TG3_RX_TSTAMP_LSB
);
6736 tstamp
|= (u64
)tr32(TG3_RX_TSTAMP_MSB
) << 32;
6739 if (len
> TG3_RX_COPY_THRESH(tp
)) {
6741 unsigned int frag_size
;
6743 skb_size
= tg3_alloc_rx_data(tp
, tpr
, opaque_key
,
6744 *post_ptr
, &frag_size
);
6748 pci_unmap_single(tp
->pdev
, dma_addr
, skb_size
,
6749 PCI_DMA_FROMDEVICE
);
6751 skb
= build_skb(data
, frag_size
);
6753 tg3_frag_free(frag_size
!= 0, data
);
6754 goto drop_it_no_recycle
;
6756 skb_reserve(skb
, TG3_RX_OFFSET(tp
));
6757 /* Ensure that the update to the data happens
6758 * after the usage of the old DMA mapping.
6765 tg3_recycle_rx(tnapi
, tpr
, opaque_key
,
6766 desc_idx
, *post_ptr
);
6768 skb
= netdev_alloc_skb(tp
->dev
,
6769 len
+ TG3_RAW_IP_ALIGN
);
6771 goto drop_it_no_recycle
;
6773 skb_reserve(skb
, TG3_RAW_IP_ALIGN
);
6774 pci_dma_sync_single_for_cpu(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
6776 data
+ TG3_RX_OFFSET(tp
),
6778 pci_dma_sync_single_for_device(tp
->pdev
, dma_addr
, len
, PCI_DMA_FROMDEVICE
);
6783 tg3_hwclock_to_timestamp(tp
, tstamp
,
6784 skb_hwtstamps(skb
));
6786 if ((tp
->dev
->features
& NETIF_F_RXCSUM
) &&
6787 (desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
6788 (((desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
6789 >> RXD_TCPCSUM_SHIFT
) == 0xffff))
6790 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
6792 skb_checksum_none_assert(skb
);
6794 skb
->protocol
= eth_type_trans(skb
, tp
->dev
);
6796 if (len
> (tp
->dev
->mtu
+ ETH_HLEN
) &&
6797 skb
->protocol
!= htons(ETH_P_8021Q
)) {
6799 goto drop_it_no_recycle
;
6802 if (desc
->type_flags
& RXD_FLAG_VLAN
&&
6803 !(tp
->rx_mode
& RX_MODE_KEEP_VLAN_TAG
))
6804 __vlan_hwaccel_put_tag(skb
, htons(ETH_P_8021Q
),
6805 desc
->err_vlan
& RXD_VLAN_MASK
);
6807 napi_gro_receive(&tnapi
->napi
, skb
);
6815 if (unlikely(rx_std_posted
>= tp
->rx_std_max_post
)) {
6816 tpr
->rx_std_prod_idx
= std_prod_idx
&
6817 tp
->rx_std_ring_mask
;
6818 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
6819 tpr
->rx_std_prod_idx
);
6820 work_mask
&= ~RXD_OPAQUE_RING_STD
;
6825 sw_idx
&= tp
->rx_ret_ring_mask
;
6827 /* Refresh hw_idx to see if there is new work */
6828 if (sw_idx
== hw_idx
) {
6829 hw_idx
= *(tnapi
->rx_rcb_prod_idx
);
6834 /* ACK the status ring. */
6835 tnapi
->rx_rcb_ptr
= sw_idx
;
6836 tw32_rx_mbox(tnapi
->consmbox
, sw_idx
);
6838 /* Refill RX ring(s). */
6839 if (!tg3_flag(tp
, ENABLE_RSS
)) {
6840 /* Sync BD data before updating mailbox */
6843 if (work_mask
& RXD_OPAQUE_RING_STD
) {
6844 tpr
->rx_std_prod_idx
= std_prod_idx
&
6845 tp
->rx_std_ring_mask
;
6846 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
6847 tpr
->rx_std_prod_idx
);
6849 if (work_mask
& RXD_OPAQUE_RING_JUMBO
) {
6850 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
&
6851 tp
->rx_jmb_ring_mask
;
6852 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
6853 tpr
->rx_jmb_prod_idx
);
6856 } else if (work_mask
) {
6857 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
6858 * updated before the producer indices can be updated.
6862 tpr
->rx_std_prod_idx
= std_prod_idx
& tp
->rx_std_ring_mask
;
6863 tpr
->rx_jmb_prod_idx
= jmb_prod_idx
& tp
->rx_jmb_ring_mask
;
6865 if (tnapi
!= &tp
->napi
[1]) {
6866 tp
->rx_refill
= true;
6867 napi_schedule(&tp
->napi
[1].napi
);
6874 static void tg3_poll_link(struct tg3
*tp
)
6876 /* handle link change and other phy events */
6877 if (!(tg3_flag(tp
, USE_LINKCHG_REG
) || tg3_flag(tp
, POLL_SERDES
))) {
6878 struct tg3_hw_status
*sblk
= tp
->napi
[0].hw_status
;
6880 if (sblk
->status
& SD_STATUS_LINK_CHG
) {
6881 sblk
->status
= SD_STATUS_UPDATED
|
6882 (sblk
->status
& ~SD_STATUS_LINK_CHG
);
6883 spin_lock(&tp
->lock
);
6884 if (tg3_flag(tp
, USE_PHYLIB
)) {
6886 (MAC_STATUS_SYNC_CHANGED
|
6887 MAC_STATUS_CFG_CHANGED
|
6888 MAC_STATUS_MI_COMPLETION
|
6889 MAC_STATUS_LNKSTATE_CHANGED
));
6892 tg3_setup_phy(tp
, false);
6893 spin_unlock(&tp
->lock
);
6898 static int tg3_rx_prodring_xfer(struct tg3
*tp
,
6899 struct tg3_rx_prodring_set
*dpr
,
6900 struct tg3_rx_prodring_set
*spr
)
6902 u32 si
, di
, cpycnt
, src_prod_idx
;
6906 src_prod_idx
= spr
->rx_std_prod_idx
;
6908 /* Make sure updates to the rx_std_buffers[] entries and the
6909 * standard producer index are seen in the correct order.
6913 if (spr
->rx_std_cons_idx
== src_prod_idx
)
6916 if (spr
->rx_std_cons_idx
< src_prod_idx
)
6917 cpycnt
= src_prod_idx
- spr
->rx_std_cons_idx
;
6919 cpycnt
= tp
->rx_std_ring_mask
+ 1 -
6920 spr
->rx_std_cons_idx
;
6922 cpycnt
= min(cpycnt
,
6923 tp
->rx_std_ring_mask
+ 1 - dpr
->rx_std_prod_idx
);
6925 si
= spr
->rx_std_cons_idx
;
6926 di
= dpr
->rx_std_prod_idx
;
6928 for (i
= di
; i
< di
+ cpycnt
; i
++) {
6929 if (dpr
->rx_std_buffers
[i
].data
) {
6939 /* Ensure that updates to the rx_std_buffers ring and the
6940 * shadowed hardware producer ring from tg3_recycle_skb() are
6941 * ordered correctly WRT the skb check above.
6945 memcpy(&dpr
->rx_std_buffers
[di
],
6946 &spr
->rx_std_buffers
[si
],
6947 cpycnt
* sizeof(struct ring_info
));
6949 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
6950 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
6951 sbd
= &spr
->rx_std
[si
];
6952 dbd
= &dpr
->rx_std
[di
];
6953 dbd
->addr_hi
= sbd
->addr_hi
;
6954 dbd
->addr_lo
= sbd
->addr_lo
;
6957 spr
->rx_std_cons_idx
= (spr
->rx_std_cons_idx
+ cpycnt
) &
6958 tp
->rx_std_ring_mask
;
6959 dpr
->rx_std_prod_idx
= (dpr
->rx_std_prod_idx
+ cpycnt
) &
6960 tp
->rx_std_ring_mask
;
6964 src_prod_idx
= spr
->rx_jmb_prod_idx
;
6966 /* Make sure updates to the rx_jmb_buffers[] entries and
6967 * the jumbo producer index are seen in the correct order.
6971 if (spr
->rx_jmb_cons_idx
== src_prod_idx
)
6974 if (spr
->rx_jmb_cons_idx
< src_prod_idx
)
6975 cpycnt
= src_prod_idx
- spr
->rx_jmb_cons_idx
;
6977 cpycnt
= tp
->rx_jmb_ring_mask
+ 1 -
6978 spr
->rx_jmb_cons_idx
;
6980 cpycnt
= min(cpycnt
,
6981 tp
->rx_jmb_ring_mask
+ 1 - dpr
->rx_jmb_prod_idx
);
6983 si
= spr
->rx_jmb_cons_idx
;
6984 di
= dpr
->rx_jmb_prod_idx
;
6986 for (i
= di
; i
< di
+ cpycnt
; i
++) {
6987 if (dpr
->rx_jmb_buffers
[i
].data
) {
6997 /* Ensure that updates to the rx_jmb_buffers ring and the
6998 * shadowed hardware producer ring from tg3_recycle_skb() are
6999 * ordered correctly WRT the skb check above.
7003 memcpy(&dpr
->rx_jmb_buffers
[di
],
7004 &spr
->rx_jmb_buffers
[si
],
7005 cpycnt
* sizeof(struct ring_info
));
7007 for (i
= 0; i
< cpycnt
; i
++, di
++, si
++) {
7008 struct tg3_rx_buffer_desc
*sbd
, *dbd
;
7009 sbd
= &spr
->rx_jmb
[si
].std
;
7010 dbd
= &dpr
->rx_jmb
[di
].std
;
7011 dbd
->addr_hi
= sbd
->addr_hi
;
7012 dbd
->addr_lo
= sbd
->addr_lo
;
7015 spr
->rx_jmb_cons_idx
= (spr
->rx_jmb_cons_idx
+ cpycnt
) &
7016 tp
->rx_jmb_ring_mask
;
7017 dpr
->rx_jmb_prod_idx
= (dpr
->rx_jmb_prod_idx
+ cpycnt
) &
7018 tp
->rx_jmb_ring_mask
;
7024 static int tg3_poll_work(struct tg3_napi
*tnapi
, int work_done
, int budget
)
7026 struct tg3
*tp
= tnapi
->tp
;
7028 /* run TX completion thread */
7029 if (tnapi
->hw_status
->idx
[0].tx_consumer
!= tnapi
->tx_cons
) {
7031 if (unlikely(tg3_flag(tp
, TX_RECOVERY_PENDING
)))
7035 if (!tnapi
->rx_rcb_prod_idx
)
7038 /* run RX thread, within the bounds set by NAPI.
7039 * All RX "locking" is done by ensuring outside
7040 * code synchronizes with tg3->napi.poll()
7042 if (*(tnapi
->rx_rcb_prod_idx
) != tnapi
->rx_rcb_ptr
)
7043 work_done
+= tg3_rx(tnapi
, budget
- work_done
);
7045 if (tg3_flag(tp
, ENABLE_RSS
) && tnapi
== &tp
->napi
[1]) {
7046 struct tg3_rx_prodring_set
*dpr
= &tp
->napi
[0].prodring
;
7048 u32 std_prod_idx
= dpr
->rx_std_prod_idx
;
7049 u32 jmb_prod_idx
= dpr
->rx_jmb_prod_idx
;
7051 tp
->rx_refill
= false;
7052 for (i
= 1; i
<= tp
->rxq_cnt
; i
++)
7053 err
|= tg3_rx_prodring_xfer(tp
, dpr
,
7054 &tp
->napi
[i
].prodring
);
7058 if (std_prod_idx
!= dpr
->rx_std_prod_idx
)
7059 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
,
7060 dpr
->rx_std_prod_idx
);
7062 if (jmb_prod_idx
!= dpr
->rx_jmb_prod_idx
)
7063 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
,
7064 dpr
->rx_jmb_prod_idx
);
7069 tw32_f(HOSTCC_MODE
, tp
->coal_now
);
7075 static inline void tg3_reset_task_schedule(struct tg3
*tp
)
7077 if (!test_and_set_bit(TG3_FLAG_RESET_TASK_PENDING
, tp
->tg3_flags
))
7078 schedule_work(&tp
->reset_task
);
7081 static inline void tg3_reset_task_cancel(struct tg3
*tp
)
7083 cancel_work_sync(&tp
->reset_task
);
7084 tg3_flag_clear(tp
, RESET_TASK_PENDING
);
7085 tg3_flag_clear(tp
, TX_RECOVERY_PENDING
);
7088 static int tg3_poll_msix(struct napi_struct
*napi
, int budget
)
7090 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
7091 struct tg3
*tp
= tnapi
->tp
;
7093 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7096 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
7098 if (unlikely(tg3_flag(tp
, TX_RECOVERY_PENDING
)))
7101 if (unlikely(work_done
>= budget
))
7104 /* tp->last_tag is used in tg3_int_reenable() below
7105 * to tell the hw how much work has been processed,
7106 * so we must read it before checking for more work.
7108 tnapi
->last_tag
= sblk
->status_tag
;
7109 tnapi
->last_irq_tag
= tnapi
->last_tag
;
7112 /* check for RX/TX work to do */
7113 if (likely(sblk
->idx
[0].tx_consumer
== tnapi
->tx_cons
&&
7114 *(tnapi
->rx_rcb_prod_idx
) == tnapi
->rx_rcb_ptr
)) {
7116 /* This test here is not race free, but will reduce
7117 * the number of interrupts by looping again.
7119 if (tnapi
== &tp
->napi
[1] && tp
->rx_refill
)
7122 napi_complete(napi
);
7123 /* Reenable interrupts. */
7124 tw32_mailbox(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
7126 /* This test here is synchronized by napi_schedule()
7127 * and napi_complete() to close the race condition.
7129 if (unlikely(tnapi
== &tp
->napi
[1] && tp
->rx_refill
)) {
7130 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
7131 HOSTCC_MODE_ENABLE
|
7142 /* work_done is guaranteed to be less than budget. */
7143 napi_complete(napi
);
7144 tg3_reset_task_schedule(tp
);
7148 static void tg3_process_error(struct tg3
*tp
)
7151 bool real_error
= false;
7153 if (tg3_flag(tp
, ERROR_PROCESSED
))
7156 /* Check Flow Attention register */
7157 val
= tr32(HOSTCC_FLOW_ATTN
);
7158 if (val
& ~HOSTCC_FLOW_ATTN_MBUF_LWM
) {
7159 netdev_err(tp
->dev
, "FLOW Attention error. Resetting chip.\n");
7163 if (tr32(MSGINT_STATUS
) & ~MSGINT_STATUS_MSI_REQ
) {
7164 netdev_err(tp
->dev
, "MSI Status error. Resetting chip.\n");
7168 if (tr32(RDMAC_STATUS
) || tr32(WDMAC_STATUS
)) {
7169 netdev_err(tp
->dev
, "DMA Status error. Resetting chip.\n");
7178 tg3_flag_set(tp
, ERROR_PROCESSED
);
7179 tg3_reset_task_schedule(tp
);
7182 static int tg3_poll(struct napi_struct
*napi
, int budget
)
7184 struct tg3_napi
*tnapi
= container_of(napi
, struct tg3_napi
, napi
);
7185 struct tg3
*tp
= tnapi
->tp
;
7187 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7190 if (sblk
->status
& SD_STATUS_ERROR
)
7191 tg3_process_error(tp
);
7195 work_done
= tg3_poll_work(tnapi
, work_done
, budget
);
7197 if (unlikely(tg3_flag(tp
, TX_RECOVERY_PENDING
)))
7200 if (unlikely(work_done
>= budget
))
7203 if (tg3_flag(tp
, TAGGED_STATUS
)) {
7204 /* tp->last_tag is used in tg3_int_reenable() below
7205 * to tell the hw how much work has been processed,
7206 * so we must read it before checking for more work.
7208 tnapi
->last_tag
= sblk
->status_tag
;
7209 tnapi
->last_irq_tag
= tnapi
->last_tag
;
7212 sblk
->status
&= ~SD_STATUS_UPDATED
;
7214 if (likely(!tg3_has_work(tnapi
))) {
7215 napi_complete(napi
);
7216 tg3_int_reenable(tnapi
);
7224 /* work_done is guaranteed to be less than budget. */
7225 napi_complete(napi
);
7226 tg3_reset_task_schedule(tp
);
7230 static void tg3_napi_disable(struct tg3
*tp
)
7234 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--)
7235 napi_disable(&tp
->napi
[i
].napi
);
7238 static void tg3_napi_enable(struct tg3
*tp
)
7242 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7243 napi_enable(&tp
->napi
[i
].napi
);
7246 static void tg3_napi_init(struct tg3
*tp
)
7250 netif_napi_add(tp
->dev
, &tp
->napi
[0].napi
, tg3_poll
, 64);
7251 for (i
= 1; i
< tp
->irq_cnt
; i
++)
7252 netif_napi_add(tp
->dev
, &tp
->napi
[i
].napi
, tg3_poll_msix
, 64);
7255 static void tg3_napi_fini(struct tg3
*tp
)
7259 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7260 netif_napi_del(&tp
->napi
[i
].napi
);
7263 static inline void tg3_netif_stop(struct tg3
*tp
)
7265 tp
->dev
->trans_start
= jiffies
; /* prevent tx timeout */
7266 tg3_napi_disable(tp
);
7267 netif_carrier_off(tp
->dev
);
7268 netif_tx_disable(tp
->dev
);
7271 /* tp->lock must be held */
7272 static inline void tg3_netif_start(struct tg3
*tp
)
7276 /* NOTE: unconditional netif_tx_wake_all_queues is only
7277 * appropriate so long as all callers are assured to
7278 * have free tx slots (such as after tg3_init_hw)
7280 netif_tx_wake_all_queues(tp
->dev
);
7283 netif_carrier_on(tp
->dev
);
7285 tg3_napi_enable(tp
);
7286 tp
->napi
[0].hw_status
->status
|= SD_STATUS_UPDATED
;
7287 tg3_enable_ints(tp
);
7290 static void tg3_irq_quiesce(struct tg3
*tp
)
7294 BUG_ON(tp
->irq_sync
);
7299 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7300 synchronize_irq(tp
->napi
[i
].irq_vec
);
7303 /* Fully shutdown all tg3 driver activity elsewhere in the system.
7304 * If irq_sync is non-zero, then the IRQ handler must be synchronized
7305 * with as well. Most of the time, this is not necessary except when
7306 * shutting down the device.
7308 static inline void tg3_full_lock(struct tg3
*tp
, int irq_sync
)
7310 spin_lock_bh(&tp
->lock
);
7312 tg3_irq_quiesce(tp
);
7315 static inline void tg3_full_unlock(struct tg3
*tp
)
7317 spin_unlock_bh(&tp
->lock
);
7320 /* One-shot MSI handler - Chip automatically disables interrupt
7321 * after sending MSI so driver doesn't have to do it.
7323 static irqreturn_t
tg3_msi_1shot(int irq
, void *dev_id
)
7325 struct tg3_napi
*tnapi
= dev_id
;
7326 struct tg3
*tp
= tnapi
->tp
;
7328 prefetch(tnapi
->hw_status
);
7330 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
7332 if (likely(!tg3_irq_sync(tp
)))
7333 napi_schedule(&tnapi
->napi
);
7338 /* MSI ISR - No need to check for interrupt sharing and no need to
7339 * flush status block and interrupt mailbox. PCI ordering rules
7340 * guarantee that MSI will arrive after the status block.
7342 static irqreturn_t
tg3_msi(int irq
, void *dev_id
)
7344 struct tg3_napi
*tnapi
= dev_id
;
7345 struct tg3
*tp
= tnapi
->tp
;
7347 prefetch(tnapi
->hw_status
);
7349 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
7351 * Writing any value to intr-mbox-0 clears PCI INTA# and
7352 * chip-internal interrupt pending events.
7353 * Writing non-zero to intr-mbox-0 additional tells the
7354 * NIC to stop sending us irqs, engaging "in-intr-handler"
7357 tw32_mailbox(tnapi
->int_mbox
, 0x00000001);
7358 if (likely(!tg3_irq_sync(tp
)))
7359 napi_schedule(&tnapi
->napi
);
7361 return IRQ_RETVAL(1);
7364 static irqreturn_t
tg3_interrupt(int irq
, void *dev_id
)
7366 struct tg3_napi
*tnapi
= dev_id
;
7367 struct tg3
*tp
= tnapi
->tp
;
7368 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7369 unsigned int handled
= 1;
7371 /* In INTx mode, it is possible for the interrupt to arrive at
7372 * the CPU before the status block posted prior to the interrupt.
7373 * Reading the PCI State register will confirm whether the
7374 * interrupt is ours and will flush the status block.
7376 if (unlikely(!(sblk
->status
& SD_STATUS_UPDATED
))) {
7377 if (tg3_flag(tp
, CHIP_RESETTING
) ||
7378 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
7385 * Writing any value to intr-mbox-0 clears PCI INTA# and
7386 * chip-internal interrupt pending events.
7387 * Writing non-zero to intr-mbox-0 additional tells the
7388 * NIC to stop sending us irqs, engaging "in-intr-handler"
7391 * Flush the mailbox to de-assert the IRQ immediately to prevent
7392 * spurious interrupts. The flush impacts performance but
7393 * excessive spurious interrupts can be worse in some cases.
7395 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
7396 if (tg3_irq_sync(tp
))
7398 sblk
->status
&= ~SD_STATUS_UPDATED
;
7399 if (likely(tg3_has_work(tnapi
))) {
7400 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
7401 napi_schedule(&tnapi
->napi
);
7403 /* No work, shared interrupt perhaps? re-enable
7404 * interrupts, and flush that PCI write
7406 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
,
7410 return IRQ_RETVAL(handled
);
7413 static irqreturn_t
tg3_interrupt_tagged(int irq
, void *dev_id
)
7415 struct tg3_napi
*tnapi
= dev_id
;
7416 struct tg3
*tp
= tnapi
->tp
;
7417 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7418 unsigned int handled
= 1;
7420 /* In INTx mode, it is possible for the interrupt to arrive at
7421 * the CPU before the status block posted prior to the interrupt.
7422 * Reading the PCI State register will confirm whether the
7423 * interrupt is ours and will flush the status block.
7425 if (unlikely(sblk
->status_tag
== tnapi
->last_irq_tag
)) {
7426 if (tg3_flag(tp
, CHIP_RESETTING
) ||
7427 (tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
7434 * writing any value to intr-mbox-0 clears PCI INTA# and
7435 * chip-internal interrupt pending events.
7436 * writing non-zero to intr-mbox-0 additional tells the
7437 * NIC to stop sending us irqs, engaging "in-intr-handler"
7440 * Flush the mailbox to de-assert the IRQ immediately to prevent
7441 * spurious interrupts. The flush impacts performance but
7442 * excessive spurious interrupts can be worse in some cases.
7444 tw32_mailbox_f(MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
, 0x00000001);
7447 * In a shared interrupt configuration, sometimes other devices'
7448 * interrupts will scream. We record the current status tag here
7449 * so that the above check can report that the screaming interrupts
7450 * are unhandled. Eventually they will be silenced.
7452 tnapi
->last_irq_tag
= sblk
->status_tag
;
7454 if (tg3_irq_sync(tp
))
7457 prefetch(&tnapi
->rx_rcb
[tnapi
->rx_rcb_ptr
]);
7459 napi_schedule(&tnapi
->napi
);
7462 return IRQ_RETVAL(handled
);
7465 /* ISR for interrupt test */
7466 static irqreturn_t
tg3_test_isr(int irq
, void *dev_id
)
7468 struct tg3_napi
*tnapi
= dev_id
;
7469 struct tg3
*tp
= tnapi
->tp
;
7470 struct tg3_hw_status
*sblk
= tnapi
->hw_status
;
7472 if ((sblk
->status
& SD_STATUS_UPDATED
) ||
7473 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_INT_NOT_ACTIVE
)) {
7474 tg3_disable_ints(tp
);
7475 return IRQ_RETVAL(1);
7477 return IRQ_RETVAL(0);
7480 #ifdef CONFIG_NET_POLL_CONTROLLER
7481 static void tg3_poll_controller(struct net_device
*dev
)
7484 struct tg3
*tp
= netdev_priv(dev
);
7486 if (tg3_irq_sync(tp
))
7489 for (i
= 0; i
< tp
->irq_cnt
; i
++)
7490 tg3_interrupt(tp
->napi
[i
].irq_vec
, &tp
->napi
[i
]);
7494 static void tg3_tx_timeout(struct net_device
*dev
)
7496 struct tg3
*tp
= netdev_priv(dev
);
7498 if (netif_msg_tx_err(tp
)) {
7499 netdev_err(dev
, "transmit timed out, resetting\n");
7503 tg3_reset_task_schedule(tp
);
7506 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
7507 static inline int tg3_4g_overflow_test(dma_addr_t mapping
, int len
)
7509 u32 base
= (u32
) mapping
& 0xffffffff;
7511 return (base
> 0xffffdcc0) && (base
+ len
+ 8 < base
);
7514 /* Test for DMA addresses > 40-bit */
7515 static inline int tg3_40bit_overflow_test(struct tg3
*tp
, dma_addr_t mapping
,
7518 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
7519 if (tg3_flag(tp
, 40BIT_DMA_BUG
))
7520 return ((u64
) mapping
+ len
) > DMA_BIT_MASK(40);
7527 static inline void tg3_tx_set_bd(struct tg3_tx_buffer_desc
*txbd
,
7528 dma_addr_t mapping
, u32 len
, u32 flags
,
7531 txbd
->addr_hi
= ((u64
) mapping
>> 32);
7532 txbd
->addr_lo
= ((u64
) mapping
& 0xffffffff);
7533 txbd
->len_flags
= (len
<< TXD_LEN_SHIFT
) | (flags
& 0x0000ffff);
7534 txbd
->vlan_tag
= (mss
<< TXD_MSS_SHIFT
) | (vlan
<< TXD_VLAN_TAG_SHIFT
);
7537 static bool tg3_tx_frag_set(struct tg3_napi
*tnapi
, u32
*entry
, u32
*budget
,
7538 dma_addr_t map
, u32 len
, u32 flags
,
7541 struct tg3
*tp
= tnapi
->tp
;
7544 if (tg3_flag(tp
, SHORT_DMA_BUG
) && len
<= 8)
7547 if (tg3_4g_overflow_test(map
, len
))
7550 if (tg3_40bit_overflow_test(tp
, map
, len
))
7553 if (tp
->dma_limit
) {
7554 u32 prvidx
= *entry
;
7555 u32 tmp_flag
= flags
& ~TXD_FLAG_END
;
7556 while (len
> tp
->dma_limit
&& *budget
) {
7557 u32 frag_len
= tp
->dma_limit
;
7558 len
-= tp
->dma_limit
;
7560 /* Avoid the 8byte DMA problem */
7562 len
+= tp
->dma_limit
/ 2;
7563 frag_len
= tp
->dma_limit
/ 2;
7566 tnapi
->tx_buffers
[*entry
].fragmented
= true;
7568 tg3_tx_set_bd(&tnapi
->tx_ring
[*entry
], map
,
7569 frag_len
, tmp_flag
, mss
, vlan
);
7572 *entry
= NEXT_TX(*entry
);
7579 tg3_tx_set_bd(&tnapi
->tx_ring
[*entry
], map
,
7580 len
, flags
, mss
, vlan
);
7582 *entry
= NEXT_TX(*entry
);
7585 tnapi
->tx_buffers
[prvidx
].fragmented
= false;
7589 tg3_tx_set_bd(&tnapi
->tx_ring
[*entry
], map
,
7590 len
, flags
, mss
, vlan
);
7591 *entry
= NEXT_TX(*entry
);
7597 static void tg3_tx_skb_unmap(struct tg3_napi
*tnapi
, u32 entry
, int last
)
7600 struct sk_buff
*skb
;
7601 struct tg3_tx_ring_info
*txb
= &tnapi
->tx_buffers
[entry
];
7606 pci_unmap_single(tnapi
->tp
->pdev
,
7607 dma_unmap_addr(txb
, mapping
),
7611 while (txb
->fragmented
) {
7612 txb
->fragmented
= false;
7613 entry
= NEXT_TX(entry
);
7614 txb
= &tnapi
->tx_buffers
[entry
];
7617 for (i
= 0; i
<= last
; i
++) {
7618 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
7620 entry
= NEXT_TX(entry
);
7621 txb
= &tnapi
->tx_buffers
[entry
];
7623 pci_unmap_page(tnapi
->tp
->pdev
,
7624 dma_unmap_addr(txb
, mapping
),
7625 skb_frag_size(frag
), PCI_DMA_TODEVICE
);
7627 while (txb
->fragmented
) {
7628 txb
->fragmented
= false;
7629 entry
= NEXT_TX(entry
);
7630 txb
= &tnapi
->tx_buffers
[entry
];
7635 /* Workaround 4GB and 40-bit hardware DMA bugs. */
7636 static int tigon3_dma_hwbug_workaround(struct tg3_napi
*tnapi
,
7637 struct sk_buff
**pskb
,
7638 u32
*entry
, u32
*budget
,
7639 u32 base_flags
, u32 mss
, u32 vlan
)
7641 struct tg3
*tp
= tnapi
->tp
;
7642 struct sk_buff
*new_skb
, *skb
= *pskb
;
7643 dma_addr_t new_addr
= 0;
7646 if (tg3_asic_rev(tp
) != ASIC_REV_5701
)
7647 new_skb
= skb_copy(skb
, GFP_ATOMIC
);
7649 int more_headroom
= 4 - ((unsigned long)skb
->data
& 3);
7651 new_skb
= skb_copy_expand(skb
,
7652 skb_headroom(skb
) + more_headroom
,
7653 skb_tailroom(skb
), GFP_ATOMIC
);
7659 /* New SKB is guaranteed to be linear. */
7660 new_addr
= pci_map_single(tp
->pdev
, new_skb
->data
, new_skb
->len
,
7662 /* Make sure the mapping succeeded */
7663 if (pci_dma_mapping_error(tp
->pdev
, new_addr
)) {
7664 dev_kfree_skb(new_skb
);
7667 u32 save_entry
= *entry
;
7669 base_flags
|= TXD_FLAG_END
;
7671 tnapi
->tx_buffers
[*entry
].skb
= new_skb
;
7672 dma_unmap_addr_set(&tnapi
->tx_buffers
[*entry
],
7675 if (tg3_tx_frag_set(tnapi
, entry
, budget
, new_addr
,
7676 new_skb
->len
, base_flags
,
7678 tg3_tx_skb_unmap(tnapi
, save_entry
, -1);
7679 dev_kfree_skb(new_skb
);
7690 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*, struct net_device
*);
7692 /* Use GSO to workaround a rare TSO bug that may be triggered when the
7693 * TSO header is greater than 80 bytes.
7695 static int tg3_tso_bug(struct tg3
*tp
, struct sk_buff
*skb
)
7697 struct sk_buff
*segs
, *nskb
;
7698 u32 frag_cnt_est
= skb_shinfo(skb
)->gso_segs
* 3;
7700 /* Estimate the number of fragments in the worst case */
7701 if (unlikely(tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)) {
7702 netif_stop_queue(tp
->dev
);
7704 /* netif_tx_stop_queue() must be done before checking
7705 * checking tx index in tg3_tx_avail() below, because in
7706 * tg3_tx(), we update tx index before checking for
7707 * netif_tx_queue_stopped().
7710 if (tg3_tx_avail(&tp
->napi
[0]) <= frag_cnt_est
)
7711 return NETDEV_TX_BUSY
;
7713 netif_wake_queue(tp
->dev
);
7716 segs
= skb_gso_segment(skb
, tp
->dev
->features
& ~NETIF_F_TSO
);
7718 goto tg3_tso_bug_end
;
7724 tg3_start_xmit(nskb
, tp
->dev
);
7730 return NETDEV_TX_OK
;
7733 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
7734 * support TG3_FLAG_HW_TSO_1 or firmware TSO only.
7736 static netdev_tx_t
tg3_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
7738 struct tg3
*tp
= netdev_priv(dev
);
7739 u32 len
, entry
, base_flags
, mss
, vlan
= 0;
7741 int i
= -1, would_hit_hwbug
;
7743 struct tg3_napi
*tnapi
;
7744 struct netdev_queue
*txq
;
7747 txq
= netdev_get_tx_queue(dev
, skb_get_queue_mapping(skb
));
7748 tnapi
= &tp
->napi
[skb_get_queue_mapping(skb
)];
7749 if (tg3_flag(tp
, ENABLE_TSS
))
7752 budget
= tg3_tx_avail(tnapi
);
7754 /* We are running in BH disabled context with netif_tx_lock
7755 * and TX reclaim runs via tp->napi.poll inside of a software
7756 * interrupt. Furthermore, IRQ processing runs lockless so we have
7757 * no IRQ context deadlocks to worry about either. Rejoice!
7759 if (unlikely(budget
<= (skb_shinfo(skb
)->nr_frags
+ 1))) {
7760 if (!netif_tx_queue_stopped(txq
)) {
7761 netif_tx_stop_queue(txq
);
7763 /* This is a hard error, log it. */
7765 "BUG! Tx Ring full when queue awake!\n");
7767 return NETDEV_TX_BUSY
;
7770 entry
= tnapi
->tx_prod
;
7772 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
7773 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
7775 mss
= skb_shinfo(skb
)->gso_size
;
7778 u32 tcp_opt_len
, hdr_len
;
7780 if (skb_header_cloned(skb
) &&
7781 pskb_expand_head(skb
, 0, 0, GFP_ATOMIC
))
7785 tcp_opt_len
= tcp_optlen(skb
);
7787 hdr_len
= skb_transport_offset(skb
) + tcp_hdrlen(skb
) - ETH_HLEN
;
7789 if (!skb_is_gso_v6(skb
)) {
7791 iph
->tot_len
= htons(mss
+ hdr_len
);
7794 if (unlikely((ETH_HLEN
+ hdr_len
) > 80) &&
7795 tg3_flag(tp
, TSO_BUG
))
7796 return tg3_tso_bug(tp
, skb
);
7798 base_flags
|= (TXD_FLAG_CPU_PRE_DMA
|
7799 TXD_FLAG_CPU_POST_DMA
);
7801 if (tg3_flag(tp
, HW_TSO_1
) ||
7802 tg3_flag(tp
, HW_TSO_2
) ||
7803 tg3_flag(tp
, HW_TSO_3
)) {
7804 tcp_hdr(skb
)->check
= 0;
7805 base_flags
&= ~TXD_FLAG_TCPUDP_CSUM
;
7807 tcp_hdr(skb
)->check
= ~csum_tcpudp_magic(iph
->saddr
,
7812 if (tg3_flag(tp
, HW_TSO_3
)) {
7813 mss
|= (hdr_len
& 0xc) << 12;
7815 base_flags
|= 0x00000010;
7816 base_flags
|= (hdr_len
& 0x3e0) << 5;
7817 } else if (tg3_flag(tp
, HW_TSO_2
))
7818 mss
|= hdr_len
<< 9;
7819 else if (tg3_flag(tp
, HW_TSO_1
) ||
7820 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
7821 if (tcp_opt_len
|| iph
->ihl
> 5) {
7824 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
7825 mss
|= (tsflags
<< 11);
7828 if (tcp_opt_len
|| iph
->ihl
> 5) {
7831 tsflags
= (iph
->ihl
- 5) + (tcp_opt_len
>> 2);
7832 base_flags
|= tsflags
<< 12;
7837 if (tg3_flag(tp
, USE_JUMBO_BDFLAG
) &&
7838 !mss
&& skb
->len
> VLAN_ETH_FRAME_LEN
)
7839 base_flags
|= TXD_FLAG_JMB_PKT
;
7841 if (vlan_tx_tag_present(skb
)) {
7842 base_flags
|= TXD_FLAG_VLAN
;
7843 vlan
= vlan_tx_tag_get(skb
);
7846 if ((unlikely(skb_shinfo(skb
)->tx_flags
& SKBTX_HW_TSTAMP
)) &&
7847 tg3_flag(tp
, TX_TSTAMP_EN
)) {
7848 skb_shinfo(skb
)->tx_flags
|= SKBTX_IN_PROGRESS
;
7849 base_flags
|= TXD_FLAG_HWTSTAMP
;
7852 len
= skb_headlen(skb
);
7854 mapping
= pci_map_single(tp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
7855 if (pci_dma_mapping_error(tp
->pdev
, mapping
))
7859 tnapi
->tx_buffers
[entry
].skb
= skb
;
7860 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
, mapping
);
7862 would_hit_hwbug
= 0;
7864 if (tg3_flag(tp
, 5701_DMA_BUG
))
7865 would_hit_hwbug
= 1;
7867 if (tg3_tx_frag_set(tnapi
, &entry
, &budget
, mapping
, len
, base_flags
|
7868 ((skb_shinfo(skb
)->nr_frags
== 0) ? TXD_FLAG_END
: 0),
7870 would_hit_hwbug
= 1;
7871 } else if (skb_shinfo(skb
)->nr_frags
> 0) {
7874 if (!tg3_flag(tp
, HW_TSO_1
) &&
7875 !tg3_flag(tp
, HW_TSO_2
) &&
7876 !tg3_flag(tp
, HW_TSO_3
))
7879 /* Now loop through additional data
7880 * fragments, and queue them.
7882 last
= skb_shinfo(skb
)->nr_frags
- 1;
7883 for (i
= 0; i
<= last
; i
++) {
7884 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
7886 len
= skb_frag_size(frag
);
7887 mapping
= skb_frag_dma_map(&tp
->pdev
->dev
, frag
, 0,
7888 len
, DMA_TO_DEVICE
);
7890 tnapi
->tx_buffers
[entry
].skb
= NULL
;
7891 dma_unmap_addr_set(&tnapi
->tx_buffers
[entry
], mapping
,
7893 if (dma_mapping_error(&tp
->pdev
->dev
, mapping
))
7897 tg3_tx_frag_set(tnapi
, &entry
, &budget
, mapping
,
7899 ((i
== last
) ? TXD_FLAG_END
: 0),
7901 would_hit_hwbug
= 1;
7907 if (would_hit_hwbug
) {
7908 tg3_tx_skb_unmap(tnapi
, tnapi
->tx_prod
, i
);
7910 /* If the workaround fails due to memory/mapping
7911 * failure, silently drop this packet.
7913 entry
= tnapi
->tx_prod
;
7914 budget
= tg3_tx_avail(tnapi
);
7915 if (tigon3_dma_hwbug_workaround(tnapi
, &skb
, &entry
, &budget
,
7916 base_flags
, mss
, vlan
))
7920 skb_tx_timestamp(skb
);
7921 netdev_tx_sent_queue(txq
, skb
->len
);
7923 /* Sync BD data before updating mailbox */
7926 /* Packets are ready, update Tx producer idx local and on card. */
7927 tw32_tx_mbox(tnapi
->prodmbox
, entry
);
7929 tnapi
->tx_prod
= entry
;
7930 if (unlikely(tg3_tx_avail(tnapi
) <= (MAX_SKB_FRAGS
+ 1))) {
7931 netif_tx_stop_queue(txq
);
7933 /* netif_tx_stop_queue() must be done before checking
7934 * checking tx index in tg3_tx_avail() below, because in
7935 * tg3_tx(), we update tx index before checking for
7936 * netif_tx_queue_stopped().
7939 if (tg3_tx_avail(tnapi
) > TG3_TX_WAKEUP_THRESH(tnapi
))
7940 netif_tx_wake_queue(txq
);
7944 return NETDEV_TX_OK
;
7947 tg3_tx_skb_unmap(tnapi
, tnapi
->tx_prod
, --i
);
7948 tnapi
->tx_buffers
[tnapi
->tx_prod
].skb
= NULL
;
7953 return NETDEV_TX_OK
;
7956 static void tg3_mac_loopback(struct tg3
*tp
, bool enable
)
7959 tp
->mac_mode
&= ~(MAC_MODE_HALF_DUPLEX
|
7960 MAC_MODE_PORT_MODE_MASK
);
7962 tp
->mac_mode
|= MAC_MODE_PORT_INT_LPBACK
;
7964 if (!tg3_flag(tp
, 5705_PLUS
))
7965 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
7967 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
7968 tp
->mac_mode
|= MAC_MODE_PORT_MODE_MII
;
7970 tp
->mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
7972 tp
->mac_mode
&= ~MAC_MODE_PORT_INT_LPBACK
;
7974 if (tg3_flag(tp
, 5705_PLUS
) ||
7975 (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) ||
7976 tg3_asic_rev(tp
) == ASIC_REV_5700
)
7977 tp
->mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
7980 tw32(MAC_MODE
, tp
->mac_mode
);
7984 static int tg3_phy_lpbk_set(struct tg3
*tp
, u32 speed
, bool extlpbk
)
7986 u32 val
, bmcr
, mac_mode
, ptest
= 0;
7988 tg3_phy_toggle_apd(tp
, false);
7989 tg3_phy_toggle_automdix(tp
, false);
7991 if (extlpbk
&& tg3_phy_set_extloopbk(tp
))
7994 bmcr
= BMCR_FULLDPLX
;
7999 bmcr
|= BMCR_SPEED100
;
8003 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) {
8005 bmcr
|= BMCR_SPEED100
;
8008 bmcr
|= BMCR_SPEED1000
;
8013 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
8014 tg3_readphy(tp
, MII_CTRL1000
, &val
);
8015 val
|= CTL1000_AS_MASTER
|
8016 CTL1000_ENABLE_MASTER
;
8017 tg3_writephy(tp
, MII_CTRL1000
, val
);
8019 ptest
= MII_TG3_FET_PTEST_TRIM_SEL
|
8020 MII_TG3_FET_PTEST_TRIM_2
;
8021 tg3_writephy(tp
, MII_TG3_FET_PTEST
, ptest
);
8024 bmcr
|= BMCR_LOOPBACK
;
8026 tg3_writephy(tp
, MII_BMCR
, bmcr
);
8028 /* The write needs to be flushed for the FETs */
8029 if (tp
->phy_flags
& TG3_PHYFLG_IS_FET
)
8030 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
8034 if ((tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
8035 tg3_asic_rev(tp
) == ASIC_REV_5785
) {
8036 tg3_writephy(tp
, MII_TG3_FET_PTEST
, ptest
|
8037 MII_TG3_FET_PTEST_FRC_TX_LINK
|
8038 MII_TG3_FET_PTEST_FRC_TX_LOCK
);
8040 /* The write needs to be flushed for the AC131 */
8041 tg3_readphy(tp
, MII_TG3_FET_PTEST
, &val
);
8044 /* Reset to prevent losing 1st rx packet intermittently */
8045 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
8046 tg3_flag(tp
, 5780_CLASS
)) {
8047 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
8049 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8052 mac_mode
= tp
->mac_mode
&
8053 ~(MAC_MODE_PORT_MODE_MASK
| MAC_MODE_HALF_DUPLEX
);
8054 if (speed
== SPEED_1000
)
8055 mac_mode
|= MAC_MODE_PORT_MODE_GMII
;
8057 mac_mode
|= MAC_MODE_PORT_MODE_MII
;
8059 if (tg3_asic_rev(tp
) == ASIC_REV_5700
) {
8060 u32 masked_phy_id
= tp
->phy_id
& TG3_PHY_ID_MASK
;
8062 if (masked_phy_id
== TG3_PHY_ID_BCM5401
)
8063 mac_mode
&= ~MAC_MODE_LINK_POLARITY
;
8064 else if (masked_phy_id
== TG3_PHY_ID_BCM5411
)
8065 mac_mode
|= MAC_MODE_LINK_POLARITY
;
8067 tg3_writephy(tp
, MII_TG3_EXT_CTRL
,
8068 MII_TG3_EXT_CTRL_LNK3_LED_MODE
);
8071 tw32(MAC_MODE
, mac_mode
);
8077 static void tg3_set_loopback(struct net_device
*dev
, netdev_features_t features
)
8079 struct tg3
*tp
= netdev_priv(dev
);
8081 if (features
& NETIF_F_LOOPBACK
) {
8082 if (tp
->mac_mode
& MAC_MODE_PORT_INT_LPBACK
)
8085 spin_lock_bh(&tp
->lock
);
8086 tg3_mac_loopback(tp
, true);
8087 netif_carrier_on(tp
->dev
);
8088 spin_unlock_bh(&tp
->lock
);
8089 netdev_info(dev
, "Internal MAC loopback mode enabled.\n");
8091 if (!(tp
->mac_mode
& MAC_MODE_PORT_INT_LPBACK
))
8094 spin_lock_bh(&tp
->lock
);
8095 tg3_mac_loopback(tp
, false);
8096 /* Force link status check */
8097 tg3_setup_phy(tp
, true);
8098 spin_unlock_bh(&tp
->lock
);
8099 netdev_info(dev
, "Internal MAC loopback mode disabled.\n");
8103 static netdev_features_t
tg3_fix_features(struct net_device
*dev
,
8104 netdev_features_t features
)
8106 struct tg3
*tp
= netdev_priv(dev
);
8108 if (dev
->mtu
> ETH_DATA_LEN
&& tg3_flag(tp
, 5780_CLASS
))
8109 features
&= ~NETIF_F_ALL_TSO
;
8114 static int tg3_set_features(struct net_device
*dev
, netdev_features_t features
)
8116 netdev_features_t changed
= dev
->features
^ features
;
8118 if ((changed
& NETIF_F_LOOPBACK
) && netif_running(dev
))
8119 tg3_set_loopback(dev
, features
);
8124 static void tg3_rx_prodring_free(struct tg3
*tp
,
8125 struct tg3_rx_prodring_set
*tpr
)
8129 if (tpr
!= &tp
->napi
[0].prodring
) {
8130 for (i
= tpr
->rx_std_cons_idx
; i
!= tpr
->rx_std_prod_idx
;
8131 i
= (i
+ 1) & tp
->rx_std_ring_mask
)
8132 tg3_rx_data_free(tp
, &tpr
->rx_std_buffers
[i
],
8135 if (tg3_flag(tp
, JUMBO_CAPABLE
)) {
8136 for (i
= tpr
->rx_jmb_cons_idx
;
8137 i
!= tpr
->rx_jmb_prod_idx
;
8138 i
= (i
+ 1) & tp
->rx_jmb_ring_mask
) {
8139 tg3_rx_data_free(tp
, &tpr
->rx_jmb_buffers
[i
],
8147 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++)
8148 tg3_rx_data_free(tp
, &tpr
->rx_std_buffers
[i
],
8151 if (tg3_flag(tp
, JUMBO_CAPABLE
) && !tg3_flag(tp
, 5780_CLASS
)) {
8152 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++)
8153 tg3_rx_data_free(tp
, &tpr
->rx_jmb_buffers
[i
],
8158 /* Initialize rx rings for packet processing.
8160 * The chip has been shut down and the driver detached from
8161 * the networking, so no interrupts or new tx packets will
8162 * end up in the driver. tp->{tx,}lock are held and thus
8165 static int tg3_rx_prodring_alloc(struct tg3
*tp
,
8166 struct tg3_rx_prodring_set
*tpr
)
8168 u32 i
, rx_pkt_dma_sz
;
8170 tpr
->rx_std_cons_idx
= 0;
8171 tpr
->rx_std_prod_idx
= 0;
8172 tpr
->rx_jmb_cons_idx
= 0;
8173 tpr
->rx_jmb_prod_idx
= 0;
8175 if (tpr
!= &tp
->napi
[0].prodring
) {
8176 memset(&tpr
->rx_std_buffers
[0], 0,
8177 TG3_RX_STD_BUFF_RING_SIZE(tp
));
8178 if (tpr
->rx_jmb_buffers
)
8179 memset(&tpr
->rx_jmb_buffers
[0], 0,
8180 TG3_RX_JMB_BUFF_RING_SIZE(tp
));
8184 /* Zero out all descriptors. */
8185 memset(tpr
->rx_std
, 0, TG3_RX_STD_RING_BYTES(tp
));
8187 rx_pkt_dma_sz
= TG3_RX_STD_DMA_SZ
;
8188 if (tg3_flag(tp
, 5780_CLASS
) &&
8189 tp
->dev
->mtu
> ETH_DATA_LEN
)
8190 rx_pkt_dma_sz
= TG3_RX_JMB_DMA_SZ
;
8191 tp
->rx_pkt_map_sz
= TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz
);
8193 /* Initialize invariants of the rings, we only set this
8194 * stuff once. This works because the card does not
8195 * write into the rx buffer posting rings.
8197 for (i
= 0; i
<= tp
->rx_std_ring_mask
; i
++) {
8198 struct tg3_rx_buffer_desc
*rxd
;
8200 rxd
= &tpr
->rx_std
[i
];
8201 rxd
->idx_len
= rx_pkt_dma_sz
<< RXD_LEN_SHIFT
;
8202 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
);
8203 rxd
->opaque
= (RXD_OPAQUE_RING_STD
|
8204 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
8207 /* Now allocate fresh SKBs for each rx ring. */
8208 for (i
= 0; i
< tp
->rx_pending
; i
++) {
8209 unsigned int frag_size
;
8211 if (tg3_alloc_rx_data(tp
, tpr
, RXD_OPAQUE_RING_STD
, i
,
8213 netdev_warn(tp
->dev
,
8214 "Using a smaller RX standard ring. Only "
8215 "%d out of %d buffers were allocated "
8216 "successfully\n", i
, tp
->rx_pending
);
8224 if (!tg3_flag(tp
, JUMBO_CAPABLE
) || tg3_flag(tp
, 5780_CLASS
))
8227 memset(tpr
->rx_jmb
, 0, TG3_RX_JMB_RING_BYTES(tp
));
8229 if (!tg3_flag(tp
, JUMBO_RING_ENABLE
))
8232 for (i
= 0; i
<= tp
->rx_jmb_ring_mask
; i
++) {
8233 struct tg3_rx_buffer_desc
*rxd
;
8235 rxd
= &tpr
->rx_jmb
[i
].std
;
8236 rxd
->idx_len
= TG3_RX_JMB_DMA_SZ
<< RXD_LEN_SHIFT
;
8237 rxd
->type_flags
= (RXD_FLAG_END
<< RXD_FLAGS_SHIFT
) |
8239 rxd
->opaque
= (RXD_OPAQUE_RING_JUMBO
|
8240 (i
<< RXD_OPAQUE_INDEX_SHIFT
));
8243 for (i
= 0; i
< tp
->rx_jumbo_pending
; i
++) {
8244 unsigned int frag_size
;
8246 if (tg3_alloc_rx_data(tp
, tpr
, RXD_OPAQUE_RING_JUMBO
, i
,
8248 netdev_warn(tp
->dev
,
8249 "Using a smaller RX jumbo ring. Only %d "
8250 "out of %d buffers were allocated "
8251 "successfully\n", i
, tp
->rx_jumbo_pending
);
8254 tp
->rx_jumbo_pending
= i
;
8263 tg3_rx_prodring_free(tp
, tpr
);
8267 static void tg3_rx_prodring_fini(struct tg3
*tp
,
8268 struct tg3_rx_prodring_set
*tpr
)
8270 kfree(tpr
->rx_std_buffers
);
8271 tpr
->rx_std_buffers
= NULL
;
8272 kfree(tpr
->rx_jmb_buffers
);
8273 tpr
->rx_jmb_buffers
= NULL
;
8275 dma_free_coherent(&tp
->pdev
->dev
, TG3_RX_STD_RING_BYTES(tp
),
8276 tpr
->rx_std
, tpr
->rx_std_mapping
);
8280 dma_free_coherent(&tp
->pdev
->dev
, TG3_RX_JMB_RING_BYTES(tp
),
8281 tpr
->rx_jmb
, tpr
->rx_jmb_mapping
);
8286 static int tg3_rx_prodring_init(struct tg3
*tp
,
8287 struct tg3_rx_prodring_set
*tpr
)
8289 tpr
->rx_std_buffers
= kzalloc(TG3_RX_STD_BUFF_RING_SIZE(tp
),
8291 if (!tpr
->rx_std_buffers
)
8294 tpr
->rx_std
= dma_alloc_coherent(&tp
->pdev
->dev
,
8295 TG3_RX_STD_RING_BYTES(tp
),
8296 &tpr
->rx_std_mapping
,
8301 if (tg3_flag(tp
, JUMBO_CAPABLE
) && !tg3_flag(tp
, 5780_CLASS
)) {
8302 tpr
->rx_jmb_buffers
= kzalloc(TG3_RX_JMB_BUFF_RING_SIZE(tp
),
8304 if (!tpr
->rx_jmb_buffers
)
8307 tpr
->rx_jmb
= dma_alloc_coherent(&tp
->pdev
->dev
,
8308 TG3_RX_JMB_RING_BYTES(tp
),
8309 &tpr
->rx_jmb_mapping
,
8318 tg3_rx_prodring_fini(tp
, tpr
);
8322 /* Free up pending packets in all rx/tx rings.
8324 * The chip has been shut down and the driver detached from
8325 * the networking, so no interrupts or new tx packets will
8326 * end up in the driver. tp->{tx,}lock is not held and we are not
8327 * in an interrupt context and thus may sleep.
8329 static void tg3_free_rings(struct tg3
*tp
)
8333 for (j
= 0; j
< tp
->irq_cnt
; j
++) {
8334 struct tg3_napi
*tnapi
= &tp
->napi
[j
];
8336 tg3_rx_prodring_free(tp
, &tnapi
->prodring
);
8338 if (!tnapi
->tx_buffers
)
8341 for (i
= 0; i
< TG3_TX_RING_SIZE
; i
++) {
8342 struct sk_buff
*skb
= tnapi
->tx_buffers
[i
].skb
;
8347 tg3_tx_skb_unmap(tnapi
, i
,
8348 skb_shinfo(skb
)->nr_frags
- 1);
8350 dev_kfree_skb_any(skb
);
8352 netdev_tx_reset_queue(netdev_get_tx_queue(tp
->dev
, j
));
8356 /* Initialize tx/rx rings for packet processing.
8358 * The chip has been shut down and the driver detached from
8359 * the networking, so no interrupts or new tx packets will
8360 * end up in the driver. tp->{tx,}lock are held and thus
8363 static int tg3_init_rings(struct tg3
*tp
)
8367 /* Free up all the SKBs. */
8370 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8371 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8373 tnapi
->last_tag
= 0;
8374 tnapi
->last_irq_tag
= 0;
8375 tnapi
->hw_status
->status
= 0;
8376 tnapi
->hw_status
->status_tag
= 0;
8377 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
8382 memset(tnapi
->tx_ring
, 0, TG3_TX_RING_BYTES
);
8384 tnapi
->rx_rcb_ptr
= 0;
8386 memset(tnapi
->rx_rcb
, 0, TG3_RX_RCB_RING_BYTES(tp
));
8388 if (tg3_rx_prodring_alloc(tp
, &tnapi
->prodring
)) {
8397 static void tg3_mem_tx_release(struct tg3
*tp
)
8401 for (i
= 0; i
< tp
->irq_max
; i
++) {
8402 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8404 if (tnapi
->tx_ring
) {
8405 dma_free_coherent(&tp
->pdev
->dev
, TG3_TX_RING_BYTES
,
8406 tnapi
->tx_ring
, tnapi
->tx_desc_mapping
);
8407 tnapi
->tx_ring
= NULL
;
8410 kfree(tnapi
->tx_buffers
);
8411 tnapi
->tx_buffers
= NULL
;
8415 static int tg3_mem_tx_acquire(struct tg3
*tp
)
8418 struct tg3_napi
*tnapi
= &tp
->napi
[0];
8420 /* If multivector TSS is enabled, vector 0 does not handle
8421 * tx interrupts. Don't allocate any resources for it.
8423 if (tg3_flag(tp
, ENABLE_TSS
))
8426 for (i
= 0; i
< tp
->txq_cnt
; i
++, tnapi
++) {
8427 tnapi
->tx_buffers
= kzalloc(sizeof(struct tg3_tx_ring_info
) *
8428 TG3_TX_RING_SIZE
, GFP_KERNEL
);
8429 if (!tnapi
->tx_buffers
)
8432 tnapi
->tx_ring
= dma_alloc_coherent(&tp
->pdev
->dev
,
8434 &tnapi
->tx_desc_mapping
,
8436 if (!tnapi
->tx_ring
)
8443 tg3_mem_tx_release(tp
);
8447 static void tg3_mem_rx_release(struct tg3
*tp
)
8451 for (i
= 0; i
< tp
->irq_max
; i
++) {
8452 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8454 tg3_rx_prodring_fini(tp
, &tnapi
->prodring
);
8459 dma_free_coherent(&tp
->pdev
->dev
,
8460 TG3_RX_RCB_RING_BYTES(tp
),
8462 tnapi
->rx_rcb_mapping
);
8463 tnapi
->rx_rcb
= NULL
;
8467 static int tg3_mem_rx_acquire(struct tg3
*tp
)
8469 unsigned int i
, limit
;
8471 limit
= tp
->rxq_cnt
;
8473 /* If RSS is enabled, we need a (dummy) producer ring
8474 * set on vector zero. This is the true hw prodring.
8476 if (tg3_flag(tp
, ENABLE_RSS
))
8479 for (i
= 0; i
< limit
; i
++) {
8480 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8482 if (tg3_rx_prodring_init(tp
, &tnapi
->prodring
))
8485 /* If multivector RSS is enabled, vector 0
8486 * does not handle rx or tx interrupts.
8487 * Don't allocate any resources for it.
8489 if (!i
&& tg3_flag(tp
, ENABLE_RSS
))
8492 tnapi
->rx_rcb
= dma_alloc_coherent(&tp
->pdev
->dev
,
8493 TG3_RX_RCB_RING_BYTES(tp
),
8494 &tnapi
->rx_rcb_mapping
,
8495 GFP_KERNEL
| __GFP_ZERO
);
8503 tg3_mem_rx_release(tp
);
8508 * Must not be invoked with interrupt sources disabled and
8509 * the hardware shutdown down.
8511 static void tg3_free_consistent(struct tg3
*tp
)
8515 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8516 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8518 if (tnapi
->hw_status
) {
8519 dma_free_coherent(&tp
->pdev
->dev
, TG3_HW_STATUS_SIZE
,
8521 tnapi
->status_mapping
);
8522 tnapi
->hw_status
= NULL
;
8526 tg3_mem_rx_release(tp
);
8527 tg3_mem_tx_release(tp
);
8530 dma_free_coherent(&tp
->pdev
->dev
, sizeof(struct tg3_hw_stats
),
8531 tp
->hw_stats
, tp
->stats_mapping
);
8532 tp
->hw_stats
= NULL
;
8537 * Must not be invoked with interrupt sources disabled and
8538 * the hardware shutdown down. Can sleep.
8540 static int tg3_alloc_consistent(struct tg3
*tp
)
8544 tp
->hw_stats
= dma_alloc_coherent(&tp
->pdev
->dev
,
8545 sizeof(struct tg3_hw_stats
),
8547 GFP_KERNEL
| __GFP_ZERO
);
8551 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8552 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8553 struct tg3_hw_status
*sblk
;
8555 tnapi
->hw_status
= dma_alloc_coherent(&tp
->pdev
->dev
,
8557 &tnapi
->status_mapping
,
8558 GFP_KERNEL
| __GFP_ZERO
);
8559 if (!tnapi
->hw_status
)
8562 sblk
= tnapi
->hw_status
;
8564 if (tg3_flag(tp
, ENABLE_RSS
)) {
8565 u16
*prodptr
= NULL
;
8568 * When RSS is enabled, the status block format changes
8569 * slightly. The "rx_jumbo_consumer", "reserved",
8570 * and "rx_mini_consumer" members get mapped to the
8571 * other three rx return ring producer indexes.
8575 prodptr
= &sblk
->idx
[0].rx_producer
;
8578 prodptr
= &sblk
->rx_jumbo_consumer
;
8581 prodptr
= &sblk
->reserved
;
8584 prodptr
= &sblk
->rx_mini_consumer
;
8587 tnapi
->rx_rcb_prod_idx
= prodptr
;
8589 tnapi
->rx_rcb_prod_idx
= &sblk
->idx
[0].rx_producer
;
8593 if (tg3_mem_tx_acquire(tp
) || tg3_mem_rx_acquire(tp
))
8599 tg3_free_consistent(tp
);
8603 #define MAX_WAIT_CNT 1000
8605 /* To stop a block, clear the enable bit and poll till it
8606 * clears. tp->lock is held.
8608 static int tg3_stop_block(struct tg3
*tp
, unsigned long ofs
, u32 enable_bit
, bool silent
)
8613 if (tg3_flag(tp
, 5705_PLUS
)) {
8620 /* We can't enable/disable these bits of the
8621 * 5705/5750, just say success.
8634 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
8637 if ((val
& enable_bit
) == 0)
8641 if (i
== MAX_WAIT_CNT
&& !silent
) {
8642 dev_err(&tp
->pdev
->dev
,
8643 "tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
8651 /* tp->lock is held. */
8652 static int tg3_abort_hw(struct tg3
*tp
, bool silent
)
8656 tg3_disable_ints(tp
);
8658 tp
->rx_mode
&= ~RX_MODE_ENABLE
;
8659 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
8662 err
= tg3_stop_block(tp
, RCVBDI_MODE
, RCVBDI_MODE_ENABLE
, silent
);
8663 err
|= tg3_stop_block(tp
, RCVLPC_MODE
, RCVLPC_MODE_ENABLE
, silent
);
8664 err
|= tg3_stop_block(tp
, RCVLSC_MODE
, RCVLSC_MODE_ENABLE
, silent
);
8665 err
|= tg3_stop_block(tp
, RCVDBDI_MODE
, RCVDBDI_MODE_ENABLE
, silent
);
8666 err
|= tg3_stop_block(tp
, RCVDCC_MODE
, RCVDCC_MODE_ENABLE
, silent
);
8667 err
|= tg3_stop_block(tp
, RCVCC_MODE
, RCVCC_MODE_ENABLE
, silent
);
8669 err
|= tg3_stop_block(tp
, SNDBDS_MODE
, SNDBDS_MODE_ENABLE
, silent
);
8670 err
|= tg3_stop_block(tp
, SNDBDI_MODE
, SNDBDI_MODE_ENABLE
, silent
);
8671 err
|= tg3_stop_block(tp
, SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
, silent
);
8672 err
|= tg3_stop_block(tp
, RDMAC_MODE
, RDMAC_MODE_ENABLE
, silent
);
8673 err
|= tg3_stop_block(tp
, SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
, silent
);
8674 err
|= tg3_stop_block(tp
, DMAC_MODE
, DMAC_MODE_ENABLE
, silent
);
8675 err
|= tg3_stop_block(tp
, SNDBDC_MODE
, SNDBDC_MODE_ENABLE
, silent
);
8677 tp
->mac_mode
&= ~MAC_MODE_TDE_ENABLE
;
8678 tw32_f(MAC_MODE
, tp
->mac_mode
);
8681 tp
->tx_mode
&= ~TX_MODE_ENABLE
;
8682 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
8684 for (i
= 0; i
< MAX_WAIT_CNT
; i
++) {
8686 if (!(tr32(MAC_TX_MODE
) & TX_MODE_ENABLE
))
8689 if (i
>= MAX_WAIT_CNT
) {
8690 dev_err(&tp
->pdev
->dev
,
8691 "%s timed out, TX_MODE_ENABLE will not clear "
8692 "MAC_TX_MODE=%08x\n", __func__
, tr32(MAC_TX_MODE
));
8696 err
|= tg3_stop_block(tp
, HOSTCC_MODE
, HOSTCC_MODE_ENABLE
, silent
);
8697 err
|= tg3_stop_block(tp
, WDMAC_MODE
, WDMAC_MODE_ENABLE
, silent
);
8698 err
|= tg3_stop_block(tp
, MBFREE_MODE
, MBFREE_MODE_ENABLE
, silent
);
8700 tw32(FTQ_RESET
, 0xffffffff);
8701 tw32(FTQ_RESET
, 0x00000000);
8703 err
|= tg3_stop_block(tp
, BUFMGR_MODE
, BUFMGR_MODE_ENABLE
, silent
);
8704 err
|= tg3_stop_block(tp
, MEMARB_MODE
, MEMARB_MODE_ENABLE
, silent
);
8706 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8707 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8708 if (tnapi
->hw_status
)
8709 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
8715 /* Save PCI command register before chip reset */
8716 static void tg3_save_pci_state(struct tg3
*tp
)
8718 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &tp
->pci_cmd
);
8721 /* Restore PCI state after chip reset */
8722 static void tg3_restore_pci_state(struct tg3
*tp
)
8726 /* Re-enable indirect register accesses. */
8727 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
8728 tp
->misc_host_ctrl
);
8730 /* Set MAX PCI retry to zero. */
8731 val
= (PCISTATE_ROM_ENABLE
| PCISTATE_ROM_RETRY_ENABLE
);
8732 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5704_A0
&&
8733 tg3_flag(tp
, PCIX_MODE
))
8734 val
|= PCISTATE_RETRY_SAME_DMA
;
8735 /* Allow reads and writes to the APE register and memory space. */
8736 if (tg3_flag(tp
, ENABLE_APE
))
8737 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
8738 PCISTATE_ALLOW_APE_SHMEM_WR
|
8739 PCISTATE_ALLOW_APE_PSPACE_WR
;
8740 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, val
);
8742 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, tp
->pci_cmd
);
8744 if (!tg3_flag(tp
, PCI_EXPRESS
)) {
8745 pci_write_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
8746 tp
->pci_cacheline_sz
);
8747 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
8751 /* Make sure PCI-X relaxed ordering bit is clear. */
8752 if (tg3_flag(tp
, PCIX_MODE
)) {
8755 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8757 pcix_cmd
&= ~PCI_X_CMD_ERO
;
8758 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
8762 if (tg3_flag(tp
, 5780_CLASS
)) {
8764 /* Chip reset on 5780 will reset MSI enable bit,
8765 * so need to restore it.
8767 if (tg3_flag(tp
, USING_MSI
)) {
8770 pci_read_config_word(tp
->pdev
,
8771 tp
->msi_cap
+ PCI_MSI_FLAGS
,
8773 pci_write_config_word(tp
->pdev
,
8774 tp
->msi_cap
+ PCI_MSI_FLAGS
,
8775 ctrl
| PCI_MSI_FLAGS_ENABLE
);
8776 val
= tr32(MSGINT_MODE
);
8777 tw32(MSGINT_MODE
, val
| MSGINT_MODE_ENABLE
);
8782 /* tp->lock is held. */
8783 static int tg3_chip_reset(struct tg3
*tp
)
8786 void (*write_op
)(struct tg3
*, u32
, u32
);
8791 tg3_ape_lock(tp
, TG3_APE_LOCK_GRC
);
8793 /* No matching tg3_nvram_unlock() after this because
8794 * chip reset below will undo the nvram lock.
8796 tp
->nvram_lock_cnt
= 0;
8798 /* GRC_MISC_CFG core clock reset will clear the memory
8799 * enable bit in PCI register 4 and the MSI enable bit
8800 * on some chips, so we save relevant registers here.
8802 tg3_save_pci_state(tp
);
8804 if (tg3_asic_rev(tp
) == ASIC_REV_5752
||
8805 tg3_flag(tp
, 5755_PLUS
))
8806 tw32(GRC_FASTBOOT_PC
, 0);
8809 * We must avoid the readl() that normally takes place.
8810 * It locks machines, causes machine checks, and other
8811 * fun things. So, temporarily disable the 5701
8812 * hardware workaround, while we do the reset.
8814 write_op
= tp
->write32
;
8815 if (write_op
== tg3_write_flush_reg32
)
8816 tp
->write32
= tg3_write32
;
8818 /* Prevent the irq handler from reading or writing PCI registers
8819 * during chip reset when the memory enable bit in the PCI command
8820 * register may be cleared. The chip does not generate interrupt
8821 * at this time, but the irq handler may still be called due to irq
8822 * sharing or irqpoll.
8824 tg3_flag_set(tp
, CHIP_RESETTING
);
8825 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
8826 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
8827 if (tnapi
->hw_status
) {
8828 tnapi
->hw_status
->status
= 0;
8829 tnapi
->hw_status
->status_tag
= 0;
8831 tnapi
->last_tag
= 0;
8832 tnapi
->last_irq_tag
= 0;
8836 for (i
= 0; i
< tp
->irq_cnt
; i
++)
8837 synchronize_irq(tp
->napi
[i
].irq_vec
);
8839 if (tg3_asic_rev(tp
) == ASIC_REV_57780
) {
8840 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
8841 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
8845 val
= GRC_MISC_CFG_CORECLK_RESET
;
8847 if (tg3_flag(tp
, PCI_EXPRESS
)) {
8848 /* Force PCIe 1.0a mode */
8849 if (tg3_asic_rev(tp
) != ASIC_REV_5785
&&
8850 !tg3_flag(tp
, 57765_PLUS
) &&
8851 tr32(TG3_PCIE_PHY_TSTCTL
) ==
8852 (TG3_PCIE_PHY_TSTCTL_PCIE10
| TG3_PCIE_PHY_TSTCTL_PSCRAM
))
8853 tw32(TG3_PCIE_PHY_TSTCTL
, TG3_PCIE_PHY_TSTCTL_PSCRAM
);
8855 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A0
) {
8856 tw32(GRC_MISC_CFG
, (1 << 29));
8861 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
8862 tw32(VCPU_STATUS
, tr32(VCPU_STATUS
) | VCPU_STATUS_DRV_RESET
);
8863 tw32(GRC_VCPU_EXT_CTRL
,
8864 tr32(GRC_VCPU_EXT_CTRL
) & ~GRC_VCPU_EXT_CTRL_HALT_CPU
);
8867 /* Manage gphy power for all CPMU absent PCIe devices. */
8868 if (tg3_flag(tp
, 5705_PLUS
) && !tg3_flag(tp
, CPMU_PRESENT
))
8869 val
|= GRC_MISC_CFG_KEEP_GPHY_POWER
;
8871 tw32(GRC_MISC_CFG
, val
);
8873 /* restore 5701 hardware bug workaround write method */
8874 tp
->write32
= write_op
;
8876 /* Unfortunately, we have to delay before the PCI read back.
8877 * Some 575X chips even will not respond to a PCI cfg access
8878 * when the reset command is given to the chip.
8880 * How do these hardware designers expect things to work
8881 * properly if the PCI write is posted for a long period
8882 * of time? It is always necessary to have some method by
8883 * which a register read back can occur to push the write
8884 * out which does the reset.
8886 * For most tg3 variants the trick below was working.
8891 /* Flush PCI posted writes. The normal MMIO registers
8892 * are inaccessible at this time so this is the only
8893 * way to make this reliably (actually, this is no longer
8894 * the case, see above). I tried to use indirect
8895 * register read/write but this upset some 5701 variants.
8897 pci_read_config_dword(tp
->pdev
, PCI_COMMAND
, &val
);
8901 if (tg3_flag(tp
, PCI_EXPRESS
) && pci_is_pcie(tp
->pdev
)) {
8904 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5750_A0
) {
8908 /* Wait for link training to complete. */
8909 for (j
= 0; j
< 5000; j
++)
8912 pci_read_config_dword(tp
->pdev
, 0xc4, &cfg_val
);
8913 pci_write_config_dword(tp
->pdev
, 0xc4,
8914 cfg_val
| (1 << 15));
8917 /* Clear the "no snoop" and "relaxed ordering" bits. */
8918 val16
= PCI_EXP_DEVCTL_RELAX_EN
| PCI_EXP_DEVCTL_NOSNOOP_EN
;
8920 * Older PCIe devices only support the 128 byte
8921 * MPS setting. Enforce the restriction.
8923 if (!tg3_flag(tp
, CPMU_PRESENT
))
8924 val16
|= PCI_EXP_DEVCTL_PAYLOAD
;
8925 pcie_capability_clear_word(tp
->pdev
, PCI_EXP_DEVCTL
, val16
);
8927 /* Clear error status */
8928 pcie_capability_write_word(tp
->pdev
, PCI_EXP_DEVSTA
,
8929 PCI_EXP_DEVSTA_CED
|
8930 PCI_EXP_DEVSTA_NFED
|
8931 PCI_EXP_DEVSTA_FED
|
8932 PCI_EXP_DEVSTA_URD
);
8935 tg3_restore_pci_state(tp
);
8937 tg3_flag_clear(tp
, CHIP_RESETTING
);
8938 tg3_flag_clear(tp
, ERROR_PROCESSED
);
8941 if (tg3_flag(tp
, 5780_CLASS
))
8942 val
= tr32(MEMARB_MODE
);
8943 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
8945 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5750_A3
) {
8947 tw32(0x5000, 0x400);
8950 if (tg3_flag(tp
, IS_SSB_CORE
)) {
8952 * BCM4785: In order to avoid repercussions from using
8953 * potentially defective internal ROM, stop the Rx RISC CPU,
8954 * which is not required.
8957 tg3_halt_cpu(tp
, RX_CPU_BASE
);
8960 tw32(GRC_MODE
, tp
->grc_mode
);
8962 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A0
) {
8965 tw32(0xc4, val
| (1 << 15));
8968 if ((tp
->nic_sram_data_cfg
& NIC_SRAM_DATA_CFG_MINI_PCI
) != 0 &&
8969 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
8970 tp
->pci_clock_ctrl
|= CLOCK_CTRL_CLKRUN_OENABLE
;
8971 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A0
)
8972 tp
->pci_clock_ctrl
|= CLOCK_CTRL_FORCE_CLKRUN
;
8973 tw32(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
8976 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
8977 tp
->mac_mode
= MAC_MODE_PORT_MODE_TBI
;
8979 } else if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
8980 tp
->mac_mode
= MAC_MODE_PORT_MODE_GMII
;
8985 tw32_f(MAC_MODE
, val
);
8988 tg3_ape_unlock(tp
, TG3_APE_LOCK_GRC
);
8990 err
= tg3_poll_fw(tp
);
8996 if (tg3_flag(tp
, PCI_EXPRESS
) &&
8997 tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A0
&&
8998 tg3_asic_rev(tp
) != ASIC_REV_5785
&&
8999 !tg3_flag(tp
, 57765_PLUS
)) {
9002 tw32(0x7c00, val
| (1 << 25));
9005 if (tg3_asic_rev(tp
) == ASIC_REV_5720
) {
9006 val
= tr32(TG3_CPMU_CLCK_ORIDE
);
9007 tw32(TG3_CPMU_CLCK_ORIDE
, val
& ~CPMU_CLCK_ORIDE_MAC_ORIDE_EN
);
9010 /* Reprobe ASF enable state. */
9011 tg3_flag_clear(tp
, ENABLE_ASF
);
9012 tp
->phy_flags
&= ~(TG3_PHYFLG_1G_ON_VAUX_OK
|
9013 TG3_PHYFLG_KEEP_LINK_ON_PWRDN
);
9015 tg3_flag_clear(tp
, ASF_NEW_HANDSHAKE
);
9016 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
9017 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
9020 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
9021 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
9022 tg3_flag_set(tp
, ENABLE_ASF
);
9023 tp
->last_event_jiffies
= jiffies
;
9024 if (tg3_flag(tp
, 5750_PLUS
))
9025 tg3_flag_set(tp
, ASF_NEW_HANDSHAKE
);
9027 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &nic_cfg
);
9028 if (nic_cfg
& NIC_SRAM_1G_ON_VAUX_OK
)
9029 tp
->phy_flags
|= TG3_PHYFLG_1G_ON_VAUX_OK
;
9030 if (nic_cfg
& NIC_SRAM_LNK_FLAP_AVOID
)
9031 tp
->phy_flags
|= TG3_PHYFLG_KEEP_LINK_ON_PWRDN
;
9038 static void tg3_get_nstats(struct tg3
*, struct rtnl_link_stats64
*);
9039 static void tg3_get_estats(struct tg3
*, struct tg3_ethtool_stats
*);
9041 /* tp->lock is held. */
9042 static int tg3_halt(struct tg3
*tp
, int kind
, bool silent
)
9048 tg3_write_sig_pre_reset(tp
, kind
);
9050 tg3_abort_hw(tp
, silent
);
9051 err
= tg3_chip_reset(tp
);
9053 __tg3_set_mac_addr(tp
, false);
9055 tg3_write_sig_legacy(tp
, kind
);
9056 tg3_write_sig_post_reset(tp
, kind
);
9059 /* Save the stats across chip resets... */
9060 tg3_get_nstats(tp
, &tp
->net_stats_prev
);
9061 tg3_get_estats(tp
, &tp
->estats_prev
);
9063 /* And make sure the next sample is new data */
9064 memset(tp
->hw_stats
, 0, sizeof(struct tg3_hw_stats
));
9073 static int tg3_set_mac_addr(struct net_device
*dev
, void *p
)
9075 struct tg3
*tp
= netdev_priv(dev
);
9076 struct sockaddr
*addr
= p
;
9078 bool skip_mac_1
= false;
9080 if (!is_valid_ether_addr(addr
->sa_data
))
9081 return -EADDRNOTAVAIL
;
9083 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
9085 if (!netif_running(dev
))
9088 if (tg3_flag(tp
, ENABLE_ASF
)) {
9089 u32 addr0_high
, addr0_low
, addr1_high
, addr1_low
;
9091 addr0_high
= tr32(MAC_ADDR_0_HIGH
);
9092 addr0_low
= tr32(MAC_ADDR_0_LOW
);
9093 addr1_high
= tr32(MAC_ADDR_1_HIGH
);
9094 addr1_low
= tr32(MAC_ADDR_1_LOW
);
9096 /* Skip MAC addr 1 if ASF is using it. */
9097 if ((addr0_high
!= addr1_high
|| addr0_low
!= addr1_low
) &&
9098 !(addr1_high
== 0 && addr1_low
== 0))
9101 spin_lock_bh(&tp
->lock
);
9102 __tg3_set_mac_addr(tp
, skip_mac_1
);
9103 spin_unlock_bh(&tp
->lock
);
9108 /* tp->lock is held. */
9109 static void tg3_set_bdinfo(struct tg3
*tp
, u32 bdinfo_addr
,
9110 dma_addr_t mapping
, u32 maxlen_flags
,
9114 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
),
9115 ((u64
) mapping
>> 32));
9117 (bdinfo_addr
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
),
9118 ((u64
) mapping
& 0xffffffff));
9120 (bdinfo_addr
+ TG3_BDINFO_MAXLEN_FLAGS
),
9123 if (!tg3_flag(tp
, 5705_PLUS
))
9125 (bdinfo_addr
+ TG3_BDINFO_NIC_ADDR
),
9130 static void tg3_coal_tx_init(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
9134 if (!tg3_flag(tp
, ENABLE_TSS
)) {
9135 tw32(HOSTCC_TXCOL_TICKS
, ec
->tx_coalesce_usecs
);
9136 tw32(HOSTCC_TXMAX_FRAMES
, ec
->tx_max_coalesced_frames
);
9137 tw32(HOSTCC_TXCOAL_MAXF_INT
, ec
->tx_max_coalesced_frames_irq
);
9139 tw32(HOSTCC_TXCOL_TICKS
, 0);
9140 tw32(HOSTCC_TXMAX_FRAMES
, 0);
9141 tw32(HOSTCC_TXCOAL_MAXF_INT
, 0);
9143 for (; i
< tp
->txq_cnt
; i
++) {
9146 reg
= HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18;
9147 tw32(reg
, ec
->tx_coalesce_usecs
);
9148 reg
= HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18;
9149 tw32(reg
, ec
->tx_max_coalesced_frames
);
9150 reg
= HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
9151 tw32(reg
, ec
->tx_max_coalesced_frames_irq
);
9155 for (; i
< tp
->irq_max
- 1; i
++) {
9156 tw32(HOSTCC_TXCOL_TICKS_VEC1
+ i
* 0x18, 0);
9157 tw32(HOSTCC_TXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
9158 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
9162 static void tg3_coal_rx_init(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
9165 u32 limit
= tp
->rxq_cnt
;
9167 if (!tg3_flag(tp
, ENABLE_RSS
)) {
9168 tw32(HOSTCC_RXCOL_TICKS
, ec
->rx_coalesce_usecs
);
9169 tw32(HOSTCC_RXMAX_FRAMES
, ec
->rx_max_coalesced_frames
);
9170 tw32(HOSTCC_RXCOAL_MAXF_INT
, ec
->rx_max_coalesced_frames_irq
);
9173 tw32(HOSTCC_RXCOL_TICKS
, 0);
9174 tw32(HOSTCC_RXMAX_FRAMES
, 0);
9175 tw32(HOSTCC_RXCOAL_MAXF_INT
, 0);
9178 for (; i
< limit
; i
++) {
9181 reg
= HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18;
9182 tw32(reg
, ec
->rx_coalesce_usecs
);
9183 reg
= HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18;
9184 tw32(reg
, ec
->rx_max_coalesced_frames
);
9185 reg
= HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18;
9186 tw32(reg
, ec
->rx_max_coalesced_frames_irq
);
9189 for (; i
< tp
->irq_max
- 1; i
++) {
9190 tw32(HOSTCC_RXCOL_TICKS_VEC1
+ i
* 0x18, 0);
9191 tw32(HOSTCC_RXMAX_FRAMES_VEC1
+ i
* 0x18, 0);
9192 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1
+ i
* 0x18, 0);
9196 static void __tg3_set_coalesce(struct tg3
*tp
, struct ethtool_coalesce
*ec
)
9198 tg3_coal_tx_init(tp
, ec
);
9199 tg3_coal_rx_init(tp
, ec
);
9201 if (!tg3_flag(tp
, 5705_PLUS
)) {
9202 u32 val
= ec
->stats_block_coalesce_usecs
;
9204 tw32(HOSTCC_RXCOAL_TICK_INT
, ec
->rx_coalesce_usecs_irq
);
9205 tw32(HOSTCC_TXCOAL_TICK_INT
, ec
->tx_coalesce_usecs_irq
);
9210 tw32(HOSTCC_STAT_COAL_TICKS
, val
);
9214 /* tp->lock is held. */
9215 static void tg3_rings_reset(struct tg3
*tp
)
9218 u32 stblk
, txrcb
, rxrcb
, limit
;
9219 struct tg3_napi
*tnapi
= &tp
->napi
[0];
9221 /* Disable all transmit rings but the first. */
9222 if (!tg3_flag(tp
, 5705_PLUS
))
9223 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 16;
9224 else if (tg3_flag(tp
, 5717_PLUS
))
9225 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 4;
9226 else if (tg3_flag(tp
, 57765_CLASS
) ||
9227 tg3_asic_rev(tp
) == ASIC_REV_5762
)
9228 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
* 2;
9230 limit
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
9232 for (txrcb
= NIC_SRAM_SEND_RCB
+ TG3_BDINFO_SIZE
;
9233 txrcb
< limit
; txrcb
+= TG3_BDINFO_SIZE
)
9234 tg3_write_mem(tp
, txrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
9235 BDINFO_FLAGS_DISABLED
);
9238 /* Disable all receive return rings but the first. */
9239 if (tg3_flag(tp
, 5717_PLUS
))
9240 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 17;
9241 else if (!tg3_flag(tp
, 5705_PLUS
))
9242 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 16;
9243 else if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
9244 tg3_asic_rev(tp
) == ASIC_REV_5762
||
9245 tg3_flag(tp
, 57765_CLASS
))
9246 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
* 4;
9248 limit
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
9250 for (rxrcb
= NIC_SRAM_RCV_RET_RCB
+ TG3_BDINFO_SIZE
;
9251 rxrcb
< limit
; rxrcb
+= TG3_BDINFO_SIZE
)
9252 tg3_write_mem(tp
, rxrcb
+ TG3_BDINFO_MAXLEN_FLAGS
,
9253 BDINFO_FLAGS_DISABLED
);
9255 /* Disable interrupts */
9256 tw32_mailbox_f(tp
->napi
[0].int_mbox
, 1);
9257 tp
->napi
[0].chk_msi_cnt
= 0;
9258 tp
->napi
[0].last_rx_cons
= 0;
9259 tp
->napi
[0].last_tx_cons
= 0;
9261 /* Zero mailbox registers. */
9262 if (tg3_flag(tp
, SUPPORT_MSIX
)) {
9263 for (i
= 1; i
< tp
->irq_max
; i
++) {
9264 tp
->napi
[i
].tx_prod
= 0;
9265 tp
->napi
[i
].tx_cons
= 0;
9266 if (tg3_flag(tp
, ENABLE_TSS
))
9267 tw32_mailbox(tp
->napi
[i
].prodmbox
, 0);
9268 tw32_rx_mbox(tp
->napi
[i
].consmbox
, 0);
9269 tw32_mailbox_f(tp
->napi
[i
].int_mbox
, 1);
9270 tp
->napi
[i
].chk_msi_cnt
= 0;
9271 tp
->napi
[i
].last_rx_cons
= 0;
9272 tp
->napi
[i
].last_tx_cons
= 0;
9274 if (!tg3_flag(tp
, ENABLE_TSS
))
9275 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
9277 tp
->napi
[0].tx_prod
= 0;
9278 tp
->napi
[0].tx_cons
= 0;
9279 tw32_mailbox(tp
->napi
[0].prodmbox
, 0);
9280 tw32_rx_mbox(tp
->napi
[0].consmbox
, 0);
9283 /* Make sure the NIC-based send BD rings are disabled. */
9284 if (!tg3_flag(tp
, 5705_PLUS
)) {
9285 u32 mbox
= MAILBOX_SNDNIC_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
9286 for (i
= 0; i
< 16; i
++)
9287 tw32_tx_mbox(mbox
+ i
* 8, 0);
9290 txrcb
= NIC_SRAM_SEND_RCB
;
9291 rxrcb
= NIC_SRAM_RCV_RET_RCB
;
9293 /* Clear status block in ram. */
9294 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
9296 /* Set status block DMA address */
9297 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
9298 ((u64
) tnapi
->status_mapping
>> 32));
9299 tw32(HOSTCC_STATUS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
9300 ((u64
) tnapi
->status_mapping
& 0xffffffff));
9302 if (tnapi
->tx_ring
) {
9303 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
9304 (TG3_TX_RING_SIZE
<<
9305 BDINFO_FLAGS_MAXLEN_SHIFT
),
9306 NIC_SRAM_TX_BUFFER_DESC
);
9307 txrcb
+= TG3_BDINFO_SIZE
;
9310 if (tnapi
->rx_rcb
) {
9311 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
9312 (tp
->rx_ret_ring_mask
+ 1) <<
9313 BDINFO_FLAGS_MAXLEN_SHIFT
, 0);
9314 rxrcb
+= TG3_BDINFO_SIZE
;
9317 stblk
= HOSTCC_STATBLCK_RING1
;
9319 for (i
= 1, tnapi
++; i
< tp
->irq_cnt
; i
++, tnapi
++) {
9320 u64 mapping
= (u64
)tnapi
->status_mapping
;
9321 tw32(stblk
+ TG3_64BIT_REG_HIGH
, mapping
>> 32);
9322 tw32(stblk
+ TG3_64BIT_REG_LOW
, mapping
& 0xffffffff);
9324 /* Clear status block in ram. */
9325 memset(tnapi
->hw_status
, 0, TG3_HW_STATUS_SIZE
);
9327 if (tnapi
->tx_ring
) {
9328 tg3_set_bdinfo(tp
, txrcb
, tnapi
->tx_desc_mapping
,
9329 (TG3_TX_RING_SIZE
<<
9330 BDINFO_FLAGS_MAXLEN_SHIFT
),
9331 NIC_SRAM_TX_BUFFER_DESC
);
9332 txrcb
+= TG3_BDINFO_SIZE
;
9335 tg3_set_bdinfo(tp
, rxrcb
, tnapi
->rx_rcb_mapping
,
9336 ((tp
->rx_ret_ring_mask
+ 1) <<
9337 BDINFO_FLAGS_MAXLEN_SHIFT
), 0);
9340 rxrcb
+= TG3_BDINFO_SIZE
;
9344 static void tg3_setup_rxbd_thresholds(struct tg3
*tp
)
9346 u32 val
, bdcache_maxcnt
, host_rep_thresh
, nic_rep_thresh
;
9348 if (!tg3_flag(tp
, 5750_PLUS
) ||
9349 tg3_flag(tp
, 5780_CLASS
) ||
9350 tg3_asic_rev(tp
) == ASIC_REV_5750
||
9351 tg3_asic_rev(tp
) == ASIC_REV_5752
||
9352 tg3_flag(tp
, 57765_PLUS
))
9353 bdcache_maxcnt
= TG3_SRAM_RX_STD_BDCACHE_SIZE_5700
;
9354 else if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
9355 tg3_asic_rev(tp
) == ASIC_REV_5787
)
9356 bdcache_maxcnt
= TG3_SRAM_RX_STD_BDCACHE_SIZE_5755
;
9358 bdcache_maxcnt
= TG3_SRAM_RX_STD_BDCACHE_SIZE_5906
;
9360 nic_rep_thresh
= min(bdcache_maxcnt
/ 2, tp
->rx_std_max_post
);
9361 host_rep_thresh
= max_t(u32
, tp
->rx_pending
/ 8, 1);
9363 val
= min(nic_rep_thresh
, host_rep_thresh
);
9364 tw32(RCVBDI_STD_THRESH
, val
);
9366 if (tg3_flag(tp
, 57765_PLUS
))
9367 tw32(STD_REPLENISH_LWM
, bdcache_maxcnt
);
9369 if (!tg3_flag(tp
, JUMBO_CAPABLE
) || tg3_flag(tp
, 5780_CLASS
))
9372 bdcache_maxcnt
= TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700
;
9374 host_rep_thresh
= max_t(u32
, tp
->rx_jumbo_pending
/ 8, 1);
9376 val
= min(bdcache_maxcnt
/ 2, host_rep_thresh
);
9377 tw32(RCVBDI_JUMBO_THRESH
, val
);
9379 if (tg3_flag(tp
, 57765_PLUS
))
9380 tw32(JMB_REPLENISH_LWM
, bdcache_maxcnt
);
9383 static inline u32
calc_crc(unsigned char *buf
, int len
)
9391 for (j
= 0; j
< len
; j
++) {
9394 for (k
= 0; k
< 8; k
++) {
9407 static void tg3_set_multi(struct tg3
*tp
, unsigned int accept_all
)
9409 /* accept or reject all multicast frames */
9410 tw32(MAC_HASH_REG_0
, accept_all
? 0xffffffff : 0);
9411 tw32(MAC_HASH_REG_1
, accept_all
? 0xffffffff : 0);
9412 tw32(MAC_HASH_REG_2
, accept_all
? 0xffffffff : 0);
9413 tw32(MAC_HASH_REG_3
, accept_all
? 0xffffffff : 0);
9416 static void __tg3_set_rx_mode(struct net_device
*dev
)
9418 struct tg3
*tp
= netdev_priv(dev
);
9421 rx_mode
= tp
->rx_mode
& ~(RX_MODE_PROMISC
|
9422 RX_MODE_KEEP_VLAN_TAG
);
9424 #if !defined(CONFIG_VLAN_8021Q) && !defined(CONFIG_VLAN_8021Q_MODULE)
9425 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9428 if (!tg3_flag(tp
, ENABLE_ASF
))
9429 rx_mode
|= RX_MODE_KEEP_VLAN_TAG
;
9432 if (dev
->flags
& IFF_PROMISC
) {
9433 /* Promiscuous mode. */
9434 rx_mode
|= RX_MODE_PROMISC
;
9435 } else if (dev
->flags
& IFF_ALLMULTI
) {
9436 /* Accept all multicast. */
9437 tg3_set_multi(tp
, 1);
9438 } else if (netdev_mc_empty(dev
)) {
9439 /* Reject all multicast. */
9440 tg3_set_multi(tp
, 0);
9442 /* Accept one or more multicast(s). */
9443 struct netdev_hw_addr
*ha
;
9444 u32 mc_filter
[4] = { 0, };
9449 netdev_for_each_mc_addr(ha
, dev
) {
9450 crc
= calc_crc(ha
->addr
, ETH_ALEN
);
9452 regidx
= (bit
& 0x60) >> 5;
9454 mc_filter
[regidx
] |= (1 << bit
);
9457 tw32(MAC_HASH_REG_0
, mc_filter
[0]);
9458 tw32(MAC_HASH_REG_1
, mc_filter
[1]);
9459 tw32(MAC_HASH_REG_2
, mc_filter
[2]);
9460 tw32(MAC_HASH_REG_3
, mc_filter
[3]);
9463 if (rx_mode
!= tp
->rx_mode
) {
9464 tp
->rx_mode
= rx_mode
;
9465 tw32_f(MAC_RX_MODE
, rx_mode
);
9470 static void tg3_rss_init_dflt_indir_tbl(struct tg3
*tp
, u32 qcnt
)
9474 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++)
9475 tp
->rss_ind_tbl
[i
] = ethtool_rxfh_indir_default(i
, qcnt
);
9478 static void tg3_rss_check_indir_tbl(struct tg3
*tp
)
9482 if (!tg3_flag(tp
, SUPPORT_MSIX
))
9485 if (tp
->rxq_cnt
== 1) {
9486 memset(&tp
->rss_ind_tbl
[0], 0, sizeof(tp
->rss_ind_tbl
));
9490 /* Validate table against current IRQ count */
9491 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++) {
9492 if (tp
->rss_ind_tbl
[i
] >= tp
->rxq_cnt
)
9496 if (i
!= TG3_RSS_INDIR_TBL_SIZE
)
9497 tg3_rss_init_dflt_indir_tbl(tp
, tp
->rxq_cnt
);
9500 static void tg3_rss_write_indir_tbl(struct tg3
*tp
)
9503 u32 reg
= MAC_RSS_INDIR_TBL_0
;
9505 while (i
< TG3_RSS_INDIR_TBL_SIZE
) {
9506 u32 val
= tp
->rss_ind_tbl
[i
];
9508 for (; i
% 8; i
++) {
9510 val
|= tp
->rss_ind_tbl
[i
];
9517 /* tp->lock is held. */
9518 static int tg3_reset_hw(struct tg3
*tp
, bool reset_phy
)
9520 u32 val
, rdmac_mode
;
9522 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
9524 tg3_disable_ints(tp
);
9528 tg3_write_sig_pre_reset(tp
, RESET_KIND_INIT
);
9530 if (tg3_flag(tp
, INIT_COMPLETE
))
9531 tg3_abort_hw(tp
, 1);
9533 if ((tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
) &&
9534 !(tp
->phy_flags
& TG3_PHYFLG_USER_CONFIGURED
)) {
9535 tg3_phy_pull_config(tp
);
9536 tg3_eee_pull_config(tp
, NULL
);
9537 tp
->phy_flags
|= TG3_PHYFLG_USER_CONFIGURED
;
9540 /* Enable MAC control of LPI */
9541 if (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
)
9547 err
= tg3_chip_reset(tp
);
9551 tg3_write_sig_legacy(tp
, RESET_KIND_INIT
);
9553 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
) {
9554 val
= tr32(TG3_CPMU_CTRL
);
9555 val
&= ~(CPMU_CTRL_LINK_AWARE_MODE
| CPMU_CTRL_LINK_IDLE_MODE
);
9556 tw32(TG3_CPMU_CTRL
, val
);
9558 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
9559 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
9560 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
9561 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
9563 val
= tr32(TG3_CPMU_LNK_AWARE_PWRMD
);
9564 val
&= ~CPMU_LNK_AWARE_MACCLK_MASK
;
9565 val
|= CPMU_LNK_AWARE_MACCLK_6_25
;
9566 tw32(TG3_CPMU_LNK_AWARE_PWRMD
, val
);
9568 val
= tr32(TG3_CPMU_HST_ACC
);
9569 val
&= ~CPMU_HST_ACC_MACCLK_MASK
;
9570 val
|= CPMU_HST_ACC_MACCLK_6_25
;
9571 tw32(TG3_CPMU_HST_ACC
, val
);
9574 if (tg3_asic_rev(tp
) == ASIC_REV_57780
) {
9575 val
= tr32(PCIE_PWR_MGMT_THRESH
) & ~PCIE_PWR_MGMT_L1_THRESH_MSK
;
9576 val
|= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN
|
9577 PCIE_PWR_MGMT_L1_THRESH_4MS
;
9578 tw32(PCIE_PWR_MGMT_THRESH
, val
);
9580 val
= tr32(TG3_PCIE_EIDLE_DELAY
) & ~TG3_PCIE_EIDLE_DELAY_MASK
;
9581 tw32(TG3_PCIE_EIDLE_DELAY
, val
| TG3_PCIE_EIDLE_DELAY_13_CLKS
);
9583 tw32(TG3_CORR_ERR_STAT
, TG3_CORR_ERR_STAT_CLEAR
);
9585 val
= tr32(TG3_PCIE_LNKCTL
) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN
;
9586 tw32(TG3_PCIE_LNKCTL
, val
| TG3_PCIE_LNKCTL_L1_PLL_PD_DIS
);
9589 if (tg3_flag(tp
, L1PLLPD_EN
)) {
9590 u32 grc_mode
= tr32(GRC_MODE
);
9592 /* Access the lower 1K of PL PCIE block registers. */
9593 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
9594 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
9596 val
= tr32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
);
9597 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL1
,
9598 val
| TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN
);
9600 tw32(GRC_MODE
, grc_mode
);
9603 if (tg3_flag(tp
, 57765_CLASS
)) {
9604 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_57765_A0
) {
9605 u32 grc_mode
= tr32(GRC_MODE
);
9607 /* Access the lower 1K of PL PCIE block registers. */
9608 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
9609 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_PL_SEL
);
9611 val
= tr32(TG3_PCIE_TLDLPL_PORT
+
9612 TG3_PCIE_PL_LO_PHYCTL5
);
9613 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_PL_LO_PHYCTL5
,
9614 val
| TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ
);
9616 tw32(GRC_MODE
, grc_mode
);
9619 if (tg3_chip_rev(tp
) != CHIPREV_57765_AX
) {
9622 /* Fix transmit hangs */
9623 val
= tr32(TG3_CPMU_PADRNG_CTL
);
9624 val
|= TG3_CPMU_PADRNG_CTL_RDIV2
;
9625 tw32(TG3_CPMU_PADRNG_CTL
, val
);
9627 grc_mode
= tr32(GRC_MODE
);
9629 /* Access the lower 1K of DL PCIE block registers. */
9630 val
= grc_mode
& ~GRC_MODE_PCIE_PORT_MASK
;
9631 tw32(GRC_MODE
, val
| GRC_MODE_PCIE_DL_SEL
);
9633 val
= tr32(TG3_PCIE_TLDLPL_PORT
+
9634 TG3_PCIE_DL_LO_FTSMAX
);
9635 val
&= ~TG3_PCIE_DL_LO_FTSMAX_MSK
;
9636 tw32(TG3_PCIE_TLDLPL_PORT
+ TG3_PCIE_DL_LO_FTSMAX
,
9637 val
| TG3_PCIE_DL_LO_FTSMAX_VAL
);
9639 tw32(GRC_MODE
, grc_mode
);
9642 val
= tr32(TG3_CPMU_LSPD_10MB_CLK
);
9643 val
&= ~CPMU_LSPD_10MB_MACCLK_MASK
;
9644 val
|= CPMU_LSPD_10MB_MACCLK_6_25
;
9645 tw32(TG3_CPMU_LSPD_10MB_CLK
, val
);
9648 /* This works around an issue with Athlon chipsets on
9649 * B3 tigon3 silicon. This bit has no effect on any
9650 * other revision. But do not set this on PCI Express
9651 * chips and don't even touch the clocks if the CPMU is present.
9653 if (!tg3_flag(tp
, CPMU_PRESENT
)) {
9654 if (!tg3_flag(tp
, PCI_EXPRESS
))
9655 tp
->pci_clock_ctrl
|= CLOCK_CTRL_DELAY_PCI_GRANT
;
9656 tw32_f(TG3PCI_CLOCK_CTRL
, tp
->pci_clock_ctrl
);
9659 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5704_A0
&&
9660 tg3_flag(tp
, PCIX_MODE
)) {
9661 val
= tr32(TG3PCI_PCISTATE
);
9662 val
|= PCISTATE_RETRY_SAME_DMA
;
9663 tw32(TG3PCI_PCISTATE
, val
);
9666 if (tg3_flag(tp
, ENABLE_APE
)) {
9667 /* Allow reads and writes to the
9668 * APE register and memory space.
9670 val
= tr32(TG3PCI_PCISTATE
);
9671 val
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
9672 PCISTATE_ALLOW_APE_SHMEM_WR
|
9673 PCISTATE_ALLOW_APE_PSPACE_WR
;
9674 tw32(TG3PCI_PCISTATE
, val
);
9677 if (tg3_chip_rev(tp
) == CHIPREV_5704_BX
) {
9678 /* Enable some hw fixes. */
9679 val
= tr32(TG3PCI_MSI_DATA
);
9680 val
|= (1 << 26) | (1 << 28) | (1 << 29);
9681 tw32(TG3PCI_MSI_DATA
, val
);
9684 /* Descriptor ring init may make accesses to the
9685 * NIC SRAM area to setup the TX descriptors, so we
9686 * can only do this after the hardware has been
9687 * successfully reset.
9689 err
= tg3_init_rings(tp
);
9693 if (tg3_flag(tp
, 57765_PLUS
)) {
9694 val
= tr32(TG3PCI_DMA_RW_CTRL
) &
9695 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
9696 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_57765_A0
)
9697 val
&= ~DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK
;
9698 if (!tg3_flag(tp
, 57765_CLASS
) &&
9699 tg3_asic_rev(tp
) != ASIC_REV_5717
&&
9700 tg3_asic_rev(tp
) != ASIC_REV_5762
)
9701 val
|= DMA_RWCTRL_TAGGED_STAT_WA
;
9702 tw32(TG3PCI_DMA_RW_CTRL
, val
| tp
->dma_rwctrl
);
9703 } else if (tg3_asic_rev(tp
) != ASIC_REV_5784
&&
9704 tg3_asic_rev(tp
) != ASIC_REV_5761
) {
9705 /* This value is determined during the probe time DMA
9706 * engine test, tg3_test_dma.
9708 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
9711 tp
->grc_mode
&= ~(GRC_MODE_HOST_SENDBDS
|
9712 GRC_MODE_4X_NIC_SEND_RINGS
|
9713 GRC_MODE_NO_TX_PHDR_CSUM
|
9714 GRC_MODE_NO_RX_PHDR_CSUM
);
9715 tp
->grc_mode
|= GRC_MODE_HOST_SENDBDS
;
9717 /* Pseudo-header checksum is done by hardware logic and not
9718 * the offload processers, so make the chip do the pseudo-
9719 * header checksums on receive. For transmit it is more
9720 * convenient to do the pseudo-header checksum in software
9721 * as Linux does that on transmit for us in all cases.
9723 tp
->grc_mode
|= GRC_MODE_NO_TX_PHDR_CSUM
;
9725 val
= GRC_MODE_IRQ_ON_MAC_ATTN
| GRC_MODE_HOST_STACKUP
;
9727 tw32(TG3_RX_PTP_CTL
,
9728 tp
->rxptpctl
| TG3_RX_PTP_CTL_HWTS_INTERLOCK
);
9730 if (tg3_flag(tp
, PTP_CAPABLE
))
9731 val
|= GRC_MODE_TIME_SYNC_ENABLE
;
9733 tw32(GRC_MODE
, tp
->grc_mode
| val
);
9735 /* Setup the timer prescalar register. Clock is always 66Mhz. */
9736 val
= tr32(GRC_MISC_CFG
);
9738 val
|= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT
);
9739 tw32(GRC_MISC_CFG
, val
);
9741 /* Initialize MBUF/DESC pool. */
9742 if (tg3_flag(tp
, 5750_PLUS
)) {
9744 } else if (tg3_asic_rev(tp
) != ASIC_REV_5705
) {
9745 tw32(BUFMGR_MB_POOL_ADDR
, NIC_SRAM_MBUF_POOL_BASE
);
9746 if (tg3_asic_rev(tp
) == ASIC_REV_5704
)
9747 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE64
);
9749 tw32(BUFMGR_MB_POOL_SIZE
, NIC_SRAM_MBUF_POOL_SIZE96
);
9750 tw32(BUFMGR_DMA_DESC_POOL_ADDR
, NIC_SRAM_DMA_DESC_POOL_BASE
);
9751 tw32(BUFMGR_DMA_DESC_POOL_SIZE
, NIC_SRAM_DMA_DESC_POOL_SIZE
);
9752 } else if (tg3_flag(tp
, TSO_CAPABLE
)) {
9755 fw_len
= tp
->fw_len
;
9756 fw_len
= (fw_len
+ (0x80 - 1)) & ~(0x80 - 1);
9757 tw32(BUFMGR_MB_POOL_ADDR
,
9758 NIC_SRAM_MBUF_POOL_BASE5705
+ fw_len
);
9759 tw32(BUFMGR_MB_POOL_SIZE
,
9760 NIC_SRAM_MBUF_POOL_SIZE5705
- fw_len
- 0xa00);
9763 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
9764 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
9765 tp
->bufmgr_config
.mbuf_read_dma_low_water
);
9766 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
9767 tp
->bufmgr_config
.mbuf_mac_rx_low_water
);
9768 tw32(BUFMGR_MB_HIGH_WATER
,
9769 tp
->bufmgr_config
.mbuf_high_water
);
9771 tw32(BUFMGR_MB_RDMA_LOW_WATER
,
9772 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
);
9773 tw32(BUFMGR_MB_MACRX_LOW_WATER
,
9774 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
);
9775 tw32(BUFMGR_MB_HIGH_WATER
,
9776 tp
->bufmgr_config
.mbuf_high_water_jumbo
);
9778 tw32(BUFMGR_DMA_LOW_WATER
,
9779 tp
->bufmgr_config
.dma_low_water
);
9780 tw32(BUFMGR_DMA_HIGH_WATER
,
9781 tp
->bufmgr_config
.dma_high_water
);
9783 val
= BUFMGR_MODE_ENABLE
| BUFMGR_MODE_ATTN_ENABLE
;
9784 if (tg3_asic_rev(tp
) == ASIC_REV_5719
)
9785 val
|= BUFMGR_MODE_NO_TX_UNDERRUN
;
9786 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
9787 tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
||
9788 tg3_chip_rev_id(tp
) == CHIPREV_ID_5720_A0
)
9789 val
|= BUFMGR_MODE_MBLOW_ATTN_ENAB
;
9790 tw32(BUFMGR_MODE
, val
);
9791 for (i
= 0; i
< 2000; i
++) {
9792 if (tr32(BUFMGR_MODE
) & BUFMGR_MODE_ENABLE
)
9797 netdev_err(tp
->dev
, "%s cannot enable BUFMGR\n", __func__
);
9801 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5906_A1
)
9802 tw32(ISO_PKT_TX
, (tr32(ISO_PKT_TX
) & ~0x3) | 0x2);
9804 tg3_setup_rxbd_thresholds(tp
);
9806 /* Initialize TG3_BDINFO's at:
9807 * RCVDBDI_STD_BD: standard eth size rx ring
9808 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
9809 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
9812 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
9813 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
9814 * ring attribute flags
9815 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
9817 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
9818 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
9820 * The size of each ring is fixed in the firmware, but the location is
9823 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
9824 ((u64
) tpr
->rx_std_mapping
>> 32));
9825 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
9826 ((u64
) tpr
->rx_std_mapping
& 0xffffffff));
9827 if (!tg3_flag(tp
, 5717_PLUS
))
9828 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_NIC_ADDR
,
9829 NIC_SRAM_RX_BUFFER_DESC
);
9831 /* Disable the mini ring */
9832 if (!tg3_flag(tp
, 5705_PLUS
))
9833 tw32(RCVDBDI_MINI_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
9834 BDINFO_FLAGS_DISABLED
);
9836 /* Program the jumbo buffer descriptor ring control
9837 * blocks on those devices that have them.
9839 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
||
9840 (tg3_flag(tp
, JUMBO_CAPABLE
) && !tg3_flag(tp
, 5780_CLASS
))) {
9842 if (tg3_flag(tp
, JUMBO_RING_ENABLE
)) {
9843 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
9844 ((u64
) tpr
->rx_jmb_mapping
>> 32));
9845 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
9846 ((u64
) tpr
->rx_jmb_mapping
& 0xffffffff));
9847 val
= TG3_RX_JMB_RING_SIZE(tp
) <<
9848 BDINFO_FLAGS_MAXLEN_SHIFT
;
9849 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
9850 val
| BDINFO_FLAGS_USE_EXT_RECV
);
9851 if (!tg3_flag(tp
, USE_JUMBO_BDFLAG
) ||
9852 tg3_flag(tp
, 57765_CLASS
) ||
9853 tg3_asic_rev(tp
) == ASIC_REV_5762
)
9854 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_NIC_ADDR
,
9855 NIC_SRAM_RX_JUMBO_BUFFER_DESC
);
9857 tw32(RCVDBDI_JUMBO_BD
+ TG3_BDINFO_MAXLEN_FLAGS
,
9858 BDINFO_FLAGS_DISABLED
);
9861 if (tg3_flag(tp
, 57765_PLUS
)) {
9862 val
= TG3_RX_STD_RING_SIZE(tp
);
9863 val
<<= BDINFO_FLAGS_MAXLEN_SHIFT
;
9864 val
|= (TG3_RX_STD_DMA_SZ
<< 2);
9866 val
= TG3_RX_STD_DMA_SZ
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
9868 val
= TG3_RX_STD_MAX_SIZE_5700
<< BDINFO_FLAGS_MAXLEN_SHIFT
;
9870 tw32(RCVDBDI_STD_BD
+ TG3_BDINFO_MAXLEN_FLAGS
, val
);
9872 tpr
->rx_std_prod_idx
= tp
->rx_pending
;
9873 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG
, tpr
->rx_std_prod_idx
);
9875 tpr
->rx_jmb_prod_idx
=
9876 tg3_flag(tp
, JUMBO_RING_ENABLE
) ? tp
->rx_jumbo_pending
: 0;
9877 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG
, tpr
->rx_jmb_prod_idx
);
9879 tg3_rings_reset(tp
);
9881 /* Initialize MAC address and backoff seed. */
9882 __tg3_set_mac_addr(tp
, false);
9884 /* MTU + ethernet header + FCS + optional VLAN tag */
9885 tw32(MAC_RX_MTU_SIZE
,
9886 tp
->dev
->mtu
+ ETH_HLEN
+ ETH_FCS_LEN
+ VLAN_HLEN
);
9888 /* The slot time is changed by tg3_setup_phy if we
9889 * run at gigabit with half duplex.
9891 val
= (2 << TX_LENGTHS_IPG_CRS_SHIFT
) |
9892 (6 << TX_LENGTHS_IPG_SHIFT
) |
9893 (32 << TX_LENGTHS_SLOT_TIME_SHIFT
);
9895 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
9896 tg3_asic_rev(tp
) == ASIC_REV_5762
)
9897 val
|= tr32(MAC_TX_LENGTHS
) &
9898 (TX_LENGTHS_JMB_FRM_LEN_MSK
|
9899 TX_LENGTHS_CNT_DWN_VAL_MSK
);
9901 tw32(MAC_TX_LENGTHS
, val
);
9903 /* Receive rules. */
9904 tw32(MAC_RCV_RULE_CFG
, RCV_RULE_CFG_DEFAULT_CLASS
);
9905 tw32(RCVLPC_CONFIG
, 0x0181);
9907 /* Calculate RDMAC_MODE setting early, we need it to determine
9908 * the RCVLPC_STATE_ENABLE mask.
9910 rdmac_mode
= (RDMAC_MODE_ENABLE
| RDMAC_MODE_TGTABORT_ENAB
|
9911 RDMAC_MODE_MSTABORT_ENAB
| RDMAC_MODE_PARITYERR_ENAB
|
9912 RDMAC_MODE_ADDROFLOW_ENAB
| RDMAC_MODE_FIFOOFLOW_ENAB
|
9913 RDMAC_MODE_FIFOURUN_ENAB
| RDMAC_MODE_FIFOOREAD_ENAB
|
9914 RDMAC_MODE_LNGREAD_ENAB
);
9916 if (tg3_asic_rev(tp
) == ASIC_REV_5717
)
9917 rdmac_mode
|= RDMAC_MODE_MULT_DMA_RD_DIS
;
9919 if (tg3_asic_rev(tp
) == ASIC_REV_5784
||
9920 tg3_asic_rev(tp
) == ASIC_REV_5785
||
9921 tg3_asic_rev(tp
) == ASIC_REV_57780
)
9922 rdmac_mode
|= RDMAC_MODE_BD_SBD_CRPT_ENAB
|
9923 RDMAC_MODE_MBUF_RBD_CRPT_ENAB
|
9924 RDMAC_MODE_MBUF_SBD_CRPT_ENAB
;
9926 if (tg3_asic_rev(tp
) == ASIC_REV_5705
&&
9927 tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A0
) {
9928 if (tg3_flag(tp
, TSO_CAPABLE
) &&
9929 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
9930 rdmac_mode
|= RDMAC_MODE_FIFO_SIZE_128
;
9931 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
9932 !tg3_flag(tp
, IS_5788
)) {
9933 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
9937 if (tg3_flag(tp
, PCI_EXPRESS
))
9938 rdmac_mode
|= RDMAC_MODE_FIFO_LONG_BURST
;
9940 if (tg3_asic_rev(tp
) == ASIC_REV_57766
) {
9942 if (tp
->dev
->mtu
<= ETH_DATA_LEN
) {
9943 rdmac_mode
|= RDMAC_MODE_JMB_2K_MMRR
;
9944 tp
->dma_limit
= TG3_TX_BD_DMA_MAX_2K
;
9948 if (tg3_flag(tp
, HW_TSO_1
) ||
9949 tg3_flag(tp
, HW_TSO_2
) ||
9950 tg3_flag(tp
, HW_TSO_3
))
9951 rdmac_mode
|= RDMAC_MODE_IPV4_LSO_EN
;
9953 if (tg3_flag(tp
, 57765_PLUS
) ||
9954 tg3_asic_rev(tp
) == ASIC_REV_5785
||
9955 tg3_asic_rev(tp
) == ASIC_REV_57780
)
9956 rdmac_mode
|= RDMAC_MODE_IPV6_LSO_EN
;
9958 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
9959 tg3_asic_rev(tp
) == ASIC_REV_5762
)
9960 rdmac_mode
|= tr32(RDMAC_MODE
) & RDMAC_MODE_H2BNC_VLAN_DET
;
9962 if (tg3_asic_rev(tp
) == ASIC_REV_5761
||
9963 tg3_asic_rev(tp
) == ASIC_REV_5784
||
9964 tg3_asic_rev(tp
) == ASIC_REV_5785
||
9965 tg3_asic_rev(tp
) == ASIC_REV_57780
||
9966 tg3_flag(tp
, 57765_PLUS
)) {
9969 if (tg3_asic_rev(tp
) == ASIC_REV_5762
)
9970 tgtreg
= TG3_RDMA_RSRVCTRL_REG2
;
9972 tgtreg
= TG3_RDMA_RSRVCTRL_REG
;
9975 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
||
9976 tg3_asic_rev(tp
) == ASIC_REV_5762
) {
9977 val
&= ~(TG3_RDMA_RSRVCTRL_TXMRGN_MASK
|
9978 TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK
|
9979 TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK
);
9980 val
|= TG3_RDMA_RSRVCTRL_TXMRGN_320B
|
9981 TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K
|
9982 TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K
;
9984 tw32(tgtreg
, val
| TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX
);
9987 if (tg3_asic_rev(tp
) == ASIC_REV_5719
||
9988 tg3_asic_rev(tp
) == ASIC_REV_5720
||
9989 tg3_asic_rev(tp
) == ASIC_REV_5762
) {
9992 if (tg3_asic_rev(tp
) == ASIC_REV_5762
)
9993 tgtreg
= TG3_LSO_RD_DMA_CRPTEN_CTRL2
;
9995 tgtreg
= TG3_LSO_RD_DMA_CRPTEN_CTRL
;
9999 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K
|
10000 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K
);
10003 /* Receive/send statistics. */
10004 if (tg3_flag(tp
, 5750_PLUS
)) {
10005 val
= tr32(RCVLPC_STATS_ENABLE
);
10006 val
&= ~RCVLPC_STATSENAB_DACK_FIX
;
10007 tw32(RCVLPC_STATS_ENABLE
, val
);
10008 } else if ((rdmac_mode
& RDMAC_MODE_FIFO_SIZE_128
) &&
10009 tg3_flag(tp
, TSO_CAPABLE
)) {
10010 val
= tr32(RCVLPC_STATS_ENABLE
);
10011 val
&= ~RCVLPC_STATSENAB_LNGBRST_RFIX
;
10012 tw32(RCVLPC_STATS_ENABLE
, val
);
10014 tw32(RCVLPC_STATS_ENABLE
, 0xffffff);
10016 tw32(RCVLPC_STATSCTRL
, RCVLPC_STATSCTRL_ENABLE
);
10017 tw32(SNDDATAI_STATSENAB
, 0xffffff);
10018 tw32(SNDDATAI_STATSCTRL
,
10019 (SNDDATAI_SCTRL_ENABLE
|
10020 SNDDATAI_SCTRL_FASTUPD
));
10022 /* Setup host coalescing engine. */
10023 tw32(HOSTCC_MODE
, 0);
10024 for (i
= 0; i
< 2000; i
++) {
10025 if (!(tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
))
10030 __tg3_set_coalesce(tp
, &tp
->coal
);
10032 if (!tg3_flag(tp
, 5705_PLUS
)) {
10033 /* Status/statistics block address. See tg3_timer,
10034 * the tg3_periodic_fetch_stats call there, and
10035 * tg3_get_stats to see how this works for 5705/5750 chips.
10037 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_HIGH
,
10038 ((u64
) tp
->stats_mapping
>> 32));
10039 tw32(HOSTCC_STATS_BLK_HOST_ADDR
+ TG3_64BIT_REG_LOW
,
10040 ((u64
) tp
->stats_mapping
& 0xffffffff));
10041 tw32(HOSTCC_STATS_BLK_NIC_ADDR
, NIC_SRAM_STATS_BLK
);
10043 tw32(HOSTCC_STATUS_BLK_NIC_ADDR
, NIC_SRAM_STATUS_BLK
);
10045 /* Clear statistics and status block memory areas */
10046 for (i
= NIC_SRAM_STATS_BLK
;
10047 i
< NIC_SRAM_STATUS_BLK
+ TG3_HW_STATUS_SIZE
;
10048 i
+= sizeof(u32
)) {
10049 tg3_write_mem(tp
, i
, 0);
10054 tw32(HOSTCC_MODE
, HOSTCC_MODE_ENABLE
| tp
->coalesce_mode
);
10056 tw32(RCVCC_MODE
, RCVCC_MODE_ENABLE
| RCVCC_MODE_ATTN_ENABLE
);
10057 tw32(RCVLPC_MODE
, RCVLPC_MODE_ENABLE
);
10058 if (!tg3_flag(tp
, 5705_PLUS
))
10059 tw32(RCVLSC_MODE
, RCVLSC_MODE_ENABLE
| RCVLSC_MODE_ATTN_ENABLE
);
10061 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) {
10062 tp
->phy_flags
&= ~TG3_PHYFLG_PARALLEL_DETECT
;
10063 /* reset to prevent losing 1st rx packet intermittently */
10064 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10068 tp
->mac_mode
|= MAC_MODE_TXSTAT_ENABLE
| MAC_MODE_RXSTAT_ENABLE
|
10069 MAC_MODE_TDE_ENABLE
| MAC_MODE_RDE_ENABLE
|
10070 MAC_MODE_FHDE_ENABLE
;
10071 if (tg3_flag(tp
, ENABLE_APE
))
10072 tp
->mac_mode
|= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
10073 if (!tg3_flag(tp
, 5705_PLUS
) &&
10074 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
10075 tg3_asic_rev(tp
) != ASIC_REV_5700
)
10076 tp
->mac_mode
|= MAC_MODE_LINK_POLARITY
;
10077 tw32_f(MAC_MODE
, tp
->mac_mode
| MAC_MODE_RXSTAT_CLEAR
| MAC_MODE_TXSTAT_CLEAR
);
10080 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
10081 * If TG3_FLAG_IS_NIC is zero, we should read the
10082 * register to preserve the GPIO settings for LOMs. The GPIOs,
10083 * whether used as inputs or outputs, are set by boot code after
10086 if (!tg3_flag(tp
, IS_NIC
)) {
10089 gpio_mask
= GRC_LCLCTRL_GPIO_OE0
| GRC_LCLCTRL_GPIO_OE1
|
10090 GRC_LCLCTRL_GPIO_OE2
| GRC_LCLCTRL_GPIO_OUTPUT0
|
10091 GRC_LCLCTRL_GPIO_OUTPUT1
| GRC_LCLCTRL_GPIO_OUTPUT2
;
10093 if (tg3_asic_rev(tp
) == ASIC_REV_5752
)
10094 gpio_mask
|= GRC_LCLCTRL_GPIO_OE3
|
10095 GRC_LCLCTRL_GPIO_OUTPUT3
;
10097 if (tg3_asic_rev(tp
) == ASIC_REV_5755
)
10098 gpio_mask
|= GRC_LCLCTRL_GPIO_UART_SEL
;
10100 tp
->grc_local_ctrl
&= ~gpio_mask
;
10101 tp
->grc_local_ctrl
|= tr32(GRC_LOCAL_CTRL
) & gpio_mask
;
10103 /* GPIO1 must be driven high for eeprom write protect */
10104 if (tg3_flag(tp
, EEPROM_WRITE_PROT
))
10105 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
10106 GRC_LCLCTRL_GPIO_OUTPUT1
);
10108 tw32_f(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
10111 if (tg3_flag(tp
, USING_MSIX
)) {
10112 val
= tr32(MSGINT_MODE
);
10113 val
|= MSGINT_MODE_ENABLE
;
10114 if (tp
->irq_cnt
> 1)
10115 val
|= MSGINT_MODE_MULTIVEC_EN
;
10116 if (!tg3_flag(tp
, 1SHOT_MSI
))
10117 val
|= MSGINT_MODE_ONE_SHOT_DISABLE
;
10118 tw32(MSGINT_MODE
, val
);
10121 if (!tg3_flag(tp
, 5705_PLUS
)) {
10122 tw32_f(DMAC_MODE
, DMAC_MODE_ENABLE
);
10126 val
= (WDMAC_MODE_ENABLE
| WDMAC_MODE_TGTABORT_ENAB
|
10127 WDMAC_MODE_MSTABORT_ENAB
| WDMAC_MODE_PARITYERR_ENAB
|
10128 WDMAC_MODE_ADDROFLOW_ENAB
| WDMAC_MODE_FIFOOFLOW_ENAB
|
10129 WDMAC_MODE_FIFOURUN_ENAB
| WDMAC_MODE_FIFOOREAD_ENAB
|
10130 WDMAC_MODE_LNGREAD_ENAB
);
10132 if (tg3_asic_rev(tp
) == ASIC_REV_5705
&&
10133 tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A0
) {
10134 if (tg3_flag(tp
, TSO_CAPABLE
) &&
10135 (tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A1
||
10136 tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A2
)) {
10138 } else if (!(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
) &&
10139 !tg3_flag(tp
, IS_5788
)) {
10140 val
|= WDMAC_MODE_RX_ACCEL
;
10144 /* Enable host coalescing bug fix */
10145 if (tg3_flag(tp
, 5755_PLUS
))
10146 val
|= WDMAC_MODE_STATUS_TAG_FIX
;
10148 if (tg3_asic_rev(tp
) == ASIC_REV_5785
)
10149 val
|= WDMAC_MODE_BURST_ALL_DATA
;
10151 tw32_f(WDMAC_MODE
, val
);
10154 if (tg3_flag(tp
, PCIX_MODE
)) {
10157 pci_read_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
10159 if (tg3_asic_rev(tp
) == ASIC_REV_5703
) {
10160 pcix_cmd
&= ~PCI_X_CMD_MAX_READ
;
10161 pcix_cmd
|= PCI_X_CMD_READ_2K
;
10162 } else if (tg3_asic_rev(tp
) == ASIC_REV_5704
) {
10163 pcix_cmd
&= ~(PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
);
10164 pcix_cmd
|= PCI_X_CMD_READ_2K
;
10166 pci_write_config_word(tp
->pdev
, tp
->pcix_cap
+ PCI_X_CMD
,
10170 tw32_f(RDMAC_MODE
, rdmac_mode
);
10173 if (tg3_asic_rev(tp
) == ASIC_REV_5719
) {
10174 for (i
= 0; i
< TG3_NUM_RDMA_CHANNELS
; i
++) {
10175 if (tr32(TG3_RDMA_LENGTH
+ (i
<< 2)) > TG3_MAX_MTU(tp
))
10178 if (i
< TG3_NUM_RDMA_CHANNELS
) {
10179 val
= tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL
);
10180 val
|= TG3_LSO_RD_DMA_TX_LENGTH_WA
;
10181 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL
, val
);
10182 tg3_flag_set(tp
, 5719_RDMA_BUG
);
10186 tw32(RCVDCC_MODE
, RCVDCC_MODE_ENABLE
| RCVDCC_MODE_ATTN_ENABLE
);
10187 if (!tg3_flag(tp
, 5705_PLUS
))
10188 tw32(MBFREE_MODE
, MBFREE_MODE_ENABLE
);
10190 if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
10191 tw32(SNDDATAC_MODE
,
10192 SNDDATAC_MODE_ENABLE
| SNDDATAC_MODE_CDELAY
);
10194 tw32(SNDDATAC_MODE
, SNDDATAC_MODE_ENABLE
);
10196 tw32(SNDBDC_MODE
, SNDBDC_MODE_ENABLE
| SNDBDC_MODE_ATTN_ENABLE
);
10197 tw32(RCVBDI_MODE
, RCVBDI_MODE_ENABLE
| RCVBDI_MODE_RCB_ATTN_ENAB
);
10198 val
= RCVDBDI_MODE_ENABLE
| RCVDBDI_MODE_INV_RING_SZ
;
10199 if (tg3_flag(tp
, LRG_PROD_RING_CAP
))
10200 val
|= RCVDBDI_MODE_LRG_RING_SZ
;
10201 tw32(RCVDBDI_MODE
, val
);
10202 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
);
10203 if (tg3_flag(tp
, HW_TSO_1
) ||
10204 tg3_flag(tp
, HW_TSO_2
) ||
10205 tg3_flag(tp
, HW_TSO_3
))
10206 tw32(SNDDATAI_MODE
, SNDDATAI_MODE_ENABLE
| 0x8);
10207 val
= SNDBDI_MODE_ENABLE
| SNDBDI_MODE_ATTN_ENABLE
;
10208 if (tg3_flag(tp
, ENABLE_TSS
))
10209 val
|= SNDBDI_MODE_MULTI_TXQ_EN
;
10210 tw32(SNDBDI_MODE
, val
);
10211 tw32(SNDBDS_MODE
, SNDBDS_MODE_ENABLE
| SNDBDS_MODE_ATTN_ENABLE
);
10213 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
) {
10214 err
= tg3_load_5701_a0_firmware_fix(tp
);
10219 if (tg3_asic_rev(tp
) == ASIC_REV_57766
) {
10220 /* Ignore any errors for the firmware download. If download
10221 * fails, the device will operate with EEE disabled
10223 tg3_load_57766_firmware(tp
);
10226 if (tg3_flag(tp
, TSO_CAPABLE
)) {
10227 err
= tg3_load_tso_firmware(tp
);
10232 tp
->tx_mode
= TX_MODE_ENABLE
;
10234 if (tg3_flag(tp
, 5755_PLUS
) ||
10235 tg3_asic_rev(tp
) == ASIC_REV_5906
)
10236 tp
->tx_mode
|= TX_MODE_MBUF_LOCKUP_FIX
;
10238 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
10239 tg3_asic_rev(tp
) == ASIC_REV_5762
) {
10240 val
= TX_MODE_JMB_FRM_LEN
| TX_MODE_CNT_DN_MODE
;
10241 tp
->tx_mode
&= ~val
;
10242 tp
->tx_mode
|= tr32(MAC_TX_MODE
) & val
;
10245 tw32_f(MAC_TX_MODE
, tp
->tx_mode
);
10248 if (tg3_flag(tp
, ENABLE_RSS
)) {
10249 tg3_rss_write_indir_tbl(tp
);
10251 /* Setup the "secret" hash key. */
10252 tw32(MAC_RSS_HASH_KEY_0
, 0x5f865437);
10253 tw32(MAC_RSS_HASH_KEY_1
, 0xe4ac62cc);
10254 tw32(MAC_RSS_HASH_KEY_2
, 0x50103a45);
10255 tw32(MAC_RSS_HASH_KEY_3
, 0x36621985);
10256 tw32(MAC_RSS_HASH_KEY_4
, 0xbf14c0e8);
10257 tw32(MAC_RSS_HASH_KEY_5
, 0x1bc27a1e);
10258 tw32(MAC_RSS_HASH_KEY_6
, 0x84f4b556);
10259 tw32(MAC_RSS_HASH_KEY_7
, 0x094ea6fe);
10260 tw32(MAC_RSS_HASH_KEY_8
, 0x7dda01e7);
10261 tw32(MAC_RSS_HASH_KEY_9
, 0xc04d7481);
10264 tp
->rx_mode
= RX_MODE_ENABLE
;
10265 if (tg3_flag(tp
, 5755_PLUS
))
10266 tp
->rx_mode
|= RX_MODE_IPV6_CSUM_ENABLE
;
10268 if (tg3_flag(tp
, ENABLE_RSS
))
10269 tp
->rx_mode
|= RX_MODE_RSS_ENABLE
|
10270 RX_MODE_RSS_ITBL_HASH_BITS_7
|
10271 RX_MODE_RSS_IPV6_HASH_EN
|
10272 RX_MODE_RSS_TCP_IPV6_HASH_EN
|
10273 RX_MODE_RSS_IPV4_HASH_EN
|
10274 RX_MODE_RSS_TCP_IPV4_HASH_EN
;
10276 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10279 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
10281 tw32(MAC_MI_STAT
, MAC_MI_STAT_LNKSTAT_ATTN_ENAB
);
10282 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
10283 tw32_f(MAC_RX_MODE
, RX_MODE_RESET
);
10286 tw32_f(MAC_RX_MODE
, tp
->rx_mode
);
10289 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
10290 if ((tg3_asic_rev(tp
) == ASIC_REV_5704
) &&
10291 !(tp
->phy_flags
& TG3_PHYFLG_SERDES_PREEMPHASIS
)) {
10292 /* Set drive transmission level to 1.2V */
10293 /* only if the signal pre-emphasis bit is not set */
10294 val
= tr32(MAC_SERDES_CFG
);
10297 tw32(MAC_SERDES_CFG
, val
);
10299 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5703_A1
)
10300 tw32(MAC_SERDES_CFG
, 0x616000);
10303 /* Prevent chip from dropping frames when flow control
10306 if (tg3_flag(tp
, 57765_CLASS
))
10310 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME
, val
);
10312 if (tg3_asic_rev(tp
) == ASIC_REV_5704
&&
10313 (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
10314 /* Use hardware link auto-negotiation */
10315 tg3_flag_set(tp
, HW_AUTONEG
);
10318 if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
10319 tg3_asic_rev(tp
) == ASIC_REV_5714
) {
10322 tmp
= tr32(SERDES_RX_CTRL
);
10323 tw32(SERDES_RX_CTRL
, tmp
| SERDES_RX_SIG_DETECT
);
10324 tp
->grc_local_ctrl
&= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT
;
10325 tp
->grc_local_ctrl
|= GRC_LCLCTRL_USE_SIG_DETECT
;
10326 tw32(GRC_LOCAL_CTRL
, tp
->grc_local_ctrl
);
10329 if (!tg3_flag(tp
, USE_PHYLIB
)) {
10330 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
10331 tp
->phy_flags
&= ~TG3_PHYFLG_IS_LOW_POWER
;
10333 err
= tg3_setup_phy(tp
, false);
10337 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
10338 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
)) {
10341 /* Clear CRC stats. */
10342 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &tmp
)) {
10343 tg3_writephy(tp
, MII_TG3_TEST1
,
10344 tmp
| MII_TG3_TEST1_CRC_EN
);
10345 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &tmp
);
10350 __tg3_set_rx_mode(tp
->dev
);
10352 /* Initialize receive rules. */
10353 tw32(MAC_RCV_RULE_0
, 0xc2000000 & RCV_RULE_DISABLE_MASK
);
10354 tw32(MAC_RCV_VALUE_0
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
10355 tw32(MAC_RCV_RULE_1
, 0x86000004 & RCV_RULE_DISABLE_MASK
);
10356 tw32(MAC_RCV_VALUE_1
, 0xffffffff & RCV_RULE_DISABLE_MASK
);
10358 if (tg3_flag(tp
, 5705_PLUS
) && !tg3_flag(tp
, 5780_CLASS
))
10362 if (tg3_flag(tp
, ENABLE_ASF
))
10366 tw32(MAC_RCV_RULE_15
, 0); tw32(MAC_RCV_VALUE_15
, 0);
10368 tw32(MAC_RCV_RULE_14
, 0); tw32(MAC_RCV_VALUE_14
, 0);
10370 tw32(MAC_RCV_RULE_13
, 0); tw32(MAC_RCV_VALUE_13
, 0);
10372 tw32(MAC_RCV_RULE_12
, 0); tw32(MAC_RCV_VALUE_12
, 0);
10374 tw32(MAC_RCV_RULE_11
, 0); tw32(MAC_RCV_VALUE_11
, 0);
10376 tw32(MAC_RCV_RULE_10
, 0); tw32(MAC_RCV_VALUE_10
, 0);
10378 tw32(MAC_RCV_RULE_9
, 0); tw32(MAC_RCV_VALUE_9
, 0);
10380 tw32(MAC_RCV_RULE_8
, 0); tw32(MAC_RCV_VALUE_8
, 0);
10382 tw32(MAC_RCV_RULE_7
, 0); tw32(MAC_RCV_VALUE_7
, 0);
10384 tw32(MAC_RCV_RULE_6
, 0); tw32(MAC_RCV_VALUE_6
, 0);
10386 tw32(MAC_RCV_RULE_5
, 0); tw32(MAC_RCV_VALUE_5
, 0);
10388 tw32(MAC_RCV_RULE_4
, 0); tw32(MAC_RCV_VALUE_4
, 0);
10390 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
10392 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
10400 if (tg3_flag(tp
, ENABLE_APE
))
10401 /* Write our heartbeat update interval to APE. */
10402 tg3_ape_write32(tp
, TG3_APE_HOST_HEARTBEAT_INT_MS
,
10403 APE_HOST_HEARTBEAT_INT_DISABLE
);
10405 tg3_write_sig_post_reset(tp
, RESET_KIND_INIT
);
10410 /* Called at device open time to get the chip ready for
10411 * packet processing. Invoked with tp->lock held.
10413 static int tg3_init_hw(struct tg3
*tp
, bool reset_phy
)
10415 tg3_switch_clocks(tp
);
10417 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
10419 return tg3_reset_hw(tp
, reset_phy
);
10422 static void tg3_sd_scan_scratchpad(struct tg3
*tp
, struct tg3_ocir
*ocir
)
10426 for (i
= 0; i
< TG3_SD_NUM_RECS
; i
++, ocir
++) {
10427 u32 off
= i
* TG3_OCIR_LEN
, len
= TG3_OCIR_LEN
;
10429 tg3_ape_scratchpad_read(tp
, (u32
*) ocir
, off
, len
);
10432 if (ocir
->signature
!= TG3_OCIR_SIG_MAGIC
||
10433 !(ocir
->version_flags
& TG3_OCIR_FLAG_ACTIVE
))
10434 memset(ocir
, 0, TG3_OCIR_LEN
);
10438 /* sysfs attributes for hwmon */
10439 static ssize_t
tg3_show_temp(struct device
*dev
,
10440 struct device_attribute
*devattr
, char *buf
)
10442 struct pci_dev
*pdev
= to_pci_dev(dev
);
10443 struct net_device
*netdev
= pci_get_drvdata(pdev
);
10444 struct tg3
*tp
= netdev_priv(netdev
);
10445 struct sensor_device_attribute
*attr
= to_sensor_dev_attr(devattr
);
10448 spin_lock_bh(&tp
->lock
);
10449 tg3_ape_scratchpad_read(tp
, &temperature
, attr
->index
,
10450 sizeof(temperature
));
10451 spin_unlock_bh(&tp
->lock
);
10452 return sprintf(buf
, "%u\n", temperature
);
10456 static SENSOR_DEVICE_ATTR(temp1_input
, S_IRUGO
, tg3_show_temp
, NULL
,
10457 TG3_TEMP_SENSOR_OFFSET
);
10458 static SENSOR_DEVICE_ATTR(temp1_crit
, S_IRUGO
, tg3_show_temp
, NULL
,
10459 TG3_TEMP_CAUTION_OFFSET
);
10460 static SENSOR_DEVICE_ATTR(temp1_max
, S_IRUGO
, tg3_show_temp
, NULL
,
10461 TG3_TEMP_MAX_OFFSET
);
10463 static struct attribute
*tg3_attributes
[] = {
10464 &sensor_dev_attr_temp1_input
.dev_attr
.attr
,
10465 &sensor_dev_attr_temp1_crit
.dev_attr
.attr
,
10466 &sensor_dev_attr_temp1_max
.dev_attr
.attr
,
10470 static const struct attribute_group tg3_group
= {
10471 .attrs
= tg3_attributes
,
10474 static void tg3_hwmon_close(struct tg3
*tp
)
10476 if (tp
->hwmon_dev
) {
10477 hwmon_device_unregister(tp
->hwmon_dev
);
10478 tp
->hwmon_dev
= NULL
;
10479 sysfs_remove_group(&tp
->pdev
->dev
.kobj
, &tg3_group
);
10483 static void tg3_hwmon_open(struct tg3
*tp
)
10487 struct pci_dev
*pdev
= tp
->pdev
;
10488 struct tg3_ocir ocirs
[TG3_SD_NUM_RECS
];
10490 tg3_sd_scan_scratchpad(tp
, ocirs
);
10492 for (i
= 0; i
< TG3_SD_NUM_RECS
; i
++) {
10493 if (!ocirs
[i
].src_data_length
)
10496 size
+= ocirs
[i
].src_hdr_length
;
10497 size
+= ocirs
[i
].src_data_length
;
10503 /* Register hwmon sysfs hooks */
10504 err
= sysfs_create_group(&pdev
->dev
.kobj
, &tg3_group
);
10506 dev_err(&pdev
->dev
, "Cannot create sysfs group, aborting\n");
10510 tp
->hwmon_dev
= hwmon_device_register(&pdev
->dev
);
10511 if (IS_ERR(tp
->hwmon_dev
)) {
10512 tp
->hwmon_dev
= NULL
;
10513 dev_err(&pdev
->dev
, "Cannot register hwmon device, aborting\n");
10514 sysfs_remove_group(&pdev
->dev
.kobj
, &tg3_group
);
10519 #define TG3_STAT_ADD32(PSTAT, REG) \
10520 do { u32 __val = tr32(REG); \
10521 (PSTAT)->low += __val; \
10522 if ((PSTAT)->low < __val) \
10523 (PSTAT)->high += 1; \
10526 static void tg3_periodic_fetch_stats(struct tg3
*tp
)
10528 struct tg3_hw_stats
*sp
= tp
->hw_stats
;
10533 TG3_STAT_ADD32(&sp
->tx_octets
, MAC_TX_STATS_OCTETS
);
10534 TG3_STAT_ADD32(&sp
->tx_collisions
, MAC_TX_STATS_COLLISIONS
);
10535 TG3_STAT_ADD32(&sp
->tx_xon_sent
, MAC_TX_STATS_XON_SENT
);
10536 TG3_STAT_ADD32(&sp
->tx_xoff_sent
, MAC_TX_STATS_XOFF_SENT
);
10537 TG3_STAT_ADD32(&sp
->tx_mac_errors
, MAC_TX_STATS_MAC_ERRORS
);
10538 TG3_STAT_ADD32(&sp
->tx_single_collisions
, MAC_TX_STATS_SINGLE_COLLISIONS
);
10539 TG3_STAT_ADD32(&sp
->tx_mult_collisions
, MAC_TX_STATS_MULT_COLLISIONS
);
10540 TG3_STAT_ADD32(&sp
->tx_deferred
, MAC_TX_STATS_DEFERRED
);
10541 TG3_STAT_ADD32(&sp
->tx_excessive_collisions
, MAC_TX_STATS_EXCESSIVE_COL
);
10542 TG3_STAT_ADD32(&sp
->tx_late_collisions
, MAC_TX_STATS_LATE_COL
);
10543 TG3_STAT_ADD32(&sp
->tx_ucast_packets
, MAC_TX_STATS_UCAST
);
10544 TG3_STAT_ADD32(&sp
->tx_mcast_packets
, MAC_TX_STATS_MCAST
);
10545 TG3_STAT_ADD32(&sp
->tx_bcast_packets
, MAC_TX_STATS_BCAST
);
10546 if (unlikely(tg3_flag(tp
, 5719_RDMA_BUG
) &&
10547 (sp
->tx_ucast_packets
.low
+ sp
->tx_mcast_packets
.low
+
10548 sp
->tx_bcast_packets
.low
) > TG3_NUM_RDMA_CHANNELS
)) {
10551 val
= tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL
);
10552 val
&= ~TG3_LSO_RD_DMA_TX_LENGTH_WA
;
10553 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL
, val
);
10554 tg3_flag_clear(tp
, 5719_RDMA_BUG
);
10557 TG3_STAT_ADD32(&sp
->rx_octets
, MAC_RX_STATS_OCTETS
);
10558 TG3_STAT_ADD32(&sp
->rx_fragments
, MAC_RX_STATS_FRAGMENTS
);
10559 TG3_STAT_ADD32(&sp
->rx_ucast_packets
, MAC_RX_STATS_UCAST
);
10560 TG3_STAT_ADD32(&sp
->rx_mcast_packets
, MAC_RX_STATS_MCAST
);
10561 TG3_STAT_ADD32(&sp
->rx_bcast_packets
, MAC_RX_STATS_BCAST
);
10562 TG3_STAT_ADD32(&sp
->rx_fcs_errors
, MAC_RX_STATS_FCS_ERRORS
);
10563 TG3_STAT_ADD32(&sp
->rx_align_errors
, MAC_RX_STATS_ALIGN_ERRORS
);
10564 TG3_STAT_ADD32(&sp
->rx_xon_pause_rcvd
, MAC_RX_STATS_XON_PAUSE_RECVD
);
10565 TG3_STAT_ADD32(&sp
->rx_xoff_pause_rcvd
, MAC_RX_STATS_XOFF_PAUSE_RECVD
);
10566 TG3_STAT_ADD32(&sp
->rx_mac_ctrl_rcvd
, MAC_RX_STATS_MAC_CTRL_RECVD
);
10567 TG3_STAT_ADD32(&sp
->rx_xoff_entered
, MAC_RX_STATS_XOFF_ENTERED
);
10568 TG3_STAT_ADD32(&sp
->rx_frame_too_long_errors
, MAC_RX_STATS_FRAME_TOO_LONG
);
10569 TG3_STAT_ADD32(&sp
->rx_jabbers
, MAC_RX_STATS_JABBERS
);
10570 TG3_STAT_ADD32(&sp
->rx_undersize_packets
, MAC_RX_STATS_UNDERSIZE
);
10572 TG3_STAT_ADD32(&sp
->rxbds_empty
, RCVLPC_NO_RCV_BD_CNT
);
10573 if (tg3_asic_rev(tp
) != ASIC_REV_5717
&&
10574 tg3_chip_rev_id(tp
) != CHIPREV_ID_5719_A0
&&
10575 tg3_chip_rev_id(tp
) != CHIPREV_ID_5720_A0
) {
10576 TG3_STAT_ADD32(&sp
->rx_discards
, RCVLPC_IN_DISCARDS_CNT
);
10578 u32 val
= tr32(HOSTCC_FLOW_ATTN
);
10579 val
= (val
& HOSTCC_FLOW_ATTN_MBUF_LWM
) ? 1 : 0;
10581 tw32(HOSTCC_FLOW_ATTN
, HOSTCC_FLOW_ATTN_MBUF_LWM
);
10582 sp
->rx_discards
.low
+= val
;
10583 if (sp
->rx_discards
.low
< val
)
10584 sp
->rx_discards
.high
+= 1;
10586 sp
->mbuf_lwm_thresh_hit
= sp
->rx_discards
;
10588 TG3_STAT_ADD32(&sp
->rx_errors
, RCVLPC_IN_ERRORS_CNT
);
10591 static void tg3_chk_missed_msi(struct tg3
*tp
)
10595 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
10596 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
10598 if (tg3_has_work(tnapi
)) {
10599 if (tnapi
->last_rx_cons
== tnapi
->rx_rcb_ptr
&&
10600 tnapi
->last_tx_cons
== tnapi
->tx_cons
) {
10601 if (tnapi
->chk_msi_cnt
< 1) {
10602 tnapi
->chk_msi_cnt
++;
10608 tnapi
->chk_msi_cnt
= 0;
10609 tnapi
->last_rx_cons
= tnapi
->rx_rcb_ptr
;
10610 tnapi
->last_tx_cons
= tnapi
->tx_cons
;
10614 static void tg3_timer(unsigned long __opaque
)
10616 struct tg3
*tp
= (struct tg3
*) __opaque
;
10618 if (tp
->irq_sync
|| tg3_flag(tp
, RESET_TASK_PENDING
))
10619 goto restart_timer
;
10621 spin_lock(&tp
->lock
);
10623 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
10624 tg3_flag(tp
, 57765_CLASS
))
10625 tg3_chk_missed_msi(tp
);
10627 if (tg3_flag(tp
, FLUSH_POSTED_WRITES
)) {
10628 /* BCM4785: Flush posted writes from GbE to host memory. */
10632 if (!tg3_flag(tp
, TAGGED_STATUS
)) {
10633 /* All of this garbage is because when using non-tagged
10634 * IRQ status the mailbox/status_block protocol the chip
10635 * uses with the cpu is race prone.
10637 if (tp
->napi
[0].hw_status
->status
& SD_STATUS_UPDATED
) {
10638 tw32(GRC_LOCAL_CTRL
,
10639 tp
->grc_local_ctrl
| GRC_LCLCTRL_SETINT
);
10641 tw32(HOSTCC_MODE
, tp
->coalesce_mode
|
10642 HOSTCC_MODE_ENABLE
| HOSTCC_MODE_NOW
);
10645 if (!(tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
10646 spin_unlock(&tp
->lock
);
10647 tg3_reset_task_schedule(tp
);
10648 goto restart_timer
;
10652 /* This part only runs once per second. */
10653 if (!--tp
->timer_counter
) {
10654 if (tg3_flag(tp
, 5705_PLUS
))
10655 tg3_periodic_fetch_stats(tp
);
10657 if (tp
->setlpicnt
&& !--tp
->setlpicnt
)
10658 tg3_phy_eee_enable(tp
);
10660 if (tg3_flag(tp
, USE_LINKCHG_REG
)) {
10664 mac_stat
= tr32(MAC_STATUS
);
10667 if (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) {
10668 if (mac_stat
& MAC_STATUS_MI_INTERRUPT
)
10670 } else if (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)
10674 tg3_setup_phy(tp
, false);
10675 } else if (tg3_flag(tp
, POLL_SERDES
)) {
10676 u32 mac_stat
= tr32(MAC_STATUS
);
10677 int need_setup
= 0;
10680 (mac_stat
& MAC_STATUS_LNKSTATE_CHANGED
)) {
10683 if (!tp
->link_up
&&
10684 (mac_stat
& (MAC_STATUS_PCS_SYNCED
|
10685 MAC_STATUS_SIGNAL_DET
))) {
10689 if (!tp
->serdes_counter
) {
10692 ~MAC_MODE_PORT_MODE_MASK
));
10694 tw32_f(MAC_MODE
, tp
->mac_mode
);
10697 tg3_setup_phy(tp
, false);
10699 } else if ((tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
) &&
10700 tg3_flag(tp
, 5780_CLASS
)) {
10701 tg3_serdes_parallel_detect(tp
);
10704 tp
->timer_counter
= tp
->timer_multiplier
;
10707 /* Heartbeat is only sent once every 2 seconds.
10709 * The heartbeat is to tell the ASF firmware that the host
10710 * driver is still alive. In the event that the OS crashes,
10711 * ASF needs to reset the hardware to free up the FIFO space
10712 * that may be filled with rx packets destined for the host.
10713 * If the FIFO is full, ASF will no longer function properly.
10715 * Unintended resets have been reported on real time kernels
10716 * where the timer doesn't run on time. Netpoll will also have
10719 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
10720 * to check the ring condition when the heartbeat is expiring
10721 * before doing the reset. This will prevent most unintended
10724 if (!--tp
->asf_counter
) {
10725 if (tg3_flag(tp
, ENABLE_ASF
) && !tg3_flag(tp
, ENABLE_APE
)) {
10726 tg3_wait_for_event_ack(tp
);
10728 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_MBOX
,
10729 FWCMD_NICDRV_ALIVE3
);
10730 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_LEN_MBOX
, 4);
10731 tg3_write_mem(tp
, NIC_SRAM_FW_CMD_DATA_MBOX
,
10732 TG3_FW_UPDATE_TIMEOUT_SEC
);
10734 tg3_generate_fw_event(tp
);
10736 tp
->asf_counter
= tp
->asf_multiplier
;
10739 spin_unlock(&tp
->lock
);
10742 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
10743 add_timer(&tp
->timer
);
10746 static void tg3_timer_init(struct tg3
*tp
)
10748 if (tg3_flag(tp
, TAGGED_STATUS
) &&
10749 tg3_asic_rev(tp
) != ASIC_REV_5717
&&
10750 !tg3_flag(tp
, 57765_CLASS
))
10751 tp
->timer_offset
= HZ
;
10753 tp
->timer_offset
= HZ
/ 10;
10755 BUG_ON(tp
->timer_offset
> HZ
);
10757 tp
->timer_multiplier
= (HZ
/ tp
->timer_offset
);
10758 tp
->asf_multiplier
= (HZ
/ tp
->timer_offset
) *
10759 TG3_FW_UPDATE_FREQ_SEC
;
10761 init_timer(&tp
->timer
);
10762 tp
->timer
.data
= (unsigned long) tp
;
10763 tp
->timer
.function
= tg3_timer
;
10766 static void tg3_timer_start(struct tg3
*tp
)
10768 tp
->asf_counter
= tp
->asf_multiplier
;
10769 tp
->timer_counter
= tp
->timer_multiplier
;
10771 tp
->timer
.expires
= jiffies
+ tp
->timer_offset
;
10772 add_timer(&tp
->timer
);
10775 static void tg3_timer_stop(struct tg3
*tp
)
10777 del_timer_sync(&tp
->timer
);
10780 /* Restart hardware after configuration changes, self-test, etc.
10781 * Invoked with tp->lock held.
10783 static int tg3_restart_hw(struct tg3
*tp
, bool reset_phy
)
10784 __releases(tp
->lock
)
10785 __acquires(tp
->lock
)
10789 err
= tg3_init_hw(tp
, reset_phy
);
10791 netdev_err(tp
->dev
,
10792 "Failed to re-initialize device, aborting\n");
10793 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
10794 tg3_full_unlock(tp
);
10795 tg3_timer_stop(tp
);
10797 tg3_napi_enable(tp
);
10798 dev_close(tp
->dev
);
10799 tg3_full_lock(tp
, 0);
10804 static void tg3_reset_task(struct work_struct
*work
)
10806 struct tg3
*tp
= container_of(work
, struct tg3
, reset_task
);
10809 tg3_full_lock(tp
, 0);
10811 if (!netif_running(tp
->dev
)) {
10812 tg3_flag_clear(tp
, RESET_TASK_PENDING
);
10813 tg3_full_unlock(tp
);
10817 tg3_full_unlock(tp
);
10821 tg3_netif_stop(tp
);
10823 tg3_full_lock(tp
, 1);
10825 if (tg3_flag(tp
, TX_RECOVERY_PENDING
)) {
10826 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
10827 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
10828 tg3_flag_set(tp
, MBOX_WRITE_REORDER
);
10829 tg3_flag_clear(tp
, TX_RECOVERY_PENDING
);
10832 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
10833 err
= tg3_init_hw(tp
, true);
10837 tg3_netif_start(tp
);
10840 tg3_full_unlock(tp
);
10845 tg3_flag_clear(tp
, RESET_TASK_PENDING
);
10848 static int tg3_request_irq(struct tg3
*tp
, int irq_num
)
10851 unsigned long flags
;
10853 struct tg3_napi
*tnapi
= &tp
->napi
[irq_num
];
10855 if (tp
->irq_cnt
== 1)
10856 name
= tp
->dev
->name
;
10858 name
= &tnapi
->irq_lbl
[0];
10859 snprintf(name
, IFNAMSIZ
, "%s-%d", tp
->dev
->name
, irq_num
);
10860 name
[IFNAMSIZ
-1] = 0;
10863 if (tg3_flag(tp
, USING_MSI
) || tg3_flag(tp
, USING_MSIX
)) {
10865 if (tg3_flag(tp
, 1SHOT_MSI
))
10866 fn
= tg3_msi_1shot
;
10869 fn
= tg3_interrupt
;
10870 if (tg3_flag(tp
, TAGGED_STATUS
))
10871 fn
= tg3_interrupt_tagged
;
10872 flags
= IRQF_SHARED
;
10875 return request_irq(tnapi
->irq_vec
, fn
, flags
, name
, tnapi
);
10878 static int tg3_test_interrupt(struct tg3
*tp
)
10880 struct tg3_napi
*tnapi
= &tp
->napi
[0];
10881 struct net_device
*dev
= tp
->dev
;
10882 int err
, i
, intr_ok
= 0;
10885 if (!netif_running(dev
))
10888 tg3_disable_ints(tp
);
10890 free_irq(tnapi
->irq_vec
, tnapi
);
10893 * Turn off MSI one shot mode. Otherwise this test has no
10894 * observable way to know whether the interrupt was delivered.
10896 if (tg3_flag(tp
, 57765_PLUS
)) {
10897 val
= tr32(MSGINT_MODE
) | MSGINT_MODE_ONE_SHOT_DISABLE
;
10898 tw32(MSGINT_MODE
, val
);
10901 err
= request_irq(tnapi
->irq_vec
, tg3_test_isr
,
10902 IRQF_SHARED
, dev
->name
, tnapi
);
10906 tnapi
->hw_status
->status
&= ~SD_STATUS_UPDATED
;
10907 tg3_enable_ints(tp
);
10909 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
10912 for (i
= 0; i
< 5; i
++) {
10913 u32 int_mbox
, misc_host_ctrl
;
10915 int_mbox
= tr32_mailbox(tnapi
->int_mbox
);
10916 misc_host_ctrl
= tr32(TG3PCI_MISC_HOST_CTRL
);
10918 if ((int_mbox
!= 0) ||
10919 (misc_host_ctrl
& MISC_HOST_CTRL_MASK_PCI_INT
)) {
10924 if (tg3_flag(tp
, 57765_PLUS
) &&
10925 tnapi
->hw_status
->status_tag
!= tnapi
->last_tag
)
10926 tw32_mailbox_f(tnapi
->int_mbox
, tnapi
->last_tag
<< 24);
10931 tg3_disable_ints(tp
);
10933 free_irq(tnapi
->irq_vec
, tnapi
);
10935 err
= tg3_request_irq(tp
, 0);
10941 /* Reenable MSI one shot mode. */
10942 if (tg3_flag(tp
, 57765_PLUS
) && tg3_flag(tp
, 1SHOT_MSI
)) {
10943 val
= tr32(MSGINT_MODE
) & ~MSGINT_MODE_ONE_SHOT_DISABLE
;
10944 tw32(MSGINT_MODE
, val
);
10952 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
10953 * successfully restored
10955 static int tg3_test_msi(struct tg3
*tp
)
10960 if (!tg3_flag(tp
, USING_MSI
))
10963 /* Turn off SERR reporting in case MSI terminates with Master
10966 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
10967 pci_write_config_word(tp
->pdev
, PCI_COMMAND
,
10968 pci_cmd
& ~PCI_COMMAND_SERR
);
10970 err
= tg3_test_interrupt(tp
);
10972 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
10977 /* other failures */
10981 /* MSI test failed, go back to INTx mode */
10982 netdev_warn(tp
->dev
, "No interrupt was generated using MSI. Switching "
10983 "to INTx mode. Please report this failure to the PCI "
10984 "maintainer and include system chipset information\n");
10986 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
10988 pci_disable_msi(tp
->pdev
);
10990 tg3_flag_clear(tp
, USING_MSI
);
10991 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
10993 err
= tg3_request_irq(tp
, 0);
10997 /* Need to reset the chip because the MSI cycle may have terminated
10998 * with Master Abort.
11000 tg3_full_lock(tp
, 1);
11002 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11003 err
= tg3_init_hw(tp
, true);
11005 tg3_full_unlock(tp
);
11008 free_irq(tp
->napi
[0].irq_vec
, &tp
->napi
[0]);
11013 static int tg3_request_firmware(struct tg3
*tp
)
11015 const struct tg3_firmware_hdr
*fw_hdr
;
11017 if (request_firmware(&tp
->fw
, tp
->fw_needed
, &tp
->pdev
->dev
)) {
11018 netdev_err(tp
->dev
, "Failed to load firmware \"%s\"\n",
11023 fw_hdr
= (struct tg3_firmware_hdr
*)tp
->fw
->data
;
11025 /* Firmware blob starts with version numbers, followed by
11026 * start address and _full_ length including BSS sections
11027 * (which must be longer than the actual data, of course
11030 tp
->fw_len
= be32_to_cpu(fw_hdr
->len
); /* includes bss */
11031 if (tp
->fw_len
< (tp
->fw
->size
- TG3_FW_HDR_LEN
)) {
11032 netdev_err(tp
->dev
, "bogus length %d in \"%s\"\n",
11033 tp
->fw_len
, tp
->fw_needed
);
11034 release_firmware(tp
->fw
);
11039 /* We no longer need firmware; we have it. */
11040 tp
->fw_needed
= NULL
;
11044 static u32
tg3_irq_count(struct tg3
*tp
)
11046 u32 irq_cnt
= max(tp
->rxq_cnt
, tp
->txq_cnt
);
11049 /* We want as many rx rings enabled as there are cpus.
11050 * In multiqueue MSI-X mode, the first MSI-X vector
11051 * only deals with link interrupts, etc, so we add
11052 * one to the number of vectors we are requesting.
11054 irq_cnt
= min_t(unsigned, irq_cnt
+ 1, tp
->irq_max
);
11060 static bool tg3_enable_msix(struct tg3
*tp
)
11063 struct msix_entry msix_ent
[TG3_IRQ_MAX_VECS
];
11065 tp
->txq_cnt
= tp
->txq_req
;
11066 tp
->rxq_cnt
= tp
->rxq_req
;
11068 tp
->rxq_cnt
= netif_get_num_default_rss_queues();
11069 if (tp
->rxq_cnt
> tp
->rxq_max
)
11070 tp
->rxq_cnt
= tp
->rxq_max
;
11072 /* Disable multiple TX rings by default. Simple round-robin hardware
11073 * scheduling of the TX rings can cause starvation of rings with
11074 * small packets when other rings have TSO or jumbo packets.
11079 tp
->irq_cnt
= tg3_irq_count(tp
);
11081 for (i
= 0; i
< tp
->irq_max
; i
++) {
11082 msix_ent
[i
].entry
= i
;
11083 msix_ent
[i
].vector
= 0;
11086 rc
= pci_enable_msix(tp
->pdev
, msix_ent
, tp
->irq_cnt
);
11089 } else if (rc
!= 0) {
11090 if (pci_enable_msix(tp
->pdev
, msix_ent
, rc
))
11092 netdev_notice(tp
->dev
, "Requested %d MSI-X vectors, received %d\n",
11095 tp
->rxq_cnt
= max(rc
- 1, 1);
11097 tp
->txq_cnt
= min(tp
->rxq_cnt
, tp
->txq_max
);
11100 for (i
= 0; i
< tp
->irq_max
; i
++)
11101 tp
->napi
[i
].irq_vec
= msix_ent
[i
].vector
;
11103 if (netif_set_real_num_rx_queues(tp
->dev
, tp
->rxq_cnt
)) {
11104 pci_disable_msix(tp
->pdev
);
11108 if (tp
->irq_cnt
== 1)
11111 tg3_flag_set(tp
, ENABLE_RSS
);
11113 if (tp
->txq_cnt
> 1)
11114 tg3_flag_set(tp
, ENABLE_TSS
);
11116 netif_set_real_num_tx_queues(tp
->dev
, tp
->txq_cnt
);
11121 static void tg3_ints_init(struct tg3
*tp
)
11123 if ((tg3_flag(tp
, SUPPORT_MSI
) || tg3_flag(tp
, SUPPORT_MSIX
)) &&
11124 !tg3_flag(tp
, TAGGED_STATUS
)) {
11125 /* All MSI supporting chips should support tagged
11126 * status. Assert that this is the case.
11128 netdev_warn(tp
->dev
,
11129 "MSI without TAGGED_STATUS? Not using MSI\n");
11133 if (tg3_flag(tp
, SUPPORT_MSIX
) && tg3_enable_msix(tp
))
11134 tg3_flag_set(tp
, USING_MSIX
);
11135 else if (tg3_flag(tp
, SUPPORT_MSI
) && pci_enable_msi(tp
->pdev
) == 0)
11136 tg3_flag_set(tp
, USING_MSI
);
11138 if (tg3_flag(tp
, USING_MSI
) || tg3_flag(tp
, USING_MSIX
)) {
11139 u32 msi_mode
= tr32(MSGINT_MODE
);
11140 if (tg3_flag(tp
, USING_MSIX
) && tp
->irq_cnt
> 1)
11141 msi_mode
|= MSGINT_MODE_MULTIVEC_EN
;
11142 if (!tg3_flag(tp
, 1SHOT_MSI
))
11143 msi_mode
|= MSGINT_MODE_ONE_SHOT_DISABLE
;
11144 tw32(MSGINT_MODE
, msi_mode
| MSGINT_MODE_ENABLE
);
11147 if (!tg3_flag(tp
, USING_MSIX
)) {
11149 tp
->napi
[0].irq_vec
= tp
->pdev
->irq
;
11152 if (tp
->irq_cnt
== 1) {
11155 netif_set_real_num_tx_queues(tp
->dev
, 1);
11156 netif_set_real_num_rx_queues(tp
->dev
, 1);
11160 static void tg3_ints_fini(struct tg3
*tp
)
11162 if (tg3_flag(tp
, USING_MSIX
))
11163 pci_disable_msix(tp
->pdev
);
11164 else if (tg3_flag(tp
, USING_MSI
))
11165 pci_disable_msi(tp
->pdev
);
11166 tg3_flag_clear(tp
, USING_MSI
);
11167 tg3_flag_clear(tp
, USING_MSIX
);
11168 tg3_flag_clear(tp
, ENABLE_RSS
);
11169 tg3_flag_clear(tp
, ENABLE_TSS
);
11172 static int tg3_start(struct tg3
*tp
, bool reset_phy
, bool test_irq
,
11175 struct net_device
*dev
= tp
->dev
;
11179 * Setup interrupts first so we know how
11180 * many NAPI resources to allocate
11184 tg3_rss_check_indir_tbl(tp
);
11186 /* The placement of this call is tied
11187 * to the setup and use of Host TX descriptors.
11189 err
= tg3_alloc_consistent(tp
);
11195 tg3_napi_enable(tp
);
11197 for (i
= 0; i
< tp
->irq_cnt
; i
++) {
11198 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
11199 err
= tg3_request_irq(tp
, i
);
11201 for (i
--; i
>= 0; i
--) {
11202 tnapi
= &tp
->napi
[i
];
11203 free_irq(tnapi
->irq_vec
, tnapi
);
11209 tg3_full_lock(tp
, 0);
11211 err
= tg3_init_hw(tp
, reset_phy
);
11213 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11214 tg3_free_rings(tp
);
11217 tg3_full_unlock(tp
);
11222 if (test_irq
&& tg3_flag(tp
, USING_MSI
)) {
11223 err
= tg3_test_msi(tp
);
11226 tg3_full_lock(tp
, 0);
11227 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11228 tg3_free_rings(tp
);
11229 tg3_full_unlock(tp
);
11234 if (!tg3_flag(tp
, 57765_PLUS
) && tg3_flag(tp
, USING_MSI
)) {
11235 u32 val
= tr32(PCIE_TRANSACTION_CFG
);
11237 tw32(PCIE_TRANSACTION_CFG
,
11238 val
| PCIE_TRANS_CFG_1SHOT_MSI
);
11244 tg3_hwmon_open(tp
);
11246 tg3_full_lock(tp
, 0);
11248 tg3_timer_start(tp
);
11249 tg3_flag_set(tp
, INIT_COMPLETE
);
11250 tg3_enable_ints(tp
);
11255 tg3_ptp_resume(tp
);
11258 tg3_full_unlock(tp
);
11260 netif_tx_start_all_queues(dev
);
11263 * Reset loopback feature if it was turned on while the device was down
11264 * make sure that it's installed properly now.
11266 if (dev
->features
& NETIF_F_LOOPBACK
)
11267 tg3_set_loopback(dev
, dev
->features
);
11272 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
11273 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
11274 free_irq(tnapi
->irq_vec
, tnapi
);
11278 tg3_napi_disable(tp
);
11280 tg3_free_consistent(tp
);
11288 static void tg3_stop(struct tg3
*tp
)
11292 tg3_reset_task_cancel(tp
);
11293 tg3_netif_stop(tp
);
11295 tg3_timer_stop(tp
);
11297 tg3_hwmon_close(tp
);
11301 tg3_full_lock(tp
, 1);
11303 tg3_disable_ints(tp
);
11305 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
11306 tg3_free_rings(tp
);
11307 tg3_flag_clear(tp
, INIT_COMPLETE
);
11309 tg3_full_unlock(tp
);
11311 for (i
= tp
->irq_cnt
- 1; i
>= 0; i
--) {
11312 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
11313 free_irq(tnapi
->irq_vec
, tnapi
);
11320 tg3_free_consistent(tp
);
11323 static int tg3_open(struct net_device
*dev
)
11325 struct tg3
*tp
= netdev_priv(dev
);
11328 if (tp
->fw_needed
) {
11329 err
= tg3_request_firmware(tp
);
11330 if (tg3_asic_rev(tp
) == ASIC_REV_57766
) {
11332 netdev_warn(tp
->dev
, "EEE capability disabled\n");
11333 tp
->phy_flags
&= ~TG3_PHYFLG_EEE_CAP
;
11334 } else if (!(tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
)) {
11335 netdev_warn(tp
->dev
, "EEE capability restored\n");
11336 tp
->phy_flags
|= TG3_PHYFLG_EEE_CAP
;
11338 } else if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
) {
11342 netdev_warn(tp
->dev
, "TSO capability disabled\n");
11343 tg3_flag_clear(tp
, TSO_CAPABLE
);
11344 } else if (!tg3_flag(tp
, TSO_CAPABLE
)) {
11345 netdev_notice(tp
->dev
, "TSO capability restored\n");
11346 tg3_flag_set(tp
, TSO_CAPABLE
);
11350 tg3_carrier_off(tp
);
11352 err
= tg3_power_up(tp
);
11356 tg3_full_lock(tp
, 0);
11358 tg3_disable_ints(tp
);
11359 tg3_flag_clear(tp
, INIT_COMPLETE
);
11361 tg3_full_unlock(tp
);
11363 err
= tg3_start(tp
,
11364 !(tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
),
11367 tg3_frob_aux_power(tp
, false);
11368 pci_set_power_state(tp
->pdev
, PCI_D3hot
);
11371 if (tg3_flag(tp
, PTP_CAPABLE
)) {
11372 tp
->ptp_clock
= ptp_clock_register(&tp
->ptp_info
,
11374 if (IS_ERR(tp
->ptp_clock
))
11375 tp
->ptp_clock
= NULL
;
11381 static int tg3_close(struct net_device
*dev
)
11383 struct tg3
*tp
= netdev_priv(dev
);
11389 /* Clear stats across close / open calls */
11390 memset(&tp
->net_stats_prev
, 0, sizeof(tp
->net_stats_prev
));
11391 memset(&tp
->estats_prev
, 0, sizeof(tp
->estats_prev
));
11393 tg3_power_down(tp
);
11395 tg3_carrier_off(tp
);
11400 static inline u64
get_stat64(tg3_stat64_t
*val
)
11402 return ((u64
)val
->high
<< 32) | ((u64
)val
->low
);
11405 static u64
tg3_calc_crc_errors(struct tg3
*tp
)
11407 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
11409 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
11410 (tg3_asic_rev(tp
) == ASIC_REV_5700
||
11411 tg3_asic_rev(tp
) == ASIC_REV_5701
)) {
11414 if (!tg3_readphy(tp
, MII_TG3_TEST1
, &val
)) {
11415 tg3_writephy(tp
, MII_TG3_TEST1
,
11416 val
| MII_TG3_TEST1_CRC_EN
);
11417 tg3_readphy(tp
, MII_TG3_RXR_COUNTERS
, &val
);
11421 tp
->phy_crc_errors
+= val
;
11423 return tp
->phy_crc_errors
;
11426 return get_stat64(&hw_stats
->rx_fcs_errors
);
11429 #define ESTAT_ADD(member) \
11430 estats->member = old_estats->member + \
11431 get_stat64(&hw_stats->member)
11433 static void tg3_get_estats(struct tg3
*tp
, struct tg3_ethtool_stats
*estats
)
11435 struct tg3_ethtool_stats
*old_estats
= &tp
->estats_prev
;
11436 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
11438 ESTAT_ADD(rx_octets
);
11439 ESTAT_ADD(rx_fragments
);
11440 ESTAT_ADD(rx_ucast_packets
);
11441 ESTAT_ADD(rx_mcast_packets
);
11442 ESTAT_ADD(rx_bcast_packets
);
11443 ESTAT_ADD(rx_fcs_errors
);
11444 ESTAT_ADD(rx_align_errors
);
11445 ESTAT_ADD(rx_xon_pause_rcvd
);
11446 ESTAT_ADD(rx_xoff_pause_rcvd
);
11447 ESTAT_ADD(rx_mac_ctrl_rcvd
);
11448 ESTAT_ADD(rx_xoff_entered
);
11449 ESTAT_ADD(rx_frame_too_long_errors
);
11450 ESTAT_ADD(rx_jabbers
);
11451 ESTAT_ADD(rx_undersize_packets
);
11452 ESTAT_ADD(rx_in_length_errors
);
11453 ESTAT_ADD(rx_out_length_errors
);
11454 ESTAT_ADD(rx_64_or_less_octet_packets
);
11455 ESTAT_ADD(rx_65_to_127_octet_packets
);
11456 ESTAT_ADD(rx_128_to_255_octet_packets
);
11457 ESTAT_ADD(rx_256_to_511_octet_packets
);
11458 ESTAT_ADD(rx_512_to_1023_octet_packets
);
11459 ESTAT_ADD(rx_1024_to_1522_octet_packets
);
11460 ESTAT_ADD(rx_1523_to_2047_octet_packets
);
11461 ESTAT_ADD(rx_2048_to_4095_octet_packets
);
11462 ESTAT_ADD(rx_4096_to_8191_octet_packets
);
11463 ESTAT_ADD(rx_8192_to_9022_octet_packets
);
11465 ESTAT_ADD(tx_octets
);
11466 ESTAT_ADD(tx_collisions
);
11467 ESTAT_ADD(tx_xon_sent
);
11468 ESTAT_ADD(tx_xoff_sent
);
11469 ESTAT_ADD(tx_flow_control
);
11470 ESTAT_ADD(tx_mac_errors
);
11471 ESTAT_ADD(tx_single_collisions
);
11472 ESTAT_ADD(tx_mult_collisions
);
11473 ESTAT_ADD(tx_deferred
);
11474 ESTAT_ADD(tx_excessive_collisions
);
11475 ESTAT_ADD(tx_late_collisions
);
11476 ESTAT_ADD(tx_collide_2times
);
11477 ESTAT_ADD(tx_collide_3times
);
11478 ESTAT_ADD(tx_collide_4times
);
11479 ESTAT_ADD(tx_collide_5times
);
11480 ESTAT_ADD(tx_collide_6times
);
11481 ESTAT_ADD(tx_collide_7times
);
11482 ESTAT_ADD(tx_collide_8times
);
11483 ESTAT_ADD(tx_collide_9times
);
11484 ESTAT_ADD(tx_collide_10times
);
11485 ESTAT_ADD(tx_collide_11times
);
11486 ESTAT_ADD(tx_collide_12times
);
11487 ESTAT_ADD(tx_collide_13times
);
11488 ESTAT_ADD(tx_collide_14times
);
11489 ESTAT_ADD(tx_collide_15times
);
11490 ESTAT_ADD(tx_ucast_packets
);
11491 ESTAT_ADD(tx_mcast_packets
);
11492 ESTAT_ADD(tx_bcast_packets
);
11493 ESTAT_ADD(tx_carrier_sense_errors
);
11494 ESTAT_ADD(tx_discards
);
11495 ESTAT_ADD(tx_errors
);
11497 ESTAT_ADD(dma_writeq_full
);
11498 ESTAT_ADD(dma_write_prioq_full
);
11499 ESTAT_ADD(rxbds_empty
);
11500 ESTAT_ADD(rx_discards
);
11501 ESTAT_ADD(rx_errors
);
11502 ESTAT_ADD(rx_threshold_hit
);
11504 ESTAT_ADD(dma_readq_full
);
11505 ESTAT_ADD(dma_read_prioq_full
);
11506 ESTAT_ADD(tx_comp_queue_full
);
11508 ESTAT_ADD(ring_set_send_prod_index
);
11509 ESTAT_ADD(ring_status_update
);
11510 ESTAT_ADD(nic_irqs
);
11511 ESTAT_ADD(nic_avoided_irqs
);
11512 ESTAT_ADD(nic_tx_threshold_hit
);
11514 ESTAT_ADD(mbuf_lwm_thresh_hit
);
11517 static void tg3_get_nstats(struct tg3
*tp
, struct rtnl_link_stats64
*stats
)
11519 struct rtnl_link_stats64
*old_stats
= &tp
->net_stats_prev
;
11520 struct tg3_hw_stats
*hw_stats
= tp
->hw_stats
;
11522 stats
->rx_packets
= old_stats
->rx_packets
+
11523 get_stat64(&hw_stats
->rx_ucast_packets
) +
11524 get_stat64(&hw_stats
->rx_mcast_packets
) +
11525 get_stat64(&hw_stats
->rx_bcast_packets
);
11527 stats
->tx_packets
= old_stats
->tx_packets
+
11528 get_stat64(&hw_stats
->tx_ucast_packets
) +
11529 get_stat64(&hw_stats
->tx_mcast_packets
) +
11530 get_stat64(&hw_stats
->tx_bcast_packets
);
11532 stats
->rx_bytes
= old_stats
->rx_bytes
+
11533 get_stat64(&hw_stats
->rx_octets
);
11534 stats
->tx_bytes
= old_stats
->tx_bytes
+
11535 get_stat64(&hw_stats
->tx_octets
);
11537 stats
->rx_errors
= old_stats
->rx_errors
+
11538 get_stat64(&hw_stats
->rx_errors
);
11539 stats
->tx_errors
= old_stats
->tx_errors
+
11540 get_stat64(&hw_stats
->tx_errors
) +
11541 get_stat64(&hw_stats
->tx_mac_errors
) +
11542 get_stat64(&hw_stats
->tx_carrier_sense_errors
) +
11543 get_stat64(&hw_stats
->tx_discards
);
11545 stats
->multicast
= old_stats
->multicast
+
11546 get_stat64(&hw_stats
->rx_mcast_packets
);
11547 stats
->collisions
= old_stats
->collisions
+
11548 get_stat64(&hw_stats
->tx_collisions
);
11550 stats
->rx_length_errors
= old_stats
->rx_length_errors
+
11551 get_stat64(&hw_stats
->rx_frame_too_long_errors
) +
11552 get_stat64(&hw_stats
->rx_undersize_packets
);
11554 stats
->rx_over_errors
= old_stats
->rx_over_errors
+
11555 get_stat64(&hw_stats
->rxbds_empty
);
11556 stats
->rx_frame_errors
= old_stats
->rx_frame_errors
+
11557 get_stat64(&hw_stats
->rx_align_errors
);
11558 stats
->tx_aborted_errors
= old_stats
->tx_aborted_errors
+
11559 get_stat64(&hw_stats
->tx_discards
);
11560 stats
->tx_carrier_errors
= old_stats
->tx_carrier_errors
+
11561 get_stat64(&hw_stats
->tx_carrier_sense_errors
);
11563 stats
->rx_crc_errors
= old_stats
->rx_crc_errors
+
11564 tg3_calc_crc_errors(tp
);
11566 stats
->rx_missed_errors
= old_stats
->rx_missed_errors
+
11567 get_stat64(&hw_stats
->rx_discards
);
11569 stats
->rx_dropped
= tp
->rx_dropped
;
11570 stats
->tx_dropped
= tp
->tx_dropped
;
11573 static int tg3_get_regs_len(struct net_device
*dev
)
11575 return TG3_REG_BLK_SIZE
;
11578 static void tg3_get_regs(struct net_device
*dev
,
11579 struct ethtool_regs
*regs
, void *_p
)
11581 struct tg3
*tp
= netdev_priv(dev
);
11585 memset(_p
, 0, TG3_REG_BLK_SIZE
);
11587 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11590 tg3_full_lock(tp
, 0);
11592 tg3_dump_legacy_regs(tp
, (u32
*)_p
);
11594 tg3_full_unlock(tp
);
11597 static int tg3_get_eeprom_len(struct net_device
*dev
)
11599 struct tg3
*tp
= netdev_priv(dev
);
11601 return tp
->nvram_size
;
11604 static int tg3_get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
11606 struct tg3
*tp
= netdev_priv(dev
);
11609 u32 i
, offset
, len
, b_offset
, b_count
;
11612 if (tg3_flag(tp
, NO_NVRAM
))
11615 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11618 offset
= eeprom
->offset
;
11622 eeprom
->magic
= TG3_EEPROM_MAGIC
;
11625 /* adjustments to start on required 4 byte boundary */
11626 b_offset
= offset
& 3;
11627 b_count
= 4 - b_offset
;
11628 if (b_count
> len
) {
11629 /* i.e. offset=1 len=2 */
11632 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &val
);
11635 memcpy(data
, ((char *)&val
) + b_offset
, b_count
);
11638 eeprom
->len
+= b_count
;
11641 /* read bytes up to the last 4 byte boundary */
11642 pd
= &data
[eeprom
->len
];
11643 for (i
= 0; i
< (len
- (len
& 3)); i
+= 4) {
11644 ret
= tg3_nvram_read_be32(tp
, offset
+ i
, &val
);
11649 memcpy(pd
+ i
, &val
, 4);
11654 /* read last bytes not ending on 4 byte boundary */
11655 pd
= &data
[eeprom
->len
];
11657 b_offset
= offset
+ len
- b_count
;
11658 ret
= tg3_nvram_read_be32(tp
, b_offset
, &val
);
11661 memcpy(pd
, &val
, b_count
);
11662 eeprom
->len
+= b_count
;
11667 static int tg3_set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
, u8
*data
)
11669 struct tg3
*tp
= netdev_priv(dev
);
11671 u32 offset
, len
, b_offset
, odd_len
;
11675 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
11678 if (tg3_flag(tp
, NO_NVRAM
) ||
11679 eeprom
->magic
!= TG3_EEPROM_MAGIC
)
11682 offset
= eeprom
->offset
;
11685 if ((b_offset
= (offset
& 3))) {
11686 /* adjustments to start on required 4 byte boundary */
11687 ret
= tg3_nvram_read_be32(tp
, offset
-b_offset
, &start
);
11698 /* adjustments to end on required 4 byte boundary */
11700 len
= (len
+ 3) & ~3;
11701 ret
= tg3_nvram_read_be32(tp
, offset
+len
-4, &end
);
11707 if (b_offset
|| odd_len
) {
11708 buf
= kmalloc(len
, GFP_KERNEL
);
11712 memcpy(buf
, &start
, 4);
11714 memcpy(buf
+len
-4, &end
, 4);
11715 memcpy(buf
+ b_offset
, data
, eeprom
->len
);
11718 ret
= tg3_nvram_write_block(tp
, offset
, len
, buf
);
11726 static int tg3_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
11728 struct tg3
*tp
= netdev_priv(dev
);
11730 if (tg3_flag(tp
, USE_PHYLIB
)) {
11731 struct phy_device
*phydev
;
11732 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
11734 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
11735 return phy_ethtool_gset(phydev
, cmd
);
11738 cmd
->supported
= (SUPPORTED_Autoneg
);
11740 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
11741 cmd
->supported
|= (SUPPORTED_1000baseT_Half
|
11742 SUPPORTED_1000baseT_Full
);
11744 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
11745 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
11746 SUPPORTED_100baseT_Full
|
11747 SUPPORTED_10baseT_Half
|
11748 SUPPORTED_10baseT_Full
|
11750 cmd
->port
= PORT_TP
;
11752 cmd
->supported
|= SUPPORTED_FIBRE
;
11753 cmd
->port
= PORT_FIBRE
;
11756 cmd
->advertising
= tp
->link_config
.advertising
;
11757 if (tg3_flag(tp
, PAUSE_AUTONEG
)) {
11758 if (tp
->link_config
.flowctrl
& FLOW_CTRL_RX
) {
11759 if (tp
->link_config
.flowctrl
& FLOW_CTRL_TX
) {
11760 cmd
->advertising
|= ADVERTISED_Pause
;
11762 cmd
->advertising
|= ADVERTISED_Pause
|
11763 ADVERTISED_Asym_Pause
;
11765 } else if (tp
->link_config
.flowctrl
& FLOW_CTRL_TX
) {
11766 cmd
->advertising
|= ADVERTISED_Asym_Pause
;
11769 if (netif_running(dev
) && tp
->link_up
) {
11770 ethtool_cmd_speed_set(cmd
, tp
->link_config
.active_speed
);
11771 cmd
->duplex
= tp
->link_config
.active_duplex
;
11772 cmd
->lp_advertising
= tp
->link_config
.rmt_adv
;
11773 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)) {
11774 if (tp
->phy_flags
& TG3_PHYFLG_MDIX_STATE
)
11775 cmd
->eth_tp_mdix
= ETH_TP_MDI_X
;
11777 cmd
->eth_tp_mdix
= ETH_TP_MDI
;
11780 ethtool_cmd_speed_set(cmd
, SPEED_UNKNOWN
);
11781 cmd
->duplex
= DUPLEX_UNKNOWN
;
11782 cmd
->eth_tp_mdix
= ETH_TP_MDI_INVALID
;
11784 cmd
->phy_address
= tp
->phy_addr
;
11785 cmd
->transceiver
= XCVR_INTERNAL
;
11786 cmd
->autoneg
= tp
->link_config
.autoneg
;
11792 static int tg3_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
11794 struct tg3
*tp
= netdev_priv(dev
);
11795 u32 speed
= ethtool_cmd_speed(cmd
);
11797 if (tg3_flag(tp
, USE_PHYLIB
)) {
11798 struct phy_device
*phydev
;
11799 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
11801 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
11802 return phy_ethtool_sset(phydev
, cmd
);
11805 if (cmd
->autoneg
!= AUTONEG_ENABLE
&&
11806 cmd
->autoneg
!= AUTONEG_DISABLE
)
11809 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
11810 cmd
->duplex
!= DUPLEX_FULL
&&
11811 cmd
->duplex
!= DUPLEX_HALF
)
11814 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
11815 u32 mask
= ADVERTISED_Autoneg
|
11817 ADVERTISED_Asym_Pause
;
11819 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
11820 mask
|= ADVERTISED_1000baseT_Half
|
11821 ADVERTISED_1000baseT_Full
;
11823 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
11824 mask
|= ADVERTISED_100baseT_Half
|
11825 ADVERTISED_100baseT_Full
|
11826 ADVERTISED_10baseT_Half
|
11827 ADVERTISED_10baseT_Full
|
11830 mask
|= ADVERTISED_FIBRE
;
11832 if (cmd
->advertising
& ~mask
)
11835 mask
&= (ADVERTISED_1000baseT_Half
|
11836 ADVERTISED_1000baseT_Full
|
11837 ADVERTISED_100baseT_Half
|
11838 ADVERTISED_100baseT_Full
|
11839 ADVERTISED_10baseT_Half
|
11840 ADVERTISED_10baseT_Full
);
11842 cmd
->advertising
&= mask
;
11844 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) {
11845 if (speed
!= SPEED_1000
)
11848 if (cmd
->duplex
!= DUPLEX_FULL
)
11851 if (speed
!= SPEED_100
&&
11857 tg3_full_lock(tp
, 0);
11859 tp
->link_config
.autoneg
= cmd
->autoneg
;
11860 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
11861 tp
->link_config
.advertising
= (cmd
->advertising
|
11862 ADVERTISED_Autoneg
);
11863 tp
->link_config
.speed
= SPEED_UNKNOWN
;
11864 tp
->link_config
.duplex
= DUPLEX_UNKNOWN
;
11866 tp
->link_config
.advertising
= 0;
11867 tp
->link_config
.speed
= speed
;
11868 tp
->link_config
.duplex
= cmd
->duplex
;
11871 tp
->phy_flags
|= TG3_PHYFLG_USER_CONFIGURED
;
11873 tg3_warn_mgmt_link_flap(tp
);
11875 if (netif_running(dev
))
11876 tg3_setup_phy(tp
, true);
11878 tg3_full_unlock(tp
);
11883 static void tg3_get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
11885 struct tg3
*tp
= netdev_priv(dev
);
11887 strlcpy(info
->driver
, DRV_MODULE_NAME
, sizeof(info
->driver
));
11888 strlcpy(info
->version
, DRV_MODULE_VERSION
, sizeof(info
->version
));
11889 strlcpy(info
->fw_version
, tp
->fw_ver
, sizeof(info
->fw_version
));
11890 strlcpy(info
->bus_info
, pci_name(tp
->pdev
), sizeof(info
->bus_info
));
11893 static void tg3_get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
11895 struct tg3
*tp
= netdev_priv(dev
);
11897 if (tg3_flag(tp
, WOL_CAP
) && device_can_wakeup(&tp
->pdev
->dev
))
11898 wol
->supported
= WAKE_MAGIC
;
11900 wol
->supported
= 0;
11902 if (tg3_flag(tp
, WOL_ENABLE
) && device_can_wakeup(&tp
->pdev
->dev
))
11903 wol
->wolopts
= WAKE_MAGIC
;
11904 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
11907 static int tg3_set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
11909 struct tg3
*tp
= netdev_priv(dev
);
11910 struct device
*dp
= &tp
->pdev
->dev
;
11912 if (wol
->wolopts
& ~WAKE_MAGIC
)
11914 if ((wol
->wolopts
& WAKE_MAGIC
) &&
11915 !(tg3_flag(tp
, WOL_CAP
) && device_can_wakeup(dp
)))
11918 device_set_wakeup_enable(dp
, wol
->wolopts
& WAKE_MAGIC
);
11920 spin_lock_bh(&tp
->lock
);
11921 if (device_may_wakeup(dp
))
11922 tg3_flag_set(tp
, WOL_ENABLE
);
11924 tg3_flag_clear(tp
, WOL_ENABLE
);
11925 spin_unlock_bh(&tp
->lock
);
11930 static u32
tg3_get_msglevel(struct net_device
*dev
)
11932 struct tg3
*tp
= netdev_priv(dev
);
11933 return tp
->msg_enable
;
11936 static void tg3_set_msglevel(struct net_device
*dev
, u32 value
)
11938 struct tg3
*tp
= netdev_priv(dev
);
11939 tp
->msg_enable
= value
;
11942 static int tg3_nway_reset(struct net_device
*dev
)
11944 struct tg3
*tp
= netdev_priv(dev
);
11947 if (!netif_running(dev
))
11950 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
11953 tg3_warn_mgmt_link_flap(tp
);
11955 if (tg3_flag(tp
, USE_PHYLIB
)) {
11956 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
11958 r
= phy_start_aneg(tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
]);
11962 spin_lock_bh(&tp
->lock
);
11964 tg3_readphy(tp
, MII_BMCR
, &bmcr
);
11965 if (!tg3_readphy(tp
, MII_BMCR
, &bmcr
) &&
11966 ((bmcr
& BMCR_ANENABLE
) ||
11967 (tp
->phy_flags
& TG3_PHYFLG_PARALLEL_DETECT
))) {
11968 tg3_writephy(tp
, MII_BMCR
, bmcr
| BMCR_ANRESTART
|
11972 spin_unlock_bh(&tp
->lock
);
11978 static void tg3_get_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
11980 struct tg3
*tp
= netdev_priv(dev
);
11982 ering
->rx_max_pending
= tp
->rx_std_ring_mask
;
11983 if (tg3_flag(tp
, JUMBO_RING_ENABLE
))
11984 ering
->rx_jumbo_max_pending
= tp
->rx_jmb_ring_mask
;
11986 ering
->rx_jumbo_max_pending
= 0;
11988 ering
->tx_max_pending
= TG3_TX_RING_SIZE
- 1;
11990 ering
->rx_pending
= tp
->rx_pending
;
11991 if (tg3_flag(tp
, JUMBO_RING_ENABLE
))
11992 ering
->rx_jumbo_pending
= tp
->rx_jumbo_pending
;
11994 ering
->rx_jumbo_pending
= 0;
11996 ering
->tx_pending
= tp
->napi
[0].tx_pending
;
11999 static int tg3_set_ringparam(struct net_device
*dev
, struct ethtool_ringparam
*ering
)
12001 struct tg3
*tp
= netdev_priv(dev
);
12002 int i
, irq_sync
= 0, err
= 0;
12004 if ((ering
->rx_pending
> tp
->rx_std_ring_mask
) ||
12005 (ering
->rx_jumbo_pending
> tp
->rx_jmb_ring_mask
) ||
12006 (ering
->tx_pending
> TG3_TX_RING_SIZE
- 1) ||
12007 (ering
->tx_pending
<= MAX_SKB_FRAGS
) ||
12008 (tg3_flag(tp
, TSO_BUG
) &&
12009 (ering
->tx_pending
<= (MAX_SKB_FRAGS
* 3))))
12012 if (netif_running(dev
)) {
12014 tg3_netif_stop(tp
);
12018 tg3_full_lock(tp
, irq_sync
);
12020 tp
->rx_pending
= ering
->rx_pending
;
12022 if (tg3_flag(tp
, MAX_RXPEND_64
) &&
12023 tp
->rx_pending
> 63)
12024 tp
->rx_pending
= 63;
12025 tp
->rx_jumbo_pending
= ering
->rx_jumbo_pending
;
12027 for (i
= 0; i
< tp
->irq_max
; i
++)
12028 tp
->napi
[i
].tx_pending
= ering
->tx_pending
;
12030 if (netif_running(dev
)) {
12031 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
12032 err
= tg3_restart_hw(tp
, false);
12034 tg3_netif_start(tp
);
12037 tg3_full_unlock(tp
);
12039 if (irq_sync
&& !err
)
12045 static void tg3_get_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
12047 struct tg3
*tp
= netdev_priv(dev
);
12049 epause
->autoneg
= !!tg3_flag(tp
, PAUSE_AUTONEG
);
12051 if (tp
->link_config
.flowctrl
& FLOW_CTRL_RX
)
12052 epause
->rx_pause
= 1;
12054 epause
->rx_pause
= 0;
12056 if (tp
->link_config
.flowctrl
& FLOW_CTRL_TX
)
12057 epause
->tx_pause
= 1;
12059 epause
->tx_pause
= 0;
12062 static int tg3_set_pauseparam(struct net_device
*dev
, struct ethtool_pauseparam
*epause
)
12064 struct tg3
*tp
= netdev_priv(dev
);
12067 if (tp
->link_config
.autoneg
== AUTONEG_ENABLE
)
12068 tg3_warn_mgmt_link_flap(tp
);
12070 if (tg3_flag(tp
, USE_PHYLIB
)) {
12072 struct phy_device
*phydev
;
12074 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
12076 if (!(phydev
->supported
& SUPPORTED_Pause
) ||
12077 (!(phydev
->supported
& SUPPORTED_Asym_Pause
) &&
12078 (epause
->rx_pause
!= epause
->tx_pause
)))
12081 tp
->link_config
.flowctrl
= 0;
12082 if (epause
->rx_pause
) {
12083 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
12085 if (epause
->tx_pause
) {
12086 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
12087 newadv
= ADVERTISED_Pause
;
12089 newadv
= ADVERTISED_Pause
|
12090 ADVERTISED_Asym_Pause
;
12091 } else if (epause
->tx_pause
) {
12092 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
12093 newadv
= ADVERTISED_Asym_Pause
;
12097 if (epause
->autoneg
)
12098 tg3_flag_set(tp
, PAUSE_AUTONEG
);
12100 tg3_flag_clear(tp
, PAUSE_AUTONEG
);
12102 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
12103 u32 oldadv
= phydev
->advertising
&
12104 (ADVERTISED_Pause
| ADVERTISED_Asym_Pause
);
12105 if (oldadv
!= newadv
) {
12106 phydev
->advertising
&=
12107 ~(ADVERTISED_Pause
|
12108 ADVERTISED_Asym_Pause
);
12109 phydev
->advertising
|= newadv
;
12110 if (phydev
->autoneg
) {
12112 * Always renegotiate the link to
12113 * inform our link partner of our
12114 * flow control settings, even if the
12115 * flow control is forced. Let
12116 * tg3_adjust_link() do the final
12117 * flow control setup.
12119 return phy_start_aneg(phydev
);
12123 if (!epause
->autoneg
)
12124 tg3_setup_flow_control(tp
, 0, 0);
12126 tp
->link_config
.advertising
&=
12127 ~(ADVERTISED_Pause
|
12128 ADVERTISED_Asym_Pause
);
12129 tp
->link_config
.advertising
|= newadv
;
12134 if (netif_running(dev
)) {
12135 tg3_netif_stop(tp
);
12139 tg3_full_lock(tp
, irq_sync
);
12141 if (epause
->autoneg
)
12142 tg3_flag_set(tp
, PAUSE_AUTONEG
);
12144 tg3_flag_clear(tp
, PAUSE_AUTONEG
);
12145 if (epause
->rx_pause
)
12146 tp
->link_config
.flowctrl
|= FLOW_CTRL_RX
;
12148 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_RX
;
12149 if (epause
->tx_pause
)
12150 tp
->link_config
.flowctrl
|= FLOW_CTRL_TX
;
12152 tp
->link_config
.flowctrl
&= ~FLOW_CTRL_TX
;
12154 if (netif_running(dev
)) {
12155 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
12156 err
= tg3_restart_hw(tp
, false);
12158 tg3_netif_start(tp
);
12161 tg3_full_unlock(tp
);
12164 tp
->phy_flags
|= TG3_PHYFLG_USER_CONFIGURED
;
12169 static int tg3_get_sset_count(struct net_device
*dev
, int sset
)
12173 return TG3_NUM_TEST
;
12175 return TG3_NUM_STATS
;
12177 return -EOPNOTSUPP
;
12181 static int tg3_get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
,
12182 u32
*rules __always_unused
)
12184 struct tg3
*tp
= netdev_priv(dev
);
12186 if (!tg3_flag(tp
, SUPPORT_MSIX
))
12187 return -EOPNOTSUPP
;
12189 switch (info
->cmd
) {
12190 case ETHTOOL_GRXRINGS
:
12191 if (netif_running(tp
->dev
))
12192 info
->data
= tp
->rxq_cnt
;
12194 info
->data
= num_online_cpus();
12195 if (info
->data
> TG3_RSS_MAX_NUM_QS
)
12196 info
->data
= TG3_RSS_MAX_NUM_QS
;
12199 /* The first interrupt vector only
12200 * handles link interrupts.
12206 return -EOPNOTSUPP
;
12210 static u32
tg3_get_rxfh_indir_size(struct net_device
*dev
)
12213 struct tg3
*tp
= netdev_priv(dev
);
12215 if (tg3_flag(tp
, SUPPORT_MSIX
))
12216 size
= TG3_RSS_INDIR_TBL_SIZE
;
12221 static int tg3_get_rxfh_indir(struct net_device
*dev
, u32
*indir
)
12223 struct tg3
*tp
= netdev_priv(dev
);
12226 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++)
12227 indir
[i
] = tp
->rss_ind_tbl
[i
];
12232 static int tg3_set_rxfh_indir(struct net_device
*dev
, const u32
*indir
)
12234 struct tg3
*tp
= netdev_priv(dev
);
12237 for (i
= 0; i
< TG3_RSS_INDIR_TBL_SIZE
; i
++)
12238 tp
->rss_ind_tbl
[i
] = indir
[i
];
12240 if (!netif_running(dev
) || !tg3_flag(tp
, ENABLE_RSS
))
12243 /* It is legal to write the indirection
12244 * table while the device is running.
12246 tg3_full_lock(tp
, 0);
12247 tg3_rss_write_indir_tbl(tp
);
12248 tg3_full_unlock(tp
);
12253 static void tg3_get_channels(struct net_device
*dev
,
12254 struct ethtool_channels
*channel
)
12256 struct tg3
*tp
= netdev_priv(dev
);
12257 u32 deflt_qs
= netif_get_num_default_rss_queues();
12259 channel
->max_rx
= tp
->rxq_max
;
12260 channel
->max_tx
= tp
->txq_max
;
12262 if (netif_running(dev
)) {
12263 channel
->rx_count
= tp
->rxq_cnt
;
12264 channel
->tx_count
= tp
->txq_cnt
;
12267 channel
->rx_count
= tp
->rxq_req
;
12269 channel
->rx_count
= min(deflt_qs
, tp
->rxq_max
);
12272 channel
->tx_count
= tp
->txq_req
;
12274 channel
->tx_count
= min(deflt_qs
, tp
->txq_max
);
12278 static int tg3_set_channels(struct net_device
*dev
,
12279 struct ethtool_channels
*channel
)
12281 struct tg3
*tp
= netdev_priv(dev
);
12283 if (!tg3_flag(tp
, SUPPORT_MSIX
))
12284 return -EOPNOTSUPP
;
12286 if (channel
->rx_count
> tp
->rxq_max
||
12287 channel
->tx_count
> tp
->txq_max
)
12290 tp
->rxq_req
= channel
->rx_count
;
12291 tp
->txq_req
= channel
->tx_count
;
12293 if (!netif_running(dev
))
12298 tg3_carrier_off(tp
);
12300 tg3_start(tp
, true, false, false);
12305 static void tg3_get_strings(struct net_device
*dev
, u32 stringset
, u8
*buf
)
12307 switch (stringset
) {
12309 memcpy(buf
, ðtool_stats_keys
, sizeof(ethtool_stats_keys
));
12312 memcpy(buf
, ðtool_test_keys
, sizeof(ethtool_test_keys
));
12315 WARN_ON(1); /* we need a WARN() */
12320 static int tg3_set_phys_id(struct net_device
*dev
,
12321 enum ethtool_phys_id_state state
)
12323 struct tg3
*tp
= netdev_priv(dev
);
12325 if (!netif_running(tp
->dev
))
12329 case ETHTOOL_ID_ACTIVE
:
12330 return 1; /* cycle on/off once per second */
12332 case ETHTOOL_ID_ON
:
12333 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
12334 LED_CTRL_1000MBPS_ON
|
12335 LED_CTRL_100MBPS_ON
|
12336 LED_CTRL_10MBPS_ON
|
12337 LED_CTRL_TRAFFIC_OVERRIDE
|
12338 LED_CTRL_TRAFFIC_BLINK
|
12339 LED_CTRL_TRAFFIC_LED
);
12342 case ETHTOOL_ID_OFF
:
12343 tw32(MAC_LED_CTRL
, LED_CTRL_LNKLED_OVERRIDE
|
12344 LED_CTRL_TRAFFIC_OVERRIDE
);
12347 case ETHTOOL_ID_INACTIVE
:
12348 tw32(MAC_LED_CTRL
, tp
->led_ctrl
);
12355 static void tg3_get_ethtool_stats(struct net_device
*dev
,
12356 struct ethtool_stats
*estats
, u64
*tmp_stats
)
12358 struct tg3
*tp
= netdev_priv(dev
);
12361 tg3_get_estats(tp
, (struct tg3_ethtool_stats
*)tmp_stats
);
12363 memset(tmp_stats
, 0, sizeof(struct tg3_ethtool_stats
));
12366 static __be32
*tg3_vpd_readblock(struct tg3
*tp
, u32
*vpdlen
)
12370 u32 offset
= 0, len
= 0;
12373 if (tg3_flag(tp
, NO_NVRAM
) || tg3_nvram_read(tp
, 0, &magic
))
12376 if (magic
== TG3_EEPROM_MAGIC
) {
12377 for (offset
= TG3_NVM_DIR_START
;
12378 offset
< TG3_NVM_DIR_END
;
12379 offset
+= TG3_NVM_DIRENT_SIZE
) {
12380 if (tg3_nvram_read(tp
, offset
, &val
))
12383 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) ==
12384 TG3_NVM_DIRTYPE_EXTVPD
)
12388 if (offset
!= TG3_NVM_DIR_END
) {
12389 len
= (val
& TG3_NVM_DIRTYPE_LENMSK
) * 4;
12390 if (tg3_nvram_read(tp
, offset
+ 4, &offset
))
12393 offset
= tg3_nvram_logical_addr(tp
, offset
);
12397 if (!offset
|| !len
) {
12398 offset
= TG3_NVM_VPD_OFF
;
12399 len
= TG3_NVM_VPD_LEN
;
12402 buf
= kmalloc(len
, GFP_KERNEL
);
12406 if (magic
== TG3_EEPROM_MAGIC
) {
12407 for (i
= 0; i
< len
; i
+= 4) {
12408 /* The data is in little-endian format in NVRAM.
12409 * Use the big-endian read routines to preserve
12410 * the byte order as it exists in NVRAM.
12412 if (tg3_nvram_read_be32(tp
, offset
+ i
, &buf
[i
/4]))
12418 unsigned int pos
= 0;
12420 ptr
= (u8
*)&buf
[0];
12421 for (i
= 0; pos
< len
&& i
< 3; i
++, pos
+= cnt
, ptr
+= cnt
) {
12422 cnt
= pci_read_vpd(tp
->pdev
, pos
,
12424 if (cnt
== -ETIMEDOUT
|| cnt
== -EINTR
)
12442 #define NVRAM_TEST_SIZE 0x100
12443 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
12444 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
12445 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
12446 #define NVRAM_SELFBOOT_FORMAT1_4_SIZE 0x20
12447 #define NVRAM_SELFBOOT_FORMAT1_5_SIZE 0x24
12448 #define NVRAM_SELFBOOT_FORMAT1_6_SIZE 0x50
12449 #define NVRAM_SELFBOOT_HW_SIZE 0x20
12450 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
12452 static int tg3_test_nvram(struct tg3
*tp
)
12454 u32 csum
, magic
, len
;
12456 int i
, j
, k
, err
= 0, size
;
12458 if (tg3_flag(tp
, NO_NVRAM
))
12461 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
12464 if (magic
== TG3_EEPROM_MAGIC
)
12465 size
= NVRAM_TEST_SIZE
;
12466 else if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
) {
12467 if ((magic
& TG3_EEPROM_SB_FORMAT_MASK
) ==
12468 TG3_EEPROM_SB_FORMAT_1
) {
12469 switch (magic
& TG3_EEPROM_SB_REVISION_MASK
) {
12470 case TG3_EEPROM_SB_REVISION_0
:
12471 size
= NVRAM_SELFBOOT_FORMAT1_0_SIZE
;
12473 case TG3_EEPROM_SB_REVISION_2
:
12474 size
= NVRAM_SELFBOOT_FORMAT1_2_SIZE
;
12476 case TG3_EEPROM_SB_REVISION_3
:
12477 size
= NVRAM_SELFBOOT_FORMAT1_3_SIZE
;
12479 case TG3_EEPROM_SB_REVISION_4
:
12480 size
= NVRAM_SELFBOOT_FORMAT1_4_SIZE
;
12482 case TG3_EEPROM_SB_REVISION_5
:
12483 size
= NVRAM_SELFBOOT_FORMAT1_5_SIZE
;
12485 case TG3_EEPROM_SB_REVISION_6
:
12486 size
= NVRAM_SELFBOOT_FORMAT1_6_SIZE
;
12493 } else if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
12494 size
= NVRAM_SELFBOOT_HW_SIZE
;
12498 buf
= kmalloc(size
, GFP_KERNEL
);
12503 for (i
= 0, j
= 0; i
< size
; i
+= 4, j
++) {
12504 err
= tg3_nvram_read_be32(tp
, i
, &buf
[j
]);
12511 /* Selfboot format */
12512 magic
= be32_to_cpu(buf
[0]);
12513 if ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) ==
12514 TG3_EEPROM_MAGIC_FW
) {
12515 u8
*buf8
= (u8
*) buf
, csum8
= 0;
12517 if ((magic
& TG3_EEPROM_SB_REVISION_MASK
) ==
12518 TG3_EEPROM_SB_REVISION_2
) {
12519 /* For rev 2, the csum doesn't include the MBA. */
12520 for (i
= 0; i
< TG3_EEPROM_SB_F1R2_MBA_OFF
; i
++)
12522 for (i
= TG3_EEPROM_SB_F1R2_MBA_OFF
+ 4; i
< size
; i
++)
12525 for (i
= 0; i
< size
; i
++)
12538 if ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) ==
12539 TG3_EEPROM_MAGIC_HW
) {
12540 u8 data
[NVRAM_SELFBOOT_DATA_SIZE
];
12541 u8 parity
[NVRAM_SELFBOOT_DATA_SIZE
];
12542 u8
*buf8
= (u8
*) buf
;
12544 /* Separate the parity bits and the data bytes. */
12545 for (i
= 0, j
= 0, k
= 0; i
< NVRAM_SELFBOOT_HW_SIZE
; i
++) {
12546 if ((i
== 0) || (i
== 8)) {
12550 for (l
= 0, msk
= 0x80; l
< 7; l
++, msk
>>= 1)
12551 parity
[k
++] = buf8
[i
] & msk
;
12553 } else if (i
== 16) {
12557 for (l
= 0, msk
= 0x20; l
< 6; l
++, msk
>>= 1)
12558 parity
[k
++] = buf8
[i
] & msk
;
12561 for (l
= 0, msk
= 0x80; l
< 8; l
++, msk
>>= 1)
12562 parity
[k
++] = buf8
[i
] & msk
;
12565 data
[j
++] = buf8
[i
];
12569 for (i
= 0; i
< NVRAM_SELFBOOT_DATA_SIZE
; i
++) {
12570 u8 hw8
= hweight8(data
[i
]);
12572 if ((hw8
& 0x1) && parity
[i
])
12574 else if (!(hw8
& 0x1) && !parity
[i
])
12583 /* Bootstrap checksum at offset 0x10 */
12584 csum
= calc_crc((unsigned char *) buf
, 0x10);
12585 if (csum
!= le32_to_cpu(buf
[0x10/4]))
12588 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
12589 csum
= calc_crc((unsigned char *) &buf
[0x74/4], 0x88);
12590 if (csum
!= le32_to_cpu(buf
[0xfc/4]))
12595 buf
= tg3_vpd_readblock(tp
, &len
);
12599 i
= pci_vpd_find_tag((u8
*)buf
, 0, len
, PCI_VPD_LRDT_RO_DATA
);
12601 j
= pci_vpd_lrdt_size(&((u8
*)buf
)[i
]);
12605 if (i
+ PCI_VPD_LRDT_TAG_SIZE
+ j
> len
)
12608 i
+= PCI_VPD_LRDT_TAG_SIZE
;
12609 j
= pci_vpd_find_info_keyword((u8
*)buf
, i
, j
,
12610 PCI_VPD_RO_KEYWORD_CHKSUM
);
12614 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
12616 for (i
= 0; i
<= j
; i
++)
12617 csum8
+= ((u8
*)buf
)[i
];
12631 #define TG3_SERDES_TIMEOUT_SEC 2
12632 #define TG3_COPPER_TIMEOUT_SEC 6
12634 static int tg3_test_link(struct tg3
*tp
)
12638 if (!netif_running(tp
->dev
))
12641 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
12642 max
= TG3_SERDES_TIMEOUT_SEC
;
12644 max
= TG3_COPPER_TIMEOUT_SEC
;
12646 for (i
= 0; i
< max
; i
++) {
12650 if (msleep_interruptible(1000))
12657 /* Only test the commonly used registers */
12658 static int tg3_test_registers(struct tg3
*tp
)
12660 int i
, is_5705
, is_5750
;
12661 u32 offset
, read_mask
, write_mask
, val
, save_val
, read_val
;
12665 #define TG3_FL_5705 0x1
12666 #define TG3_FL_NOT_5705 0x2
12667 #define TG3_FL_NOT_5788 0x4
12668 #define TG3_FL_NOT_5750 0x8
12672 /* MAC Control Registers */
12673 { MAC_MODE
, TG3_FL_NOT_5705
,
12674 0x00000000, 0x00ef6f8c },
12675 { MAC_MODE
, TG3_FL_5705
,
12676 0x00000000, 0x01ef6b8c },
12677 { MAC_STATUS
, TG3_FL_NOT_5705
,
12678 0x03800107, 0x00000000 },
12679 { MAC_STATUS
, TG3_FL_5705
,
12680 0x03800100, 0x00000000 },
12681 { MAC_ADDR_0_HIGH
, 0x0000,
12682 0x00000000, 0x0000ffff },
12683 { MAC_ADDR_0_LOW
, 0x0000,
12684 0x00000000, 0xffffffff },
12685 { MAC_RX_MTU_SIZE
, 0x0000,
12686 0x00000000, 0x0000ffff },
12687 { MAC_TX_MODE
, 0x0000,
12688 0x00000000, 0x00000070 },
12689 { MAC_TX_LENGTHS
, 0x0000,
12690 0x00000000, 0x00003fff },
12691 { MAC_RX_MODE
, TG3_FL_NOT_5705
,
12692 0x00000000, 0x000007fc },
12693 { MAC_RX_MODE
, TG3_FL_5705
,
12694 0x00000000, 0x000007dc },
12695 { MAC_HASH_REG_0
, 0x0000,
12696 0x00000000, 0xffffffff },
12697 { MAC_HASH_REG_1
, 0x0000,
12698 0x00000000, 0xffffffff },
12699 { MAC_HASH_REG_2
, 0x0000,
12700 0x00000000, 0xffffffff },
12701 { MAC_HASH_REG_3
, 0x0000,
12702 0x00000000, 0xffffffff },
12704 /* Receive Data and Receive BD Initiator Control Registers. */
12705 { RCVDBDI_JUMBO_BD
+0, TG3_FL_NOT_5705
,
12706 0x00000000, 0xffffffff },
12707 { RCVDBDI_JUMBO_BD
+4, TG3_FL_NOT_5705
,
12708 0x00000000, 0xffffffff },
12709 { RCVDBDI_JUMBO_BD
+8, TG3_FL_NOT_5705
,
12710 0x00000000, 0x00000003 },
12711 { RCVDBDI_JUMBO_BD
+0xc, TG3_FL_NOT_5705
,
12712 0x00000000, 0xffffffff },
12713 { RCVDBDI_STD_BD
+0, 0x0000,
12714 0x00000000, 0xffffffff },
12715 { RCVDBDI_STD_BD
+4, 0x0000,
12716 0x00000000, 0xffffffff },
12717 { RCVDBDI_STD_BD
+8, 0x0000,
12718 0x00000000, 0xffff0002 },
12719 { RCVDBDI_STD_BD
+0xc, 0x0000,
12720 0x00000000, 0xffffffff },
12722 /* Receive BD Initiator Control Registers. */
12723 { RCVBDI_STD_THRESH
, TG3_FL_NOT_5705
,
12724 0x00000000, 0xffffffff },
12725 { RCVBDI_STD_THRESH
, TG3_FL_5705
,
12726 0x00000000, 0x000003ff },
12727 { RCVBDI_JUMBO_THRESH
, TG3_FL_NOT_5705
,
12728 0x00000000, 0xffffffff },
12730 /* Host Coalescing Control Registers. */
12731 { HOSTCC_MODE
, TG3_FL_NOT_5705
,
12732 0x00000000, 0x00000004 },
12733 { HOSTCC_MODE
, TG3_FL_5705
,
12734 0x00000000, 0x000000f6 },
12735 { HOSTCC_RXCOL_TICKS
, TG3_FL_NOT_5705
,
12736 0x00000000, 0xffffffff },
12737 { HOSTCC_RXCOL_TICKS
, TG3_FL_5705
,
12738 0x00000000, 0x000003ff },
12739 { HOSTCC_TXCOL_TICKS
, TG3_FL_NOT_5705
,
12740 0x00000000, 0xffffffff },
12741 { HOSTCC_TXCOL_TICKS
, TG3_FL_5705
,
12742 0x00000000, 0x000003ff },
12743 { HOSTCC_RXMAX_FRAMES
, TG3_FL_NOT_5705
,
12744 0x00000000, 0xffffffff },
12745 { HOSTCC_RXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
12746 0x00000000, 0x000000ff },
12747 { HOSTCC_TXMAX_FRAMES
, TG3_FL_NOT_5705
,
12748 0x00000000, 0xffffffff },
12749 { HOSTCC_TXMAX_FRAMES
, TG3_FL_5705
| TG3_FL_NOT_5788
,
12750 0x00000000, 0x000000ff },
12751 { HOSTCC_RXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
12752 0x00000000, 0xffffffff },
12753 { HOSTCC_TXCOAL_TICK_INT
, TG3_FL_NOT_5705
,
12754 0x00000000, 0xffffffff },
12755 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
12756 0x00000000, 0xffffffff },
12757 { HOSTCC_RXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
12758 0x00000000, 0x000000ff },
12759 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_NOT_5705
,
12760 0x00000000, 0xffffffff },
12761 { HOSTCC_TXCOAL_MAXF_INT
, TG3_FL_5705
| TG3_FL_NOT_5788
,
12762 0x00000000, 0x000000ff },
12763 { HOSTCC_STAT_COAL_TICKS
, TG3_FL_NOT_5705
,
12764 0x00000000, 0xffffffff },
12765 { HOSTCC_STATS_BLK_HOST_ADDR
, TG3_FL_NOT_5705
,
12766 0x00000000, 0xffffffff },
12767 { HOSTCC_STATS_BLK_HOST_ADDR
+4, TG3_FL_NOT_5705
,
12768 0x00000000, 0xffffffff },
12769 { HOSTCC_STATUS_BLK_HOST_ADDR
, 0x0000,
12770 0x00000000, 0xffffffff },
12771 { HOSTCC_STATUS_BLK_HOST_ADDR
+4, 0x0000,
12772 0x00000000, 0xffffffff },
12773 { HOSTCC_STATS_BLK_NIC_ADDR
, 0x0000,
12774 0xffffffff, 0x00000000 },
12775 { HOSTCC_STATUS_BLK_NIC_ADDR
, 0x0000,
12776 0xffffffff, 0x00000000 },
12778 /* Buffer Manager Control Registers. */
12779 { BUFMGR_MB_POOL_ADDR
, TG3_FL_NOT_5750
,
12780 0x00000000, 0x007fff80 },
12781 { BUFMGR_MB_POOL_SIZE
, TG3_FL_NOT_5750
,
12782 0x00000000, 0x007fffff },
12783 { BUFMGR_MB_RDMA_LOW_WATER
, 0x0000,
12784 0x00000000, 0x0000003f },
12785 { BUFMGR_MB_MACRX_LOW_WATER
, 0x0000,
12786 0x00000000, 0x000001ff },
12787 { BUFMGR_MB_HIGH_WATER
, 0x0000,
12788 0x00000000, 0x000001ff },
12789 { BUFMGR_DMA_DESC_POOL_ADDR
, TG3_FL_NOT_5705
,
12790 0xffffffff, 0x00000000 },
12791 { BUFMGR_DMA_DESC_POOL_SIZE
, TG3_FL_NOT_5705
,
12792 0xffffffff, 0x00000000 },
12794 /* Mailbox Registers */
12795 { GRCMBOX_RCVSTD_PROD_IDX
+4, 0x0000,
12796 0x00000000, 0x000001ff },
12797 { GRCMBOX_RCVJUMBO_PROD_IDX
+4, TG3_FL_NOT_5705
,
12798 0x00000000, 0x000001ff },
12799 { GRCMBOX_RCVRET_CON_IDX_0
+4, 0x0000,
12800 0x00000000, 0x000007ff },
12801 { GRCMBOX_SNDHOST_PROD_IDX_0
+4, 0x0000,
12802 0x00000000, 0x000001ff },
12804 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
12807 is_5705
= is_5750
= 0;
12808 if (tg3_flag(tp
, 5705_PLUS
)) {
12810 if (tg3_flag(tp
, 5750_PLUS
))
12814 for (i
= 0; reg_tbl
[i
].offset
!= 0xffff; i
++) {
12815 if (is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5705
))
12818 if (!is_5705
&& (reg_tbl
[i
].flags
& TG3_FL_5705
))
12821 if (tg3_flag(tp
, IS_5788
) &&
12822 (reg_tbl
[i
].flags
& TG3_FL_NOT_5788
))
12825 if (is_5750
&& (reg_tbl
[i
].flags
& TG3_FL_NOT_5750
))
12828 offset
= (u32
) reg_tbl
[i
].offset
;
12829 read_mask
= reg_tbl
[i
].read_mask
;
12830 write_mask
= reg_tbl
[i
].write_mask
;
12832 /* Save the original register content */
12833 save_val
= tr32(offset
);
12835 /* Determine the read-only value. */
12836 read_val
= save_val
& read_mask
;
12838 /* Write zero to the register, then make sure the read-only bits
12839 * are not changed and the read/write bits are all zeros.
12843 val
= tr32(offset
);
12845 /* Test the read-only and read/write bits. */
12846 if (((val
& read_mask
) != read_val
) || (val
& write_mask
))
12849 /* Write ones to all the bits defined by RdMask and WrMask, then
12850 * make sure the read-only bits are not changed and the
12851 * read/write bits are all ones.
12853 tw32(offset
, read_mask
| write_mask
);
12855 val
= tr32(offset
);
12857 /* Test the read-only bits. */
12858 if ((val
& read_mask
) != read_val
)
12861 /* Test the read/write bits. */
12862 if ((val
& write_mask
) != write_mask
)
12865 tw32(offset
, save_val
);
12871 if (netif_msg_hw(tp
))
12872 netdev_err(tp
->dev
,
12873 "Register test failed at offset %x\n", offset
);
12874 tw32(offset
, save_val
);
12878 static int tg3_do_mem_test(struct tg3
*tp
, u32 offset
, u32 len
)
12880 static const u32 test_pattern
[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
12884 for (i
= 0; i
< ARRAY_SIZE(test_pattern
); i
++) {
12885 for (j
= 0; j
< len
; j
+= 4) {
12888 tg3_write_mem(tp
, offset
+ j
, test_pattern
[i
]);
12889 tg3_read_mem(tp
, offset
+ j
, &val
);
12890 if (val
!= test_pattern
[i
])
12897 static int tg3_test_memory(struct tg3
*tp
)
12899 static struct mem_entry
{
12902 } mem_tbl_570x
[] = {
12903 { 0x00000000, 0x00b50},
12904 { 0x00002000, 0x1c000},
12905 { 0xffffffff, 0x00000}
12906 }, mem_tbl_5705
[] = {
12907 { 0x00000100, 0x0000c},
12908 { 0x00000200, 0x00008},
12909 { 0x00004000, 0x00800},
12910 { 0x00006000, 0x01000},
12911 { 0x00008000, 0x02000},
12912 { 0x00010000, 0x0e000},
12913 { 0xffffffff, 0x00000}
12914 }, mem_tbl_5755
[] = {
12915 { 0x00000200, 0x00008},
12916 { 0x00004000, 0x00800},
12917 { 0x00006000, 0x00800},
12918 { 0x00008000, 0x02000},
12919 { 0x00010000, 0x0c000},
12920 { 0xffffffff, 0x00000}
12921 }, mem_tbl_5906
[] = {
12922 { 0x00000200, 0x00008},
12923 { 0x00004000, 0x00400},
12924 { 0x00006000, 0x00400},
12925 { 0x00008000, 0x01000},
12926 { 0x00010000, 0x01000},
12927 { 0xffffffff, 0x00000}
12928 }, mem_tbl_5717
[] = {
12929 { 0x00000200, 0x00008},
12930 { 0x00010000, 0x0a000},
12931 { 0x00020000, 0x13c00},
12932 { 0xffffffff, 0x00000}
12933 }, mem_tbl_57765
[] = {
12934 { 0x00000200, 0x00008},
12935 { 0x00004000, 0x00800},
12936 { 0x00006000, 0x09800},
12937 { 0x00010000, 0x0a000},
12938 { 0xffffffff, 0x00000}
12940 struct mem_entry
*mem_tbl
;
12944 if (tg3_flag(tp
, 5717_PLUS
))
12945 mem_tbl
= mem_tbl_5717
;
12946 else if (tg3_flag(tp
, 57765_CLASS
) ||
12947 tg3_asic_rev(tp
) == ASIC_REV_5762
)
12948 mem_tbl
= mem_tbl_57765
;
12949 else if (tg3_flag(tp
, 5755_PLUS
))
12950 mem_tbl
= mem_tbl_5755
;
12951 else if (tg3_asic_rev(tp
) == ASIC_REV_5906
)
12952 mem_tbl
= mem_tbl_5906
;
12953 else if (tg3_flag(tp
, 5705_PLUS
))
12954 mem_tbl
= mem_tbl_5705
;
12956 mem_tbl
= mem_tbl_570x
;
12958 for (i
= 0; mem_tbl
[i
].offset
!= 0xffffffff; i
++) {
12959 err
= tg3_do_mem_test(tp
, mem_tbl
[i
].offset
, mem_tbl
[i
].len
);
12967 #define TG3_TSO_MSS 500
12969 #define TG3_TSO_IP_HDR_LEN 20
12970 #define TG3_TSO_TCP_HDR_LEN 20
12971 #define TG3_TSO_TCP_OPT_LEN 12
12973 static const u8 tg3_tso_header
[] = {
12975 0x45, 0x00, 0x00, 0x00,
12976 0x00, 0x00, 0x40, 0x00,
12977 0x40, 0x06, 0x00, 0x00,
12978 0x0a, 0x00, 0x00, 0x01,
12979 0x0a, 0x00, 0x00, 0x02,
12980 0x0d, 0x00, 0xe0, 0x00,
12981 0x00, 0x00, 0x01, 0x00,
12982 0x00, 0x00, 0x02, 0x00,
12983 0x80, 0x10, 0x10, 0x00,
12984 0x14, 0x09, 0x00, 0x00,
12985 0x01, 0x01, 0x08, 0x0a,
12986 0x11, 0x11, 0x11, 0x11,
12987 0x11, 0x11, 0x11, 0x11,
12990 static int tg3_run_loopback(struct tg3
*tp
, u32 pktsz
, bool tso_loopback
)
12992 u32 rx_start_idx
, rx_idx
, tx_idx
, opaque_key
;
12993 u32 base_flags
= 0, mss
= 0, desc_idx
, coal_now
, data_off
, val
;
12995 struct sk_buff
*skb
;
12996 u8
*tx_data
, *rx_data
;
12998 int num_pkts
, tx_len
, rx_len
, i
, err
;
12999 struct tg3_rx_buffer_desc
*desc
;
13000 struct tg3_napi
*tnapi
, *rnapi
;
13001 struct tg3_rx_prodring_set
*tpr
= &tp
->napi
[0].prodring
;
13003 tnapi
= &tp
->napi
[0];
13004 rnapi
= &tp
->napi
[0];
13005 if (tp
->irq_cnt
> 1) {
13006 if (tg3_flag(tp
, ENABLE_RSS
))
13007 rnapi
= &tp
->napi
[1];
13008 if (tg3_flag(tp
, ENABLE_TSS
))
13009 tnapi
= &tp
->napi
[1];
13011 coal_now
= tnapi
->coal_now
| rnapi
->coal_now
;
13016 skb
= netdev_alloc_skb(tp
->dev
, tx_len
);
13020 tx_data
= skb_put(skb
, tx_len
);
13021 memcpy(tx_data
, tp
->dev
->dev_addr
, 6);
13022 memset(tx_data
+ 6, 0x0, 8);
13024 tw32(MAC_RX_MTU_SIZE
, tx_len
+ ETH_FCS_LEN
);
13026 if (tso_loopback
) {
13027 struct iphdr
*iph
= (struct iphdr
*)&tx_data
[ETH_HLEN
];
13029 u32 hdr_len
= TG3_TSO_IP_HDR_LEN
+ TG3_TSO_TCP_HDR_LEN
+
13030 TG3_TSO_TCP_OPT_LEN
;
13032 memcpy(tx_data
+ ETH_ALEN
* 2, tg3_tso_header
,
13033 sizeof(tg3_tso_header
));
13036 val
= tx_len
- ETH_ALEN
* 2 - sizeof(tg3_tso_header
);
13037 num_pkts
= DIV_ROUND_UP(val
, TG3_TSO_MSS
);
13039 /* Set the total length field in the IP header */
13040 iph
->tot_len
= htons((u16
)(mss
+ hdr_len
));
13042 base_flags
= (TXD_FLAG_CPU_PRE_DMA
|
13043 TXD_FLAG_CPU_POST_DMA
);
13045 if (tg3_flag(tp
, HW_TSO_1
) ||
13046 tg3_flag(tp
, HW_TSO_2
) ||
13047 tg3_flag(tp
, HW_TSO_3
)) {
13049 val
= ETH_HLEN
+ TG3_TSO_IP_HDR_LEN
;
13050 th
= (struct tcphdr
*)&tx_data
[val
];
13053 base_flags
|= TXD_FLAG_TCPUDP_CSUM
;
13055 if (tg3_flag(tp
, HW_TSO_3
)) {
13056 mss
|= (hdr_len
& 0xc) << 12;
13057 if (hdr_len
& 0x10)
13058 base_flags
|= 0x00000010;
13059 base_flags
|= (hdr_len
& 0x3e0) << 5;
13060 } else if (tg3_flag(tp
, HW_TSO_2
))
13061 mss
|= hdr_len
<< 9;
13062 else if (tg3_flag(tp
, HW_TSO_1
) ||
13063 tg3_asic_rev(tp
) == ASIC_REV_5705
) {
13064 mss
|= (TG3_TSO_TCP_OPT_LEN
<< 9);
13066 base_flags
|= (TG3_TSO_TCP_OPT_LEN
<< 10);
13069 data_off
= ETH_ALEN
* 2 + sizeof(tg3_tso_header
);
13072 data_off
= ETH_HLEN
;
13074 if (tg3_flag(tp
, USE_JUMBO_BDFLAG
) &&
13075 tx_len
> VLAN_ETH_FRAME_LEN
)
13076 base_flags
|= TXD_FLAG_JMB_PKT
;
13079 for (i
= data_off
; i
< tx_len
; i
++)
13080 tx_data
[i
] = (u8
) (i
& 0xff);
13082 map
= pci_map_single(tp
->pdev
, skb
->data
, tx_len
, PCI_DMA_TODEVICE
);
13083 if (pci_dma_mapping_error(tp
->pdev
, map
)) {
13084 dev_kfree_skb(skb
);
13088 val
= tnapi
->tx_prod
;
13089 tnapi
->tx_buffers
[val
].skb
= skb
;
13090 dma_unmap_addr_set(&tnapi
->tx_buffers
[val
], mapping
, map
);
13092 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
13097 rx_start_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
13099 budget
= tg3_tx_avail(tnapi
);
13100 if (tg3_tx_frag_set(tnapi
, &val
, &budget
, map
, tx_len
,
13101 base_flags
| TXD_FLAG_END
, mss
, 0)) {
13102 tnapi
->tx_buffers
[val
].skb
= NULL
;
13103 dev_kfree_skb(skb
);
13109 /* Sync BD data before updating mailbox */
13112 tw32_tx_mbox(tnapi
->prodmbox
, tnapi
->tx_prod
);
13113 tr32_mailbox(tnapi
->prodmbox
);
13117 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
13118 for (i
= 0; i
< 35; i
++) {
13119 tw32_f(HOSTCC_MODE
, tp
->coalesce_mode
| HOSTCC_MODE_ENABLE
|
13124 tx_idx
= tnapi
->hw_status
->idx
[0].tx_consumer
;
13125 rx_idx
= rnapi
->hw_status
->idx
[0].rx_producer
;
13126 if ((tx_idx
== tnapi
->tx_prod
) &&
13127 (rx_idx
== (rx_start_idx
+ num_pkts
)))
13131 tg3_tx_skb_unmap(tnapi
, tnapi
->tx_prod
- 1, -1);
13132 dev_kfree_skb(skb
);
13134 if (tx_idx
!= tnapi
->tx_prod
)
13137 if (rx_idx
!= rx_start_idx
+ num_pkts
)
13141 while (rx_idx
!= rx_start_idx
) {
13142 desc
= &rnapi
->rx_rcb
[rx_start_idx
++];
13143 desc_idx
= desc
->opaque
& RXD_OPAQUE_INDEX_MASK
;
13144 opaque_key
= desc
->opaque
& RXD_OPAQUE_RING_MASK
;
13146 if ((desc
->err_vlan
& RXD_ERR_MASK
) != 0 &&
13147 (desc
->err_vlan
!= RXD_ERR_ODD_NIBBLE_RCVD_MII
))
13150 rx_len
= ((desc
->idx_len
& RXD_LEN_MASK
) >> RXD_LEN_SHIFT
)
13153 if (!tso_loopback
) {
13154 if (rx_len
!= tx_len
)
13157 if (pktsz
<= TG3_RX_STD_DMA_SZ
- ETH_FCS_LEN
) {
13158 if (opaque_key
!= RXD_OPAQUE_RING_STD
)
13161 if (opaque_key
!= RXD_OPAQUE_RING_JUMBO
)
13164 } else if ((desc
->type_flags
& RXD_FLAG_TCPUDP_CSUM
) &&
13165 (desc
->ip_tcp_csum
& RXD_TCPCSUM_MASK
)
13166 >> RXD_TCPCSUM_SHIFT
!= 0xffff) {
13170 if (opaque_key
== RXD_OPAQUE_RING_STD
) {
13171 rx_data
= tpr
->rx_std_buffers
[desc_idx
].data
;
13172 map
= dma_unmap_addr(&tpr
->rx_std_buffers
[desc_idx
],
13174 } else if (opaque_key
== RXD_OPAQUE_RING_JUMBO
) {
13175 rx_data
= tpr
->rx_jmb_buffers
[desc_idx
].data
;
13176 map
= dma_unmap_addr(&tpr
->rx_jmb_buffers
[desc_idx
],
13181 pci_dma_sync_single_for_cpu(tp
->pdev
, map
, rx_len
,
13182 PCI_DMA_FROMDEVICE
);
13184 rx_data
+= TG3_RX_OFFSET(tp
);
13185 for (i
= data_off
; i
< rx_len
; i
++, val
++) {
13186 if (*(rx_data
+ i
) != (u8
) (val
& 0xff))
13193 /* tg3_free_rings will unmap and free the rx_data */
13198 #define TG3_STD_LOOPBACK_FAILED 1
13199 #define TG3_JMB_LOOPBACK_FAILED 2
13200 #define TG3_TSO_LOOPBACK_FAILED 4
13201 #define TG3_LOOPBACK_FAILED \
13202 (TG3_STD_LOOPBACK_FAILED | \
13203 TG3_JMB_LOOPBACK_FAILED | \
13204 TG3_TSO_LOOPBACK_FAILED)
13206 static int tg3_test_loopback(struct tg3
*tp
, u64
*data
, bool do_extlpbk
)
13210 u32 jmb_pkt_sz
= 9000;
13213 jmb_pkt_sz
= tp
->dma_limit
- ETH_HLEN
;
13215 eee_cap
= tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
;
13216 tp
->phy_flags
&= ~TG3_PHYFLG_EEE_CAP
;
13218 if (!netif_running(tp
->dev
)) {
13219 data
[TG3_MAC_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13220 data
[TG3_PHY_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13222 data
[TG3_EXT_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13226 err
= tg3_reset_hw(tp
, true);
13228 data
[TG3_MAC_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13229 data
[TG3_PHY_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13231 data
[TG3_EXT_LOOPB_TEST
] = TG3_LOOPBACK_FAILED
;
13235 if (tg3_flag(tp
, ENABLE_RSS
)) {
13238 /* Reroute all rx packets to the 1st queue */
13239 for (i
= MAC_RSS_INDIR_TBL_0
;
13240 i
< MAC_RSS_INDIR_TBL_0
+ TG3_RSS_INDIR_TBL_SIZE
; i
+= 4)
13244 /* HW errata - mac loopback fails in some cases on 5780.
13245 * Normal traffic and PHY loopback are not affected by
13246 * errata. Also, the MAC loopback test is deprecated for
13247 * all newer ASIC revisions.
13249 if (tg3_asic_rev(tp
) != ASIC_REV_5780
&&
13250 !tg3_flag(tp
, CPMU_PRESENT
)) {
13251 tg3_mac_loopback(tp
, true);
13253 if (tg3_run_loopback(tp
, ETH_FRAME_LEN
, false))
13254 data
[TG3_MAC_LOOPB_TEST
] |= TG3_STD_LOOPBACK_FAILED
;
13256 if (tg3_flag(tp
, JUMBO_RING_ENABLE
) &&
13257 tg3_run_loopback(tp
, jmb_pkt_sz
+ ETH_HLEN
, false))
13258 data
[TG3_MAC_LOOPB_TEST
] |= TG3_JMB_LOOPBACK_FAILED
;
13260 tg3_mac_loopback(tp
, false);
13263 if (!(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) &&
13264 !tg3_flag(tp
, USE_PHYLIB
)) {
13267 tg3_phy_lpbk_set(tp
, 0, false);
13269 /* Wait for link */
13270 for (i
= 0; i
< 100; i
++) {
13271 if (tr32(MAC_TX_STATUS
) & TX_STATUS_LINK_UP
)
13276 if (tg3_run_loopback(tp
, ETH_FRAME_LEN
, false))
13277 data
[TG3_PHY_LOOPB_TEST
] |= TG3_STD_LOOPBACK_FAILED
;
13278 if (tg3_flag(tp
, TSO_CAPABLE
) &&
13279 tg3_run_loopback(tp
, ETH_FRAME_LEN
, true))
13280 data
[TG3_PHY_LOOPB_TEST
] |= TG3_TSO_LOOPBACK_FAILED
;
13281 if (tg3_flag(tp
, JUMBO_RING_ENABLE
) &&
13282 tg3_run_loopback(tp
, jmb_pkt_sz
+ ETH_HLEN
, false))
13283 data
[TG3_PHY_LOOPB_TEST
] |= TG3_JMB_LOOPBACK_FAILED
;
13286 tg3_phy_lpbk_set(tp
, 0, true);
13288 /* All link indications report up, but the hardware
13289 * isn't really ready for about 20 msec. Double it
13294 if (tg3_run_loopback(tp
, ETH_FRAME_LEN
, false))
13295 data
[TG3_EXT_LOOPB_TEST
] |=
13296 TG3_STD_LOOPBACK_FAILED
;
13297 if (tg3_flag(tp
, TSO_CAPABLE
) &&
13298 tg3_run_loopback(tp
, ETH_FRAME_LEN
, true))
13299 data
[TG3_EXT_LOOPB_TEST
] |=
13300 TG3_TSO_LOOPBACK_FAILED
;
13301 if (tg3_flag(tp
, JUMBO_RING_ENABLE
) &&
13302 tg3_run_loopback(tp
, jmb_pkt_sz
+ ETH_HLEN
, false))
13303 data
[TG3_EXT_LOOPB_TEST
] |=
13304 TG3_JMB_LOOPBACK_FAILED
;
13307 /* Re-enable gphy autopowerdown. */
13308 if (tp
->phy_flags
& TG3_PHYFLG_ENABLE_APD
)
13309 tg3_phy_toggle_apd(tp
, true);
13312 err
= (data
[TG3_MAC_LOOPB_TEST
] | data
[TG3_PHY_LOOPB_TEST
] |
13313 data
[TG3_EXT_LOOPB_TEST
]) ? -EIO
: 0;
13316 tp
->phy_flags
|= eee_cap
;
13321 static void tg3_self_test(struct net_device
*dev
, struct ethtool_test
*etest
,
13324 struct tg3
*tp
= netdev_priv(dev
);
13325 bool doextlpbk
= etest
->flags
& ETH_TEST_FL_EXTERNAL_LB
;
13327 if ((tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
) &&
13328 tg3_power_up(tp
)) {
13329 etest
->flags
|= ETH_TEST_FL_FAILED
;
13330 memset(data
, 1, sizeof(u64
) * TG3_NUM_TEST
);
13334 memset(data
, 0, sizeof(u64
) * TG3_NUM_TEST
);
13336 if (tg3_test_nvram(tp
) != 0) {
13337 etest
->flags
|= ETH_TEST_FL_FAILED
;
13338 data
[TG3_NVRAM_TEST
] = 1;
13340 if (!doextlpbk
&& tg3_test_link(tp
)) {
13341 etest
->flags
|= ETH_TEST_FL_FAILED
;
13342 data
[TG3_LINK_TEST
] = 1;
13344 if (etest
->flags
& ETH_TEST_FL_OFFLINE
) {
13345 int err
, err2
= 0, irq_sync
= 0;
13347 if (netif_running(dev
)) {
13349 tg3_netif_stop(tp
);
13353 tg3_full_lock(tp
, irq_sync
);
13354 tg3_halt(tp
, RESET_KIND_SUSPEND
, 1);
13355 err
= tg3_nvram_lock(tp
);
13356 tg3_halt_cpu(tp
, RX_CPU_BASE
);
13357 if (!tg3_flag(tp
, 5705_PLUS
))
13358 tg3_halt_cpu(tp
, TX_CPU_BASE
);
13360 tg3_nvram_unlock(tp
);
13362 if (tp
->phy_flags
& TG3_PHYFLG_MII_SERDES
)
13365 if (tg3_test_registers(tp
) != 0) {
13366 etest
->flags
|= ETH_TEST_FL_FAILED
;
13367 data
[TG3_REGISTER_TEST
] = 1;
13370 if (tg3_test_memory(tp
) != 0) {
13371 etest
->flags
|= ETH_TEST_FL_FAILED
;
13372 data
[TG3_MEMORY_TEST
] = 1;
13376 etest
->flags
|= ETH_TEST_FL_EXTERNAL_LB_DONE
;
13378 if (tg3_test_loopback(tp
, data
, doextlpbk
))
13379 etest
->flags
|= ETH_TEST_FL_FAILED
;
13381 tg3_full_unlock(tp
);
13383 if (tg3_test_interrupt(tp
) != 0) {
13384 etest
->flags
|= ETH_TEST_FL_FAILED
;
13385 data
[TG3_INTERRUPT_TEST
] = 1;
13388 tg3_full_lock(tp
, 0);
13390 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13391 if (netif_running(dev
)) {
13392 tg3_flag_set(tp
, INIT_COMPLETE
);
13393 err2
= tg3_restart_hw(tp
, true);
13395 tg3_netif_start(tp
);
13398 tg3_full_unlock(tp
);
13400 if (irq_sync
&& !err2
)
13403 if (tp
->phy_flags
& TG3_PHYFLG_IS_LOW_POWER
)
13404 tg3_power_down(tp
);
13408 static int tg3_hwtstamp_ioctl(struct net_device
*dev
,
13409 struct ifreq
*ifr
, int cmd
)
13411 struct tg3
*tp
= netdev_priv(dev
);
13412 struct hwtstamp_config stmpconf
;
13414 if (!tg3_flag(tp
, PTP_CAPABLE
))
13417 if (copy_from_user(&stmpconf
, ifr
->ifr_data
, sizeof(stmpconf
)))
13420 if (stmpconf
.flags
)
13423 switch (stmpconf
.tx_type
) {
13424 case HWTSTAMP_TX_ON
:
13425 tg3_flag_set(tp
, TX_TSTAMP_EN
);
13427 case HWTSTAMP_TX_OFF
:
13428 tg3_flag_clear(tp
, TX_TSTAMP_EN
);
13434 switch (stmpconf
.rx_filter
) {
13435 case HWTSTAMP_FILTER_NONE
:
13438 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
13439 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V1_EN
|
13440 TG3_RX_PTP_CTL_ALL_V1_EVENTS
;
13442 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
13443 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V1_EN
|
13444 TG3_RX_PTP_CTL_SYNC_EVNT
;
13446 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
13447 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V1_EN
|
13448 TG3_RX_PTP_CTL_DELAY_REQ
;
13450 case HWTSTAMP_FILTER_PTP_V2_EVENT
:
13451 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_EN
|
13452 TG3_RX_PTP_CTL_ALL_V2_EVENTS
;
13454 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT
:
13455 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
|
13456 TG3_RX_PTP_CTL_ALL_V2_EVENTS
;
13458 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
13459 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
|
13460 TG3_RX_PTP_CTL_ALL_V2_EVENTS
;
13462 case HWTSTAMP_FILTER_PTP_V2_SYNC
:
13463 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_EN
|
13464 TG3_RX_PTP_CTL_SYNC_EVNT
;
13466 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC
:
13467 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
|
13468 TG3_RX_PTP_CTL_SYNC_EVNT
;
13470 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
13471 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
|
13472 TG3_RX_PTP_CTL_SYNC_EVNT
;
13474 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ
:
13475 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_EN
|
13476 TG3_RX_PTP_CTL_DELAY_REQ
;
13478 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ
:
13479 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L2_EN
|
13480 TG3_RX_PTP_CTL_DELAY_REQ
;
13482 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
13483 tp
->rxptpctl
= TG3_RX_PTP_CTL_RX_PTP_V2_L4_EN
|
13484 TG3_RX_PTP_CTL_DELAY_REQ
;
13490 if (netif_running(dev
) && tp
->rxptpctl
)
13491 tw32(TG3_RX_PTP_CTL
,
13492 tp
->rxptpctl
| TG3_RX_PTP_CTL_HWTS_INTERLOCK
);
13494 return copy_to_user(ifr
->ifr_data
, &stmpconf
, sizeof(stmpconf
)) ?
13498 static int tg3_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
13500 struct mii_ioctl_data
*data
= if_mii(ifr
);
13501 struct tg3
*tp
= netdev_priv(dev
);
13504 if (tg3_flag(tp
, USE_PHYLIB
)) {
13505 struct phy_device
*phydev
;
13506 if (!(tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
))
13508 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
13509 return phy_mii_ioctl(phydev
, ifr
, cmd
);
13514 data
->phy_id
= tp
->phy_addr
;
13517 case SIOCGMIIREG
: {
13520 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
13521 break; /* We have no PHY */
13523 if (!netif_running(dev
))
13526 spin_lock_bh(&tp
->lock
);
13527 err
= __tg3_readphy(tp
, data
->phy_id
& 0x1f,
13528 data
->reg_num
& 0x1f, &mii_regval
);
13529 spin_unlock_bh(&tp
->lock
);
13531 data
->val_out
= mii_regval
;
13537 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
13538 break; /* We have no PHY */
13540 if (!netif_running(dev
))
13543 spin_lock_bh(&tp
->lock
);
13544 err
= __tg3_writephy(tp
, data
->phy_id
& 0x1f,
13545 data
->reg_num
& 0x1f, data
->val_in
);
13546 spin_unlock_bh(&tp
->lock
);
13550 case SIOCSHWTSTAMP
:
13551 return tg3_hwtstamp_ioctl(dev
, ifr
, cmd
);
13557 return -EOPNOTSUPP
;
13560 static int tg3_get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
13562 struct tg3
*tp
= netdev_priv(dev
);
13564 memcpy(ec
, &tp
->coal
, sizeof(*ec
));
13568 static int tg3_set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*ec
)
13570 struct tg3
*tp
= netdev_priv(dev
);
13571 u32 max_rxcoal_tick_int
= 0, max_txcoal_tick_int
= 0;
13572 u32 max_stat_coal_ticks
= 0, min_stat_coal_ticks
= 0;
13574 if (!tg3_flag(tp
, 5705_PLUS
)) {
13575 max_rxcoal_tick_int
= MAX_RXCOAL_TICK_INT
;
13576 max_txcoal_tick_int
= MAX_TXCOAL_TICK_INT
;
13577 max_stat_coal_ticks
= MAX_STAT_COAL_TICKS
;
13578 min_stat_coal_ticks
= MIN_STAT_COAL_TICKS
;
13581 if ((ec
->rx_coalesce_usecs
> MAX_RXCOL_TICKS
) ||
13582 (ec
->tx_coalesce_usecs
> MAX_TXCOL_TICKS
) ||
13583 (ec
->rx_max_coalesced_frames
> MAX_RXMAX_FRAMES
) ||
13584 (ec
->tx_max_coalesced_frames
> MAX_TXMAX_FRAMES
) ||
13585 (ec
->rx_coalesce_usecs_irq
> max_rxcoal_tick_int
) ||
13586 (ec
->tx_coalesce_usecs_irq
> max_txcoal_tick_int
) ||
13587 (ec
->rx_max_coalesced_frames_irq
> MAX_RXCOAL_MAXF_INT
) ||
13588 (ec
->tx_max_coalesced_frames_irq
> MAX_TXCOAL_MAXF_INT
) ||
13589 (ec
->stats_block_coalesce_usecs
> max_stat_coal_ticks
) ||
13590 (ec
->stats_block_coalesce_usecs
< min_stat_coal_ticks
))
13593 /* No rx interrupts will be generated if both are zero */
13594 if ((ec
->rx_coalesce_usecs
== 0) &&
13595 (ec
->rx_max_coalesced_frames
== 0))
13598 /* No tx interrupts will be generated if both are zero */
13599 if ((ec
->tx_coalesce_usecs
== 0) &&
13600 (ec
->tx_max_coalesced_frames
== 0))
13603 /* Only copy relevant parameters, ignore all others. */
13604 tp
->coal
.rx_coalesce_usecs
= ec
->rx_coalesce_usecs
;
13605 tp
->coal
.tx_coalesce_usecs
= ec
->tx_coalesce_usecs
;
13606 tp
->coal
.rx_max_coalesced_frames
= ec
->rx_max_coalesced_frames
;
13607 tp
->coal
.tx_max_coalesced_frames
= ec
->tx_max_coalesced_frames
;
13608 tp
->coal
.rx_coalesce_usecs_irq
= ec
->rx_coalesce_usecs_irq
;
13609 tp
->coal
.tx_coalesce_usecs_irq
= ec
->tx_coalesce_usecs_irq
;
13610 tp
->coal
.rx_max_coalesced_frames_irq
= ec
->rx_max_coalesced_frames_irq
;
13611 tp
->coal
.tx_max_coalesced_frames_irq
= ec
->tx_max_coalesced_frames_irq
;
13612 tp
->coal
.stats_block_coalesce_usecs
= ec
->stats_block_coalesce_usecs
;
13614 if (netif_running(dev
)) {
13615 tg3_full_lock(tp
, 0);
13616 __tg3_set_coalesce(tp
, &tp
->coal
);
13617 tg3_full_unlock(tp
);
13622 static const struct ethtool_ops tg3_ethtool_ops
= {
13623 .get_settings
= tg3_get_settings
,
13624 .set_settings
= tg3_set_settings
,
13625 .get_drvinfo
= tg3_get_drvinfo
,
13626 .get_regs_len
= tg3_get_regs_len
,
13627 .get_regs
= tg3_get_regs
,
13628 .get_wol
= tg3_get_wol
,
13629 .set_wol
= tg3_set_wol
,
13630 .get_msglevel
= tg3_get_msglevel
,
13631 .set_msglevel
= tg3_set_msglevel
,
13632 .nway_reset
= tg3_nway_reset
,
13633 .get_link
= ethtool_op_get_link
,
13634 .get_eeprom_len
= tg3_get_eeprom_len
,
13635 .get_eeprom
= tg3_get_eeprom
,
13636 .set_eeprom
= tg3_set_eeprom
,
13637 .get_ringparam
= tg3_get_ringparam
,
13638 .set_ringparam
= tg3_set_ringparam
,
13639 .get_pauseparam
= tg3_get_pauseparam
,
13640 .set_pauseparam
= tg3_set_pauseparam
,
13641 .self_test
= tg3_self_test
,
13642 .get_strings
= tg3_get_strings
,
13643 .set_phys_id
= tg3_set_phys_id
,
13644 .get_ethtool_stats
= tg3_get_ethtool_stats
,
13645 .get_coalesce
= tg3_get_coalesce
,
13646 .set_coalesce
= tg3_set_coalesce
,
13647 .get_sset_count
= tg3_get_sset_count
,
13648 .get_rxnfc
= tg3_get_rxnfc
,
13649 .get_rxfh_indir_size
= tg3_get_rxfh_indir_size
,
13650 .get_rxfh_indir
= tg3_get_rxfh_indir
,
13651 .set_rxfh_indir
= tg3_set_rxfh_indir
,
13652 .get_channels
= tg3_get_channels
,
13653 .set_channels
= tg3_set_channels
,
13654 .get_ts_info
= tg3_get_ts_info
,
13657 static struct rtnl_link_stats64
*tg3_get_stats64(struct net_device
*dev
,
13658 struct rtnl_link_stats64
*stats
)
13660 struct tg3
*tp
= netdev_priv(dev
);
13662 spin_lock_bh(&tp
->lock
);
13663 if (!tp
->hw_stats
) {
13664 spin_unlock_bh(&tp
->lock
);
13665 return &tp
->net_stats_prev
;
13668 tg3_get_nstats(tp
, stats
);
13669 spin_unlock_bh(&tp
->lock
);
13674 static void tg3_set_rx_mode(struct net_device
*dev
)
13676 struct tg3
*tp
= netdev_priv(dev
);
13678 if (!netif_running(dev
))
13681 tg3_full_lock(tp
, 0);
13682 __tg3_set_rx_mode(dev
);
13683 tg3_full_unlock(tp
);
13686 static inline void tg3_set_mtu(struct net_device
*dev
, struct tg3
*tp
,
13689 dev
->mtu
= new_mtu
;
13691 if (new_mtu
> ETH_DATA_LEN
) {
13692 if (tg3_flag(tp
, 5780_CLASS
)) {
13693 netdev_update_features(dev
);
13694 tg3_flag_clear(tp
, TSO_CAPABLE
);
13696 tg3_flag_set(tp
, JUMBO_RING_ENABLE
);
13699 if (tg3_flag(tp
, 5780_CLASS
)) {
13700 tg3_flag_set(tp
, TSO_CAPABLE
);
13701 netdev_update_features(dev
);
13703 tg3_flag_clear(tp
, JUMBO_RING_ENABLE
);
13707 static int tg3_change_mtu(struct net_device
*dev
, int new_mtu
)
13709 struct tg3
*tp
= netdev_priv(dev
);
13711 bool reset_phy
= false;
13713 if (new_mtu
< TG3_MIN_MTU
|| new_mtu
> TG3_MAX_MTU(tp
))
13716 if (!netif_running(dev
)) {
13717 /* We'll just catch it later when the
13720 tg3_set_mtu(dev
, tp
, new_mtu
);
13726 tg3_netif_stop(tp
);
13728 tg3_full_lock(tp
, 1);
13730 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
13732 tg3_set_mtu(dev
, tp
, new_mtu
);
13734 /* Reset PHY, otherwise the read DMA engine will be in a mode that
13735 * breaks all requests to 256 bytes.
13737 if (tg3_asic_rev(tp
) == ASIC_REV_57766
)
13740 err
= tg3_restart_hw(tp
, reset_phy
);
13743 tg3_netif_start(tp
);
13745 tg3_full_unlock(tp
);
13753 static const struct net_device_ops tg3_netdev_ops
= {
13754 .ndo_open
= tg3_open
,
13755 .ndo_stop
= tg3_close
,
13756 .ndo_start_xmit
= tg3_start_xmit
,
13757 .ndo_get_stats64
= tg3_get_stats64
,
13758 .ndo_validate_addr
= eth_validate_addr
,
13759 .ndo_set_rx_mode
= tg3_set_rx_mode
,
13760 .ndo_set_mac_address
= tg3_set_mac_addr
,
13761 .ndo_do_ioctl
= tg3_ioctl
,
13762 .ndo_tx_timeout
= tg3_tx_timeout
,
13763 .ndo_change_mtu
= tg3_change_mtu
,
13764 .ndo_fix_features
= tg3_fix_features
,
13765 .ndo_set_features
= tg3_set_features
,
13766 #ifdef CONFIG_NET_POLL_CONTROLLER
13767 .ndo_poll_controller
= tg3_poll_controller
,
13771 static void tg3_get_eeprom_size(struct tg3
*tp
)
13773 u32 cursize
, val
, magic
;
13775 tp
->nvram_size
= EEPROM_CHIP_SIZE
;
13777 if (tg3_nvram_read(tp
, 0, &magic
) != 0)
13780 if ((magic
!= TG3_EEPROM_MAGIC
) &&
13781 ((magic
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
) &&
13782 ((magic
& TG3_EEPROM_MAGIC_HW_MSK
) != TG3_EEPROM_MAGIC_HW
))
13786 * Size the chip by reading offsets at increasing powers of two.
13787 * When we encounter our validation signature, we know the addressing
13788 * has wrapped around, and thus have our chip size.
13792 while (cursize
< tp
->nvram_size
) {
13793 if (tg3_nvram_read(tp
, cursize
, &val
) != 0)
13802 tp
->nvram_size
= cursize
;
13805 static void tg3_get_nvram_size(struct tg3
*tp
)
13809 if (tg3_flag(tp
, NO_NVRAM
) || tg3_nvram_read(tp
, 0, &val
) != 0)
13812 /* Selfboot format */
13813 if (val
!= TG3_EEPROM_MAGIC
) {
13814 tg3_get_eeprom_size(tp
);
13818 if (tg3_nvram_read(tp
, 0xf0, &val
) == 0) {
13820 /* This is confusing. We want to operate on the
13821 * 16-bit value at offset 0xf2. The tg3_nvram_read()
13822 * call will read from NVRAM and byteswap the data
13823 * according to the byteswapping settings for all
13824 * other register accesses. This ensures the data we
13825 * want will always reside in the lower 16-bits.
13826 * However, the data in NVRAM is in LE format, which
13827 * means the data from the NVRAM read will always be
13828 * opposite the endianness of the CPU. The 16-bit
13829 * byteswap then brings the data to CPU endianness.
13831 tp
->nvram_size
= swab16((u16
)(val
& 0x0000ffff)) * 1024;
13835 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
13838 static void tg3_get_nvram_info(struct tg3
*tp
)
13842 nvcfg1
= tr32(NVRAM_CFG1
);
13843 if (nvcfg1
& NVRAM_CFG1_FLASHIF_ENAB
) {
13844 tg3_flag_set(tp
, FLASH
);
13846 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
13847 tw32(NVRAM_CFG1
, nvcfg1
);
13850 if (tg3_asic_rev(tp
) == ASIC_REV_5750
||
13851 tg3_flag(tp
, 5780_CLASS
)) {
13852 switch (nvcfg1
& NVRAM_CFG1_VENDOR_MASK
) {
13853 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED
:
13854 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
13855 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
13856 tg3_flag_set(tp
, NVRAM_BUFFERED
);
13858 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED
:
13859 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
13860 tp
->nvram_pagesize
= ATMEL_AT25F512_PAGE_SIZE
;
13862 case FLASH_VENDOR_ATMEL_EEPROM
:
13863 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
13864 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
13865 tg3_flag_set(tp
, NVRAM_BUFFERED
);
13867 case FLASH_VENDOR_ST
:
13868 tp
->nvram_jedecnum
= JEDEC_ST
;
13869 tp
->nvram_pagesize
= ST_M45PEX0_PAGE_SIZE
;
13870 tg3_flag_set(tp
, NVRAM_BUFFERED
);
13872 case FLASH_VENDOR_SAIFUN
:
13873 tp
->nvram_jedecnum
= JEDEC_SAIFUN
;
13874 tp
->nvram_pagesize
= SAIFUN_SA25F0XX_PAGE_SIZE
;
13876 case FLASH_VENDOR_SST_SMALL
:
13877 case FLASH_VENDOR_SST_LARGE
:
13878 tp
->nvram_jedecnum
= JEDEC_SST
;
13879 tp
->nvram_pagesize
= SST_25VF0X0_PAGE_SIZE
;
13883 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
13884 tp
->nvram_pagesize
= ATMEL_AT45DB0X1B_PAGE_SIZE
;
13885 tg3_flag_set(tp
, NVRAM_BUFFERED
);
13889 static void tg3_nvram_get_pagesize(struct tg3
*tp
, u32 nvmcfg1
)
13891 switch (nvmcfg1
& NVRAM_CFG1_5752PAGE_SIZE_MASK
) {
13892 case FLASH_5752PAGE_SIZE_256
:
13893 tp
->nvram_pagesize
= 256;
13895 case FLASH_5752PAGE_SIZE_512
:
13896 tp
->nvram_pagesize
= 512;
13898 case FLASH_5752PAGE_SIZE_1K
:
13899 tp
->nvram_pagesize
= 1024;
13901 case FLASH_5752PAGE_SIZE_2K
:
13902 tp
->nvram_pagesize
= 2048;
13904 case FLASH_5752PAGE_SIZE_4K
:
13905 tp
->nvram_pagesize
= 4096;
13907 case FLASH_5752PAGE_SIZE_264
:
13908 tp
->nvram_pagesize
= 264;
13910 case FLASH_5752PAGE_SIZE_528
:
13911 tp
->nvram_pagesize
= 528;
13916 static void tg3_get_5752_nvram_info(struct tg3
*tp
)
13920 nvcfg1
= tr32(NVRAM_CFG1
);
13922 /* NVRAM protection for TPM */
13923 if (nvcfg1
& (1 << 27))
13924 tg3_flag_set(tp
, PROTECTED_NVRAM
);
13926 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
13927 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ
:
13928 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ
:
13929 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
13930 tg3_flag_set(tp
, NVRAM_BUFFERED
);
13932 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
13933 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
13934 tg3_flag_set(tp
, NVRAM_BUFFERED
);
13935 tg3_flag_set(tp
, FLASH
);
13937 case FLASH_5752VENDOR_ST_M45PE10
:
13938 case FLASH_5752VENDOR_ST_M45PE20
:
13939 case FLASH_5752VENDOR_ST_M45PE40
:
13940 tp
->nvram_jedecnum
= JEDEC_ST
;
13941 tg3_flag_set(tp
, NVRAM_BUFFERED
);
13942 tg3_flag_set(tp
, FLASH
);
13946 if (tg3_flag(tp
, FLASH
)) {
13947 tg3_nvram_get_pagesize(tp
, nvcfg1
);
13949 /* For eeprom, set pagesize to maximum eeprom size */
13950 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
13952 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
13953 tw32(NVRAM_CFG1
, nvcfg1
);
13957 static void tg3_get_5755_nvram_info(struct tg3
*tp
)
13959 u32 nvcfg1
, protect
= 0;
13961 nvcfg1
= tr32(NVRAM_CFG1
);
13963 /* NVRAM protection for TPM */
13964 if (nvcfg1
& (1 << 27)) {
13965 tg3_flag_set(tp
, PROTECTED_NVRAM
);
13969 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
13971 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
13972 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
13973 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
13974 case FLASH_5755VENDOR_ATMEL_FLASH_5
:
13975 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
13976 tg3_flag_set(tp
, NVRAM_BUFFERED
);
13977 tg3_flag_set(tp
, FLASH
);
13978 tp
->nvram_pagesize
= 264;
13979 if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_1
||
13980 nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_5
)
13981 tp
->nvram_size
= (protect
? 0x3e200 :
13982 TG3_NVRAM_SIZE_512KB
);
13983 else if (nvcfg1
== FLASH_5755VENDOR_ATMEL_FLASH_2
)
13984 tp
->nvram_size
= (protect
? 0x1f200 :
13985 TG3_NVRAM_SIZE_256KB
);
13987 tp
->nvram_size
= (protect
? 0x1f200 :
13988 TG3_NVRAM_SIZE_128KB
);
13990 case FLASH_5752VENDOR_ST_M45PE10
:
13991 case FLASH_5752VENDOR_ST_M45PE20
:
13992 case FLASH_5752VENDOR_ST_M45PE40
:
13993 tp
->nvram_jedecnum
= JEDEC_ST
;
13994 tg3_flag_set(tp
, NVRAM_BUFFERED
);
13995 tg3_flag_set(tp
, FLASH
);
13996 tp
->nvram_pagesize
= 256;
13997 if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE10
)
13998 tp
->nvram_size
= (protect
?
13999 TG3_NVRAM_SIZE_64KB
:
14000 TG3_NVRAM_SIZE_128KB
);
14001 else if (nvcfg1
== FLASH_5752VENDOR_ST_M45PE20
)
14002 tp
->nvram_size
= (protect
?
14003 TG3_NVRAM_SIZE_64KB
:
14004 TG3_NVRAM_SIZE_256KB
);
14006 tp
->nvram_size
= (protect
?
14007 TG3_NVRAM_SIZE_128KB
:
14008 TG3_NVRAM_SIZE_512KB
);
14013 static void tg3_get_5787_nvram_info(struct tg3
*tp
)
14017 nvcfg1
= tr32(NVRAM_CFG1
);
14019 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14020 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ
:
14021 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
14022 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ
:
14023 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
14024 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14025 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14026 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14028 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14029 tw32(NVRAM_CFG1
, nvcfg1
);
14031 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
14032 case FLASH_5755VENDOR_ATMEL_FLASH_1
:
14033 case FLASH_5755VENDOR_ATMEL_FLASH_2
:
14034 case FLASH_5755VENDOR_ATMEL_FLASH_3
:
14035 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14036 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14037 tg3_flag_set(tp
, FLASH
);
14038 tp
->nvram_pagesize
= 264;
14040 case FLASH_5752VENDOR_ST_M45PE10
:
14041 case FLASH_5752VENDOR_ST_M45PE20
:
14042 case FLASH_5752VENDOR_ST_M45PE40
:
14043 tp
->nvram_jedecnum
= JEDEC_ST
;
14044 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14045 tg3_flag_set(tp
, FLASH
);
14046 tp
->nvram_pagesize
= 256;
14051 static void tg3_get_5761_nvram_info(struct tg3
*tp
)
14053 u32 nvcfg1
, protect
= 0;
14055 nvcfg1
= tr32(NVRAM_CFG1
);
14057 /* NVRAM protection for TPM */
14058 if (nvcfg1
& (1 << 27)) {
14059 tg3_flag_set(tp
, PROTECTED_NVRAM
);
14063 nvcfg1
&= NVRAM_CFG1_5752VENDOR_MASK
;
14065 case FLASH_5761VENDOR_ATMEL_ADB021D
:
14066 case FLASH_5761VENDOR_ATMEL_ADB041D
:
14067 case FLASH_5761VENDOR_ATMEL_ADB081D
:
14068 case FLASH_5761VENDOR_ATMEL_ADB161D
:
14069 case FLASH_5761VENDOR_ATMEL_MDB021D
:
14070 case FLASH_5761VENDOR_ATMEL_MDB041D
:
14071 case FLASH_5761VENDOR_ATMEL_MDB081D
:
14072 case FLASH_5761VENDOR_ATMEL_MDB161D
:
14073 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14074 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14075 tg3_flag_set(tp
, FLASH
);
14076 tg3_flag_set(tp
, NO_NVRAM_ADDR_TRANS
);
14077 tp
->nvram_pagesize
= 256;
14079 case FLASH_5761VENDOR_ST_A_M45PE20
:
14080 case FLASH_5761VENDOR_ST_A_M45PE40
:
14081 case FLASH_5761VENDOR_ST_A_M45PE80
:
14082 case FLASH_5761VENDOR_ST_A_M45PE16
:
14083 case FLASH_5761VENDOR_ST_M_M45PE20
:
14084 case FLASH_5761VENDOR_ST_M_M45PE40
:
14085 case FLASH_5761VENDOR_ST_M_M45PE80
:
14086 case FLASH_5761VENDOR_ST_M_M45PE16
:
14087 tp
->nvram_jedecnum
= JEDEC_ST
;
14088 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14089 tg3_flag_set(tp
, FLASH
);
14090 tp
->nvram_pagesize
= 256;
14095 tp
->nvram_size
= tr32(NVRAM_ADDR_LOCKOUT
);
14098 case FLASH_5761VENDOR_ATMEL_ADB161D
:
14099 case FLASH_5761VENDOR_ATMEL_MDB161D
:
14100 case FLASH_5761VENDOR_ST_A_M45PE16
:
14101 case FLASH_5761VENDOR_ST_M_M45PE16
:
14102 tp
->nvram_size
= TG3_NVRAM_SIZE_2MB
;
14104 case FLASH_5761VENDOR_ATMEL_ADB081D
:
14105 case FLASH_5761VENDOR_ATMEL_MDB081D
:
14106 case FLASH_5761VENDOR_ST_A_M45PE80
:
14107 case FLASH_5761VENDOR_ST_M_M45PE80
:
14108 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
14110 case FLASH_5761VENDOR_ATMEL_ADB041D
:
14111 case FLASH_5761VENDOR_ATMEL_MDB041D
:
14112 case FLASH_5761VENDOR_ST_A_M45PE40
:
14113 case FLASH_5761VENDOR_ST_M_M45PE40
:
14114 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14116 case FLASH_5761VENDOR_ATMEL_ADB021D
:
14117 case FLASH_5761VENDOR_ATMEL_MDB021D
:
14118 case FLASH_5761VENDOR_ST_A_M45PE20
:
14119 case FLASH_5761VENDOR_ST_M_M45PE20
:
14120 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14126 static void tg3_get_5906_nvram_info(struct tg3
*tp
)
14128 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14129 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14130 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14133 static void tg3_get_57780_nvram_info(struct tg3
*tp
)
14137 nvcfg1
= tr32(NVRAM_CFG1
);
14139 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14140 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ
:
14141 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ
:
14142 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14143 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14144 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14146 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14147 tw32(NVRAM_CFG1
, nvcfg1
);
14149 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
14150 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
14151 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
14152 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
14153 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
14154 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
14155 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
14156 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14157 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14158 tg3_flag_set(tp
, FLASH
);
14160 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14161 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED
:
14162 case FLASH_57780VENDOR_ATMEL_AT45DB011D
:
14163 case FLASH_57780VENDOR_ATMEL_AT45DB011B
:
14164 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14166 case FLASH_57780VENDOR_ATMEL_AT45DB021D
:
14167 case FLASH_57780VENDOR_ATMEL_AT45DB021B
:
14168 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14170 case FLASH_57780VENDOR_ATMEL_AT45DB041D
:
14171 case FLASH_57780VENDOR_ATMEL_AT45DB041B
:
14172 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14176 case FLASH_5752VENDOR_ST_M45PE10
:
14177 case FLASH_5752VENDOR_ST_M45PE20
:
14178 case FLASH_5752VENDOR_ST_M45PE40
:
14179 tp
->nvram_jedecnum
= JEDEC_ST
;
14180 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14181 tg3_flag_set(tp
, FLASH
);
14183 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14184 case FLASH_5752VENDOR_ST_M45PE10
:
14185 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14187 case FLASH_5752VENDOR_ST_M45PE20
:
14188 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14190 case FLASH_5752VENDOR_ST_M45PE40
:
14191 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14196 tg3_flag_set(tp
, NO_NVRAM
);
14200 tg3_nvram_get_pagesize(tp
, nvcfg1
);
14201 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
14202 tg3_flag_set(tp
, NO_NVRAM_ADDR_TRANS
);
14206 static void tg3_get_5717_nvram_info(struct tg3
*tp
)
14210 nvcfg1
= tr32(NVRAM_CFG1
);
14212 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14213 case FLASH_5717VENDOR_ATMEL_EEPROM
:
14214 case FLASH_5717VENDOR_MICRO_EEPROM
:
14215 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14216 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14217 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14219 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14220 tw32(NVRAM_CFG1
, nvcfg1
);
14222 case FLASH_5717VENDOR_ATMEL_MDB011D
:
14223 case FLASH_5717VENDOR_ATMEL_ADB011B
:
14224 case FLASH_5717VENDOR_ATMEL_ADB011D
:
14225 case FLASH_5717VENDOR_ATMEL_MDB021D
:
14226 case FLASH_5717VENDOR_ATMEL_ADB021B
:
14227 case FLASH_5717VENDOR_ATMEL_ADB021D
:
14228 case FLASH_5717VENDOR_ATMEL_45USPT
:
14229 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14230 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14231 tg3_flag_set(tp
, FLASH
);
14233 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14234 case FLASH_5717VENDOR_ATMEL_MDB021D
:
14235 /* Detect size with tg3_nvram_get_size() */
14237 case FLASH_5717VENDOR_ATMEL_ADB021B
:
14238 case FLASH_5717VENDOR_ATMEL_ADB021D
:
14239 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14242 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14246 case FLASH_5717VENDOR_ST_M_M25PE10
:
14247 case FLASH_5717VENDOR_ST_A_M25PE10
:
14248 case FLASH_5717VENDOR_ST_M_M45PE10
:
14249 case FLASH_5717VENDOR_ST_A_M45PE10
:
14250 case FLASH_5717VENDOR_ST_M_M25PE20
:
14251 case FLASH_5717VENDOR_ST_A_M25PE20
:
14252 case FLASH_5717VENDOR_ST_M_M45PE20
:
14253 case FLASH_5717VENDOR_ST_A_M45PE20
:
14254 case FLASH_5717VENDOR_ST_25USPT
:
14255 case FLASH_5717VENDOR_ST_45USPT
:
14256 tp
->nvram_jedecnum
= JEDEC_ST
;
14257 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14258 tg3_flag_set(tp
, FLASH
);
14260 switch (nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
) {
14261 case FLASH_5717VENDOR_ST_M_M25PE20
:
14262 case FLASH_5717VENDOR_ST_M_M45PE20
:
14263 /* Detect size with tg3_nvram_get_size() */
14265 case FLASH_5717VENDOR_ST_A_M25PE20
:
14266 case FLASH_5717VENDOR_ST_A_M45PE20
:
14267 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14270 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14275 tg3_flag_set(tp
, NO_NVRAM
);
14279 tg3_nvram_get_pagesize(tp
, nvcfg1
);
14280 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
14281 tg3_flag_set(tp
, NO_NVRAM_ADDR_TRANS
);
14284 static void tg3_get_5720_nvram_info(struct tg3
*tp
)
14286 u32 nvcfg1
, nvmpinstrp
;
14288 nvcfg1
= tr32(NVRAM_CFG1
);
14289 nvmpinstrp
= nvcfg1
& NVRAM_CFG1_5752VENDOR_MASK
;
14291 if (tg3_asic_rev(tp
) == ASIC_REV_5762
) {
14292 if (!(nvcfg1
& NVRAM_CFG1_5762VENDOR_MASK
)) {
14293 tg3_flag_set(tp
, NO_NVRAM
);
14297 switch (nvmpinstrp
) {
14298 case FLASH_5762_EEPROM_HD
:
14299 nvmpinstrp
= FLASH_5720_EEPROM_HD
;
14301 case FLASH_5762_EEPROM_LD
:
14302 nvmpinstrp
= FLASH_5720_EEPROM_LD
;
14304 case FLASH_5720VENDOR_M_ST_M45PE20
:
14305 /* This pinstrap supports multiple sizes, so force it
14306 * to read the actual size from location 0xf0.
14308 nvmpinstrp
= FLASH_5720VENDOR_ST_45USPT
;
14313 switch (nvmpinstrp
) {
14314 case FLASH_5720_EEPROM_HD
:
14315 case FLASH_5720_EEPROM_LD
:
14316 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14317 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14319 nvcfg1
&= ~NVRAM_CFG1_COMPAT_BYPASS
;
14320 tw32(NVRAM_CFG1
, nvcfg1
);
14321 if (nvmpinstrp
== FLASH_5720_EEPROM_HD
)
14322 tp
->nvram_pagesize
= ATMEL_AT24C512_CHIP_SIZE
;
14324 tp
->nvram_pagesize
= ATMEL_AT24C02_CHIP_SIZE
;
14326 case FLASH_5720VENDOR_M_ATMEL_DB011D
:
14327 case FLASH_5720VENDOR_A_ATMEL_DB011B
:
14328 case FLASH_5720VENDOR_A_ATMEL_DB011D
:
14329 case FLASH_5720VENDOR_M_ATMEL_DB021D
:
14330 case FLASH_5720VENDOR_A_ATMEL_DB021B
:
14331 case FLASH_5720VENDOR_A_ATMEL_DB021D
:
14332 case FLASH_5720VENDOR_M_ATMEL_DB041D
:
14333 case FLASH_5720VENDOR_A_ATMEL_DB041B
:
14334 case FLASH_5720VENDOR_A_ATMEL_DB041D
:
14335 case FLASH_5720VENDOR_M_ATMEL_DB081D
:
14336 case FLASH_5720VENDOR_A_ATMEL_DB081D
:
14337 case FLASH_5720VENDOR_ATMEL_45USPT
:
14338 tp
->nvram_jedecnum
= JEDEC_ATMEL
;
14339 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14340 tg3_flag_set(tp
, FLASH
);
14342 switch (nvmpinstrp
) {
14343 case FLASH_5720VENDOR_M_ATMEL_DB021D
:
14344 case FLASH_5720VENDOR_A_ATMEL_DB021B
:
14345 case FLASH_5720VENDOR_A_ATMEL_DB021D
:
14346 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14348 case FLASH_5720VENDOR_M_ATMEL_DB041D
:
14349 case FLASH_5720VENDOR_A_ATMEL_DB041B
:
14350 case FLASH_5720VENDOR_A_ATMEL_DB041D
:
14351 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14353 case FLASH_5720VENDOR_M_ATMEL_DB081D
:
14354 case FLASH_5720VENDOR_A_ATMEL_DB081D
:
14355 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
14358 if (tg3_asic_rev(tp
) != ASIC_REV_5762
)
14359 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14363 case FLASH_5720VENDOR_M_ST_M25PE10
:
14364 case FLASH_5720VENDOR_M_ST_M45PE10
:
14365 case FLASH_5720VENDOR_A_ST_M25PE10
:
14366 case FLASH_5720VENDOR_A_ST_M45PE10
:
14367 case FLASH_5720VENDOR_M_ST_M25PE20
:
14368 case FLASH_5720VENDOR_M_ST_M45PE20
:
14369 case FLASH_5720VENDOR_A_ST_M25PE20
:
14370 case FLASH_5720VENDOR_A_ST_M45PE20
:
14371 case FLASH_5720VENDOR_M_ST_M25PE40
:
14372 case FLASH_5720VENDOR_M_ST_M45PE40
:
14373 case FLASH_5720VENDOR_A_ST_M25PE40
:
14374 case FLASH_5720VENDOR_A_ST_M45PE40
:
14375 case FLASH_5720VENDOR_M_ST_M25PE80
:
14376 case FLASH_5720VENDOR_M_ST_M45PE80
:
14377 case FLASH_5720VENDOR_A_ST_M25PE80
:
14378 case FLASH_5720VENDOR_A_ST_M45PE80
:
14379 case FLASH_5720VENDOR_ST_25USPT
:
14380 case FLASH_5720VENDOR_ST_45USPT
:
14381 tp
->nvram_jedecnum
= JEDEC_ST
;
14382 tg3_flag_set(tp
, NVRAM_BUFFERED
);
14383 tg3_flag_set(tp
, FLASH
);
14385 switch (nvmpinstrp
) {
14386 case FLASH_5720VENDOR_M_ST_M25PE20
:
14387 case FLASH_5720VENDOR_M_ST_M45PE20
:
14388 case FLASH_5720VENDOR_A_ST_M25PE20
:
14389 case FLASH_5720VENDOR_A_ST_M45PE20
:
14390 tp
->nvram_size
= TG3_NVRAM_SIZE_256KB
;
14392 case FLASH_5720VENDOR_M_ST_M25PE40
:
14393 case FLASH_5720VENDOR_M_ST_M45PE40
:
14394 case FLASH_5720VENDOR_A_ST_M25PE40
:
14395 case FLASH_5720VENDOR_A_ST_M45PE40
:
14396 tp
->nvram_size
= TG3_NVRAM_SIZE_512KB
;
14398 case FLASH_5720VENDOR_M_ST_M25PE80
:
14399 case FLASH_5720VENDOR_M_ST_M45PE80
:
14400 case FLASH_5720VENDOR_A_ST_M25PE80
:
14401 case FLASH_5720VENDOR_A_ST_M45PE80
:
14402 tp
->nvram_size
= TG3_NVRAM_SIZE_1MB
;
14405 if (tg3_asic_rev(tp
) != ASIC_REV_5762
)
14406 tp
->nvram_size
= TG3_NVRAM_SIZE_128KB
;
14411 tg3_flag_set(tp
, NO_NVRAM
);
14415 tg3_nvram_get_pagesize(tp
, nvcfg1
);
14416 if (tp
->nvram_pagesize
!= 264 && tp
->nvram_pagesize
!= 528)
14417 tg3_flag_set(tp
, NO_NVRAM_ADDR_TRANS
);
14419 if (tg3_asic_rev(tp
) == ASIC_REV_5762
) {
14422 if (tg3_nvram_read(tp
, 0, &val
))
14425 if (val
!= TG3_EEPROM_MAGIC
&&
14426 (val
& TG3_EEPROM_MAGIC_FW_MSK
) != TG3_EEPROM_MAGIC_FW
)
14427 tg3_flag_set(tp
, NO_NVRAM
);
14431 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
14432 static void tg3_nvram_init(struct tg3
*tp
)
14434 if (tg3_flag(tp
, IS_SSB_CORE
)) {
14435 /* No NVRAM and EEPROM on the SSB Broadcom GigE core. */
14436 tg3_flag_clear(tp
, NVRAM
);
14437 tg3_flag_clear(tp
, NVRAM_BUFFERED
);
14438 tg3_flag_set(tp
, NO_NVRAM
);
14442 tw32_f(GRC_EEPROM_ADDR
,
14443 (EEPROM_ADDR_FSM_RESET
|
14444 (EEPROM_DEFAULT_CLOCK_PERIOD
<<
14445 EEPROM_ADDR_CLKPERD_SHIFT
)));
14449 /* Enable seeprom accesses. */
14450 tw32_f(GRC_LOCAL_CTRL
,
14451 tr32(GRC_LOCAL_CTRL
) | GRC_LCLCTRL_AUTO_SEEPROM
);
14454 if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
14455 tg3_asic_rev(tp
) != ASIC_REV_5701
) {
14456 tg3_flag_set(tp
, NVRAM
);
14458 if (tg3_nvram_lock(tp
)) {
14459 netdev_warn(tp
->dev
,
14460 "Cannot get nvram lock, %s failed\n",
14464 tg3_enable_nvram_access(tp
);
14466 tp
->nvram_size
= 0;
14468 if (tg3_asic_rev(tp
) == ASIC_REV_5752
)
14469 tg3_get_5752_nvram_info(tp
);
14470 else if (tg3_asic_rev(tp
) == ASIC_REV_5755
)
14471 tg3_get_5755_nvram_info(tp
);
14472 else if (tg3_asic_rev(tp
) == ASIC_REV_5787
||
14473 tg3_asic_rev(tp
) == ASIC_REV_5784
||
14474 tg3_asic_rev(tp
) == ASIC_REV_5785
)
14475 tg3_get_5787_nvram_info(tp
);
14476 else if (tg3_asic_rev(tp
) == ASIC_REV_5761
)
14477 tg3_get_5761_nvram_info(tp
);
14478 else if (tg3_asic_rev(tp
) == ASIC_REV_5906
)
14479 tg3_get_5906_nvram_info(tp
);
14480 else if (tg3_asic_rev(tp
) == ASIC_REV_57780
||
14481 tg3_flag(tp
, 57765_CLASS
))
14482 tg3_get_57780_nvram_info(tp
);
14483 else if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
14484 tg3_asic_rev(tp
) == ASIC_REV_5719
)
14485 tg3_get_5717_nvram_info(tp
);
14486 else if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
14487 tg3_asic_rev(tp
) == ASIC_REV_5762
)
14488 tg3_get_5720_nvram_info(tp
);
14490 tg3_get_nvram_info(tp
);
14492 if (tp
->nvram_size
== 0)
14493 tg3_get_nvram_size(tp
);
14495 tg3_disable_nvram_access(tp
);
14496 tg3_nvram_unlock(tp
);
14499 tg3_flag_clear(tp
, NVRAM
);
14500 tg3_flag_clear(tp
, NVRAM_BUFFERED
);
14502 tg3_get_eeprom_size(tp
);
14506 struct subsys_tbl_ent
{
14507 u16 subsys_vendor
, subsys_devid
;
14511 static struct subsys_tbl_ent subsys_id_to_phy_id
[] = {
14512 /* Broadcom boards. */
14513 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14514 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6
, TG3_PHY_ID_BCM5401
},
14515 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14516 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5
, TG3_PHY_ID_BCM5701
},
14517 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14518 TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6
, TG3_PHY_ID_BCM8002
},
14519 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14520 TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9
, 0 },
14521 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14522 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1
, TG3_PHY_ID_BCM5701
},
14523 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14524 TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8
, TG3_PHY_ID_BCM5701
},
14525 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14526 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7
, 0 },
14527 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14528 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10
, TG3_PHY_ID_BCM5701
},
14529 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14530 TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12
, TG3_PHY_ID_BCM5701
},
14531 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14532 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1
, TG3_PHY_ID_BCM5703
},
14533 { TG3PCI_SUBVENDOR_ID_BROADCOM
,
14534 TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2
, TG3_PHY_ID_BCM5703
},
14537 { TG3PCI_SUBVENDOR_ID_3COM
,
14538 TG3PCI_SUBDEVICE_ID_3COM_3C996T
, TG3_PHY_ID_BCM5401
},
14539 { TG3PCI_SUBVENDOR_ID_3COM
,
14540 TG3PCI_SUBDEVICE_ID_3COM_3C996BT
, TG3_PHY_ID_BCM5701
},
14541 { TG3PCI_SUBVENDOR_ID_3COM
,
14542 TG3PCI_SUBDEVICE_ID_3COM_3C996SX
, 0 },
14543 { TG3PCI_SUBVENDOR_ID_3COM
,
14544 TG3PCI_SUBDEVICE_ID_3COM_3C1000T
, TG3_PHY_ID_BCM5701
},
14545 { TG3PCI_SUBVENDOR_ID_3COM
,
14546 TG3PCI_SUBDEVICE_ID_3COM_3C940BR01
, TG3_PHY_ID_BCM5701
},
14549 { TG3PCI_SUBVENDOR_ID_DELL
,
14550 TG3PCI_SUBDEVICE_ID_DELL_VIPER
, TG3_PHY_ID_BCM5401
},
14551 { TG3PCI_SUBVENDOR_ID_DELL
,
14552 TG3PCI_SUBDEVICE_ID_DELL_JAGUAR
, TG3_PHY_ID_BCM5401
},
14553 { TG3PCI_SUBVENDOR_ID_DELL
,
14554 TG3PCI_SUBDEVICE_ID_DELL_MERLOT
, TG3_PHY_ID_BCM5411
},
14555 { TG3PCI_SUBVENDOR_ID_DELL
,
14556 TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT
, TG3_PHY_ID_BCM5411
},
14558 /* Compaq boards. */
14559 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
14560 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE
, TG3_PHY_ID_BCM5701
},
14561 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
14562 TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2
, TG3_PHY_ID_BCM5701
},
14563 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
14564 TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING
, 0 },
14565 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
14566 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780
, TG3_PHY_ID_BCM5701
},
14567 { TG3PCI_SUBVENDOR_ID_COMPAQ
,
14568 TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2
, TG3_PHY_ID_BCM5701
},
14571 { TG3PCI_SUBVENDOR_ID_IBM
,
14572 TG3PCI_SUBDEVICE_ID_IBM_5703SAX2
, 0 }
14575 static struct subsys_tbl_ent
*tg3_lookup_by_subsys(struct tg3
*tp
)
14579 for (i
= 0; i
< ARRAY_SIZE(subsys_id_to_phy_id
); i
++) {
14580 if ((subsys_id_to_phy_id
[i
].subsys_vendor
==
14581 tp
->pdev
->subsystem_vendor
) &&
14582 (subsys_id_to_phy_id
[i
].subsys_devid
==
14583 tp
->pdev
->subsystem_device
))
14584 return &subsys_id_to_phy_id
[i
];
14589 static void tg3_get_eeprom_hw_cfg(struct tg3
*tp
)
14593 tp
->phy_id
= TG3_PHY_ID_INVALID
;
14594 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
14596 /* Assume an onboard device and WOL capable by default. */
14597 tg3_flag_set(tp
, EEPROM_WRITE_PROT
);
14598 tg3_flag_set(tp
, WOL_CAP
);
14600 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
14601 if (!(tr32(PCIE_TRANSACTION_CFG
) & PCIE_TRANS_CFG_LOM
)) {
14602 tg3_flag_clear(tp
, EEPROM_WRITE_PROT
);
14603 tg3_flag_set(tp
, IS_NIC
);
14605 val
= tr32(VCPU_CFGSHDW
);
14606 if (val
& VCPU_CFGSHDW_ASPM_DBNC
)
14607 tg3_flag_set(tp
, ASPM_WORKAROUND
);
14608 if ((val
& VCPU_CFGSHDW_WOL_ENABLE
) &&
14609 (val
& VCPU_CFGSHDW_WOL_MAGPKT
)) {
14610 tg3_flag_set(tp
, WOL_ENABLE
);
14611 device_set_wakeup_enable(&tp
->pdev
->dev
, true);
14616 tg3_read_mem(tp
, NIC_SRAM_DATA_SIG
, &val
);
14617 if (val
== NIC_SRAM_DATA_SIG_MAGIC
) {
14618 u32 nic_cfg
, led_cfg
;
14619 u32 nic_phy_id
, ver
, cfg2
= 0, cfg4
= 0, eeprom_phy_id
;
14620 int eeprom_phy_serdes
= 0;
14622 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG
, &nic_cfg
);
14623 tp
->nic_sram_data_cfg
= nic_cfg
;
14625 tg3_read_mem(tp
, NIC_SRAM_DATA_VER
, &ver
);
14626 ver
>>= NIC_SRAM_DATA_VER_SHIFT
;
14627 if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
14628 tg3_asic_rev(tp
) != ASIC_REV_5701
&&
14629 tg3_asic_rev(tp
) != ASIC_REV_5703
&&
14630 (ver
> 0) && (ver
< 0x100))
14631 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_2
, &cfg2
);
14633 if (tg3_asic_rev(tp
) == ASIC_REV_5785
)
14634 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_4
, &cfg4
);
14636 if ((nic_cfg
& NIC_SRAM_DATA_CFG_PHY_TYPE_MASK
) ==
14637 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER
)
14638 eeprom_phy_serdes
= 1;
14640 tg3_read_mem(tp
, NIC_SRAM_DATA_PHY_ID
, &nic_phy_id
);
14641 if (nic_phy_id
!= 0) {
14642 u32 id1
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID1_MASK
;
14643 u32 id2
= nic_phy_id
& NIC_SRAM_DATA_PHY_ID2_MASK
;
14645 eeprom_phy_id
= (id1
>> 16) << 10;
14646 eeprom_phy_id
|= (id2
& 0xfc00) << 16;
14647 eeprom_phy_id
|= (id2
& 0x03ff) << 0;
14651 tp
->phy_id
= eeprom_phy_id
;
14652 if (eeprom_phy_serdes
) {
14653 if (!tg3_flag(tp
, 5705_PLUS
))
14654 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
14656 tp
->phy_flags
|= TG3_PHYFLG_MII_SERDES
;
14659 if (tg3_flag(tp
, 5750_PLUS
))
14660 led_cfg
= cfg2
& (NIC_SRAM_DATA_CFG_LED_MODE_MASK
|
14661 SHASTA_EXT_LED_MODE_MASK
);
14663 led_cfg
= nic_cfg
& NIC_SRAM_DATA_CFG_LED_MODE_MASK
;
14667 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1
:
14668 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
14671 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2
:
14672 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
14675 case NIC_SRAM_DATA_CFG_LED_MODE_MAC
:
14676 tp
->led_ctrl
= LED_CTRL_MODE_MAC
;
14678 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
14679 * read on some older 5700/5701 bootcode.
14681 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
14682 tg3_asic_rev(tp
) == ASIC_REV_5701
)
14683 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
14687 case SHASTA_EXT_LED_SHARED
:
14688 tp
->led_ctrl
= LED_CTRL_MODE_SHARED
;
14689 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A0
&&
14690 tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A1
)
14691 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
14692 LED_CTRL_MODE_PHY_2
);
14695 case SHASTA_EXT_LED_MAC
:
14696 tp
->led_ctrl
= LED_CTRL_MODE_SHASTA_MAC
;
14699 case SHASTA_EXT_LED_COMBO
:
14700 tp
->led_ctrl
= LED_CTRL_MODE_COMBO
;
14701 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5750_A0
)
14702 tp
->led_ctrl
|= (LED_CTRL_MODE_PHY_1
|
14703 LED_CTRL_MODE_PHY_2
);
14708 if ((tg3_asic_rev(tp
) == ASIC_REV_5700
||
14709 tg3_asic_rev(tp
) == ASIC_REV_5701
) &&
14710 tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
)
14711 tp
->led_ctrl
= LED_CTRL_MODE_PHY_2
;
14713 if (tg3_chip_rev(tp
) == CHIPREV_5784_AX
)
14714 tp
->led_ctrl
= LED_CTRL_MODE_PHY_1
;
14716 if (nic_cfg
& NIC_SRAM_DATA_CFG_EEPROM_WP
) {
14717 tg3_flag_set(tp
, EEPROM_WRITE_PROT
);
14718 if ((tp
->pdev
->subsystem_vendor
==
14719 PCI_VENDOR_ID_ARIMA
) &&
14720 (tp
->pdev
->subsystem_device
== 0x205a ||
14721 tp
->pdev
->subsystem_device
== 0x2063))
14722 tg3_flag_clear(tp
, EEPROM_WRITE_PROT
);
14724 tg3_flag_clear(tp
, EEPROM_WRITE_PROT
);
14725 tg3_flag_set(tp
, IS_NIC
);
14728 if (nic_cfg
& NIC_SRAM_DATA_CFG_ASF_ENABLE
) {
14729 tg3_flag_set(tp
, ENABLE_ASF
);
14730 if (tg3_flag(tp
, 5750_PLUS
))
14731 tg3_flag_set(tp
, ASF_NEW_HANDSHAKE
);
14734 if ((nic_cfg
& NIC_SRAM_DATA_CFG_APE_ENABLE
) &&
14735 tg3_flag(tp
, 5750_PLUS
))
14736 tg3_flag_set(tp
, ENABLE_APE
);
14738 if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
&&
14739 !(nic_cfg
& NIC_SRAM_DATA_CFG_FIBER_WOL
))
14740 tg3_flag_clear(tp
, WOL_CAP
);
14742 if (tg3_flag(tp
, WOL_CAP
) &&
14743 (nic_cfg
& NIC_SRAM_DATA_CFG_WOL_ENABLE
)) {
14744 tg3_flag_set(tp
, WOL_ENABLE
);
14745 device_set_wakeup_enable(&tp
->pdev
->dev
, true);
14748 if (cfg2
& (1 << 17))
14749 tp
->phy_flags
|= TG3_PHYFLG_CAPACITIVE_COUPLING
;
14751 /* serdes signal pre-emphasis in register 0x590 set by */
14752 /* bootcode if bit 18 is set */
14753 if (cfg2
& (1 << 18))
14754 tp
->phy_flags
|= TG3_PHYFLG_SERDES_PREEMPHASIS
;
14756 if ((tg3_flag(tp
, 57765_PLUS
) ||
14757 (tg3_asic_rev(tp
) == ASIC_REV_5784
&&
14758 tg3_chip_rev(tp
) != CHIPREV_5784_AX
)) &&
14759 (cfg2
& NIC_SRAM_DATA_CFG_2_APD_EN
))
14760 tp
->phy_flags
|= TG3_PHYFLG_ENABLE_APD
;
14762 if (tg3_flag(tp
, PCI_EXPRESS
)) {
14765 tg3_read_mem(tp
, NIC_SRAM_DATA_CFG_3
, &cfg3
);
14766 if (tg3_asic_rev(tp
) != ASIC_REV_5785
&&
14767 !tg3_flag(tp
, 57765_PLUS
) &&
14768 (cfg3
& NIC_SRAM_ASPM_DEBOUNCE
))
14769 tg3_flag_set(tp
, ASPM_WORKAROUND
);
14770 if (cfg3
& NIC_SRAM_LNK_FLAP_AVOID
)
14771 tp
->phy_flags
|= TG3_PHYFLG_KEEP_LINK_ON_PWRDN
;
14772 if (cfg3
& NIC_SRAM_1G_ON_VAUX_OK
)
14773 tp
->phy_flags
|= TG3_PHYFLG_1G_ON_VAUX_OK
;
14776 if (cfg4
& NIC_SRAM_RGMII_INBAND_DISABLE
)
14777 tg3_flag_set(tp
, RGMII_INBAND_DISABLE
);
14778 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_RX_EN
)
14779 tg3_flag_set(tp
, RGMII_EXT_IBND_RX_EN
);
14780 if (cfg4
& NIC_SRAM_RGMII_EXT_IBND_TX_EN
)
14781 tg3_flag_set(tp
, RGMII_EXT_IBND_TX_EN
);
14784 if (tg3_flag(tp
, WOL_CAP
))
14785 device_set_wakeup_enable(&tp
->pdev
->dev
,
14786 tg3_flag(tp
, WOL_ENABLE
));
14788 device_set_wakeup_capable(&tp
->pdev
->dev
, false);
14791 static int tg3_ape_otp_read(struct tg3
*tp
, u32 offset
, u32
*val
)
14794 u32 val2
, off
= offset
* 8;
14796 err
= tg3_nvram_lock(tp
);
14800 tg3_ape_write32(tp
, TG3_APE_OTP_ADDR
, off
| APE_OTP_ADDR_CPU_ENABLE
);
14801 tg3_ape_write32(tp
, TG3_APE_OTP_CTRL
, APE_OTP_CTRL_PROG_EN
|
14802 APE_OTP_CTRL_CMD_RD
| APE_OTP_CTRL_START
);
14803 tg3_ape_read32(tp
, TG3_APE_OTP_CTRL
);
14806 for (i
= 0; i
< 100; i
++) {
14807 val2
= tg3_ape_read32(tp
, TG3_APE_OTP_STATUS
);
14808 if (val2
& APE_OTP_STATUS_CMD_DONE
) {
14809 *val
= tg3_ape_read32(tp
, TG3_APE_OTP_RD_DATA
);
14815 tg3_ape_write32(tp
, TG3_APE_OTP_CTRL
, 0);
14817 tg3_nvram_unlock(tp
);
14818 if (val2
& APE_OTP_STATUS_CMD_DONE
)
14824 static int tg3_issue_otp_command(struct tg3
*tp
, u32 cmd
)
14829 tw32(OTP_CTRL
, cmd
| OTP_CTRL_OTP_CMD_START
);
14830 tw32(OTP_CTRL
, cmd
);
14832 /* Wait for up to 1 ms for command to execute. */
14833 for (i
= 0; i
< 100; i
++) {
14834 val
= tr32(OTP_STATUS
);
14835 if (val
& OTP_STATUS_CMD_DONE
)
14840 return (val
& OTP_STATUS_CMD_DONE
) ? 0 : -EBUSY
;
14843 /* Read the gphy configuration from the OTP region of the chip. The gphy
14844 * configuration is a 32-bit value that straddles the alignment boundary.
14845 * We do two 32-bit reads and then shift and merge the results.
14847 static u32
tg3_read_otp_phycfg(struct tg3
*tp
)
14849 u32 bhalf_otp
, thalf_otp
;
14851 tw32(OTP_MODE
, OTP_MODE_OTP_THRU_GRC
);
14853 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_INIT
))
14856 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC1
);
14858 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
14861 thalf_otp
= tr32(OTP_READ_DATA
);
14863 tw32(OTP_ADDRESS
, OTP_ADDRESS_MAGIC2
);
14865 if (tg3_issue_otp_command(tp
, OTP_CTRL_OTP_CMD_READ
))
14868 bhalf_otp
= tr32(OTP_READ_DATA
);
14870 return ((thalf_otp
& 0x0000ffff) << 16) | (bhalf_otp
>> 16);
14873 static void tg3_phy_init_link_config(struct tg3
*tp
)
14875 u32 adv
= ADVERTISED_Autoneg
;
14877 if (!(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
14878 adv
|= ADVERTISED_1000baseT_Half
|
14879 ADVERTISED_1000baseT_Full
;
14881 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
14882 adv
|= ADVERTISED_100baseT_Half
|
14883 ADVERTISED_100baseT_Full
|
14884 ADVERTISED_10baseT_Half
|
14885 ADVERTISED_10baseT_Full
|
14888 adv
|= ADVERTISED_FIBRE
;
14890 tp
->link_config
.advertising
= adv
;
14891 tp
->link_config
.speed
= SPEED_UNKNOWN
;
14892 tp
->link_config
.duplex
= DUPLEX_UNKNOWN
;
14893 tp
->link_config
.autoneg
= AUTONEG_ENABLE
;
14894 tp
->link_config
.active_speed
= SPEED_UNKNOWN
;
14895 tp
->link_config
.active_duplex
= DUPLEX_UNKNOWN
;
14900 static int tg3_phy_probe(struct tg3
*tp
)
14902 u32 hw_phy_id_1
, hw_phy_id_2
;
14903 u32 hw_phy_id
, hw_phy_id_masked
;
14906 /* flow control autonegotiation is default behavior */
14907 tg3_flag_set(tp
, PAUSE_AUTONEG
);
14908 tp
->link_config
.flowctrl
= FLOW_CTRL_TX
| FLOW_CTRL_RX
;
14910 if (tg3_flag(tp
, ENABLE_APE
)) {
14911 switch (tp
->pci_fn
) {
14913 tp
->phy_ape_lock
= TG3_APE_LOCK_PHY0
;
14916 tp
->phy_ape_lock
= TG3_APE_LOCK_PHY1
;
14919 tp
->phy_ape_lock
= TG3_APE_LOCK_PHY2
;
14922 tp
->phy_ape_lock
= TG3_APE_LOCK_PHY3
;
14927 if (!tg3_flag(tp
, ENABLE_ASF
) &&
14928 !(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
14929 !(tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
))
14930 tp
->phy_flags
&= ~(TG3_PHYFLG_1G_ON_VAUX_OK
|
14931 TG3_PHYFLG_KEEP_LINK_ON_PWRDN
);
14933 if (tg3_flag(tp
, USE_PHYLIB
))
14934 return tg3_phy_init(tp
);
14936 /* Reading the PHY ID register can conflict with ASF
14937 * firmware access to the PHY hardware.
14940 if (tg3_flag(tp
, ENABLE_ASF
) || tg3_flag(tp
, ENABLE_APE
)) {
14941 hw_phy_id
= hw_phy_id_masked
= TG3_PHY_ID_INVALID
;
14943 /* Now read the physical PHY_ID from the chip and verify
14944 * that it is sane. If it doesn't look good, we fall back
14945 * to either the hard-coded table based PHY_ID and failing
14946 * that the value found in the eeprom area.
14948 err
|= tg3_readphy(tp
, MII_PHYSID1
, &hw_phy_id_1
);
14949 err
|= tg3_readphy(tp
, MII_PHYSID2
, &hw_phy_id_2
);
14951 hw_phy_id
= (hw_phy_id_1
& 0xffff) << 10;
14952 hw_phy_id
|= (hw_phy_id_2
& 0xfc00) << 16;
14953 hw_phy_id
|= (hw_phy_id_2
& 0x03ff) << 0;
14955 hw_phy_id_masked
= hw_phy_id
& TG3_PHY_ID_MASK
;
14958 if (!err
&& TG3_KNOWN_PHY_ID(hw_phy_id_masked
)) {
14959 tp
->phy_id
= hw_phy_id
;
14960 if (hw_phy_id_masked
== TG3_PHY_ID_BCM8002
)
14961 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
14963 tp
->phy_flags
&= ~TG3_PHYFLG_PHY_SERDES
;
14965 if (tp
->phy_id
!= TG3_PHY_ID_INVALID
) {
14966 /* Do nothing, phy ID already set up in
14967 * tg3_get_eeprom_hw_cfg().
14970 struct subsys_tbl_ent
*p
;
14972 /* No eeprom signature? Try the hardcoded
14973 * subsys device table.
14975 p
= tg3_lookup_by_subsys(tp
);
14977 tp
->phy_id
= p
->phy_id
;
14978 } else if (!tg3_flag(tp
, IS_SSB_CORE
)) {
14979 /* For now we saw the IDs 0xbc050cd0,
14980 * 0xbc050f80 and 0xbc050c30 on devices
14981 * connected to an BCM4785 and there are
14982 * probably more. Just assume that the phy is
14983 * supported when it is connected to a SSB core
14990 tp
->phy_id
== TG3_PHY_ID_BCM8002
)
14991 tp
->phy_flags
|= TG3_PHYFLG_PHY_SERDES
;
14995 if (!(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
14996 (tg3_asic_rev(tp
) == ASIC_REV_5719
||
14997 tg3_asic_rev(tp
) == ASIC_REV_5720
||
14998 tg3_asic_rev(tp
) == ASIC_REV_57766
||
14999 tg3_asic_rev(tp
) == ASIC_REV_5762
||
15000 (tg3_asic_rev(tp
) == ASIC_REV_5717
&&
15001 tg3_chip_rev_id(tp
) != CHIPREV_ID_5717_A0
) ||
15002 (tg3_asic_rev(tp
) == ASIC_REV_57765
&&
15003 tg3_chip_rev_id(tp
) != CHIPREV_ID_57765_A0
))) {
15004 tp
->phy_flags
|= TG3_PHYFLG_EEE_CAP
;
15006 tp
->eee
.supported
= SUPPORTED_100baseT_Full
|
15007 SUPPORTED_1000baseT_Full
;
15008 tp
->eee
.advertised
= ADVERTISED_100baseT_Full
|
15009 ADVERTISED_1000baseT_Full
;
15010 tp
->eee
.eee_enabled
= 1;
15011 tp
->eee
.tx_lpi_enabled
= 1;
15012 tp
->eee
.tx_lpi_timer
= TG3_CPMU_DBTMR1_LNKIDLE_2047US
;
15015 tg3_phy_init_link_config(tp
);
15017 if (!(tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
) &&
15018 !(tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
) &&
15019 !tg3_flag(tp
, ENABLE_APE
) &&
15020 !tg3_flag(tp
, ENABLE_ASF
)) {
15023 tg3_readphy(tp
, MII_BMSR
, &bmsr
);
15024 if (!tg3_readphy(tp
, MII_BMSR
, &bmsr
) &&
15025 (bmsr
& BMSR_LSTATUS
))
15026 goto skip_phy_reset
;
15028 err
= tg3_phy_reset(tp
);
15032 tg3_phy_set_wirespeed(tp
);
15034 if (!tg3_phy_copper_an_config_ok(tp
, &dummy
)) {
15035 tg3_phy_autoneg_cfg(tp
, tp
->link_config
.advertising
,
15036 tp
->link_config
.flowctrl
);
15038 tg3_writephy(tp
, MII_BMCR
,
15039 BMCR_ANENABLE
| BMCR_ANRESTART
);
15044 if ((tp
->phy_id
& TG3_PHY_ID_MASK
) == TG3_PHY_ID_BCM5401
) {
15045 err
= tg3_init_5401phy_dsp(tp
);
15049 err
= tg3_init_5401phy_dsp(tp
);
15055 static void tg3_read_vpd(struct tg3
*tp
)
15058 unsigned int block_end
, rosize
, len
;
15062 vpd_data
= (u8
*)tg3_vpd_readblock(tp
, &vpdlen
);
15066 i
= pci_vpd_find_tag(vpd_data
, 0, vpdlen
, PCI_VPD_LRDT_RO_DATA
);
15068 goto out_not_found
;
15070 rosize
= pci_vpd_lrdt_size(&vpd_data
[i
]);
15071 block_end
= i
+ PCI_VPD_LRDT_TAG_SIZE
+ rosize
;
15072 i
+= PCI_VPD_LRDT_TAG_SIZE
;
15074 if (block_end
> vpdlen
)
15075 goto out_not_found
;
15077 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
15078 PCI_VPD_RO_KEYWORD_MFR_ID
);
15080 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
15082 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
15083 if (j
+ len
> block_end
|| len
!= 4 ||
15084 memcmp(&vpd_data
[j
], "1028", 4))
15087 j
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
15088 PCI_VPD_RO_KEYWORD_VENDOR0
);
15092 len
= pci_vpd_info_field_size(&vpd_data
[j
]);
15094 j
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
15095 if (j
+ len
> block_end
)
15098 if (len
>= sizeof(tp
->fw_ver
))
15099 len
= sizeof(tp
->fw_ver
) - 1;
15100 memset(tp
->fw_ver
, 0, sizeof(tp
->fw_ver
));
15101 snprintf(tp
->fw_ver
, sizeof(tp
->fw_ver
), "%.*s bc ", len
,
15106 i
= pci_vpd_find_info_keyword(vpd_data
, i
, rosize
,
15107 PCI_VPD_RO_KEYWORD_PARTNO
);
15109 goto out_not_found
;
15111 len
= pci_vpd_info_field_size(&vpd_data
[i
]);
15113 i
+= PCI_VPD_INFO_FLD_HDR_SIZE
;
15114 if (len
> TG3_BPN_SIZE
||
15115 (len
+ i
) > vpdlen
)
15116 goto out_not_found
;
15118 memcpy(tp
->board_part_number
, &vpd_data
[i
], len
);
15122 if (tp
->board_part_number
[0])
15126 if (tg3_asic_rev(tp
) == ASIC_REV_5717
) {
15127 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
15128 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717_C
)
15129 strcpy(tp
->board_part_number
, "BCM5717");
15130 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
)
15131 strcpy(tp
->board_part_number
, "BCM5718");
15134 } else if (tg3_asic_rev(tp
) == ASIC_REV_57780
) {
15135 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57780
)
15136 strcpy(tp
->board_part_number
, "BCM57780");
15137 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57760
)
15138 strcpy(tp
->board_part_number
, "BCM57760");
15139 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57790
)
15140 strcpy(tp
->board_part_number
, "BCM57790");
15141 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57788
)
15142 strcpy(tp
->board_part_number
, "BCM57788");
15145 } else if (tg3_asic_rev(tp
) == ASIC_REV_57765
) {
15146 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
)
15147 strcpy(tp
->board_part_number
, "BCM57761");
15148 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
)
15149 strcpy(tp
->board_part_number
, "BCM57765");
15150 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
)
15151 strcpy(tp
->board_part_number
, "BCM57781");
15152 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
)
15153 strcpy(tp
->board_part_number
, "BCM57785");
15154 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
)
15155 strcpy(tp
->board_part_number
, "BCM57791");
15156 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
)
15157 strcpy(tp
->board_part_number
, "BCM57795");
15160 } else if (tg3_asic_rev(tp
) == ASIC_REV_57766
) {
15161 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57762
)
15162 strcpy(tp
->board_part_number
, "BCM57762");
15163 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57766
)
15164 strcpy(tp
->board_part_number
, "BCM57766");
15165 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57782
)
15166 strcpy(tp
->board_part_number
, "BCM57782");
15167 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57786
)
15168 strcpy(tp
->board_part_number
, "BCM57786");
15171 } else if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
15172 strcpy(tp
->board_part_number
, "BCM95906");
15175 strcpy(tp
->board_part_number
, "none");
15179 static int tg3_fw_img_is_valid(struct tg3
*tp
, u32 offset
)
15183 if (tg3_nvram_read(tp
, offset
, &val
) ||
15184 (val
& 0xfc000000) != 0x0c000000 ||
15185 tg3_nvram_read(tp
, offset
+ 4, &val
) ||
15192 static void tg3_read_bc_ver(struct tg3
*tp
)
15194 u32 val
, offset
, start
, ver_offset
;
15196 bool newver
= false;
15198 if (tg3_nvram_read(tp
, 0xc, &offset
) ||
15199 tg3_nvram_read(tp
, 0x4, &start
))
15202 offset
= tg3_nvram_logical_addr(tp
, offset
);
15204 if (tg3_nvram_read(tp
, offset
, &val
))
15207 if ((val
& 0xfc000000) == 0x0c000000) {
15208 if (tg3_nvram_read(tp
, offset
+ 4, &val
))
15215 dst_off
= strlen(tp
->fw_ver
);
15218 if (TG3_VER_SIZE
- dst_off
< 16 ||
15219 tg3_nvram_read(tp
, offset
+ 8, &ver_offset
))
15222 offset
= offset
+ ver_offset
- start
;
15223 for (i
= 0; i
< 16; i
+= 4) {
15225 if (tg3_nvram_read_be32(tp
, offset
+ i
, &v
))
15228 memcpy(tp
->fw_ver
+ dst_off
+ i
, &v
, sizeof(v
));
15233 if (tg3_nvram_read(tp
, TG3_NVM_PTREV_BCVER
, &ver_offset
))
15236 major
= (ver_offset
& TG3_NVM_BCVER_MAJMSK
) >>
15237 TG3_NVM_BCVER_MAJSFT
;
15238 minor
= ver_offset
& TG3_NVM_BCVER_MINMSK
;
15239 snprintf(&tp
->fw_ver
[dst_off
], TG3_VER_SIZE
- dst_off
,
15240 "v%d.%02d", major
, minor
);
15244 static void tg3_read_hwsb_ver(struct tg3
*tp
)
15246 u32 val
, major
, minor
;
15248 /* Use native endian representation */
15249 if (tg3_nvram_read(tp
, TG3_NVM_HWSB_CFG1
, &val
))
15252 major
= (val
& TG3_NVM_HWSB_CFG1_MAJMSK
) >>
15253 TG3_NVM_HWSB_CFG1_MAJSFT
;
15254 minor
= (val
& TG3_NVM_HWSB_CFG1_MINMSK
) >>
15255 TG3_NVM_HWSB_CFG1_MINSFT
;
15257 snprintf(&tp
->fw_ver
[0], 32, "sb v%d.%02d", major
, minor
);
15260 static void tg3_read_sb_ver(struct tg3
*tp
, u32 val
)
15262 u32 offset
, major
, minor
, build
;
15264 strncat(tp
->fw_ver
, "sb", TG3_VER_SIZE
- strlen(tp
->fw_ver
) - 1);
15266 if ((val
& TG3_EEPROM_SB_FORMAT_MASK
) != TG3_EEPROM_SB_FORMAT_1
)
15269 switch (val
& TG3_EEPROM_SB_REVISION_MASK
) {
15270 case TG3_EEPROM_SB_REVISION_0
:
15271 offset
= TG3_EEPROM_SB_F1R0_EDH_OFF
;
15273 case TG3_EEPROM_SB_REVISION_2
:
15274 offset
= TG3_EEPROM_SB_F1R2_EDH_OFF
;
15276 case TG3_EEPROM_SB_REVISION_3
:
15277 offset
= TG3_EEPROM_SB_F1R3_EDH_OFF
;
15279 case TG3_EEPROM_SB_REVISION_4
:
15280 offset
= TG3_EEPROM_SB_F1R4_EDH_OFF
;
15282 case TG3_EEPROM_SB_REVISION_5
:
15283 offset
= TG3_EEPROM_SB_F1R5_EDH_OFF
;
15285 case TG3_EEPROM_SB_REVISION_6
:
15286 offset
= TG3_EEPROM_SB_F1R6_EDH_OFF
;
15292 if (tg3_nvram_read(tp
, offset
, &val
))
15295 build
= (val
& TG3_EEPROM_SB_EDH_BLD_MASK
) >>
15296 TG3_EEPROM_SB_EDH_BLD_SHFT
;
15297 major
= (val
& TG3_EEPROM_SB_EDH_MAJ_MASK
) >>
15298 TG3_EEPROM_SB_EDH_MAJ_SHFT
;
15299 minor
= val
& TG3_EEPROM_SB_EDH_MIN_MASK
;
15301 if (minor
> 99 || build
> 26)
15304 offset
= strlen(tp
->fw_ver
);
15305 snprintf(&tp
->fw_ver
[offset
], TG3_VER_SIZE
- offset
,
15306 " v%d.%02d", major
, minor
);
15309 offset
= strlen(tp
->fw_ver
);
15310 if (offset
< TG3_VER_SIZE
- 1)
15311 tp
->fw_ver
[offset
] = 'a' + build
- 1;
15315 static void tg3_read_mgmtfw_ver(struct tg3
*tp
)
15317 u32 val
, offset
, start
;
15320 for (offset
= TG3_NVM_DIR_START
;
15321 offset
< TG3_NVM_DIR_END
;
15322 offset
+= TG3_NVM_DIRENT_SIZE
) {
15323 if (tg3_nvram_read(tp
, offset
, &val
))
15326 if ((val
>> TG3_NVM_DIRTYPE_SHIFT
) == TG3_NVM_DIRTYPE_ASFINI
)
15330 if (offset
== TG3_NVM_DIR_END
)
15333 if (!tg3_flag(tp
, 5705_PLUS
))
15334 start
= 0x08000000;
15335 else if (tg3_nvram_read(tp
, offset
- 4, &start
))
15338 if (tg3_nvram_read(tp
, offset
+ 4, &offset
) ||
15339 !tg3_fw_img_is_valid(tp
, offset
) ||
15340 tg3_nvram_read(tp
, offset
+ 8, &val
))
15343 offset
+= val
- start
;
15345 vlen
= strlen(tp
->fw_ver
);
15347 tp
->fw_ver
[vlen
++] = ',';
15348 tp
->fw_ver
[vlen
++] = ' ';
15350 for (i
= 0; i
< 4; i
++) {
15352 if (tg3_nvram_read_be32(tp
, offset
, &v
))
15355 offset
+= sizeof(v
);
15357 if (vlen
> TG3_VER_SIZE
- sizeof(v
)) {
15358 memcpy(&tp
->fw_ver
[vlen
], &v
, TG3_VER_SIZE
- vlen
);
15362 memcpy(&tp
->fw_ver
[vlen
], &v
, sizeof(v
));
15367 static void tg3_probe_ncsi(struct tg3
*tp
)
15371 apedata
= tg3_ape_read32(tp
, TG3_APE_SEG_SIG
);
15372 if (apedata
!= APE_SEG_SIG_MAGIC
)
15375 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_STATUS
);
15376 if (!(apedata
& APE_FW_STATUS_READY
))
15379 if (tg3_ape_read32(tp
, TG3_APE_FW_FEATURES
) & TG3_APE_FW_FEATURE_NCSI
)
15380 tg3_flag_set(tp
, APE_HAS_NCSI
);
15383 static void tg3_read_dash_ver(struct tg3
*tp
)
15389 apedata
= tg3_ape_read32(tp
, TG3_APE_FW_VERSION
);
15391 if (tg3_flag(tp
, APE_HAS_NCSI
))
15393 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5725
)
15398 vlen
= strlen(tp
->fw_ver
);
15400 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " %s v%d.%d.%d.%d",
15402 (apedata
& APE_FW_VERSION_MAJMSK
) >> APE_FW_VERSION_MAJSFT
,
15403 (apedata
& APE_FW_VERSION_MINMSK
) >> APE_FW_VERSION_MINSFT
,
15404 (apedata
& APE_FW_VERSION_REVMSK
) >> APE_FW_VERSION_REVSFT
,
15405 (apedata
& APE_FW_VERSION_BLDMSK
));
15408 static void tg3_read_otp_ver(struct tg3
*tp
)
15412 if (tg3_asic_rev(tp
) != ASIC_REV_5762
)
15415 if (!tg3_ape_otp_read(tp
, OTP_ADDRESS_MAGIC0
, &val
) &&
15416 !tg3_ape_otp_read(tp
, OTP_ADDRESS_MAGIC0
+ 4, &val2
) &&
15417 TG3_OTP_MAGIC0_VALID(val
)) {
15418 u64 val64
= (u64
) val
<< 32 | val2
;
15422 for (i
= 0; i
< 7; i
++) {
15423 if ((val64
& 0xff) == 0)
15425 ver
= val64
& 0xff;
15428 vlen
= strlen(tp
->fw_ver
);
15429 snprintf(&tp
->fw_ver
[vlen
], TG3_VER_SIZE
- vlen
, " .%02d", ver
);
15433 static void tg3_read_fw_ver(struct tg3
*tp
)
15436 bool vpd_vers
= false;
15438 if (tp
->fw_ver
[0] != 0)
15441 if (tg3_flag(tp
, NO_NVRAM
)) {
15442 strcat(tp
->fw_ver
, "sb");
15443 tg3_read_otp_ver(tp
);
15447 if (tg3_nvram_read(tp
, 0, &val
))
15450 if (val
== TG3_EEPROM_MAGIC
)
15451 tg3_read_bc_ver(tp
);
15452 else if ((val
& TG3_EEPROM_MAGIC_FW_MSK
) == TG3_EEPROM_MAGIC_FW
)
15453 tg3_read_sb_ver(tp
, val
);
15454 else if ((val
& TG3_EEPROM_MAGIC_HW_MSK
) == TG3_EEPROM_MAGIC_HW
)
15455 tg3_read_hwsb_ver(tp
);
15457 if (tg3_flag(tp
, ENABLE_ASF
)) {
15458 if (tg3_flag(tp
, ENABLE_APE
)) {
15459 tg3_probe_ncsi(tp
);
15461 tg3_read_dash_ver(tp
);
15462 } else if (!vpd_vers
) {
15463 tg3_read_mgmtfw_ver(tp
);
15467 tp
->fw_ver
[TG3_VER_SIZE
- 1] = 0;
15470 static inline u32
tg3_rx_ret_ring_size(struct tg3
*tp
)
15472 if (tg3_flag(tp
, LRG_PROD_RING_CAP
))
15473 return TG3_RX_RET_MAX_SIZE_5717
;
15474 else if (tg3_flag(tp
, JUMBO_CAPABLE
) && !tg3_flag(tp
, 5780_CLASS
))
15475 return TG3_RX_RET_MAX_SIZE_5700
;
15477 return TG3_RX_RET_MAX_SIZE_5705
;
15480 static DEFINE_PCI_DEVICE_TABLE(tg3_write_reorder_chipsets
) = {
15481 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_FE_GATE_700C
) },
15482 { PCI_DEVICE(PCI_VENDOR_ID_AMD
, PCI_DEVICE_ID_AMD_8131_BRIDGE
) },
15483 { PCI_DEVICE(PCI_VENDOR_ID_VIA
, PCI_DEVICE_ID_VIA_8385_0
) },
15487 static struct pci_dev
*tg3_find_peer(struct tg3
*tp
)
15489 struct pci_dev
*peer
;
15490 unsigned int func
, devnr
= tp
->pdev
->devfn
& ~7;
15492 for (func
= 0; func
< 8; func
++) {
15493 peer
= pci_get_slot(tp
->pdev
->bus
, devnr
| func
);
15494 if (peer
&& peer
!= tp
->pdev
)
15498 /* 5704 can be configured in single-port mode, set peer to
15499 * tp->pdev in that case.
15507 * We don't need to keep the refcount elevated; there's no way
15508 * to remove one half of this device without removing the other
15515 static void tg3_detect_asic_rev(struct tg3
*tp
, u32 misc_ctrl_reg
)
15517 tp
->pci_chip_rev_id
= misc_ctrl_reg
>> MISC_HOST_CTRL_CHIPREV_SHIFT
;
15518 if (tg3_asic_rev(tp
) == ASIC_REV_USE_PROD_ID_REG
) {
15521 /* All devices that use the alternate
15522 * ASIC REV location have a CPMU.
15524 tg3_flag_set(tp
, CPMU_PRESENT
);
15526 if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
15527 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717_C
||
15528 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
15529 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
||
15530 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5720
||
15531 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5762
||
15532 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5725
||
15533 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5727
)
15534 reg
= TG3PCI_GEN2_PRODID_ASICREV
;
15535 else if (tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57781
||
15536 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57785
||
15537 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57761
||
15538 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57765
||
15539 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57791
||
15540 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57795
||
15541 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57762
||
15542 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57766
||
15543 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57782
||
15544 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_57786
)
15545 reg
= TG3PCI_GEN15_PRODID_ASICREV
;
15547 reg
= TG3PCI_PRODID_ASICREV
;
15549 pci_read_config_dword(tp
->pdev
, reg
, &tp
->pci_chip_rev_id
);
15552 /* Wrong chip ID in 5752 A0. This code can be removed later
15553 * as A0 is not in production.
15555 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5752_A0_HW
)
15556 tp
->pci_chip_rev_id
= CHIPREV_ID_5752_A0
;
15558 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5717_C0
)
15559 tp
->pci_chip_rev_id
= CHIPREV_ID_5720_A0
;
15561 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
15562 tg3_asic_rev(tp
) == ASIC_REV_5719
||
15563 tg3_asic_rev(tp
) == ASIC_REV_5720
)
15564 tg3_flag_set(tp
, 5717_PLUS
);
15566 if (tg3_asic_rev(tp
) == ASIC_REV_57765
||
15567 tg3_asic_rev(tp
) == ASIC_REV_57766
)
15568 tg3_flag_set(tp
, 57765_CLASS
);
15570 if (tg3_flag(tp
, 57765_CLASS
) || tg3_flag(tp
, 5717_PLUS
) ||
15571 tg3_asic_rev(tp
) == ASIC_REV_5762
)
15572 tg3_flag_set(tp
, 57765_PLUS
);
15574 /* Intentionally exclude ASIC_REV_5906 */
15575 if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
15576 tg3_asic_rev(tp
) == ASIC_REV_5787
||
15577 tg3_asic_rev(tp
) == ASIC_REV_5784
||
15578 tg3_asic_rev(tp
) == ASIC_REV_5761
||
15579 tg3_asic_rev(tp
) == ASIC_REV_5785
||
15580 tg3_asic_rev(tp
) == ASIC_REV_57780
||
15581 tg3_flag(tp
, 57765_PLUS
))
15582 tg3_flag_set(tp
, 5755_PLUS
);
15584 if (tg3_asic_rev(tp
) == ASIC_REV_5780
||
15585 tg3_asic_rev(tp
) == ASIC_REV_5714
)
15586 tg3_flag_set(tp
, 5780_CLASS
);
15588 if (tg3_asic_rev(tp
) == ASIC_REV_5750
||
15589 tg3_asic_rev(tp
) == ASIC_REV_5752
||
15590 tg3_asic_rev(tp
) == ASIC_REV_5906
||
15591 tg3_flag(tp
, 5755_PLUS
) ||
15592 tg3_flag(tp
, 5780_CLASS
))
15593 tg3_flag_set(tp
, 5750_PLUS
);
15595 if (tg3_asic_rev(tp
) == ASIC_REV_5705
||
15596 tg3_flag(tp
, 5750_PLUS
))
15597 tg3_flag_set(tp
, 5705_PLUS
);
15600 static bool tg3_10_100_only_device(struct tg3
*tp
,
15601 const struct pci_device_id
*ent
)
15603 u32 grc_misc_cfg
= tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
;
15605 if ((tg3_asic_rev(tp
) == ASIC_REV_5703
&&
15606 (grc_misc_cfg
== 0x8000 || grc_misc_cfg
== 0x4000)) ||
15607 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
))
15610 if (ent
->driver_data
& TG3_DRV_DATA_FLAG_10_100_ONLY
) {
15611 if (tg3_asic_rev(tp
) == ASIC_REV_5705
) {
15612 if (ent
->driver_data
& TG3_DRV_DATA_FLAG_5705_10_100
)
15622 static int tg3_get_invariants(struct tg3
*tp
, const struct pci_device_id
*ent
)
15625 u32 pci_state_reg
, grc_misc_cfg
;
15630 /* Force memory write invalidate off. If we leave it on,
15631 * then on 5700_BX chips we have to enable a workaround.
15632 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
15633 * to match the cacheline size. The Broadcom driver have this
15634 * workaround but turns MWI off all the times so never uses
15635 * it. This seems to suggest that the workaround is insufficient.
15637 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
15638 pci_cmd
&= ~PCI_COMMAND_INVALIDATE
;
15639 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
15641 /* Important! -- Make sure register accesses are byteswapped
15642 * correctly. Also, for those chips that require it, make
15643 * sure that indirect register accesses are enabled before
15644 * the first operation.
15646 pci_read_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
15648 tp
->misc_host_ctrl
|= (misc_ctrl_reg
&
15649 MISC_HOST_CTRL_CHIPREV
);
15650 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
15651 tp
->misc_host_ctrl
);
15653 tg3_detect_asic_rev(tp
, misc_ctrl_reg
);
15655 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
15656 * we need to disable memory and use config. cycles
15657 * only to access all registers. The 5702/03 chips
15658 * can mistakenly decode the special cycles from the
15659 * ICH chipsets as memory write cycles, causing corruption
15660 * of register and memory space. Only certain ICH bridges
15661 * will drive special cycles with non-zero data during the
15662 * address phase which can fall within the 5703's address
15663 * range. This is not an ICH bug as the PCI spec allows
15664 * non-zero address during special cycles. However, only
15665 * these ICH bridges are known to drive non-zero addresses
15666 * during special cycles.
15668 * Since special cycles do not cross PCI bridges, we only
15669 * enable this workaround if the 5703 is on the secondary
15670 * bus of these ICH bridges.
15672 if ((tg3_chip_rev_id(tp
) == CHIPREV_ID_5703_A1
) ||
15673 (tg3_chip_rev_id(tp
) == CHIPREV_ID_5703_A2
)) {
15674 static struct tg3_dev_id
{
15678 } ich_chipsets
[] = {
15679 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AA_8
,
15681 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801AB_8
,
15683 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_11
,
15685 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_82801BA_6
,
15689 struct tg3_dev_id
*pci_id
= &ich_chipsets
[0];
15690 struct pci_dev
*bridge
= NULL
;
15692 while (pci_id
->vendor
!= 0) {
15693 bridge
= pci_get_device(pci_id
->vendor
, pci_id
->device
,
15699 if (pci_id
->rev
!= PCI_ANY_ID
) {
15700 if (bridge
->revision
> pci_id
->rev
)
15703 if (bridge
->subordinate
&&
15704 (bridge
->subordinate
->number
==
15705 tp
->pdev
->bus
->number
)) {
15706 tg3_flag_set(tp
, ICH_WORKAROUND
);
15707 pci_dev_put(bridge
);
15713 if (tg3_asic_rev(tp
) == ASIC_REV_5701
) {
15714 static struct tg3_dev_id
{
15717 } bridge_chipsets
[] = {
15718 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_0
},
15719 { PCI_VENDOR_ID_INTEL
, PCI_DEVICE_ID_INTEL_PXH_1
},
15722 struct tg3_dev_id
*pci_id
= &bridge_chipsets
[0];
15723 struct pci_dev
*bridge
= NULL
;
15725 while (pci_id
->vendor
!= 0) {
15726 bridge
= pci_get_device(pci_id
->vendor
,
15733 if (bridge
->subordinate
&&
15734 (bridge
->subordinate
->number
<=
15735 tp
->pdev
->bus
->number
) &&
15736 (bridge
->subordinate
->busn_res
.end
>=
15737 tp
->pdev
->bus
->number
)) {
15738 tg3_flag_set(tp
, 5701_DMA_BUG
);
15739 pci_dev_put(bridge
);
15745 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
15746 * DMA addresses > 40-bit. This bridge may have other additional
15747 * 57xx devices behind it in some 4-port NIC designs for example.
15748 * Any tg3 device found behind the bridge will also need the 40-bit
15751 if (tg3_flag(tp
, 5780_CLASS
)) {
15752 tg3_flag_set(tp
, 40BIT_DMA_BUG
);
15753 tp
->msi_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_MSI
);
15755 struct pci_dev
*bridge
= NULL
;
15758 bridge
= pci_get_device(PCI_VENDOR_ID_SERVERWORKS
,
15759 PCI_DEVICE_ID_SERVERWORKS_EPB
,
15761 if (bridge
&& bridge
->subordinate
&&
15762 (bridge
->subordinate
->number
<=
15763 tp
->pdev
->bus
->number
) &&
15764 (bridge
->subordinate
->busn_res
.end
>=
15765 tp
->pdev
->bus
->number
)) {
15766 tg3_flag_set(tp
, 40BIT_DMA_BUG
);
15767 pci_dev_put(bridge
);
15773 if (tg3_asic_rev(tp
) == ASIC_REV_5704
||
15774 tg3_asic_rev(tp
) == ASIC_REV_5714
)
15775 tp
->pdev_peer
= tg3_find_peer(tp
);
15777 /* Determine TSO capabilities */
15778 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
)
15779 ; /* Do nothing. HW bug. */
15780 else if (tg3_flag(tp
, 57765_PLUS
))
15781 tg3_flag_set(tp
, HW_TSO_3
);
15782 else if (tg3_flag(tp
, 5755_PLUS
) ||
15783 tg3_asic_rev(tp
) == ASIC_REV_5906
)
15784 tg3_flag_set(tp
, HW_TSO_2
);
15785 else if (tg3_flag(tp
, 5750_PLUS
)) {
15786 tg3_flag_set(tp
, HW_TSO_1
);
15787 tg3_flag_set(tp
, TSO_BUG
);
15788 if (tg3_asic_rev(tp
) == ASIC_REV_5750
&&
15789 tg3_chip_rev_id(tp
) >= CHIPREV_ID_5750_C2
)
15790 tg3_flag_clear(tp
, TSO_BUG
);
15791 } else if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
15792 tg3_asic_rev(tp
) != ASIC_REV_5701
&&
15793 tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A0
) {
15794 tg3_flag_set(tp
, FW_TSO
);
15795 tg3_flag_set(tp
, TSO_BUG
);
15796 if (tg3_asic_rev(tp
) == ASIC_REV_5705
)
15797 tp
->fw_needed
= FIRMWARE_TG3TSO5
;
15799 tp
->fw_needed
= FIRMWARE_TG3TSO
;
15802 /* Selectively allow TSO based on operating conditions */
15803 if (tg3_flag(tp
, HW_TSO_1
) ||
15804 tg3_flag(tp
, HW_TSO_2
) ||
15805 tg3_flag(tp
, HW_TSO_3
) ||
15806 tg3_flag(tp
, FW_TSO
)) {
15807 /* For firmware TSO, assume ASF is disabled.
15808 * We'll disable TSO later if we discover ASF
15809 * is enabled in tg3_get_eeprom_hw_cfg().
15811 tg3_flag_set(tp
, TSO_CAPABLE
);
15813 tg3_flag_clear(tp
, TSO_CAPABLE
);
15814 tg3_flag_clear(tp
, TSO_BUG
);
15815 tp
->fw_needed
= NULL
;
15818 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
)
15819 tp
->fw_needed
= FIRMWARE_TG3
;
15821 if (tg3_asic_rev(tp
) == ASIC_REV_57766
)
15822 tp
->fw_needed
= FIRMWARE_TG357766
;
15826 if (tg3_flag(tp
, 5750_PLUS
)) {
15827 tg3_flag_set(tp
, SUPPORT_MSI
);
15828 if (tg3_chip_rev(tp
) == CHIPREV_5750_AX
||
15829 tg3_chip_rev(tp
) == CHIPREV_5750_BX
||
15830 (tg3_asic_rev(tp
) == ASIC_REV_5714
&&
15831 tg3_chip_rev_id(tp
) <= CHIPREV_ID_5714_A2
&&
15832 tp
->pdev_peer
== tp
->pdev
))
15833 tg3_flag_clear(tp
, SUPPORT_MSI
);
15835 if (tg3_flag(tp
, 5755_PLUS
) ||
15836 tg3_asic_rev(tp
) == ASIC_REV_5906
) {
15837 tg3_flag_set(tp
, 1SHOT_MSI
);
15840 if (tg3_flag(tp
, 57765_PLUS
)) {
15841 tg3_flag_set(tp
, SUPPORT_MSIX
);
15842 tp
->irq_max
= TG3_IRQ_MAX_VECS
;
15848 if (tp
->irq_max
> 1) {
15849 tp
->rxq_max
= TG3_RSS_MAX_NUM_QS
;
15850 tg3_rss_init_dflt_indir_tbl(tp
, TG3_RSS_MAX_NUM_QS
);
15852 if (tg3_asic_rev(tp
) == ASIC_REV_5719
||
15853 tg3_asic_rev(tp
) == ASIC_REV_5720
)
15854 tp
->txq_max
= tp
->irq_max
- 1;
15857 if (tg3_flag(tp
, 5755_PLUS
) ||
15858 tg3_asic_rev(tp
) == ASIC_REV_5906
)
15859 tg3_flag_set(tp
, SHORT_DMA_BUG
);
15861 if (tg3_asic_rev(tp
) == ASIC_REV_5719
)
15862 tp
->dma_limit
= TG3_TX_BD_DMA_MAX_4K
;
15864 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
15865 tg3_asic_rev(tp
) == ASIC_REV_5719
||
15866 tg3_asic_rev(tp
) == ASIC_REV_5720
||
15867 tg3_asic_rev(tp
) == ASIC_REV_5762
)
15868 tg3_flag_set(tp
, LRG_PROD_RING_CAP
);
15870 if (tg3_flag(tp
, 57765_PLUS
) &&
15871 tg3_chip_rev_id(tp
) != CHIPREV_ID_5719_A0
)
15872 tg3_flag_set(tp
, USE_JUMBO_BDFLAG
);
15874 if (!tg3_flag(tp
, 5705_PLUS
) ||
15875 tg3_flag(tp
, 5780_CLASS
) ||
15876 tg3_flag(tp
, USE_JUMBO_BDFLAG
))
15877 tg3_flag_set(tp
, JUMBO_CAPABLE
);
15879 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
15882 if (pci_is_pcie(tp
->pdev
)) {
15885 tg3_flag_set(tp
, PCI_EXPRESS
);
15887 pcie_capability_read_word(tp
->pdev
, PCI_EXP_LNKCTL
, &lnkctl
);
15888 if (lnkctl
& PCI_EXP_LNKCTL_CLKREQ_EN
) {
15889 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
15890 tg3_flag_clear(tp
, HW_TSO_2
);
15891 tg3_flag_clear(tp
, TSO_CAPABLE
);
15893 if (tg3_asic_rev(tp
) == ASIC_REV_5784
||
15894 tg3_asic_rev(tp
) == ASIC_REV_5761
||
15895 tg3_chip_rev_id(tp
) == CHIPREV_ID_57780_A0
||
15896 tg3_chip_rev_id(tp
) == CHIPREV_ID_57780_A1
)
15897 tg3_flag_set(tp
, CLKREQ_BUG
);
15898 } else if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5717_A0
) {
15899 tg3_flag_set(tp
, L1PLLPD_EN
);
15901 } else if (tg3_asic_rev(tp
) == ASIC_REV_5785
) {
15902 /* BCM5785 devices are effectively PCIe devices, and should
15903 * follow PCIe codepaths, but do not have a PCIe capabilities
15906 tg3_flag_set(tp
, PCI_EXPRESS
);
15907 } else if (!tg3_flag(tp
, 5705_PLUS
) ||
15908 tg3_flag(tp
, 5780_CLASS
)) {
15909 tp
->pcix_cap
= pci_find_capability(tp
->pdev
, PCI_CAP_ID_PCIX
);
15910 if (!tp
->pcix_cap
) {
15911 dev_err(&tp
->pdev
->dev
,
15912 "Cannot find PCI-X capability, aborting\n");
15916 if (!(pci_state_reg
& PCISTATE_CONV_PCI_MODE
))
15917 tg3_flag_set(tp
, PCIX_MODE
);
15920 /* If we have an AMD 762 or VIA K8T800 chipset, write
15921 * reordering to the mailbox registers done by the host
15922 * controller can cause major troubles. We read back from
15923 * every mailbox register write to force the writes to be
15924 * posted to the chip in order.
15926 if (pci_dev_present(tg3_write_reorder_chipsets
) &&
15927 !tg3_flag(tp
, PCI_EXPRESS
))
15928 tg3_flag_set(tp
, MBOX_WRITE_REORDER
);
15930 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
,
15931 &tp
->pci_cacheline_sz
);
15932 pci_read_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
15933 &tp
->pci_lat_timer
);
15934 if (tg3_asic_rev(tp
) == ASIC_REV_5703
&&
15935 tp
->pci_lat_timer
< 64) {
15936 tp
->pci_lat_timer
= 64;
15937 pci_write_config_byte(tp
->pdev
, PCI_LATENCY_TIMER
,
15938 tp
->pci_lat_timer
);
15941 /* Important! -- It is critical that the PCI-X hw workaround
15942 * situation is decided before the first MMIO register access.
15944 if (tg3_chip_rev(tp
) == CHIPREV_5700_BX
) {
15945 /* 5700 BX chips need to have their TX producer index
15946 * mailboxes written twice to workaround a bug.
15948 tg3_flag_set(tp
, TXD_MBOX_HWBUG
);
15950 /* If we are in PCI-X mode, enable register write workaround.
15952 * The workaround is to use indirect register accesses
15953 * for all chip writes not to mailbox registers.
15955 if (tg3_flag(tp
, PCIX_MODE
)) {
15958 tg3_flag_set(tp
, PCIX_TARGET_HWBUG
);
15960 /* The chip can have it's power management PCI config
15961 * space registers clobbered due to this bug.
15962 * So explicitly force the chip into D0 here.
15964 pci_read_config_dword(tp
->pdev
,
15965 tp
->pm_cap
+ PCI_PM_CTRL
,
15967 pm_reg
&= ~PCI_PM_CTRL_STATE_MASK
;
15968 pm_reg
|= PCI_PM_CTRL_PME_ENABLE
| 0 /* D0 */;
15969 pci_write_config_dword(tp
->pdev
,
15970 tp
->pm_cap
+ PCI_PM_CTRL
,
15973 /* Also, force SERR#/PERR# in PCI command. */
15974 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
15975 pci_cmd
|= PCI_COMMAND_PARITY
| PCI_COMMAND_SERR
;
15976 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
15980 if ((pci_state_reg
& PCISTATE_BUS_SPEED_HIGH
) != 0)
15981 tg3_flag_set(tp
, PCI_HIGH_SPEED
);
15982 if ((pci_state_reg
& PCISTATE_BUS_32BIT
) != 0)
15983 tg3_flag_set(tp
, PCI_32BIT
);
15985 /* Chip-specific fixup from Broadcom driver */
15986 if ((tg3_chip_rev_id(tp
) == CHIPREV_ID_5704_A0
) &&
15987 (!(pci_state_reg
& PCISTATE_RETRY_SAME_DMA
))) {
15988 pci_state_reg
|= PCISTATE_RETRY_SAME_DMA
;
15989 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
, pci_state_reg
);
15992 /* Default fast path register access methods */
15993 tp
->read32
= tg3_read32
;
15994 tp
->write32
= tg3_write32
;
15995 tp
->read32_mbox
= tg3_read32
;
15996 tp
->write32_mbox
= tg3_write32
;
15997 tp
->write32_tx_mbox
= tg3_write32
;
15998 tp
->write32_rx_mbox
= tg3_write32
;
16000 /* Various workaround register access methods */
16001 if (tg3_flag(tp
, PCIX_TARGET_HWBUG
))
16002 tp
->write32
= tg3_write_indirect_reg32
;
16003 else if (tg3_asic_rev(tp
) == ASIC_REV_5701
||
16004 (tg3_flag(tp
, PCI_EXPRESS
) &&
16005 tg3_chip_rev_id(tp
) == CHIPREV_ID_5750_A0
)) {
16007 * Back to back register writes can cause problems on these
16008 * chips, the workaround is to read back all reg writes
16009 * except those to mailbox regs.
16011 * See tg3_write_indirect_reg32().
16013 tp
->write32
= tg3_write_flush_reg32
;
16016 if (tg3_flag(tp
, TXD_MBOX_HWBUG
) || tg3_flag(tp
, MBOX_WRITE_REORDER
)) {
16017 tp
->write32_tx_mbox
= tg3_write32_tx_mbox
;
16018 if (tg3_flag(tp
, MBOX_WRITE_REORDER
))
16019 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
16022 if (tg3_flag(tp
, ICH_WORKAROUND
)) {
16023 tp
->read32
= tg3_read_indirect_reg32
;
16024 tp
->write32
= tg3_write_indirect_reg32
;
16025 tp
->read32_mbox
= tg3_read_indirect_mbox
;
16026 tp
->write32_mbox
= tg3_write_indirect_mbox
;
16027 tp
->write32_tx_mbox
= tg3_write_indirect_mbox
;
16028 tp
->write32_rx_mbox
= tg3_write_indirect_mbox
;
16033 pci_read_config_word(tp
->pdev
, PCI_COMMAND
, &pci_cmd
);
16034 pci_cmd
&= ~PCI_COMMAND_MEMORY
;
16035 pci_write_config_word(tp
->pdev
, PCI_COMMAND
, pci_cmd
);
16037 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
16038 tp
->read32_mbox
= tg3_read32_mbox_5906
;
16039 tp
->write32_mbox
= tg3_write32_mbox_5906
;
16040 tp
->write32_tx_mbox
= tg3_write32_mbox_5906
;
16041 tp
->write32_rx_mbox
= tg3_write32_mbox_5906
;
16044 if (tp
->write32
== tg3_write_indirect_reg32
||
16045 (tg3_flag(tp
, PCIX_MODE
) &&
16046 (tg3_asic_rev(tp
) == ASIC_REV_5700
||
16047 tg3_asic_rev(tp
) == ASIC_REV_5701
)))
16048 tg3_flag_set(tp
, SRAM_USE_CONFIG
);
16050 /* The memory arbiter has to be enabled in order for SRAM accesses
16051 * to succeed. Normally on powerup the tg3 chip firmware will make
16052 * sure it is enabled, but other entities such as system netboot
16053 * code might disable it.
16055 val
= tr32(MEMARB_MODE
);
16056 tw32(MEMARB_MODE
, val
| MEMARB_MODE_ENABLE
);
16058 tp
->pci_fn
= PCI_FUNC(tp
->pdev
->devfn
) & 3;
16059 if (tg3_asic_rev(tp
) == ASIC_REV_5704
||
16060 tg3_flag(tp
, 5780_CLASS
)) {
16061 if (tg3_flag(tp
, PCIX_MODE
)) {
16062 pci_read_config_dword(tp
->pdev
,
16063 tp
->pcix_cap
+ PCI_X_STATUS
,
16065 tp
->pci_fn
= val
& 0x7;
16067 } else if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
16068 tg3_asic_rev(tp
) == ASIC_REV_5719
||
16069 tg3_asic_rev(tp
) == ASIC_REV_5720
) {
16070 tg3_read_mem(tp
, NIC_SRAM_CPMU_STATUS
, &val
);
16071 if ((val
& NIC_SRAM_CPMUSTAT_SIG_MSK
) != NIC_SRAM_CPMUSTAT_SIG
)
16072 val
= tr32(TG3_CPMU_STATUS
);
16074 if (tg3_asic_rev(tp
) == ASIC_REV_5717
)
16075 tp
->pci_fn
= (val
& TG3_CPMU_STATUS_FMSK_5717
) ? 1 : 0;
16077 tp
->pci_fn
= (val
& TG3_CPMU_STATUS_FMSK_5719
) >>
16078 TG3_CPMU_STATUS_FSHFT_5719
;
16081 if (tg3_flag(tp
, FLUSH_POSTED_WRITES
)) {
16082 tp
->write32_tx_mbox
= tg3_write_flush_reg32
;
16083 tp
->write32_rx_mbox
= tg3_write_flush_reg32
;
16086 /* Get eeprom hw config before calling tg3_set_power_state().
16087 * In particular, the TG3_FLAG_IS_NIC flag must be
16088 * determined before calling tg3_set_power_state() so that
16089 * we know whether or not to switch out of Vaux power.
16090 * When the flag is set, it means that GPIO1 is used for eeprom
16091 * write protect and also implies that it is a LOM where GPIOs
16092 * are not used to switch power.
16094 tg3_get_eeprom_hw_cfg(tp
);
16096 if (tg3_flag(tp
, FW_TSO
) && tg3_flag(tp
, ENABLE_ASF
)) {
16097 tg3_flag_clear(tp
, TSO_CAPABLE
);
16098 tg3_flag_clear(tp
, TSO_BUG
);
16099 tp
->fw_needed
= NULL
;
16102 if (tg3_flag(tp
, ENABLE_APE
)) {
16103 /* Allow reads and writes to the
16104 * APE register and memory space.
16106 pci_state_reg
|= PCISTATE_ALLOW_APE_CTLSPC_WR
|
16107 PCISTATE_ALLOW_APE_SHMEM_WR
|
16108 PCISTATE_ALLOW_APE_PSPACE_WR
;
16109 pci_write_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
16112 tg3_ape_lock_init(tp
);
16115 /* Set up tp->grc_local_ctrl before calling
16116 * tg3_pwrsrc_switch_to_vmain(). GPIO1 driven high
16117 * will bring 5700's external PHY out of reset.
16118 * It is also used as eeprom write protect on LOMs.
16120 tp
->grc_local_ctrl
= GRC_LCLCTRL_INT_ON_ATTN
| GRC_LCLCTRL_AUTO_SEEPROM
;
16121 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
16122 tg3_flag(tp
, EEPROM_WRITE_PROT
))
16123 tp
->grc_local_ctrl
|= (GRC_LCLCTRL_GPIO_OE1
|
16124 GRC_LCLCTRL_GPIO_OUTPUT1
);
16125 /* Unused GPIO3 must be driven as output on 5752 because there
16126 * are no pull-up resistors on unused GPIO pins.
16128 else if (tg3_asic_rev(tp
) == ASIC_REV_5752
)
16129 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE3
;
16131 if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
16132 tg3_asic_rev(tp
) == ASIC_REV_57780
||
16133 tg3_flag(tp
, 57765_CLASS
))
16134 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
16136 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
16137 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
) {
16138 /* Turn off the debug UART. */
16139 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_UART_SEL
;
16140 if (tg3_flag(tp
, IS_NIC
))
16141 /* Keep VMain power. */
16142 tp
->grc_local_ctrl
|= GRC_LCLCTRL_GPIO_OE0
|
16143 GRC_LCLCTRL_GPIO_OUTPUT0
;
16146 if (tg3_asic_rev(tp
) == ASIC_REV_5762
)
16147 tp
->grc_local_ctrl
|=
16148 tr32(GRC_LOCAL_CTRL
) & GRC_LCLCTRL_GPIO_UART_SEL
;
16150 /* Switch out of Vaux if it is a NIC */
16151 tg3_pwrsrc_switch_to_vmain(tp
);
16153 /* Derive initial jumbo mode from MTU assigned in
16154 * ether_setup() via the alloc_etherdev() call
16156 if (tp
->dev
->mtu
> ETH_DATA_LEN
&& !tg3_flag(tp
, 5780_CLASS
))
16157 tg3_flag_set(tp
, JUMBO_RING_ENABLE
);
16159 /* Determine WakeOnLan speed to use. */
16160 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
16161 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
16162 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
||
16163 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B2
) {
16164 tg3_flag_clear(tp
, WOL_SPEED_100MB
);
16166 tg3_flag_set(tp
, WOL_SPEED_100MB
);
16169 if (tg3_asic_rev(tp
) == ASIC_REV_5906
)
16170 tp
->phy_flags
|= TG3_PHYFLG_IS_FET
;
16172 /* A few boards don't want Ethernet@WireSpeed phy feature */
16173 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
16174 (tg3_asic_rev(tp
) == ASIC_REV_5705
&&
16175 (tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A0
) &&
16176 (tg3_chip_rev_id(tp
) != CHIPREV_ID_5705_A1
)) ||
16177 (tp
->phy_flags
& TG3_PHYFLG_IS_FET
) ||
16178 (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
))
16179 tp
->phy_flags
|= TG3_PHYFLG_NO_ETH_WIRE_SPEED
;
16181 if (tg3_chip_rev(tp
) == CHIPREV_5703_AX
||
16182 tg3_chip_rev(tp
) == CHIPREV_5704_AX
)
16183 tp
->phy_flags
|= TG3_PHYFLG_ADC_BUG
;
16184 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5704_A0
)
16185 tp
->phy_flags
|= TG3_PHYFLG_5704_A0_BUG
;
16187 if (tg3_flag(tp
, 5705_PLUS
) &&
16188 !(tp
->phy_flags
& TG3_PHYFLG_IS_FET
) &&
16189 tg3_asic_rev(tp
) != ASIC_REV_5785
&&
16190 tg3_asic_rev(tp
) != ASIC_REV_57780
&&
16191 !tg3_flag(tp
, 57765_PLUS
)) {
16192 if (tg3_asic_rev(tp
) == ASIC_REV_5755
||
16193 tg3_asic_rev(tp
) == ASIC_REV_5787
||
16194 tg3_asic_rev(tp
) == ASIC_REV_5784
||
16195 tg3_asic_rev(tp
) == ASIC_REV_5761
) {
16196 if (tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5756
&&
16197 tp
->pdev
->device
!= PCI_DEVICE_ID_TIGON3_5722
)
16198 tp
->phy_flags
|= TG3_PHYFLG_JITTER_BUG
;
16199 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5755M
)
16200 tp
->phy_flags
|= TG3_PHYFLG_ADJUST_TRIM
;
16202 tp
->phy_flags
|= TG3_PHYFLG_BER_BUG
;
16205 if (tg3_asic_rev(tp
) == ASIC_REV_5784
&&
16206 tg3_chip_rev(tp
) != CHIPREV_5784_AX
) {
16207 tp
->phy_otp
= tg3_read_otp_phycfg(tp
);
16208 if (tp
->phy_otp
== 0)
16209 tp
->phy_otp
= TG3_OTP_DEFAULT
;
16212 if (tg3_flag(tp
, CPMU_PRESENT
))
16213 tp
->mi_mode
= MAC_MI_MODE_500KHZ_CONST
;
16215 tp
->mi_mode
= MAC_MI_MODE_BASE
;
16217 tp
->coalesce_mode
= 0;
16218 if (tg3_chip_rev(tp
) != CHIPREV_5700_AX
&&
16219 tg3_chip_rev(tp
) != CHIPREV_5700_BX
)
16220 tp
->coalesce_mode
|= HOSTCC_MODE_32BYTE
;
16222 /* Set these bits to enable statistics workaround. */
16223 if (tg3_asic_rev(tp
) == ASIC_REV_5717
||
16224 tg3_chip_rev_id(tp
) == CHIPREV_ID_5719_A0
||
16225 tg3_chip_rev_id(tp
) == CHIPREV_ID_5720_A0
) {
16226 tp
->coalesce_mode
|= HOSTCC_MODE_ATTN
;
16227 tp
->grc_mode
|= GRC_MODE_IRQ_ON_FLOW_ATTN
;
16230 if (tg3_asic_rev(tp
) == ASIC_REV_5785
||
16231 tg3_asic_rev(tp
) == ASIC_REV_57780
)
16232 tg3_flag_set(tp
, USE_PHYLIB
);
16234 err
= tg3_mdio_init(tp
);
16238 /* Initialize data/descriptor byte/word swapping. */
16239 val
= tr32(GRC_MODE
);
16240 if (tg3_asic_rev(tp
) == ASIC_REV_5720
||
16241 tg3_asic_rev(tp
) == ASIC_REV_5762
)
16242 val
&= (GRC_MODE_BYTE_SWAP_B2HRX_DATA
|
16243 GRC_MODE_WORD_SWAP_B2HRX_DATA
|
16244 GRC_MODE_B2HRX_ENABLE
|
16245 GRC_MODE_HTX2B_ENABLE
|
16246 GRC_MODE_HOST_STACKUP
);
16248 val
&= GRC_MODE_HOST_STACKUP
;
16250 tw32(GRC_MODE
, val
| tp
->grc_mode
);
16252 tg3_switch_clocks(tp
);
16254 /* Clear this out for sanity. */
16255 tw32(TG3PCI_MEM_WIN_BASE_ADDR
, 0);
16257 pci_read_config_dword(tp
->pdev
, TG3PCI_PCISTATE
,
16259 if ((pci_state_reg
& PCISTATE_CONV_PCI_MODE
) == 0 &&
16260 !tg3_flag(tp
, PCIX_TARGET_HWBUG
)) {
16261 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_A0
||
16262 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B0
||
16263 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B2
||
16264 tg3_chip_rev_id(tp
) == CHIPREV_ID_5701_B5
) {
16265 void __iomem
*sram_base
;
16267 /* Write some dummy words into the SRAM status block
16268 * area, see if it reads back correctly. If the return
16269 * value is bad, force enable the PCIX workaround.
16271 sram_base
= tp
->regs
+ NIC_SRAM_WIN_BASE
+ NIC_SRAM_STATS_BLK
;
16273 writel(0x00000000, sram_base
);
16274 writel(0x00000000, sram_base
+ 4);
16275 writel(0xffffffff, sram_base
+ 4);
16276 if (readl(sram_base
) != 0x00000000)
16277 tg3_flag_set(tp
, PCIX_TARGET_HWBUG
);
16282 tg3_nvram_init(tp
);
16284 /* If the device has an NVRAM, no need to load patch firmware */
16285 if (tg3_asic_rev(tp
) == ASIC_REV_57766
&&
16286 !tg3_flag(tp
, NO_NVRAM
))
16287 tp
->fw_needed
= NULL
;
16289 grc_misc_cfg
= tr32(GRC_MISC_CFG
);
16290 grc_misc_cfg
&= GRC_MISC_CFG_BOARD_ID_MASK
;
16292 if (tg3_asic_rev(tp
) == ASIC_REV_5705
&&
16293 (grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788
||
16294 grc_misc_cfg
== GRC_MISC_CFG_BOARD_ID_5788M
))
16295 tg3_flag_set(tp
, IS_5788
);
16297 if (!tg3_flag(tp
, IS_5788
) &&
16298 tg3_asic_rev(tp
) != ASIC_REV_5700
)
16299 tg3_flag_set(tp
, TAGGED_STATUS
);
16300 if (tg3_flag(tp
, TAGGED_STATUS
)) {
16301 tp
->coalesce_mode
|= (HOSTCC_MODE_CLRTICK_RXBD
|
16302 HOSTCC_MODE_CLRTICK_TXBD
);
16304 tp
->misc_host_ctrl
|= MISC_HOST_CTRL_TAGGED_STATUS
;
16305 pci_write_config_dword(tp
->pdev
, TG3PCI_MISC_HOST_CTRL
,
16306 tp
->misc_host_ctrl
);
16309 /* Preserve the APE MAC_MODE bits */
16310 if (tg3_flag(tp
, ENABLE_APE
))
16311 tp
->mac_mode
= MAC_MODE_APE_TX_EN
| MAC_MODE_APE_RX_EN
;
16315 if (tg3_10_100_only_device(tp
, ent
))
16316 tp
->phy_flags
|= TG3_PHYFLG_10_100_ONLY
;
16318 err
= tg3_phy_probe(tp
);
16320 dev_err(&tp
->pdev
->dev
, "phy probe failed, err %d\n", err
);
16321 /* ... but do not return immediately ... */
16326 tg3_read_fw_ver(tp
);
16328 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
) {
16329 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
16331 if (tg3_asic_rev(tp
) == ASIC_REV_5700
)
16332 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
16334 tp
->phy_flags
&= ~TG3_PHYFLG_USE_MI_INTERRUPT
;
16337 /* 5700 {AX,BX} chips have a broken status block link
16338 * change bit implementation, so we must use the
16339 * status register in those cases.
16341 if (tg3_asic_rev(tp
) == ASIC_REV_5700
)
16342 tg3_flag_set(tp
, USE_LINKCHG_REG
);
16344 tg3_flag_clear(tp
, USE_LINKCHG_REG
);
16346 /* The led_ctrl is set during tg3_phy_probe, here we might
16347 * have to force the link status polling mechanism based
16348 * upon subsystem IDs.
16350 if (tp
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_DELL
&&
16351 tg3_asic_rev(tp
) == ASIC_REV_5701
&&
16352 !(tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)) {
16353 tp
->phy_flags
|= TG3_PHYFLG_USE_MI_INTERRUPT
;
16354 tg3_flag_set(tp
, USE_LINKCHG_REG
);
16357 /* For all SERDES we poll the MAC status register. */
16358 if (tp
->phy_flags
& TG3_PHYFLG_PHY_SERDES
)
16359 tg3_flag_set(tp
, POLL_SERDES
);
16361 tg3_flag_clear(tp
, POLL_SERDES
);
16363 tp
->rx_offset
= NET_SKB_PAD
+ NET_IP_ALIGN
;
16364 tp
->rx_copy_thresh
= TG3_RX_COPY_THRESHOLD
;
16365 if (tg3_asic_rev(tp
) == ASIC_REV_5701
&&
16366 tg3_flag(tp
, PCIX_MODE
)) {
16367 tp
->rx_offset
= NET_SKB_PAD
;
16368 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
16369 tp
->rx_copy_thresh
= ~(u16
)0;
16373 tp
->rx_std_ring_mask
= TG3_RX_STD_RING_SIZE(tp
) - 1;
16374 tp
->rx_jmb_ring_mask
= TG3_RX_JMB_RING_SIZE(tp
) - 1;
16375 tp
->rx_ret_ring_mask
= tg3_rx_ret_ring_size(tp
) - 1;
16377 tp
->rx_std_max_post
= tp
->rx_std_ring_mask
+ 1;
16379 /* Increment the rx prod index on the rx std ring by at most
16380 * 8 for these chips to workaround hw errata.
16382 if (tg3_asic_rev(tp
) == ASIC_REV_5750
||
16383 tg3_asic_rev(tp
) == ASIC_REV_5752
||
16384 tg3_asic_rev(tp
) == ASIC_REV_5755
)
16385 tp
->rx_std_max_post
= 8;
16387 if (tg3_flag(tp
, ASPM_WORKAROUND
))
16388 tp
->pwrmgmt_thresh
= tr32(PCIE_PWR_MGMT_THRESH
) &
16389 PCIE_PWR_MGMT_L1_THRESH_MSK
;
16394 #ifdef CONFIG_SPARC
16395 static int tg3_get_macaddr_sparc(struct tg3
*tp
)
16397 struct net_device
*dev
= tp
->dev
;
16398 struct pci_dev
*pdev
= tp
->pdev
;
16399 struct device_node
*dp
= pci_device_to_OF_node(pdev
);
16400 const unsigned char *addr
;
16403 addr
= of_get_property(dp
, "local-mac-address", &len
);
16404 if (addr
&& len
== 6) {
16405 memcpy(dev
->dev_addr
, addr
, 6);
16411 static int tg3_get_default_macaddr_sparc(struct tg3
*tp
)
16413 struct net_device
*dev
= tp
->dev
;
16415 memcpy(dev
->dev_addr
, idprom
->id_ethaddr
, 6);
16420 static int tg3_get_device_address(struct tg3
*tp
)
16422 struct net_device
*dev
= tp
->dev
;
16423 u32 hi
, lo
, mac_offset
;
16427 #ifdef CONFIG_SPARC
16428 if (!tg3_get_macaddr_sparc(tp
))
16432 if (tg3_flag(tp
, IS_SSB_CORE
)) {
16433 err
= ssb_gige_get_macaddr(tp
->pdev
, &dev
->dev_addr
[0]);
16434 if (!err
&& is_valid_ether_addr(&dev
->dev_addr
[0]))
16439 if (tg3_asic_rev(tp
) == ASIC_REV_5704
||
16440 tg3_flag(tp
, 5780_CLASS
)) {
16441 if (tr32(TG3PCI_DUAL_MAC_CTRL
) & DUAL_MAC_CTRL_ID
)
16443 if (tg3_nvram_lock(tp
))
16444 tw32_f(NVRAM_CMD
, NVRAM_CMD_RESET
);
16446 tg3_nvram_unlock(tp
);
16447 } else if (tg3_flag(tp
, 5717_PLUS
)) {
16448 if (tp
->pci_fn
& 1)
16450 if (tp
->pci_fn
> 1)
16451 mac_offset
+= 0x18c;
16452 } else if (tg3_asic_rev(tp
) == ASIC_REV_5906
)
16455 /* First try to get it from MAC address mailbox. */
16456 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_HIGH_MBOX
, &hi
);
16457 if ((hi
>> 16) == 0x484b) {
16458 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
16459 dev
->dev_addr
[1] = (hi
>> 0) & 0xff;
16461 tg3_read_mem(tp
, NIC_SRAM_MAC_ADDR_LOW_MBOX
, &lo
);
16462 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
16463 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
16464 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
16465 dev
->dev_addr
[5] = (lo
>> 0) & 0xff;
16467 /* Some old bootcode may report a 0 MAC address in SRAM */
16468 addr_ok
= is_valid_ether_addr(&dev
->dev_addr
[0]);
16471 /* Next, try NVRAM. */
16472 if (!tg3_flag(tp
, NO_NVRAM
) &&
16473 !tg3_nvram_read_be32(tp
, mac_offset
+ 0, &hi
) &&
16474 !tg3_nvram_read_be32(tp
, mac_offset
+ 4, &lo
)) {
16475 memcpy(&dev
->dev_addr
[0], ((char *)&hi
) + 2, 2);
16476 memcpy(&dev
->dev_addr
[2], (char *)&lo
, sizeof(lo
));
16478 /* Finally just fetch it out of the MAC control regs. */
16480 hi
= tr32(MAC_ADDR_0_HIGH
);
16481 lo
= tr32(MAC_ADDR_0_LOW
);
16483 dev
->dev_addr
[5] = lo
& 0xff;
16484 dev
->dev_addr
[4] = (lo
>> 8) & 0xff;
16485 dev
->dev_addr
[3] = (lo
>> 16) & 0xff;
16486 dev
->dev_addr
[2] = (lo
>> 24) & 0xff;
16487 dev
->dev_addr
[1] = hi
& 0xff;
16488 dev
->dev_addr
[0] = (hi
>> 8) & 0xff;
16492 if (!is_valid_ether_addr(&dev
->dev_addr
[0])) {
16493 #ifdef CONFIG_SPARC
16494 if (!tg3_get_default_macaddr_sparc(tp
))
16502 #define BOUNDARY_SINGLE_CACHELINE 1
16503 #define BOUNDARY_MULTI_CACHELINE 2
16505 static u32
tg3_calc_dma_bndry(struct tg3
*tp
, u32 val
)
16507 int cacheline_size
;
16511 pci_read_config_byte(tp
->pdev
, PCI_CACHE_LINE_SIZE
, &byte
);
16513 cacheline_size
= 1024;
16515 cacheline_size
= (int) byte
* 4;
16517 /* On 5703 and later chips, the boundary bits have no
16520 if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
16521 tg3_asic_rev(tp
) != ASIC_REV_5701
&&
16522 !tg3_flag(tp
, PCI_EXPRESS
))
16525 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
16526 goal
= BOUNDARY_MULTI_CACHELINE
;
16528 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
16529 goal
= BOUNDARY_SINGLE_CACHELINE
;
16535 if (tg3_flag(tp
, 57765_PLUS
)) {
16536 val
= goal
? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT
;
16543 /* PCI controllers on most RISC systems tend to disconnect
16544 * when a device tries to burst across a cache-line boundary.
16545 * Therefore, letting tg3 do so just wastes PCI bandwidth.
16547 * Unfortunately, for PCI-E there are only limited
16548 * write-side controls for this, and thus for reads
16549 * we will still get the disconnects. We'll also waste
16550 * these PCI cycles for both read and write for chips
16551 * other than 5700 and 5701 which do not implement the
16554 if (tg3_flag(tp
, PCIX_MODE
) && !tg3_flag(tp
, PCI_EXPRESS
)) {
16555 switch (cacheline_size
) {
16560 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
16561 val
|= (DMA_RWCTRL_READ_BNDRY_128_PCIX
|
16562 DMA_RWCTRL_WRITE_BNDRY_128_PCIX
);
16564 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
16565 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
16570 val
|= (DMA_RWCTRL_READ_BNDRY_256_PCIX
|
16571 DMA_RWCTRL_WRITE_BNDRY_256_PCIX
);
16575 val
|= (DMA_RWCTRL_READ_BNDRY_384_PCIX
|
16576 DMA_RWCTRL_WRITE_BNDRY_384_PCIX
);
16579 } else if (tg3_flag(tp
, PCI_EXPRESS
)) {
16580 switch (cacheline_size
) {
16584 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
16585 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
16586 val
|= DMA_RWCTRL_WRITE_BNDRY_64_PCIE
;
16592 val
&= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE
;
16593 val
|= DMA_RWCTRL_WRITE_BNDRY_128_PCIE
;
16597 switch (cacheline_size
) {
16599 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
16600 val
|= (DMA_RWCTRL_READ_BNDRY_16
|
16601 DMA_RWCTRL_WRITE_BNDRY_16
);
16606 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
16607 val
|= (DMA_RWCTRL_READ_BNDRY_32
|
16608 DMA_RWCTRL_WRITE_BNDRY_32
);
16613 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
16614 val
|= (DMA_RWCTRL_READ_BNDRY_64
|
16615 DMA_RWCTRL_WRITE_BNDRY_64
);
16620 if (goal
== BOUNDARY_SINGLE_CACHELINE
) {
16621 val
|= (DMA_RWCTRL_READ_BNDRY_128
|
16622 DMA_RWCTRL_WRITE_BNDRY_128
);
16627 val
|= (DMA_RWCTRL_READ_BNDRY_256
|
16628 DMA_RWCTRL_WRITE_BNDRY_256
);
16631 val
|= (DMA_RWCTRL_READ_BNDRY_512
|
16632 DMA_RWCTRL_WRITE_BNDRY_512
);
16636 val
|= (DMA_RWCTRL_READ_BNDRY_1024
|
16637 DMA_RWCTRL_WRITE_BNDRY_1024
);
16646 static int tg3_do_test_dma(struct tg3
*tp
, u32
*buf
, dma_addr_t buf_dma
,
16647 int size
, bool to_device
)
16649 struct tg3_internal_buffer_desc test_desc
;
16650 u32 sram_dma_descs
;
16653 sram_dma_descs
= NIC_SRAM_DMA_DESC_POOL_BASE
;
16655 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
, 0);
16656 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
, 0);
16657 tw32(RDMAC_STATUS
, 0);
16658 tw32(WDMAC_STATUS
, 0);
16660 tw32(BUFMGR_MODE
, 0);
16661 tw32(FTQ_RESET
, 0);
16663 test_desc
.addr_hi
= ((u64
) buf_dma
) >> 32;
16664 test_desc
.addr_lo
= buf_dma
& 0xffffffff;
16665 test_desc
.nic_mbuf
= 0x00002100;
16666 test_desc
.len
= size
;
16669 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
16670 * the *second* time the tg3 driver was getting loaded after an
16673 * Broadcom tells me:
16674 * ...the DMA engine is connected to the GRC block and a DMA
16675 * reset may affect the GRC block in some unpredictable way...
16676 * The behavior of resets to individual blocks has not been tested.
16678 * Broadcom noted the GRC reset will also reset all sub-components.
16681 test_desc
.cqid_sqid
= (13 << 8) | 2;
16683 tw32_f(RDMAC_MODE
, RDMAC_MODE_ENABLE
);
16686 test_desc
.cqid_sqid
= (16 << 8) | 7;
16688 tw32_f(WDMAC_MODE
, WDMAC_MODE_ENABLE
);
16691 test_desc
.flags
= 0x00000005;
16693 for (i
= 0; i
< (sizeof(test_desc
) / sizeof(u32
)); i
++) {
16696 val
= *(((u32
*)&test_desc
) + i
);
16697 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
,
16698 sram_dma_descs
+ (i
* sizeof(u32
)));
16699 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_DATA
, val
);
16701 pci_write_config_dword(tp
->pdev
, TG3PCI_MEM_WIN_BASE_ADDR
, 0);
16704 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ
, sram_dma_descs
);
16706 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ
, sram_dma_descs
);
16709 for (i
= 0; i
< 40; i
++) {
16713 val
= tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ
);
16715 val
= tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ
);
16716 if ((val
& 0xffff) == sram_dma_descs
) {
16727 #define TEST_BUFFER_SIZE 0x2000
16729 static DEFINE_PCI_DEVICE_TABLE(tg3_dma_wait_state_chipsets
) = {
16730 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, PCI_DEVICE_ID_APPLE_UNI_N_PCI15
) },
16734 static int tg3_test_dma(struct tg3
*tp
)
16736 dma_addr_t buf_dma
;
16737 u32
*buf
, saved_dma_rwctrl
;
16740 buf
= dma_alloc_coherent(&tp
->pdev
->dev
, TEST_BUFFER_SIZE
,
16741 &buf_dma
, GFP_KERNEL
);
16747 tp
->dma_rwctrl
= ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT
) |
16748 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT
));
16750 tp
->dma_rwctrl
= tg3_calc_dma_bndry(tp
, tp
->dma_rwctrl
);
16752 if (tg3_flag(tp
, 57765_PLUS
))
16755 if (tg3_flag(tp
, PCI_EXPRESS
)) {
16756 /* DMA read watermark not used on PCIE */
16757 tp
->dma_rwctrl
|= 0x00180000;
16758 } else if (!tg3_flag(tp
, PCIX_MODE
)) {
16759 if (tg3_asic_rev(tp
) == ASIC_REV_5705
||
16760 tg3_asic_rev(tp
) == ASIC_REV_5750
)
16761 tp
->dma_rwctrl
|= 0x003f0000;
16763 tp
->dma_rwctrl
|= 0x003f000f;
16765 if (tg3_asic_rev(tp
) == ASIC_REV_5703
||
16766 tg3_asic_rev(tp
) == ASIC_REV_5704
) {
16767 u32 ccval
= (tr32(TG3PCI_CLOCK_CTRL
) & 0x1f);
16768 u32 read_water
= 0x7;
16770 /* If the 5704 is behind the EPB bridge, we can
16771 * do the less restrictive ONE_DMA workaround for
16772 * better performance.
16774 if (tg3_flag(tp
, 40BIT_DMA_BUG
) &&
16775 tg3_asic_rev(tp
) == ASIC_REV_5704
)
16776 tp
->dma_rwctrl
|= 0x8000;
16777 else if (ccval
== 0x6 || ccval
== 0x7)
16778 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
16780 if (tg3_asic_rev(tp
) == ASIC_REV_5703
)
16782 /* Set bit 23 to enable PCIX hw bug fix */
16784 (read_water
<< DMA_RWCTRL_READ_WATER_SHIFT
) |
16785 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT
) |
16787 } else if (tg3_asic_rev(tp
) == ASIC_REV_5780
) {
16788 /* 5780 always in PCIX mode */
16789 tp
->dma_rwctrl
|= 0x00144000;
16790 } else if (tg3_asic_rev(tp
) == ASIC_REV_5714
) {
16791 /* 5714 always in PCIX mode */
16792 tp
->dma_rwctrl
|= 0x00148000;
16794 tp
->dma_rwctrl
|= 0x001b000f;
16797 if (tg3_flag(tp
, ONE_DMA_AT_ONCE
))
16798 tp
->dma_rwctrl
|= DMA_RWCTRL_ONE_DMA
;
16800 if (tg3_asic_rev(tp
) == ASIC_REV_5703
||
16801 tg3_asic_rev(tp
) == ASIC_REV_5704
)
16802 tp
->dma_rwctrl
&= 0xfffffff0;
16804 if (tg3_asic_rev(tp
) == ASIC_REV_5700
||
16805 tg3_asic_rev(tp
) == ASIC_REV_5701
) {
16806 /* Remove this if it causes problems for some boards. */
16807 tp
->dma_rwctrl
|= DMA_RWCTRL_USE_MEM_READ_MULT
;
16809 /* On 5700/5701 chips, we need to set this bit.
16810 * Otherwise the chip will issue cacheline transactions
16811 * to streamable DMA memory with not all the byte
16812 * enables turned on. This is an error on several
16813 * RISC PCI controllers, in particular sparc64.
16815 * On 5703/5704 chips, this bit has been reassigned
16816 * a different meaning. In particular, it is used
16817 * on those chips to enable a PCI-X workaround.
16819 tp
->dma_rwctrl
|= DMA_RWCTRL_ASSERT_ALL_BE
;
16822 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
16825 /* Unneeded, already done by tg3_get_invariants. */
16826 tg3_switch_clocks(tp
);
16829 if (tg3_asic_rev(tp
) != ASIC_REV_5700
&&
16830 tg3_asic_rev(tp
) != ASIC_REV_5701
)
16833 /* It is best to perform DMA test with maximum write burst size
16834 * to expose the 5700/5701 write DMA bug.
16836 saved_dma_rwctrl
= tp
->dma_rwctrl
;
16837 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
16838 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
16843 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++)
16846 /* Send the buffer to the chip. */
16847 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, true);
16849 dev_err(&tp
->pdev
->dev
,
16850 "%s: Buffer write failed. err = %d\n",
16856 /* validate data reached card RAM correctly. */
16857 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
16859 tg3_read_mem(tp
, 0x2100 + (i
*4), &val
);
16860 if (le32_to_cpu(val
) != p
[i
]) {
16861 dev_err(&tp
->pdev
->dev
,
16862 "%s: Buffer corrupted on device! "
16863 "(%d != %d)\n", __func__
, val
, i
);
16864 /* ret = -ENODEV here? */
16869 /* Now read it back. */
16870 ret
= tg3_do_test_dma(tp
, buf
, buf_dma
, TEST_BUFFER_SIZE
, false);
16872 dev_err(&tp
->pdev
->dev
, "%s: Buffer read failed. "
16873 "err = %d\n", __func__
, ret
);
16878 for (i
= 0; i
< TEST_BUFFER_SIZE
/ sizeof(u32
); i
++) {
16882 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
16883 DMA_RWCTRL_WRITE_BNDRY_16
) {
16884 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
16885 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
16886 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
16889 dev_err(&tp
->pdev
->dev
,
16890 "%s: Buffer corrupted on read back! "
16891 "(%d != %d)\n", __func__
, p
[i
], i
);
16897 if (i
== (TEST_BUFFER_SIZE
/ sizeof(u32
))) {
16903 if ((tp
->dma_rwctrl
& DMA_RWCTRL_WRITE_BNDRY_MASK
) !=
16904 DMA_RWCTRL_WRITE_BNDRY_16
) {
16905 /* DMA test passed without adjusting DMA boundary,
16906 * now look for chipsets that are known to expose the
16907 * DMA bug without failing the test.
16909 if (pci_dev_present(tg3_dma_wait_state_chipsets
)) {
16910 tp
->dma_rwctrl
&= ~DMA_RWCTRL_WRITE_BNDRY_MASK
;
16911 tp
->dma_rwctrl
|= DMA_RWCTRL_WRITE_BNDRY_16
;
16913 /* Safe to use the calculated DMA boundary. */
16914 tp
->dma_rwctrl
= saved_dma_rwctrl
;
16917 tw32(TG3PCI_DMA_RW_CTRL
, tp
->dma_rwctrl
);
16921 dma_free_coherent(&tp
->pdev
->dev
, TEST_BUFFER_SIZE
, buf
, buf_dma
);
16926 static void tg3_init_bufmgr_config(struct tg3
*tp
)
16928 if (tg3_flag(tp
, 57765_PLUS
)) {
16929 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
16930 DEFAULT_MB_RDMA_LOW_WATER_5705
;
16931 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
16932 DEFAULT_MB_MACRX_LOW_WATER_57765
;
16933 tp
->bufmgr_config
.mbuf_high_water
=
16934 DEFAULT_MB_HIGH_WATER_57765
;
16936 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
16937 DEFAULT_MB_RDMA_LOW_WATER_5705
;
16938 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
16939 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765
;
16940 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
16941 DEFAULT_MB_HIGH_WATER_JUMBO_57765
;
16942 } else if (tg3_flag(tp
, 5705_PLUS
)) {
16943 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
16944 DEFAULT_MB_RDMA_LOW_WATER_5705
;
16945 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
16946 DEFAULT_MB_MACRX_LOW_WATER_5705
;
16947 tp
->bufmgr_config
.mbuf_high_water
=
16948 DEFAULT_MB_HIGH_WATER_5705
;
16949 if (tg3_asic_rev(tp
) == ASIC_REV_5906
) {
16950 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
16951 DEFAULT_MB_MACRX_LOW_WATER_5906
;
16952 tp
->bufmgr_config
.mbuf_high_water
=
16953 DEFAULT_MB_HIGH_WATER_5906
;
16956 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
16957 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780
;
16958 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
16959 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780
;
16960 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
16961 DEFAULT_MB_HIGH_WATER_JUMBO_5780
;
16963 tp
->bufmgr_config
.mbuf_read_dma_low_water
=
16964 DEFAULT_MB_RDMA_LOW_WATER
;
16965 tp
->bufmgr_config
.mbuf_mac_rx_low_water
=
16966 DEFAULT_MB_MACRX_LOW_WATER
;
16967 tp
->bufmgr_config
.mbuf_high_water
=
16968 DEFAULT_MB_HIGH_WATER
;
16970 tp
->bufmgr_config
.mbuf_read_dma_low_water_jumbo
=
16971 DEFAULT_MB_RDMA_LOW_WATER_JUMBO
;
16972 tp
->bufmgr_config
.mbuf_mac_rx_low_water_jumbo
=
16973 DEFAULT_MB_MACRX_LOW_WATER_JUMBO
;
16974 tp
->bufmgr_config
.mbuf_high_water_jumbo
=
16975 DEFAULT_MB_HIGH_WATER_JUMBO
;
16978 tp
->bufmgr_config
.dma_low_water
= DEFAULT_DMA_LOW_WATER
;
16979 tp
->bufmgr_config
.dma_high_water
= DEFAULT_DMA_HIGH_WATER
;
16982 static char *tg3_phy_string(struct tg3
*tp
)
16984 switch (tp
->phy_id
& TG3_PHY_ID_MASK
) {
16985 case TG3_PHY_ID_BCM5400
: return "5400";
16986 case TG3_PHY_ID_BCM5401
: return "5401";
16987 case TG3_PHY_ID_BCM5411
: return "5411";
16988 case TG3_PHY_ID_BCM5701
: return "5701";
16989 case TG3_PHY_ID_BCM5703
: return "5703";
16990 case TG3_PHY_ID_BCM5704
: return "5704";
16991 case TG3_PHY_ID_BCM5705
: return "5705";
16992 case TG3_PHY_ID_BCM5750
: return "5750";
16993 case TG3_PHY_ID_BCM5752
: return "5752";
16994 case TG3_PHY_ID_BCM5714
: return "5714";
16995 case TG3_PHY_ID_BCM5780
: return "5780";
16996 case TG3_PHY_ID_BCM5755
: return "5755";
16997 case TG3_PHY_ID_BCM5787
: return "5787";
16998 case TG3_PHY_ID_BCM5784
: return "5784";
16999 case TG3_PHY_ID_BCM5756
: return "5722/5756";
17000 case TG3_PHY_ID_BCM5906
: return "5906";
17001 case TG3_PHY_ID_BCM5761
: return "5761";
17002 case TG3_PHY_ID_BCM5718C
: return "5718C";
17003 case TG3_PHY_ID_BCM5718S
: return "5718S";
17004 case TG3_PHY_ID_BCM57765
: return "57765";
17005 case TG3_PHY_ID_BCM5719C
: return "5719C";
17006 case TG3_PHY_ID_BCM5720C
: return "5720C";
17007 case TG3_PHY_ID_BCM5762
: return "5762C";
17008 case TG3_PHY_ID_BCM8002
: return "8002/serdes";
17009 case 0: return "serdes";
17010 default: return "unknown";
17014 static char *tg3_bus_string(struct tg3
*tp
, char *str
)
17016 if (tg3_flag(tp
, PCI_EXPRESS
)) {
17017 strcpy(str
, "PCI Express");
17019 } else if (tg3_flag(tp
, PCIX_MODE
)) {
17020 u32 clock_ctrl
= tr32(TG3PCI_CLOCK_CTRL
) & 0x1f;
17022 strcpy(str
, "PCIX:");
17024 if ((clock_ctrl
== 7) ||
17025 ((tr32(GRC_MISC_CFG
) & GRC_MISC_CFG_BOARD_ID_MASK
) ==
17026 GRC_MISC_CFG_BOARD_ID_5704CIOBE
))
17027 strcat(str
, "133MHz");
17028 else if (clock_ctrl
== 0)
17029 strcat(str
, "33MHz");
17030 else if (clock_ctrl
== 2)
17031 strcat(str
, "50MHz");
17032 else if (clock_ctrl
== 4)
17033 strcat(str
, "66MHz");
17034 else if (clock_ctrl
== 6)
17035 strcat(str
, "100MHz");
17037 strcpy(str
, "PCI:");
17038 if (tg3_flag(tp
, PCI_HIGH_SPEED
))
17039 strcat(str
, "66MHz");
17041 strcat(str
, "33MHz");
17043 if (tg3_flag(tp
, PCI_32BIT
))
17044 strcat(str
, ":32-bit");
17046 strcat(str
, ":64-bit");
17050 static void tg3_init_coal(struct tg3
*tp
)
17052 struct ethtool_coalesce
*ec
= &tp
->coal
;
17054 memset(ec
, 0, sizeof(*ec
));
17055 ec
->cmd
= ETHTOOL_GCOALESCE
;
17056 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS
;
17057 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS
;
17058 ec
->rx_max_coalesced_frames
= LOW_RXMAX_FRAMES
;
17059 ec
->tx_max_coalesced_frames
= LOW_TXMAX_FRAMES
;
17060 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT
;
17061 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT
;
17062 ec
->rx_max_coalesced_frames_irq
= DEFAULT_RXCOAL_MAXF_INT
;
17063 ec
->tx_max_coalesced_frames_irq
= DEFAULT_TXCOAL_MAXF_INT
;
17064 ec
->stats_block_coalesce_usecs
= DEFAULT_STAT_COAL_TICKS
;
17066 if (tp
->coalesce_mode
& (HOSTCC_MODE_CLRTICK_RXBD
|
17067 HOSTCC_MODE_CLRTICK_TXBD
)) {
17068 ec
->rx_coalesce_usecs
= LOW_RXCOL_TICKS_CLRTCKS
;
17069 ec
->rx_coalesce_usecs_irq
= DEFAULT_RXCOAL_TICK_INT_CLRTCKS
;
17070 ec
->tx_coalesce_usecs
= LOW_TXCOL_TICKS_CLRTCKS
;
17071 ec
->tx_coalesce_usecs_irq
= DEFAULT_TXCOAL_TICK_INT_CLRTCKS
;
17074 if (tg3_flag(tp
, 5705_PLUS
)) {
17075 ec
->rx_coalesce_usecs_irq
= 0;
17076 ec
->tx_coalesce_usecs_irq
= 0;
17077 ec
->stats_block_coalesce_usecs
= 0;
17081 static int tg3_init_one(struct pci_dev
*pdev
,
17082 const struct pci_device_id
*ent
)
17084 struct net_device
*dev
;
17086 int i
, err
, pm_cap
;
17087 u32 sndmbx
, rcvmbx
, intmbx
;
17089 u64 dma_mask
, persist_dma_mask
;
17090 netdev_features_t features
= 0;
17092 printk_once(KERN_INFO
"%s\n", version
);
17094 err
= pci_enable_device(pdev
);
17096 dev_err(&pdev
->dev
, "Cannot enable PCI device, aborting\n");
17100 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
17102 dev_err(&pdev
->dev
, "Cannot obtain PCI resources, aborting\n");
17103 goto err_out_disable_pdev
;
17106 pci_set_master(pdev
);
17108 /* Find power-management capability. */
17109 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
17111 dev_err(&pdev
->dev
,
17112 "Cannot find Power Management capability, aborting\n");
17114 goto err_out_free_res
;
17117 err
= pci_set_power_state(pdev
, PCI_D0
);
17119 dev_err(&pdev
->dev
, "Transition to D0 failed, aborting\n");
17120 goto err_out_free_res
;
17123 dev
= alloc_etherdev_mq(sizeof(*tp
), TG3_IRQ_MAX_VECS
);
17126 goto err_out_power_down
;
17129 SET_NETDEV_DEV(dev
, &pdev
->dev
);
17131 tp
= netdev_priv(dev
);
17134 tp
->pm_cap
= pm_cap
;
17135 tp
->rx_mode
= TG3_DEF_RX_MODE
;
17136 tp
->tx_mode
= TG3_DEF_TX_MODE
;
17140 tp
->msg_enable
= tg3_debug
;
17142 tp
->msg_enable
= TG3_DEF_MSG_ENABLE
;
17144 if (pdev_is_ssb_gige_core(pdev
)) {
17145 tg3_flag_set(tp
, IS_SSB_CORE
);
17146 if (ssb_gige_must_flush_posted_writes(pdev
))
17147 tg3_flag_set(tp
, FLUSH_POSTED_WRITES
);
17148 if (ssb_gige_one_dma_at_once(pdev
))
17149 tg3_flag_set(tp
, ONE_DMA_AT_ONCE
);
17150 if (ssb_gige_have_roboswitch(pdev
))
17151 tg3_flag_set(tp
, ROBOSWITCH
);
17152 if (ssb_gige_is_rgmii(pdev
))
17153 tg3_flag_set(tp
, RGMII_MODE
);
17156 /* The word/byte swap controls here control register access byte
17157 * swapping. DMA data byte swapping is controlled in the GRC_MODE
17160 tp
->misc_host_ctrl
=
17161 MISC_HOST_CTRL_MASK_PCI_INT
|
17162 MISC_HOST_CTRL_WORD_SWAP
|
17163 MISC_HOST_CTRL_INDIR_ACCESS
|
17164 MISC_HOST_CTRL_PCISTATE_RW
;
17166 /* The NONFRM (non-frame) byte/word swap controls take effect
17167 * on descriptor entries, anything which isn't packet data.
17169 * The StrongARM chips on the board (one for tx, one for rx)
17170 * are running in big-endian mode.
17172 tp
->grc_mode
= (GRC_MODE_WSWAP_DATA
| GRC_MODE_BSWAP_DATA
|
17173 GRC_MODE_WSWAP_NONFRM_DATA
);
17174 #ifdef __BIG_ENDIAN
17175 tp
->grc_mode
|= GRC_MODE_BSWAP_NONFRM_DATA
;
17177 spin_lock_init(&tp
->lock
);
17178 spin_lock_init(&tp
->indirect_lock
);
17179 INIT_WORK(&tp
->reset_task
, tg3_reset_task
);
17181 tp
->regs
= pci_ioremap_bar(pdev
, BAR_0
);
17183 dev_err(&pdev
->dev
, "Cannot map device registers, aborting\n");
17185 goto err_out_free_dev
;
17188 if (tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761
||
17189 tp
->pdev
->device
== PCI_DEVICE_ID_TIGON3_5761E
||
17190 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761S
||
17191 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5761SE
||
17192 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717
||
17193 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5717_C
||
17194 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5718
||
17195 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5719
||
17196 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5720
||
17197 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5762
||
17198 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5725
||
17199 tp
->pdev
->device
== TG3PCI_DEVICE_TIGON3_5727
) {
17200 tg3_flag_set(tp
, ENABLE_APE
);
17201 tp
->aperegs
= pci_ioremap_bar(pdev
, BAR_2
);
17202 if (!tp
->aperegs
) {
17203 dev_err(&pdev
->dev
,
17204 "Cannot map APE registers, aborting\n");
17206 goto err_out_iounmap
;
17210 tp
->rx_pending
= TG3_DEF_RX_RING_PENDING
;
17211 tp
->rx_jumbo_pending
= TG3_DEF_RX_JUMBO_RING_PENDING
;
17213 dev
->ethtool_ops
= &tg3_ethtool_ops
;
17214 dev
->watchdog_timeo
= TG3_TX_TIMEOUT
;
17215 dev
->netdev_ops
= &tg3_netdev_ops
;
17216 dev
->irq
= pdev
->irq
;
17218 err
= tg3_get_invariants(tp
, ent
);
17220 dev_err(&pdev
->dev
,
17221 "Problem fetching invariants of chip, aborting\n");
17222 goto err_out_apeunmap
;
17225 /* The EPB bridge inside 5714, 5715, and 5780 and any
17226 * device behind the EPB cannot support DMA addresses > 40-bit.
17227 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
17228 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
17229 * do DMA address check in tg3_start_xmit().
17231 if (tg3_flag(tp
, IS_5788
))
17232 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(32);
17233 else if (tg3_flag(tp
, 40BIT_DMA_BUG
)) {
17234 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(40);
17235 #ifdef CONFIG_HIGHMEM
17236 dma_mask
= DMA_BIT_MASK(64);
17239 persist_dma_mask
= dma_mask
= DMA_BIT_MASK(64);
17241 /* Configure DMA attributes. */
17242 if (dma_mask
> DMA_BIT_MASK(32)) {
17243 err
= pci_set_dma_mask(pdev
, dma_mask
);
17245 features
|= NETIF_F_HIGHDMA
;
17246 err
= pci_set_consistent_dma_mask(pdev
,
17249 dev_err(&pdev
->dev
, "Unable to obtain 64 bit "
17250 "DMA for consistent allocations\n");
17251 goto err_out_apeunmap
;
17255 if (err
|| dma_mask
== DMA_BIT_MASK(32)) {
17256 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
17258 dev_err(&pdev
->dev
,
17259 "No usable DMA configuration, aborting\n");
17260 goto err_out_apeunmap
;
17264 tg3_init_bufmgr_config(tp
);
17266 features
|= NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
17268 /* 5700 B0 chips do not support checksumming correctly due
17269 * to hardware bugs.
17271 if (tg3_chip_rev_id(tp
) != CHIPREV_ID_5700_B0
) {
17272 features
|= NETIF_F_SG
| NETIF_F_IP_CSUM
| NETIF_F_RXCSUM
;
17274 if (tg3_flag(tp
, 5755_PLUS
))
17275 features
|= NETIF_F_IPV6_CSUM
;
17278 /* TSO is on by default on chips that support hardware TSO.
17279 * Firmware TSO on older chips gives lower performance, so it
17280 * is off by default, but can be enabled using ethtool.
17282 if ((tg3_flag(tp
, HW_TSO_1
) ||
17283 tg3_flag(tp
, HW_TSO_2
) ||
17284 tg3_flag(tp
, HW_TSO_3
)) &&
17285 (features
& NETIF_F_IP_CSUM
))
17286 features
|= NETIF_F_TSO
;
17287 if (tg3_flag(tp
, HW_TSO_2
) || tg3_flag(tp
, HW_TSO_3
)) {
17288 if (features
& NETIF_F_IPV6_CSUM
)
17289 features
|= NETIF_F_TSO6
;
17290 if (tg3_flag(tp
, HW_TSO_3
) ||
17291 tg3_asic_rev(tp
) == ASIC_REV_5761
||
17292 (tg3_asic_rev(tp
) == ASIC_REV_5784
&&
17293 tg3_chip_rev(tp
) != CHIPREV_5784_AX
) ||
17294 tg3_asic_rev(tp
) == ASIC_REV_5785
||
17295 tg3_asic_rev(tp
) == ASIC_REV_57780
)
17296 features
|= NETIF_F_TSO_ECN
;
17299 dev
->features
|= features
;
17300 dev
->vlan_features
|= features
;
17303 * Add loopback capability only for a subset of devices that support
17304 * MAC-LOOPBACK. Eventually this need to be enhanced to allow INT-PHY
17305 * loopback for the remaining devices.
17307 if (tg3_asic_rev(tp
) != ASIC_REV_5780
&&
17308 !tg3_flag(tp
, CPMU_PRESENT
))
17309 /* Add the loopback capability */
17310 features
|= NETIF_F_LOOPBACK
;
17312 dev
->hw_features
|= features
;
17314 if (tg3_chip_rev_id(tp
) == CHIPREV_ID_5705_A1
&&
17315 !tg3_flag(tp
, TSO_CAPABLE
) &&
17316 !(tr32(TG3PCI_PCISTATE
) & PCISTATE_BUS_SPEED_HIGH
)) {
17317 tg3_flag_set(tp
, MAX_RXPEND_64
);
17318 tp
->rx_pending
= 63;
17321 err
= tg3_get_device_address(tp
);
17323 dev_err(&pdev
->dev
,
17324 "Could not obtain valid ethernet address, aborting\n");
17325 goto err_out_apeunmap
;
17329 * Reset chip in case UNDI or EFI driver did not shutdown
17330 * DMA self test will enable WDMAC and we'll see (spurious)
17331 * pending DMA on the PCI bus at that point.
17333 if ((tr32(HOSTCC_MODE
) & HOSTCC_MODE_ENABLE
) ||
17334 (tr32(WDMAC_MODE
) & WDMAC_MODE_ENABLE
)) {
17335 tw32(MEMARB_MODE
, MEMARB_MODE_ENABLE
);
17336 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
17339 err
= tg3_test_dma(tp
);
17341 dev_err(&pdev
->dev
, "DMA engine test failed, aborting\n");
17342 goto err_out_apeunmap
;
17345 intmbx
= MAILBOX_INTERRUPT_0
+ TG3_64BIT_REG_LOW
;
17346 rcvmbx
= MAILBOX_RCVRET_CON_IDX_0
+ TG3_64BIT_REG_LOW
;
17347 sndmbx
= MAILBOX_SNDHOST_PROD_IDX_0
+ TG3_64BIT_REG_LOW
;
17348 for (i
= 0; i
< tp
->irq_max
; i
++) {
17349 struct tg3_napi
*tnapi
= &tp
->napi
[i
];
17352 tnapi
->tx_pending
= TG3_DEF_TX_RING_PENDING
;
17354 tnapi
->int_mbox
= intmbx
;
17360 tnapi
->consmbox
= rcvmbx
;
17361 tnapi
->prodmbox
= sndmbx
;
17364 tnapi
->coal_now
= HOSTCC_MODE_COAL_VEC1_NOW
<< (i
- 1);
17366 tnapi
->coal_now
= HOSTCC_MODE_NOW
;
17368 if (!tg3_flag(tp
, SUPPORT_MSIX
))
17372 * If we support MSIX, we'll be using RSS. If we're using
17373 * RSS, the first vector only handles link interrupts and the
17374 * remaining vectors handle rx and tx interrupts. Reuse the
17375 * mailbox values for the next iteration. The values we setup
17376 * above are still useful for the single vectored mode.
17391 pci_set_drvdata(pdev
, dev
);
17393 if (tg3_asic_rev(tp
) == ASIC_REV_5719
||
17394 tg3_asic_rev(tp
) == ASIC_REV_5720
||
17395 tg3_asic_rev(tp
) == ASIC_REV_5762
)
17396 tg3_flag_set(tp
, PTP_CAPABLE
);
17398 if (tg3_flag(tp
, 5717_PLUS
)) {
17399 /* Resume a low-power mode */
17400 tg3_frob_aux_power(tp
, false);
17403 tg3_timer_init(tp
);
17405 tg3_carrier_off(tp
);
17407 err
= register_netdev(dev
);
17409 dev_err(&pdev
->dev
, "Cannot register net device, aborting\n");
17410 goto err_out_apeunmap
;
17413 netdev_info(dev
, "Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
17414 tp
->board_part_number
,
17415 tg3_chip_rev_id(tp
),
17416 tg3_bus_string(tp
, str
),
17419 if (tp
->phy_flags
& TG3_PHYFLG_IS_CONNECTED
) {
17420 struct phy_device
*phydev
;
17421 phydev
= tp
->mdio_bus
->phy_map
[TG3_PHY_MII_ADDR
];
17423 "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
17424 phydev
->drv
->name
, dev_name(&phydev
->dev
));
17428 if (tp
->phy_flags
& TG3_PHYFLG_10_100_ONLY
)
17429 ethtype
= "10/100Base-TX";
17430 else if (tp
->phy_flags
& TG3_PHYFLG_ANY_SERDES
)
17431 ethtype
= "1000Base-SX";
17433 ethtype
= "10/100/1000Base-T";
17435 netdev_info(dev
, "attached PHY is %s (%s Ethernet) "
17436 "(WireSpeed[%d], EEE[%d])\n",
17437 tg3_phy_string(tp
), ethtype
,
17438 (tp
->phy_flags
& TG3_PHYFLG_NO_ETH_WIRE_SPEED
) == 0,
17439 (tp
->phy_flags
& TG3_PHYFLG_EEE_CAP
) != 0);
17442 netdev_info(dev
, "RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
17443 (dev
->features
& NETIF_F_RXCSUM
) != 0,
17444 tg3_flag(tp
, USE_LINKCHG_REG
) != 0,
17445 (tp
->phy_flags
& TG3_PHYFLG_USE_MI_INTERRUPT
) != 0,
17446 tg3_flag(tp
, ENABLE_ASF
) != 0,
17447 tg3_flag(tp
, TSO_CAPABLE
) != 0);
17448 netdev_info(dev
, "dma_rwctrl[%08x] dma_mask[%d-bit]\n",
17450 pdev
->dma_mask
== DMA_BIT_MASK(32) ? 32 :
17451 ((u64
)pdev
->dma_mask
) == DMA_BIT_MASK(40) ? 40 : 64);
17453 pci_save_state(pdev
);
17459 iounmap(tp
->aperegs
);
17460 tp
->aperegs
= NULL
;
17472 err_out_power_down
:
17473 pci_set_power_state(pdev
, PCI_D3hot
);
17476 pci_release_regions(pdev
);
17478 err_out_disable_pdev
:
17479 pci_disable_device(pdev
);
17480 pci_set_drvdata(pdev
, NULL
);
17484 static void tg3_remove_one(struct pci_dev
*pdev
)
17486 struct net_device
*dev
= pci_get_drvdata(pdev
);
17489 struct tg3
*tp
= netdev_priv(dev
);
17491 release_firmware(tp
->fw
);
17493 tg3_reset_task_cancel(tp
);
17495 if (tg3_flag(tp
, USE_PHYLIB
)) {
17500 unregister_netdev(dev
);
17502 iounmap(tp
->aperegs
);
17503 tp
->aperegs
= NULL
;
17510 pci_release_regions(pdev
);
17511 pci_disable_device(pdev
);
17512 pci_set_drvdata(pdev
, NULL
);
17516 #ifdef CONFIG_PM_SLEEP
17517 static int tg3_suspend(struct device
*device
)
17519 struct pci_dev
*pdev
= to_pci_dev(device
);
17520 struct net_device
*dev
= pci_get_drvdata(pdev
);
17521 struct tg3
*tp
= netdev_priv(dev
);
17524 if (!netif_running(dev
))
17527 tg3_reset_task_cancel(tp
);
17529 tg3_netif_stop(tp
);
17531 tg3_timer_stop(tp
);
17533 tg3_full_lock(tp
, 1);
17534 tg3_disable_ints(tp
);
17535 tg3_full_unlock(tp
);
17537 netif_device_detach(dev
);
17539 tg3_full_lock(tp
, 0);
17540 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 1);
17541 tg3_flag_clear(tp
, INIT_COMPLETE
);
17542 tg3_full_unlock(tp
);
17544 err
= tg3_power_down_prepare(tp
);
17548 tg3_full_lock(tp
, 0);
17550 tg3_flag_set(tp
, INIT_COMPLETE
);
17551 err2
= tg3_restart_hw(tp
, true);
17555 tg3_timer_start(tp
);
17557 netif_device_attach(dev
);
17558 tg3_netif_start(tp
);
17561 tg3_full_unlock(tp
);
17570 static int tg3_resume(struct device
*device
)
17572 struct pci_dev
*pdev
= to_pci_dev(device
);
17573 struct net_device
*dev
= pci_get_drvdata(pdev
);
17574 struct tg3
*tp
= netdev_priv(dev
);
17577 if (!netif_running(dev
))
17580 netif_device_attach(dev
);
17582 tg3_full_lock(tp
, 0);
17584 tg3_flag_set(tp
, INIT_COMPLETE
);
17585 err
= tg3_restart_hw(tp
,
17586 !(tp
->phy_flags
& TG3_PHYFLG_KEEP_LINK_ON_PWRDN
));
17590 tg3_timer_start(tp
);
17592 tg3_netif_start(tp
);
17595 tg3_full_unlock(tp
);
17602 #endif /* CONFIG_PM_SLEEP */
17604 static SIMPLE_DEV_PM_OPS(tg3_pm_ops
, tg3_suspend
, tg3_resume
);
17607 * tg3_io_error_detected - called when PCI error is detected
17608 * @pdev: Pointer to PCI device
17609 * @state: The current pci connection state
17611 * This function is called after a PCI bus error affecting
17612 * this device has been detected.
17614 static pci_ers_result_t
tg3_io_error_detected(struct pci_dev
*pdev
,
17615 pci_channel_state_t state
)
17617 struct net_device
*netdev
= pci_get_drvdata(pdev
);
17618 struct tg3
*tp
= netdev_priv(netdev
);
17619 pci_ers_result_t err
= PCI_ERS_RESULT_NEED_RESET
;
17621 netdev_info(netdev
, "PCI I/O error detected\n");
17625 if (!netif_running(netdev
))
17630 tg3_netif_stop(tp
);
17632 tg3_timer_stop(tp
);
17634 /* Want to make sure that the reset task doesn't run */
17635 tg3_reset_task_cancel(tp
);
17637 netif_device_detach(netdev
);
17639 /* Clean up software state, even if MMIO is blocked */
17640 tg3_full_lock(tp
, 0);
17641 tg3_halt(tp
, RESET_KIND_SHUTDOWN
, 0);
17642 tg3_full_unlock(tp
);
17645 if (state
== pci_channel_io_perm_failure
)
17646 err
= PCI_ERS_RESULT_DISCONNECT
;
17648 pci_disable_device(pdev
);
17656 * tg3_io_slot_reset - called after the pci bus has been reset.
17657 * @pdev: Pointer to PCI device
17659 * Restart the card from scratch, as if from a cold-boot.
17660 * At this point, the card has exprienced a hard reset,
17661 * followed by fixups by BIOS, and has its config space
17662 * set up identically to what it was at cold boot.
17664 static pci_ers_result_t
tg3_io_slot_reset(struct pci_dev
*pdev
)
17666 struct net_device
*netdev
= pci_get_drvdata(pdev
);
17667 struct tg3
*tp
= netdev_priv(netdev
);
17668 pci_ers_result_t rc
= PCI_ERS_RESULT_DISCONNECT
;
17673 if (pci_enable_device(pdev
)) {
17674 netdev_err(netdev
, "Cannot re-enable PCI device after reset.\n");
17678 pci_set_master(pdev
);
17679 pci_restore_state(pdev
);
17680 pci_save_state(pdev
);
17682 if (!netif_running(netdev
)) {
17683 rc
= PCI_ERS_RESULT_RECOVERED
;
17687 err
= tg3_power_up(tp
);
17691 rc
= PCI_ERS_RESULT_RECOVERED
;
17700 * tg3_io_resume - called when traffic can start flowing again.
17701 * @pdev: Pointer to PCI device
17703 * This callback is called when the error recovery driver tells
17704 * us that its OK to resume normal operation.
17706 static void tg3_io_resume(struct pci_dev
*pdev
)
17708 struct net_device
*netdev
= pci_get_drvdata(pdev
);
17709 struct tg3
*tp
= netdev_priv(netdev
);
17714 if (!netif_running(netdev
))
17717 tg3_full_lock(tp
, 0);
17718 tg3_flag_set(tp
, INIT_COMPLETE
);
17719 err
= tg3_restart_hw(tp
, true);
17721 tg3_full_unlock(tp
);
17722 netdev_err(netdev
, "Cannot restart hardware after reset.\n");
17726 netif_device_attach(netdev
);
17728 tg3_timer_start(tp
);
17730 tg3_netif_start(tp
);
17732 tg3_full_unlock(tp
);
17740 static const struct pci_error_handlers tg3_err_handler
= {
17741 .error_detected
= tg3_io_error_detected
,
17742 .slot_reset
= tg3_io_slot_reset
,
17743 .resume
= tg3_io_resume
17746 static struct pci_driver tg3_driver
= {
17747 .name
= DRV_MODULE_NAME
,
17748 .id_table
= tg3_pci_tbl
,
17749 .probe
= tg3_init_one
,
17750 .remove
= tg3_remove_one
,
17751 .err_handler
= &tg3_err_handler
,
17752 .driver
.pm
= &tg3_pm_ops
,
17755 static int __init
tg3_init(void)
17757 return pci_register_driver(&tg3_driver
);
17760 static void __exit
tg3_cleanup(void)
17762 pci_unregister_driver(&tg3_driver
);
17765 module_init(tg3_init
);
17766 module_exit(tg3_cleanup
);