bna: ENET and Tx Rx Redesign Enablement
[deliverable/linux.git] / drivers / net / ethernet / brocade / bna / bfa_ioc.h
1 /*
2 * Linux network driver for Brocade Converged Network Adapter.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License (GPL) Version 2 as
6 * published by the Free Software Foundation
7 *
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
12 */
13 /*
14 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
15 * All rights reserved
16 * www.brocade.com
17 */
18
19 #ifndef __BFA_IOC_H__
20 #define __BFA_IOC_H__
21
22 #include "bfa_cs.h"
23 #include "bfi.h"
24 #include "cna.h"
25
26 #define BFA_IOC_TOV 3000 /* msecs */
27 #define BFA_IOC_HWSEM_TOV 500 /* msecs */
28 #define BFA_IOC_HB_TOV 500 /* msecs */
29 #define BFA_IOC_HWINIT_MAX 5
30 #define BFA_IOC_POLL_TOV 200 /* msecs */
31
32 /**
33 * PCI device information required by IOC
34 */
35 struct bfa_pcidev {
36 int pci_slot;
37 u8 pci_func;
38 u16 device_id;
39 void __iomem *pci_bar_kva;
40 };
41
42 /**
43 * Structure used to remember the DMA-able memory block's KVA and Physical
44 * Address
45 */
46 struct bfa_dma {
47 void *kva; /* ! Kernel virtual address */
48 u64 pa; /* ! Physical address */
49 };
50
51 #define BFA_DMA_ALIGN_SZ 256
52
53 /**
54 * smem size for Crossbow and Catapult
55 */
56 #define BFI_SMEM_CB_SIZE 0x200000U /* ! 2MB for crossbow */
57 #define BFI_SMEM_CT_SIZE 0x280000U /* ! 2.5MB for catapult */
58
59 /**
60 * @brief BFA dma address assignment macro. (big endian format)
61 */
62 #define bfa_dma_be_addr_set(dma_addr, pa) \
63 __bfa_dma_be_addr_set(&dma_addr, (u64)pa)
64 static inline void
65 __bfa_dma_be_addr_set(union bfi_addr_u *dma_addr, u64 pa)
66 {
67 dma_addr->a32.addr_lo = (u32) htonl(pa);
68 dma_addr->a32.addr_hi = (u32) htonl(upper_32_bits(pa));
69 }
70
71 struct bfa_ioc_regs {
72 void __iomem *hfn_mbox_cmd;
73 void __iomem *hfn_mbox;
74 void __iomem *lpu_mbox_cmd;
75 void __iomem *lpu_mbox;
76 void __iomem *pss_ctl_reg;
77 void __iomem *pss_err_status_reg;
78 void __iomem *app_pll_fast_ctl_reg;
79 void __iomem *app_pll_slow_ctl_reg;
80 void __iomem *ioc_sem_reg;
81 void __iomem *ioc_usage_sem_reg;
82 void __iomem *ioc_init_sem_reg;
83 void __iomem *ioc_usage_reg;
84 void __iomem *host_page_num_fn;
85 void __iomem *heartbeat;
86 void __iomem *ioc_fwstate;
87 void __iomem *alt_ioc_fwstate;
88 void __iomem *ll_halt;
89 void __iomem *alt_ll_halt;
90 void __iomem *err_set;
91 void __iomem *ioc_fail_sync;
92 void __iomem *shirq_isr_next;
93 void __iomem *shirq_msk_next;
94 void __iomem *smem_page_start;
95 u32 smem_pg0;
96 };
97
98 /**
99 * IOC Mailbox structures
100 */
101 typedef void (*bfa_mbox_cmd_cbfn_t)(void *cbarg);
102 struct bfa_mbox_cmd {
103 struct list_head qe;
104 bfa_mbox_cmd_cbfn_t cbfn;
105 void *cbarg;
106 u32 msg[BFI_IOC_MSGSZ];
107 };
108
109 /**
110 * IOC mailbox module
111 */
112 typedef void (*bfa_ioc_mbox_mcfunc_t)(void *cbarg, struct bfi_mbmsg *m);
113 struct bfa_ioc_mbox_mod {
114 struct list_head cmd_q; /*!< pending mbox queue */
115 int nmclass; /*!< number of handlers */
116 struct {
117 bfa_ioc_mbox_mcfunc_t cbfn; /*!< message handlers */
118 void *cbarg;
119 } mbhdlr[BFI_MC_MAX];
120 };
121
122 /**
123 * IOC callback function interfaces
124 */
125 typedef void (*bfa_ioc_enable_cbfn_t)(void *bfa, enum bfa_status status);
126 typedef void (*bfa_ioc_disable_cbfn_t)(void *bfa);
127 typedef void (*bfa_ioc_hbfail_cbfn_t)(void *bfa);
128 typedef void (*bfa_ioc_reset_cbfn_t)(void *bfa);
129 struct bfa_ioc_cbfn {
130 bfa_ioc_enable_cbfn_t enable_cbfn;
131 bfa_ioc_disable_cbfn_t disable_cbfn;
132 bfa_ioc_hbfail_cbfn_t hbfail_cbfn;
133 bfa_ioc_reset_cbfn_t reset_cbfn;
134 };
135
136 /**
137 * IOC event notification mechanism.
138 */
139 enum bfa_ioc_event {
140 BFA_IOC_E_ENABLED = 1,
141 BFA_IOC_E_DISABLED = 2,
142 BFA_IOC_E_FAILED = 3,
143 };
144
145 typedef void (*bfa_ioc_notify_cbfn_t)(void *, enum bfa_ioc_event);
146
147 struct bfa_ioc_notify {
148 struct list_head qe;
149 bfa_ioc_notify_cbfn_t cbfn;
150 void *cbarg;
151 };
152
153 /**
154 * Heartbeat failure notification queue element.
155 */
156 struct bfa_ioc_hbfail_notify {
157 struct list_head qe;
158 bfa_ioc_hbfail_cbfn_t cbfn;
159 void *cbarg;
160 };
161
162 /**
163 * Initialize a heartbeat failure notification structure
164 */
165 #define bfa_ioc_notify_init(__notify, __cbfn, __cbarg) do { \
166 (__notify)->cbfn = (__cbfn); \
167 (__notify)->cbarg = (__cbarg); \
168 } while (0)
169
170 struct bfa_iocpf {
171 bfa_fsm_t fsm;
172 struct bfa_ioc *ioc;
173 bool fw_mismatch_notified;
174 bool auto_recover;
175 u32 poll_time;
176 };
177
178 struct bfa_ioc {
179 bfa_fsm_t fsm;
180 struct bfa *bfa;
181 struct bfa_pcidev pcidev;
182 struct timer_list ioc_timer;
183 struct timer_list iocpf_timer;
184 struct timer_list sem_timer;
185 struct timer_list hb_timer;
186 u32 hb_count;
187 struct list_head notify_q;
188 void *dbg_fwsave;
189 int dbg_fwsave_len;
190 bool dbg_fwsave_once;
191 enum bfi_pcifn_class clscode;
192 struct bfa_ioc_regs ioc_regs;
193 struct bfa_ioc_drv_stats stats;
194 bool fcmode;
195 bool pllinit;
196 bool stats_busy; /*!< outstanding stats */
197 u8 port_id;
198
199 struct bfa_dma attr_dma;
200 struct bfi_ioc_attr *attr;
201 struct bfa_ioc_cbfn *cbfn;
202 struct bfa_ioc_mbox_mod mbox_mod;
203 struct bfa_ioc_hwif *ioc_hwif;
204 struct bfa_iocpf iocpf;
205 enum bfi_asic_gen asic_gen;
206 enum bfi_asic_mode asic_mode;
207 enum bfi_port_mode port0_mode;
208 enum bfi_port_mode port1_mode;
209 enum bfa_mode port_mode;
210 u8 ad_cap_bm; /*!< adapter cap bit mask */
211 u8 port_mode_cfg; /*!< config port mode */
212 };
213
214 struct bfa_ioc_hwif {
215 enum bfa_status (*ioc_pll_init) (void __iomem *rb,
216 enum bfi_asic_mode m);
217 bool (*ioc_firmware_lock) (struct bfa_ioc *ioc);
218 void (*ioc_firmware_unlock) (struct bfa_ioc *ioc);
219 void (*ioc_reg_init) (struct bfa_ioc *ioc);
220 void (*ioc_map_port) (struct bfa_ioc *ioc);
221 void (*ioc_isr_mode_set) (struct bfa_ioc *ioc,
222 bool msix);
223 void (*ioc_notify_fail) (struct bfa_ioc *ioc);
224 void (*ioc_ownership_reset) (struct bfa_ioc *ioc);
225 bool (*ioc_sync_start) (struct bfa_ioc *ioc);
226 void (*ioc_sync_join) (struct bfa_ioc *ioc);
227 void (*ioc_sync_leave) (struct bfa_ioc *ioc);
228 void (*ioc_sync_ack) (struct bfa_ioc *ioc);
229 bool (*ioc_sync_complete) (struct bfa_ioc *ioc);
230 bool (*ioc_lpu_read_stat) (struct bfa_ioc *ioc);
231 };
232
233 #define bfa_ioc_pcifn(__ioc) ((__ioc)->pcidev.pci_func)
234 #define bfa_ioc_devid(__ioc) ((__ioc)->pcidev.device_id)
235 #define bfa_ioc_bar0(__ioc) ((__ioc)->pcidev.pci_bar_kva)
236 #define bfa_ioc_portid(__ioc) ((__ioc)->port_id)
237 #define bfa_ioc_asic_gen(__ioc) ((__ioc)->asic_gen)
238 #define bfa_ioc_fetch_stats(__ioc, __stats) \
239 (((__stats)->drv_stats) = (__ioc)->stats)
240 #define bfa_ioc_clr_stats(__ioc) \
241 memset(&(__ioc)->stats, 0, sizeof((__ioc)->stats))
242 #define bfa_ioc_maxfrsize(__ioc) ((__ioc)->attr->maxfrsize)
243 #define bfa_ioc_rx_bbcredit(__ioc) ((__ioc)->attr->rx_bbcredit)
244 #define bfa_ioc_speed_sup(__ioc) \
245 BFI_ADAPTER_GETP(SPEED, (__ioc)->attr->adapter_prop)
246 #define bfa_ioc_get_nports(__ioc) \
247 BFI_ADAPTER_GETP(NPORTS, (__ioc)->attr->adapter_prop)
248
249 #define bfa_ioc_stats(_ioc, _stats) ((_ioc)->stats._stats++)
250 #define bfa_ioc_stats_hb_count(_ioc, _hb_count) \
251 ((_ioc)->stats.hb_count = (_hb_count))
252 #define BFA_IOC_FWIMG_MINSZ (16 * 1024)
253 #define BFA_IOC_FWIMG_TYPE(__ioc) \
254 (((__ioc)->ctdev) ? \
255 (((__ioc)->fcmode) ? BFI_IMAGE_CT_FC : BFI_IMAGE_CT_CNA) : \
256 BFI_IMAGE_CB_FC)
257 #define BFA_IOC_FW_SMEM_SIZE(__ioc) \
258 ((bfa_ioc_asic_gen(__ioc) == BFI_ASIC_GEN_CB) \
259 ? BFI_SMEM_CB_SIZE : BFI_SMEM_CT_SIZE)
260 #define BFA_IOC_FLASH_CHUNK_NO(off) (off / BFI_FLASH_CHUNK_SZ_WORDS)
261 #define BFA_IOC_FLASH_OFFSET_IN_CHUNK(off) (off % BFI_FLASH_CHUNK_SZ_WORDS)
262 #define BFA_IOC_FLASH_CHUNK_ADDR(chunkno) (chunkno * BFI_FLASH_CHUNK_SZ_WORDS)
263
264 /**
265 * IOC mailbox interface
266 */
267 bool bfa_nw_ioc_mbox_queue(struct bfa_ioc *ioc,
268 struct bfa_mbox_cmd *cmd,
269 bfa_mbox_cmd_cbfn_t cbfn, void *cbarg);
270 void bfa_nw_ioc_mbox_isr(struct bfa_ioc *ioc);
271 void bfa_nw_ioc_mbox_regisr(struct bfa_ioc *ioc, enum bfi_mclass mc,
272 bfa_ioc_mbox_mcfunc_t cbfn, void *cbarg);
273
274 /**
275 * IOC interfaces
276 */
277
278 #define bfa_ioc_pll_init_asic(__ioc) \
279 ((__ioc)->ioc_hwif->ioc_pll_init((__ioc)->pcidev.pci_bar_kva, \
280 (__ioc)->asic_mode))
281
282 #define bfa_ioc_isr_mode_set(__ioc, __msix) \
283 ((__ioc)->ioc_hwif->ioc_isr_mode_set(__ioc, __msix))
284 #define bfa_ioc_ownership_reset(__ioc) \
285 ((__ioc)->ioc_hwif->ioc_ownership_reset(__ioc))
286
287 #define bfa_ioc_lpu_read_stat(__ioc) do { \
288 if ((__ioc)->ioc_hwif->ioc_lpu_read_stat) \
289 ((__ioc)->ioc_hwif->ioc_lpu_read_stat(__ioc)); \
290 } while (0)
291
292 void bfa_nw_ioc_set_ct_hwif(struct bfa_ioc *ioc);
293
294 void bfa_nw_ioc_attach(struct bfa_ioc *ioc, void *bfa,
295 struct bfa_ioc_cbfn *cbfn);
296 void bfa_nw_ioc_auto_recover(bool auto_recover);
297 void bfa_nw_ioc_detach(struct bfa_ioc *ioc);
298 void bfa_nw_ioc_pci_init(struct bfa_ioc *ioc, struct bfa_pcidev *pcidev,
299 enum bfi_pcifn_class clscode);
300 u32 bfa_nw_ioc_meminfo(void);
301 void bfa_nw_ioc_mem_claim(struct bfa_ioc *ioc, u8 *dm_kva, u64 dm_pa);
302 void bfa_nw_ioc_enable(struct bfa_ioc *ioc);
303 void bfa_nw_ioc_disable(struct bfa_ioc *ioc);
304
305 void bfa_nw_ioc_error_isr(struct bfa_ioc *ioc);
306 bool bfa_nw_ioc_is_disabled(struct bfa_ioc *ioc);
307 void bfa_nw_ioc_get_attr(struct bfa_ioc *ioc, struct bfa_ioc_attr *ioc_attr);
308 void bfa_nw_ioc_notify_register(struct bfa_ioc *ioc,
309 struct bfa_ioc_notify *notify);
310 bool bfa_nw_ioc_sem_get(void __iomem *sem_reg);
311 void bfa_nw_ioc_sem_release(void __iomem *sem_reg);
312 void bfa_nw_ioc_hw_sem_release(struct bfa_ioc *ioc);
313 void bfa_nw_ioc_fwver_get(struct bfa_ioc *ioc,
314 struct bfi_ioc_image_hdr *fwhdr);
315 bool bfa_nw_ioc_fwver_cmp(struct bfa_ioc *ioc,
316 struct bfi_ioc_image_hdr *fwhdr);
317 mac_t bfa_nw_ioc_get_mac(struct bfa_ioc *ioc);
318
319 /*
320 * Timeout APIs
321 */
322 void bfa_nw_ioc_timeout(void *ioc);
323 void bfa_nw_ioc_hb_check(void *ioc);
324 void bfa_nw_iocpf_timeout(void *ioc);
325 void bfa_nw_iocpf_sem_timeout(void *ioc);
326
327 /*
328 * F/W Image Size & Chunk
329 */
330 u32 *bfa_cb_image_get_chunk(enum bfi_asic_gen asic_gen, u32 off);
331 u32 bfa_cb_image_get_size(enum bfi_asic_gen asic_gen);
332
333 #endif /* __BFA_IOC_H__ */
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