drivers/net/ethernet/brocade/bna/bfi.h

   1 /*
   2  * Linux network driver for QLogic BR-series Converged Network Adapter.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License (GPL) Version 2 as
   6  * published by the Free Software Foundation
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  */
  13 /*
  14  * Copyright (c) 2005-2014 Brocade Communications Systems, Inc.
  15  * Copyright (c) 2014-2015 QLogic Corporation
  16  * All rights reserved
  17  * www.qlogic.com
  18  */
  19 #ifndef __BFI_H__
  20 #define __BFI_H__
  21
  22 #include "bfa_defs.h"
  23
  24 /* BFI FW image type */
  25 #define BFI_FLASH_CHUNK_SZ                      256     /*!< Flash chunk size */
  26 #define BFI_FLASH_CHUNK_SZ_WORDS        (BFI_FLASH_CHUNK_SZ/sizeof(u32))
  27 #define BFI_FLASH_IMAGE_SZ              0x100000
  28
  29 /* Msg header common to all msgs */
  30 struct bfi_mhdr {
  31         u8              msg_class;      /*!< @ref enum bfi_mclass           */
  32         u8              msg_id;         /*!< msg opcode with in the class   */
  33         union {
  34                 struct {
  35                         u8      qid;
  36                         u8      fn_lpu; /*!< msg destination                */
  37                 } __packed h2i;
  38                 u16     i2htok; /*!< token in msgs to host          */
  39         } __packed mtag;
  40 } __packed;
  41
  42 #define bfi_fn_lpu(__fn, __lpu) ((__fn) << 1 | (__lpu))
  43 #define bfi_mhdr_2_fn(_mh)      ((_mh)->mtag.h2i.fn_lpu >> 1)
  44 #define bfi_mhdr_2_qid(_mh)     ((_mh)->mtag.h2i.qid)
  45
  46 #define bfi_h2i_set(_mh, _mc, _op, _fn_lpu) do {                \
  47         (_mh).msg_class                 = (_mc);                \
  48         (_mh).msg_id                    = (_op);                \
  49         (_mh).mtag.h2i.fn_lpu   = (_fn_lpu);                    \
  50 } while (0)
  51
  52 #define bfi_i2h_set(_mh, _mc, _op, _i2htok) do {                \
  53         (_mh).msg_class                 = (_mc);                \
  54         (_mh).msg_id                    = (_op);                \
  55         (_mh).mtag.i2htok               = (_i2htok);            \
  56 } while (0)
  57
  58 /*
  59  * Message opcodes: 0-127 to firmware, 128-255 to host
  60  */
  61 #define BFI_I2H_OPCODE_BASE     128
  62 #define BFA_I2HM(_x)                    ((_x) + BFI_I2H_OPCODE_BASE)
  63
  64 /****************************************************************************
  65  *
  66  * Scatter Gather Element and Page definition
  67  *
  68  ****************************************************************************
  69  */
  70
  71 /* DMA addresses */
  72 union bfi_addr_u {
  73         struct {
  74                 u32     addr_lo;
  75                 u32     addr_hi;
  76         } __packed a32;
  77 } __packed;
  78
  79 /* Generic DMA addr-len pair. */
  80 struct bfi_alen {
  81         union bfi_addr_u        al_addr;        /* DMA addr of buffer   */
  82         u32                     al_len;         /* length of buffer */
  83 } __packed;
  84
  85 /*
  86  * Large Message structure - 128 Bytes size Msgs
  87  */
  88 #define BFI_LMSG_SZ             128
  89 #define BFI_LMSG_PL_WSZ \
  90                         ((BFI_LMSG_SZ - sizeof(struct bfi_mhdr)) / 4)
  91
  92 /* Mailbox message structure */
  93 #define BFI_MBMSG_SZ            7
  94 struct bfi_mbmsg {
  95         struct bfi_mhdr mh;
  96         u32             pl[BFI_MBMSG_SZ];
  97 } __packed;
  98
  99 /* Supported PCI function class codes (personality) */
 100 enum bfi_pcifn_class {
 101         BFI_PCIFN_CLASS_FC      = 0x0c04,
 102         BFI_PCIFN_CLASS_ETH     = 0x0200,
 103 };
 104
 105 /* Message Classes */
 106 enum bfi_mclass {
 107         BFI_MC_IOC              = 1,    /*!< IO Controller (IOC)            */
 108         BFI_MC_DIAG             = 2,    /*!< Diagnostic Msgs                */
 109         BFI_MC_FLASH            = 3,    /*!< Flash message class            */
 110         BFI_MC_CEE              = 4,    /*!< CEE                            */
 111         BFI_MC_FCPORT           = 5,    /*!< FC port                        */
 112         BFI_MC_IOCFC            = 6,    /*!< FC - IO Controller (IOC)       */
 113         BFI_MC_LL               = 7,    /*!< Link Layer                     */
 114         BFI_MC_UF               = 8,    /*!< Unsolicited frame receive      */
 115         BFI_MC_FCXP             = 9,    /*!< FC Transport                   */
 116         BFI_MC_LPS              = 10,   /*!< lport fc login services        */
 117         BFI_MC_RPORT            = 11,   /*!< Remote port                    */
 118         BFI_MC_ITNIM            = 12,   /*!< I-T nexus (Initiator mode)     */
 119         BFI_MC_IOIM_READ        = 13,   /*!< read IO (Initiator mode)       */
 120         BFI_MC_IOIM_WRITE       = 14,   /*!< write IO (Initiator mode)      */
 121         BFI_MC_IOIM_IO          = 15,   /*!< IO (Initiator mode)            */
 122         BFI_MC_IOIM             = 16,   /*!< IO (Initiator mode)            */
 123         BFI_MC_IOIM_IOCOM       = 17,   /*!< good IO completion             */
 124         BFI_MC_TSKIM            = 18,   /*!< Initiator Task management      */
 125         BFI_MC_SBOOT            = 19,   /*!< SAN boot services              */
 126         BFI_MC_IPFC             = 20,   /*!< IP over FC Msgs                */
 127         BFI_MC_PORT             = 21,   /*!< Physical port                  */
 128         BFI_MC_SFP              = 22,   /*!< SFP module                     */
 129         BFI_MC_MSGQ             = 23,   /*!< MSGQ                           */
 130         BFI_MC_ENET             = 24,   /*!< ENET commands/responses        */
 131         BFI_MC_PHY              = 25,   /*!< External PHY message class     */
 132         BFI_MC_NBOOT            = 26,   /*!< Network Boot                   */
 133         BFI_MC_TIO_READ         = 27,   /*!< read IO (Target mode)          */
 134         BFI_MC_TIO_WRITE        = 28,   /*!< write IO (Target mode)         */
 135         BFI_MC_TIO_DATA_XFERED  = 29,   /*!< ds transferred (target mode)   */
 136         BFI_MC_TIO_IO           = 30,   /*!< IO (Target mode)               */
 137         BFI_MC_TIO              = 31,   /*!< IO (target mode)               */
 138         BFI_MC_MFG              = 32,   /*!< MFG/ASIC block commands        */
 139         BFI_MC_EDMA             = 33,   /*!< EDMA copy commands             */
 140         BFI_MC_MAX              = 34
 141 };
 142
 143 #define BFI_IOC_MSGLEN_MAX      32      /* 32 bytes */
 144
 145 #define BFI_FWBOOT_ENV_OS               0
 146
 147 /*----------------------------------------------------------------------
 148  *                              IOC
 149  *----------------------------------------------------------------------
 150  */
 151
 152 /* Different asic generations */
 153 enum bfi_asic_gen {
 154         BFI_ASIC_GEN_CB         = 1,
 155         BFI_ASIC_GEN_CT         = 2,
 156         BFI_ASIC_GEN_CT2        = 3,
 157 };
 158
 159 enum bfi_asic_mode {
 160         BFI_ASIC_MODE_FC        = 1,    /* FC up to 8G speed            */
 161         BFI_ASIC_MODE_FC16      = 2,    /* FC up to 16G speed           */
 162         BFI_ASIC_MODE_ETH       = 3,    /* Ethernet ports               */
 163         BFI_ASIC_MODE_COMBO     = 4,    /* FC 16G and Ethernet 10G port */
 164 };
 165
 166 enum bfi_ioc_h2i_msgs {
 167         BFI_IOC_H2I_ENABLE_REQ          = 1,
 168         BFI_IOC_H2I_DISABLE_REQ         = 2,
 169         BFI_IOC_H2I_GETATTR_REQ         = 3,
 170         BFI_IOC_H2I_DBG_SYNC            = 4,
 171         BFI_IOC_H2I_DBG_DUMP            = 5,
 172 };
 173
 174 enum bfi_ioc_i2h_msgs {
 175         BFI_IOC_I2H_ENABLE_REPLY        = BFA_I2HM(1),
 176         BFI_IOC_I2H_DISABLE_REPLY       = BFA_I2HM(2),
 177         BFI_IOC_I2H_GETATTR_REPLY       = BFA_I2HM(3),
 178         BFI_IOC_I2H_HBEAT               = BFA_I2HM(4),
 179 };
 180
 181 /* BFI_IOC_H2I_GETATTR_REQ message */
 182 struct bfi_ioc_getattr_req {
 183         struct bfi_mhdr mh;
 184         union bfi_addr_u        attr_addr;
 185 } __packed;
 186
 187 struct bfi_ioc_attr {
 188         u64             mfg_pwwn;       /*!< Mfg port wwn          */
 189         u64             mfg_nwwn;       /*!< Mfg node wwn          */
 190         u8              mfg_mac[ETH_ALEN]; /*!< Mfg mac            */
 191         u8              port_mode;      /* enum bfi_port_mode      */
 192         u8              rsvd_a;
 193         u64             pwwn;
 194         u64             nwwn;
 195         u8              mac[ETH_ALEN];  /*!< PBC or Mfg mac        */
 196         u16     rsvd_b;
 197         u8              fcoe_mac[ETH_ALEN];
 198         u16     rsvd_c;
 199         char            brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
 200         u8              pcie_gen;
 201         u8              pcie_lanes_orig;
 202         u8              pcie_lanes;
 203         u8              rx_bbcredit;    /*!< receive buffer credits */
 204         u32     adapter_prop;   /*!< adapter properties     */
 205         u16     maxfrsize;      /*!< max receive frame size */
 206         char            asic_rev;
 207         u8              rsvd_d;
 208         char            fw_version[BFA_VERSION_LEN];
 209         char            optrom_version[BFA_VERSION_LEN];
 210         struct bfa_mfg_vpd vpd;
 211         u32     card_type;      /*!< card type                  */
 212 } __packed;
 213
 214 /* BFI_IOC_I2H_GETATTR_REPLY message */
 215 struct bfi_ioc_getattr_reply {
 216         struct bfi_mhdr mh;     /*!< Common msg header          */
 217         u8                      status; /*!< cfg reply status           */
 218         u8                      rsvd[3];
 219 } __packed;
 220
 221 /* Firmware memory page offsets */
 222 #define BFI_IOC_SMEM_PG0_CB     (0x40)
 223 #define BFI_IOC_SMEM_PG0_CT     (0x180)
 224
 225 /* Firmware statistic offset */
 226 #define BFI_IOC_FWSTATS_OFF     (0x6B40)
 227 #define BFI_IOC_FWSTATS_SZ      (4096)
 228
 229 /* Firmware trace offset */
 230 #define BFI_IOC_TRC_OFF         (0x4b00)
 231 #define BFI_IOC_TRC_ENTS        256
 232 #define BFI_IOC_TRC_ENT_SZ      16
 233 #define BFI_IOC_TRC_HDR_SZ      32
 234
 235 #define BFI_IOC_FW_SIGNATURE    (0xbfadbfad)
 236 #define BFI_IOC_FW_INV_SIGN     (0xdeaddead)
 237 #define BFI_IOC_MD5SUM_SZ       4
 238
 239 struct bfi_ioc_fwver {
 240 #ifdef __BIG_ENDIAN
 241         u8 patch;
 242         u8 maint;
 243         u8 minor;
 244         u8 major;
 245         u8 rsvd[2];
 246         u8 build;
 247         u8 phase;
 248 #else
 249         u8 major;
 250         u8 minor;
 251         u8 maint;
 252         u8 patch;
 253         u8 phase;
 254         u8 build;
 255         u8 rsvd[2];
 256 #endif
 257 } __packed;
 258
 259 struct bfi_ioc_image_hdr {
 260         u32     signature;      /*!< constant signature */
 261         u8      asic_gen;       /*!< asic generation */
 262         u8      asic_mode;
 263         u8      port0_mode;     /*!< device mode for port 0 */
 264         u8      port1_mode;     /*!< device mode for port 1 */
 265         u32     exec;           /*!< exec vector        */
 266         u32     bootenv;        /*!< firmware boot env */
 267         u32     rsvd_b[2];
 268         struct bfi_ioc_fwver fwver;
 269         u32     md5sum[BFI_IOC_MD5SUM_SZ];
 270 } __packed;
 271
 272 enum bfi_ioc_img_ver_cmp {
 273         BFI_IOC_IMG_VER_INCOMP,
 274         BFI_IOC_IMG_VER_OLD,
 275         BFI_IOC_IMG_VER_SAME,
 276         BFI_IOC_IMG_VER_BETTER
 277 };
 278
 279 #define BFI_FWBOOT_DEVMODE_OFF          4
 280 #define BFI_FWBOOT_TYPE_OFF             8
 281 #define BFI_FWBOOT_ENV_OFF              12
 282 #define BFI_FWBOOT_DEVMODE(__asic_gen, __asic_mode, __p0_mode, __p1_mode) \
 283         (((u32)(__asic_gen)) << 24 |    \
 284          ((u32)(__asic_mode)) << 16 |   \
 285          ((u32)(__p0_mode)) << 8 |      \
 286          ((u32)(__p1_mode)))
 287
 288 enum bfi_fwboot_type {
 289         BFI_FWBOOT_TYPE_NORMAL  = 0,
 290         BFI_FWBOOT_TYPE_FLASH   = 1,
 291         BFI_FWBOOT_TYPE_MEMTEST = 2,
 292 };
 293
 294 enum bfi_port_mode {
 295         BFI_PORT_MODE_FC        = 1,
 296         BFI_PORT_MODE_ETH       = 2,
 297 };
 298
 299 struct bfi_ioc_hbeat {
 300         struct bfi_mhdr mh;             /*!< common msg header          */
 301         u32        hb_count;    /*!< current heart beat count   */
 302 } __packed;
 303
 304 /* IOC hardware/firmware state */
 305 enum bfi_ioc_state {
 306         BFI_IOC_UNINIT          = 0,    /*!< not initialized                 */
 307         BFI_IOC_INITING         = 1,    /*!< h/w is being initialized        */
 308         BFI_IOC_HWINIT          = 2,    /*!< h/w is initialized              */
 309         BFI_IOC_CFG             = 3,    /*!< IOC configuration in progress   */
 310         BFI_IOC_OP              = 4,    /*!< IOC is operational              */
 311         BFI_IOC_DISABLING       = 5,    /*!< IOC is being disabled           */
 312         BFI_IOC_DISABLED        = 6,    /*!< IOC is disabled                 */
 313         BFI_IOC_CFG_DISABLED    = 7,    /*!< IOC is being disabled;transient */
 314         BFI_IOC_FAIL            = 8,    /*!< IOC heart-beat failure          */
 315         BFI_IOC_MEMTEST         = 9,    /*!< IOC is doing memtest            */
 316 };
 317
 318 enum {
 319         BFI_ADAPTER_TYPE_FC     = 0x01,         /*!< FC adapters           */
 320         BFI_ADAPTER_TYPE_MK     = 0x0f0000,     /*!< adapter type mask     */
 321         BFI_ADAPTER_TYPE_SH     = 16,           /*!< adapter type shift    */
 322         BFI_ADAPTER_NPORTS_MK   = 0xff00,       /*!< number of ports mask  */
 323         BFI_ADAPTER_NPORTS_SH   = 8,            /*!< number of ports shift */
 324         BFI_ADAPTER_SPEED_MK    = 0xff,         /*!< adapter speed mask    */
 325         BFI_ADAPTER_SPEED_SH    = 0,            /*!< adapter speed shift   */
 326         BFI_ADAPTER_PROTO       = 0x100000,     /*!< prototype adapaters   */
 327         BFI_ADAPTER_TTV         = 0x200000,     /*!< TTV debug capable     */
 328         BFI_ADAPTER_UNSUPP      = 0x400000,     /*!< unknown adapter type  */
 329 };
 330
 331 #define BFI_ADAPTER_GETP(__prop, __adap_prop)                   \
 332         (((__adap_prop) & BFI_ADAPTER_ ## __prop ## _MK) >>     \
 333                 BFI_ADAPTER_ ## __prop ## _SH)
 334 #define BFI_ADAPTER_SETP(__prop, __val)                         \
 335         ((__val) << BFI_ADAPTER_ ## __prop ## _SH)
 336 #define BFI_ADAPTER_IS_SPECIAL(__adap_type)                     \
 337         ((__adap_type) & (BFI_ADAPTER_TTV | BFI_ADAPTER_PROTO | \
 338                         BFI_ADAPTER_UNSUPP))
 339
 340 /* BFI_IOC_H2I_ENABLE_REQ & BFI_IOC_H2I_DISABLE_REQ messages */
 341 struct bfi_ioc_ctrl_req {
 342         struct bfi_mhdr mh;
 343         u16                     clscode;
 344         u16                     rsvd;
 345         u32             tv_sec;
 346 } __packed;
 347
 348 /* BFI_IOC_I2H_ENABLE_REPLY & BFI_IOC_I2H_DISABLE_REPLY messages */
 349 struct bfi_ioc_ctrl_reply {
 350         struct bfi_mhdr mh;                     /*!< Common msg header     */
 351         u8                      status;         /*!< enable/disable status */
 352         u8                      port_mode;      /*!< enum bfa_mode */
 353         u8                      cap_bm;         /*!< capability bit mask */
 354         u8                      rsvd;
 355 } __packed;
 356
 357 #define BFI_IOC_MSGSZ   8
 358 /* H2I Messages */
 359 union bfi_ioc_h2i_msg_u {
 360         struct bfi_mhdr mh;
 361         struct bfi_ioc_ctrl_req enable_req;
 362         struct bfi_ioc_ctrl_req disable_req;
 363         struct bfi_ioc_getattr_req getattr_req;
 364         u32                     mboxmsg[BFI_IOC_MSGSZ];
 365 } __packed;
 366
 367 /* I2H Messages */
 368 union bfi_ioc_i2h_msg_u {
 369         struct bfi_mhdr mh;
 370         struct bfi_ioc_ctrl_reply fw_event;
 371         u32                     mboxmsg[BFI_IOC_MSGSZ];
 372 } __packed;
 373
 374 /*----------------------------------------------------------------------
 375  *                              MSGQ
 376  *----------------------------------------------------------------------
 377  */
 378
 379 enum bfi_msgq_h2i_msgs {
 380         BFI_MSGQ_H2I_INIT_REQ      = 1,
 381         BFI_MSGQ_H2I_DOORBELL_PI        = 2,
 382         BFI_MSGQ_H2I_DOORBELL_CI        = 3,
 383         BFI_MSGQ_H2I_CMDQ_COPY_RSP      = 4,
 384 };
 385
 386 enum bfi_msgq_i2h_msgs {
 387         BFI_MSGQ_I2H_INIT_RSP      = BFA_I2HM(BFI_MSGQ_H2I_INIT_REQ),
 388         BFI_MSGQ_I2H_DOORBELL_PI        = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_PI),
 389         BFI_MSGQ_I2H_DOORBELL_CI        = BFA_I2HM(BFI_MSGQ_H2I_DOORBELL_CI),
 390         BFI_MSGQ_I2H_CMDQ_COPY_REQ      = BFA_I2HM(BFI_MSGQ_H2I_CMDQ_COPY_RSP),
 391 };
 392
 393 /* Messages(commands/responsed/AENS will have the following header */
 394 struct bfi_msgq_mhdr {
 395         u8      msg_class;
 396         u8      msg_id;
 397         u16     msg_token;
 398         u16     num_entries;
 399         u8      enet_id;
 400         u8      rsvd[1];
 401 } __packed;
 402
 403 #define bfi_msgq_mhdr_set(_mh, _mc, _mid, _tok, _enet_id) do {  \
 404         (_mh).msg_class  = (_mc);       \
 405         (_mh).msg_id        = (_mid);       \
 406         (_mh).msg_token  = (_tok);       \
 407         (_mh).enet_id      = (_enet_id);   \
 408 } while (0)
 409
 410 /*
 411  * Mailbox  for messaging interface
 412  */
 413 #define BFI_MSGQ_CMD_ENTRY_SIZE  (64)    /* TBD */
 414 #define BFI_MSGQ_RSP_ENTRY_SIZE  (64)    /* TBD */
 415
 416 #define bfi_msgq_num_cmd_entries(_size)                          \
 417         (((_size) + BFI_MSGQ_CMD_ENTRY_SIZE - 1) / BFI_MSGQ_CMD_ENTRY_SIZE)
 418
 419 struct bfi_msgq {
 420         union bfi_addr_u addr;
 421         u16 q_depth;     /* Total num of entries in the queue */
 422         u8 rsvd[2];
 423 } __packed;
 424
 425 /* BFI_ENET_MSGQ_CFG_REQ TBD init or cfg? */
 426 struct bfi_msgq_cfg_req {
 427         struct bfi_mhdr mh;
 428         struct bfi_msgq cmdq;
 429         struct bfi_msgq rspq;
 430 } __packed;
 431
 432 /* BFI_ENET_MSGQ_CFG_RSP */
 433 struct bfi_msgq_cfg_rsp {
 434         struct bfi_mhdr mh;
 435         u8 cmd_status;
 436         u8 rsvd[3];
 437 } __packed;
 438
 439 /* BFI_MSGQ_H2I_DOORBELL */
 440 struct bfi_msgq_h2i_db {
 441         struct bfi_mhdr mh;
 442         union {
 443                 u16 cmdq_pi;
 444                 u16 rspq_ci;
 445         } __packed idx;
 446 } __packed;
 447
 448 /* BFI_MSGQ_I2H_DOORBELL */
 449 struct bfi_msgq_i2h_db {
 450         struct bfi_mhdr mh;
 451         union {
 452                 u16 rspq_pi;
 453                 u16 cmdq_ci;
 454         } __packed idx;
 455 } __packed;
 456
 457 #define BFI_CMD_COPY_SZ 28
 458
 459 /* BFI_MSGQ_H2I_CMD_COPY_RSP */
 460 struct bfi_msgq_h2i_cmdq_copy_rsp {
 461         struct bfi_mhdr mh;
 462         u8            data[BFI_CMD_COPY_SZ];
 463 } __packed;
 464
 465 /* BFI_MSGQ_I2H_CMD_COPY_REQ */
 466 struct bfi_msgq_i2h_cmdq_copy_req {
 467         struct bfi_mhdr mh;
 468         u16     offset;
 469         u16     len;
 470 } __packed;
 471
 472 /*
 473  *      FLASH module specific
 474  */
 475 enum bfi_flash_h2i_msgs {
 476         BFI_FLASH_H2I_QUERY_REQ = 1,
 477         BFI_FLASH_H2I_ERASE_REQ = 2,
 478         BFI_FLASH_H2I_WRITE_REQ = 3,
 479         BFI_FLASH_H2I_READ_REQ = 4,
 480         BFI_FLASH_H2I_BOOT_VER_REQ = 5,
 481 };
 482
 483 enum bfi_flash_i2h_msgs {
 484         BFI_FLASH_I2H_QUERY_RSP = BFA_I2HM(1),
 485         BFI_FLASH_I2H_ERASE_RSP = BFA_I2HM(2),
 486         BFI_FLASH_I2H_WRITE_RSP = BFA_I2HM(3),
 487         BFI_FLASH_I2H_READ_RSP = BFA_I2HM(4),
 488         BFI_FLASH_I2H_BOOT_VER_RSP = BFA_I2HM(5),
 489         BFI_FLASH_I2H_EVENT = BFA_I2HM(127),
 490 };
 491
 492 /*
 493  * Flash query request
 494  */
 495 struct bfi_flash_query_req {
 496         struct bfi_mhdr mh;   /* Common msg header */
 497         struct bfi_alen alen;
 498 } __packed;
 499
 500 /*
 501  * Flash write request
 502  */
 503 struct bfi_flash_write_req {
 504         struct bfi_mhdr mh;     /* Common msg header */
 505         struct bfi_alen alen;
 506         u32     type;   /* partition type */
 507         u8      instance; /* partition instance */
 508         u8      last;
 509         u8      rsv[2];
 510         u32     offset;
 511         u32     length;
 512 } __packed;
 513
 514 /*
 515  * Flash read request
 516  */
 517 struct bfi_flash_read_req {
 518         struct bfi_mhdr mh;     /* Common msg header */
 519         u32     type;           /* partition type */
 520         u8      instance;       /* partition instance */
 521         u8      rsv[3];
 522         u32     offset;
 523         u32     length;
 524         struct bfi_alen alen;
 525 } __packed;
 526
 527 /*
 528  * Flash query response
 529  */
 530 struct bfi_flash_query_rsp {
 531         struct bfi_mhdr mh;     /* Common msg header */
 532         u32     status;
 533 } __packed;
 534
 535 /*
 536  * Flash read response
 537  */
 538 struct bfi_flash_read_rsp {
 539         struct bfi_mhdr mh;     /* Common msg header */
 540         u32     type;           /* partition type */
 541         u8      instance;       /* partition instance */
 542         u8      rsv[3];
 543         u32     status;
 544         u32     length;
 545 } __packed;
 546
 547 /*
 548  * Flash write response
 549  */
 550 struct bfi_flash_write_rsp {
 551         struct bfi_mhdr mh;     /* Common msg header */
 552         u32     type;           /* partition type */
 553         u8      instance;       /* partition instance */
 554         u8      rsv[3];
 555         u32     status;
 556         u32     length;
 557 } __packed;
 558
 559 #endif /* __BFI_H__ */