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[deliverable/linux.git] / drivers / net / ethernet / cadence / macb.c
1 /*
2 * Cadence MACB/GEM Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
12 #include <linux/clk.h>
13 #include <linux/module.h>
14 #include <linux/moduleparam.h>
15 #include <linux/kernel.h>
16 #include <linux/types.h>
17 #include <linux/circ_buf.h>
18 #include <linux/slab.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
21 #include <linux/gpio.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_data/macb.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy.h>
29 #include <linux/of.h>
30 #include <linux/of_device.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
33
34 #include "macb.h"
35
36 #define MACB_RX_BUFFER_SIZE 128
37 #define RX_BUFFER_MULTIPLE 64 /* bytes */
38 #define RX_RING_SIZE 512 /* must be power of 2 */
39 #define RX_RING_BYTES (sizeof(struct macb_dma_desc) * RX_RING_SIZE)
40
41 #define TX_RING_SIZE 128 /* must be power of 2 */
42 #define TX_RING_BYTES (sizeof(struct macb_dma_desc) * TX_RING_SIZE)
43
44 /* level of occupied TX descriptors under which we wake up TX process */
45 #define MACB_TX_WAKEUP_THRESH (3 * TX_RING_SIZE / 4)
46
47 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(RXUBR) \
48 | MACB_BIT(ISR_ROVR))
49 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
50 | MACB_BIT(ISR_RLE) \
51 | MACB_BIT(TXERR))
52 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP))
53
54 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1))
55 #define GEM_MAX_TX_LEN ((unsigned int)((1 << GEM_TX_FRMLEN_SIZE) - 1))
56
57 /*
58 * Graceful stop timeouts in us. We should allow up to
59 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
60 */
61 #define MACB_HALT_TIMEOUT 1230
62
63 /* Ring buffer accessors */
64 static unsigned int macb_tx_ring_wrap(unsigned int index)
65 {
66 return index & (TX_RING_SIZE - 1);
67 }
68
69 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
70 unsigned int index)
71 {
72 return &queue->tx_ring[macb_tx_ring_wrap(index)];
73 }
74
75 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
76 unsigned int index)
77 {
78 return &queue->tx_skb[macb_tx_ring_wrap(index)];
79 }
80
81 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
82 {
83 dma_addr_t offset;
84
85 offset = macb_tx_ring_wrap(index) * sizeof(struct macb_dma_desc);
86
87 return queue->tx_ring_dma + offset;
88 }
89
90 static unsigned int macb_rx_ring_wrap(unsigned int index)
91 {
92 return index & (RX_RING_SIZE - 1);
93 }
94
95 static struct macb_dma_desc *macb_rx_desc(struct macb *bp, unsigned int index)
96 {
97 return &bp->rx_ring[macb_rx_ring_wrap(index)];
98 }
99
100 static void *macb_rx_buffer(struct macb *bp, unsigned int index)
101 {
102 return bp->rx_buffers + bp->rx_buffer_size * macb_rx_ring_wrap(index);
103 }
104
105 static void macb_set_hwaddr(struct macb *bp)
106 {
107 u32 bottom;
108 u16 top;
109
110 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
111 macb_or_gem_writel(bp, SA1B, bottom);
112 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
113 macb_or_gem_writel(bp, SA1T, top);
114
115 /* Clear unused address register sets */
116 macb_or_gem_writel(bp, SA2B, 0);
117 macb_or_gem_writel(bp, SA2T, 0);
118 macb_or_gem_writel(bp, SA3B, 0);
119 macb_or_gem_writel(bp, SA3T, 0);
120 macb_or_gem_writel(bp, SA4B, 0);
121 macb_or_gem_writel(bp, SA4T, 0);
122 }
123
124 static void macb_get_hwaddr(struct macb *bp)
125 {
126 struct macb_platform_data *pdata;
127 u32 bottom;
128 u16 top;
129 u8 addr[6];
130 int i;
131
132 pdata = dev_get_platdata(&bp->pdev->dev);
133
134 /* Check all 4 address register for vaild address */
135 for (i = 0; i < 4; i++) {
136 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
137 top = macb_or_gem_readl(bp, SA1T + i * 8);
138
139 if (pdata && pdata->rev_eth_addr) {
140 addr[5] = bottom & 0xff;
141 addr[4] = (bottom >> 8) & 0xff;
142 addr[3] = (bottom >> 16) & 0xff;
143 addr[2] = (bottom >> 24) & 0xff;
144 addr[1] = top & 0xff;
145 addr[0] = (top & 0xff00) >> 8;
146 } else {
147 addr[0] = bottom & 0xff;
148 addr[1] = (bottom >> 8) & 0xff;
149 addr[2] = (bottom >> 16) & 0xff;
150 addr[3] = (bottom >> 24) & 0xff;
151 addr[4] = top & 0xff;
152 addr[5] = (top >> 8) & 0xff;
153 }
154
155 if (is_valid_ether_addr(addr)) {
156 memcpy(bp->dev->dev_addr, addr, sizeof(addr));
157 return;
158 }
159 }
160
161 netdev_info(bp->dev, "invalid hw address, using random\n");
162 eth_hw_addr_random(bp->dev);
163 }
164
165 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
166 {
167 struct macb *bp = bus->priv;
168 int value;
169
170 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
171 | MACB_BF(RW, MACB_MAN_READ)
172 | MACB_BF(PHYA, mii_id)
173 | MACB_BF(REGA, regnum)
174 | MACB_BF(CODE, MACB_MAN_CODE)));
175
176 /* wait for end of transfer */
177 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
178 cpu_relax();
179
180 value = MACB_BFEXT(DATA, macb_readl(bp, MAN));
181
182 return value;
183 }
184
185 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
186 u16 value)
187 {
188 struct macb *bp = bus->priv;
189
190 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_SOF)
191 | MACB_BF(RW, MACB_MAN_WRITE)
192 | MACB_BF(PHYA, mii_id)
193 | MACB_BF(REGA, regnum)
194 | MACB_BF(CODE, MACB_MAN_CODE)
195 | MACB_BF(DATA, value)));
196
197 /* wait for end of transfer */
198 while (!MACB_BFEXT(IDLE, macb_readl(bp, NSR)))
199 cpu_relax();
200
201 return 0;
202 }
203
204 /**
205 * macb_set_tx_clk() - Set a clock to a new frequency
206 * @clk Pointer to the clock to change
207 * @rate New frequency in Hz
208 * @dev Pointer to the struct net_device
209 */
210 static void macb_set_tx_clk(struct clk *clk, int speed, struct net_device *dev)
211 {
212 long ferr, rate, rate_rounded;
213
214 if (!clk)
215 return;
216
217 switch (speed) {
218 case SPEED_10:
219 rate = 2500000;
220 break;
221 case SPEED_100:
222 rate = 25000000;
223 break;
224 case SPEED_1000:
225 rate = 125000000;
226 break;
227 default:
228 return;
229 }
230
231 rate_rounded = clk_round_rate(clk, rate);
232 if (rate_rounded < 0)
233 return;
234
235 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
236 * is not satisfied.
237 */
238 ferr = abs(rate_rounded - rate);
239 ferr = DIV_ROUND_UP(ferr, rate / 100000);
240 if (ferr > 5)
241 netdev_warn(dev, "unable to generate target frequency: %ld Hz\n",
242 rate);
243
244 if (clk_set_rate(clk, rate_rounded))
245 netdev_err(dev, "adjusting tx_clk failed.\n");
246 }
247
248 static void macb_handle_link_change(struct net_device *dev)
249 {
250 struct macb *bp = netdev_priv(dev);
251 struct phy_device *phydev = bp->phy_dev;
252 unsigned long flags;
253
254 int status_change = 0;
255
256 spin_lock_irqsave(&bp->lock, flags);
257
258 if (phydev->link) {
259 if ((bp->speed != phydev->speed) ||
260 (bp->duplex != phydev->duplex)) {
261 u32 reg;
262
263 reg = macb_readl(bp, NCFGR);
264 reg &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
265 if (macb_is_gem(bp))
266 reg &= ~GEM_BIT(GBE);
267
268 if (phydev->duplex)
269 reg |= MACB_BIT(FD);
270 if (phydev->speed == SPEED_100)
271 reg |= MACB_BIT(SPD);
272 if (phydev->speed == SPEED_1000 &&
273 bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
274 reg |= GEM_BIT(GBE);
275
276 macb_or_gem_writel(bp, NCFGR, reg);
277
278 bp->speed = phydev->speed;
279 bp->duplex = phydev->duplex;
280 status_change = 1;
281 }
282 }
283
284 if (phydev->link != bp->link) {
285 if (!phydev->link) {
286 bp->speed = 0;
287 bp->duplex = -1;
288 }
289 bp->link = phydev->link;
290
291 status_change = 1;
292 }
293
294 spin_unlock_irqrestore(&bp->lock, flags);
295
296 if (status_change) {
297 if (phydev->link) {
298 /* Update the TX clock rate if and only if the link is
299 * up and there has been a link change.
300 */
301 macb_set_tx_clk(bp->tx_clk, phydev->speed, dev);
302
303 netif_carrier_on(dev);
304 netdev_info(dev, "link up (%d/%s)\n",
305 phydev->speed,
306 phydev->duplex == DUPLEX_FULL ?
307 "Full" : "Half");
308 } else {
309 netif_carrier_off(dev);
310 netdev_info(dev, "link down\n");
311 }
312 }
313 }
314
315 /* based on au1000_eth. c*/
316 static int macb_mii_probe(struct net_device *dev)
317 {
318 struct macb *bp = netdev_priv(dev);
319 struct macb_platform_data *pdata;
320 struct phy_device *phydev;
321 int phy_irq;
322 int ret;
323
324 phydev = phy_find_first(bp->mii_bus);
325 if (!phydev) {
326 netdev_err(dev, "no PHY found\n");
327 return -ENXIO;
328 }
329
330 pdata = dev_get_platdata(&bp->pdev->dev);
331 if (pdata && gpio_is_valid(pdata->phy_irq_pin)) {
332 ret = devm_gpio_request(&bp->pdev->dev, pdata->phy_irq_pin, "phy int");
333 if (!ret) {
334 phy_irq = gpio_to_irq(pdata->phy_irq_pin);
335 phydev->irq = (phy_irq < 0) ? PHY_POLL : phy_irq;
336 }
337 }
338
339 /* attach the mac to the phy */
340 ret = phy_connect_direct(dev, phydev, &macb_handle_link_change,
341 bp->phy_interface);
342 if (ret) {
343 netdev_err(dev, "Could not attach to PHY\n");
344 return ret;
345 }
346
347 /* mask with MAC supported features */
348 if (macb_is_gem(bp) && bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)
349 phydev->supported &= PHY_GBIT_FEATURES;
350 else
351 phydev->supported &= PHY_BASIC_FEATURES;
352
353 phydev->advertising = phydev->supported;
354
355 bp->link = 0;
356 bp->speed = 0;
357 bp->duplex = -1;
358 bp->phy_dev = phydev;
359
360 return 0;
361 }
362
363 static int macb_mii_init(struct macb *bp)
364 {
365 struct macb_platform_data *pdata;
366 struct device_node *np;
367 int err = -ENXIO, i;
368
369 /* Enable management port */
370 macb_writel(bp, NCR, MACB_BIT(MPE));
371
372 bp->mii_bus = mdiobus_alloc();
373 if (bp->mii_bus == NULL) {
374 err = -ENOMEM;
375 goto err_out;
376 }
377
378 bp->mii_bus->name = "MACB_mii_bus";
379 bp->mii_bus->read = &macb_mdio_read;
380 bp->mii_bus->write = &macb_mdio_write;
381 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
382 bp->pdev->name, bp->pdev->id);
383 bp->mii_bus->priv = bp;
384 bp->mii_bus->parent = &bp->dev->dev;
385 pdata = dev_get_platdata(&bp->pdev->dev);
386
387 bp->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL);
388 if (!bp->mii_bus->irq) {
389 err = -ENOMEM;
390 goto err_out_free_mdiobus;
391 }
392
393 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
394
395 np = bp->pdev->dev.of_node;
396 if (np) {
397 /* try dt phy registration */
398 err = of_mdiobus_register(bp->mii_bus, np);
399
400 /* fallback to standard phy registration if no phy were
401 found during dt phy registration */
402 if (!err && !phy_find_first(bp->mii_bus)) {
403 for (i = 0; i < PHY_MAX_ADDR; i++) {
404 struct phy_device *phydev;
405
406 phydev = mdiobus_scan(bp->mii_bus, i);
407 if (IS_ERR(phydev)) {
408 err = PTR_ERR(phydev);
409 break;
410 }
411 }
412
413 if (err)
414 goto err_out_unregister_bus;
415 }
416 } else {
417 for (i = 0; i < PHY_MAX_ADDR; i++)
418 bp->mii_bus->irq[i] = PHY_POLL;
419
420 if (pdata)
421 bp->mii_bus->phy_mask = pdata->phy_mask;
422
423 err = mdiobus_register(bp->mii_bus);
424 }
425
426 if (err)
427 goto err_out_free_mdio_irq;
428
429 err = macb_mii_probe(bp->dev);
430 if (err)
431 goto err_out_unregister_bus;
432
433 return 0;
434
435 err_out_unregister_bus:
436 mdiobus_unregister(bp->mii_bus);
437 err_out_free_mdio_irq:
438 kfree(bp->mii_bus->irq);
439 err_out_free_mdiobus:
440 mdiobus_free(bp->mii_bus);
441 err_out:
442 return err;
443 }
444
445 static void macb_update_stats(struct macb *bp)
446 {
447 u32 __iomem *reg = bp->regs + MACB_PFR;
448 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
449 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
450
451 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
452
453 for(; p < end; p++, reg++)
454 *p += readl_relaxed(reg);
455 }
456
457 static int macb_halt_tx(struct macb *bp)
458 {
459 unsigned long halt_time, timeout;
460 u32 status;
461
462 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
463
464 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
465 do {
466 halt_time = jiffies;
467 status = macb_readl(bp, TSR);
468 if (!(status & MACB_BIT(TGO)))
469 return 0;
470
471 usleep_range(10, 250);
472 } while (time_before(halt_time, timeout));
473
474 return -ETIMEDOUT;
475 }
476
477 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb)
478 {
479 if (tx_skb->mapping) {
480 if (tx_skb->mapped_as_page)
481 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
482 tx_skb->size, DMA_TO_DEVICE);
483 else
484 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
485 tx_skb->size, DMA_TO_DEVICE);
486 tx_skb->mapping = 0;
487 }
488
489 if (tx_skb->skb) {
490 dev_kfree_skb_any(tx_skb->skb);
491 tx_skb->skb = NULL;
492 }
493 }
494
495 static void macb_tx_error_task(struct work_struct *work)
496 {
497 struct macb_queue *queue = container_of(work, struct macb_queue,
498 tx_error_task);
499 struct macb *bp = queue->bp;
500 struct macb_tx_skb *tx_skb;
501 struct macb_dma_desc *desc;
502 struct sk_buff *skb;
503 unsigned int tail;
504 unsigned long flags;
505
506 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
507 (unsigned int)(queue - bp->queues),
508 queue->tx_tail, queue->tx_head);
509
510 /* Prevent the queue IRQ handlers from running: each of them may call
511 * macb_tx_interrupt(), which in turn may call netif_wake_subqueue().
512 * As explained below, we have to halt the transmission before updating
513 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
514 * network engine about the macb/gem being halted.
515 */
516 spin_lock_irqsave(&bp->lock, flags);
517
518 /* Make sure nobody is trying to queue up new packets */
519 netif_tx_stop_all_queues(bp->dev);
520
521 /*
522 * Stop transmission now
523 * (in case we have just queued new packets)
524 * macb/gem must be halted to write TBQP register
525 */
526 if (macb_halt_tx(bp))
527 /* Just complain for now, reinitializing TX path can be good */
528 netdev_err(bp->dev, "BUG: halt tx timed out\n");
529
530 /*
531 * Treat frames in TX queue including the ones that caused the error.
532 * Free transmit buffers in upper layer.
533 */
534 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
535 u32 ctrl;
536
537 desc = macb_tx_desc(queue, tail);
538 ctrl = desc->ctrl;
539 tx_skb = macb_tx_skb(queue, tail);
540 skb = tx_skb->skb;
541
542 if (ctrl & MACB_BIT(TX_USED)) {
543 /* skb is set for the last buffer of the frame */
544 while (!skb) {
545 macb_tx_unmap(bp, tx_skb);
546 tail++;
547 tx_skb = macb_tx_skb(queue, tail);
548 skb = tx_skb->skb;
549 }
550
551 /* ctrl still refers to the first buffer descriptor
552 * since it's the only one written back by the hardware
553 */
554 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
555 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
556 macb_tx_ring_wrap(tail), skb->data);
557 bp->stats.tx_packets++;
558 bp->stats.tx_bytes += skb->len;
559 }
560 } else {
561 /*
562 * "Buffers exhausted mid-frame" errors may only happen
563 * if the driver is buggy, so complain loudly about those.
564 * Statistics are updated by hardware.
565 */
566 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
567 netdev_err(bp->dev,
568 "BUG: TX buffers exhausted mid-frame\n");
569
570 desc->ctrl = ctrl | MACB_BIT(TX_USED);
571 }
572
573 macb_tx_unmap(bp, tx_skb);
574 }
575
576 /* Set end of TX queue */
577 desc = macb_tx_desc(queue, 0);
578 desc->addr = 0;
579 desc->ctrl = MACB_BIT(TX_USED);
580
581 /* Make descriptor updates visible to hardware */
582 wmb();
583
584 /* Reinitialize the TX desc queue */
585 queue_writel(queue, TBQP, queue->tx_ring_dma);
586 /* Make TX ring reflect state of hardware */
587 queue->tx_head = 0;
588 queue->tx_tail = 0;
589
590 /* Housework before enabling TX IRQ */
591 macb_writel(bp, TSR, macb_readl(bp, TSR));
592 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
593
594 /* Now we are ready to start transmission again */
595 netif_tx_start_all_queues(bp->dev);
596 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
597
598 spin_unlock_irqrestore(&bp->lock, flags);
599 }
600
601 static void macb_tx_interrupt(struct macb_queue *queue)
602 {
603 unsigned int tail;
604 unsigned int head;
605 u32 status;
606 struct macb *bp = queue->bp;
607 u16 queue_index = queue - bp->queues;
608
609 status = macb_readl(bp, TSR);
610 macb_writel(bp, TSR, status);
611
612 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
613 queue_writel(queue, ISR, MACB_BIT(TCOMP));
614
615 netdev_vdbg(bp->dev, "macb_tx_interrupt status = 0x%03lx\n",
616 (unsigned long)status);
617
618 head = queue->tx_head;
619 for (tail = queue->tx_tail; tail != head; tail++) {
620 struct macb_tx_skb *tx_skb;
621 struct sk_buff *skb;
622 struct macb_dma_desc *desc;
623 u32 ctrl;
624
625 desc = macb_tx_desc(queue, tail);
626
627 /* Make hw descriptor updates visible to CPU */
628 rmb();
629
630 ctrl = desc->ctrl;
631
632 /* TX_USED bit is only set by hardware on the very first buffer
633 * descriptor of the transmitted frame.
634 */
635 if (!(ctrl & MACB_BIT(TX_USED)))
636 break;
637
638 /* Process all buffers of the current transmitted frame */
639 for (;; tail++) {
640 tx_skb = macb_tx_skb(queue, tail);
641 skb = tx_skb->skb;
642
643 /* First, update TX stats if needed */
644 if (skb) {
645 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
646 macb_tx_ring_wrap(tail), skb->data);
647 bp->stats.tx_packets++;
648 bp->stats.tx_bytes += skb->len;
649 }
650
651 /* Now we can safely release resources */
652 macb_tx_unmap(bp, tx_skb);
653
654 /* skb is set only for the last buffer of the frame.
655 * WARNING: at this point skb has been freed by
656 * macb_tx_unmap().
657 */
658 if (skb)
659 break;
660 }
661 }
662
663 queue->tx_tail = tail;
664 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
665 CIRC_CNT(queue->tx_head, queue->tx_tail,
666 TX_RING_SIZE) <= MACB_TX_WAKEUP_THRESH)
667 netif_wake_subqueue(bp->dev, queue_index);
668 }
669
670 static void gem_rx_refill(struct macb *bp)
671 {
672 unsigned int entry;
673 struct sk_buff *skb;
674 dma_addr_t paddr;
675
676 while (CIRC_SPACE(bp->rx_prepared_head, bp->rx_tail, RX_RING_SIZE) > 0) {
677 entry = macb_rx_ring_wrap(bp->rx_prepared_head);
678
679 /* Make hw descriptor updates visible to CPU */
680 rmb();
681
682 bp->rx_prepared_head++;
683
684 if (bp->rx_skbuff[entry] == NULL) {
685 /* allocate sk_buff for this free entry in ring */
686 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
687 if (unlikely(skb == NULL)) {
688 netdev_err(bp->dev,
689 "Unable to allocate sk_buff\n");
690 break;
691 }
692
693 /* now fill corresponding descriptor entry */
694 paddr = dma_map_single(&bp->pdev->dev, skb->data,
695 bp->rx_buffer_size, DMA_FROM_DEVICE);
696 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
697 dev_kfree_skb(skb);
698 break;
699 }
700
701 bp->rx_skbuff[entry] = skb;
702
703 if (entry == RX_RING_SIZE - 1)
704 paddr |= MACB_BIT(RX_WRAP);
705 bp->rx_ring[entry].addr = paddr;
706 bp->rx_ring[entry].ctrl = 0;
707
708 /* properly align Ethernet header */
709 skb_reserve(skb, NET_IP_ALIGN);
710 } else {
711 bp->rx_ring[entry].addr &= ~MACB_BIT(RX_USED);
712 bp->rx_ring[entry].ctrl = 0;
713 }
714 }
715
716 /* Make descriptor updates visible to hardware */
717 wmb();
718
719 netdev_vdbg(bp->dev, "rx ring: prepared head %d, tail %d\n",
720 bp->rx_prepared_head, bp->rx_tail);
721 }
722
723 /* Mark DMA descriptors from begin up to and not including end as unused */
724 static void discard_partial_frame(struct macb *bp, unsigned int begin,
725 unsigned int end)
726 {
727 unsigned int frag;
728
729 for (frag = begin; frag != end; frag++) {
730 struct macb_dma_desc *desc = macb_rx_desc(bp, frag);
731 desc->addr &= ~MACB_BIT(RX_USED);
732 }
733
734 /* Make descriptor updates visible to hardware */
735 wmb();
736
737 /*
738 * When this happens, the hardware stats registers for
739 * whatever caused this is updated, so we don't have to record
740 * anything.
741 */
742 }
743
744 static int gem_rx(struct macb *bp, int budget)
745 {
746 unsigned int len;
747 unsigned int entry;
748 struct sk_buff *skb;
749 struct macb_dma_desc *desc;
750 int count = 0;
751
752 while (count < budget) {
753 u32 addr, ctrl;
754
755 entry = macb_rx_ring_wrap(bp->rx_tail);
756 desc = &bp->rx_ring[entry];
757
758 /* Make hw descriptor updates visible to CPU */
759 rmb();
760
761 addr = desc->addr;
762 ctrl = desc->ctrl;
763
764 if (!(addr & MACB_BIT(RX_USED)))
765 break;
766
767 bp->rx_tail++;
768 count++;
769
770 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
771 netdev_err(bp->dev,
772 "not whole frame pointed by descriptor\n");
773 bp->stats.rx_dropped++;
774 break;
775 }
776 skb = bp->rx_skbuff[entry];
777 if (unlikely(!skb)) {
778 netdev_err(bp->dev,
779 "inconsistent Rx descriptor chain\n");
780 bp->stats.rx_dropped++;
781 break;
782 }
783 /* now everything is ready for receiving packet */
784 bp->rx_skbuff[entry] = NULL;
785 len = MACB_BFEXT(RX_FRMLEN, ctrl);
786
787 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
788
789 skb_put(skb, len);
790 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, addr));
791 dma_unmap_single(&bp->pdev->dev, addr,
792 bp->rx_buffer_size, DMA_FROM_DEVICE);
793
794 skb->protocol = eth_type_trans(skb, bp->dev);
795 skb_checksum_none_assert(skb);
796 if (bp->dev->features & NETIF_F_RXCSUM &&
797 !(bp->dev->flags & IFF_PROMISC) &&
798 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
799 skb->ip_summed = CHECKSUM_UNNECESSARY;
800
801 bp->stats.rx_packets++;
802 bp->stats.rx_bytes += skb->len;
803
804 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
805 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
806 skb->len, skb->csum);
807 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
808 skb_mac_header(skb), 16, true);
809 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
810 skb->data, 32, true);
811 #endif
812
813 netif_receive_skb(skb);
814 }
815
816 gem_rx_refill(bp);
817
818 return count;
819 }
820
821 static int macb_rx_frame(struct macb *bp, unsigned int first_frag,
822 unsigned int last_frag)
823 {
824 unsigned int len;
825 unsigned int frag;
826 unsigned int offset;
827 struct sk_buff *skb;
828 struct macb_dma_desc *desc;
829
830 desc = macb_rx_desc(bp, last_frag);
831 len = MACB_BFEXT(RX_FRMLEN, desc->ctrl);
832
833 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
834 macb_rx_ring_wrap(first_frag),
835 macb_rx_ring_wrap(last_frag), len);
836
837 /*
838 * The ethernet header starts NET_IP_ALIGN bytes into the
839 * first buffer. Since the header is 14 bytes, this makes the
840 * payload word-aligned.
841 *
842 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
843 * the two padding bytes into the skb so that we avoid hitting
844 * the slowpath in memcpy(), and pull them off afterwards.
845 */
846 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
847 if (!skb) {
848 bp->stats.rx_dropped++;
849 for (frag = first_frag; ; frag++) {
850 desc = macb_rx_desc(bp, frag);
851 desc->addr &= ~MACB_BIT(RX_USED);
852 if (frag == last_frag)
853 break;
854 }
855
856 /* Make descriptor updates visible to hardware */
857 wmb();
858
859 return 1;
860 }
861
862 offset = 0;
863 len += NET_IP_ALIGN;
864 skb_checksum_none_assert(skb);
865 skb_put(skb, len);
866
867 for (frag = first_frag; ; frag++) {
868 unsigned int frag_len = bp->rx_buffer_size;
869
870 if (offset + frag_len > len) {
871 BUG_ON(frag != last_frag);
872 frag_len = len - offset;
873 }
874 skb_copy_to_linear_data_offset(skb, offset,
875 macb_rx_buffer(bp, frag), frag_len);
876 offset += bp->rx_buffer_size;
877 desc = macb_rx_desc(bp, frag);
878 desc->addr &= ~MACB_BIT(RX_USED);
879
880 if (frag == last_frag)
881 break;
882 }
883
884 /* Make descriptor updates visible to hardware */
885 wmb();
886
887 __skb_pull(skb, NET_IP_ALIGN);
888 skb->protocol = eth_type_trans(skb, bp->dev);
889
890 bp->stats.rx_packets++;
891 bp->stats.rx_bytes += skb->len;
892 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
893 skb->len, skb->csum);
894 netif_receive_skb(skb);
895
896 return 0;
897 }
898
899 static int macb_rx(struct macb *bp, int budget)
900 {
901 int received = 0;
902 unsigned int tail;
903 int first_frag = -1;
904
905 for (tail = bp->rx_tail; budget > 0; tail++) {
906 struct macb_dma_desc *desc = macb_rx_desc(bp, tail);
907 u32 addr, ctrl;
908
909 /* Make hw descriptor updates visible to CPU */
910 rmb();
911
912 addr = desc->addr;
913 ctrl = desc->ctrl;
914
915 if (!(addr & MACB_BIT(RX_USED)))
916 break;
917
918 if (ctrl & MACB_BIT(RX_SOF)) {
919 if (first_frag != -1)
920 discard_partial_frame(bp, first_frag, tail);
921 first_frag = tail;
922 }
923
924 if (ctrl & MACB_BIT(RX_EOF)) {
925 int dropped;
926 BUG_ON(first_frag == -1);
927
928 dropped = macb_rx_frame(bp, first_frag, tail);
929 first_frag = -1;
930 if (!dropped) {
931 received++;
932 budget--;
933 }
934 }
935 }
936
937 if (first_frag != -1)
938 bp->rx_tail = first_frag;
939 else
940 bp->rx_tail = tail;
941
942 return received;
943 }
944
945 static int macb_poll(struct napi_struct *napi, int budget)
946 {
947 struct macb *bp = container_of(napi, struct macb, napi);
948 int work_done;
949 u32 status;
950
951 status = macb_readl(bp, RSR);
952 macb_writel(bp, RSR, status);
953
954 work_done = 0;
955
956 netdev_vdbg(bp->dev, "poll: status = %08lx, budget = %d\n",
957 (unsigned long)status, budget);
958
959 work_done = bp->macbgem_ops.mog_rx(bp, budget);
960 if (work_done < budget) {
961 napi_complete(napi);
962
963 /* Packets received while interrupts were disabled */
964 status = macb_readl(bp, RSR);
965 if (status) {
966 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
967 macb_writel(bp, ISR, MACB_BIT(RCOMP));
968 napi_reschedule(napi);
969 } else {
970 macb_writel(bp, IER, MACB_RX_INT_FLAGS);
971 }
972 }
973
974 /* TODO: Handle errors */
975
976 return work_done;
977 }
978
979 static irqreturn_t macb_interrupt(int irq, void *dev_id)
980 {
981 struct macb_queue *queue = dev_id;
982 struct macb *bp = queue->bp;
983 struct net_device *dev = bp->dev;
984 u32 status, ctrl;
985
986 status = queue_readl(queue, ISR);
987
988 if (unlikely(!status))
989 return IRQ_NONE;
990
991 spin_lock(&bp->lock);
992
993 while (status) {
994 /* close possible race with dev_close */
995 if (unlikely(!netif_running(dev))) {
996 queue_writel(queue, IDR, -1);
997 break;
998 }
999
1000 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1001 (unsigned int)(queue - bp->queues),
1002 (unsigned long)status);
1003
1004 if (status & MACB_RX_INT_FLAGS) {
1005 /*
1006 * There's no point taking any more interrupts
1007 * until we have processed the buffers. The
1008 * scheduling call may fail if the poll routine
1009 * is already scheduled, so disable interrupts
1010 * now.
1011 */
1012 queue_writel(queue, IDR, MACB_RX_INT_FLAGS);
1013 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1014 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1015
1016 if (napi_schedule_prep(&bp->napi)) {
1017 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1018 __napi_schedule(&bp->napi);
1019 }
1020 }
1021
1022 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1023 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1024 schedule_work(&queue->tx_error_task);
1025
1026 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1027 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1028
1029 break;
1030 }
1031
1032 if (status & MACB_BIT(TCOMP))
1033 macb_tx_interrupt(queue);
1034
1035 /*
1036 * Link change detection isn't possible with RMII, so we'll
1037 * add that if/when we get our hands on a full-blown MII PHY.
1038 */
1039
1040 /* There is a hardware issue under heavy load where DMA can
1041 * stop, this causes endless "used buffer descriptor read"
1042 * interrupts but it can be cleared by re-enabling RX. See
1043 * the at91 manual, section 41.3.1 or the Zynq manual
1044 * section 16.7.4 for details.
1045 */
1046 if (status & MACB_BIT(RXUBR)) {
1047 ctrl = macb_readl(bp, NCR);
1048 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1049 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1050
1051 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1052 macb_writel(bp, ISR, MACB_BIT(RXUBR));
1053 }
1054
1055 if (status & MACB_BIT(ISR_ROVR)) {
1056 /* We missed at least one packet */
1057 if (macb_is_gem(bp))
1058 bp->hw_stats.gem.rx_overruns++;
1059 else
1060 bp->hw_stats.macb.rx_overruns++;
1061
1062 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1063 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1064 }
1065
1066 if (status & MACB_BIT(HRESP)) {
1067 /*
1068 * TODO: Reset the hardware, and maybe move the
1069 * netdev_err to a lower-priority context as well
1070 * (work queue?)
1071 */
1072 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1073
1074 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1075 queue_writel(queue, ISR, MACB_BIT(HRESP));
1076 }
1077
1078 status = queue_readl(queue, ISR);
1079 }
1080
1081 spin_unlock(&bp->lock);
1082
1083 return IRQ_HANDLED;
1084 }
1085
1086 #ifdef CONFIG_NET_POLL_CONTROLLER
1087 /*
1088 * Polling receive - used by netconsole and other diagnostic tools
1089 * to allow network i/o with interrupts disabled.
1090 */
1091 static void macb_poll_controller(struct net_device *dev)
1092 {
1093 struct macb *bp = netdev_priv(dev);
1094 struct macb_queue *queue;
1095 unsigned long flags;
1096 unsigned int q;
1097
1098 local_irq_save(flags);
1099 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1100 macb_interrupt(dev->irq, queue);
1101 local_irq_restore(flags);
1102 }
1103 #endif
1104
1105 static inline unsigned int macb_count_tx_descriptors(struct macb *bp,
1106 unsigned int len)
1107 {
1108 return (len + bp->max_tx_length - 1) / bp->max_tx_length;
1109 }
1110
1111 static unsigned int macb_tx_map(struct macb *bp,
1112 struct macb_queue *queue,
1113 struct sk_buff *skb)
1114 {
1115 dma_addr_t mapping;
1116 unsigned int len, entry, i, tx_head = queue->tx_head;
1117 struct macb_tx_skb *tx_skb = NULL;
1118 struct macb_dma_desc *desc;
1119 unsigned int offset, size, count = 0;
1120 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1121 unsigned int eof = 1;
1122 u32 ctrl;
1123
1124 /* First, map non-paged data */
1125 len = skb_headlen(skb);
1126 offset = 0;
1127 while (len) {
1128 size = min(len, bp->max_tx_length);
1129 entry = macb_tx_ring_wrap(tx_head);
1130 tx_skb = &queue->tx_skb[entry];
1131
1132 mapping = dma_map_single(&bp->pdev->dev,
1133 skb->data + offset,
1134 size, DMA_TO_DEVICE);
1135 if (dma_mapping_error(&bp->pdev->dev, mapping))
1136 goto dma_error;
1137
1138 /* Save info to properly release resources */
1139 tx_skb->skb = NULL;
1140 tx_skb->mapping = mapping;
1141 tx_skb->size = size;
1142 tx_skb->mapped_as_page = false;
1143
1144 len -= size;
1145 offset += size;
1146 count++;
1147 tx_head++;
1148 }
1149
1150 /* Then, map paged data from fragments */
1151 for (f = 0; f < nr_frags; f++) {
1152 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
1153
1154 len = skb_frag_size(frag);
1155 offset = 0;
1156 while (len) {
1157 size = min(len, bp->max_tx_length);
1158 entry = macb_tx_ring_wrap(tx_head);
1159 tx_skb = &queue->tx_skb[entry];
1160
1161 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
1162 offset, size, DMA_TO_DEVICE);
1163 if (dma_mapping_error(&bp->pdev->dev, mapping))
1164 goto dma_error;
1165
1166 /* Save info to properly release resources */
1167 tx_skb->skb = NULL;
1168 tx_skb->mapping = mapping;
1169 tx_skb->size = size;
1170 tx_skb->mapped_as_page = true;
1171
1172 len -= size;
1173 offset += size;
1174 count++;
1175 tx_head++;
1176 }
1177 }
1178
1179 /* Should never happen */
1180 if (unlikely(tx_skb == NULL)) {
1181 netdev_err(bp->dev, "BUG! empty skb!\n");
1182 return 0;
1183 }
1184
1185 /* This is the last buffer of the frame: save socket buffer */
1186 tx_skb->skb = skb;
1187
1188 /* Update TX ring: update buffer descriptors in reverse order
1189 * to avoid race condition
1190 */
1191
1192 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
1193 * to set the end of TX queue
1194 */
1195 i = tx_head;
1196 entry = macb_tx_ring_wrap(i);
1197 ctrl = MACB_BIT(TX_USED);
1198 desc = &queue->tx_ring[entry];
1199 desc->ctrl = ctrl;
1200
1201 do {
1202 i--;
1203 entry = macb_tx_ring_wrap(i);
1204 tx_skb = &queue->tx_skb[entry];
1205 desc = &queue->tx_ring[entry];
1206
1207 ctrl = (u32)tx_skb->size;
1208 if (eof) {
1209 ctrl |= MACB_BIT(TX_LAST);
1210 eof = 0;
1211 }
1212 if (unlikely(entry == (TX_RING_SIZE - 1)))
1213 ctrl |= MACB_BIT(TX_WRAP);
1214
1215 /* Set TX buffer descriptor */
1216 desc->addr = tx_skb->mapping;
1217 /* desc->addr must be visible to hardware before clearing
1218 * 'TX_USED' bit in desc->ctrl.
1219 */
1220 wmb();
1221 desc->ctrl = ctrl;
1222 } while (i != queue->tx_head);
1223
1224 queue->tx_head = tx_head;
1225
1226 return count;
1227
1228 dma_error:
1229 netdev_err(bp->dev, "TX DMA map failed\n");
1230
1231 for (i = queue->tx_head; i != tx_head; i++) {
1232 tx_skb = macb_tx_skb(queue, i);
1233
1234 macb_tx_unmap(bp, tx_skb);
1235 }
1236
1237 return 0;
1238 }
1239
1240 static int macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
1241 {
1242 u16 queue_index = skb_get_queue_mapping(skb);
1243 struct macb *bp = netdev_priv(dev);
1244 struct macb_queue *queue = &bp->queues[queue_index];
1245 unsigned long flags;
1246 unsigned int count, nr_frags, frag_size, f;
1247
1248 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1249 netdev_vdbg(bp->dev,
1250 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
1251 queue_index, skb->len, skb->head, skb->data,
1252 skb_tail_pointer(skb), skb_end_pointer(skb));
1253 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
1254 skb->data, 16, true);
1255 #endif
1256
1257 /* Count how many TX buffer descriptors are needed to send this
1258 * socket buffer: skb fragments of jumbo frames may need to be
1259 * splitted into many buffer descriptors.
1260 */
1261 count = macb_count_tx_descriptors(bp, skb_headlen(skb));
1262 nr_frags = skb_shinfo(skb)->nr_frags;
1263 for (f = 0; f < nr_frags; f++) {
1264 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
1265 count += macb_count_tx_descriptors(bp, frag_size);
1266 }
1267
1268 spin_lock_irqsave(&bp->lock, flags);
1269
1270 /* This is a hard error, log it. */
1271 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < count) {
1272 netif_stop_subqueue(dev, queue_index);
1273 spin_unlock_irqrestore(&bp->lock, flags);
1274 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
1275 queue->tx_head, queue->tx_tail);
1276 return NETDEV_TX_BUSY;
1277 }
1278
1279 /* Map socket buffer for DMA transfer */
1280 if (!macb_tx_map(bp, queue, skb)) {
1281 dev_kfree_skb_any(skb);
1282 goto unlock;
1283 }
1284
1285 /* Make newly initialized descriptor visible to hardware */
1286 wmb();
1287
1288 skb_tx_timestamp(skb);
1289
1290 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1291
1292 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, TX_RING_SIZE) < 1)
1293 netif_stop_subqueue(dev, queue_index);
1294
1295 unlock:
1296 spin_unlock_irqrestore(&bp->lock, flags);
1297
1298 return NETDEV_TX_OK;
1299 }
1300
1301 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
1302 {
1303 if (!macb_is_gem(bp)) {
1304 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
1305 } else {
1306 bp->rx_buffer_size = size;
1307
1308 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
1309 netdev_dbg(bp->dev,
1310 "RX buffer must be multiple of %d bytes, expanding\n",
1311 RX_BUFFER_MULTIPLE);
1312 bp->rx_buffer_size =
1313 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
1314 }
1315 }
1316
1317 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%Zu]\n",
1318 bp->dev->mtu, bp->rx_buffer_size);
1319 }
1320
1321 static void gem_free_rx_buffers(struct macb *bp)
1322 {
1323 struct sk_buff *skb;
1324 struct macb_dma_desc *desc;
1325 dma_addr_t addr;
1326 int i;
1327
1328 if (!bp->rx_skbuff)
1329 return;
1330
1331 for (i = 0; i < RX_RING_SIZE; i++) {
1332 skb = bp->rx_skbuff[i];
1333
1334 if (skb == NULL)
1335 continue;
1336
1337 desc = &bp->rx_ring[i];
1338 addr = MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1339 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
1340 DMA_FROM_DEVICE);
1341 dev_kfree_skb_any(skb);
1342 skb = NULL;
1343 }
1344
1345 kfree(bp->rx_skbuff);
1346 bp->rx_skbuff = NULL;
1347 }
1348
1349 static void macb_free_rx_buffers(struct macb *bp)
1350 {
1351 if (bp->rx_buffers) {
1352 dma_free_coherent(&bp->pdev->dev,
1353 RX_RING_SIZE * bp->rx_buffer_size,
1354 bp->rx_buffers, bp->rx_buffers_dma);
1355 bp->rx_buffers = NULL;
1356 }
1357 }
1358
1359 static void macb_free_consistent(struct macb *bp)
1360 {
1361 struct macb_queue *queue;
1362 unsigned int q;
1363
1364 bp->macbgem_ops.mog_free_rx_buffers(bp);
1365 if (bp->rx_ring) {
1366 dma_free_coherent(&bp->pdev->dev, RX_RING_BYTES,
1367 bp->rx_ring, bp->rx_ring_dma);
1368 bp->rx_ring = NULL;
1369 }
1370
1371 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1372 kfree(queue->tx_skb);
1373 queue->tx_skb = NULL;
1374 if (queue->tx_ring) {
1375 dma_free_coherent(&bp->pdev->dev, TX_RING_BYTES,
1376 queue->tx_ring, queue->tx_ring_dma);
1377 queue->tx_ring = NULL;
1378 }
1379 }
1380 }
1381
1382 static int gem_alloc_rx_buffers(struct macb *bp)
1383 {
1384 int size;
1385
1386 size = RX_RING_SIZE * sizeof(struct sk_buff *);
1387 bp->rx_skbuff = kzalloc(size, GFP_KERNEL);
1388 if (!bp->rx_skbuff)
1389 return -ENOMEM;
1390 else
1391 netdev_dbg(bp->dev,
1392 "Allocated %d RX struct sk_buff entries at %p\n",
1393 RX_RING_SIZE, bp->rx_skbuff);
1394 return 0;
1395 }
1396
1397 static int macb_alloc_rx_buffers(struct macb *bp)
1398 {
1399 int size;
1400
1401 size = RX_RING_SIZE * bp->rx_buffer_size;
1402 bp->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
1403 &bp->rx_buffers_dma, GFP_KERNEL);
1404 if (!bp->rx_buffers)
1405 return -ENOMEM;
1406 else
1407 netdev_dbg(bp->dev,
1408 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
1409 size, (unsigned long)bp->rx_buffers_dma, bp->rx_buffers);
1410 return 0;
1411 }
1412
1413 static int macb_alloc_consistent(struct macb *bp)
1414 {
1415 struct macb_queue *queue;
1416 unsigned int q;
1417 int size;
1418
1419 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1420 size = TX_RING_BYTES;
1421 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1422 &queue->tx_ring_dma,
1423 GFP_KERNEL);
1424 if (!queue->tx_ring)
1425 goto out_err;
1426 netdev_dbg(bp->dev,
1427 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
1428 q, size, (unsigned long)queue->tx_ring_dma,
1429 queue->tx_ring);
1430
1431 size = TX_RING_SIZE * sizeof(struct macb_tx_skb);
1432 queue->tx_skb = kmalloc(size, GFP_KERNEL);
1433 if (!queue->tx_skb)
1434 goto out_err;
1435 }
1436
1437 size = RX_RING_BYTES;
1438 bp->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
1439 &bp->rx_ring_dma, GFP_KERNEL);
1440 if (!bp->rx_ring)
1441 goto out_err;
1442 netdev_dbg(bp->dev,
1443 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
1444 size, (unsigned long)bp->rx_ring_dma, bp->rx_ring);
1445
1446 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
1447 goto out_err;
1448
1449 return 0;
1450
1451 out_err:
1452 macb_free_consistent(bp);
1453 return -ENOMEM;
1454 }
1455
1456 static void gem_init_rings(struct macb *bp)
1457 {
1458 struct macb_queue *queue;
1459 unsigned int q;
1460 int i;
1461
1462 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1463 for (i = 0; i < TX_RING_SIZE; i++) {
1464 queue->tx_ring[i].addr = 0;
1465 queue->tx_ring[i].ctrl = MACB_BIT(TX_USED);
1466 }
1467 queue->tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1468 queue->tx_head = 0;
1469 queue->tx_tail = 0;
1470 }
1471
1472 bp->rx_tail = 0;
1473 bp->rx_prepared_head = 0;
1474
1475 gem_rx_refill(bp);
1476 }
1477
1478 static void macb_init_rings(struct macb *bp)
1479 {
1480 int i;
1481 dma_addr_t addr;
1482
1483 addr = bp->rx_buffers_dma;
1484 for (i = 0; i < RX_RING_SIZE; i++) {
1485 bp->rx_ring[i].addr = addr;
1486 bp->rx_ring[i].ctrl = 0;
1487 addr += bp->rx_buffer_size;
1488 }
1489 bp->rx_ring[RX_RING_SIZE - 1].addr |= MACB_BIT(RX_WRAP);
1490
1491 for (i = 0; i < TX_RING_SIZE; i++) {
1492 bp->queues[0].tx_ring[i].addr = 0;
1493 bp->queues[0].tx_ring[i].ctrl = MACB_BIT(TX_USED);
1494 }
1495 bp->queues[0].tx_head = 0;
1496 bp->queues[0].tx_tail = 0;
1497 bp->queues[0].tx_ring[TX_RING_SIZE - 1].ctrl |= MACB_BIT(TX_WRAP);
1498
1499 bp->rx_tail = 0;
1500 }
1501
1502 static void macb_reset_hw(struct macb *bp)
1503 {
1504 struct macb_queue *queue;
1505 unsigned int q;
1506
1507 /*
1508 * Disable RX and TX (XXX: Should we halt the transmission
1509 * more gracefully?)
1510 */
1511 macb_writel(bp, NCR, 0);
1512
1513 /* Clear the stats registers (XXX: Update stats first?) */
1514 macb_writel(bp, NCR, MACB_BIT(CLRSTAT));
1515
1516 /* Clear all status flags */
1517 macb_writel(bp, TSR, -1);
1518 macb_writel(bp, RSR, -1);
1519
1520 /* Disable all interrupts */
1521 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1522 queue_writel(queue, IDR, -1);
1523 queue_readl(queue, ISR);
1524 }
1525 }
1526
1527 static u32 gem_mdc_clk_div(struct macb *bp)
1528 {
1529 u32 config;
1530 unsigned long pclk_hz = clk_get_rate(bp->pclk);
1531
1532 if (pclk_hz <= 20000000)
1533 config = GEM_BF(CLK, GEM_CLK_DIV8);
1534 else if (pclk_hz <= 40000000)
1535 config = GEM_BF(CLK, GEM_CLK_DIV16);
1536 else if (pclk_hz <= 80000000)
1537 config = GEM_BF(CLK, GEM_CLK_DIV32);
1538 else if (pclk_hz <= 120000000)
1539 config = GEM_BF(CLK, GEM_CLK_DIV48);
1540 else if (pclk_hz <= 160000000)
1541 config = GEM_BF(CLK, GEM_CLK_DIV64);
1542 else
1543 config = GEM_BF(CLK, GEM_CLK_DIV96);
1544
1545 return config;
1546 }
1547
1548 static u32 macb_mdc_clk_div(struct macb *bp)
1549 {
1550 u32 config;
1551 unsigned long pclk_hz;
1552
1553 if (macb_is_gem(bp))
1554 return gem_mdc_clk_div(bp);
1555
1556 pclk_hz = clk_get_rate(bp->pclk);
1557 if (pclk_hz <= 20000000)
1558 config = MACB_BF(CLK, MACB_CLK_DIV8);
1559 else if (pclk_hz <= 40000000)
1560 config = MACB_BF(CLK, MACB_CLK_DIV16);
1561 else if (pclk_hz <= 80000000)
1562 config = MACB_BF(CLK, MACB_CLK_DIV32);
1563 else
1564 config = MACB_BF(CLK, MACB_CLK_DIV64);
1565
1566 return config;
1567 }
1568
1569 /*
1570 * Get the DMA bus width field of the network configuration register that we
1571 * should program. We find the width from decoding the design configuration
1572 * register to find the maximum supported data bus width.
1573 */
1574 static u32 macb_dbw(struct macb *bp)
1575 {
1576 if (!macb_is_gem(bp))
1577 return 0;
1578
1579 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
1580 case 4:
1581 return GEM_BF(DBW, GEM_DBW128);
1582 case 2:
1583 return GEM_BF(DBW, GEM_DBW64);
1584 case 1:
1585 default:
1586 return GEM_BF(DBW, GEM_DBW32);
1587 }
1588 }
1589
1590 /*
1591 * Configure the receive DMA engine
1592 * - use the correct receive buffer size
1593 * - set best burst length for DMA operations
1594 * (if not supported by FIFO, it will fallback to default)
1595 * - set both rx/tx packet buffers to full memory size
1596 * These are configurable parameters for GEM.
1597 */
1598 static void macb_configure_dma(struct macb *bp)
1599 {
1600 u32 dmacfg;
1601 u32 tmp, ncr;
1602
1603 if (macb_is_gem(bp)) {
1604 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
1605 dmacfg |= GEM_BF(RXBS, bp->rx_buffer_size / RX_BUFFER_MULTIPLE);
1606 if (bp->dma_burst_length)
1607 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
1608 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
1609 dmacfg &= ~GEM_BIT(ENDIA_PKT);
1610
1611 /* Find the CPU endianness by using the loopback bit of net_ctrl
1612 * register. save it first. When the CPU is in big endian we
1613 * need to program swaped mode for management descriptor access.
1614 */
1615 ncr = macb_readl(bp, NCR);
1616 __raw_writel(MACB_BIT(LLB), bp->regs + MACB_NCR);
1617 tmp = __raw_readl(bp->regs + MACB_NCR);
1618
1619 if (tmp == MACB_BIT(LLB))
1620 dmacfg &= ~GEM_BIT(ENDIA_DESC);
1621 else
1622 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
1623
1624 /* Restore net_ctrl */
1625 macb_writel(bp, NCR, ncr);
1626
1627 if (bp->dev->features & NETIF_F_HW_CSUM)
1628 dmacfg |= GEM_BIT(TXCOEN);
1629 else
1630 dmacfg &= ~GEM_BIT(TXCOEN);
1631 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
1632 dmacfg);
1633 gem_writel(bp, DMACFG, dmacfg);
1634 }
1635 }
1636
1637 static void macb_init_hw(struct macb *bp)
1638 {
1639 struct macb_queue *queue;
1640 unsigned int q;
1641
1642 u32 config;
1643
1644 macb_reset_hw(bp);
1645 macb_set_hwaddr(bp);
1646
1647 config = macb_mdc_clk_div(bp);
1648 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
1649 config |= MACB_BIT(PAE); /* PAuse Enable */
1650 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
1651 config |= MACB_BIT(BIG); /* Receive oversized frames */
1652 if (bp->dev->flags & IFF_PROMISC)
1653 config |= MACB_BIT(CAF); /* Copy All Frames */
1654 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
1655 config |= GEM_BIT(RXCOEN);
1656 if (!(bp->dev->flags & IFF_BROADCAST))
1657 config |= MACB_BIT(NBC); /* No BroadCast */
1658 config |= macb_dbw(bp);
1659 macb_writel(bp, NCFGR, config);
1660 bp->speed = SPEED_10;
1661 bp->duplex = DUPLEX_HALF;
1662
1663 macb_configure_dma(bp);
1664
1665 /* Initialize TX and RX buffers */
1666 macb_writel(bp, RBQP, bp->rx_ring_dma);
1667 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1668 queue_writel(queue, TBQP, queue->tx_ring_dma);
1669
1670 /* Enable interrupts */
1671 queue_writel(queue, IER,
1672 MACB_RX_INT_FLAGS |
1673 MACB_TX_INT_FLAGS |
1674 MACB_BIT(HRESP));
1675 }
1676
1677 /* Enable TX and RX */
1678 macb_writel(bp, NCR, MACB_BIT(RE) | MACB_BIT(TE) | MACB_BIT(MPE));
1679 }
1680
1681 /*
1682 * The hash address register is 64 bits long and takes up two
1683 * locations in the memory map. The least significant bits are stored
1684 * in EMAC_HSL and the most significant bits in EMAC_HSH.
1685 *
1686 * The unicast hash enable and the multicast hash enable bits in the
1687 * network configuration register enable the reception of hash matched
1688 * frames. The destination address is reduced to a 6 bit index into
1689 * the 64 bit hash register using the following hash function. The
1690 * hash function is an exclusive or of every sixth bit of the
1691 * destination address.
1692 *
1693 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
1694 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
1695 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
1696 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
1697 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
1698 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
1699 *
1700 * da[0] represents the least significant bit of the first byte
1701 * received, that is, the multicast/unicast indicator, and da[47]
1702 * represents the most significant bit of the last byte received. If
1703 * the hash index, hi[n], points to a bit that is set in the hash
1704 * register then the frame will be matched according to whether the
1705 * frame is multicast or unicast. A multicast match will be signalled
1706 * if the multicast hash enable bit is set, da[0] is 1 and the hash
1707 * index points to a bit set in the hash register. A unicast match
1708 * will be signalled if the unicast hash enable bit is set, da[0] is 0
1709 * and the hash index points to a bit set in the hash register. To
1710 * receive all multicast frames, the hash register should be set with
1711 * all ones and the multicast hash enable bit should be set in the
1712 * network configuration register.
1713 */
1714
1715 static inline int hash_bit_value(int bitnr, __u8 *addr)
1716 {
1717 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
1718 return 1;
1719 return 0;
1720 }
1721
1722 /*
1723 * Return the hash index value for the specified address.
1724 */
1725 static int hash_get_index(__u8 *addr)
1726 {
1727 int i, j, bitval;
1728 int hash_index = 0;
1729
1730 for (j = 0; j < 6; j++) {
1731 for (i = 0, bitval = 0; i < 8; i++)
1732 bitval ^= hash_bit_value(i * 6 + j, addr);
1733
1734 hash_index |= (bitval << j);
1735 }
1736
1737 return hash_index;
1738 }
1739
1740 /*
1741 * Add multicast addresses to the internal multicast-hash table.
1742 */
1743 static void macb_sethashtable(struct net_device *dev)
1744 {
1745 struct netdev_hw_addr *ha;
1746 unsigned long mc_filter[2];
1747 unsigned int bitnr;
1748 struct macb *bp = netdev_priv(dev);
1749
1750 mc_filter[0] = mc_filter[1] = 0;
1751
1752 netdev_for_each_mc_addr(ha, dev) {
1753 bitnr = hash_get_index(ha->addr);
1754 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
1755 }
1756
1757 macb_or_gem_writel(bp, HRB, mc_filter[0]);
1758 macb_or_gem_writel(bp, HRT, mc_filter[1]);
1759 }
1760
1761 /*
1762 * Enable/Disable promiscuous and multicast modes.
1763 */
1764 static void macb_set_rx_mode(struct net_device *dev)
1765 {
1766 unsigned long cfg;
1767 struct macb *bp = netdev_priv(dev);
1768
1769 cfg = macb_readl(bp, NCFGR);
1770
1771 if (dev->flags & IFF_PROMISC) {
1772 /* Enable promiscuous mode */
1773 cfg |= MACB_BIT(CAF);
1774
1775 /* Disable RX checksum offload */
1776 if (macb_is_gem(bp))
1777 cfg &= ~GEM_BIT(RXCOEN);
1778 } else {
1779 /* Disable promiscuous mode */
1780 cfg &= ~MACB_BIT(CAF);
1781
1782 /* Enable RX checksum offload only if requested */
1783 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
1784 cfg |= GEM_BIT(RXCOEN);
1785 }
1786
1787 if (dev->flags & IFF_ALLMULTI) {
1788 /* Enable all multicast mode */
1789 macb_or_gem_writel(bp, HRB, -1);
1790 macb_or_gem_writel(bp, HRT, -1);
1791 cfg |= MACB_BIT(NCFGR_MTI);
1792 } else if (!netdev_mc_empty(dev)) {
1793 /* Enable specific multicasts */
1794 macb_sethashtable(dev);
1795 cfg |= MACB_BIT(NCFGR_MTI);
1796 } else if (dev->flags & (~IFF_ALLMULTI)) {
1797 /* Disable all multicast mode */
1798 macb_or_gem_writel(bp, HRB, 0);
1799 macb_or_gem_writel(bp, HRT, 0);
1800 cfg &= ~MACB_BIT(NCFGR_MTI);
1801 }
1802
1803 macb_writel(bp, NCFGR, cfg);
1804 }
1805
1806 static int macb_open(struct net_device *dev)
1807 {
1808 struct macb *bp = netdev_priv(dev);
1809 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
1810 int err;
1811
1812 netdev_dbg(bp->dev, "open\n");
1813
1814 /* carrier starts down */
1815 netif_carrier_off(dev);
1816
1817 /* if the phy is not yet register, retry later*/
1818 if (!bp->phy_dev)
1819 return -EAGAIN;
1820
1821 /* RX buffers initialization */
1822 macb_init_rx_buffer_size(bp, bufsz);
1823
1824 err = macb_alloc_consistent(bp);
1825 if (err) {
1826 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
1827 err);
1828 return err;
1829 }
1830
1831 napi_enable(&bp->napi);
1832
1833 bp->macbgem_ops.mog_init_rings(bp);
1834 macb_init_hw(bp);
1835
1836 /* schedule a link state check */
1837 phy_start(bp->phy_dev);
1838
1839 netif_tx_start_all_queues(dev);
1840
1841 return 0;
1842 }
1843
1844 static int macb_close(struct net_device *dev)
1845 {
1846 struct macb *bp = netdev_priv(dev);
1847 unsigned long flags;
1848
1849 netif_tx_stop_all_queues(dev);
1850 napi_disable(&bp->napi);
1851
1852 if (bp->phy_dev)
1853 phy_stop(bp->phy_dev);
1854
1855 spin_lock_irqsave(&bp->lock, flags);
1856 macb_reset_hw(bp);
1857 netif_carrier_off(dev);
1858 spin_unlock_irqrestore(&bp->lock, flags);
1859
1860 macb_free_consistent(bp);
1861
1862 return 0;
1863 }
1864
1865 static void gem_update_stats(struct macb *bp)
1866 {
1867 int i;
1868 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
1869
1870 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
1871 u32 offset = gem_statistics[i].offset;
1872 u64 val = readl_relaxed(bp->regs + offset);
1873
1874 bp->ethtool_stats[i] += val;
1875 *p += val;
1876
1877 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
1878 /* Add GEM_OCTTXH, GEM_OCTRXH */
1879 val = readl_relaxed(bp->regs + offset + 4);
1880 bp->ethtool_stats[i] += ((u64)val) << 32;
1881 *(++p) += val;
1882 }
1883 }
1884 }
1885
1886 static struct net_device_stats *gem_get_stats(struct macb *bp)
1887 {
1888 struct gem_stats *hwstat = &bp->hw_stats.gem;
1889 struct net_device_stats *nstat = &bp->stats;
1890
1891 gem_update_stats(bp);
1892
1893 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
1894 hwstat->rx_alignment_errors +
1895 hwstat->rx_resource_errors +
1896 hwstat->rx_overruns +
1897 hwstat->rx_oversize_frames +
1898 hwstat->rx_jabbers +
1899 hwstat->rx_undersized_frames +
1900 hwstat->rx_length_field_frame_errors);
1901 nstat->tx_errors = (hwstat->tx_late_collisions +
1902 hwstat->tx_excessive_collisions +
1903 hwstat->tx_underrun +
1904 hwstat->tx_carrier_sense_errors);
1905 nstat->multicast = hwstat->rx_multicast_frames;
1906 nstat->collisions = (hwstat->tx_single_collision_frames +
1907 hwstat->tx_multiple_collision_frames +
1908 hwstat->tx_excessive_collisions);
1909 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
1910 hwstat->rx_jabbers +
1911 hwstat->rx_undersized_frames +
1912 hwstat->rx_length_field_frame_errors);
1913 nstat->rx_over_errors = hwstat->rx_resource_errors;
1914 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
1915 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
1916 nstat->rx_fifo_errors = hwstat->rx_overruns;
1917 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
1918 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
1919 nstat->tx_fifo_errors = hwstat->tx_underrun;
1920
1921 return nstat;
1922 }
1923
1924 static void gem_get_ethtool_stats(struct net_device *dev,
1925 struct ethtool_stats *stats, u64 *data)
1926 {
1927 struct macb *bp;
1928
1929 bp = netdev_priv(dev);
1930 gem_update_stats(bp);
1931 memcpy(data, &bp->ethtool_stats, sizeof(u64) * GEM_STATS_LEN);
1932 }
1933
1934 static int gem_get_sset_count(struct net_device *dev, int sset)
1935 {
1936 switch (sset) {
1937 case ETH_SS_STATS:
1938 return GEM_STATS_LEN;
1939 default:
1940 return -EOPNOTSUPP;
1941 }
1942 }
1943
1944 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
1945 {
1946 int i;
1947
1948 switch (sset) {
1949 case ETH_SS_STATS:
1950 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
1951 memcpy(p, gem_statistics[i].stat_string,
1952 ETH_GSTRING_LEN);
1953 break;
1954 }
1955 }
1956
1957 static struct net_device_stats *macb_get_stats(struct net_device *dev)
1958 {
1959 struct macb *bp = netdev_priv(dev);
1960 struct net_device_stats *nstat = &bp->stats;
1961 struct macb_stats *hwstat = &bp->hw_stats.macb;
1962
1963 if (macb_is_gem(bp))
1964 return gem_get_stats(bp);
1965
1966 /* read stats from hardware */
1967 macb_update_stats(bp);
1968
1969 /* Convert HW stats into netdevice stats */
1970 nstat->rx_errors = (hwstat->rx_fcs_errors +
1971 hwstat->rx_align_errors +
1972 hwstat->rx_resource_errors +
1973 hwstat->rx_overruns +
1974 hwstat->rx_oversize_pkts +
1975 hwstat->rx_jabbers +
1976 hwstat->rx_undersize_pkts +
1977 hwstat->rx_length_mismatch);
1978 nstat->tx_errors = (hwstat->tx_late_cols +
1979 hwstat->tx_excessive_cols +
1980 hwstat->tx_underruns +
1981 hwstat->tx_carrier_errors +
1982 hwstat->sqe_test_errors);
1983 nstat->collisions = (hwstat->tx_single_cols +
1984 hwstat->tx_multiple_cols +
1985 hwstat->tx_excessive_cols);
1986 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
1987 hwstat->rx_jabbers +
1988 hwstat->rx_undersize_pkts +
1989 hwstat->rx_length_mismatch);
1990 nstat->rx_over_errors = hwstat->rx_resource_errors +
1991 hwstat->rx_overruns;
1992 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
1993 nstat->rx_frame_errors = hwstat->rx_align_errors;
1994 nstat->rx_fifo_errors = hwstat->rx_overruns;
1995 /* XXX: What does "missed" mean? */
1996 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
1997 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
1998 nstat->tx_fifo_errors = hwstat->tx_underruns;
1999 /* Don't know about heartbeat or window errors... */
2000
2001 return nstat;
2002 }
2003
2004 static int macb_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2005 {
2006 struct macb *bp = netdev_priv(dev);
2007 struct phy_device *phydev = bp->phy_dev;
2008
2009 if (!phydev)
2010 return -ENODEV;
2011
2012 return phy_ethtool_gset(phydev, cmd);
2013 }
2014
2015 static int macb_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2016 {
2017 struct macb *bp = netdev_priv(dev);
2018 struct phy_device *phydev = bp->phy_dev;
2019
2020 if (!phydev)
2021 return -ENODEV;
2022
2023 return phy_ethtool_sset(phydev, cmd);
2024 }
2025
2026 static int macb_get_regs_len(struct net_device *netdev)
2027 {
2028 return MACB_GREGS_NBR * sizeof(u32);
2029 }
2030
2031 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2032 void *p)
2033 {
2034 struct macb *bp = netdev_priv(dev);
2035 unsigned int tail, head;
2036 u32 *regs_buff = p;
2037
2038 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
2039 | MACB_GREGS_VERSION;
2040
2041 tail = macb_tx_ring_wrap(bp->queues[0].tx_tail);
2042 head = macb_tx_ring_wrap(bp->queues[0].tx_head);
2043
2044 regs_buff[0] = macb_readl(bp, NCR);
2045 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
2046 regs_buff[2] = macb_readl(bp, NSR);
2047 regs_buff[3] = macb_readl(bp, TSR);
2048 regs_buff[4] = macb_readl(bp, RBQP);
2049 regs_buff[5] = macb_readl(bp, TBQP);
2050 regs_buff[6] = macb_readl(bp, RSR);
2051 regs_buff[7] = macb_readl(bp, IMR);
2052
2053 regs_buff[8] = tail;
2054 regs_buff[9] = head;
2055 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
2056 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
2057
2058 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
2059 if (macb_is_gem(bp)) {
2060 regs_buff[13] = gem_readl(bp, DMACFG);
2061 }
2062 }
2063
2064 static const struct ethtool_ops macb_ethtool_ops = {
2065 .get_settings = macb_get_settings,
2066 .set_settings = macb_set_settings,
2067 .get_regs_len = macb_get_regs_len,
2068 .get_regs = macb_get_regs,
2069 .get_link = ethtool_op_get_link,
2070 .get_ts_info = ethtool_op_get_ts_info,
2071 };
2072
2073 static const struct ethtool_ops gem_ethtool_ops = {
2074 .get_settings = macb_get_settings,
2075 .set_settings = macb_set_settings,
2076 .get_regs_len = macb_get_regs_len,
2077 .get_regs = macb_get_regs,
2078 .get_link = ethtool_op_get_link,
2079 .get_ts_info = ethtool_op_get_ts_info,
2080 .get_ethtool_stats = gem_get_ethtool_stats,
2081 .get_strings = gem_get_ethtool_strings,
2082 .get_sset_count = gem_get_sset_count,
2083 };
2084
2085 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2086 {
2087 struct macb *bp = netdev_priv(dev);
2088 struct phy_device *phydev = bp->phy_dev;
2089
2090 if (!netif_running(dev))
2091 return -EINVAL;
2092
2093 if (!phydev)
2094 return -ENODEV;
2095
2096 return phy_mii_ioctl(phydev, rq, cmd);
2097 }
2098
2099 static int macb_set_features(struct net_device *netdev,
2100 netdev_features_t features)
2101 {
2102 struct macb *bp = netdev_priv(netdev);
2103 netdev_features_t changed = features ^ netdev->features;
2104
2105 /* TX checksum offload */
2106 if ((changed & NETIF_F_HW_CSUM) && macb_is_gem(bp)) {
2107 u32 dmacfg;
2108
2109 dmacfg = gem_readl(bp, DMACFG);
2110 if (features & NETIF_F_HW_CSUM)
2111 dmacfg |= GEM_BIT(TXCOEN);
2112 else
2113 dmacfg &= ~GEM_BIT(TXCOEN);
2114 gem_writel(bp, DMACFG, dmacfg);
2115 }
2116
2117 /* RX checksum offload */
2118 if ((changed & NETIF_F_RXCSUM) && macb_is_gem(bp)) {
2119 u32 netcfg;
2120
2121 netcfg = gem_readl(bp, NCFGR);
2122 if (features & NETIF_F_RXCSUM &&
2123 !(netdev->flags & IFF_PROMISC))
2124 netcfg |= GEM_BIT(RXCOEN);
2125 else
2126 netcfg &= ~GEM_BIT(RXCOEN);
2127 gem_writel(bp, NCFGR, netcfg);
2128 }
2129
2130 return 0;
2131 }
2132
2133 static const struct net_device_ops macb_netdev_ops = {
2134 .ndo_open = macb_open,
2135 .ndo_stop = macb_close,
2136 .ndo_start_xmit = macb_start_xmit,
2137 .ndo_set_rx_mode = macb_set_rx_mode,
2138 .ndo_get_stats = macb_get_stats,
2139 .ndo_do_ioctl = macb_ioctl,
2140 .ndo_validate_addr = eth_validate_addr,
2141 .ndo_change_mtu = eth_change_mtu,
2142 .ndo_set_mac_address = eth_mac_addr,
2143 #ifdef CONFIG_NET_POLL_CONTROLLER
2144 .ndo_poll_controller = macb_poll_controller,
2145 #endif
2146 .ndo_set_features = macb_set_features,
2147 };
2148
2149 /*
2150 * Configure peripheral capabilities according to device tree
2151 * and integration options used
2152 */
2153 static void macb_configure_caps(struct macb *bp, const struct macb_config *dt_conf)
2154 {
2155 u32 dcfg;
2156
2157 if (dt_conf)
2158 bp->caps = dt_conf->caps;
2159
2160 if (macb_is_gem_hw(bp->regs)) {
2161 bp->caps |= MACB_CAPS_MACB_IS_GEM;
2162
2163 dcfg = gem_readl(bp, DCFG1);
2164 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
2165 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
2166 dcfg = gem_readl(bp, DCFG2);
2167 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
2168 bp->caps |= MACB_CAPS_FIFO_MODE;
2169 }
2170
2171 netdev_dbg(bp->dev, "Cadence caps 0x%08x\n", bp->caps);
2172 }
2173
2174 static void macb_probe_queues(void __iomem *mem,
2175 unsigned int *queue_mask,
2176 unsigned int *num_queues)
2177 {
2178 unsigned int hw_q;
2179
2180 *queue_mask = 0x1;
2181 *num_queues = 1;
2182
2183 /* is it macb or gem ?
2184 *
2185 * We need to read directly from the hardware here because
2186 * we are early in the probe process and don't have the
2187 * MACB_CAPS_MACB_IS_GEM flag positioned
2188 */
2189 if (!macb_is_gem_hw(mem))
2190 return;
2191
2192 /* bit 0 is never set but queue 0 always exists */
2193 *queue_mask = readl_relaxed(mem + GEM_DCFG6) & 0xff;
2194
2195 *queue_mask |= 0x1;
2196
2197 for (hw_q = 1; hw_q < MACB_MAX_QUEUES; ++hw_q)
2198 if (*queue_mask & (1 << hw_q))
2199 (*num_queues)++;
2200 }
2201
2202 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
2203 struct clk **hclk, struct clk **tx_clk)
2204 {
2205 int err;
2206
2207 *pclk = devm_clk_get(&pdev->dev, "pclk");
2208 if (IS_ERR(*pclk)) {
2209 err = PTR_ERR(*pclk);
2210 dev_err(&pdev->dev, "failed to get macb_clk (%u)\n", err);
2211 return err;
2212 }
2213
2214 *hclk = devm_clk_get(&pdev->dev, "hclk");
2215 if (IS_ERR(*hclk)) {
2216 err = PTR_ERR(*hclk);
2217 dev_err(&pdev->dev, "failed to get hclk (%u)\n", err);
2218 return err;
2219 }
2220
2221 *tx_clk = devm_clk_get(&pdev->dev, "tx_clk");
2222 if (IS_ERR(*tx_clk))
2223 *tx_clk = NULL;
2224
2225 err = clk_prepare_enable(*pclk);
2226 if (err) {
2227 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2228 return err;
2229 }
2230
2231 err = clk_prepare_enable(*hclk);
2232 if (err) {
2233 dev_err(&pdev->dev, "failed to enable hclk (%u)\n", err);
2234 goto err_disable_pclk;
2235 }
2236
2237 err = clk_prepare_enable(*tx_clk);
2238 if (err) {
2239 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
2240 goto err_disable_hclk;
2241 }
2242
2243 return 0;
2244
2245 err_disable_hclk:
2246 clk_disable_unprepare(*hclk);
2247
2248 err_disable_pclk:
2249 clk_disable_unprepare(*pclk);
2250
2251 return err;
2252 }
2253
2254 static int macb_init(struct platform_device *pdev)
2255 {
2256 struct net_device *dev = platform_get_drvdata(pdev);
2257 unsigned int hw_q, q;
2258 struct macb *bp = netdev_priv(dev);
2259 struct macb_queue *queue;
2260 int err;
2261 u32 val;
2262
2263 /* set the queue register mapping once for all: queue0 has a special
2264 * register mapping but we don't want to test the queue index then
2265 * compute the corresponding register offset at run time.
2266 */
2267 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
2268 if (!(bp->queue_mask & (1 << hw_q)))
2269 continue;
2270
2271 queue = &bp->queues[q];
2272 queue->bp = bp;
2273 if (hw_q) {
2274 queue->ISR = GEM_ISR(hw_q - 1);
2275 queue->IER = GEM_IER(hw_q - 1);
2276 queue->IDR = GEM_IDR(hw_q - 1);
2277 queue->IMR = GEM_IMR(hw_q - 1);
2278 queue->TBQP = GEM_TBQP(hw_q - 1);
2279 } else {
2280 /* queue0 uses legacy registers */
2281 queue->ISR = MACB_ISR;
2282 queue->IER = MACB_IER;
2283 queue->IDR = MACB_IDR;
2284 queue->IMR = MACB_IMR;
2285 queue->TBQP = MACB_TBQP;
2286 }
2287
2288 /* get irq: here we use the linux queue index, not the hardware
2289 * queue index. the queue irq definitions in the device tree
2290 * must remove the optional gaps that could exist in the
2291 * hardware queue mask.
2292 */
2293 queue->irq = platform_get_irq(pdev, q);
2294 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
2295 IRQF_SHARED, dev->name, queue);
2296 if (err) {
2297 dev_err(&pdev->dev,
2298 "Unable to request IRQ %d (error %d)\n",
2299 queue->irq, err);
2300 return err;
2301 }
2302
2303 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
2304 q++;
2305 }
2306
2307 dev->netdev_ops = &macb_netdev_ops;
2308 netif_napi_add(dev, &bp->napi, macb_poll, 64);
2309
2310 /* setup appropriated routines according to adapter type */
2311 if (macb_is_gem(bp)) {
2312 bp->max_tx_length = GEM_MAX_TX_LEN;
2313 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
2314 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
2315 bp->macbgem_ops.mog_init_rings = gem_init_rings;
2316 bp->macbgem_ops.mog_rx = gem_rx;
2317 dev->ethtool_ops = &gem_ethtool_ops;
2318 } else {
2319 bp->max_tx_length = MACB_MAX_TX_LEN;
2320 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
2321 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
2322 bp->macbgem_ops.mog_init_rings = macb_init_rings;
2323 bp->macbgem_ops.mog_rx = macb_rx;
2324 dev->ethtool_ops = &macb_ethtool_ops;
2325 }
2326
2327 /* Set features */
2328 dev->hw_features = NETIF_F_SG;
2329 /* Checksum offload is only available on gem with packet buffer */
2330 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
2331 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
2332 if (bp->caps & MACB_CAPS_SG_DISABLED)
2333 dev->hw_features &= ~NETIF_F_SG;
2334 dev->features = dev->hw_features;
2335
2336 val = 0;
2337 if (bp->phy_interface == PHY_INTERFACE_MODE_RGMII)
2338 val = GEM_BIT(RGMII);
2339 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
2340 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2341 val = MACB_BIT(RMII);
2342 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII))
2343 val = MACB_BIT(MII);
2344
2345 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
2346 val |= MACB_BIT(CLKEN);
2347
2348 macb_or_gem_writel(bp, USRIO, val);
2349
2350 /* Set MII management clock divider */
2351 val = macb_mdc_clk_div(bp);
2352 val |= macb_dbw(bp);
2353 macb_writel(bp, NCFGR, val);
2354
2355 return 0;
2356 }
2357
2358 #if defined(CONFIG_OF)
2359 /* 1518 rounded up */
2360 #define AT91ETHER_MAX_RBUFF_SZ 0x600
2361 /* max number of receive buffers */
2362 #define AT91ETHER_MAX_RX_DESCR 9
2363
2364 /* Initialize and start the Receiver and Transmit subsystems */
2365 static int at91ether_start(struct net_device *dev)
2366 {
2367 struct macb *lp = netdev_priv(dev);
2368 dma_addr_t addr;
2369 u32 ctl;
2370 int i;
2371
2372 lp->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
2373 (AT91ETHER_MAX_RX_DESCR *
2374 sizeof(struct macb_dma_desc)),
2375 &lp->rx_ring_dma, GFP_KERNEL);
2376 if (!lp->rx_ring)
2377 return -ENOMEM;
2378
2379 lp->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
2380 AT91ETHER_MAX_RX_DESCR *
2381 AT91ETHER_MAX_RBUFF_SZ,
2382 &lp->rx_buffers_dma, GFP_KERNEL);
2383 if (!lp->rx_buffers) {
2384 dma_free_coherent(&lp->pdev->dev,
2385 AT91ETHER_MAX_RX_DESCR *
2386 sizeof(struct macb_dma_desc),
2387 lp->rx_ring, lp->rx_ring_dma);
2388 lp->rx_ring = NULL;
2389 return -ENOMEM;
2390 }
2391
2392 addr = lp->rx_buffers_dma;
2393 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
2394 lp->rx_ring[i].addr = addr;
2395 lp->rx_ring[i].ctrl = 0;
2396 addr += AT91ETHER_MAX_RBUFF_SZ;
2397 }
2398
2399 /* Set the Wrap bit on the last descriptor */
2400 lp->rx_ring[AT91ETHER_MAX_RX_DESCR - 1].addr |= MACB_BIT(RX_WRAP);
2401
2402 /* Reset buffer index */
2403 lp->rx_tail = 0;
2404
2405 /* Program address of descriptor list in Rx Buffer Queue register */
2406 macb_writel(lp, RBQP, lp->rx_ring_dma);
2407
2408 /* Enable Receive and Transmit */
2409 ctl = macb_readl(lp, NCR);
2410 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
2411
2412 return 0;
2413 }
2414
2415 /* Open the ethernet interface */
2416 static int at91ether_open(struct net_device *dev)
2417 {
2418 struct macb *lp = netdev_priv(dev);
2419 u32 ctl;
2420 int ret;
2421
2422 /* Clear internal statistics */
2423 ctl = macb_readl(lp, NCR);
2424 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
2425
2426 macb_set_hwaddr(lp);
2427
2428 ret = at91ether_start(dev);
2429 if (ret)
2430 return ret;
2431
2432 /* Enable MAC interrupts */
2433 macb_writel(lp, IER, MACB_BIT(RCOMP) |
2434 MACB_BIT(RXUBR) |
2435 MACB_BIT(ISR_TUND) |
2436 MACB_BIT(ISR_RLE) |
2437 MACB_BIT(TCOMP) |
2438 MACB_BIT(ISR_ROVR) |
2439 MACB_BIT(HRESP));
2440
2441 /* schedule a link state check */
2442 phy_start(lp->phy_dev);
2443
2444 netif_start_queue(dev);
2445
2446 return 0;
2447 }
2448
2449 /* Close the interface */
2450 static int at91ether_close(struct net_device *dev)
2451 {
2452 struct macb *lp = netdev_priv(dev);
2453 u32 ctl;
2454
2455 /* Disable Receiver and Transmitter */
2456 ctl = macb_readl(lp, NCR);
2457 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
2458
2459 /* Disable MAC interrupts */
2460 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
2461 MACB_BIT(RXUBR) |
2462 MACB_BIT(ISR_TUND) |
2463 MACB_BIT(ISR_RLE) |
2464 MACB_BIT(TCOMP) |
2465 MACB_BIT(ISR_ROVR) |
2466 MACB_BIT(HRESP));
2467
2468 netif_stop_queue(dev);
2469
2470 dma_free_coherent(&lp->pdev->dev,
2471 AT91ETHER_MAX_RX_DESCR *
2472 sizeof(struct macb_dma_desc),
2473 lp->rx_ring, lp->rx_ring_dma);
2474 lp->rx_ring = NULL;
2475
2476 dma_free_coherent(&lp->pdev->dev,
2477 AT91ETHER_MAX_RX_DESCR * AT91ETHER_MAX_RBUFF_SZ,
2478 lp->rx_buffers, lp->rx_buffers_dma);
2479 lp->rx_buffers = NULL;
2480
2481 return 0;
2482 }
2483
2484 /* Transmit packet */
2485 static int at91ether_start_xmit(struct sk_buff *skb, struct net_device *dev)
2486 {
2487 struct macb *lp = netdev_priv(dev);
2488
2489 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
2490 netif_stop_queue(dev);
2491
2492 /* Store packet information (to free when Tx completed) */
2493 lp->skb = skb;
2494 lp->skb_length = skb->len;
2495 lp->skb_physaddr = dma_map_single(NULL, skb->data, skb->len,
2496 DMA_TO_DEVICE);
2497
2498 /* Set address of the data in the Transmit Address register */
2499 macb_writel(lp, TAR, lp->skb_physaddr);
2500 /* Set length of the packet in the Transmit Control register */
2501 macb_writel(lp, TCR, skb->len);
2502
2503 } else {
2504 netdev_err(dev, "%s called, but device is busy!\n", __func__);
2505 return NETDEV_TX_BUSY;
2506 }
2507
2508 return NETDEV_TX_OK;
2509 }
2510
2511 /* Extract received frame from buffer descriptors and sent to upper layers.
2512 * (Called from interrupt context)
2513 */
2514 static void at91ether_rx(struct net_device *dev)
2515 {
2516 struct macb *lp = netdev_priv(dev);
2517 unsigned char *p_recv;
2518 struct sk_buff *skb;
2519 unsigned int pktlen;
2520
2521 while (lp->rx_ring[lp->rx_tail].addr & MACB_BIT(RX_USED)) {
2522 p_recv = lp->rx_buffers + lp->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
2523 pktlen = MACB_BF(RX_FRMLEN, lp->rx_ring[lp->rx_tail].ctrl);
2524 skb = netdev_alloc_skb(dev, pktlen + 2);
2525 if (skb) {
2526 skb_reserve(skb, 2);
2527 memcpy(skb_put(skb, pktlen), p_recv, pktlen);
2528
2529 skb->protocol = eth_type_trans(skb, dev);
2530 lp->stats.rx_packets++;
2531 lp->stats.rx_bytes += pktlen;
2532 netif_rx(skb);
2533 } else {
2534 lp->stats.rx_dropped++;
2535 }
2536
2537 if (lp->rx_ring[lp->rx_tail].ctrl & MACB_BIT(RX_MHASH_MATCH))
2538 lp->stats.multicast++;
2539
2540 /* reset ownership bit */
2541 lp->rx_ring[lp->rx_tail].addr &= ~MACB_BIT(RX_USED);
2542
2543 /* wrap after last buffer */
2544 if (lp->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
2545 lp->rx_tail = 0;
2546 else
2547 lp->rx_tail++;
2548 }
2549 }
2550
2551 /* MAC interrupt handler */
2552 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
2553 {
2554 struct net_device *dev = dev_id;
2555 struct macb *lp = netdev_priv(dev);
2556 u32 intstatus, ctl;
2557
2558 /* MAC Interrupt Status register indicates what interrupts are pending.
2559 * It is automatically cleared once read.
2560 */
2561 intstatus = macb_readl(lp, ISR);
2562
2563 /* Receive complete */
2564 if (intstatus & MACB_BIT(RCOMP))
2565 at91ether_rx(dev);
2566
2567 /* Transmit complete */
2568 if (intstatus & MACB_BIT(TCOMP)) {
2569 /* The TCOM bit is set even if the transmission failed */
2570 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
2571 lp->stats.tx_errors++;
2572
2573 if (lp->skb) {
2574 dev_kfree_skb_irq(lp->skb);
2575 lp->skb = NULL;
2576 dma_unmap_single(NULL, lp->skb_physaddr,
2577 lp->skb_length, DMA_TO_DEVICE);
2578 lp->stats.tx_packets++;
2579 lp->stats.tx_bytes += lp->skb_length;
2580 }
2581 netif_wake_queue(dev);
2582 }
2583
2584 /* Work-around for EMAC Errata section 41.3.1 */
2585 if (intstatus & MACB_BIT(RXUBR)) {
2586 ctl = macb_readl(lp, NCR);
2587 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
2588 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
2589 }
2590
2591 if (intstatus & MACB_BIT(ISR_ROVR))
2592 netdev_err(dev, "ROVR error\n");
2593
2594 return IRQ_HANDLED;
2595 }
2596
2597 #ifdef CONFIG_NET_POLL_CONTROLLER
2598 static void at91ether_poll_controller(struct net_device *dev)
2599 {
2600 unsigned long flags;
2601
2602 local_irq_save(flags);
2603 at91ether_interrupt(dev->irq, dev);
2604 local_irq_restore(flags);
2605 }
2606 #endif
2607
2608 static const struct net_device_ops at91ether_netdev_ops = {
2609 .ndo_open = at91ether_open,
2610 .ndo_stop = at91ether_close,
2611 .ndo_start_xmit = at91ether_start_xmit,
2612 .ndo_get_stats = macb_get_stats,
2613 .ndo_set_rx_mode = macb_set_rx_mode,
2614 .ndo_set_mac_address = eth_mac_addr,
2615 .ndo_do_ioctl = macb_ioctl,
2616 .ndo_validate_addr = eth_validate_addr,
2617 .ndo_change_mtu = eth_change_mtu,
2618 #ifdef CONFIG_NET_POLL_CONTROLLER
2619 .ndo_poll_controller = at91ether_poll_controller,
2620 #endif
2621 };
2622
2623 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
2624 struct clk **hclk, struct clk **tx_clk)
2625 {
2626 int err;
2627
2628 *hclk = NULL;
2629 *tx_clk = NULL;
2630
2631 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
2632 if (IS_ERR(*pclk))
2633 return PTR_ERR(*pclk);
2634
2635 err = clk_prepare_enable(*pclk);
2636 if (err) {
2637 dev_err(&pdev->dev, "failed to enable pclk (%u)\n", err);
2638 return err;
2639 }
2640
2641 return 0;
2642 }
2643
2644 static int at91ether_init(struct platform_device *pdev)
2645 {
2646 struct net_device *dev = platform_get_drvdata(pdev);
2647 struct macb *bp = netdev_priv(dev);
2648 int err;
2649 u32 reg;
2650
2651 dev->netdev_ops = &at91ether_netdev_ops;
2652 dev->ethtool_ops = &macb_ethtool_ops;
2653
2654 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
2655 0, dev->name, dev);
2656 if (err)
2657 return err;
2658
2659 macb_writel(bp, NCR, 0);
2660
2661 reg = MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG);
2662 if (bp->phy_interface == PHY_INTERFACE_MODE_RMII)
2663 reg |= MACB_BIT(RM9200_RMII);
2664
2665 macb_writel(bp, NCFGR, reg);
2666
2667 return 0;
2668 }
2669
2670 static const struct macb_config at91sam9260_config = {
2671 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII,
2672 .clk_init = macb_clk_init,
2673 .init = macb_init,
2674 };
2675
2676 static const struct macb_config pc302gem_config = {
2677 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2678 .dma_burst_length = 16,
2679 .clk_init = macb_clk_init,
2680 .init = macb_init,
2681 };
2682
2683 static const struct macb_config sama5d3_config = {
2684 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
2685 .dma_burst_length = 16,
2686 .clk_init = macb_clk_init,
2687 .init = macb_init,
2688 };
2689
2690 static const struct macb_config sama5d4_config = {
2691 .caps = 0,
2692 .dma_burst_length = 4,
2693 .clk_init = macb_clk_init,
2694 .init = macb_init,
2695 };
2696
2697 static const struct macb_config emac_config = {
2698 .clk_init = at91ether_clk_init,
2699 .init = at91ether_init,
2700 };
2701
2702 static const struct of_device_id macb_dt_ids[] = {
2703 { .compatible = "cdns,at32ap7000-macb" },
2704 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
2705 { .compatible = "cdns,macb" },
2706 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
2707 { .compatible = "cdns,gem", .data = &pc302gem_config },
2708 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
2709 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
2710 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
2711 { .compatible = "cdns,emac", .data = &emac_config },
2712 { /* sentinel */ }
2713 };
2714 MODULE_DEVICE_TABLE(of, macb_dt_ids);
2715 #endif /* CONFIG_OF */
2716
2717 static int macb_probe(struct platform_device *pdev)
2718 {
2719 int (*clk_init)(struct platform_device *, struct clk **,
2720 struct clk **, struct clk **)
2721 = macb_clk_init;
2722 int (*init)(struct platform_device *) = macb_init;
2723 struct device_node *np = pdev->dev.of_node;
2724 const struct macb_config *macb_config = NULL;
2725 struct clk *pclk, *hclk, *tx_clk;
2726 unsigned int queue_mask, num_queues;
2727 struct macb_platform_data *pdata;
2728 struct phy_device *phydev;
2729 struct net_device *dev;
2730 struct resource *regs;
2731 void __iomem *mem;
2732 const char *mac;
2733 struct macb *bp;
2734 int err;
2735
2736 if (np) {
2737 const struct of_device_id *match;
2738
2739 match = of_match_node(macb_dt_ids, np);
2740 if (match && match->data) {
2741 macb_config = match->data;
2742 clk_init = macb_config->clk_init;
2743 init = macb_config->init;
2744 }
2745 }
2746
2747 err = clk_init(pdev, &pclk, &hclk, &tx_clk);
2748 if (err)
2749 return err;
2750
2751 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2752 mem = devm_ioremap_resource(&pdev->dev, regs);
2753 if (IS_ERR(mem)) {
2754 err = PTR_ERR(mem);
2755 goto err_disable_clocks;
2756 }
2757
2758 macb_probe_queues(mem, &queue_mask, &num_queues);
2759 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
2760 if (!dev) {
2761 err = -ENOMEM;
2762 goto err_disable_clocks;
2763 }
2764
2765 dev->base_addr = regs->start;
2766
2767 SET_NETDEV_DEV(dev, &pdev->dev);
2768
2769 bp = netdev_priv(dev);
2770 bp->pdev = pdev;
2771 bp->dev = dev;
2772 bp->regs = mem;
2773 bp->num_queues = num_queues;
2774 bp->queue_mask = queue_mask;
2775 if (macb_config)
2776 bp->dma_burst_length = macb_config->dma_burst_length;
2777 bp->pclk = pclk;
2778 bp->hclk = hclk;
2779 bp->tx_clk = tx_clk;
2780 spin_lock_init(&bp->lock);
2781
2782 /* setup capabilities */
2783 macb_configure_caps(bp, macb_config);
2784
2785 platform_set_drvdata(pdev, dev);
2786
2787 dev->irq = platform_get_irq(pdev, 0);
2788 if (dev->irq < 0) {
2789 err = dev->irq;
2790 goto err_disable_clocks;
2791 }
2792
2793 mac = of_get_mac_address(np);
2794 if (mac)
2795 memcpy(bp->dev->dev_addr, mac, ETH_ALEN);
2796 else
2797 macb_get_hwaddr(bp);
2798
2799 err = of_get_phy_mode(np);
2800 if (err < 0) {
2801 pdata = dev_get_platdata(&pdev->dev);
2802 if (pdata && pdata->is_rmii)
2803 bp->phy_interface = PHY_INTERFACE_MODE_RMII;
2804 else
2805 bp->phy_interface = PHY_INTERFACE_MODE_MII;
2806 } else {
2807 bp->phy_interface = err;
2808 }
2809
2810 /* IP specific init */
2811 err = init(pdev);
2812 if (err)
2813 goto err_out_free_netdev;
2814
2815 err = register_netdev(dev);
2816 if (err) {
2817 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
2818 goto err_out_unregister_netdev;
2819 }
2820
2821 err = macb_mii_init(bp);
2822 if (err)
2823 goto err_out_unregister_netdev;
2824
2825 netif_carrier_off(dev);
2826
2827 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
2828 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
2829 dev->base_addr, dev->irq, dev->dev_addr);
2830
2831 phydev = bp->phy_dev;
2832 netdev_info(dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n",
2833 phydev->drv->name, dev_name(&phydev->dev), phydev->irq);
2834
2835 return 0;
2836
2837 err_out_unregister_netdev:
2838 unregister_netdev(dev);
2839
2840 err_out_free_netdev:
2841 free_netdev(dev);
2842
2843 err_disable_clocks:
2844 clk_disable_unprepare(tx_clk);
2845 clk_disable_unprepare(hclk);
2846 clk_disable_unprepare(pclk);
2847
2848 return err;
2849 }
2850
2851 static int macb_remove(struct platform_device *pdev)
2852 {
2853 struct net_device *dev;
2854 struct macb *bp;
2855
2856 dev = platform_get_drvdata(pdev);
2857
2858 if (dev) {
2859 bp = netdev_priv(dev);
2860 if (bp->phy_dev)
2861 phy_disconnect(bp->phy_dev);
2862 mdiobus_unregister(bp->mii_bus);
2863 kfree(bp->mii_bus->irq);
2864 mdiobus_free(bp->mii_bus);
2865 unregister_netdev(dev);
2866 clk_disable_unprepare(bp->tx_clk);
2867 clk_disable_unprepare(bp->hclk);
2868 clk_disable_unprepare(bp->pclk);
2869 free_netdev(dev);
2870 }
2871
2872 return 0;
2873 }
2874
2875 static int __maybe_unused macb_suspend(struct device *dev)
2876 {
2877 struct platform_device *pdev = to_platform_device(dev);
2878 struct net_device *netdev = platform_get_drvdata(pdev);
2879 struct macb *bp = netdev_priv(netdev);
2880
2881 netif_carrier_off(netdev);
2882 netif_device_detach(netdev);
2883
2884 clk_disable_unprepare(bp->tx_clk);
2885 clk_disable_unprepare(bp->hclk);
2886 clk_disable_unprepare(bp->pclk);
2887
2888 return 0;
2889 }
2890
2891 static int __maybe_unused macb_resume(struct device *dev)
2892 {
2893 struct platform_device *pdev = to_platform_device(dev);
2894 struct net_device *netdev = platform_get_drvdata(pdev);
2895 struct macb *bp = netdev_priv(netdev);
2896
2897 clk_prepare_enable(bp->pclk);
2898 clk_prepare_enable(bp->hclk);
2899 clk_prepare_enable(bp->tx_clk);
2900
2901 netif_device_attach(netdev);
2902
2903 return 0;
2904 }
2905
2906 static SIMPLE_DEV_PM_OPS(macb_pm_ops, macb_suspend, macb_resume);
2907
2908 static struct platform_driver macb_driver = {
2909 .probe = macb_probe,
2910 .remove = macb_remove,
2911 .driver = {
2912 .name = "macb",
2913 .of_match_table = of_match_ptr(macb_dt_ids),
2914 .pm = &macb_pm_ops,
2915 },
2916 };
2917
2918 module_platform_driver(macb_driver);
2919
2920 MODULE_LICENSE("GPL");
2921 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
2922 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
2923 MODULE_ALIAS("platform:macb");
Linux kernel - Deliverables
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