drivers/net/ethernet/cavium/liquidio/cn68xx_regs.h

   1 /**********************************************************************
   2 * Author: Cavium, Inc.
   3 *
   4 * Contact: support@cavium.com
   5 *          Please include "LiquidIO" in the subject.
   6 *
   7 * Copyright (c) 2003-2015 Cavium, Inc.
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * This file may also be available under a different license from Cavium.
  20 * Contact Cavium, Inc. for more information
  21 **********************************************************************/
  22
  23 /*! \file cn68xx_regs.h
  24  *  \brief Host Driver: Register Address and Register Mask values for
  25  *  Octeon CN68XX devices. The register map for CN66XX is the same
  26  *  for most registers. This file has the other registers that are
  27  *  68XX-specific.
  28  */
  29
  30 #ifndef __CN68XX_REGS_H__
  31 #define __CN68XX_REGS_H__
  32
  33 /*###################### REQUEST QUEUE #########################*/
  34
  35 #define    CN68XX_SLI_IQ_PORT0_PKIND             0x0800
  36
  37 #define    CN68XX_SLI_IQ_PORT_PKIND(iq)           \
  38         (CN68XX_SLI_IQ_PORT0_PKIND + ((iq) * CN6XXX_IQ_OFFSET))
  39
  40 /*############################ OUTPUT QUEUE #########################*/
  41
  42 /* Starting pipe number and number of pipes used by the SLI packet output. */
  43 #define    CN68XX_SLI_TX_PIPE                    0x1230
  44
  45 /*######################## INTERRUPTS #########################*/
  46
  47 /*------------------ Interrupt Masks ----------------*/
  48 #define    CN68XX_INTR_PIPE_ERR                  BIT_ULL(61)
  49
  50 #endif