1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2015 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
24 * @file octeon_console.c
26 #include <linux/pci.h>
27 #include <linux/netdevice.h>
28 #include <linux/crc32.h>
29 #include "liquidio_common.h"
30 #include "octeon_droq.h"
31 #include "octeon_iq.h"
32 #include "response_manager.h"
33 #include "octeon_device.h"
34 #include "liquidio_image.h"
35 #include "octeon_mem_ops.h"
37 static void octeon_remote_lock(void);
38 static void octeon_remote_unlock(void);
39 static u64
cvmx_bootmem_phy_named_block_find(struct octeon_device
*oct
,
42 static int octeon_console_read(struct octeon_device
*oct
, u32 console_num
,
43 char *buffer
, u32 buf_size
);
44 static u32 console_bitmask
;
45 module_param(console_bitmask
, int, 0644);
46 MODULE_PARM_DESC(console_bitmask
,
47 "Bitmask indicating which consoles have debug output redirected to syslog.");
49 #define MIN(a, b) min((a), (b))
50 #define CAST_ULL(v) ((u64)(v))
52 #define BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR 0x0006c008
53 #define BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR 0x0006c004
54 #define BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR 0x0006c000
55 #define BOOTLOADER_PCI_READ_DESC_ADDR 0x0006c100
56 #define BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN 248
58 #define OCTEON_PCI_IO_BUF_OWNER_OCTEON 0x00000001
59 #define OCTEON_PCI_IO_BUF_OWNER_HOST 0x00000002
61 /** Can change without breaking ABI */
62 #define CVMX_BOOTMEM_NUM_NAMED_BLOCKS 64
64 /** minimum alignment of bootmem alloced blocks */
65 #define CVMX_BOOTMEM_ALIGNMENT_SIZE (16ull)
67 /** CVMX bootmem descriptor major version */
68 #define CVMX_BOOTMEM_DESC_MAJ_VER 3
69 /* CVMX bootmem descriptor minor version */
70 #define CVMX_BOOTMEM_DESC_MIN_VER 0
72 /* Current versions */
73 #define OCTEON_PCI_CONSOLE_MAJOR_VERSION 1
74 #define OCTEON_PCI_CONSOLE_MINOR_VERSION 0
75 #define OCTEON_PCI_CONSOLE_BLOCK_NAME "__pci_console"
76 #define OCTEON_CONSOLE_POLL_INTERVAL_MS 100 /* 10 times per second */
78 /* First three members of cvmx_bootmem_desc are left in original
79 ** positions for backwards compatibility.
80 ** Assumes big endian target
82 struct cvmx_bootmem_desc
{
83 /** spinlock to control access to list */
86 /** flags for indicating various conditions */
91 /** incremented changed when incompatible changes made */
94 /** incremented changed when compatible changes made,
95 * reset to zero when major incremented
102 /** number of elements in named blocks array */
105 /** length of name array in bootmem blocks */
106 u32 named_block_name_len
;
108 /** address of named memory block descriptors */
109 u64 named_block_array_addr
;
112 /* Structure that defines a single console.
114 * Note: when read_index == write_index, the buffer is empty.
115 * The actual usable size of each console is console_buf_size -1;
117 struct octeon_pci_console
{
119 u32 input_read_index
;
120 u32 input_write_index
;
121 u64 output_base_addr
;
122 u32 output_read_index
;
123 u32 output_write_index
;
128 /* This is the main container structure that contains all the information
129 * about all PCI consoles. The address of this structure is passed to various
130 * routines that operation on PCI consoles.
132 struct octeon_pci_console_desc
{
139 /* must be 64 bit aligned here... */
140 /* Array of addresses of octeon_pci_console structures */
141 u64 console_addr_array
[0];
142 /* Implicit storage for console_addr_array */
146 * This macro returns the size of a member of a structure.
147 * Logically it is the same as "sizeof(s::field)" in C++, but
148 * C lacks the "::" operator.
150 #define SIZEOF_FIELD(s, field) sizeof(((s *)NULL)->field)
153 * This macro returns a member of the cvmx_bootmem_desc
154 * structure. These members can't be directly addressed as
155 * they might be in memory not directly reachable. In the case
156 * where bootmem is compiled with LINUX_HOST, the structure
157 * itself might be located on a remote Octeon. The argument
158 * "field" is the member name of the cvmx_bootmem_desc to read.
159 * Regardless of the type of the field, the return type is always
162 #define CVMX_BOOTMEM_DESC_GET_FIELD(oct, field) \
163 __cvmx_bootmem_desc_get(oct, oct->bootmem_desc_addr, \
164 offsetof(struct cvmx_bootmem_desc, field), \
165 SIZEOF_FIELD(struct cvmx_bootmem_desc, field))
167 #define __cvmx_bootmem_lock(flags) (flags = flags)
168 #define __cvmx_bootmem_unlock(flags) (flags = flags)
171 * This macro returns a member of the
172 * cvmx_bootmem_named_block_desc structure. These members can't
173 * be directly addressed as they might be in memory not directly
174 * reachable. In the case where bootmem is compiled with
175 * LINUX_HOST, the structure itself might be located on a remote
176 * Octeon. The argument "field" is the member name of the
177 * cvmx_bootmem_named_block_desc to read. Regardless of the type
178 * of the field, the return type is always a u64. The "addr"
179 * parameter is the physical address of the structure.
181 #define CVMX_BOOTMEM_NAMED_GET_FIELD(oct, addr, field) \
182 __cvmx_bootmem_desc_get(oct, addr, \
183 offsetof(struct cvmx_bootmem_named_block_desc, field), \
184 SIZEOF_FIELD(struct cvmx_bootmem_named_block_desc, field))
186 * \brief determines if a given console has debug enabled.
187 * @param console console to check
188 * @returns 1 = enabled. 0 otherwise
190 static int octeon_console_debug_enabled(u32 console
)
192 return (console_bitmask
>> (console
)) & 0x1;
196 * This function is the implementation of the get macros defined
197 * for individual structure members. The argument are generated
198 * by the macros inorder to read only the needed memory.
200 * @param oct Pointer to current octeon device
201 * @param base 64bit physical address of the complete structure
202 * @param offset Offset from the beginning of the structure to the member being
204 * @param size Size of the structure member.
206 * @return Value of the structure member promoted into a u64.
208 static inline u64
__cvmx_bootmem_desc_get(struct octeon_device
*oct
,
213 base
= (1ull << 63) | (base
+ offset
);
216 return octeon_read_device_mem32(oct
, base
);
218 return octeon_read_device_mem64(oct
, base
);
225 * This function retrieves the string name of a named block. It is
226 * more complicated than a simple memcpy() since the named block
227 * descriptor may not be directly accessible.
229 * @param addr Physical address of the named block descriptor
230 * @param str String to receive the named block string name
231 * @param len Length of the string buffer, which must match the length
232 * stored in the bootmem descriptor.
234 static void CVMX_BOOTMEM_NAMED_GET_NAME(struct octeon_device
*oct
,
239 addr
+= offsetof(struct cvmx_bootmem_named_block_desc
, name
);
240 octeon_pci_read_core_mem(oct
, addr
, (u8
*)str
, len
);
244 /* See header file for descriptions of functions */
247 * Check the version information on the bootmem descriptor
250 * Exact major version to check against. A zero means
251 * check that the version supports named blocks.
253 * @return Zero if the version is correct. Negative if the version is
254 * incorrect. Failures also cause a message to be displayed.
256 static int __cvmx_bootmem_check_version(struct octeon_device
*oct
,
262 if (!oct
->bootmem_desc_addr
)
263 oct
->bootmem_desc_addr
=
264 octeon_read_device_mem64(oct
,
265 BOOTLOADER_PCI_READ_DESC_ADDR
);
267 (u32
)CVMX_BOOTMEM_DESC_GET_FIELD(oct
, major_version
);
269 (u32
)CVMX_BOOTMEM_DESC_GET_FIELD(oct
, minor_version
);
270 dev_dbg(&oct
->pci_dev
->dev
, "%s: major_version=%d\n", __func__
,
272 if ((major_version
> 3) ||
273 (exact_match
&& major_version
!= exact_match
)) {
274 dev_err(&oct
->pci_dev
->dev
, "bootmem ver mismatch %d.%d addr:0x%llx\n",
275 major_version
, minor_version
,
276 CAST_ULL(oct
->bootmem_desc_addr
));
283 static const struct cvmx_bootmem_named_block_desc
284 *__cvmx_bootmem_find_named_block_flags(struct octeon_device
*oct
,
285 const char *name
, u32 flags
)
287 struct cvmx_bootmem_named_block_desc
*desc
=
288 &oct
->bootmem_named_block_desc
;
289 u64 named_addr
= cvmx_bootmem_phy_named_block_find(oct
, name
, flags
);
292 desc
->base_addr
= CVMX_BOOTMEM_NAMED_GET_FIELD(oct
, named_addr
,
295 CVMX_BOOTMEM_NAMED_GET_FIELD(oct
, named_addr
, size
);
296 strncpy(desc
->name
, name
, sizeof(desc
->name
));
297 desc
->name
[sizeof(desc
->name
) - 1] = 0;
298 return &oct
->bootmem_named_block_desc
;
304 static u64
cvmx_bootmem_phy_named_block_find(struct octeon_device
*oct
,
310 __cvmx_bootmem_lock(flags
);
311 if (!__cvmx_bootmem_check_version(oct
, 3)) {
313 u64 named_block_array_addr
=
314 CVMX_BOOTMEM_DESC_GET_FIELD(oct
,
315 named_block_array_addr
);
316 u32 num_blocks
= (u32
)
317 CVMX_BOOTMEM_DESC_GET_FIELD(oct
, nb_num_blocks
);
318 u32 name_length
= (u32
)
319 CVMX_BOOTMEM_DESC_GET_FIELD(oct
, named_block_name_len
);
320 u64 named_addr
= named_block_array_addr
;
322 for (i
= 0; i
< num_blocks
; i
++) {
324 CVMX_BOOTMEM_NAMED_GET_FIELD(oct
, named_addr
,
326 if (name
&& named_size
) {
328 kmalloc(name_length
+ 1, GFP_KERNEL
);
332 CVMX_BOOTMEM_NAMED_GET_NAME(oct
, named_addr
,
335 if (!strncmp(name
, name_tmp
, name_length
)) {
341 } else if (!name
&& !named_size
) {
347 sizeof(struct cvmx_bootmem_named_block_desc
);
350 __cvmx_bootmem_unlock(flags
);
355 * Find a named block on the remote Octeon
357 * @param name Name of block to find
358 * @param base_addr Address the block is at (OUTPUT)
359 * @param size The size of the block (OUTPUT)
361 * @return Zero on success, One on failure.
363 static int octeon_named_block_find(struct octeon_device
*oct
, const char *name
,
364 u64
*base_addr
, u64
*size
)
366 const struct cvmx_bootmem_named_block_desc
*named_block
;
368 octeon_remote_lock();
369 named_block
= __cvmx_bootmem_find_named_block_flags(oct
, name
, 0);
370 octeon_remote_unlock();
372 *base_addr
= named_block
->base_addr
;
373 *size
= named_block
->size
;
379 static void octeon_remote_lock(void)
381 /* fill this in if any sharing is needed */
384 static void octeon_remote_unlock(void)
386 /* fill this in if any sharing is needed */
389 int octeon_console_send_cmd(struct octeon_device
*oct
, char *cmd_str
,
392 u32 len
= (u32
)strlen(cmd_str
);
394 dev_dbg(&oct
->pci_dev
->dev
, "sending \"%s\" to bootloader\n", cmd_str
);
396 if (len
> BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN
- 1) {
397 dev_err(&oct
->pci_dev
->dev
, "Command string too long, max length is: %d\n",
398 BOOTLOADER_PCI_WRITE_BUFFER_STR_LEN
- 1);
402 if (octeon_wait_for_bootloader(oct
, wait_hundredths
) != 0) {
403 dev_err(&oct
->pci_dev
->dev
, "Bootloader not ready for command.\n");
407 /* Write command to bootloader */
408 octeon_remote_lock();
409 octeon_pci_write_core_mem(oct
, BOOTLOADER_PCI_READ_BUFFER_DATA_ADDR
,
411 octeon_write_device_mem32(oct
, BOOTLOADER_PCI_READ_BUFFER_LEN_ADDR
,
413 octeon_write_device_mem32(oct
, BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR
,
414 OCTEON_PCI_IO_BUF_OWNER_OCTEON
);
416 /* Bootloader should accept command very quickly
417 * if it really was ready
419 if (octeon_wait_for_bootloader(oct
, 200) != 0) {
420 octeon_remote_unlock();
421 dev_err(&oct
->pci_dev
->dev
, "Bootloader did not accept command.\n");
424 octeon_remote_unlock();
428 int octeon_wait_for_bootloader(struct octeon_device
*oct
,
429 u32 wait_time_hundredths
)
431 dev_dbg(&oct
->pci_dev
->dev
, "waiting %d0 ms for bootloader\n",
432 wait_time_hundredths
);
434 if (octeon_mem_access_ok(oct
))
437 while (wait_time_hundredths
> 0 &&
438 octeon_read_device_mem32(oct
,
439 BOOTLOADER_PCI_READ_BUFFER_OWNER_ADDR
)
440 != OCTEON_PCI_IO_BUF_OWNER_HOST
) {
441 if (--wait_time_hundredths
<= 0)
443 schedule_timeout_uninterruptible(HZ
/ 100);
448 static void octeon_console_handle_result(struct octeon_device
*oct
,
451 struct octeon_console
*console
;
453 console
= &oct
->console
[console_num
];
455 console
->waiting
= 0;
458 static char console_buffer
[OCTEON_CONSOLE_MAX_READ_BYTES
];
460 static void output_console_line(struct octeon_device
*oct
,
461 struct octeon_console
*console
,
463 char *console_buffer
,
469 line
= console_buffer
;
470 for (i
= 0; i
< bytes_read
; i
++) {
471 /* Output a line at a time, prefixed */
472 if (console_buffer
[i
] == '\n') {
473 console_buffer
[i
] = '\0';
474 if (console
->leftover
[0]) {
475 dev_info(&oct
->pci_dev
->dev
, "%lu: %s%s\n",
476 console_num
, console
->leftover
,
478 console
->leftover
[0] = '\0';
480 dev_info(&oct
->pci_dev
->dev
, "%lu: %s\n",
483 line
= &console_buffer
[i
+ 1];
487 /* Save off any leftovers */
488 if (line
!= &console_buffer
[bytes_read
]) {
489 console_buffer
[bytes_read
] = '\0';
490 strcpy(console
->leftover
, line
);
494 static void check_console(struct work_struct
*work
)
496 s32 bytes_read
, tries
, total_read
;
497 struct octeon_console
*console
;
498 struct cavium_wk
*wk
= (struct cavium_wk
*)work
;
499 struct octeon_device
*oct
= (struct octeon_device
*)wk
->ctxptr
;
500 u32 console_num
= (u32
)wk
->ctxul
;
503 console
= &oct
->console
[console_num
];
508 /* Take console output regardless of whether it will
512 octeon_console_read(oct
, console_num
, console_buffer
,
513 sizeof(console_buffer
) - 1);
514 if (bytes_read
> 0) {
515 total_read
+= bytes_read
;
516 if (console
->waiting
)
517 octeon_console_handle_result(oct
, console_num
);
518 if (octeon_console_debug_enabled(console_num
)) {
519 output_console_line(oct
, console
, console_num
,
520 console_buffer
, bytes_read
);
522 } else if (bytes_read
< 0) {
523 dev_err(&oct
->pci_dev
->dev
, "Error reading console %u, ret=%d\n",
524 console_num
, bytes_read
);
528 } while ((bytes_read
> 0) && (tries
< 16));
530 /* If nothing is read after polling the console,
531 * output any leftovers if any
533 if (octeon_console_debug_enabled(console_num
) &&
534 (total_read
== 0) && (console
->leftover
[0])) {
535 dev_info(&oct
->pci_dev
->dev
, "%u: %s\n",
536 console_num
, console
->leftover
);
537 console
->leftover
[0] = '\0';
540 delay
= OCTEON_CONSOLE_POLL_INTERVAL_MS
;
542 schedule_delayed_work(&wk
->work
, msecs_to_jiffies(delay
));
545 int octeon_init_consoles(struct octeon_device
*oct
)
550 ret
= octeon_mem_access_ok(oct
);
552 dev_err(&oct
->pci_dev
->dev
, "Memory access not okay'\n");
556 ret
= octeon_named_block_find(oct
, OCTEON_PCI_CONSOLE_BLOCK_NAME
, &addr
,
559 dev_err(&oct
->pci_dev
->dev
, "Could not find console '%s'\n",
560 OCTEON_PCI_CONSOLE_BLOCK_NAME
);
564 /* num_consoles > 0, is an indication that the consoles
567 oct
->num_consoles
= octeon_read_device_mem32(oct
,
568 addr
+ offsetof(struct octeon_pci_console_desc
,
570 oct
->console_desc_addr
= addr
;
572 dev_dbg(&oct
->pci_dev
->dev
, "Initialized consoles. %d available\n",
578 int octeon_add_console(struct octeon_device
*oct
, u32 console_num
)
583 struct delayed_work
*work
;
584 struct octeon_console
*console
;
586 if (console_num
>= oct
->num_consoles
) {
587 dev_err(&oct
->pci_dev
->dev
,
588 "trying to read from console number %d when only 0 to %d exist\n",
589 console_num
, oct
->num_consoles
);
591 console
= &oct
->console
[console_num
];
593 console
->waiting
= 0;
595 coreaddr
= oct
->console_desc_addr
+ console_num
* 8 +
596 offsetof(struct octeon_pci_console_desc
,
598 console
->addr
= octeon_read_device_mem64(oct
, coreaddr
);
599 coreaddr
= console
->addr
+ offsetof(struct octeon_pci_console
,
601 console
->buffer_size
= octeon_read_device_mem32(oct
, coreaddr
);
602 coreaddr
= console
->addr
+ offsetof(struct octeon_pci_console
,
604 console
->input_base_addr
=
605 octeon_read_device_mem64(oct
, coreaddr
);
606 coreaddr
= console
->addr
+ offsetof(struct octeon_pci_console
,
608 console
->output_base_addr
=
609 octeon_read_device_mem64(oct
, coreaddr
);
610 console
->leftover
[0] = '\0';
612 work
= &oct
->console_poll_work
[console_num
].work
;
614 INIT_DELAYED_WORK(work
, check_console
);
615 oct
->console_poll_work
[console_num
].ctxptr
= (void *)oct
;
616 oct
->console_poll_work
[console_num
].ctxul
= console_num
;
617 delay
= OCTEON_CONSOLE_POLL_INTERVAL_MS
;
618 schedule_delayed_work(work
, msecs_to_jiffies(delay
));
620 if (octeon_console_debug_enabled(console_num
)) {
621 ret
= octeon_console_send_cmd(oct
,
622 "setenv pci_console_active 1",
633 * Removes all consoles
635 * @param oct octeon device
637 void octeon_remove_consoles(struct octeon_device
*oct
)
640 struct octeon_console
*console
;
642 for (i
= 0; i
< oct
->num_consoles
; i
++) {
643 console
= &oct
->console
[i
];
645 if (!console
->active
)
648 cancel_delayed_work_sync(&oct
->console_poll_work
[i
].
651 console
->buffer_size
= 0;
652 console
->input_base_addr
= 0;
653 console
->output_base_addr
= 0;
656 oct
->num_consoles
= 0;
659 static inline int octeon_console_free_bytes(u32 buffer_size
,
663 if (rd_idx
>= buffer_size
|| wr_idx
>= buffer_size
)
666 return ((buffer_size
- 1) - (wr_idx
- rd_idx
)) % buffer_size
;
669 static inline int octeon_console_avail_bytes(u32 buffer_size
,
673 if (rd_idx
>= buffer_size
|| wr_idx
>= buffer_size
)
676 return buffer_size
- 1 -
677 octeon_console_free_bytes(buffer_size
, wr_idx
, rd_idx
);
680 static int octeon_console_read(struct octeon_device
*oct
, u32 console_num
,
681 char *buffer
, u32 buf_size
)
685 struct octeon_console
*console
;
687 if (console_num
>= oct
->num_consoles
) {
688 dev_err(&oct
->pci_dev
->dev
, "Attempted to read from disabled console %d\n",
693 console
= &oct
->console
[console_num
];
695 /* Check to see if any data is available.
696 * Maybe optimize this with 64-bit read.
698 rd_idx
= octeon_read_device_mem32(oct
, console
->addr
+
699 offsetof(struct octeon_pci_console
, output_read_index
));
700 wr_idx
= octeon_read_device_mem32(oct
, console
->addr
+
701 offsetof(struct octeon_pci_console
, output_write_index
));
703 bytes_to_read
= octeon_console_avail_bytes(console
->buffer_size
,
705 if (bytes_to_read
<= 0)
706 return bytes_to_read
;
708 bytes_to_read
= MIN(bytes_to_read
, (s32
)buf_size
);
710 /* Check to see if what we want to read is not contiguous, and limit
711 * ourselves to the contiguous block
713 if (rd_idx
+ bytes_to_read
>= console
->buffer_size
)
714 bytes_to_read
= console
->buffer_size
- rd_idx
;
716 octeon_pci_read_core_mem(oct
, console
->output_base_addr
+ rd_idx
,
717 (u8
*)buffer
, bytes_to_read
);
718 octeon_write_device_mem32(oct
, console
->addr
+
719 offsetof(struct octeon_pci_console
,
721 (rd_idx
+ bytes_to_read
) %
722 console
->buffer_size
);
724 return bytes_to_read
;
727 #define FBUF_SIZE (4 * 1024 * 1024)
730 int octeon_download_firmware(struct octeon_device
*oct
, const u8
*data
,
738 struct octeon_firmware_file_header
*h
;
741 if (size
< sizeof(struct octeon_firmware_file_header
)) {
742 dev_err(&oct
->pci_dev
->dev
, "Firmware file too small (%d < %d).\n",
744 (u32
)sizeof(struct octeon_firmware_file_header
));
748 h
= (struct octeon_firmware_file_header
*)data
;
750 if (be32_to_cpu(h
->magic
) != LIO_NIC_MAGIC
) {
751 dev_err(&oct
->pci_dev
->dev
, "Unrecognized firmware file.\n");
755 crc32_result
= crc32((unsigned int)~0, data
,
756 sizeof(struct octeon_firmware_file_header
) -
758 if (crc32_result
!= be32_to_cpu(h
->crc32
)) {
759 dev_err(&oct
->pci_dev
->dev
, "Firmware CRC mismatch (0x%08x != 0x%08x).\n",
760 crc32_result
, be32_to_cpu(h
->crc32
));
764 if (strncmp(LIQUIDIO_PACKAGE
, h
->version
, strlen(LIQUIDIO_PACKAGE
))) {
765 dev_err(&oct
->pci_dev
->dev
, "Unmatched firmware package type. Expected %s, got %s.\n",
766 LIQUIDIO_PACKAGE
, h
->version
);
770 if (memcmp(LIQUIDIO_BASE_VERSION
, h
->version
+ strlen(LIQUIDIO_PACKAGE
),
771 strlen(LIQUIDIO_BASE_VERSION
))) {
772 dev_err(&oct
->pci_dev
->dev
, "Unmatched firmware version. Expected %s.x, got %s.\n",
773 LIQUIDIO_BASE_VERSION
,
774 h
->version
+ strlen(LIQUIDIO_PACKAGE
));
778 if (be32_to_cpu(h
->num_images
) > LIO_MAX_IMAGES
) {
779 dev_err(&oct
->pci_dev
->dev
, "Too many images in firmware file (%d).\n",
780 be32_to_cpu(h
->num_images
));
784 dev_info(&oct
->pci_dev
->dev
, "Firmware version: %s\n", h
->version
);
785 snprintf(oct
->fw_info
.liquidio_firmware_version
, 32, "LIQUIDIO: %s",
788 data
+= sizeof(struct octeon_firmware_file_header
);
790 dev_info(&oct
->pci_dev
->dev
, "%s: Loading %d images\n", __func__
,
791 be32_to_cpu(h
->num_images
));
792 /* load all images */
793 for (i
= 0; i
< be32_to_cpu(h
->num_images
); i
++) {
794 load_addr
= be64_to_cpu(h
->desc
[i
].addr
);
795 image_len
= be32_to_cpu(h
->desc
[i
].len
);
797 dev_info(&oct
->pci_dev
->dev
, "Loading firmware %d at %llx\n",
798 image_len
, load_addr
);
800 /* Write in 4MB chunks*/
809 memcpy(p
, data
, size
);
811 /* download the image */
812 octeon_pci_write_core_mem(oct
, load_addr
, p
, (u32
)size
);
819 dev_info(&oct
->pci_dev
->dev
, "Writing boot command: %s\n",
822 /* Invoke the bootcmd */
823 ret
= octeon_console_send_cmd(oct
, h
->bootcmd
, 50);