1 /**********************************************************************
4 * Contact: support@cavium.com
5 * Please include "LiquidIO" in the subject.
7 * Copyright (c) 2003-2015 Cavium, Inc.
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
19 * This file may also be available under a different license from Cavium.
20 * Contact Cavium, Inc. for more information
21 **********************************************************************/
22 #include <linux/netdevice.h>
23 #include "liquidio_common.h"
24 #include "octeon_droq.h"
25 #include "octeon_iq.h"
26 #include "response_manager.h"
27 #include "octeon_device.h"
29 #define MEMOPS_IDX MAX_BAR1_MAP_INDEX
31 #ifdef __BIG_ENDIAN_BITFIELD
33 octeon_toggle_bar1_swapmode(struct octeon_device
*oct
, u32 idx
)
37 mask
= oct
->fn_list
.bar1_idx_read(oct
, idx
);
38 mask
= (mask
& 0x2) ? (mask
& ~2) : (mask
| 2);
39 oct
->fn_list
.bar1_idx_write(oct
, idx
, mask
);
42 #define octeon_toggle_bar1_swapmode(oct, idx) (oct = oct)
46 octeon_pci_fastwrite(struct octeon_device
*oct
, u8 __iomem
*mapped_addr
,
49 while ((len
) && ((unsigned long)mapped_addr
) & 7) {
50 writeb(*(hostbuf
++), mapped_addr
++);
54 octeon_toggle_bar1_swapmode(oct
, MEMOPS_IDX
);
57 writeq(*((u64
*)hostbuf
), mapped_addr
);
63 octeon_toggle_bar1_swapmode(oct
, MEMOPS_IDX
);
66 writeb(*(hostbuf
++), mapped_addr
++);
70 octeon_pci_fastread(struct octeon_device
*oct
, u8 __iomem
*mapped_addr
,
73 while ((len
) && ((unsigned long)mapped_addr
) & 7) {
74 *(hostbuf
++) = readb(mapped_addr
++);
78 octeon_toggle_bar1_swapmode(oct
, MEMOPS_IDX
);
81 *((u64
*)hostbuf
) = readq(mapped_addr
);
87 octeon_toggle_bar1_swapmode(oct
, MEMOPS_IDX
);
90 *(hostbuf
++) = readb(mapped_addr
++);
93 /* Core mem read/write with temporary bar1 settings. */
94 /* op = 1 to read, op = 0 to write. */
96 __octeon_pci_rw_core_mem(struct octeon_device
*oct
, u64 addr
,
97 u8
*hostbuf
, u32 len
, u32 op
)
99 u32 copy_len
= 0, index_reg_val
= 0;
101 u8 __iomem
*mapped_addr
;
103 spin_lock_irqsave(&oct
->mem_access_lock
, flags
);
105 /* Save the original index reg value. */
106 index_reg_val
= oct
->fn_list
.bar1_idx_read(oct
, MEMOPS_IDX
);
108 oct
->fn_list
.bar1_idx_setup(oct
, addr
, MEMOPS_IDX
, 1);
109 mapped_addr
= oct
->mmio
[1].hw_addr
110 + (MEMOPS_IDX
<< 22) + (addr
& 0x3fffff);
112 /* If operation crosses a 4MB boundary, split the transfer
116 if (((addr
+ len
- 1) & ~(0x3fffff)) != (addr
& ~(0x3fffff))) {
117 copy_len
= (u32
)(((addr
& ~(0x3fffff)) +
118 (MEMOPS_IDX
<< 22)) - addr
);
123 if (op
) { /* read from core */
124 octeon_pci_fastread(oct
, mapped_addr
, hostbuf
,
127 octeon_pci_fastwrite(oct
, mapped_addr
, hostbuf
,
137 oct
->fn_list
.bar1_idx_write(oct
, MEMOPS_IDX
, index_reg_val
);
139 spin_unlock_irqrestore(&oct
->mem_access_lock
, flags
);
143 octeon_pci_read_core_mem(struct octeon_device
*oct
,
148 __octeon_pci_rw_core_mem(oct
, coreaddr
, buf
, len
, 1);
152 octeon_pci_write_core_mem(struct octeon_device
*oct
,
157 __octeon_pci_rw_core_mem(oct
, coreaddr
, buf
, len
, 0);
160 u64
octeon_read_device_mem64(struct octeon_device
*oct
, u64 coreaddr
)
164 __octeon_pci_rw_core_mem(oct
, coreaddr
, (u8
*)&ret
, 8, 1);
166 return be64_to_cpu(ret
);
169 u32
octeon_read_device_mem32(struct octeon_device
*oct
, u64 coreaddr
)
173 __octeon_pci_rw_core_mem(oct
, coreaddr
, (u8
*)&ret
, 4, 1);
175 return be32_to_cpu(ret
);
178 void octeon_write_device_mem32(struct octeon_device
*oct
, u64 coreaddr
,
181 __be32 t
= cpu_to_be32(val
);
183 __octeon_pci_rw_core_mem(oct
, coreaddr
, (u8
*)&t
, 4, 0);
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