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[deliverable/linux.git] / drivers / net / ethernet / cavium / thunder / nic_main.c
1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/etherdevice.h>
13 #include <linux/of.h>
14
15 #include "nic_reg.h"
16 #include "nic.h"
17 #include "q_struct.h"
18 #include "thunder_bgx.h"
19
20 #define DRV_NAME "thunder-nic"
21 #define DRV_VERSION "1.0"
22
23 struct hw_info {
24 u8 bgx_cnt;
25 u8 chans_per_lmac;
26 u8 chans_per_bgx; /* Rx/Tx chans */
27 u8 chans_per_rgx;
28 u8 chans_per_lbk;
29 u16 cpi_cnt;
30 u16 rssi_cnt;
31 u16 rss_ind_tbl_size;
32 u16 tl4_cnt;
33 u16 tl3_cnt;
34 u8 tl2_cnt;
35 u8 tl1_cnt;
36 bool tl1_per_bgx; /* TL1 per BGX or per LMAC */
37 };
38
39 struct nicpf {
40 struct pci_dev *pdev;
41 struct hw_info *hw;
42 u8 node;
43 unsigned int flags;
44 u8 num_vf_en; /* No of VF enabled */
45 bool vf_enabled[MAX_NUM_VFS_SUPPORTED];
46 void __iomem *reg_base; /* Register start address */
47 u8 num_sqs_en; /* Secondary qsets enabled */
48 u64 nicvf[MAX_NUM_VFS_SUPPORTED];
49 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
50 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED];
51 bool sqs_used[MAX_NUM_VFS_SUPPORTED];
52 struct pkind_cfg pkind;
53 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF))
54 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF)
55 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF)
56 u8 vf_lmac_map[MAX_LMAC];
57 struct delayed_work dwork;
58 struct workqueue_struct *check_link;
59 u8 link[MAX_LMAC];
60 u8 duplex[MAX_LMAC];
61 u32 speed[MAX_LMAC];
62 u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
63 u16 rssi_base[MAX_NUM_VFS_SUPPORTED];
64 bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
65
66 /* MSI-X */
67 bool msix_enabled;
68 u8 num_vec;
69 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS];
70 bool irq_allocated[NIC_PF_MSIX_VECTORS];
71 };
72
73 /* Supported devices */
74 static const struct pci_device_id nic_id_table[] = {
75 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
76 { 0, } /* end of table */
77 };
78
79 MODULE_AUTHOR("Sunil Goutham");
80 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
81 MODULE_LICENSE("GPL v2");
82 MODULE_VERSION(DRV_VERSION);
83 MODULE_DEVICE_TABLE(pci, nic_id_table);
84
85 /* The Cavium ThunderX network controller can *only* be found in SoCs
86 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
87 * registers on this platform are implicitly strongly ordered with respect
88 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
89 * with no memory barriers in this driver. The readq()/writeq() functions add
90 * explicit ordering operation which in this case are redundant, and only
91 * add overhead.
92 */
93
94 /* Register read/write APIs */
95 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val)
96 {
97 writeq_relaxed(val, nic->reg_base + offset);
98 }
99
100 static u64 nic_reg_read(struct nicpf *nic, u64 offset)
101 {
102 return readq_relaxed(nic->reg_base + offset);
103 }
104
105 /* PF -> VF mailbox communication APIs */
106 static void nic_enable_mbx_intr(struct nicpf *nic)
107 {
108 /* Enable mailbox interrupt for all 128 VFs */
109 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0ull);
110 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), ~0ull);
111 }
112
113 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
114 {
115 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
116 }
117
118 static u64 nic_get_mbx_addr(int vf)
119 {
120 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT);
121 }
122
123 /* Send a mailbox message to VF
124 * @vf: vf to which this message to be sent
125 * @mbx: Message to be sent
126 */
127 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
128 {
129 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf);
130 u64 *msg = (u64 *)mbx;
131
132 /* In first revision HW, mbox interrupt is triggerred
133 * when PF writes to MBOX(1), in next revisions when
134 * PF writes to MBOX(0)
135 */
136 if (pass1_silicon(nic->pdev)) {
137 /* see the comment for nic_reg_write()/nic_reg_read()
138 * functions above
139 */
140 writeq_relaxed(msg[0], mbx_addr);
141 writeq_relaxed(msg[1], mbx_addr + 8);
142 } else {
143 writeq_relaxed(msg[1], mbx_addr + 8);
144 writeq_relaxed(msg[0], mbx_addr);
145 }
146 }
147
148 /* Responds to VF's READY message with VF's
149 * ID, node, MAC address e.t.c
150 * @vf: VF which sent READY message
151 */
152 static void nic_mbx_send_ready(struct nicpf *nic, int vf)
153 {
154 union nic_mbx mbx = {};
155 int bgx_idx, lmac;
156 const char *mac;
157
158 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
159 mbx.nic_cfg.vf_id = vf;
160
161 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
162
163 if (vf < MAX_LMAC) {
164 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
165 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
166
167 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
168 if (mac)
169 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac);
170 }
171 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false;
172 mbx.nic_cfg.node_id = nic->node;
173
174 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC;
175
176 nic_send_msg_to_vf(nic, vf, &mbx);
177 }
178
179 /* ACKs VF's mailbox message
180 * @vf: VF to which ACK to be sent
181 */
182 static void nic_mbx_send_ack(struct nicpf *nic, int vf)
183 {
184 union nic_mbx mbx = {};
185
186 mbx.msg.msg = NIC_MBOX_MSG_ACK;
187 nic_send_msg_to_vf(nic, vf, &mbx);
188 }
189
190 /* NACKs VF's mailbox message that PF is not able to
191 * complete the action
192 * @vf: VF to which ACK to be sent
193 */
194 static void nic_mbx_send_nack(struct nicpf *nic, int vf)
195 {
196 union nic_mbx mbx = {};
197
198 mbx.msg.msg = NIC_MBOX_MSG_NACK;
199 nic_send_msg_to_vf(nic, vf, &mbx);
200 }
201
202 /* Flush all in flight receive packets to memory and
203 * bring down an active RQ
204 */
205 static int nic_rcv_queue_sw_sync(struct nicpf *nic)
206 {
207 u16 timeout = ~0x00;
208
209 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
210 /* Wait till sync cycle is finished */
211 while (timeout) {
212 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
213 break;
214 timeout--;
215 }
216 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
217 if (!timeout) {
218 dev_err(&nic->pdev->dev, "Receive queue software sync failed");
219 return 1;
220 }
221 return 0;
222 }
223
224 /* Get BGX Rx/Tx stats and respond to VF's request */
225 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
226 {
227 int bgx_idx, lmac;
228 union nic_mbx mbx = {};
229
230 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
231 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
232
233 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
234 mbx.bgx_stats.vf_id = bgx->vf_id;
235 mbx.bgx_stats.rx = bgx->rx;
236 mbx.bgx_stats.idx = bgx->idx;
237 if (bgx->rx)
238 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx,
239 lmac, bgx->idx);
240 else
241 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx,
242 lmac, bgx->idx);
243 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
244 }
245
246 /* Update hardware min/max frame size */
247 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
248 {
249 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) {
250 dev_err(&nic->pdev->dev,
251 "Invalid MTU setting from VF%d rejected, should be between %d and %d\n",
252 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS);
253 return 1;
254 }
255 new_frs += ETH_HLEN;
256 if (new_frs <= nic->pkind.maxlen)
257 return 0;
258
259 nic->pkind.maxlen = new_frs;
260 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(u64 *)&nic->pkind);
261 return 0;
262 }
263
264 /* Set minimum transmit packet size */
265 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size)
266 {
267 int lmac;
268 u64 lmac_cfg;
269
270 /* Max value that can be set is 60 */
271 if (size > 60)
272 size = 60;
273
274 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) {
275 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
276 lmac_cfg &= ~(0xF << 2);
277 lmac_cfg |= ((size / 4) << 2);
278 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
279 }
280 }
281
282 /* Function to check number of LMACs present and set VF::LMAC mapping.
283 * Mapping will be used while initializing channels.
284 */
285 static void nic_set_lmac_vf_mapping(struct nicpf *nic)
286 {
287 unsigned bgx_map = bgx_get_map(nic->node);
288 int bgx, next_bgx_lmac = 0;
289 int lmac, lmac_cnt = 0;
290 u64 lmac_credit;
291
292 nic->num_vf_en = 0;
293
294 for (bgx = 0; bgx < nic->hw->bgx_cnt; bgx++) {
295 if (!(bgx_map & (1 << bgx)))
296 continue;
297 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
298 for (lmac = 0; lmac < lmac_cnt; lmac++)
299 nic->vf_lmac_map[next_bgx_lmac++] =
300 NIC_SET_VF_LMAC_MAP(bgx, lmac);
301 nic->num_vf_en += lmac_cnt;
302
303 /* Program LMAC credits */
304 lmac_credit = (1ull << 1); /* channel credit enable */
305 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
306 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
307 lmac_credit |= (((((48 * 1024) / lmac_cnt) -
308 NIC_HW_MAX_FRS) / 16) << 12);
309 lmac = bgx * MAX_LMAC_PER_BGX;
310 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
311 nic_reg_write(nic,
312 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
313 lmac_credit);
314 }
315 }
316
317 static void nic_get_hw_info(struct nicpf *nic)
318 {
319 u16 sdevid;
320 struct hw_info *hw = nic->hw;
321
322 pci_read_config_word(nic->pdev, PCI_SUBSYSTEM_ID, &sdevid);
323
324 switch (sdevid) {
325 case PCI_SUBSYS_DEVID_88XX_NIC_PF:
326 hw->bgx_cnt = MAX_BGX_PER_CN88XX;
327 hw->chans_per_lmac = 16;
328 hw->chans_per_bgx = 128;
329 hw->cpi_cnt = 2048;
330 hw->rssi_cnt = 4096;
331 hw->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
332 hw->tl3_cnt = 256;
333 hw->tl2_cnt = 64;
334 hw->tl1_cnt = 2;
335 hw->tl1_per_bgx = true;
336 break;
337 case PCI_SUBSYS_DEVID_81XX_NIC_PF:
338 hw->bgx_cnt = MAX_BGX_PER_CN81XX;
339 hw->chans_per_lmac = 8;
340 hw->chans_per_bgx = 32;
341 hw->chans_per_rgx = 8;
342 hw->chans_per_lbk = 24;
343 hw->cpi_cnt = 512;
344 hw->rssi_cnt = 256;
345 hw->rss_ind_tbl_size = 32; /* Max RSSI / Max interfaces */
346 hw->tl3_cnt = 64;
347 hw->tl2_cnt = 16;
348 hw->tl1_cnt = 10;
349 hw->tl1_per_bgx = false;
350 break;
351 case PCI_SUBSYS_DEVID_83XX_NIC_PF:
352 hw->bgx_cnt = MAX_BGX_PER_CN83XX;
353 hw->chans_per_lmac = 8;
354 hw->chans_per_bgx = 32;
355 hw->chans_per_lbk = 64;
356 hw->cpi_cnt = 2048;
357 hw->rssi_cnt = 1024;
358 hw->rss_ind_tbl_size = 64; /* Max RSSI / Max interfaces */
359 hw->tl3_cnt = 256;
360 hw->tl2_cnt = 64;
361 hw->tl1_cnt = 18;
362 hw->tl1_per_bgx = false;
363 break;
364 }
365 hw->tl4_cnt = MAX_QUEUES_PER_QSET * pci_sriov_get_totalvfs(nic->pdev);
366 }
367
368 #define BGX0_BLOCK 8
369 #define BGX1_BLOCK 9
370
371 static void nic_init_hw(struct nicpf *nic)
372 {
373 int i;
374 u64 cqm_cfg;
375
376 /* Get HW capability info */
377 nic_get_hw_info(nic);
378
379 /* Enable NIC HW block */
380 nic_reg_write(nic, NIC_PF_CFG, 0x3);
381
382 /* Enable backpressure */
383 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
384
385 /* TNS and TNS bypass modes are present only on 88xx */
386 if (nic->pdev->subsystem_device == PCI_SUBSYS_DEVID_88XX_NIC_PF) {
387 /* Disable TNS mode on both interfaces */
388 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
389 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
390 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
391 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
392 }
393
394 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
395 (1ULL << 63) | BGX0_BLOCK);
396 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
397 (1ULL << 63) | BGX1_BLOCK);
398
399 /* PKIND configuration */
400 nic->pkind.minlen = 0;
401 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN;
402 nic->pkind.lenerr_en = 1;
403 nic->pkind.rx_hdr = 0;
404 nic->pkind.hdr_sl = 0;
405
406 for (i = 0; i < NIC_MAX_PKIND; i++)
407 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
408 *(u64 *)&nic->pkind);
409
410 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
411
412 /* Timer config */
413 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
414
415 /* Enable VLAN ethertype matching and stripping */
416 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7,
417 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q);
418
419 /* Check if HW expected value is higher (could be in future chips) */
420 cqm_cfg = nic_reg_read(nic, NIC_PF_CQM_CFG);
421 if (cqm_cfg < NICPF_CQM_MIN_DROP_LEVEL)
422 nic_reg_write(nic, NIC_PF_CQM_CFG, NICPF_CQM_MIN_DROP_LEVEL);
423 }
424
425 /* Channel parse index configuration */
426 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
427 {
428 struct hw_info *hw = nic->hw;
429 u32 vnic, bgx, lmac, chan;
430 u32 padd, cpi_count = 0;
431 u64 cpi_base, cpi, rssi_base, rssi;
432 u8 qset, rq_idx = 0;
433
434 vnic = cfg->vf_id;
435 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
436 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
437
438 chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx);
439 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) +
440 (bgx * (hw->cpi_cnt / hw->bgx_cnt));
441 rssi_base = (lmac * hw->rss_ind_tbl_size) +
442 (bgx * (hw->rssi_cnt / hw->bgx_cnt));
443
444 /* Rx channel configuration */
445 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
446 (1ull << 63) | (vnic << 0));
447 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
448 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48));
449
450 if (cfg->cpi_alg == CPI_ALG_NONE)
451 cpi_count = 1;
452 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
453 cpi_count = 8;
454 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
455 cpi_count = 16;
456 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
457 cpi_count = NIC_MAX_CPI_PER_LMAC;
458
459 /* RSS Qset, Qidx mapping */
460 qset = cfg->vf_id;
461 rssi = rssi_base;
462 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
463 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
464 (qset << 3) | rq_idx);
465 rq_idx++;
466 }
467
468 rssi = 0;
469 cpi = cpi_base;
470 for (; cpi < (cpi_base + cpi_count); cpi++) {
471 /* Determine port to channel adder */
472 if (cfg->cpi_alg != CPI_ALG_DIFF)
473 padd = cpi % cpi_count;
474 else
475 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
476
477 /* Leave RSS_SIZE as '0' to disable RSS */
478 if (pass1_silicon(nic->pdev)) {
479 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
480 (vnic << 24) | (padd << 16) |
481 (rssi_base + rssi));
482 } else {
483 /* Set MPI_ALG to '0' to disable MCAM parsing */
484 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
485 (padd << 16));
486 /* MPI index is same as CPI if MPI_ALG is not enabled */
487 nic_reg_write(nic, NIC_PF_MPI_0_2047_CFG | (cpi << 3),
488 (vnic << 24) | (rssi_base + rssi));
489 }
490
491 if ((rssi + 1) >= cfg->rq_cnt)
492 continue;
493
494 if (cfg->cpi_alg == CPI_ALG_VLAN)
495 rssi++;
496 else if (cfg->cpi_alg == CPI_ALG_VLAN16)
497 rssi = ((cpi - cpi_base) & 0xe) >> 1;
498 else if (cfg->cpi_alg == CPI_ALG_DIFF)
499 rssi = ((cpi - cpi_base) & 0x38) >> 3;
500 }
501 nic->cpi_base[cfg->vf_id] = cpi_base;
502 nic->rssi_base[cfg->vf_id] = rssi_base;
503 }
504
505 /* Responsds to VF with its RSS indirection table size */
506 static void nic_send_rss_size(struct nicpf *nic, int vf)
507 {
508 union nic_mbx mbx = {};
509 u64 *msg;
510
511 msg = (u64 *)&mbx;
512
513 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
514 mbx.rss_size.ind_tbl_size = nic->hw->rss_ind_tbl_size;
515 nic_send_msg_to_vf(nic, vf, &mbx);
516 }
517
518 /* Receive side scaling configuration
519 * configure:
520 * - RSS index
521 * - indir table i.e hash::RQ mapping
522 * - no of hash bits to consider
523 */
524 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
525 {
526 u8 qset, idx = 0;
527 u64 cpi_cfg, cpi_base, rssi_base, rssi;
528 u64 idx_addr;
529
530 rssi_base = nic->rssi_base[cfg->vf_id] + cfg->tbl_offset;
531
532 rssi = rssi_base;
533 qset = cfg->vf_id;
534
535 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
536 u8 svf = cfg->ind_tbl[idx] >> 3;
537
538 if (svf)
539 qset = nic->vf_sqs[cfg->vf_id][svf - 1];
540 else
541 qset = cfg->vf_id;
542 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
543 (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
544 idx++;
545 }
546
547 cpi_base = nic->cpi_base[cfg->vf_id];
548 if (pass1_silicon(nic->pdev))
549 idx_addr = NIC_PF_CPI_0_2047_CFG;
550 else
551 idx_addr = NIC_PF_MPI_0_2047_CFG;
552 cpi_cfg = nic_reg_read(nic, idx_addr | (cpi_base << 3));
553 cpi_cfg &= ~(0xFULL << 20);
554 cpi_cfg |= (cfg->hash_bits << 20);
555 nic_reg_write(nic, idx_addr | (cpi_base << 3), cpi_cfg);
556 }
557
558 /* 4 level transmit side scheduler configutation
559 * for TNS bypass mode
560 *
561 * Sample configuration for SQ0 on 88xx
562 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
563 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
564 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
565 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
566 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
567 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
568 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
569 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
570 */
571 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
572 struct sq_cfg_msg *sq)
573 {
574 struct hw_info *hw = nic->hw;
575 u32 bgx, lmac, chan;
576 u32 tl2, tl3, tl4;
577 u32 rr_quantum;
578 u8 sq_idx = sq->sq_num;
579 u8 pqs_vnic;
580 int svf;
581
582 if (sq->sqs_mode)
583 pqs_vnic = nic->pqs_vf[vnic];
584 else
585 pqs_vnic = vnic;
586
587 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
588 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
589
590 /* 24 bytes for FCS, IPG and preamble */
591 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
592
593 /* For 88xx 0-511 TL4 transmits via BGX0 and
594 * 512-1023 TL4s transmit via BGX1.
595 */
596 if (hw->tl1_per_bgx) {
597 tl4 = bgx * (hw->tl4_cnt / hw->bgx_cnt);
598 if (!sq->sqs_mode) {
599 tl4 += (lmac * MAX_QUEUES_PER_QSET);
600 } else {
601 for (svf = 0; svf < MAX_SQS_PER_VF; svf++) {
602 if (nic->vf_sqs[pqs_vnic][svf] == vnic)
603 break;
604 }
605 tl4 += (MAX_LMAC_PER_BGX * MAX_QUEUES_PER_QSET);
606 tl4 += (lmac * MAX_QUEUES_PER_QSET * MAX_SQS_PER_VF);
607 tl4 += (svf * MAX_QUEUES_PER_QSET);
608 }
609 } else {
610 tl4 = (vnic * MAX_QUEUES_PER_QSET);
611 }
612 tl4 += sq_idx;
613
614 tl3 = tl4 / (hw->tl4_cnt / hw->tl3_cnt);
615 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
616 ((u64)vnic << NIC_QS_ID_SHIFT) |
617 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
618 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
619 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
620
621 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
622
623 /* On 88xx 0-127 channels are for BGX0 and
624 * 127-255 channels for BGX1.
625 *
626 * On 81xx/83xx TL3_CHAN reg should be configured with channel
627 * within LMAC i.e 0-7 and not the actual channel number like on 88xx
628 */
629 chan = (lmac * hw->chans_per_lmac) + (bgx * hw->chans_per_bgx);
630 if (hw->tl1_per_bgx)
631 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
632 else
633 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), 0);
634
635 /* Enable backpressure on the channel */
636 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
637
638 tl2 = tl3 >> 2;
639 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
640 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
641 /* No priorities as of now */
642 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
643
644 /* Unlike 88xx where TL2s 0-31 transmits to TL1 '0' and rest to TL1 '1'
645 * on 81xx/83xx TL2 needs to be configured to transmit to one of the
646 * possible LMACs.
647 *
648 * This register doesn't exist on 88xx.
649 */
650 if (!hw->tl1_per_bgx)
651 nic_reg_write(nic, NIC_PF_TL2_LMAC | (tl2 << 3),
652 lmac + (bgx * MAX_LMAC_PER_BGX));
653 }
654
655 /* Send primary nicvf pointer to secondary QS's VF */
656 static void nic_send_pnicvf(struct nicpf *nic, int sqs)
657 {
658 union nic_mbx mbx = {};
659
660 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
661 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]];
662 nic_send_msg_to_vf(nic, sqs, &mbx);
663 }
664
665 /* Send SQS's nicvf pointer to primary QS's VF */
666 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf)
667 {
668 union nic_mbx mbx = {};
669 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id];
670
671 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
672 mbx.nicvf.sqs_id = nicvf->sqs_id;
673 mbx.nicvf.nicvf = nic->nicvf[sqs_id];
674 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx);
675 }
676
677 /* Find next available Qset that can be assigned as a
678 * secondary Qset to a VF.
679 */
680 static int nic_nxt_avail_sqs(struct nicpf *nic)
681 {
682 int sqs;
683
684 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) {
685 if (!nic->sqs_used[sqs])
686 nic->sqs_used[sqs] = true;
687 else
688 continue;
689 return sqs + nic->num_vf_en;
690 }
691 return -1;
692 }
693
694 /* Allocate additional Qsets for requested VF */
695 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs)
696 {
697 union nic_mbx mbx = {};
698 int idx, alloc_qs = 0;
699 int sqs_id;
700
701 if (!nic->num_sqs_en)
702 goto send_mbox;
703
704 for (idx = 0; idx < sqs->qs_count; idx++) {
705 sqs_id = nic_nxt_avail_sqs(nic);
706 if (sqs_id < 0)
707 break;
708 nic->vf_sqs[sqs->vf_id][idx] = sqs_id;
709 nic->pqs_vf[sqs_id] = sqs->vf_id;
710 alloc_qs++;
711 }
712
713 send_mbox:
714 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
715 mbx.sqs_alloc.vf_id = sqs->vf_id;
716 mbx.sqs_alloc.qs_count = alloc_qs;
717 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx);
718 }
719
720 static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk)
721 {
722 int bgx_idx, lmac_idx;
723
724 if (lbk->vf_id > MAX_LMAC)
725 return -1;
726
727 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
728 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
729
730 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable);
731
732 return 0;
733 }
734
735 static void nic_enable_vf(struct nicpf *nic, int vf, bool enable)
736 {
737 int bgx, lmac;
738
739 nic->vf_enabled[vf] = enable;
740
741 if (vf >= nic->num_vf_en)
742 return;
743
744 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
745 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
746
747 bgx_lmac_rx_tx_enable(nic->node, bgx, lmac, enable);
748 }
749
750 /* Interrupt handler to handle mailbox messages from VFs */
751 static void nic_handle_mbx_intr(struct nicpf *nic, int vf)
752 {
753 union nic_mbx mbx = {};
754 u64 *mbx_data;
755 u64 mbx_addr;
756 u64 reg_addr;
757 u64 cfg;
758 int bgx, lmac;
759 int i;
760 int ret = 0;
761
762 nic->mbx_lock[vf] = true;
763
764 mbx_addr = nic_get_mbx_addr(vf);
765 mbx_data = (u64 *)&mbx;
766
767 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
768 *mbx_data = nic_reg_read(nic, mbx_addr);
769 mbx_data++;
770 mbx_addr += sizeof(u64);
771 }
772
773 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg %d from VF%d\n",
774 __func__, mbx.msg.msg, vf);
775 switch (mbx.msg.msg) {
776 case NIC_MBOX_MSG_READY:
777 nic_mbx_send_ready(nic, vf);
778 if (vf < MAX_LMAC) {
779 nic->link[vf] = 0;
780 nic->duplex[vf] = 0;
781 nic->speed[vf] = 0;
782 }
783 ret = 1;
784 break;
785 case NIC_MBOX_MSG_QS_CFG:
786 reg_addr = NIC_PF_QSET_0_127_CFG |
787 (mbx.qs.num << NIC_QS_ID_SHIFT);
788 cfg = mbx.qs.cfg;
789 /* Check if its a secondary Qset */
790 if (vf >= nic->num_vf_en) {
791 cfg = cfg & (~0x7FULL);
792 /* Assign this Qset to primary Qset's VF */
793 cfg |= nic->pqs_vf[vf];
794 }
795 nic_reg_write(nic, reg_addr, cfg);
796 break;
797 case NIC_MBOX_MSG_RQ_CFG:
798 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
799 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
800 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
801 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
802 break;
803 case NIC_MBOX_MSG_RQ_BP_CFG:
804 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
805 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
806 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
807 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
808 break;
809 case NIC_MBOX_MSG_RQ_SW_SYNC:
810 ret = nic_rcv_queue_sw_sync(nic);
811 break;
812 case NIC_MBOX_MSG_RQ_DROP_CFG:
813 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
814 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
815 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
816 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
817 break;
818 case NIC_MBOX_MSG_SQ_CFG:
819 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
820 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
821 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
822 nic_reg_write(nic, reg_addr, mbx.sq.cfg);
823 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq);
824 break;
825 case NIC_MBOX_MSG_SET_MAC:
826 if (vf >= nic->num_vf_en)
827 break;
828 lmac = mbx.mac.vf_id;
829 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
830 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
831 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
832 break;
833 case NIC_MBOX_MSG_SET_MAX_FRS:
834 ret = nic_update_hw_frs(nic, mbx.frs.max_frs,
835 mbx.frs.vf_id);
836 break;
837 case NIC_MBOX_MSG_CPI_CFG:
838 nic_config_cpi(nic, &mbx.cpi_cfg);
839 break;
840 case NIC_MBOX_MSG_RSS_SIZE:
841 nic_send_rss_size(nic, vf);
842 goto unlock;
843 case NIC_MBOX_MSG_RSS_CFG:
844 case NIC_MBOX_MSG_RSS_CFG_CONT:
845 nic_config_rss(nic, &mbx.rss_cfg);
846 break;
847 case NIC_MBOX_MSG_CFG_DONE:
848 /* Last message of VF config msg sequence */
849 nic_enable_vf(nic, vf, true);
850 goto unlock;
851 case NIC_MBOX_MSG_SHUTDOWN:
852 /* First msg in VF teardown sequence */
853 if (vf >= nic->num_vf_en)
854 nic->sqs_used[vf - nic->num_vf_en] = false;
855 nic->pqs_vf[vf] = 0;
856 nic_enable_vf(nic, vf, false);
857 break;
858 case NIC_MBOX_MSG_ALLOC_SQS:
859 nic_alloc_sqs(nic, &mbx.sqs_alloc);
860 goto unlock;
861 case NIC_MBOX_MSG_NICVF_PTR:
862 nic->nicvf[vf] = mbx.nicvf.nicvf;
863 break;
864 case NIC_MBOX_MSG_PNICVF_PTR:
865 nic_send_pnicvf(nic, vf);
866 goto unlock;
867 case NIC_MBOX_MSG_SNICVF_PTR:
868 nic_send_snicvf(nic, &mbx.nicvf);
869 goto unlock;
870 case NIC_MBOX_MSG_BGX_STATS:
871 nic_get_bgx_stats(nic, &mbx.bgx_stats);
872 goto unlock;
873 case NIC_MBOX_MSG_LOOPBACK:
874 ret = nic_config_loopback(nic, &mbx.lbk);
875 break;
876 default:
877 dev_err(&nic->pdev->dev,
878 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
879 break;
880 }
881
882 if (!ret)
883 nic_mbx_send_ack(nic, vf);
884 else if (mbx.msg.msg != NIC_MBOX_MSG_READY)
885 nic_mbx_send_nack(nic, vf);
886 unlock:
887 nic->mbx_lock[vf] = false;
888 }
889
890 static void nic_mbx_intr_handler (struct nicpf *nic, int mbx)
891 {
892 u64 intr;
893 u8 vf, vf_per_mbx_reg = 64;
894
895 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
896 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
897 for (vf = 0; vf < vf_per_mbx_reg; vf++) {
898 if (intr & (1ULL << vf)) {
899 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n",
900 vf + (mbx * vf_per_mbx_reg));
901
902 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
903 nic_clear_mbx_intr(nic, vf, mbx);
904 }
905 }
906 }
907
908 static irqreturn_t nic_mbx0_intr_handler (int irq, void *nic_irq)
909 {
910 struct nicpf *nic = (struct nicpf *)nic_irq;
911
912 nic_mbx_intr_handler(nic, 0);
913
914 return IRQ_HANDLED;
915 }
916
917 static irqreturn_t nic_mbx1_intr_handler (int irq, void *nic_irq)
918 {
919 struct nicpf *nic = (struct nicpf *)nic_irq;
920
921 nic_mbx_intr_handler(nic, 1);
922
923 return IRQ_HANDLED;
924 }
925
926 static int nic_enable_msix(struct nicpf *nic)
927 {
928 int i, ret;
929
930 nic->num_vec = NIC_PF_MSIX_VECTORS;
931
932 for (i = 0; i < nic->num_vec; i++)
933 nic->msix_entries[i].entry = i;
934
935 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
936 if (ret) {
937 dev_err(&nic->pdev->dev,
938 "Request for #%d msix vectors failed\n",
939 nic->num_vec);
940 return ret;
941 }
942
943 nic->msix_enabled = 1;
944 return 0;
945 }
946
947 static void nic_disable_msix(struct nicpf *nic)
948 {
949 if (nic->msix_enabled) {
950 pci_disable_msix(nic->pdev);
951 nic->msix_enabled = 0;
952 nic->num_vec = 0;
953 }
954 }
955
956 static void nic_free_all_interrupts(struct nicpf *nic)
957 {
958 int irq;
959
960 for (irq = 0; irq < nic->num_vec; irq++) {
961 if (nic->irq_allocated[irq])
962 free_irq(nic->msix_entries[irq].vector, nic);
963 nic->irq_allocated[irq] = false;
964 }
965 }
966
967 static int nic_register_interrupts(struct nicpf *nic)
968 {
969 int ret;
970
971 /* Enable MSI-X */
972 ret = nic_enable_msix(nic);
973 if (ret)
974 return ret;
975
976 /* Register mailbox interrupt handlers */
977 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector,
978 nic_mbx0_intr_handler, 0, "NIC Mbox0", nic);
979 if (ret)
980 goto fail;
981
982 nic->irq_allocated[NIC_PF_INTR_ID_MBOX0] = true;
983
984 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX1].vector,
985 nic_mbx1_intr_handler, 0, "NIC Mbox1", nic);
986 if (ret)
987 goto fail;
988
989 nic->irq_allocated[NIC_PF_INTR_ID_MBOX1] = true;
990
991 /* Enable mailbox interrupt */
992 nic_enable_mbx_intr(nic);
993 return 0;
994
995 fail:
996 dev_err(&nic->pdev->dev, "Request irq failed\n");
997 nic_free_all_interrupts(nic);
998 return ret;
999 }
1000
1001 static void nic_unregister_interrupts(struct nicpf *nic)
1002 {
1003 nic_free_all_interrupts(nic);
1004 nic_disable_msix(nic);
1005 }
1006
1007 static int nic_num_sqs_en(struct nicpf *nic, int vf_en)
1008 {
1009 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE;
1010 u16 total_vf;
1011
1012 /* Check if its a multi-node environment */
1013 if (nr_node_ids > 1)
1014 sqs_per_vf = MAX_SQS_PER_VF;
1015
1016 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV);
1017 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf);
1018 return min(total_vf - vf_en, vf_en * sqs_per_vf);
1019 }
1020
1021 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic)
1022 {
1023 int pos = 0;
1024 int vf_en;
1025 int err;
1026 u16 total_vf_cnt;
1027
1028 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
1029 if (!pos) {
1030 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
1031 return -ENODEV;
1032 }
1033
1034 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
1035 if (total_vf_cnt < nic->num_vf_en)
1036 nic->num_vf_en = total_vf_cnt;
1037
1038 if (!total_vf_cnt)
1039 return 0;
1040
1041 vf_en = nic->num_vf_en;
1042 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en);
1043 vf_en += nic->num_sqs_en;
1044
1045 err = pci_enable_sriov(pdev, vf_en);
1046 if (err) {
1047 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
1048 vf_en);
1049 nic->num_vf_en = 0;
1050 return err;
1051 }
1052
1053 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
1054 vf_en);
1055
1056 nic->flags |= NIC_SRIOV_ENABLED;
1057 return 0;
1058 }
1059
1060 /* Poll for BGX LMAC link status and update corresponding VF
1061 * if there is a change, valid only if internal L2 switch
1062 * is not present otherwise VF link is always treated as up
1063 */
1064 static void nic_poll_for_link(struct work_struct *work)
1065 {
1066 union nic_mbx mbx = {};
1067 struct nicpf *nic;
1068 struct bgx_link_status link;
1069 u8 vf, bgx, lmac;
1070
1071 nic = container_of(work, struct nicpf, dwork.work);
1072
1073 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
1074
1075 for (vf = 0; vf < nic->num_vf_en; vf++) {
1076 /* Poll only if VF is UP */
1077 if (!nic->vf_enabled[vf])
1078 continue;
1079
1080 /* Get BGX, LMAC indices for the VF */
1081 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1082 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
1083 /* Get interface link status */
1084 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
1085
1086 /* Inform VF only if link status changed */
1087 if (nic->link[vf] == link.link_up)
1088 continue;
1089
1090 if (!nic->mbx_lock[vf]) {
1091 nic->link[vf] = link.link_up;
1092 nic->duplex[vf] = link.duplex;
1093 nic->speed[vf] = link.speed;
1094
1095 /* Send a mbox message to VF with current link status */
1096 mbx.link_status.link_up = link.link_up;
1097 mbx.link_status.duplex = link.duplex;
1098 mbx.link_status.speed = link.speed;
1099 nic_send_msg_to_vf(nic, vf, &mbx);
1100 }
1101 }
1102 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2);
1103 }
1104
1105 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1106 {
1107 struct device *dev = &pdev->dev;
1108 struct nicpf *nic;
1109 int err;
1110
1111 BUILD_BUG_ON(sizeof(union nic_mbx) > 16);
1112
1113 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL);
1114 if (!nic)
1115 return -ENOMEM;
1116
1117 nic->hw = devm_kzalloc(dev, sizeof(struct hw_info), GFP_KERNEL);
1118 if (!nic->hw) {
1119 devm_kfree(dev, nic);
1120 return -ENOMEM;
1121 }
1122
1123 pci_set_drvdata(pdev, nic);
1124
1125 nic->pdev = pdev;
1126
1127 err = pci_enable_device(pdev);
1128 if (err) {
1129 dev_err(dev, "Failed to enable PCI device\n");
1130 pci_set_drvdata(pdev, NULL);
1131 return err;
1132 }
1133
1134 err = pci_request_regions(pdev, DRV_NAME);
1135 if (err) {
1136 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1137 goto err_disable_device;
1138 }
1139
1140 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1141 if (err) {
1142 dev_err(dev, "Unable to get usable DMA configuration\n");
1143 goto err_release_regions;
1144 }
1145
1146 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1147 if (err) {
1148 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
1149 goto err_release_regions;
1150 }
1151
1152 /* MAP PF's configuration registers */
1153 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1154 if (!nic->reg_base) {
1155 dev_err(dev, "Cannot map config register space, aborting\n");
1156 err = -ENOMEM;
1157 goto err_release_regions;
1158 }
1159
1160 nic->node = nic_get_node_id(pdev);
1161
1162 /* Initialize hardware */
1163 nic_init_hw(nic);
1164
1165 nic_set_lmac_vf_mapping(nic);
1166
1167 /* Register interrupts */
1168 err = nic_register_interrupts(nic);
1169 if (err)
1170 goto err_release_regions;
1171
1172 /* Configure SRIOV */
1173 err = nic_sriov_init(pdev, nic);
1174 if (err)
1175 goto err_unregister_interrupts;
1176
1177 /* Register a physical link status poll fn() */
1178 nic->check_link = alloc_workqueue("check_link_status",
1179 WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
1180 if (!nic->check_link) {
1181 err = -ENOMEM;
1182 goto err_disable_sriov;
1183 }
1184
1185 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link);
1186 queue_delayed_work(nic->check_link, &nic->dwork, 0);
1187
1188 return 0;
1189
1190 err_disable_sriov:
1191 if (nic->flags & NIC_SRIOV_ENABLED)
1192 pci_disable_sriov(pdev);
1193 err_unregister_interrupts:
1194 nic_unregister_interrupts(nic);
1195 err_release_regions:
1196 pci_release_regions(pdev);
1197 err_disable_device:
1198 devm_kfree(dev, nic->hw);
1199 devm_kfree(dev, nic);
1200 pci_disable_device(pdev);
1201 pci_set_drvdata(pdev, NULL);
1202 return err;
1203 }
1204
1205 static void nic_remove(struct pci_dev *pdev)
1206 {
1207 struct nicpf *nic = pci_get_drvdata(pdev);
1208
1209 if (nic->flags & NIC_SRIOV_ENABLED)
1210 pci_disable_sriov(pdev);
1211
1212 if (nic->check_link) {
1213 /* Destroy work Queue */
1214 cancel_delayed_work_sync(&nic->dwork);
1215 destroy_workqueue(nic->check_link);
1216 }
1217
1218 nic_unregister_interrupts(nic);
1219 pci_release_regions(pdev);
1220
1221 devm_kfree(&pdev->dev, nic->hw);
1222 devm_kfree(&pdev->dev, nic);
1223
1224 pci_disable_device(pdev);
1225 pci_set_drvdata(pdev, NULL);
1226 }
1227
1228 static struct pci_driver nic_driver = {
1229 .name = DRV_NAME,
1230 .id_table = nic_id_table,
1231 .probe = nic_probe,
1232 .remove = nic_remove,
1233 };
1234
1235 static int __init nic_init_module(void)
1236 {
1237 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1238
1239 return pci_register_driver(&nic_driver);
1240 }
1241
1242 static void __exit nic_cleanup_module(void)
1243 {
1244 pci_unregister_driver(&nic_driver);
1245 }
1246
1247 module_init(nic_init_module);
1248 module_exit(nic_cleanup_module);
Linux kernel - Deliverables
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