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52e1acb69562c6df86928a401e5fe5796011c35b
[deliverable/linux.git] / drivers / net / ethernet / cavium / thunder / nic_main.c
1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/etherdevice.h>
13 #include <linux/of.h>
14
15 #include "nic_reg.h"
16 #include "nic.h"
17 #include "q_struct.h"
18 #include "thunder_bgx.h"
19
20 #define DRV_NAME "thunder-nic"
21 #define DRV_VERSION "1.0"
22
23 struct nicpf {
24 struct pci_dev *pdev;
25 u8 node;
26 unsigned int flags;
27 u8 num_vf_en; /* No of VF enabled */
28 bool vf_enabled[MAX_NUM_VFS_SUPPORTED];
29 void __iomem *reg_base; /* Register start address */
30 u8 num_sqs_en; /* Secondary qsets enabled */
31 u64 nicvf[MAX_NUM_VFS_SUPPORTED];
32 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
33 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED];
34 bool sqs_used[MAX_NUM_VFS_SUPPORTED];
35 struct pkind_cfg pkind;
36 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF))
37 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF)
38 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF)
39 u8 vf_lmac_map[MAX_LMAC];
40 struct delayed_work dwork;
41 struct workqueue_struct *check_link;
42 u8 link[MAX_LMAC];
43 u8 duplex[MAX_LMAC];
44 u32 speed[MAX_LMAC];
45 u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
46 u16 rss_ind_tbl_size;
47 bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
48
49 /* MSI-X */
50 bool msix_enabled;
51 u8 num_vec;
52 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS];
53 bool irq_allocated[NIC_PF_MSIX_VECTORS];
54 };
55
56 static inline bool pass1_silicon(struct nicpf *nic)
57 {
58 return nic->pdev->revision < 8;
59 }
60
61 /* Supported devices */
62 static const struct pci_device_id nic_id_table[] = {
63 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
64 { 0, } /* end of table */
65 };
66
67 MODULE_AUTHOR("Sunil Goutham");
68 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
69 MODULE_LICENSE("GPL v2");
70 MODULE_VERSION(DRV_VERSION);
71 MODULE_DEVICE_TABLE(pci, nic_id_table);
72
73 /* The Cavium ThunderX network controller can *only* be found in SoCs
74 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
75 * registers on this platform are implicitly strongly ordered with respect
76 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
77 * with no memory barriers in this driver. The readq()/writeq() functions add
78 * explicit ordering operation which in this case are redundant, and only
79 * add overhead.
80 */
81
82 /* Register read/write APIs */
83 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val)
84 {
85 writeq_relaxed(val, nic->reg_base + offset);
86 }
87
88 static u64 nic_reg_read(struct nicpf *nic, u64 offset)
89 {
90 return readq_relaxed(nic->reg_base + offset);
91 }
92
93 /* PF -> VF mailbox communication APIs */
94 static void nic_enable_mbx_intr(struct nicpf *nic)
95 {
96 /* Enable mailbox interrupt for all 128 VFs */
97 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0ull);
98 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), ~0ull);
99 }
100
101 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
102 {
103 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
104 }
105
106 static u64 nic_get_mbx_addr(int vf)
107 {
108 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT);
109 }
110
111 /* Send a mailbox message to VF
112 * @vf: vf to which this message to be sent
113 * @mbx: Message to be sent
114 */
115 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
116 {
117 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf);
118 u64 *msg = (u64 *)mbx;
119
120 /* In first revision HW, mbox interrupt is triggerred
121 * when PF writes to MBOX(1), in next revisions when
122 * PF writes to MBOX(0)
123 */
124 if (pass1_silicon(nic)) {
125 /* see the comment for nic_reg_write()/nic_reg_read()
126 * functions above
127 */
128 writeq_relaxed(msg[0], mbx_addr);
129 writeq_relaxed(msg[1], mbx_addr + 8);
130 } else {
131 writeq_relaxed(msg[1], mbx_addr + 8);
132 writeq_relaxed(msg[0], mbx_addr);
133 }
134 }
135
136 /* Responds to VF's READY message with VF's
137 * ID, node, MAC address e.t.c
138 * @vf: VF which sent READY message
139 */
140 static void nic_mbx_send_ready(struct nicpf *nic, int vf)
141 {
142 union nic_mbx mbx = {};
143 int bgx_idx, lmac;
144 const char *mac;
145
146 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
147 mbx.nic_cfg.vf_id = vf;
148
149 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
150
151 if (vf < MAX_LMAC) {
152 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
153 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
154
155 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
156 if (mac)
157 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac);
158 }
159 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false;
160 mbx.nic_cfg.node_id = nic->node;
161
162 mbx.nic_cfg.loopback_supported = vf < MAX_LMAC;
163
164 nic_send_msg_to_vf(nic, vf, &mbx);
165 }
166
167 /* ACKs VF's mailbox message
168 * @vf: VF to which ACK to be sent
169 */
170 static void nic_mbx_send_ack(struct nicpf *nic, int vf)
171 {
172 union nic_mbx mbx = {};
173
174 mbx.msg.msg = NIC_MBOX_MSG_ACK;
175 nic_send_msg_to_vf(nic, vf, &mbx);
176 }
177
178 /* NACKs VF's mailbox message that PF is not able to
179 * complete the action
180 * @vf: VF to which ACK to be sent
181 */
182 static void nic_mbx_send_nack(struct nicpf *nic, int vf)
183 {
184 union nic_mbx mbx = {};
185
186 mbx.msg.msg = NIC_MBOX_MSG_NACK;
187 nic_send_msg_to_vf(nic, vf, &mbx);
188 }
189
190 /* Flush all in flight receive packets to memory and
191 * bring down an active RQ
192 */
193 static int nic_rcv_queue_sw_sync(struct nicpf *nic)
194 {
195 u16 timeout = ~0x00;
196
197 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
198 /* Wait till sync cycle is finished */
199 while (timeout) {
200 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
201 break;
202 timeout--;
203 }
204 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
205 if (!timeout) {
206 dev_err(&nic->pdev->dev, "Receive queue software sync failed");
207 return 1;
208 }
209 return 0;
210 }
211
212 /* Get BGX Rx/Tx stats and respond to VF's request */
213 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
214 {
215 int bgx_idx, lmac;
216 union nic_mbx mbx = {};
217
218 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
219 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
220
221 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
222 mbx.bgx_stats.vf_id = bgx->vf_id;
223 mbx.bgx_stats.rx = bgx->rx;
224 mbx.bgx_stats.idx = bgx->idx;
225 if (bgx->rx)
226 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx,
227 lmac, bgx->idx);
228 else
229 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx,
230 lmac, bgx->idx);
231 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
232 }
233
234 /* Update hardware min/max frame size */
235 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
236 {
237 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) {
238 dev_err(&nic->pdev->dev,
239 "Invalid MTU setting from VF%d rejected, should be between %d and %d\n",
240 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS);
241 return 1;
242 }
243 new_frs += ETH_HLEN;
244 if (new_frs <= nic->pkind.maxlen)
245 return 0;
246
247 nic->pkind.maxlen = new_frs;
248 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(u64 *)&nic->pkind);
249 return 0;
250 }
251
252 /* Set minimum transmit packet size */
253 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size)
254 {
255 int lmac;
256 u64 lmac_cfg;
257
258 /* Max value that can be set is 60 */
259 if (size > 60)
260 size = 60;
261
262 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) {
263 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
264 lmac_cfg &= ~(0xF << 2);
265 lmac_cfg |= ((size / 4) << 2);
266 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
267 }
268 }
269
270 /* Function to check number of LMACs present and set VF::LMAC mapping.
271 * Mapping will be used while initializing channels.
272 */
273 static void nic_set_lmac_vf_mapping(struct nicpf *nic)
274 {
275 unsigned bgx_map = bgx_get_map(nic->node);
276 int bgx, next_bgx_lmac = 0;
277 int lmac, lmac_cnt = 0;
278 u64 lmac_credit;
279
280 nic->num_vf_en = 0;
281
282 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) {
283 if (!(bgx_map & (1 << bgx)))
284 continue;
285 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
286 for (lmac = 0; lmac < lmac_cnt; lmac++)
287 nic->vf_lmac_map[next_bgx_lmac++] =
288 NIC_SET_VF_LMAC_MAP(bgx, lmac);
289 nic->num_vf_en += lmac_cnt;
290
291 /* Program LMAC credits */
292 lmac_credit = (1ull << 1); /* channel credit enable */
293 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
294 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
295 lmac_credit |= (((((48 * 1024) / lmac_cnt) -
296 NIC_HW_MAX_FRS) / 16) << 12);
297 lmac = bgx * MAX_LMAC_PER_BGX;
298 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
299 nic_reg_write(nic,
300 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
301 lmac_credit);
302 }
303 }
304
305 #define BGX0_BLOCK 8
306 #define BGX1_BLOCK 9
307
308 static void nic_init_hw(struct nicpf *nic)
309 {
310 int i;
311
312 /* Enable NIC HW block */
313 nic_reg_write(nic, NIC_PF_CFG, 0x3);
314
315 /* Enable backpressure */
316 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
317
318 /* Disable TNS mode on both interfaces */
319 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
320 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
321 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
322 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
323 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
324 (1ULL << 63) | BGX0_BLOCK);
325 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
326 (1ULL << 63) | BGX1_BLOCK);
327
328 /* PKIND configuration */
329 nic->pkind.minlen = 0;
330 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN;
331 nic->pkind.lenerr_en = 1;
332 nic->pkind.rx_hdr = 0;
333 nic->pkind.hdr_sl = 0;
334
335 for (i = 0; i < NIC_MAX_PKIND; i++)
336 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
337 *(u64 *)&nic->pkind);
338
339 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
340
341 /* Timer config */
342 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
343
344 /* Enable VLAN ethertype matching and stripping */
345 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7,
346 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q);
347 }
348
349 /* Channel parse index configuration */
350 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
351 {
352 u32 vnic, bgx, lmac, chan;
353 u32 padd, cpi_count = 0;
354 u64 cpi_base, cpi, rssi_base, rssi;
355 u8 qset, rq_idx = 0;
356
357 vnic = cfg->vf_id;
358 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
359 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
360
361 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
362 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX);
363 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX);
364
365 /* Rx channel configuration */
366 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
367 (1ull << 63) | (vnic << 0));
368 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
369 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48));
370
371 if (cfg->cpi_alg == CPI_ALG_NONE)
372 cpi_count = 1;
373 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
374 cpi_count = 8;
375 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
376 cpi_count = 16;
377 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
378 cpi_count = NIC_MAX_CPI_PER_LMAC;
379
380 /* RSS Qset, Qidx mapping */
381 qset = cfg->vf_id;
382 rssi = rssi_base;
383 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
384 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
385 (qset << 3) | rq_idx);
386 rq_idx++;
387 }
388
389 rssi = 0;
390 cpi = cpi_base;
391 for (; cpi < (cpi_base + cpi_count); cpi++) {
392 /* Determine port to channel adder */
393 if (cfg->cpi_alg != CPI_ALG_DIFF)
394 padd = cpi % cpi_count;
395 else
396 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
397
398 /* Leave RSS_SIZE as '0' to disable RSS */
399 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
400 (vnic << 24) | (padd << 16) | (rssi_base + rssi));
401
402 if ((rssi + 1) >= cfg->rq_cnt)
403 continue;
404
405 if (cfg->cpi_alg == CPI_ALG_VLAN)
406 rssi++;
407 else if (cfg->cpi_alg == CPI_ALG_VLAN16)
408 rssi = ((cpi - cpi_base) & 0xe) >> 1;
409 else if (cfg->cpi_alg == CPI_ALG_DIFF)
410 rssi = ((cpi - cpi_base) & 0x38) >> 3;
411 }
412 nic->cpi_base[cfg->vf_id] = cpi_base;
413 }
414
415 /* Responsds to VF with its RSS indirection table size */
416 static void nic_send_rss_size(struct nicpf *nic, int vf)
417 {
418 union nic_mbx mbx = {};
419 u64 *msg;
420
421 msg = (u64 *)&mbx;
422
423 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
424 mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size;
425 nic_send_msg_to_vf(nic, vf, &mbx);
426 }
427
428 /* Receive side scaling configuration
429 * configure:
430 * - RSS index
431 * - indir table i.e hash::RQ mapping
432 * - no of hash bits to consider
433 */
434 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
435 {
436 u8 qset, idx = 0;
437 u64 cpi_cfg, cpi_base, rssi_base, rssi;
438
439 cpi_base = nic->cpi_base[cfg->vf_id];
440 cpi_cfg = nic_reg_read(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3));
441 rssi_base = (cpi_cfg & 0x0FFF) + cfg->tbl_offset;
442
443 rssi = rssi_base;
444 qset = cfg->vf_id;
445
446 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
447 u8 svf = cfg->ind_tbl[idx] >> 3;
448
449 if (svf)
450 qset = nic->vf_sqs[cfg->vf_id][svf - 1];
451 else
452 qset = cfg->vf_id;
453 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
454 (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
455 idx++;
456 }
457
458 cpi_cfg &= ~(0xFULL << 20);
459 cpi_cfg |= (cfg->hash_bits << 20);
460 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3), cpi_cfg);
461 }
462
463 /* 4 level transmit side scheduler configutation
464 * for TNS bypass mode
465 *
466 * Sample configuration for SQ0
467 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
468 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
469 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
470 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
471 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
472 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
473 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
474 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
475 */
476 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
477 struct sq_cfg_msg *sq)
478 {
479 u32 bgx, lmac, chan;
480 u32 tl2, tl3, tl4;
481 u32 rr_quantum;
482 u8 sq_idx = sq->sq_num;
483 u8 pqs_vnic;
484
485 if (sq->sqs_mode)
486 pqs_vnic = nic->pqs_vf[vnic];
487 else
488 pqs_vnic = vnic;
489
490 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
491 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
492
493 /* 24 bytes for FCS, IPG and preamble */
494 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
495
496 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX);
497 tl4 += sq_idx;
498 if (sq->sqs_mode)
499 tl4 += vnic * 8;
500
501 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3);
502 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
503 ((u64)vnic << NIC_QS_ID_SHIFT) |
504 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
505 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
506 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
507
508 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
509 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
510 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
511 /* Enable backpressure on the channel */
512 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
513
514 tl2 = tl3 >> 2;
515 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
516 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
517 /* No priorities as of now */
518 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
519 }
520
521 /* Send primary nicvf pointer to secondary QS's VF */
522 static void nic_send_pnicvf(struct nicpf *nic, int sqs)
523 {
524 union nic_mbx mbx = {};
525
526 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
527 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]];
528 nic_send_msg_to_vf(nic, sqs, &mbx);
529 }
530
531 /* Send SQS's nicvf pointer to primary QS's VF */
532 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf)
533 {
534 union nic_mbx mbx = {};
535 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id];
536
537 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
538 mbx.nicvf.sqs_id = nicvf->sqs_id;
539 mbx.nicvf.nicvf = nic->nicvf[sqs_id];
540 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx);
541 }
542
543 /* Find next available Qset that can be assigned as a
544 * secondary Qset to a VF.
545 */
546 static int nic_nxt_avail_sqs(struct nicpf *nic)
547 {
548 int sqs;
549
550 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) {
551 if (!nic->sqs_used[sqs])
552 nic->sqs_used[sqs] = true;
553 else
554 continue;
555 return sqs + nic->num_vf_en;
556 }
557 return -1;
558 }
559
560 /* Allocate additional Qsets for requested VF */
561 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs)
562 {
563 union nic_mbx mbx = {};
564 int idx, alloc_qs = 0;
565 int sqs_id;
566
567 if (!nic->num_sqs_en)
568 goto send_mbox;
569
570 for (idx = 0; idx < sqs->qs_count; idx++) {
571 sqs_id = nic_nxt_avail_sqs(nic);
572 if (sqs_id < 0)
573 break;
574 nic->vf_sqs[sqs->vf_id][idx] = sqs_id;
575 nic->pqs_vf[sqs_id] = sqs->vf_id;
576 alloc_qs++;
577 }
578
579 send_mbox:
580 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
581 mbx.sqs_alloc.vf_id = sqs->vf_id;
582 mbx.sqs_alloc.qs_count = alloc_qs;
583 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx);
584 }
585
586 static int nic_config_loopback(struct nicpf *nic, struct set_loopback *lbk)
587 {
588 int bgx_idx, lmac_idx;
589
590 if (lbk->vf_id > MAX_LMAC)
591 return -1;
592
593 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
594 lmac_idx = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lbk->vf_id]);
595
596 bgx_lmac_internal_loopback(nic->node, bgx_idx, lmac_idx, lbk->enable);
597
598 return 0;
599 }
600
601 /* Interrupt handler to handle mailbox messages from VFs */
602 static void nic_handle_mbx_intr(struct nicpf *nic, int vf)
603 {
604 union nic_mbx mbx = {};
605 u64 *mbx_data;
606 u64 mbx_addr;
607 u64 reg_addr;
608 u64 cfg;
609 int bgx, lmac;
610 int i;
611 int ret = 0;
612
613 nic->mbx_lock[vf] = true;
614
615 mbx_addr = nic_get_mbx_addr(vf);
616 mbx_data = (u64 *)&mbx;
617
618 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
619 *mbx_data = nic_reg_read(nic, mbx_addr);
620 mbx_data++;
621 mbx_addr += sizeof(u64);
622 }
623
624 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg %d from VF%d\n",
625 __func__, mbx.msg.msg, vf);
626 switch (mbx.msg.msg) {
627 case NIC_MBOX_MSG_READY:
628 nic_mbx_send_ready(nic, vf);
629 if (vf < MAX_LMAC) {
630 nic->link[vf] = 0;
631 nic->duplex[vf] = 0;
632 nic->speed[vf] = 0;
633 }
634 ret = 1;
635 break;
636 case NIC_MBOX_MSG_QS_CFG:
637 reg_addr = NIC_PF_QSET_0_127_CFG |
638 (mbx.qs.num << NIC_QS_ID_SHIFT);
639 cfg = mbx.qs.cfg;
640 /* Check if its a secondary Qset */
641 if (vf >= nic->num_vf_en) {
642 cfg = cfg & (~0x7FULL);
643 /* Assign this Qset to primary Qset's VF */
644 cfg |= nic->pqs_vf[vf];
645 }
646 nic_reg_write(nic, reg_addr, cfg);
647 break;
648 case NIC_MBOX_MSG_RQ_CFG:
649 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
650 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
651 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
652 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
653 break;
654 case NIC_MBOX_MSG_RQ_BP_CFG:
655 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
656 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
657 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
658 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
659 break;
660 case NIC_MBOX_MSG_RQ_SW_SYNC:
661 ret = nic_rcv_queue_sw_sync(nic);
662 break;
663 case NIC_MBOX_MSG_RQ_DROP_CFG:
664 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
665 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
666 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
667 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
668 break;
669 case NIC_MBOX_MSG_SQ_CFG:
670 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
671 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
672 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
673 nic_reg_write(nic, reg_addr, mbx.sq.cfg);
674 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq);
675 break;
676 case NIC_MBOX_MSG_SET_MAC:
677 if (vf >= nic->num_vf_en)
678 break;
679 lmac = mbx.mac.vf_id;
680 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
681 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
682 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
683 break;
684 case NIC_MBOX_MSG_SET_MAX_FRS:
685 ret = nic_update_hw_frs(nic, mbx.frs.max_frs,
686 mbx.frs.vf_id);
687 break;
688 case NIC_MBOX_MSG_CPI_CFG:
689 nic_config_cpi(nic, &mbx.cpi_cfg);
690 break;
691 case NIC_MBOX_MSG_RSS_SIZE:
692 nic_send_rss_size(nic, vf);
693 goto unlock;
694 case NIC_MBOX_MSG_RSS_CFG:
695 case NIC_MBOX_MSG_RSS_CFG_CONT:
696 nic_config_rss(nic, &mbx.rss_cfg);
697 break;
698 case NIC_MBOX_MSG_CFG_DONE:
699 /* Last message of VF config msg sequence */
700 nic->vf_enabled[vf] = true;
701 goto unlock;
702 case NIC_MBOX_MSG_SHUTDOWN:
703 /* First msg in VF teardown sequence */
704 nic->vf_enabled[vf] = false;
705 if (vf >= nic->num_vf_en)
706 nic->sqs_used[vf - nic->num_vf_en] = false;
707 nic->pqs_vf[vf] = 0;
708 break;
709 case NIC_MBOX_MSG_ALLOC_SQS:
710 nic_alloc_sqs(nic, &mbx.sqs_alloc);
711 goto unlock;
712 case NIC_MBOX_MSG_NICVF_PTR:
713 nic->nicvf[vf] = mbx.nicvf.nicvf;
714 break;
715 case NIC_MBOX_MSG_PNICVF_PTR:
716 nic_send_pnicvf(nic, vf);
717 goto unlock;
718 case NIC_MBOX_MSG_SNICVF_PTR:
719 nic_send_snicvf(nic, &mbx.nicvf);
720 goto unlock;
721 case NIC_MBOX_MSG_BGX_STATS:
722 nic_get_bgx_stats(nic, &mbx.bgx_stats);
723 goto unlock;
724 case NIC_MBOX_MSG_LOOPBACK:
725 ret = nic_config_loopback(nic, &mbx.lbk);
726 break;
727 default:
728 dev_err(&nic->pdev->dev,
729 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
730 break;
731 }
732
733 if (!ret)
734 nic_mbx_send_ack(nic, vf);
735 else if (mbx.msg.msg != NIC_MBOX_MSG_READY)
736 nic_mbx_send_nack(nic, vf);
737 unlock:
738 nic->mbx_lock[vf] = false;
739 }
740
741 static void nic_mbx_intr_handler (struct nicpf *nic, int mbx)
742 {
743 u64 intr;
744 u8 vf, vf_per_mbx_reg = 64;
745
746 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
747 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
748 for (vf = 0; vf < vf_per_mbx_reg; vf++) {
749 if (intr & (1ULL << vf)) {
750 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n",
751 vf + (mbx * vf_per_mbx_reg));
752
753 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
754 nic_clear_mbx_intr(nic, vf, mbx);
755 }
756 }
757 }
758
759 static irqreturn_t nic_mbx0_intr_handler (int irq, void *nic_irq)
760 {
761 struct nicpf *nic = (struct nicpf *)nic_irq;
762
763 nic_mbx_intr_handler(nic, 0);
764
765 return IRQ_HANDLED;
766 }
767
768 static irqreturn_t nic_mbx1_intr_handler (int irq, void *nic_irq)
769 {
770 struct nicpf *nic = (struct nicpf *)nic_irq;
771
772 nic_mbx_intr_handler(nic, 1);
773
774 return IRQ_HANDLED;
775 }
776
777 static int nic_enable_msix(struct nicpf *nic)
778 {
779 int i, ret;
780
781 nic->num_vec = NIC_PF_MSIX_VECTORS;
782
783 for (i = 0; i < nic->num_vec; i++)
784 nic->msix_entries[i].entry = i;
785
786 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
787 if (ret) {
788 dev_err(&nic->pdev->dev,
789 "Request for #%d msix vectors failed\n",
790 nic->num_vec);
791 return ret;
792 }
793
794 nic->msix_enabled = 1;
795 return 0;
796 }
797
798 static void nic_disable_msix(struct nicpf *nic)
799 {
800 if (nic->msix_enabled) {
801 pci_disable_msix(nic->pdev);
802 nic->msix_enabled = 0;
803 nic->num_vec = 0;
804 }
805 }
806
807 static void nic_free_all_interrupts(struct nicpf *nic)
808 {
809 int irq;
810
811 for (irq = 0; irq < nic->num_vec; irq++) {
812 if (nic->irq_allocated[irq])
813 free_irq(nic->msix_entries[irq].vector, nic);
814 nic->irq_allocated[irq] = false;
815 }
816 }
817
818 static int nic_register_interrupts(struct nicpf *nic)
819 {
820 int ret;
821
822 /* Enable MSI-X */
823 ret = nic_enable_msix(nic);
824 if (ret)
825 return ret;
826
827 /* Register mailbox interrupt handlers */
828 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector,
829 nic_mbx0_intr_handler, 0, "NIC Mbox0", nic);
830 if (ret)
831 goto fail;
832
833 nic->irq_allocated[NIC_PF_INTR_ID_MBOX0] = true;
834
835 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX1].vector,
836 nic_mbx1_intr_handler, 0, "NIC Mbox1", nic);
837 if (ret)
838 goto fail;
839
840 nic->irq_allocated[NIC_PF_INTR_ID_MBOX1] = true;
841
842 /* Enable mailbox interrupt */
843 nic_enable_mbx_intr(nic);
844 return 0;
845
846 fail:
847 dev_err(&nic->pdev->dev, "Request irq failed\n");
848 nic_free_all_interrupts(nic);
849 return ret;
850 }
851
852 static void nic_unregister_interrupts(struct nicpf *nic)
853 {
854 nic_free_all_interrupts(nic);
855 nic_disable_msix(nic);
856 }
857
858 static int nic_num_sqs_en(struct nicpf *nic, int vf_en)
859 {
860 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE;
861 u16 total_vf;
862
863 /* Check if its a multi-node environment */
864 if (nr_node_ids > 1)
865 sqs_per_vf = MAX_SQS_PER_VF;
866
867 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV);
868 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf);
869 return min(total_vf - vf_en, vf_en * sqs_per_vf);
870 }
871
872 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic)
873 {
874 int pos = 0;
875 int vf_en;
876 int err;
877 u16 total_vf_cnt;
878
879 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
880 if (!pos) {
881 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
882 return -ENODEV;
883 }
884
885 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
886 if (total_vf_cnt < nic->num_vf_en)
887 nic->num_vf_en = total_vf_cnt;
888
889 if (!total_vf_cnt)
890 return 0;
891
892 vf_en = nic->num_vf_en;
893 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en);
894 vf_en += nic->num_sqs_en;
895
896 err = pci_enable_sriov(pdev, vf_en);
897 if (err) {
898 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
899 vf_en);
900 nic->num_vf_en = 0;
901 return err;
902 }
903
904 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
905 vf_en);
906
907 nic->flags |= NIC_SRIOV_ENABLED;
908 return 0;
909 }
910
911 /* Poll for BGX LMAC link status and update corresponding VF
912 * if there is a change, valid only if internal L2 switch
913 * is not present otherwise VF link is always treated as up
914 */
915 static void nic_poll_for_link(struct work_struct *work)
916 {
917 union nic_mbx mbx = {};
918 struct nicpf *nic;
919 struct bgx_link_status link;
920 u8 vf, bgx, lmac;
921
922 nic = container_of(work, struct nicpf, dwork.work);
923
924 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
925
926 for (vf = 0; vf < nic->num_vf_en; vf++) {
927 /* Poll only if VF is UP */
928 if (!nic->vf_enabled[vf])
929 continue;
930
931 /* Get BGX, LMAC indices for the VF */
932 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
933 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
934 /* Get interface link status */
935 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
936
937 /* Inform VF only if link status changed */
938 if (nic->link[vf] == link.link_up)
939 continue;
940
941 if (!nic->mbx_lock[vf]) {
942 nic->link[vf] = link.link_up;
943 nic->duplex[vf] = link.duplex;
944 nic->speed[vf] = link.speed;
945
946 /* Send a mbox message to VF with current link status */
947 mbx.link_status.link_up = link.link_up;
948 mbx.link_status.duplex = link.duplex;
949 mbx.link_status.speed = link.speed;
950 nic_send_msg_to_vf(nic, vf, &mbx);
951 }
952 }
953 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2);
954 }
955
956 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
957 {
958 struct device *dev = &pdev->dev;
959 struct nicpf *nic;
960 int err;
961
962 BUILD_BUG_ON(sizeof(union nic_mbx) > 16);
963
964 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL);
965 if (!nic)
966 return -ENOMEM;
967
968 pci_set_drvdata(pdev, nic);
969
970 nic->pdev = pdev;
971
972 err = pci_enable_device(pdev);
973 if (err) {
974 dev_err(dev, "Failed to enable PCI device\n");
975 pci_set_drvdata(pdev, NULL);
976 return err;
977 }
978
979 err = pci_request_regions(pdev, DRV_NAME);
980 if (err) {
981 dev_err(dev, "PCI request regions failed 0x%x\n", err);
982 goto err_disable_device;
983 }
984
985 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
986 if (err) {
987 dev_err(dev, "Unable to get usable DMA configuration\n");
988 goto err_release_regions;
989 }
990
991 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
992 if (err) {
993 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
994 goto err_release_regions;
995 }
996
997 /* MAP PF's configuration registers */
998 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
999 if (!nic->reg_base) {
1000 dev_err(dev, "Cannot map config register space, aborting\n");
1001 err = -ENOMEM;
1002 goto err_release_regions;
1003 }
1004
1005 nic->node = nic_get_node_id(pdev);
1006
1007 nic_set_lmac_vf_mapping(nic);
1008
1009 /* Initialize hardware */
1010 nic_init_hw(nic);
1011
1012 /* Set RSS TBL size for each VF */
1013 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
1014
1015 /* Register interrupts */
1016 err = nic_register_interrupts(nic);
1017 if (err)
1018 goto err_release_regions;
1019
1020 /* Configure SRIOV */
1021 err = nic_sriov_init(pdev, nic);
1022 if (err)
1023 goto err_unregister_interrupts;
1024
1025 /* Register a physical link status poll fn() */
1026 nic->check_link = alloc_workqueue("check_link_status",
1027 WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
1028 if (!nic->check_link) {
1029 err = -ENOMEM;
1030 goto err_disable_sriov;
1031 }
1032
1033 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link);
1034 queue_delayed_work(nic->check_link, &nic->dwork, 0);
1035
1036 return 0;
1037
1038 err_disable_sriov:
1039 if (nic->flags & NIC_SRIOV_ENABLED)
1040 pci_disable_sriov(pdev);
1041 err_unregister_interrupts:
1042 nic_unregister_interrupts(nic);
1043 err_release_regions:
1044 pci_release_regions(pdev);
1045 err_disable_device:
1046 pci_disable_device(pdev);
1047 pci_set_drvdata(pdev, NULL);
1048 return err;
1049 }
1050
1051 static void nic_remove(struct pci_dev *pdev)
1052 {
1053 struct nicpf *nic = pci_get_drvdata(pdev);
1054
1055 if (nic->flags & NIC_SRIOV_ENABLED)
1056 pci_disable_sriov(pdev);
1057
1058 if (nic->check_link) {
1059 /* Destroy work Queue */
1060 cancel_delayed_work(&nic->dwork);
1061 flush_workqueue(nic->check_link);
1062 destroy_workqueue(nic->check_link);
1063 }
1064
1065 nic_unregister_interrupts(nic);
1066 pci_release_regions(pdev);
1067 pci_disable_device(pdev);
1068 pci_set_drvdata(pdev, NULL);
1069 }
1070
1071 static struct pci_driver nic_driver = {
1072 .name = DRV_NAME,
1073 .id_table = nic_id_table,
1074 .probe = nic_probe,
1075 .remove = nic_remove,
1076 };
1077
1078 static int __init nic_init_module(void)
1079 {
1080 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1081
1082 return pci_register_driver(&nic_driver);
1083 }
1084
1085 static void __exit nic_cleanup_module(void)
1086 {
1087 pci_unregister_driver(&nic_driver);
1088 }
1089
1090 module_init(nic_init_module);
1091 module_exit(nic_cleanup_module);
Linux kernel - Deliverables
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