2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/etherdevice.h>
18 #include "thunder_bgx.h"
20 #define DRV_NAME "thunder-nic"
21 #define DRV_VERSION "1.0"
28 u8 num_vf_en
; /* No of VF enabled */
29 bool vf_enabled
[MAX_NUM_VFS_SUPPORTED
];
30 void __iomem
*reg_base
; /* Register start address */
31 struct pkind_cfg pkind
;
32 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF))
33 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF)
34 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF)
35 u8 vf_lmac_map
[MAX_LMAC
];
36 struct delayed_work dwork
;
37 struct workqueue_struct
*check_link
;
41 u16 cpi_base
[MAX_NUM_VFS_SUPPORTED
];
43 bool mbx_lock
[MAX_NUM_VFS_SUPPORTED
];
48 struct msix_entry msix_entries
[NIC_PF_MSIX_VECTORS
];
49 bool irq_allocated
[NIC_PF_MSIX_VECTORS
];
52 /* Supported devices */
53 static const struct pci_device_id nic_id_table
[] = {
54 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_NIC_PF
) },
55 { 0, } /* end of table */
58 MODULE_AUTHOR("Sunil Goutham");
59 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
60 MODULE_LICENSE("GPL v2");
61 MODULE_VERSION(DRV_VERSION
);
62 MODULE_DEVICE_TABLE(pci
, nic_id_table
);
64 /* The Cavium ThunderX network controller can *only* be found in SoCs
65 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
66 * registers on this platform are implicitly strongly ordered with respect
67 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
68 * with no memory barriers in this driver. The readq()/writeq() functions add
69 * explicit ordering operation which in this case are redundant, and only
73 /* Register read/write APIs */
74 static void nic_reg_write(struct nicpf
*nic
, u64 offset
, u64 val
)
76 writeq_relaxed(val
, nic
->reg_base
+ offset
);
79 static u64
nic_reg_read(struct nicpf
*nic
, u64 offset
)
81 return readq_relaxed(nic
->reg_base
+ offset
);
84 /* PF -> VF mailbox communication APIs */
85 static void nic_enable_mbx_intr(struct nicpf
*nic
)
87 /* Enable mailbox interrupt for all 128 VFs */
88 nic_reg_write(nic
, NIC_PF_MAILBOX_ENA_W1S
, ~0ull);
89 nic_reg_write(nic
, NIC_PF_MAILBOX_ENA_W1S
+ sizeof(u64
), ~0ull);
92 static void nic_clear_mbx_intr(struct nicpf
*nic
, int vf
, int mbx_reg
)
94 nic_reg_write(nic
, NIC_PF_MAILBOX_INT
+ (mbx_reg
<< 3), BIT_ULL(vf
));
97 static u64
nic_get_mbx_addr(int vf
)
99 return NIC_PF_VF_0_127_MAILBOX_0_1
+ (vf
<< NIC_VF_NUM_SHIFT
);
102 /* Send a mailbox message to VF
103 * @vf: vf to which this message to be sent
104 * @mbx: Message to be sent
106 static void nic_send_msg_to_vf(struct nicpf
*nic
, int vf
, union nic_mbx
*mbx
)
108 void __iomem
*mbx_addr
= nic
->reg_base
+ nic_get_mbx_addr(vf
);
109 u64
*msg
= (u64
*)mbx
;
111 /* In first revision HW, mbox interrupt is triggerred
112 * when PF writes to MBOX(1), in next revisions when
113 * PF writes to MBOX(0)
115 if (nic
->rev_id
== 0) {
116 /* see the comment for nic_reg_write()/nic_reg_read()
119 writeq_relaxed(msg
[0], mbx_addr
);
120 writeq_relaxed(msg
[1], mbx_addr
+ 8);
122 writeq_relaxed(msg
[1], mbx_addr
+ 8);
123 writeq_relaxed(msg
[0], mbx_addr
);
127 /* Responds to VF's READY message with VF's
128 * ID, node, MAC address e.t.c
129 * @vf: VF which sent READY message
131 static void nic_mbx_send_ready(struct nicpf
*nic
, int vf
)
133 union nic_mbx mbx
= {};
137 mbx
.nic_cfg
.msg
= NIC_MBOX_MSG_READY
;
138 mbx
.nic_cfg
.vf_id
= vf
;
140 mbx
.nic_cfg
.tns_mode
= NIC_TNS_BYPASS_MODE
;
142 bgx_idx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
143 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
145 mac
= bgx_get_lmac_mac(nic
->node
, bgx_idx
, lmac
);
147 ether_addr_copy((u8
*)&mbx
.nic_cfg
.mac_addr
, mac
);
149 mbx
.nic_cfg
.node_id
= nic
->node
;
150 nic_send_msg_to_vf(nic
, vf
, &mbx
);
153 /* ACKs VF's mailbox message
154 * @vf: VF to which ACK to be sent
156 static void nic_mbx_send_ack(struct nicpf
*nic
, int vf
)
158 union nic_mbx mbx
= {};
160 mbx
.msg
.msg
= NIC_MBOX_MSG_ACK
;
161 nic_send_msg_to_vf(nic
, vf
, &mbx
);
164 /* NACKs VF's mailbox message that PF is not able to
165 * complete the action
166 * @vf: VF to which ACK to be sent
168 static void nic_mbx_send_nack(struct nicpf
*nic
, int vf
)
170 union nic_mbx mbx
= {};
172 mbx
.msg
.msg
= NIC_MBOX_MSG_NACK
;
173 nic_send_msg_to_vf(nic
, vf
, &mbx
);
176 /* Flush all in flight receive packets to memory and
177 * bring down an active RQ
179 static int nic_rcv_queue_sw_sync(struct nicpf
*nic
)
183 nic_reg_write(nic
, NIC_PF_SW_SYNC_RX
, 0x01);
184 /* Wait till sync cycle is finished */
186 if (nic_reg_read(nic
, NIC_PF_SW_SYNC_RX_DONE
) & 0x1)
190 nic_reg_write(nic
, NIC_PF_SW_SYNC_RX
, 0x00);
192 dev_err(&nic
->pdev
->dev
, "Receive queue software sync failed");
198 /* Get BGX Rx/Tx stats and respond to VF's request */
199 static void nic_get_bgx_stats(struct nicpf
*nic
, struct bgx_stats_msg
*bgx
)
202 union nic_mbx mbx
= {};
204 bgx_idx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[bgx
->vf_id
]);
205 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[bgx
->vf_id
]);
207 mbx
.bgx_stats
.msg
= NIC_MBOX_MSG_BGX_STATS
;
208 mbx
.bgx_stats
.vf_id
= bgx
->vf_id
;
209 mbx
.bgx_stats
.rx
= bgx
->rx
;
210 mbx
.bgx_stats
.idx
= bgx
->idx
;
212 mbx
.bgx_stats
.stats
= bgx_get_rx_stats(nic
->node
, bgx_idx
,
215 mbx
.bgx_stats
.stats
= bgx_get_tx_stats(nic
->node
, bgx_idx
,
217 nic_send_msg_to_vf(nic
, bgx
->vf_id
, &mbx
);
220 /* Update hardware min/max frame size */
221 static int nic_update_hw_frs(struct nicpf
*nic
, int new_frs
, int vf
)
223 if ((new_frs
> NIC_HW_MAX_FRS
) || (new_frs
< NIC_HW_MIN_FRS
)) {
224 dev_err(&nic
->pdev
->dev
,
225 "Invalid MTU setting from VF%d rejected, should be between %d and %d\n",
226 vf
, NIC_HW_MIN_FRS
, NIC_HW_MAX_FRS
);
230 if (new_frs
<= nic
->pkind
.maxlen
)
233 nic
->pkind
.maxlen
= new_frs
;
234 nic_reg_write(nic
, NIC_PF_PKIND_0_15_CFG
, *(u64
*)&nic
->pkind
);
238 /* Set minimum transmit packet size */
239 static void nic_set_tx_pkt_pad(struct nicpf
*nic
, int size
)
244 /* Max value that can be set is 60 */
248 for (lmac
= 0; lmac
< (MAX_BGX_PER_CN88XX
* MAX_LMAC_PER_BGX
); lmac
++) {
249 lmac_cfg
= nic_reg_read(nic
, NIC_PF_LMAC_0_7_CFG
| (lmac
<< 3));
250 lmac_cfg
&= ~(0xF << 2);
251 lmac_cfg
|= ((size
/ 4) << 2);
252 nic_reg_write(nic
, NIC_PF_LMAC_0_7_CFG
| (lmac
<< 3), lmac_cfg
);
256 /* Function to check number of LMACs present and set VF::LMAC mapping.
257 * Mapping will be used while initializing channels.
259 static void nic_set_lmac_vf_mapping(struct nicpf
*nic
)
261 unsigned bgx_map
= bgx_get_map(nic
->node
);
262 int bgx
, next_bgx_lmac
= 0;
263 int lmac
, lmac_cnt
= 0;
268 for (bgx
= 0; bgx
< NIC_MAX_BGX
; bgx
++) {
269 if (!(bgx_map
& (1 << bgx
)))
271 lmac_cnt
= bgx_get_lmac_count(nic
->node
, bgx
);
272 for (lmac
= 0; lmac
< lmac_cnt
; lmac
++)
273 nic
->vf_lmac_map
[next_bgx_lmac
++] =
274 NIC_SET_VF_LMAC_MAP(bgx
, lmac
);
275 nic
->num_vf_en
+= lmac_cnt
;
277 /* Program LMAC credits */
278 lmac_credit
= (1ull << 1); /* channel credit enable */
279 lmac_credit
|= (0x1ff << 2); /* Max outstanding pkt count */
280 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
281 lmac_credit
|= (((((48 * 1024) / lmac_cnt
) -
282 NIC_HW_MAX_FRS
) / 16) << 12);
283 lmac
= bgx
* MAX_LMAC_PER_BGX
;
284 for (; lmac
< lmac_cnt
+ (bgx
* MAX_LMAC_PER_BGX
); lmac
++)
286 NIC_PF_LMAC_0_7_CREDIT
+ (lmac
* 8),
294 static void nic_init_hw(struct nicpf
*nic
)
298 /* Reset NIC, in case the driver is repeatedly inserted and removed */
299 nic_reg_write(nic
, NIC_PF_SOFT_RESET
, 1);
301 /* Enable NIC HW block */
302 nic_reg_write(nic
, NIC_PF_CFG
, 0x3);
304 /* Enable backpressure */
305 nic_reg_write(nic
, NIC_PF_BP_CFG
, (1ULL << 6) | 0x03);
307 /* Disable TNS mode on both interfaces */
308 nic_reg_write(nic
, NIC_PF_INTF_0_1_SEND_CFG
,
309 (NIC_TNS_BYPASS_MODE
<< 7) | BGX0_BLOCK
);
310 nic_reg_write(nic
, NIC_PF_INTF_0_1_SEND_CFG
| (1 << 8),
311 (NIC_TNS_BYPASS_MODE
<< 7) | BGX1_BLOCK
);
312 nic_reg_write(nic
, NIC_PF_INTF_0_1_BP_CFG
,
313 (1ULL << 63) | BGX0_BLOCK
);
314 nic_reg_write(nic
, NIC_PF_INTF_0_1_BP_CFG
+ (1 << 8),
315 (1ULL << 63) | BGX1_BLOCK
);
317 /* PKIND configuration */
318 nic
->pkind
.minlen
= 0;
319 nic
->pkind
.maxlen
= NIC_HW_MAX_FRS
+ ETH_HLEN
;
320 nic
->pkind
.lenerr_en
= 1;
321 nic
->pkind
.rx_hdr
= 0;
322 nic
->pkind
.hdr_sl
= 0;
324 for (i
= 0; i
< NIC_MAX_PKIND
; i
++)
325 nic_reg_write(nic
, NIC_PF_PKIND_0_15_CFG
| (i
<< 3),
326 *(u64
*)&nic
->pkind
);
328 nic_set_tx_pkt_pad(nic
, NIC_HW_MIN_FRS
);
331 nic_reg_write(nic
, NIC_PF_INTR_TIMER_CFG
, NICPF_CLK_PER_INT_TICK
);
333 /* Enable VLAN ethertype matching and stripping */
334 nic_reg_write(nic
, NIC_PF_RX_ETYPE_0_7
,
335 (2 << 19) | (ETYPE_ALG_VLAN_STRIP
<< 16) | ETH_P_8021Q
);
338 /* Channel parse index configuration */
339 static void nic_config_cpi(struct nicpf
*nic
, struct cpi_cfg_msg
*cfg
)
341 u32 vnic
, bgx
, lmac
, chan
;
342 u32 padd
, cpi_count
= 0;
343 u64 cpi_base
, cpi
, rssi_base
, rssi
;
347 bgx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vnic
]);
348 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vnic
]);
350 chan
= (lmac
* MAX_BGX_CHANS_PER_LMAC
) + (bgx
* NIC_CHANS_PER_INF
);
351 cpi_base
= (lmac
* NIC_MAX_CPI_PER_LMAC
) + (bgx
* NIC_CPI_PER_BGX
);
352 rssi_base
= (lmac
* nic
->rss_ind_tbl_size
) + (bgx
* NIC_RSSI_PER_BGX
);
354 /* Rx channel configuration */
355 nic_reg_write(nic
, NIC_PF_CHAN_0_255_RX_BP_CFG
| (chan
<< 3),
356 (1ull << 63) | (vnic
<< 0));
357 nic_reg_write(nic
, NIC_PF_CHAN_0_255_RX_CFG
| (chan
<< 3),
358 ((u64
)cfg
->cpi_alg
<< 62) | (cpi_base
<< 48));
360 if (cfg
->cpi_alg
== CPI_ALG_NONE
)
362 else if (cfg
->cpi_alg
== CPI_ALG_VLAN
) /* 3 bits of PCP */
364 else if (cfg
->cpi_alg
== CPI_ALG_VLAN16
) /* 3 bits PCP + DEI */
366 else if (cfg
->cpi_alg
== CPI_ALG_DIFF
) /* 6bits DSCP */
367 cpi_count
= NIC_MAX_CPI_PER_LMAC
;
369 /* RSS Qset, Qidx mapping */
372 for (; rssi
< (rssi_base
+ cfg
->rq_cnt
); rssi
++) {
373 nic_reg_write(nic
, NIC_PF_RSSI_0_4097_RQ
| (rssi
<< 3),
374 (qset
<< 3) | rq_idx
);
380 for (; cpi
< (cpi_base
+ cpi_count
); cpi
++) {
381 /* Determine port to channel adder */
382 if (cfg
->cpi_alg
!= CPI_ALG_DIFF
)
383 padd
= cpi
% cpi_count
;
385 padd
= cpi
% 8; /* 3 bits CS out of 6bits DSCP */
387 /* Leave RSS_SIZE as '0' to disable RSS */
388 nic_reg_write(nic
, NIC_PF_CPI_0_2047_CFG
| (cpi
<< 3),
389 (vnic
<< 24) | (padd
<< 16) | (rssi_base
+ rssi
));
391 if ((rssi
+ 1) >= cfg
->rq_cnt
)
394 if (cfg
->cpi_alg
== CPI_ALG_VLAN
)
396 else if (cfg
->cpi_alg
== CPI_ALG_VLAN16
)
397 rssi
= ((cpi
- cpi_base
) & 0xe) >> 1;
398 else if (cfg
->cpi_alg
== CPI_ALG_DIFF
)
399 rssi
= ((cpi
- cpi_base
) & 0x38) >> 3;
401 nic
->cpi_base
[cfg
->vf_id
] = cpi_base
;
404 /* Responsds to VF with its RSS indirection table size */
405 static void nic_send_rss_size(struct nicpf
*nic
, int vf
)
407 union nic_mbx mbx
= {};
412 mbx
.rss_size
.msg
= NIC_MBOX_MSG_RSS_SIZE
;
413 mbx
.rss_size
.ind_tbl_size
= nic
->rss_ind_tbl_size
;
414 nic_send_msg_to_vf(nic
, vf
, &mbx
);
417 /* Receive side scaling configuration
420 * - indir table i.e hash::RQ mapping
421 * - no of hash bits to consider
423 static void nic_config_rss(struct nicpf
*nic
, struct rss_cfg_msg
*cfg
)
426 u64 cpi_cfg
, cpi_base
, rssi_base
, rssi
;
428 cpi_base
= nic
->cpi_base
[cfg
->vf_id
];
429 cpi_cfg
= nic_reg_read(nic
, NIC_PF_CPI_0_2047_CFG
| (cpi_base
<< 3));
430 rssi_base
= (cpi_cfg
& 0x0FFF) + cfg
->tbl_offset
;
435 for (; rssi
< (rssi_base
+ cfg
->tbl_len
); rssi
++) {
436 nic_reg_write(nic
, NIC_PF_RSSI_0_4097_RQ
| (rssi
<< 3),
437 (qset
<< 3) | (cfg
->ind_tbl
[idx
] & 0x7));
441 cpi_cfg
&= ~(0xFULL
<< 20);
442 cpi_cfg
|= (cfg
->hash_bits
<< 20);
443 nic_reg_write(nic
, NIC_PF_CPI_0_2047_CFG
| (cpi_base
<< 3), cpi_cfg
);
446 /* 4 level transmit side scheduler configutation
447 * for TNS bypass mode
449 * Sample configuration for SQ0
450 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
451 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
452 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
453 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
454 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
455 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
456 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
457 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
459 static void nic_tx_channel_cfg(struct nicpf
*nic
, u8 vnic
, u8 sq_idx
)
465 bgx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vnic
]);
466 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vnic
]);
467 /* 24 bytes for FCS, IPG and preamble */
468 rr_quantum
= ((NIC_HW_MAX_FRS
+ 24) / 4);
470 tl4
= (lmac
* NIC_TL4_PER_LMAC
) + (bgx
* NIC_TL4_PER_BGX
);
472 tl3
= tl4
/ (NIC_MAX_TL4
/ NIC_MAX_TL3
);
473 nic_reg_write(nic
, NIC_PF_QSET_0_127_SQ_0_7_CFG2
|
474 ((u64
)vnic
<< NIC_QS_ID_SHIFT
) |
475 ((u32
)sq_idx
<< NIC_Q_NUM_SHIFT
), tl4
);
476 nic_reg_write(nic
, NIC_PF_TL4_0_1023_CFG
| (tl4
<< 3),
477 ((u64
)vnic
<< 27) | ((u32
)sq_idx
<< 24) | rr_quantum
);
479 nic_reg_write(nic
, NIC_PF_TL3_0_255_CFG
| (tl3
<< 3), rr_quantum
);
480 chan
= (lmac
* MAX_BGX_CHANS_PER_LMAC
) + (bgx
* NIC_CHANS_PER_INF
);
481 nic_reg_write(nic
, NIC_PF_TL3_0_255_CHAN
| (tl3
<< 3), chan
);
482 /* Enable backpressure on the channel */
483 nic_reg_write(nic
, NIC_PF_CHAN_0_255_TX_CFG
| (chan
<< 3), 1);
486 nic_reg_write(nic
, NIC_PF_TL3A_0_63_CFG
| (tl2
<< 3), tl2
);
487 nic_reg_write(nic
, NIC_PF_TL2_0_63_CFG
| (tl2
<< 3), rr_quantum
);
488 /* No priorities as of now */
489 nic_reg_write(nic
, NIC_PF_TL2_0_63_PRI
| (tl2
<< 3), 0x00);
492 /* Interrupt handler to handle mailbox messages from VFs */
493 static void nic_handle_mbx_intr(struct nicpf
*nic
, int vf
)
495 union nic_mbx mbx
= {};
503 nic
->mbx_lock
[vf
] = true;
505 mbx_addr
= nic_get_mbx_addr(vf
);
506 mbx_data
= (u64
*)&mbx
;
508 for (i
= 0; i
< NIC_PF_VF_MAILBOX_SIZE
; i
++) {
509 *mbx_data
= nic_reg_read(nic
, mbx_addr
);
511 mbx_addr
+= sizeof(u64
);
514 dev_dbg(&nic
->pdev
->dev
, "%s: Mailbox msg %d from VF%d\n",
515 __func__
, mbx
.msg
.msg
, vf
);
516 switch (mbx
.msg
.msg
) {
517 case NIC_MBOX_MSG_READY
:
518 nic_mbx_send_ready(nic
, vf
);
524 case NIC_MBOX_MSG_QS_CFG
:
525 reg_addr
= NIC_PF_QSET_0_127_CFG
|
526 (mbx
.qs
.num
<< NIC_QS_ID_SHIFT
);
527 nic_reg_write(nic
, reg_addr
, mbx
.qs
.cfg
);
529 case NIC_MBOX_MSG_RQ_CFG
:
530 reg_addr
= NIC_PF_QSET_0_127_RQ_0_7_CFG
|
531 (mbx
.rq
.qs_num
<< NIC_QS_ID_SHIFT
) |
532 (mbx
.rq
.rq_num
<< NIC_Q_NUM_SHIFT
);
533 nic_reg_write(nic
, reg_addr
, mbx
.rq
.cfg
);
535 case NIC_MBOX_MSG_RQ_BP_CFG
:
536 reg_addr
= NIC_PF_QSET_0_127_RQ_0_7_BP_CFG
|
537 (mbx
.rq
.qs_num
<< NIC_QS_ID_SHIFT
) |
538 (mbx
.rq
.rq_num
<< NIC_Q_NUM_SHIFT
);
539 nic_reg_write(nic
, reg_addr
, mbx
.rq
.cfg
);
541 case NIC_MBOX_MSG_RQ_SW_SYNC
:
542 ret
= nic_rcv_queue_sw_sync(nic
);
544 case NIC_MBOX_MSG_RQ_DROP_CFG
:
545 reg_addr
= NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG
|
546 (mbx
.rq
.qs_num
<< NIC_QS_ID_SHIFT
) |
547 (mbx
.rq
.rq_num
<< NIC_Q_NUM_SHIFT
);
548 nic_reg_write(nic
, reg_addr
, mbx
.rq
.cfg
);
550 case NIC_MBOX_MSG_SQ_CFG
:
551 reg_addr
= NIC_PF_QSET_0_127_SQ_0_7_CFG
|
552 (mbx
.sq
.qs_num
<< NIC_QS_ID_SHIFT
) |
553 (mbx
.sq
.sq_num
<< NIC_Q_NUM_SHIFT
);
554 nic_reg_write(nic
, reg_addr
, mbx
.sq
.cfg
);
555 nic_tx_channel_cfg(nic
, mbx
.qs
.num
, mbx
.sq
.sq_num
);
557 case NIC_MBOX_MSG_SET_MAC
:
558 lmac
= mbx
.mac
.vf_id
;
559 bgx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[lmac
]);
560 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[lmac
]);
561 bgx_set_lmac_mac(nic
->node
, bgx
, lmac
, mbx
.mac
.mac_addr
);
563 case NIC_MBOX_MSG_SET_MAX_FRS
:
564 ret
= nic_update_hw_frs(nic
, mbx
.frs
.max_frs
,
567 case NIC_MBOX_MSG_CPI_CFG
:
568 nic_config_cpi(nic
, &mbx
.cpi_cfg
);
570 case NIC_MBOX_MSG_RSS_SIZE
:
571 nic_send_rss_size(nic
, vf
);
573 case NIC_MBOX_MSG_RSS_CFG
:
574 case NIC_MBOX_MSG_RSS_CFG_CONT
:
575 nic_config_rss(nic
, &mbx
.rss_cfg
);
577 case NIC_MBOX_MSG_CFG_DONE
:
578 /* Last message of VF config msg sequence */
579 nic
->vf_enabled
[vf
] = true;
581 case NIC_MBOX_MSG_SHUTDOWN
:
582 /* First msg in VF teardown sequence */
583 nic
->vf_enabled
[vf
] = false;
585 case NIC_MBOX_MSG_BGX_STATS
:
586 nic_get_bgx_stats(nic
, &mbx
.bgx_stats
);
589 dev_err(&nic
->pdev
->dev
,
590 "Invalid msg from VF%d, msg 0x%x\n", vf
, mbx
.msg
.msg
);
595 nic_mbx_send_ack(nic
, vf
);
596 else if (mbx
.msg
.msg
!= NIC_MBOX_MSG_READY
)
597 nic_mbx_send_nack(nic
, vf
);
599 nic
->mbx_lock
[vf
] = false;
602 static void nic_mbx_intr_handler (struct nicpf
*nic
, int mbx
)
605 u8 vf
, vf_per_mbx_reg
= 64;
607 intr
= nic_reg_read(nic
, NIC_PF_MAILBOX_INT
+ (mbx
<< 3));
608 dev_dbg(&nic
->pdev
->dev
, "PF interrupt Mbox%d 0x%llx\n", mbx
, intr
);
609 for (vf
= 0; vf
< vf_per_mbx_reg
; vf
++) {
610 if (intr
& (1ULL << vf
)) {
611 dev_dbg(&nic
->pdev
->dev
, "Intr from VF %d\n",
612 vf
+ (mbx
* vf_per_mbx_reg
));
613 if ((vf
+ (mbx
* vf_per_mbx_reg
)) > nic
->num_vf_en
)
615 nic_handle_mbx_intr(nic
, vf
+ (mbx
* vf_per_mbx_reg
));
616 nic_clear_mbx_intr(nic
, vf
, mbx
);
621 static irqreturn_t
nic_mbx0_intr_handler (int irq
, void *nic_irq
)
623 struct nicpf
*nic
= (struct nicpf
*)nic_irq
;
625 nic_mbx_intr_handler(nic
, 0);
630 static irqreturn_t
nic_mbx1_intr_handler (int irq
, void *nic_irq
)
632 struct nicpf
*nic
= (struct nicpf
*)nic_irq
;
634 nic_mbx_intr_handler(nic
, 1);
639 static int nic_enable_msix(struct nicpf
*nic
)
643 nic
->num_vec
= NIC_PF_MSIX_VECTORS
;
645 for (i
= 0; i
< nic
->num_vec
; i
++)
646 nic
->msix_entries
[i
].entry
= i
;
648 ret
= pci_enable_msix(nic
->pdev
, nic
->msix_entries
, nic
->num_vec
);
650 dev_err(&nic
->pdev
->dev
,
651 "Request for #%d msix vectors failed\n",
656 nic
->msix_enabled
= 1;
660 static void nic_disable_msix(struct nicpf
*nic
)
662 if (nic
->msix_enabled
) {
663 pci_disable_msix(nic
->pdev
);
664 nic
->msix_enabled
= 0;
669 static void nic_free_all_interrupts(struct nicpf
*nic
)
673 for (irq
= 0; irq
< nic
->num_vec
; irq
++) {
674 if (nic
->irq_allocated
[irq
])
675 free_irq(nic
->msix_entries
[irq
].vector
, nic
);
676 nic
->irq_allocated
[irq
] = false;
680 static int nic_register_interrupts(struct nicpf
*nic
)
685 ret
= nic_enable_msix(nic
);
689 /* Register mailbox interrupt handlers */
690 ret
= request_irq(nic
->msix_entries
[NIC_PF_INTR_ID_MBOX0
].vector
,
691 nic_mbx0_intr_handler
, 0, "NIC Mbox0", nic
);
695 nic
->irq_allocated
[NIC_PF_INTR_ID_MBOX0
] = true;
697 ret
= request_irq(nic
->msix_entries
[NIC_PF_INTR_ID_MBOX1
].vector
,
698 nic_mbx1_intr_handler
, 0, "NIC Mbox1", nic
);
702 nic
->irq_allocated
[NIC_PF_INTR_ID_MBOX1
] = true;
704 /* Enable mailbox interrupt */
705 nic_enable_mbx_intr(nic
);
709 dev_err(&nic
->pdev
->dev
, "Request irq failed\n");
710 nic_free_all_interrupts(nic
);
714 static void nic_unregister_interrupts(struct nicpf
*nic
)
716 nic_free_all_interrupts(nic
);
717 nic_disable_msix(nic
);
720 static int nic_sriov_init(struct pci_dev
*pdev
, struct nicpf
*nic
)
726 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_SRIOV
);
728 dev_err(&pdev
->dev
, "SRIOV capability is not found in PCIe config space\n");
732 pci_read_config_word(pdev
, (pos
+ PCI_SRIOV_TOTAL_VF
), &total_vf_cnt
);
733 if (total_vf_cnt
< nic
->num_vf_en
)
734 nic
->num_vf_en
= total_vf_cnt
;
739 err
= pci_enable_sriov(pdev
, nic
->num_vf_en
);
741 dev_err(&pdev
->dev
, "SRIOV enable failed, num VF is %d\n",
747 dev_info(&pdev
->dev
, "SRIOV enabled, number of VF available %d\n",
750 nic
->flags
|= NIC_SRIOV_ENABLED
;
754 /* Poll for BGX LMAC link status and update corresponding VF
755 * if there is a change, valid only if internal L2 switch
756 * is not present otherwise VF link is always treated as up
758 static void nic_poll_for_link(struct work_struct
*work
)
760 union nic_mbx mbx
= {};
762 struct bgx_link_status link
;
765 nic
= container_of(work
, struct nicpf
, dwork
.work
);
767 mbx
.link_status
.msg
= NIC_MBOX_MSG_BGX_LINK_CHANGE
;
769 for (vf
= 0; vf
< nic
->num_vf_en
; vf
++) {
770 /* Poll only if VF is UP */
771 if (!nic
->vf_enabled
[vf
])
774 /* Get BGX, LMAC indices for the VF */
775 bgx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
776 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
777 /* Get interface link status */
778 bgx_get_lmac_link_state(nic
->node
, bgx
, lmac
, &link
);
780 /* Inform VF only if link status changed */
781 if (nic
->link
[vf
] == link
.link_up
)
784 if (!nic
->mbx_lock
[vf
]) {
785 nic
->link
[vf
] = link
.link_up
;
786 nic
->duplex
[vf
] = link
.duplex
;
787 nic
->speed
[vf
] = link
.speed
;
789 /* Send a mbox message to VF with current link status */
790 mbx
.link_status
.link_up
= link
.link_up
;
791 mbx
.link_status
.duplex
= link
.duplex
;
792 mbx
.link_status
.speed
= link
.speed
;
793 nic_send_msg_to_vf(nic
, vf
, &mbx
);
796 queue_delayed_work(nic
->check_link
, &nic
->dwork
, HZ
* 2);
799 static int nic_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
801 struct device
*dev
= &pdev
->dev
;
805 BUILD_BUG_ON(sizeof(union nic_mbx
) > 16);
807 nic
= devm_kzalloc(dev
, sizeof(*nic
), GFP_KERNEL
);
811 pci_set_drvdata(pdev
, nic
);
815 err
= pci_enable_device(pdev
);
817 dev_err(dev
, "Failed to enable PCI device\n");
818 pci_set_drvdata(pdev
, NULL
);
822 err
= pci_request_regions(pdev
, DRV_NAME
);
824 dev_err(dev
, "PCI request regions failed 0x%x\n", err
);
825 goto err_disable_device
;
828 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(48));
830 dev_err(dev
, "Unable to get usable DMA configuration\n");
831 goto err_release_regions
;
834 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(48));
836 dev_err(dev
, "Unable to get 48-bit DMA for consistent allocations\n");
837 goto err_release_regions
;
840 /* MAP PF's configuration registers */
841 nic
->reg_base
= pcim_iomap(pdev
, PCI_CFG_REG_BAR_NUM
, 0);
842 if (!nic
->reg_base
) {
843 dev_err(dev
, "Cannot map config register space, aborting\n");
845 goto err_release_regions
;
848 pci_read_config_byte(pdev
, PCI_REVISION_ID
, &nic
->rev_id
);
850 nic
->node
= nic_get_node_id(pdev
);
852 nic_set_lmac_vf_mapping(nic
);
854 /* Initialize hardware */
857 /* Set RSS TBL size for each VF */
858 nic
->rss_ind_tbl_size
= NIC_MAX_RSS_IDR_TBL_SIZE
;
860 /* Register interrupts */
861 err
= nic_register_interrupts(nic
);
863 goto err_release_regions
;
865 /* Configure SRIOV */
866 err
= nic_sriov_init(pdev
, nic
);
868 goto err_unregister_interrupts
;
870 /* Register a physical link status poll fn() */
871 nic
->check_link
= alloc_workqueue("check_link_status",
872 WQ_UNBOUND
| WQ_MEM_RECLAIM
, 1);
873 if (!nic
->check_link
) {
875 goto err_disable_sriov
;
878 INIT_DELAYED_WORK(&nic
->dwork
, nic_poll_for_link
);
879 queue_delayed_work(nic
->check_link
, &nic
->dwork
, 0);
884 if (nic
->flags
& NIC_SRIOV_ENABLED
)
885 pci_disable_sriov(pdev
);
886 err_unregister_interrupts
:
887 nic_unregister_interrupts(nic
);
889 pci_release_regions(pdev
);
891 pci_disable_device(pdev
);
892 pci_set_drvdata(pdev
, NULL
);
896 static void nic_remove(struct pci_dev
*pdev
)
898 struct nicpf
*nic
= pci_get_drvdata(pdev
);
900 if (nic
->flags
& NIC_SRIOV_ENABLED
)
901 pci_disable_sriov(pdev
);
903 if (nic
->check_link
) {
904 /* Destroy work Queue */
905 cancel_delayed_work(&nic
->dwork
);
906 flush_workqueue(nic
->check_link
);
907 destroy_workqueue(nic
->check_link
);
910 nic_unregister_interrupts(nic
);
911 pci_release_regions(pdev
);
912 pci_disable_device(pdev
);
913 pci_set_drvdata(pdev
, NULL
);
916 static struct pci_driver nic_driver
= {
918 .id_table
= nic_id_table
,
920 .remove
= nic_remove
,
923 static int __init
nic_init_module(void)
925 pr_info("%s, ver %s\n", DRV_NAME
, DRV_VERSION
);
927 return pci_register_driver(&nic_driver
);
930 static void __exit
nic_cleanup_module(void)
932 pci_unregister_driver(&nic_driver
);
935 module_init(nic_init_module
);
936 module_exit(nic_cleanup_module
);