2 * Copyright (C) 2015 Cavium, Inc.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/etherdevice.h>
18 #include "thunder_bgx.h"
20 #define DRV_NAME "thunder-nic"
21 #define DRV_VERSION "1.0"
27 u8 num_vf_en
; /* No of VF enabled */
28 bool vf_enabled
[MAX_NUM_VFS_SUPPORTED
];
29 void __iomem
*reg_base
; /* Register start address */
30 u8 num_sqs_en
; /* Secondary qsets enabled */
31 u64 nicvf
[MAX_NUM_VFS_SUPPORTED
];
32 u8 vf_sqs
[MAX_NUM_VFS_SUPPORTED
][MAX_SQS_PER_VF
];
33 u8 pqs_vf
[MAX_NUM_VFS_SUPPORTED
];
34 bool sqs_used
[MAX_NUM_VFS_SUPPORTED
];
35 struct pkind_cfg pkind
;
36 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF))
37 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF)
38 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF)
39 u8 vf_lmac_map
[MAX_LMAC
];
40 struct delayed_work dwork
;
41 struct workqueue_struct
*check_link
;
45 u16 cpi_base
[MAX_NUM_VFS_SUPPORTED
];
46 u16 rssi_base
[MAX_NUM_VFS_SUPPORTED
];
48 bool mbx_lock
[MAX_NUM_VFS_SUPPORTED
];
53 struct msix_entry msix_entries
[NIC_PF_MSIX_VECTORS
];
54 bool irq_allocated
[NIC_PF_MSIX_VECTORS
];
57 /* Supported devices */
58 static const struct pci_device_id nic_id_table
[] = {
59 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM
, PCI_DEVICE_ID_THUNDER_NIC_PF
) },
60 { 0, } /* end of table */
63 MODULE_AUTHOR("Sunil Goutham");
64 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
65 MODULE_LICENSE("GPL v2");
66 MODULE_VERSION(DRV_VERSION
);
67 MODULE_DEVICE_TABLE(pci
, nic_id_table
);
69 /* The Cavium ThunderX network controller can *only* be found in SoCs
70 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
71 * registers on this platform are implicitly strongly ordered with respect
72 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
73 * with no memory barriers in this driver. The readq()/writeq() functions add
74 * explicit ordering operation which in this case are redundant, and only
78 /* Register read/write APIs */
79 static void nic_reg_write(struct nicpf
*nic
, u64 offset
, u64 val
)
81 writeq_relaxed(val
, nic
->reg_base
+ offset
);
84 static u64
nic_reg_read(struct nicpf
*nic
, u64 offset
)
86 return readq_relaxed(nic
->reg_base
+ offset
);
89 /* PF -> VF mailbox communication APIs */
90 static void nic_enable_mbx_intr(struct nicpf
*nic
)
92 /* Enable mailbox interrupt for all 128 VFs */
93 nic_reg_write(nic
, NIC_PF_MAILBOX_ENA_W1S
, ~0ull);
94 nic_reg_write(nic
, NIC_PF_MAILBOX_ENA_W1S
+ sizeof(u64
), ~0ull);
97 static void nic_clear_mbx_intr(struct nicpf
*nic
, int vf
, int mbx_reg
)
99 nic_reg_write(nic
, NIC_PF_MAILBOX_INT
+ (mbx_reg
<< 3), BIT_ULL(vf
));
102 static u64
nic_get_mbx_addr(int vf
)
104 return NIC_PF_VF_0_127_MAILBOX_0_1
+ (vf
<< NIC_VF_NUM_SHIFT
);
107 /* Send a mailbox message to VF
108 * @vf: vf to which this message to be sent
109 * @mbx: Message to be sent
111 static void nic_send_msg_to_vf(struct nicpf
*nic
, int vf
, union nic_mbx
*mbx
)
113 void __iomem
*mbx_addr
= nic
->reg_base
+ nic_get_mbx_addr(vf
);
114 u64
*msg
= (u64
*)mbx
;
116 /* In first revision HW, mbox interrupt is triggerred
117 * when PF writes to MBOX(1), in next revisions when
118 * PF writes to MBOX(0)
120 if (pass1_silicon(nic
->pdev
)) {
121 /* see the comment for nic_reg_write()/nic_reg_read()
124 writeq_relaxed(msg
[0], mbx_addr
);
125 writeq_relaxed(msg
[1], mbx_addr
+ 8);
127 writeq_relaxed(msg
[1], mbx_addr
+ 8);
128 writeq_relaxed(msg
[0], mbx_addr
);
132 /* Responds to VF's READY message with VF's
133 * ID, node, MAC address e.t.c
134 * @vf: VF which sent READY message
136 static void nic_mbx_send_ready(struct nicpf
*nic
, int vf
)
138 union nic_mbx mbx
= {};
142 mbx
.nic_cfg
.msg
= NIC_MBOX_MSG_READY
;
143 mbx
.nic_cfg
.vf_id
= vf
;
145 mbx
.nic_cfg
.tns_mode
= NIC_TNS_BYPASS_MODE
;
148 bgx_idx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
149 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
151 mac
= bgx_get_lmac_mac(nic
->node
, bgx_idx
, lmac
);
153 ether_addr_copy((u8
*)&mbx
.nic_cfg
.mac_addr
, mac
);
155 mbx
.nic_cfg
.sqs_mode
= (vf
>= nic
->num_vf_en
) ? true : false;
156 mbx
.nic_cfg
.node_id
= nic
->node
;
158 mbx
.nic_cfg
.loopback_supported
= vf
< MAX_LMAC
;
160 nic_send_msg_to_vf(nic
, vf
, &mbx
);
163 /* ACKs VF's mailbox message
164 * @vf: VF to which ACK to be sent
166 static void nic_mbx_send_ack(struct nicpf
*nic
, int vf
)
168 union nic_mbx mbx
= {};
170 mbx
.msg
.msg
= NIC_MBOX_MSG_ACK
;
171 nic_send_msg_to_vf(nic
, vf
, &mbx
);
174 /* NACKs VF's mailbox message that PF is not able to
175 * complete the action
176 * @vf: VF to which ACK to be sent
178 static void nic_mbx_send_nack(struct nicpf
*nic
, int vf
)
180 union nic_mbx mbx
= {};
182 mbx
.msg
.msg
= NIC_MBOX_MSG_NACK
;
183 nic_send_msg_to_vf(nic
, vf
, &mbx
);
186 /* Flush all in flight receive packets to memory and
187 * bring down an active RQ
189 static int nic_rcv_queue_sw_sync(struct nicpf
*nic
)
193 nic_reg_write(nic
, NIC_PF_SW_SYNC_RX
, 0x01);
194 /* Wait till sync cycle is finished */
196 if (nic_reg_read(nic
, NIC_PF_SW_SYNC_RX_DONE
) & 0x1)
200 nic_reg_write(nic
, NIC_PF_SW_SYNC_RX
, 0x00);
202 dev_err(&nic
->pdev
->dev
, "Receive queue software sync failed");
208 /* Get BGX Rx/Tx stats and respond to VF's request */
209 static void nic_get_bgx_stats(struct nicpf
*nic
, struct bgx_stats_msg
*bgx
)
212 union nic_mbx mbx
= {};
214 bgx_idx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[bgx
->vf_id
]);
215 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[bgx
->vf_id
]);
217 mbx
.bgx_stats
.msg
= NIC_MBOX_MSG_BGX_STATS
;
218 mbx
.bgx_stats
.vf_id
= bgx
->vf_id
;
219 mbx
.bgx_stats
.rx
= bgx
->rx
;
220 mbx
.bgx_stats
.idx
= bgx
->idx
;
222 mbx
.bgx_stats
.stats
= bgx_get_rx_stats(nic
->node
, bgx_idx
,
225 mbx
.bgx_stats
.stats
= bgx_get_tx_stats(nic
->node
, bgx_idx
,
227 nic_send_msg_to_vf(nic
, bgx
->vf_id
, &mbx
);
230 /* Update hardware min/max frame size */
231 static int nic_update_hw_frs(struct nicpf
*nic
, int new_frs
, int vf
)
233 if ((new_frs
> NIC_HW_MAX_FRS
) || (new_frs
< NIC_HW_MIN_FRS
)) {
234 dev_err(&nic
->pdev
->dev
,
235 "Invalid MTU setting from VF%d rejected, should be between %d and %d\n",
236 vf
, NIC_HW_MIN_FRS
, NIC_HW_MAX_FRS
);
240 if (new_frs
<= nic
->pkind
.maxlen
)
243 nic
->pkind
.maxlen
= new_frs
;
244 nic_reg_write(nic
, NIC_PF_PKIND_0_15_CFG
, *(u64
*)&nic
->pkind
);
248 /* Set minimum transmit packet size */
249 static void nic_set_tx_pkt_pad(struct nicpf
*nic
, int size
)
254 /* Max value that can be set is 60 */
258 for (lmac
= 0; lmac
< (MAX_BGX_PER_CN88XX
* MAX_LMAC_PER_BGX
); lmac
++) {
259 lmac_cfg
= nic_reg_read(nic
, NIC_PF_LMAC_0_7_CFG
| (lmac
<< 3));
260 lmac_cfg
&= ~(0xF << 2);
261 lmac_cfg
|= ((size
/ 4) << 2);
262 nic_reg_write(nic
, NIC_PF_LMAC_0_7_CFG
| (lmac
<< 3), lmac_cfg
);
266 /* Function to check number of LMACs present and set VF::LMAC mapping.
267 * Mapping will be used while initializing channels.
269 static void nic_set_lmac_vf_mapping(struct nicpf
*nic
)
271 unsigned bgx_map
= bgx_get_map(nic
->node
);
272 int bgx
, next_bgx_lmac
= 0;
273 int lmac
, lmac_cnt
= 0;
278 for (bgx
= 0; bgx
< NIC_MAX_BGX
; bgx
++) {
279 if (!(bgx_map
& (1 << bgx
)))
281 lmac_cnt
= bgx_get_lmac_count(nic
->node
, bgx
);
282 for (lmac
= 0; lmac
< lmac_cnt
; lmac
++)
283 nic
->vf_lmac_map
[next_bgx_lmac
++] =
284 NIC_SET_VF_LMAC_MAP(bgx
, lmac
);
285 nic
->num_vf_en
+= lmac_cnt
;
287 /* Program LMAC credits */
288 lmac_credit
= (1ull << 1); /* channel credit enable */
289 lmac_credit
|= (0x1ff << 2); /* Max outstanding pkt count */
290 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
291 lmac_credit
|= (((((48 * 1024) / lmac_cnt
) -
292 NIC_HW_MAX_FRS
) / 16) << 12);
293 lmac
= bgx
* MAX_LMAC_PER_BGX
;
294 for (; lmac
< lmac_cnt
+ (bgx
* MAX_LMAC_PER_BGX
); lmac
++)
296 NIC_PF_LMAC_0_7_CREDIT
+ (lmac
* 8),
304 static void nic_init_hw(struct nicpf
*nic
)
309 /* Enable NIC HW block */
310 nic_reg_write(nic
, NIC_PF_CFG
, 0x3);
312 /* Enable backpressure */
313 nic_reg_write(nic
, NIC_PF_BP_CFG
, (1ULL << 6) | 0x03);
315 /* Disable TNS mode on both interfaces */
316 nic_reg_write(nic
, NIC_PF_INTF_0_1_SEND_CFG
,
317 (NIC_TNS_BYPASS_MODE
<< 7) | BGX0_BLOCK
);
318 nic_reg_write(nic
, NIC_PF_INTF_0_1_SEND_CFG
| (1 << 8),
319 (NIC_TNS_BYPASS_MODE
<< 7) | BGX1_BLOCK
);
320 nic_reg_write(nic
, NIC_PF_INTF_0_1_BP_CFG
,
321 (1ULL << 63) | BGX0_BLOCK
);
322 nic_reg_write(nic
, NIC_PF_INTF_0_1_BP_CFG
+ (1 << 8),
323 (1ULL << 63) | BGX1_BLOCK
);
325 /* PKIND configuration */
326 nic
->pkind
.minlen
= 0;
327 nic
->pkind
.maxlen
= NIC_HW_MAX_FRS
+ ETH_HLEN
;
328 nic
->pkind
.lenerr_en
= 1;
329 nic
->pkind
.rx_hdr
= 0;
330 nic
->pkind
.hdr_sl
= 0;
332 for (i
= 0; i
< NIC_MAX_PKIND
; i
++)
333 nic_reg_write(nic
, NIC_PF_PKIND_0_15_CFG
| (i
<< 3),
334 *(u64
*)&nic
->pkind
);
336 nic_set_tx_pkt_pad(nic
, NIC_HW_MIN_FRS
);
339 nic_reg_write(nic
, NIC_PF_INTR_TIMER_CFG
, NICPF_CLK_PER_INT_TICK
);
341 /* Enable VLAN ethertype matching and stripping */
342 nic_reg_write(nic
, NIC_PF_RX_ETYPE_0_7
,
343 (2 << 19) | (ETYPE_ALG_VLAN_STRIP
<< 16) | ETH_P_8021Q
);
345 /* Check if HW expected value is higher (could be in future chips) */
346 cqm_cfg
= nic_reg_read(nic
, NIC_PF_CQM_CFG
);
347 if (cqm_cfg
< NICPF_CQM_MIN_DROP_LEVEL
)
348 nic_reg_write(nic
, NIC_PF_CQM_CFG
, NICPF_CQM_MIN_DROP_LEVEL
);
351 /* Channel parse index configuration */
352 static void nic_config_cpi(struct nicpf
*nic
, struct cpi_cfg_msg
*cfg
)
354 u32 vnic
, bgx
, lmac
, chan
;
355 u32 padd
, cpi_count
= 0;
356 u64 cpi_base
, cpi
, rssi_base
, rssi
;
360 bgx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vnic
]);
361 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vnic
]);
363 chan
= (lmac
* MAX_BGX_CHANS_PER_LMAC
) + (bgx
* NIC_CHANS_PER_INF
);
364 cpi_base
= (lmac
* NIC_MAX_CPI_PER_LMAC
) + (bgx
* NIC_CPI_PER_BGX
);
365 rssi_base
= (lmac
* nic
->rss_ind_tbl_size
) + (bgx
* NIC_RSSI_PER_BGX
);
367 /* Rx channel configuration */
368 nic_reg_write(nic
, NIC_PF_CHAN_0_255_RX_BP_CFG
| (chan
<< 3),
369 (1ull << 63) | (vnic
<< 0));
370 nic_reg_write(nic
, NIC_PF_CHAN_0_255_RX_CFG
| (chan
<< 3),
371 ((u64
)cfg
->cpi_alg
<< 62) | (cpi_base
<< 48));
373 if (cfg
->cpi_alg
== CPI_ALG_NONE
)
375 else if (cfg
->cpi_alg
== CPI_ALG_VLAN
) /* 3 bits of PCP */
377 else if (cfg
->cpi_alg
== CPI_ALG_VLAN16
) /* 3 bits PCP + DEI */
379 else if (cfg
->cpi_alg
== CPI_ALG_DIFF
) /* 6bits DSCP */
380 cpi_count
= NIC_MAX_CPI_PER_LMAC
;
382 /* RSS Qset, Qidx mapping */
385 for (; rssi
< (rssi_base
+ cfg
->rq_cnt
); rssi
++) {
386 nic_reg_write(nic
, NIC_PF_RSSI_0_4097_RQ
| (rssi
<< 3),
387 (qset
<< 3) | rq_idx
);
393 for (; cpi
< (cpi_base
+ cpi_count
); cpi
++) {
394 /* Determine port to channel adder */
395 if (cfg
->cpi_alg
!= CPI_ALG_DIFF
)
396 padd
= cpi
% cpi_count
;
398 padd
= cpi
% 8; /* 3 bits CS out of 6bits DSCP */
400 /* Leave RSS_SIZE as '0' to disable RSS */
401 if (pass1_silicon(nic
->pdev
)) {
402 nic_reg_write(nic
, NIC_PF_CPI_0_2047_CFG
| (cpi
<< 3),
403 (vnic
<< 24) | (padd
<< 16) |
406 /* Set MPI_ALG to '0' to disable MCAM parsing */
407 nic_reg_write(nic
, NIC_PF_CPI_0_2047_CFG
| (cpi
<< 3),
409 /* MPI index is same as CPI if MPI_ALG is not enabled */
410 nic_reg_write(nic
, NIC_PF_MPI_0_2047_CFG
| (cpi
<< 3),
411 (vnic
<< 24) | (rssi_base
+ rssi
));
414 if ((rssi
+ 1) >= cfg
->rq_cnt
)
417 if (cfg
->cpi_alg
== CPI_ALG_VLAN
)
419 else if (cfg
->cpi_alg
== CPI_ALG_VLAN16
)
420 rssi
= ((cpi
- cpi_base
) & 0xe) >> 1;
421 else if (cfg
->cpi_alg
== CPI_ALG_DIFF
)
422 rssi
= ((cpi
- cpi_base
) & 0x38) >> 3;
424 nic
->cpi_base
[cfg
->vf_id
] = cpi_base
;
425 nic
->rssi_base
[cfg
->vf_id
] = rssi_base
;
428 /* Responsds to VF with its RSS indirection table size */
429 static void nic_send_rss_size(struct nicpf
*nic
, int vf
)
431 union nic_mbx mbx
= {};
436 mbx
.rss_size
.msg
= NIC_MBOX_MSG_RSS_SIZE
;
437 mbx
.rss_size
.ind_tbl_size
= nic
->rss_ind_tbl_size
;
438 nic_send_msg_to_vf(nic
, vf
, &mbx
);
441 /* Receive side scaling configuration
444 * - indir table i.e hash::RQ mapping
445 * - no of hash bits to consider
447 static void nic_config_rss(struct nicpf
*nic
, struct rss_cfg_msg
*cfg
)
450 u64 cpi_cfg
, cpi_base
, rssi_base
, rssi
;
453 rssi_base
= nic
->rssi_base
[cfg
->vf_id
] + cfg
->tbl_offset
;
458 for (; rssi
< (rssi_base
+ cfg
->tbl_len
); rssi
++) {
459 u8 svf
= cfg
->ind_tbl
[idx
] >> 3;
462 qset
= nic
->vf_sqs
[cfg
->vf_id
][svf
- 1];
465 nic_reg_write(nic
, NIC_PF_RSSI_0_4097_RQ
| (rssi
<< 3),
466 (qset
<< 3) | (cfg
->ind_tbl
[idx
] & 0x7));
470 cpi_base
= nic
->cpi_base
[cfg
->vf_id
];
471 if (pass1_silicon(nic
->pdev
))
472 idx_addr
= NIC_PF_CPI_0_2047_CFG
;
474 idx_addr
= NIC_PF_MPI_0_2047_CFG
;
475 cpi_cfg
= nic_reg_read(nic
, idx_addr
| (cpi_base
<< 3));
476 cpi_cfg
&= ~(0xFULL
<< 20);
477 cpi_cfg
|= (cfg
->hash_bits
<< 20);
478 nic_reg_write(nic
, idx_addr
| (cpi_base
<< 3), cpi_cfg
);
481 /* 4 level transmit side scheduler configutation
482 * for TNS bypass mode
484 * Sample configuration for SQ0
485 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
486 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
487 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
488 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
489 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
490 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
491 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
492 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
494 static void nic_tx_channel_cfg(struct nicpf
*nic
, u8 vnic
,
495 struct sq_cfg_msg
*sq
)
500 u8 sq_idx
= sq
->sq_num
;
504 pqs_vnic
= nic
->pqs_vf
[vnic
];
508 bgx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[pqs_vnic
]);
509 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[pqs_vnic
]);
511 /* 24 bytes for FCS, IPG and preamble */
512 rr_quantum
= ((NIC_HW_MAX_FRS
+ 24) / 4);
514 tl4
= (lmac
* NIC_TL4_PER_LMAC
) + (bgx
* NIC_TL4_PER_BGX
);
519 tl3
= tl4
/ (NIC_MAX_TL4
/ NIC_MAX_TL3
);
520 nic_reg_write(nic
, NIC_PF_QSET_0_127_SQ_0_7_CFG2
|
521 ((u64
)vnic
<< NIC_QS_ID_SHIFT
) |
522 ((u32
)sq_idx
<< NIC_Q_NUM_SHIFT
), tl4
);
523 nic_reg_write(nic
, NIC_PF_TL4_0_1023_CFG
| (tl4
<< 3),
524 ((u64
)vnic
<< 27) | ((u32
)sq_idx
<< 24) | rr_quantum
);
526 nic_reg_write(nic
, NIC_PF_TL3_0_255_CFG
| (tl3
<< 3), rr_quantum
);
527 chan
= (lmac
* MAX_BGX_CHANS_PER_LMAC
) + (bgx
* NIC_CHANS_PER_INF
);
528 nic_reg_write(nic
, NIC_PF_TL3_0_255_CHAN
| (tl3
<< 3), chan
);
529 /* Enable backpressure on the channel */
530 nic_reg_write(nic
, NIC_PF_CHAN_0_255_TX_CFG
| (chan
<< 3), 1);
533 nic_reg_write(nic
, NIC_PF_TL3A_0_63_CFG
| (tl2
<< 3), tl2
);
534 nic_reg_write(nic
, NIC_PF_TL2_0_63_CFG
| (tl2
<< 3), rr_quantum
);
535 /* No priorities as of now */
536 nic_reg_write(nic
, NIC_PF_TL2_0_63_PRI
| (tl2
<< 3), 0x00);
539 /* Send primary nicvf pointer to secondary QS's VF */
540 static void nic_send_pnicvf(struct nicpf
*nic
, int sqs
)
542 union nic_mbx mbx
= {};
544 mbx
.nicvf
.msg
= NIC_MBOX_MSG_PNICVF_PTR
;
545 mbx
.nicvf
.nicvf
= nic
->nicvf
[nic
->pqs_vf
[sqs
]];
546 nic_send_msg_to_vf(nic
, sqs
, &mbx
);
549 /* Send SQS's nicvf pointer to primary QS's VF */
550 static void nic_send_snicvf(struct nicpf
*nic
, struct nicvf_ptr
*nicvf
)
552 union nic_mbx mbx
= {};
553 int sqs_id
= nic
->vf_sqs
[nicvf
->vf_id
][nicvf
->sqs_id
];
555 mbx
.nicvf
.msg
= NIC_MBOX_MSG_SNICVF_PTR
;
556 mbx
.nicvf
.sqs_id
= nicvf
->sqs_id
;
557 mbx
.nicvf
.nicvf
= nic
->nicvf
[sqs_id
];
558 nic_send_msg_to_vf(nic
, nicvf
->vf_id
, &mbx
);
561 /* Find next available Qset that can be assigned as a
562 * secondary Qset to a VF.
564 static int nic_nxt_avail_sqs(struct nicpf
*nic
)
568 for (sqs
= 0; sqs
< nic
->num_sqs_en
; sqs
++) {
569 if (!nic
->sqs_used
[sqs
])
570 nic
->sqs_used
[sqs
] = true;
573 return sqs
+ nic
->num_vf_en
;
578 /* Allocate additional Qsets for requested VF */
579 static void nic_alloc_sqs(struct nicpf
*nic
, struct sqs_alloc
*sqs
)
581 union nic_mbx mbx
= {};
582 int idx
, alloc_qs
= 0;
585 if (!nic
->num_sqs_en
)
588 for (idx
= 0; idx
< sqs
->qs_count
; idx
++) {
589 sqs_id
= nic_nxt_avail_sqs(nic
);
592 nic
->vf_sqs
[sqs
->vf_id
][idx
] = sqs_id
;
593 nic
->pqs_vf
[sqs_id
] = sqs
->vf_id
;
598 mbx
.sqs_alloc
.msg
= NIC_MBOX_MSG_ALLOC_SQS
;
599 mbx
.sqs_alloc
.vf_id
= sqs
->vf_id
;
600 mbx
.sqs_alloc
.qs_count
= alloc_qs
;
601 nic_send_msg_to_vf(nic
, sqs
->vf_id
, &mbx
);
604 static int nic_config_loopback(struct nicpf
*nic
, struct set_loopback
*lbk
)
606 int bgx_idx
, lmac_idx
;
608 if (lbk
->vf_id
> MAX_LMAC
)
611 bgx_idx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[lbk
->vf_id
]);
612 lmac_idx
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[lbk
->vf_id
]);
614 bgx_lmac_internal_loopback(nic
->node
, bgx_idx
, lmac_idx
, lbk
->enable
);
619 static void nic_enable_vf(struct nicpf
*nic
, int vf
, bool enable
)
623 nic
->vf_enabled
[vf
] = enable
;
625 if (vf
>= nic
->num_vf_en
)
628 bgx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
629 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
631 bgx_lmac_rx_tx_enable(nic
->node
, bgx
, lmac
, enable
);
634 /* Interrupt handler to handle mailbox messages from VFs */
635 static void nic_handle_mbx_intr(struct nicpf
*nic
, int vf
)
637 union nic_mbx mbx
= {};
646 nic
->mbx_lock
[vf
] = true;
648 mbx_addr
= nic_get_mbx_addr(vf
);
649 mbx_data
= (u64
*)&mbx
;
651 for (i
= 0; i
< NIC_PF_VF_MAILBOX_SIZE
; i
++) {
652 *mbx_data
= nic_reg_read(nic
, mbx_addr
);
654 mbx_addr
+= sizeof(u64
);
657 dev_dbg(&nic
->pdev
->dev
, "%s: Mailbox msg %d from VF%d\n",
658 __func__
, mbx
.msg
.msg
, vf
);
659 switch (mbx
.msg
.msg
) {
660 case NIC_MBOX_MSG_READY
:
661 nic_mbx_send_ready(nic
, vf
);
669 case NIC_MBOX_MSG_QS_CFG
:
670 reg_addr
= NIC_PF_QSET_0_127_CFG
|
671 (mbx
.qs
.num
<< NIC_QS_ID_SHIFT
);
673 /* Check if its a secondary Qset */
674 if (vf
>= nic
->num_vf_en
) {
675 cfg
= cfg
& (~0x7FULL
);
676 /* Assign this Qset to primary Qset's VF */
677 cfg
|= nic
->pqs_vf
[vf
];
679 nic_reg_write(nic
, reg_addr
, cfg
);
681 case NIC_MBOX_MSG_RQ_CFG
:
682 reg_addr
= NIC_PF_QSET_0_127_RQ_0_7_CFG
|
683 (mbx
.rq
.qs_num
<< NIC_QS_ID_SHIFT
) |
684 (mbx
.rq
.rq_num
<< NIC_Q_NUM_SHIFT
);
685 nic_reg_write(nic
, reg_addr
, mbx
.rq
.cfg
);
687 case NIC_MBOX_MSG_RQ_BP_CFG
:
688 reg_addr
= NIC_PF_QSET_0_127_RQ_0_7_BP_CFG
|
689 (mbx
.rq
.qs_num
<< NIC_QS_ID_SHIFT
) |
690 (mbx
.rq
.rq_num
<< NIC_Q_NUM_SHIFT
);
691 nic_reg_write(nic
, reg_addr
, mbx
.rq
.cfg
);
693 case NIC_MBOX_MSG_RQ_SW_SYNC
:
694 ret
= nic_rcv_queue_sw_sync(nic
);
696 case NIC_MBOX_MSG_RQ_DROP_CFG
:
697 reg_addr
= NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG
|
698 (mbx
.rq
.qs_num
<< NIC_QS_ID_SHIFT
) |
699 (mbx
.rq
.rq_num
<< NIC_Q_NUM_SHIFT
);
700 nic_reg_write(nic
, reg_addr
, mbx
.rq
.cfg
);
702 case NIC_MBOX_MSG_SQ_CFG
:
703 reg_addr
= NIC_PF_QSET_0_127_SQ_0_7_CFG
|
704 (mbx
.sq
.qs_num
<< NIC_QS_ID_SHIFT
) |
705 (mbx
.sq
.sq_num
<< NIC_Q_NUM_SHIFT
);
706 nic_reg_write(nic
, reg_addr
, mbx
.sq
.cfg
);
707 nic_tx_channel_cfg(nic
, mbx
.qs
.num
, &mbx
.sq
);
709 case NIC_MBOX_MSG_SET_MAC
:
710 if (vf
>= nic
->num_vf_en
)
712 lmac
= mbx
.mac
.vf_id
;
713 bgx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[lmac
]);
714 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[lmac
]);
715 bgx_set_lmac_mac(nic
->node
, bgx
, lmac
, mbx
.mac
.mac_addr
);
717 case NIC_MBOX_MSG_SET_MAX_FRS
:
718 ret
= nic_update_hw_frs(nic
, mbx
.frs
.max_frs
,
721 case NIC_MBOX_MSG_CPI_CFG
:
722 nic_config_cpi(nic
, &mbx
.cpi_cfg
);
724 case NIC_MBOX_MSG_RSS_SIZE
:
725 nic_send_rss_size(nic
, vf
);
727 case NIC_MBOX_MSG_RSS_CFG
:
728 case NIC_MBOX_MSG_RSS_CFG_CONT
:
729 nic_config_rss(nic
, &mbx
.rss_cfg
);
731 case NIC_MBOX_MSG_CFG_DONE
:
732 /* Last message of VF config msg sequence */
733 nic_enable_vf(nic
, vf
, true);
735 case NIC_MBOX_MSG_SHUTDOWN
:
736 /* First msg in VF teardown sequence */
737 if (vf
>= nic
->num_vf_en
)
738 nic
->sqs_used
[vf
- nic
->num_vf_en
] = false;
740 nic_enable_vf(nic
, vf
, false);
742 case NIC_MBOX_MSG_ALLOC_SQS
:
743 nic_alloc_sqs(nic
, &mbx
.sqs_alloc
);
745 case NIC_MBOX_MSG_NICVF_PTR
:
746 nic
->nicvf
[vf
] = mbx
.nicvf
.nicvf
;
748 case NIC_MBOX_MSG_PNICVF_PTR
:
749 nic_send_pnicvf(nic
, vf
);
751 case NIC_MBOX_MSG_SNICVF_PTR
:
752 nic_send_snicvf(nic
, &mbx
.nicvf
);
754 case NIC_MBOX_MSG_BGX_STATS
:
755 nic_get_bgx_stats(nic
, &mbx
.bgx_stats
);
757 case NIC_MBOX_MSG_LOOPBACK
:
758 ret
= nic_config_loopback(nic
, &mbx
.lbk
);
761 dev_err(&nic
->pdev
->dev
,
762 "Invalid msg from VF%d, msg 0x%x\n", vf
, mbx
.msg
.msg
);
767 nic_mbx_send_ack(nic
, vf
);
768 else if (mbx
.msg
.msg
!= NIC_MBOX_MSG_READY
)
769 nic_mbx_send_nack(nic
, vf
);
771 nic
->mbx_lock
[vf
] = false;
774 static void nic_mbx_intr_handler (struct nicpf
*nic
, int mbx
)
777 u8 vf
, vf_per_mbx_reg
= 64;
779 intr
= nic_reg_read(nic
, NIC_PF_MAILBOX_INT
+ (mbx
<< 3));
780 dev_dbg(&nic
->pdev
->dev
, "PF interrupt Mbox%d 0x%llx\n", mbx
, intr
);
781 for (vf
= 0; vf
< vf_per_mbx_reg
; vf
++) {
782 if (intr
& (1ULL << vf
)) {
783 dev_dbg(&nic
->pdev
->dev
, "Intr from VF %d\n",
784 vf
+ (mbx
* vf_per_mbx_reg
));
786 nic_handle_mbx_intr(nic
, vf
+ (mbx
* vf_per_mbx_reg
));
787 nic_clear_mbx_intr(nic
, vf
, mbx
);
792 static irqreturn_t
nic_mbx0_intr_handler (int irq
, void *nic_irq
)
794 struct nicpf
*nic
= (struct nicpf
*)nic_irq
;
796 nic_mbx_intr_handler(nic
, 0);
801 static irqreturn_t
nic_mbx1_intr_handler (int irq
, void *nic_irq
)
803 struct nicpf
*nic
= (struct nicpf
*)nic_irq
;
805 nic_mbx_intr_handler(nic
, 1);
810 static int nic_enable_msix(struct nicpf
*nic
)
814 nic
->num_vec
= NIC_PF_MSIX_VECTORS
;
816 for (i
= 0; i
< nic
->num_vec
; i
++)
817 nic
->msix_entries
[i
].entry
= i
;
819 ret
= pci_enable_msix(nic
->pdev
, nic
->msix_entries
, nic
->num_vec
);
821 dev_err(&nic
->pdev
->dev
,
822 "Request for #%d msix vectors failed\n",
827 nic
->msix_enabled
= 1;
831 static void nic_disable_msix(struct nicpf
*nic
)
833 if (nic
->msix_enabled
) {
834 pci_disable_msix(nic
->pdev
);
835 nic
->msix_enabled
= 0;
840 static void nic_free_all_interrupts(struct nicpf
*nic
)
844 for (irq
= 0; irq
< nic
->num_vec
; irq
++) {
845 if (nic
->irq_allocated
[irq
])
846 free_irq(nic
->msix_entries
[irq
].vector
, nic
);
847 nic
->irq_allocated
[irq
] = false;
851 static int nic_register_interrupts(struct nicpf
*nic
)
856 ret
= nic_enable_msix(nic
);
860 /* Register mailbox interrupt handlers */
861 ret
= request_irq(nic
->msix_entries
[NIC_PF_INTR_ID_MBOX0
].vector
,
862 nic_mbx0_intr_handler
, 0, "NIC Mbox0", nic
);
866 nic
->irq_allocated
[NIC_PF_INTR_ID_MBOX0
] = true;
868 ret
= request_irq(nic
->msix_entries
[NIC_PF_INTR_ID_MBOX1
].vector
,
869 nic_mbx1_intr_handler
, 0, "NIC Mbox1", nic
);
873 nic
->irq_allocated
[NIC_PF_INTR_ID_MBOX1
] = true;
875 /* Enable mailbox interrupt */
876 nic_enable_mbx_intr(nic
);
880 dev_err(&nic
->pdev
->dev
, "Request irq failed\n");
881 nic_free_all_interrupts(nic
);
885 static void nic_unregister_interrupts(struct nicpf
*nic
)
887 nic_free_all_interrupts(nic
);
888 nic_disable_msix(nic
);
891 static int nic_num_sqs_en(struct nicpf
*nic
, int vf_en
)
893 int pos
, sqs_per_vf
= MAX_SQS_PER_VF_SINGLE_NODE
;
896 /* Check if its a multi-node environment */
898 sqs_per_vf
= MAX_SQS_PER_VF
;
900 pos
= pci_find_ext_capability(nic
->pdev
, PCI_EXT_CAP_ID_SRIOV
);
901 pci_read_config_word(nic
->pdev
, (pos
+ PCI_SRIOV_TOTAL_VF
), &total_vf
);
902 return min(total_vf
- vf_en
, vf_en
* sqs_per_vf
);
905 static int nic_sriov_init(struct pci_dev
*pdev
, struct nicpf
*nic
)
912 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_SRIOV
);
914 dev_err(&pdev
->dev
, "SRIOV capability is not found in PCIe config space\n");
918 pci_read_config_word(pdev
, (pos
+ PCI_SRIOV_TOTAL_VF
), &total_vf_cnt
);
919 if (total_vf_cnt
< nic
->num_vf_en
)
920 nic
->num_vf_en
= total_vf_cnt
;
925 vf_en
= nic
->num_vf_en
;
926 nic
->num_sqs_en
= nic_num_sqs_en(nic
, nic
->num_vf_en
);
927 vf_en
+= nic
->num_sqs_en
;
929 err
= pci_enable_sriov(pdev
, vf_en
);
931 dev_err(&pdev
->dev
, "SRIOV enable failed, num VF is %d\n",
937 dev_info(&pdev
->dev
, "SRIOV enabled, number of VF available %d\n",
940 nic
->flags
|= NIC_SRIOV_ENABLED
;
944 /* Poll for BGX LMAC link status and update corresponding VF
945 * if there is a change, valid only if internal L2 switch
946 * is not present otherwise VF link is always treated as up
948 static void nic_poll_for_link(struct work_struct
*work
)
950 union nic_mbx mbx
= {};
952 struct bgx_link_status link
;
955 nic
= container_of(work
, struct nicpf
, dwork
.work
);
957 mbx
.link_status
.msg
= NIC_MBOX_MSG_BGX_LINK_CHANGE
;
959 for (vf
= 0; vf
< nic
->num_vf_en
; vf
++) {
960 /* Poll only if VF is UP */
961 if (!nic
->vf_enabled
[vf
])
964 /* Get BGX, LMAC indices for the VF */
965 bgx
= NIC_GET_BGX_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
966 lmac
= NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic
->vf_lmac_map
[vf
]);
967 /* Get interface link status */
968 bgx_get_lmac_link_state(nic
->node
, bgx
, lmac
, &link
);
970 /* Inform VF only if link status changed */
971 if (nic
->link
[vf
] == link
.link_up
)
974 if (!nic
->mbx_lock
[vf
]) {
975 nic
->link
[vf
] = link
.link_up
;
976 nic
->duplex
[vf
] = link
.duplex
;
977 nic
->speed
[vf
] = link
.speed
;
979 /* Send a mbox message to VF with current link status */
980 mbx
.link_status
.link_up
= link
.link_up
;
981 mbx
.link_status
.duplex
= link
.duplex
;
982 mbx
.link_status
.speed
= link
.speed
;
983 nic_send_msg_to_vf(nic
, vf
, &mbx
);
986 queue_delayed_work(nic
->check_link
, &nic
->dwork
, HZ
* 2);
989 static int nic_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
991 struct device
*dev
= &pdev
->dev
;
995 BUILD_BUG_ON(sizeof(union nic_mbx
) > 16);
997 nic
= devm_kzalloc(dev
, sizeof(*nic
), GFP_KERNEL
);
1001 pci_set_drvdata(pdev
, nic
);
1005 err
= pci_enable_device(pdev
);
1007 dev_err(dev
, "Failed to enable PCI device\n");
1008 pci_set_drvdata(pdev
, NULL
);
1012 err
= pci_request_regions(pdev
, DRV_NAME
);
1014 dev_err(dev
, "PCI request regions failed 0x%x\n", err
);
1015 goto err_disable_device
;
1018 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(48));
1020 dev_err(dev
, "Unable to get usable DMA configuration\n");
1021 goto err_release_regions
;
1024 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(48));
1026 dev_err(dev
, "Unable to get 48-bit DMA for consistent allocations\n");
1027 goto err_release_regions
;
1030 /* MAP PF's configuration registers */
1031 nic
->reg_base
= pcim_iomap(pdev
, PCI_CFG_REG_BAR_NUM
, 0);
1032 if (!nic
->reg_base
) {
1033 dev_err(dev
, "Cannot map config register space, aborting\n");
1035 goto err_release_regions
;
1038 nic
->node
= nic_get_node_id(pdev
);
1040 nic_set_lmac_vf_mapping(nic
);
1042 /* Initialize hardware */
1045 /* Set RSS TBL size for each VF */
1046 nic
->rss_ind_tbl_size
= NIC_MAX_RSS_IDR_TBL_SIZE
;
1048 /* Register interrupts */
1049 err
= nic_register_interrupts(nic
);
1051 goto err_release_regions
;
1053 /* Configure SRIOV */
1054 err
= nic_sriov_init(pdev
, nic
);
1056 goto err_unregister_interrupts
;
1058 /* Register a physical link status poll fn() */
1059 nic
->check_link
= alloc_workqueue("check_link_status",
1060 WQ_UNBOUND
| WQ_MEM_RECLAIM
, 1);
1061 if (!nic
->check_link
) {
1063 goto err_disable_sriov
;
1066 INIT_DELAYED_WORK(&nic
->dwork
, nic_poll_for_link
);
1067 queue_delayed_work(nic
->check_link
, &nic
->dwork
, 0);
1072 if (nic
->flags
& NIC_SRIOV_ENABLED
)
1073 pci_disable_sriov(pdev
);
1074 err_unregister_interrupts
:
1075 nic_unregister_interrupts(nic
);
1076 err_release_regions
:
1077 pci_release_regions(pdev
);
1079 pci_disable_device(pdev
);
1080 pci_set_drvdata(pdev
, NULL
);
1084 static void nic_remove(struct pci_dev
*pdev
)
1086 struct nicpf
*nic
= pci_get_drvdata(pdev
);
1088 if (nic
->flags
& NIC_SRIOV_ENABLED
)
1089 pci_disable_sriov(pdev
);
1091 if (nic
->check_link
) {
1092 /* Destroy work Queue */
1093 cancel_delayed_work_sync(&nic
->dwork
);
1094 destroy_workqueue(nic
->check_link
);
1097 nic_unregister_interrupts(nic
);
1098 pci_release_regions(pdev
);
1099 pci_disable_device(pdev
);
1100 pci_set_drvdata(pdev
, NULL
);
1103 static struct pci_driver nic_driver
= {
1105 .id_table
= nic_id_table
,
1107 .remove
= nic_remove
,
1110 static int __init
nic_init_module(void)
1112 pr_info("%s, ver %s\n", DRV_NAME
, DRV_VERSION
);
1114 return pci_register_driver(&nic_driver
);
1117 static void __exit
nic_cleanup_module(void)
1119 pci_unregister_driver(&nic_driver
);
1122 module_init(nic_init_module
);
1123 module_exit(nic_cleanup_module
);