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net: thunderx: Support for upto 96 queues for a VF
[deliverable/linux.git] / drivers / net / ethernet / cavium / thunder / nic_main.c
1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/etherdevice.h>
13 #include <linux/of.h>
14
15 #include "nic_reg.h"
16 #include "nic.h"
17 #include "q_struct.h"
18 #include "thunder_bgx.h"
19
20 #define DRV_NAME "thunder-nic"
21 #define DRV_VERSION "1.0"
22
23 struct nicpf {
24 struct pci_dev *pdev;
25 u8 rev_id;
26 u8 node;
27 unsigned int flags;
28 u8 num_vf_en; /* No of VF enabled */
29 bool vf_enabled[MAX_NUM_VFS_SUPPORTED];
30 void __iomem *reg_base; /* Register start address */
31 u8 num_sqs_en; /* Secondary qsets enabled */
32 u64 nicvf[MAX_NUM_VFS_SUPPORTED];
33 u8 vf_sqs[MAX_NUM_VFS_SUPPORTED][MAX_SQS_PER_VF];
34 u8 pqs_vf[MAX_NUM_VFS_SUPPORTED];
35 bool sqs_used[MAX_NUM_VFS_SUPPORTED];
36 struct pkind_cfg pkind;
37 #define NIC_SET_VF_LMAC_MAP(bgx, lmac) (((bgx & 0xF) << 4) | (lmac & 0xF))
38 #define NIC_GET_BGX_FROM_VF_LMAC_MAP(map) ((map >> 4) & 0xF)
39 #define NIC_GET_LMAC_FROM_VF_LMAC_MAP(map) (map & 0xF)
40 u8 vf_lmac_map[MAX_LMAC];
41 struct delayed_work dwork;
42 struct workqueue_struct *check_link;
43 u8 link[MAX_LMAC];
44 u8 duplex[MAX_LMAC];
45 u32 speed[MAX_LMAC];
46 u16 cpi_base[MAX_NUM_VFS_SUPPORTED];
47 u16 rss_ind_tbl_size;
48 bool mbx_lock[MAX_NUM_VFS_SUPPORTED];
49
50 /* MSI-X */
51 bool msix_enabled;
52 u8 num_vec;
53 struct msix_entry msix_entries[NIC_PF_MSIX_VECTORS];
54 bool irq_allocated[NIC_PF_MSIX_VECTORS];
55 };
56
57 /* Supported devices */
58 static const struct pci_device_id nic_id_table[] = {
59 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_NIC_PF) },
60 { 0, } /* end of table */
61 };
62
63 MODULE_AUTHOR("Sunil Goutham");
64 MODULE_DESCRIPTION("Cavium Thunder NIC Physical Function Driver");
65 MODULE_LICENSE("GPL v2");
66 MODULE_VERSION(DRV_VERSION);
67 MODULE_DEVICE_TABLE(pci, nic_id_table);
68
69 /* The Cavium ThunderX network controller can *only* be found in SoCs
70 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
71 * registers on this platform are implicitly strongly ordered with respect
72 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
73 * with no memory barriers in this driver. The readq()/writeq() functions add
74 * explicit ordering operation which in this case are redundant, and only
75 * add overhead.
76 */
77
78 /* Register read/write APIs */
79 static void nic_reg_write(struct nicpf *nic, u64 offset, u64 val)
80 {
81 writeq_relaxed(val, nic->reg_base + offset);
82 }
83
84 static u64 nic_reg_read(struct nicpf *nic, u64 offset)
85 {
86 return readq_relaxed(nic->reg_base + offset);
87 }
88
89 /* PF -> VF mailbox communication APIs */
90 static void nic_enable_mbx_intr(struct nicpf *nic)
91 {
92 /* Enable mailbox interrupt for all 128 VFs */
93 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S, ~0ull);
94 nic_reg_write(nic, NIC_PF_MAILBOX_ENA_W1S + sizeof(u64), ~0ull);
95 }
96
97 static void nic_clear_mbx_intr(struct nicpf *nic, int vf, int mbx_reg)
98 {
99 nic_reg_write(nic, NIC_PF_MAILBOX_INT + (mbx_reg << 3), BIT_ULL(vf));
100 }
101
102 static u64 nic_get_mbx_addr(int vf)
103 {
104 return NIC_PF_VF_0_127_MAILBOX_0_1 + (vf << NIC_VF_NUM_SHIFT);
105 }
106
107 /* Send a mailbox message to VF
108 * @vf: vf to which this message to be sent
109 * @mbx: Message to be sent
110 */
111 static void nic_send_msg_to_vf(struct nicpf *nic, int vf, union nic_mbx *mbx)
112 {
113 void __iomem *mbx_addr = nic->reg_base + nic_get_mbx_addr(vf);
114 u64 *msg = (u64 *)mbx;
115
116 /* In first revision HW, mbox interrupt is triggerred
117 * when PF writes to MBOX(1), in next revisions when
118 * PF writes to MBOX(0)
119 */
120 if (nic->rev_id == 0) {
121 /* see the comment for nic_reg_write()/nic_reg_read()
122 * functions above
123 */
124 writeq_relaxed(msg[0], mbx_addr);
125 writeq_relaxed(msg[1], mbx_addr + 8);
126 } else {
127 writeq_relaxed(msg[1], mbx_addr + 8);
128 writeq_relaxed(msg[0], mbx_addr);
129 }
130 }
131
132 /* Responds to VF's READY message with VF's
133 * ID, node, MAC address e.t.c
134 * @vf: VF which sent READY message
135 */
136 static void nic_mbx_send_ready(struct nicpf *nic, int vf)
137 {
138 union nic_mbx mbx = {};
139 int bgx_idx, lmac;
140 const char *mac;
141
142 mbx.nic_cfg.msg = NIC_MBOX_MSG_READY;
143 mbx.nic_cfg.vf_id = vf;
144
145 mbx.nic_cfg.tns_mode = NIC_TNS_BYPASS_MODE;
146
147 if (vf < MAX_LMAC) {
148 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
149 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
150
151 mac = bgx_get_lmac_mac(nic->node, bgx_idx, lmac);
152 if (mac)
153 ether_addr_copy((u8 *)&mbx.nic_cfg.mac_addr, mac);
154 }
155 mbx.nic_cfg.sqs_mode = (vf >= nic->num_vf_en) ? true : false;
156 mbx.nic_cfg.node_id = nic->node;
157 nic_send_msg_to_vf(nic, vf, &mbx);
158 }
159
160 /* ACKs VF's mailbox message
161 * @vf: VF to which ACK to be sent
162 */
163 static void nic_mbx_send_ack(struct nicpf *nic, int vf)
164 {
165 union nic_mbx mbx = {};
166
167 mbx.msg.msg = NIC_MBOX_MSG_ACK;
168 nic_send_msg_to_vf(nic, vf, &mbx);
169 }
170
171 /* NACKs VF's mailbox message that PF is not able to
172 * complete the action
173 * @vf: VF to which ACK to be sent
174 */
175 static void nic_mbx_send_nack(struct nicpf *nic, int vf)
176 {
177 union nic_mbx mbx = {};
178
179 mbx.msg.msg = NIC_MBOX_MSG_NACK;
180 nic_send_msg_to_vf(nic, vf, &mbx);
181 }
182
183 /* Flush all in flight receive packets to memory and
184 * bring down an active RQ
185 */
186 static int nic_rcv_queue_sw_sync(struct nicpf *nic)
187 {
188 u16 timeout = ~0x00;
189
190 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x01);
191 /* Wait till sync cycle is finished */
192 while (timeout) {
193 if (nic_reg_read(nic, NIC_PF_SW_SYNC_RX_DONE) & 0x1)
194 break;
195 timeout--;
196 }
197 nic_reg_write(nic, NIC_PF_SW_SYNC_RX, 0x00);
198 if (!timeout) {
199 dev_err(&nic->pdev->dev, "Receive queue software sync failed");
200 return 1;
201 }
202 return 0;
203 }
204
205 /* Get BGX Rx/Tx stats and respond to VF's request */
206 static void nic_get_bgx_stats(struct nicpf *nic, struct bgx_stats_msg *bgx)
207 {
208 int bgx_idx, lmac;
209 union nic_mbx mbx = {};
210
211 bgx_idx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
212 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[bgx->vf_id]);
213
214 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
215 mbx.bgx_stats.vf_id = bgx->vf_id;
216 mbx.bgx_stats.rx = bgx->rx;
217 mbx.bgx_stats.idx = bgx->idx;
218 if (bgx->rx)
219 mbx.bgx_stats.stats = bgx_get_rx_stats(nic->node, bgx_idx,
220 lmac, bgx->idx);
221 else
222 mbx.bgx_stats.stats = bgx_get_tx_stats(nic->node, bgx_idx,
223 lmac, bgx->idx);
224 nic_send_msg_to_vf(nic, bgx->vf_id, &mbx);
225 }
226
227 /* Update hardware min/max frame size */
228 static int nic_update_hw_frs(struct nicpf *nic, int new_frs, int vf)
229 {
230 if ((new_frs > NIC_HW_MAX_FRS) || (new_frs < NIC_HW_MIN_FRS)) {
231 dev_err(&nic->pdev->dev,
232 "Invalid MTU setting from VF%d rejected, should be between %d and %d\n",
233 vf, NIC_HW_MIN_FRS, NIC_HW_MAX_FRS);
234 return 1;
235 }
236 new_frs += ETH_HLEN;
237 if (new_frs <= nic->pkind.maxlen)
238 return 0;
239
240 nic->pkind.maxlen = new_frs;
241 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG, *(u64 *)&nic->pkind);
242 return 0;
243 }
244
245 /* Set minimum transmit packet size */
246 static void nic_set_tx_pkt_pad(struct nicpf *nic, int size)
247 {
248 int lmac;
249 u64 lmac_cfg;
250
251 /* Max value that can be set is 60 */
252 if (size > 60)
253 size = 60;
254
255 for (lmac = 0; lmac < (MAX_BGX_PER_CN88XX * MAX_LMAC_PER_BGX); lmac++) {
256 lmac_cfg = nic_reg_read(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3));
257 lmac_cfg &= ~(0xF << 2);
258 lmac_cfg |= ((size / 4) << 2);
259 nic_reg_write(nic, NIC_PF_LMAC_0_7_CFG | (lmac << 3), lmac_cfg);
260 }
261 }
262
263 /* Function to check number of LMACs present and set VF::LMAC mapping.
264 * Mapping will be used while initializing channels.
265 */
266 static void nic_set_lmac_vf_mapping(struct nicpf *nic)
267 {
268 unsigned bgx_map = bgx_get_map(nic->node);
269 int bgx, next_bgx_lmac = 0;
270 int lmac, lmac_cnt = 0;
271 u64 lmac_credit;
272
273 nic->num_vf_en = 0;
274
275 for (bgx = 0; bgx < NIC_MAX_BGX; bgx++) {
276 if (!(bgx_map & (1 << bgx)))
277 continue;
278 lmac_cnt = bgx_get_lmac_count(nic->node, bgx);
279 for (lmac = 0; lmac < lmac_cnt; lmac++)
280 nic->vf_lmac_map[next_bgx_lmac++] =
281 NIC_SET_VF_LMAC_MAP(bgx, lmac);
282 nic->num_vf_en += lmac_cnt;
283
284 /* Program LMAC credits */
285 lmac_credit = (1ull << 1); /* channel credit enable */
286 lmac_credit |= (0x1ff << 2); /* Max outstanding pkt count */
287 /* 48KB BGX Tx buffer size, each unit is of size 16bytes */
288 lmac_credit |= (((((48 * 1024) / lmac_cnt) -
289 NIC_HW_MAX_FRS) / 16) << 12);
290 lmac = bgx * MAX_LMAC_PER_BGX;
291 for (; lmac < lmac_cnt + (bgx * MAX_LMAC_PER_BGX); lmac++)
292 nic_reg_write(nic,
293 NIC_PF_LMAC_0_7_CREDIT + (lmac * 8),
294 lmac_credit);
295 }
296 }
297
298 #define BGX0_BLOCK 8
299 #define BGX1_BLOCK 9
300
301 static void nic_init_hw(struct nicpf *nic)
302 {
303 int i;
304
305 /* Reset NIC, in case the driver is repeatedly inserted and removed */
306 nic_reg_write(nic, NIC_PF_SOFT_RESET, 1);
307
308 /* Enable NIC HW block */
309 nic_reg_write(nic, NIC_PF_CFG, 0x3);
310
311 /* Enable backpressure */
312 nic_reg_write(nic, NIC_PF_BP_CFG, (1ULL << 6) | 0x03);
313
314 /* Disable TNS mode on both interfaces */
315 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG,
316 (NIC_TNS_BYPASS_MODE << 7) | BGX0_BLOCK);
317 nic_reg_write(nic, NIC_PF_INTF_0_1_SEND_CFG | (1 << 8),
318 (NIC_TNS_BYPASS_MODE << 7) | BGX1_BLOCK);
319 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG,
320 (1ULL << 63) | BGX0_BLOCK);
321 nic_reg_write(nic, NIC_PF_INTF_0_1_BP_CFG + (1 << 8),
322 (1ULL << 63) | BGX1_BLOCK);
323
324 /* PKIND configuration */
325 nic->pkind.minlen = 0;
326 nic->pkind.maxlen = NIC_HW_MAX_FRS + ETH_HLEN;
327 nic->pkind.lenerr_en = 1;
328 nic->pkind.rx_hdr = 0;
329 nic->pkind.hdr_sl = 0;
330
331 for (i = 0; i < NIC_MAX_PKIND; i++)
332 nic_reg_write(nic, NIC_PF_PKIND_0_15_CFG | (i << 3),
333 *(u64 *)&nic->pkind);
334
335 nic_set_tx_pkt_pad(nic, NIC_HW_MIN_FRS);
336
337 /* Timer config */
338 nic_reg_write(nic, NIC_PF_INTR_TIMER_CFG, NICPF_CLK_PER_INT_TICK);
339
340 /* Enable VLAN ethertype matching and stripping */
341 nic_reg_write(nic, NIC_PF_RX_ETYPE_0_7,
342 (2 << 19) | (ETYPE_ALG_VLAN_STRIP << 16) | ETH_P_8021Q);
343 }
344
345 /* Channel parse index configuration */
346 static void nic_config_cpi(struct nicpf *nic, struct cpi_cfg_msg *cfg)
347 {
348 u32 vnic, bgx, lmac, chan;
349 u32 padd, cpi_count = 0;
350 u64 cpi_base, cpi, rssi_base, rssi;
351 u8 qset, rq_idx = 0;
352
353 vnic = cfg->vf_id;
354 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
355 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vnic]);
356
357 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
358 cpi_base = (lmac * NIC_MAX_CPI_PER_LMAC) + (bgx * NIC_CPI_PER_BGX);
359 rssi_base = (lmac * nic->rss_ind_tbl_size) + (bgx * NIC_RSSI_PER_BGX);
360
361 /* Rx channel configuration */
362 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_BP_CFG | (chan << 3),
363 (1ull << 63) | (vnic << 0));
364 nic_reg_write(nic, NIC_PF_CHAN_0_255_RX_CFG | (chan << 3),
365 ((u64)cfg->cpi_alg << 62) | (cpi_base << 48));
366
367 if (cfg->cpi_alg == CPI_ALG_NONE)
368 cpi_count = 1;
369 else if (cfg->cpi_alg == CPI_ALG_VLAN) /* 3 bits of PCP */
370 cpi_count = 8;
371 else if (cfg->cpi_alg == CPI_ALG_VLAN16) /* 3 bits PCP + DEI */
372 cpi_count = 16;
373 else if (cfg->cpi_alg == CPI_ALG_DIFF) /* 6bits DSCP */
374 cpi_count = NIC_MAX_CPI_PER_LMAC;
375
376 /* RSS Qset, Qidx mapping */
377 qset = cfg->vf_id;
378 rssi = rssi_base;
379 for (; rssi < (rssi_base + cfg->rq_cnt); rssi++) {
380 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
381 (qset << 3) | rq_idx);
382 rq_idx++;
383 }
384
385 rssi = 0;
386 cpi = cpi_base;
387 for (; cpi < (cpi_base + cpi_count); cpi++) {
388 /* Determine port to channel adder */
389 if (cfg->cpi_alg != CPI_ALG_DIFF)
390 padd = cpi % cpi_count;
391 else
392 padd = cpi % 8; /* 3 bits CS out of 6bits DSCP */
393
394 /* Leave RSS_SIZE as '0' to disable RSS */
395 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi << 3),
396 (vnic << 24) | (padd << 16) | (rssi_base + rssi));
397
398 if ((rssi + 1) >= cfg->rq_cnt)
399 continue;
400
401 if (cfg->cpi_alg == CPI_ALG_VLAN)
402 rssi++;
403 else if (cfg->cpi_alg == CPI_ALG_VLAN16)
404 rssi = ((cpi - cpi_base) & 0xe) >> 1;
405 else if (cfg->cpi_alg == CPI_ALG_DIFF)
406 rssi = ((cpi - cpi_base) & 0x38) >> 3;
407 }
408 nic->cpi_base[cfg->vf_id] = cpi_base;
409 }
410
411 /* Responsds to VF with its RSS indirection table size */
412 static void nic_send_rss_size(struct nicpf *nic, int vf)
413 {
414 union nic_mbx mbx = {};
415 u64 *msg;
416
417 msg = (u64 *)&mbx;
418
419 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
420 mbx.rss_size.ind_tbl_size = nic->rss_ind_tbl_size;
421 nic_send_msg_to_vf(nic, vf, &mbx);
422 }
423
424 /* Receive side scaling configuration
425 * configure:
426 * - RSS index
427 * - indir table i.e hash::RQ mapping
428 * - no of hash bits to consider
429 */
430 static void nic_config_rss(struct nicpf *nic, struct rss_cfg_msg *cfg)
431 {
432 u8 qset, idx = 0;
433 u64 cpi_cfg, cpi_base, rssi_base, rssi;
434
435 cpi_base = nic->cpi_base[cfg->vf_id];
436 cpi_cfg = nic_reg_read(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3));
437 rssi_base = (cpi_cfg & 0x0FFF) + cfg->tbl_offset;
438
439 rssi = rssi_base;
440 qset = cfg->vf_id;
441
442 for (; rssi < (rssi_base + cfg->tbl_len); rssi++) {
443 u8 svf = cfg->ind_tbl[idx] >> 3;
444
445 if (svf)
446 qset = nic->vf_sqs[cfg->vf_id][svf - 1];
447 else
448 qset = cfg->vf_id;
449 nic_reg_write(nic, NIC_PF_RSSI_0_4097_RQ | (rssi << 3),
450 (qset << 3) | (cfg->ind_tbl[idx] & 0x7));
451 idx++;
452 }
453
454 cpi_cfg &= ~(0xFULL << 20);
455 cpi_cfg |= (cfg->hash_bits << 20);
456 nic_reg_write(nic, NIC_PF_CPI_0_2047_CFG | (cpi_base << 3), cpi_cfg);
457 }
458
459 /* 4 level transmit side scheduler configutation
460 * for TNS bypass mode
461 *
462 * Sample configuration for SQ0
463 * VNIC0-SQ0 -> TL4(0) -> TL3[0] -> TL2[0] -> TL1[0] -> BGX0
464 * VNIC1-SQ0 -> TL4(8) -> TL3[2] -> TL2[0] -> TL1[0] -> BGX0
465 * VNIC2-SQ0 -> TL4(16) -> TL3[4] -> TL2[1] -> TL1[0] -> BGX0
466 * VNIC3-SQ0 -> TL4(24) -> TL3[6] -> TL2[1] -> TL1[0] -> BGX0
467 * VNIC4-SQ0 -> TL4(512) -> TL3[128] -> TL2[32] -> TL1[1] -> BGX1
468 * VNIC5-SQ0 -> TL4(520) -> TL3[130] -> TL2[32] -> TL1[1] -> BGX1
469 * VNIC6-SQ0 -> TL4(528) -> TL3[132] -> TL2[33] -> TL1[1] -> BGX1
470 * VNIC7-SQ0 -> TL4(536) -> TL3[134] -> TL2[33] -> TL1[1] -> BGX1
471 */
472 static void nic_tx_channel_cfg(struct nicpf *nic, u8 vnic,
473 struct sq_cfg_msg *sq)
474 {
475 u32 bgx, lmac, chan;
476 u32 tl2, tl3, tl4;
477 u32 rr_quantum;
478 u8 sq_idx = sq->sq_num;
479 u8 pqs_vnic;
480
481 if (sq->sqs_mode)
482 pqs_vnic = nic->pqs_vf[vnic];
483 else
484 pqs_vnic = vnic;
485
486 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
487 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[pqs_vnic]);
488
489 /* 24 bytes for FCS, IPG and preamble */
490 rr_quantum = ((NIC_HW_MAX_FRS + 24) / 4);
491
492 tl4 = (lmac * NIC_TL4_PER_LMAC) + (bgx * NIC_TL4_PER_BGX);
493 tl4 += sq_idx;
494 if (sq->sqs_mode)
495 tl4 += vnic * 8;
496
497 tl3 = tl4 / (NIC_MAX_TL4 / NIC_MAX_TL3);
498 nic_reg_write(nic, NIC_PF_QSET_0_127_SQ_0_7_CFG2 |
499 ((u64)vnic << NIC_QS_ID_SHIFT) |
500 ((u32)sq_idx << NIC_Q_NUM_SHIFT), tl4);
501 nic_reg_write(nic, NIC_PF_TL4_0_1023_CFG | (tl4 << 3),
502 ((u64)vnic << 27) | ((u32)sq_idx << 24) | rr_quantum);
503
504 nic_reg_write(nic, NIC_PF_TL3_0_255_CFG | (tl3 << 3), rr_quantum);
505 chan = (lmac * MAX_BGX_CHANS_PER_LMAC) + (bgx * NIC_CHANS_PER_INF);
506 nic_reg_write(nic, NIC_PF_TL3_0_255_CHAN | (tl3 << 3), chan);
507 /* Enable backpressure on the channel */
508 nic_reg_write(nic, NIC_PF_CHAN_0_255_TX_CFG | (chan << 3), 1);
509
510 tl2 = tl3 >> 2;
511 nic_reg_write(nic, NIC_PF_TL3A_0_63_CFG | (tl2 << 3), tl2);
512 nic_reg_write(nic, NIC_PF_TL2_0_63_CFG | (tl2 << 3), rr_quantum);
513 /* No priorities as of now */
514 nic_reg_write(nic, NIC_PF_TL2_0_63_PRI | (tl2 << 3), 0x00);
515 }
516
517 /* Send primary nicvf pointer to secondary QS's VF */
518 static void nic_send_pnicvf(struct nicpf *nic, int sqs)
519 {
520 union nic_mbx mbx = {};
521
522 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
523 mbx.nicvf.nicvf = nic->nicvf[nic->pqs_vf[sqs]];
524 nic_send_msg_to_vf(nic, sqs, &mbx);
525 }
526
527 /* Send SQS's nicvf pointer to primary QS's VF */
528 static void nic_send_snicvf(struct nicpf *nic, struct nicvf_ptr *nicvf)
529 {
530 union nic_mbx mbx = {};
531 int sqs_id = nic->vf_sqs[nicvf->vf_id][nicvf->sqs_id];
532
533 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
534 mbx.nicvf.sqs_id = nicvf->sqs_id;
535 mbx.nicvf.nicvf = nic->nicvf[sqs_id];
536 nic_send_msg_to_vf(nic, nicvf->vf_id, &mbx);
537 }
538
539 /* Find next available Qset that can be assigned as a
540 * secondary Qset to a VF.
541 */
542 static int nic_nxt_avail_sqs(struct nicpf *nic)
543 {
544 int sqs;
545
546 for (sqs = 0; sqs < nic->num_sqs_en; sqs++) {
547 if (!nic->sqs_used[sqs])
548 nic->sqs_used[sqs] = true;
549 else
550 continue;
551 return sqs + nic->num_vf_en;
552 }
553 return -1;
554 }
555
556 /* Allocate additional Qsets for requested VF */
557 static void nic_alloc_sqs(struct nicpf *nic, struct sqs_alloc *sqs)
558 {
559 union nic_mbx mbx = {};
560 int idx, alloc_qs = 0;
561 int sqs_id;
562
563 if (!nic->num_sqs_en)
564 goto send_mbox;
565
566 for (idx = 0; idx < sqs->qs_count; idx++) {
567 sqs_id = nic_nxt_avail_sqs(nic);
568 if (sqs_id < 0)
569 break;
570 nic->vf_sqs[sqs->vf_id][idx] = sqs_id;
571 nic->pqs_vf[sqs_id] = sqs->vf_id;
572 alloc_qs++;
573 }
574
575 send_mbox:
576 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
577 mbx.sqs_alloc.vf_id = sqs->vf_id;
578 mbx.sqs_alloc.qs_count = alloc_qs;
579 nic_send_msg_to_vf(nic, sqs->vf_id, &mbx);
580 }
581
582 /* Interrupt handler to handle mailbox messages from VFs */
583 static void nic_handle_mbx_intr(struct nicpf *nic, int vf)
584 {
585 union nic_mbx mbx = {};
586 u64 *mbx_data;
587 u64 mbx_addr;
588 u64 reg_addr;
589 u64 cfg;
590 int bgx, lmac;
591 int i;
592 int ret = 0;
593
594 nic->mbx_lock[vf] = true;
595
596 mbx_addr = nic_get_mbx_addr(vf);
597 mbx_data = (u64 *)&mbx;
598
599 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
600 *mbx_data = nic_reg_read(nic, mbx_addr);
601 mbx_data++;
602 mbx_addr += sizeof(u64);
603 }
604
605 dev_dbg(&nic->pdev->dev, "%s: Mailbox msg %d from VF%d\n",
606 __func__, mbx.msg.msg, vf);
607 switch (mbx.msg.msg) {
608 case NIC_MBOX_MSG_READY:
609 nic_mbx_send_ready(nic, vf);
610 if (vf < MAX_LMAC) {
611 nic->link[vf] = 0;
612 nic->duplex[vf] = 0;
613 nic->speed[vf] = 0;
614 }
615 ret = 1;
616 break;
617 case NIC_MBOX_MSG_QS_CFG:
618 reg_addr = NIC_PF_QSET_0_127_CFG |
619 (mbx.qs.num << NIC_QS_ID_SHIFT);
620 cfg = mbx.qs.cfg;
621 /* Check if its a secondary Qset */
622 if (vf >= nic->num_vf_en) {
623 cfg = cfg & (~0x7FULL);
624 /* Assign this Qset to primary Qset's VF */
625 cfg |= nic->pqs_vf[vf];
626 }
627 nic_reg_write(nic, reg_addr, cfg);
628 break;
629 case NIC_MBOX_MSG_RQ_CFG:
630 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_CFG |
631 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
632 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
633 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
634 break;
635 case NIC_MBOX_MSG_RQ_BP_CFG:
636 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_BP_CFG |
637 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
638 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
639 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
640 break;
641 case NIC_MBOX_MSG_RQ_SW_SYNC:
642 ret = nic_rcv_queue_sw_sync(nic);
643 break;
644 case NIC_MBOX_MSG_RQ_DROP_CFG:
645 reg_addr = NIC_PF_QSET_0_127_RQ_0_7_DROP_CFG |
646 (mbx.rq.qs_num << NIC_QS_ID_SHIFT) |
647 (mbx.rq.rq_num << NIC_Q_NUM_SHIFT);
648 nic_reg_write(nic, reg_addr, mbx.rq.cfg);
649 break;
650 case NIC_MBOX_MSG_SQ_CFG:
651 reg_addr = NIC_PF_QSET_0_127_SQ_0_7_CFG |
652 (mbx.sq.qs_num << NIC_QS_ID_SHIFT) |
653 (mbx.sq.sq_num << NIC_Q_NUM_SHIFT);
654 nic_reg_write(nic, reg_addr, mbx.sq.cfg);
655 nic_tx_channel_cfg(nic, mbx.qs.num, &mbx.sq);
656 break;
657 case NIC_MBOX_MSG_SET_MAC:
658 if (vf >= nic->num_vf_en)
659 break;
660 lmac = mbx.mac.vf_id;
661 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
662 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[lmac]);
663 bgx_set_lmac_mac(nic->node, bgx, lmac, mbx.mac.mac_addr);
664 break;
665 case NIC_MBOX_MSG_SET_MAX_FRS:
666 ret = nic_update_hw_frs(nic, mbx.frs.max_frs,
667 mbx.frs.vf_id);
668 break;
669 case NIC_MBOX_MSG_CPI_CFG:
670 nic_config_cpi(nic, &mbx.cpi_cfg);
671 break;
672 case NIC_MBOX_MSG_RSS_SIZE:
673 nic_send_rss_size(nic, vf);
674 goto unlock;
675 case NIC_MBOX_MSG_RSS_CFG:
676 case NIC_MBOX_MSG_RSS_CFG_CONT:
677 nic_config_rss(nic, &mbx.rss_cfg);
678 break;
679 case NIC_MBOX_MSG_CFG_DONE:
680 /* Last message of VF config msg sequence */
681 nic->vf_enabled[vf] = true;
682 goto unlock;
683 case NIC_MBOX_MSG_SHUTDOWN:
684 /* First msg in VF teardown sequence */
685 nic->vf_enabled[vf] = false;
686 if (vf >= nic->num_vf_en)
687 nic->sqs_used[vf - nic->num_vf_en] = false;
688 nic->pqs_vf[vf] = 0;
689 break;
690 case NIC_MBOX_MSG_ALLOC_SQS:
691 nic_alloc_sqs(nic, &mbx.sqs_alloc);
692 goto unlock;
693 case NIC_MBOX_MSG_NICVF_PTR:
694 nic->nicvf[vf] = mbx.nicvf.nicvf;
695 break;
696 case NIC_MBOX_MSG_PNICVF_PTR:
697 nic_send_pnicvf(nic, vf);
698 goto unlock;
699 case NIC_MBOX_MSG_SNICVF_PTR:
700 nic_send_snicvf(nic, &mbx.nicvf);
701 goto unlock;
702 case NIC_MBOX_MSG_BGX_STATS:
703 nic_get_bgx_stats(nic, &mbx.bgx_stats);
704 goto unlock;
705 default:
706 dev_err(&nic->pdev->dev,
707 "Invalid msg from VF%d, msg 0x%x\n", vf, mbx.msg.msg);
708 break;
709 }
710
711 if (!ret)
712 nic_mbx_send_ack(nic, vf);
713 else if (mbx.msg.msg != NIC_MBOX_MSG_READY)
714 nic_mbx_send_nack(nic, vf);
715 unlock:
716 nic->mbx_lock[vf] = false;
717 }
718
719 static void nic_mbx_intr_handler (struct nicpf *nic, int mbx)
720 {
721 u64 intr;
722 u8 vf, vf_per_mbx_reg = 64;
723
724 intr = nic_reg_read(nic, NIC_PF_MAILBOX_INT + (mbx << 3));
725 dev_dbg(&nic->pdev->dev, "PF interrupt Mbox%d 0x%llx\n", mbx, intr);
726 for (vf = 0; vf < vf_per_mbx_reg; vf++) {
727 if (intr & (1ULL << vf)) {
728 dev_dbg(&nic->pdev->dev, "Intr from VF %d\n",
729 vf + (mbx * vf_per_mbx_reg));
730
731 nic_handle_mbx_intr(nic, vf + (mbx * vf_per_mbx_reg));
732 nic_clear_mbx_intr(nic, vf, mbx);
733 }
734 }
735 }
736
737 static irqreturn_t nic_mbx0_intr_handler (int irq, void *nic_irq)
738 {
739 struct nicpf *nic = (struct nicpf *)nic_irq;
740
741 nic_mbx_intr_handler(nic, 0);
742
743 return IRQ_HANDLED;
744 }
745
746 static irqreturn_t nic_mbx1_intr_handler (int irq, void *nic_irq)
747 {
748 struct nicpf *nic = (struct nicpf *)nic_irq;
749
750 nic_mbx_intr_handler(nic, 1);
751
752 return IRQ_HANDLED;
753 }
754
755 static int nic_enable_msix(struct nicpf *nic)
756 {
757 int i, ret;
758
759 nic->num_vec = NIC_PF_MSIX_VECTORS;
760
761 for (i = 0; i < nic->num_vec; i++)
762 nic->msix_entries[i].entry = i;
763
764 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
765 if (ret) {
766 dev_err(&nic->pdev->dev,
767 "Request for #%d msix vectors failed\n",
768 nic->num_vec);
769 return ret;
770 }
771
772 nic->msix_enabled = 1;
773 return 0;
774 }
775
776 static void nic_disable_msix(struct nicpf *nic)
777 {
778 if (nic->msix_enabled) {
779 pci_disable_msix(nic->pdev);
780 nic->msix_enabled = 0;
781 nic->num_vec = 0;
782 }
783 }
784
785 static void nic_free_all_interrupts(struct nicpf *nic)
786 {
787 int irq;
788
789 for (irq = 0; irq < nic->num_vec; irq++) {
790 if (nic->irq_allocated[irq])
791 free_irq(nic->msix_entries[irq].vector, nic);
792 nic->irq_allocated[irq] = false;
793 }
794 }
795
796 static int nic_register_interrupts(struct nicpf *nic)
797 {
798 int ret;
799
800 /* Enable MSI-X */
801 ret = nic_enable_msix(nic);
802 if (ret)
803 return ret;
804
805 /* Register mailbox interrupt handlers */
806 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX0].vector,
807 nic_mbx0_intr_handler, 0, "NIC Mbox0", nic);
808 if (ret)
809 goto fail;
810
811 nic->irq_allocated[NIC_PF_INTR_ID_MBOX0] = true;
812
813 ret = request_irq(nic->msix_entries[NIC_PF_INTR_ID_MBOX1].vector,
814 nic_mbx1_intr_handler, 0, "NIC Mbox1", nic);
815 if (ret)
816 goto fail;
817
818 nic->irq_allocated[NIC_PF_INTR_ID_MBOX1] = true;
819
820 /* Enable mailbox interrupt */
821 nic_enable_mbx_intr(nic);
822 return 0;
823
824 fail:
825 dev_err(&nic->pdev->dev, "Request irq failed\n");
826 nic_free_all_interrupts(nic);
827 return ret;
828 }
829
830 static void nic_unregister_interrupts(struct nicpf *nic)
831 {
832 nic_free_all_interrupts(nic);
833 nic_disable_msix(nic);
834 }
835
836 static int nic_num_sqs_en(struct nicpf *nic, int vf_en)
837 {
838 int pos, sqs_per_vf = MAX_SQS_PER_VF_SINGLE_NODE;
839 u16 total_vf;
840
841 /* Check if its a multi-node environment */
842 if (nr_node_ids > 1)
843 sqs_per_vf = MAX_SQS_PER_VF;
844
845 pos = pci_find_ext_capability(nic->pdev, PCI_EXT_CAP_ID_SRIOV);
846 pci_read_config_word(nic->pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf);
847 return min(total_vf - vf_en, vf_en * sqs_per_vf);
848 }
849
850 static int nic_sriov_init(struct pci_dev *pdev, struct nicpf *nic)
851 {
852 int pos = 0;
853 int vf_en;
854 int err;
855 u16 total_vf_cnt;
856
857 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
858 if (!pos) {
859 dev_err(&pdev->dev, "SRIOV capability is not found in PCIe config space\n");
860 return -ENODEV;
861 }
862
863 pci_read_config_word(pdev, (pos + PCI_SRIOV_TOTAL_VF), &total_vf_cnt);
864 if (total_vf_cnt < nic->num_vf_en)
865 nic->num_vf_en = total_vf_cnt;
866
867 if (!total_vf_cnt)
868 return 0;
869
870 vf_en = nic->num_vf_en;
871 nic->num_sqs_en = nic_num_sqs_en(nic, nic->num_vf_en);
872 vf_en += nic->num_sqs_en;
873
874 err = pci_enable_sriov(pdev, vf_en);
875 if (err) {
876 dev_err(&pdev->dev, "SRIOV enable failed, num VF is %d\n",
877 vf_en);
878 nic->num_vf_en = 0;
879 return err;
880 }
881
882 dev_info(&pdev->dev, "SRIOV enabled, number of VF available %d\n",
883 vf_en);
884
885 nic->flags |= NIC_SRIOV_ENABLED;
886 return 0;
887 }
888
889 /* Poll for BGX LMAC link status and update corresponding VF
890 * if there is a change, valid only if internal L2 switch
891 * is not present otherwise VF link is always treated as up
892 */
893 static void nic_poll_for_link(struct work_struct *work)
894 {
895 union nic_mbx mbx = {};
896 struct nicpf *nic;
897 struct bgx_link_status link;
898 u8 vf, bgx, lmac;
899
900 nic = container_of(work, struct nicpf, dwork.work);
901
902 mbx.link_status.msg = NIC_MBOX_MSG_BGX_LINK_CHANGE;
903
904 for (vf = 0; vf < nic->num_vf_en; vf++) {
905 /* Poll only if VF is UP */
906 if (!nic->vf_enabled[vf])
907 continue;
908
909 /* Get BGX, LMAC indices for the VF */
910 bgx = NIC_GET_BGX_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
911 lmac = NIC_GET_LMAC_FROM_VF_LMAC_MAP(nic->vf_lmac_map[vf]);
912 /* Get interface link status */
913 bgx_get_lmac_link_state(nic->node, bgx, lmac, &link);
914
915 /* Inform VF only if link status changed */
916 if (nic->link[vf] == link.link_up)
917 continue;
918
919 if (!nic->mbx_lock[vf]) {
920 nic->link[vf] = link.link_up;
921 nic->duplex[vf] = link.duplex;
922 nic->speed[vf] = link.speed;
923
924 /* Send a mbox message to VF with current link status */
925 mbx.link_status.link_up = link.link_up;
926 mbx.link_status.duplex = link.duplex;
927 mbx.link_status.speed = link.speed;
928 nic_send_msg_to_vf(nic, vf, &mbx);
929 }
930 }
931 queue_delayed_work(nic->check_link, &nic->dwork, HZ * 2);
932 }
933
934 static int nic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
935 {
936 struct device *dev = &pdev->dev;
937 struct nicpf *nic;
938 int err;
939
940 BUILD_BUG_ON(sizeof(union nic_mbx) > 16);
941
942 nic = devm_kzalloc(dev, sizeof(*nic), GFP_KERNEL);
943 if (!nic)
944 return -ENOMEM;
945
946 pci_set_drvdata(pdev, nic);
947
948 nic->pdev = pdev;
949
950 err = pci_enable_device(pdev);
951 if (err) {
952 dev_err(dev, "Failed to enable PCI device\n");
953 pci_set_drvdata(pdev, NULL);
954 return err;
955 }
956
957 err = pci_request_regions(pdev, DRV_NAME);
958 if (err) {
959 dev_err(dev, "PCI request regions failed 0x%x\n", err);
960 goto err_disable_device;
961 }
962
963 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
964 if (err) {
965 dev_err(dev, "Unable to get usable DMA configuration\n");
966 goto err_release_regions;
967 }
968
969 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
970 if (err) {
971 dev_err(dev, "Unable to get 48-bit DMA for consistent allocations\n");
972 goto err_release_regions;
973 }
974
975 /* MAP PF's configuration registers */
976 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
977 if (!nic->reg_base) {
978 dev_err(dev, "Cannot map config register space, aborting\n");
979 err = -ENOMEM;
980 goto err_release_regions;
981 }
982
983 pci_read_config_byte(pdev, PCI_REVISION_ID, &nic->rev_id);
984
985 nic->node = nic_get_node_id(pdev);
986
987 nic_set_lmac_vf_mapping(nic);
988
989 /* Initialize hardware */
990 nic_init_hw(nic);
991
992 /* Set RSS TBL size for each VF */
993 nic->rss_ind_tbl_size = NIC_MAX_RSS_IDR_TBL_SIZE;
994
995 /* Register interrupts */
996 err = nic_register_interrupts(nic);
997 if (err)
998 goto err_release_regions;
999
1000 /* Configure SRIOV */
1001 err = nic_sriov_init(pdev, nic);
1002 if (err)
1003 goto err_unregister_interrupts;
1004
1005 /* Register a physical link status poll fn() */
1006 nic->check_link = alloc_workqueue("check_link_status",
1007 WQ_UNBOUND | WQ_MEM_RECLAIM, 1);
1008 if (!nic->check_link) {
1009 err = -ENOMEM;
1010 goto err_disable_sriov;
1011 }
1012
1013 INIT_DELAYED_WORK(&nic->dwork, nic_poll_for_link);
1014 queue_delayed_work(nic->check_link, &nic->dwork, 0);
1015
1016 return 0;
1017
1018 err_disable_sriov:
1019 if (nic->flags & NIC_SRIOV_ENABLED)
1020 pci_disable_sriov(pdev);
1021 err_unregister_interrupts:
1022 nic_unregister_interrupts(nic);
1023 err_release_regions:
1024 pci_release_regions(pdev);
1025 err_disable_device:
1026 pci_disable_device(pdev);
1027 pci_set_drvdata(pdev, NULL);
1028 return err;
1029 }
1030
1031 static void nic_remove(struct pci_dev *pdev)
1032 {
1033 struct nicpf *nic = pci_get_drvdata(pdev);
1034
1035 if (nic->flags & NIC_SRIOV_ENABLED)
1036 pci_disable_sriov(pdev);
1037
1038 if (nic->check_link) {
1039 /* Destroy work Queue */
1040 cancel_delayed_work(&nic->dwork);
1041 flush_workqueue(nic->check_link);
1042 destroy_workqueue(nic->check_link);
1043 }
1044
1045 nic_unregister_interrupts(nic);
1046 pci_release_regions(pdev);
1047 pci_disable_device(pdev);
1048 pci_set_drvdata(pdev, NULL);
1049 }
1050
1051 static struct pci_driver nic_driver = {
1052 .name = DRV_NAME,
1053 .id_table = nic_id_table,
1054 .probe = nic_probe,
1055 .remove = nic_remove,
1056 };
1057
1058 static int __init nic_init_module(void)
1059 {
1060 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1061
1062 return pci_register_driver(&nic_driver);
1063 }
1064
1065 static void __exit nic_cleanup_module(void)
1066 {
1067 pci_unregister_driver(&nic_driver);
1068 }
1069
1070 module_init(nic_init_module);
1071 module_exit(nic_cleanup_module);
Linux kernel - Deliverables
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