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net: thunderx: Support for upto 96 queues for a VF
[deliverable/linux.git] / drivers / net / ethernet / cavium / thunder / nicvf_main.c
1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/module.h>
10 #include <linux/interrupt.h>
11 #include <linux/pci.h>
12 #include <linux/netdevice.h>
13 #include <linux/if_vlan.h>
14 #include <linux/etherdevice.h>
15 #include <linux/ethtool.h>
16 #include <linux/log2.h>
17 #include <linux/prefetch.h>
18 #include <linux/irq.h>
19
20 #include "nic_reg.h"
21 #include "nic.h"
22 #include "nicvf_queues.h"
23 #include "thunder_bgx.h"
24
25 #define DRV_NAME "thunder-nicvf"
26 #define DRV_VERSION "1.0"
27
28 /* Supported devices */
29 static const struct pci_device_id nicvf_id_table[] = {
30 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
31 PCI_DEVICE_ID_THUNDER_NIC_VF,
32 PCI_VENDOR_ID_CAVIUM, 0xA11E) },
33 { PCI_DEVICE_SUB(PCI_VENDOR_ID_CAVIUM,
34 PCI_DEVICE_ID_THUNDER_PASS1_NIC_VF,
35 PCI_VENDOR_ID_CAVIUM, 0xA11E) },
36 { 0, } /* end of table */
37 };
38
39 MODULE_AUTHOR("Sunil Goutham");
40 MODULE_DESCRIPTION("Cavium Thunder NIC Virtual Function Driver");
41 MODULE_LICENSE("GPL v2");
42 MODULE_VERSION(DRV_VERSION);
43 MODULE_DEVICE_TABLE(pci, nicvf_id_table);
44
45 static int debug = 0x00;
46 module_param(debug, int, 0644);
47 MODULE_PARM_DESC(debug, "Debug message level bitmap");
48
49 static int cpi_alg = CPI_ALG_NONE;
50 module_param(cpi_alg, int, S_IRUGO);
51 MODULE_PARM_DESC(cpi_alg,
52 "PFC algorithm (0=none, 1=VLAN, 2=VLAN16, 3=IP Diffserv)");
53
54 static inline u8 nicvf_netdev_qidx(struct nicvf *nic, u8 qidx)
55 {
56 if (nic->sqs_mode)
57 return qidx + ((nic->sqs_id + 1) * MAX_CMP_QUEUES_PER_QS);
58 else
59 return qidx;
60 }
61
62 static inline void nicvf_set_rx_frame_cnt(struct nicvf *nic,
63 struct sk_buff *skb)
64 {
65 if (skb->len <= 64)
66 nic->drv_stats.rx_frames_64++;
67 else if (skb->len <= 127)
68 nic->drv_stats.rx_frames_127++;
69 else if (skb->len <= 255)
70 nic->drv_stats.rx_frames_255++;
71 else if (skb->len <= 511)
72 nic->drv_stats.rx_frames_511++;
73 else if (skb->len <= 1023)
74 nic->drv_stats.rx_frames_1023++;
75 else if (skb->len <= 1518)
76 nic->drv_stats.rx_frames_1518++;
77 else
78 nic->drv_stats.rx_frames_jumbo++;
79 }
80
81 /* The Cavium ThunderX network controller can *only* be found in SoCs
82 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
83 * registers on this platform are implicitly strongly ordered with respect
84 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
85 * with no memory barriers in this driver. The readq()/writeq() functions add
86 * explicit ordering operation which in this case are redundant, and only
87 * add overhead.
88 */
89
90 /* Register read/write APIs */
91 void nicvf_reg_write(struct nicvf *nic, u64 offset, u64 val)
92 {
93 writeq_relaxed(val, nic->reg_base + offset);
94 }
95
96 u64 nicvf_reg_read(struct nicvf *nic, u64 offset)
97 {
98 return readq_relaxed(nic->reg_base + offset);
99 }
100
101 void nicvf_queue_reg_write(struct nicvf *nic, u64 offset,
102 u64 qidx, u64 val)
103 {
104 void __iomem *addr = nic->reg_base + offset;
105
106 writeq_relaxed(val, addr + (qidx << NIC_Q_NUM_SHIFT));
107 }
108
109 u64 nicvf_queue_reg_read(struct nicvf *nic, u64 offset, u64 qidx)
110 {
111 void __iomem *addr = nic->reg_base + offset;
112
113 return readq_relaxed(addr + (qidx << NIC_Q_NUM_SHIFT));
114 }
115
116 /* VF -> PF mailbox communication */
117 static void nicvf_write_to_mbx(struct nicvf *nic, union nic_mbx *mbx)
118 {
119 u64 *msg = (u64 *)mbx;
120
121 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 0, msg[0]);
122 nicvf_reg_write(nic, NIC_VF_PF_MAILBOX_0_1 + 8, msg[1]);
123 }
124
125 int nicvf_send_msg_to_pf(struct nicvf *nic, union nic_mbx *mbx)
126 {
127 int timeout = NIC_MBOX_MSG_TIMEOUT;
128 int sleep = 10;
129
130 nic->pf_acked = false;
131 nic->pf_nacked = false;
132
133 nicvf_write_to_mbx(nic, mbx);
134
135 /* Wait for previous message to be acked, timeout 2sec */
136 while (!nic->pf_acked) {
137 if (nic->pf_nacked)
138 return -EINVAL;
139 msleep(sleep);
140 if (nic->pf_acked)
141 break;
142 timeout -= sleep;
143 if (!timeout) {
144 netdev_err(nic->netdev,
145 "PF didn't ack to mbox msg %d from VF%d\n",
146 (mbx->msg.msg & 0xFF), nic->vf_id);
147 return -EBUSY;
148 }
149 }
150 return 0;
151 }
152
153 /* Checks if VF is able to comminicate with PF
154 * and also gets the VNIC number this VF is associated to.
155 */
156 static int nicvf_check_pf_ready(struct nicvf *nic)
157 {
158 union nic_mbx mbx = {};
159
160 mbx.msg.msg = NIC_MBOX_MSG_READY;
161 if (nicvf_send_msg_to_pf(nic, &mbx)) {
162 netdev_err(nic->netdev,
163 "PF didn't respond to READY msg\n");
164 return 0;
165 }
166
167 return 1;
168 }
169
170 static void nicvf_read_bgx_stats(struct nicvf *nic, struct bgx_stats_msg *bgx)
171 {
172 if (bgx->rx)
173 nic->bgx_stats.rx_stats[bgx->idx] = bgx->stats;
174 else
175 nic->bgx_stats.tx_stats[bgx->idx] = bgx->stats;
176 }
177
178 static void nicvf_handle_mbx_intr(struct nicvf *nic)
179 {
180 union nic_mbx mbx = {};
181 u64 *mbx_data;
182 u64 mbx_addr;
183 int i;
184
185 mbx_addr = NIC_VF_PF_MAILBOX_0_1;
186 mbx_data = (u64 *)&mbx;
187
188 for (i = 0; i < NIC_PF_VF_MAILBOX_SIZE; i++) {
189 *mbx_data = nicvf_reg_read(nic, mbx_addr);
190 mbx_data++;
191 mbx_addr += sizeof(u64);
192 }
193
194 netdev_dbg(nic->netdev, "Mbox message: msg: 0x%x\n", mbx.msg.msg);
195 switch (mbx.msg.msg) {
196 case NIC_MBOX_MSG_READY:
197 nic->pf_acked = true;
198 nic->vf_id = mbx.nic_cfg.vf_id & 0x7F;
199 nic->tns_mode = mbx.nic_cfg.tns_mode & 0x7F;
200 nic->node = mbx.nic_cfg.node_id;
201 if (!nic->set_mac_pending)
202 ether_addr_copy(nic->netdev->dev_addr,
203 mbx.nic_cfg.mac_addr);
204 nic->sqs_mode = mbx.nic_cfg.sqs_mode;
205 nic->link_up = false;
206 nic->duplex = 0;
207 nic->speed = 0;
208 break;
209 case NIC_MBOX_MSG_ACK:
210 nic->pf_acked = true;
211 break;
212 case NIC_MBOX_MSG_NACK:
213 nic->pf_nacked = true;
214 break;
215 case NIC_MBOX_MSG_RSS_SIZE:
216 nic->rss_info.rss_size = mbx.rss_size.ind_tbl_size;
217 nic->pf_acked = true;
218 break;
219 case NIC_MBOX_MSG_BGX_STATS:
220 nicvf_read_bgx_stats(nic, &mbx.bgx_stats);
221 nic->pf_acked = true;
222 break;
223 case NIC_MBOX_MSG_BGX_LINK_CHANGE:
224 nic->pf_acked = true;
225 nic->link_up = mbx.link_status.link_up;
226 nic->duplex = mbx.link_status.duplex;
227 nic->speed = mbx.link_status.speed;
228 if (nic->link_up) {
229 netdev_info(nic->netdev, "%s: Link is Up %d Mbps %s\n",
230 nic->netdev->name, nic->speed,
231 nic->duplex == DUPLEX_FULL ?
232 "Full duplex" : "Half duplex");
233 netif_carrier_on(nic->netdev);
234 netif_tx_start_all_queues(nic->netdev);
235 } else {
236 netdev_info(nic->netdev, "%s: Link is Down\n",
237 nic->netdev->name);
238 netif_carrier_off(nic->netdev);
239 netif_tx_stop_all_queues(nic->netdev);
240 }
241 break;
242 case NIC_MBOX_MSG_ALLOC_SQS:
243 nic->sqs_count = mbx.sqs_alloc.qs_count;
244 nic->pf_acked = true;
245 break;
246 case NIC_MBOX_MSG_SNICVF_PTR:
247 /* Primary VF: make note of secondary VF's pointer
248 * to be used while packet transmission.
249 */
250 nic->snicvf[mbx.nicvf.sqs_id] =
251 (struct nicvf *)mbx.nicvf.nicvf;
252 nic->pf_acked = true;
253 break;
254 case NIC_MBOX_MSG_PNICVF_PTR:
255 /* Secondary VF/Qset: make note of primary VF's pointer
256 * to be used while packet reception, to handover packet
257 * to primary VF's netdev.
258 */
259 nic->pnicvf = (struct nicvf *)mbx.nicvf.nicvf;
260 nic->pf_acked = true;
261 break;
262 default:
263 netdev_err(nic->netdev,
264 "Invalid message from PF, msg 0x%x\n", mbx.msg.msg);
265 break;
266 }
267 nicvf_clear_intr(nic, NICVF_INTR_MBOX, 0);
268 }
269
270 static int nicvf_hw_set_mac_addr(struct nicvf *nic, struct net_device *netdev)
271 {
272 union nic_mbx mbx = {};
273
274 mbx.mac.msg = NIC_MBOX_MSG_SET_MAC;
275 mbx.mac.vf_id = nic->vf_id;
276 ether_addr_copy(mbx.mac.mac_addr, netdev->dev_addr);
277
278 return nicvf_send_msg_to_pf(nic, &mbx);
279 }
280
281 static void nicvf_config_cpi(struct nicvf *nic)
282 {
283 union nic_mbx mbx = {};
284
285 mbx.cpi_cfg.msg = NIC_MBOX_MSG_CPI_CFG;
286 mbx.cpi_cfg.vf_id = nic->vf_id;
287 mbx.cpi_cfg.cpi_alg = nic->cpi_alg;
288 mbx.cpi_cfg.rq_cnt = nic->qs->rq_cnt;
289
290 nicvf_send_msg_to_pf(nic, &mbx);
291 }
292
293 static void nicvf_get_rss_size(struct nicvf *nic)
294 {
295 union nic_mbx mbx = {};
296
297 mbx.rss_size.msg = NIC_MBOX_MSG_RSS_SIZE;
298 mbx.rss_size.vf_id = nic->vf_id;
299 nicvf_send_msg_to_pf(nic, &mbx);
300 }
301
302 void nicvf_config_rss(struct nicvf *nic)
303 {
304 union nic_mbx mbx = {};
305 struct nicvf_rss_info *rss = &nic->rss_info;
306 int ind_tbl_len = rss->rss_size;
307 int i, nextq = 0;
308
309 mbx.rss_cfg.vf_id = nic->vf_id;
310 mbx.rss_cfg.hash_bits = rss->hash_bits;
311 while (ind_tbl_len) {
312 mbx.rss_cfg.tbl_offset = nextq;
313 mbx.rss_cfg.tbl_len = min(ind_tbl_len,
314 RSS_IND_TBL_LEN_PER_MBX_MSG);
315 mbx.rss_cfg.msg = mbx.rss_cfg.tbl_offset ?
316 NIC_MBOX_MSG_RSS_CFG_CONT : NIC_MBOX_MSG_RSS_CFG;
317
318 for (i = 0; i < mbx.rss_cfg.tbl_len; i++)
319 mbx.rss_cfg.ind_tbl[i] = rss->ind_tbl[nextq++];
320
321 nicvf_send_msg_to_pf(nic, &mbx);
322
323 ind_tbl_len -= mbx.rss_cfg.tbl_len;
324 }
325 }
326
327 void nicvf_set_rss_key(struct nicvf *nic)
328 {
329 struct nicvf_rss_info *rss = &nic->rss_info;
330 u64 key_addr = NIC_VNIC_RSS_KEY_0_4;
331 int idx;
332
333 for (idx = 0; idx < RSS_HASH_KEY_SIZE; idx++) {
334 nicvf_reg_write(nic, key_addr, rss->key[idx]);
335 key_addr += sizeof(u64);
336 }
337 }
338
339 static int nicvf_rss_init(struct nicvf *nic)
340 {
341 struct nicvf_rss_info *rss = &nic->rss_info;
342 int idx;
343
344 nicvf_get_rss_size(nic);
345
346 if (cpi_alg != CPI_ALG_NONE) {
347 rss->enable = false;
348 rss->hash_bits = 0;
349 return 0;
350 }
351
352 rss->enable = true;
353
354 /* Using the HW reset value for now */
355 rss->key[0] = 0xFEED0BADFEED0BADULL;
356 rss->key[1] = 0xFEED0BADFEED0BADULL;
357 rss->key[2] = 0xFEED0BADFEED0BADULL;
358 rss->key[3] = 0xFEED0BADFEED0BADULL;
359 rss->key[4] = 0xFEED0BADFEED0BADULL;
360
361 nicvf_set_rss_key(nic);
362
363 rss->cfg = RSS_IP_HASH_ENA | RSS_TCP_HASH_ENA | RSS_UDP_HASH_ENA;
364 nicvf_reg_write(nic, NIC_VNIC_RSS_CFG, rss->cfg);
365
366 rss->hash_bits = ilog2(rounddown_pow_of_two(rss->rss_size));
367
368 for (idx = 0; idx < rss->rss_size; idx++)
369 rss->ind_tbl[idx] = ethtool_rxfh_indir_default(idx,
370 nic->rx_queues);
371 nicvf_config_rss(nic);
372 return 1;
373 }
374
375 /* Request PF to allocate additional Qsets */
376 static void nicvf_request_sqs(struct nicvf *nic)
377 {
378 union nic_mbx mbx = {};
379 int sqs;
380 int sqs_count = nic->sqs_count;
381 int rx_queues = 0, tx_queues = 0;
382
383 /* Only primary VF should request */
384 if (nic->sqs_mode || !nic->sqs_count)
385 return;
386
387 mbx.sqs_alloc.msg = NIC_MBOX_MSG_ALLOC_SQS;
388 mbx.sqs_alloc.vf_id = nic->vf_id;
389 mbx.sqs_alloc.qs_count = nic->sqs_count;
390 if (nicvf_send_msg_to_pf(nic, &mbx)) {
391 /* No response from PF */
392 nic->sqs_count = 0;
393 return;
394 }
395
396 /* Return if no Secondary Qsets available */
397 if (!nic->sqs_count)
398 return;
399
400 if (nic->rx_queues > MAX_RCV_QUEUES_PER_QS)
401 rx_queues = nic->rx_queues - MAX_RCV_QUEUES_PER_QS;
402 if (nic->tx_queues > MAX_SND_QUEUES_PER_QS)
403 tx_queues = nic->tx_queues - MAX_SND_QUEUES_PER_QS;
404
405 /* Set no of Rx/Tx queues in each of the SQsets */
406 for (sqs = 0; sqs < nic->sqs_count; sqs++) {
407 mbx.nicvf.msg = NIC_MBOX_MSG_SNICVF_PTR;
408 mbx.nicvf.vf_id = nic->vf_id;
409 mbx.nicvf.sqs_id = sqs;
410 nicvf_send_msg_to_pf(nic, &mbx);
411
412 nic->snicvf[sqs]->sqs_id = sqs;
413 if (rx_queues > MAX_RCV_QUEUES_PER_QS) {
414 nic->snicvf[sqs]->qs->rq_cnt = MAX_RCV_QUEUES_PER_QS;
415 rx_queues -= MAX_RCV_QUEUES_PER_QS;
416 } else {
417 nic->snicvf[sqs]->qs->rq_cnt = rx_queues;
418 rx_queues = 0;
419 }
420
421 if (tx_queues > MAX_SND_QUEUES_PER_QS) {
422 nic->snicvf[sqs]->qs->sq_cnt = MAX_SND_QUEUES_PER_QS;
423 tx_queues -= MAX_SND_QUEUES_PER_QS;
424 } else {
425 nic->snicvf[sqs]->qs->sq_cnt = tx_queues;
426 tx_queues = 0;
427 }
428
429 nic->snicvf[sqs]->qs->cq_cnt =
430 max(nic->snicvf[sqs]->qs->rq_cnt, nic->snicvf[sqs]->qs->sq_cnt);
431
432 /* Initialize secondary Qset's queues and its interrupts */
433 nicvf_open(nic->snicvf[sqs]->netdev);
434 }
435
436 /* Update stack with actual Rx/Tx queue count allocated */
437 if (sqs_count != nic->sqs_count)
438 nicvf_set_real_num_queues(nic->netdev,
439 nic->tx_queues, nic->rx_queues);
440 }
441
442 /* Send this Qset's nicvf pointer to PF.
443 * PF inturn sends primary VF's nicvf struct to secondary Qsets/VFs
444 * so that packets received by these Qsets can use primary VF's netdev
445 */
446 static void nicvf_send_vf_struct(struct nicvf *nic)
447 {
448 union nic_mbx mbx = {};
449
450 mbx.nicvf.msg = NIC_MBOX_MSG_NICVF_PTR;
451 mbx.nicvf.sqs_mode = nic->sqs_mode;
452 mbx.nicvf.nicvf = (u64)nic;
453 nicvf_send_msg_to_pf(nic, &mbx);
454 }
455
456 static void nicvf_get_primary_vf_struct(struct nicvf *nic)
457 {
458 union nic_mbx mbx = {};
459
460 mbx.nicvf.msg = NIC_MBOX_MSG_PNICVF_PTR;
461 nicvf_send_msg_to_pf(nic, &mbx);
462 }
463
464 int nicvf_set_real_num_queues(struct net_device *netdev,
465 int tx_queues, int rx_queues)
466 {
467 int err = 0;
468
469 err = netif_set_real_num_tx_queues(netdev, tx_queues);
470 if (err) {
471 netdev_err(netdev,
472 "Failed to set no of Tx queues: %d\n", tx_queues);
473 return err;
474 }
475
476 err = netif_set_real_num_rx_queues(netdev, rx_queues);
477 if (err)
478 netdev_err(netdev,
479 "Failed to set no of Rx queues: %d\n", rx_queues);
480 return err;
481 }
482
483 static int nicvf_init_resources(struct nicvf *nic)
484 {
485 int err;
486 union nic_mbx mbx = {};
487
488 mbx.msg.msg = NIC_MBOX_MSG_CFG_DONE;
489
490 /* Enable Qset */
491 nicvf_qset_config(nic, true);
492
493 /* Initialize queues and HW for data transfer */
494 err = nicvf_config_data_transfer(nic, true);
495 if (err) {
496 netdev_err(nic->netdev,
497 "Failed to alloc/config VF's QSet resources\n");
498 return err;
499 }
500
501 /* Send VF config done msg to PF */
502 nicvf_write_to_mbx(nic, &mbx);
503
504 return 0;
505 }
506
507 static void nicvf_snd_pkt_handler(struct net_device *netdev,
508 struct cmp_queue *cq,
509 struct cqe_send_t *cqe_tx, int cqe_type)
510 {
511 struct sk_buff *skb = NULL;
512 struct nicvf *nic = netdev_priv(netdev);
513 struct snd_queue *sq;
514 struct sq_hdr_subdesc *hdr;
515
516 sq = &nic->qs->sq[cqe_tx->sq_idx];
517
518 hdr = (struct sq_hdr_subdesc *)GET_SQ_DESC(sq, cqe_tx->sqe_ptr);
519 if (hdr->subdesc_type != SQ_DESC_TYPE_HEADER)
520 return;
521
522 netdev_dbg(nic->netdev,
523 "%s Qset #%d SQ #%d SQ ptr #%d subdesc count %d\n",
524 __func__, cqe_tx->sq_qs, cqe_tx->sq_idx,
525 cqe_tx->sqe_ptr, hdr->subdesc_cnt);
526
527 nicvf_put_sq_desc(sq, hdr->subdesc_cnt + 1);
528 nicvf_check_cqe_tx_errs(nic, cq, cqe_tx);
529 skb = (struct sk_buff *)sq->skbuff[cqe_tx->sqe_ptr];
530 /* For TSO offloaded packets only one head SKB needs to be freed */
531 if (skb) {
532 prefetch(skb);
533 dev_consume_skb_any(skb);
534 sq->skbuff[cqe_tx->sqe_ptr] = (u64)NULL;
535 }
536 }
537
538 static inline void nicvf_set_rxhash(struct net_device *netdev,
539 struct cqe_rx_t *cqe_rx,
540 struct sk_buff *skb)
541 {
542 u8 hash_type;
543 u32 hash;
544
545 if (!(netdev->features & NETIF_F_RXHASH))
546 return;
547
548 switch (cqe_rx->rss_alg) {
549 case RSS_ALG_TCP_IP:
550 case RSS_ALG_UDP_IP:
551 hash_type = PKT_HASH_TYPE_L4;
552 hash = cqe_rx->rss_tag;
553 break;
554 case RSS_ALG_IP:
555 hash_type = PKT_HASH_TYPE_L3;
556 hash = cqe_rx->rss_tag;
557 break;
558 default:
559 hash_type = PKT_HASH_TYPE_NONE;
560 hash = 0;
561 }
562
563 skb_set_hash(skb, hash, hash_type);
564 }
565
566 static void nicvf_rcv_pkt_handler(struct net_device *netdev,
567 struct napi_struct *napi,
568 struct cmp_queue *cq,
569 struct cqe_rx_t *cqe_rx, int cqe_type)
570 {
571 struct sk_buff *skb;
572 struct nicvf *nic = netdev_priv(netdev);
573 int err = 0;
574 int rq_idx;
575
576 rq_idx = nicvf_netdev_qidx(nic, cqe_rx->rq_idx);
577
578 if (nic->sqs_mode) {
579 /* Use primary VF's 'nicvf' struct */
580 nic = nic->pnicvf;
581 netdev = nic->netdev;
582 }
583
584 /* Check for errors */
585 err = nicvf_check_cqe_rx_errs(nic, cq, cqe_rx);
586 if (err && !cqe_rx->rb_cnt)
587 return;
588
589 skb = nicvf_get_rcv_skb(nic, cqe_rx);
590 if (!skb) {
591 netdev_dbg(nic->netdev, "Packet not received\n");
592 return;
593 }
594
595 if (netif_msg_pktdata(nic)) {
596 netdev_info(nic->netdev, "%s: skb 0x%p, len=%d\n", netdev->name,
597 skb, skb->len);
598 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
599 skb->data, skb->len, true);
600 }
601
602 /* If error packet, drop it here */
603 if (err) {
604 dev_kfree_skb_any(skb);
605 return;
606 }
607
608 nicvf_set_rx_frame_cnt(nic, skb);
609
610 nicvf_set_rxhash(netdev, cqe_rx, skb);
611
612 skb_record_rx_queue(skb, rq_idx);
613 if (netdev->hw_features & NETIF_F_RXCSUM) {
614 /* HW by default verifies TCP/UDP/SCTP checksums */
615 skb->ip_summed = CHECKSUM_UNNECESSARY;
616 } else {
617 skb_checksum_none_assert(skb);
618 }
619
620 skb->protocol = eth_type_trans(skb, netdev);
621
622 /* Check for stripped VLAN */
623 if (cqe_rx->vlan_found && cqe_rx->vlan_stripped)
624 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
625 ntohs((__force __be16)cqe_rx->vlan_tci));
626
627 if (napi && (netdev->features & NETIF_F_GRO))
628 napi_gro_receive(napi, skb);
629 else
630 netif_receive_skb(skb);
631 }
632
633 static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
634 struct napi_struct *napi, int budget)
635 {
636 int processed_cqe, work_done = 0, tx_done = 0;
637 int cqe_count, cqe_head;
638 struct nicvf *nic = netdev_priv(netdev);
639 struct queue_set *qs = nic->qs;
640 struct cmp_queue *cq = &qs->cq[cq_idx];
641 struct cqe_rx_t *cq_desc;
642 struct netdev_queue *txq;
643
644 spin_lock_bh(&cq->lock);
645 loop:
646 processed_cqe = 0;
647 /* Get no of valid CQ entries to process */
648 cqe_count = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS, cq_idx);
649 cqe_count &= CQ_CQE_COUNT;
650 if (!cqe_count)
651 goto done;
652
653 /* Get head of the valid CQ entries */
654 cqe_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD, cq_idx) >> 9;
655 cqe_head &= 0xFFFF;
656
657 netdev_dbg(nic->netdev, "%s CQ%d cqe_count %d cqe_head %d\n",
658 __func__, cq_idx, cqe_count, cqe_head);
659 while (processed_cqe < cqe_count) {
660 /* Get the CQ descriptor */
661 cq_desc = (struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head);
662 cqe_head++;
663 cqe_head &= (cq->dmem.q_len - 1);
664 /* Initiate prefetch for next descriptor */
665 prefetch((struct cqe_rx_t *)GET_CQ_DESC(cq, cqe_head));
666
667 if ((work_done >= budget) && napi &&
668 (cq_desc->cqe_type != CQE_TYPE_SEND)) {
669 break;
670 }
671
672 netdev_dbg(nic->netdev, "CQ%d cq_desc->cqe_type %d\n",
673 cq_idx, cq_desc->cqe_type);
674 switch (cq_desc->cqe_type) {
675 case CQE_TYPE_RX:
676 nicvf_rcv_pkt_handler(netdev, napi, cq,
677 cq_desc, CQE_TYPE_RX);
678 work_done++;
679 break;
680 case CQE_TYPE_SEND:
681 nicvf_snd_pkt_handler(netdev, cq,
682 (void *)cq_desc, CQE_TYPE_SEND);
683 tx_done++;
684 break;
685 case CQE_TYPE_INVALID:
686 case CQE_TYPE_RX_SPLIT:
687 case CQE_TYPE_RX_TCP:
688 case CQE_TYPE_SEND_PTP:
689 /* Ignore for now */
690 break;
691 }
692 processed_cqe++;
693 }
694 netdev_dbg(nic->netdev,
695 "%s CQ%d processed_cqe %d work_done %d budget %d\n",
696 __func__, cq_idx, processed_cqe, work_done, budget);
697
698 /* Ring doorbell to inform H/W to reuse processed CQEs */
699 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_DOOR,
700 cq_idx, processed_cqe);
701
702 if ((work_done < budget) && napi)
703 goto loop;
704
705 done:
706 /* Wakeup TXQ if its stopped earlier due to SQ full */
707 if (tx_done) {
708 netdev = nic->pnicvf->netdev;
709 txq = netdev_get_tx_queue(netdev,
710 nicvf_netdev_qidx(nic, cq_idx));
711 nic = nic->pnicvf;
712 if (netif_tx_queue_stopped(txq) && netif_carrier_ok(netdev)) {
713 netif_tx_start_queue(txq);
714 nic->drv_stats.txq_wake++;
715 if (netif_msg_tx_err(nic))
716 netdev_warn(netdev,
717 "%s: Transmit queue wakeup SQ%d\n",
718 netdev->name, cq_idx);
719 }
720 }
721
722 spin_unlock_bh(&cq->lock);
723 return work_done;
724 }
725
726 static int nicvf_poll(struct napi_struct *napi, int budget)
727 {
728 u64 cq_head;
729 int work_done = 0;
730 struct net_device *netdev = napi->dev;
731 struct nicvf *nic = netdev_priv(netdev);
732 struct nicvf_cq_poll *cq;
733
734 cq = container_of(napi, struct nicvf_cq_poll, napi);
735 work_done = nicvf_cq_intr_handler(netdev, cq->cq_idx, napi, budget);
736
737 if (work_done < budget) {
738 /* Slow packet rate, exit polling */
739 napi_complete(napi);
740 /* Re-enable interrupts */
741 cq_head = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_HEAD,
742 cq->cq_idx);
743 nicvf_clear_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
744 nicvf_queue_reg_write(nic, NIC_QSET_CQ_0_7_HEAD,
745 cq->cq_idx, cq_head);
746 nicvf_enable_intr(nic, NICVF_INTR_CQ, cq->cq_idx);
747 }
748 return work_done;
749 }
750
751 /* Qset error interrupt handler
752 *
753 * As of now only CQ errors are handled
754 */
755 static void nicvf_handle_qs_err(unsigned long data)
756 {
757 struct nicvf *nic = (struct nicvf *)data;
758 struct queue_set *qs = nic->qs;
759 int qidx;
760 u64 status;
761
762 netif_tx_disable(nic->netdev);
763
764 /* Check if it is CQ err */
765 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
766 status = nicvf_queue_reg_read(nic, NIC_QSET_CQ_0_7_STATUS,
767 qidx);
768 if (!(status & CQ_ERR_MASK))
769 continue;
770 /* Process already queued CQEs and reconfig CQ */
771 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
772 nicvf_sq_disable(nic, qidx);
773 nicvf_cq_intr_handler(nic->netdev, qidx, NULL, 0);
774 nicvf_cmp_queue_config(nic, qs, qidx, true);
775 nicvf_sq_free_used_descs(nic->netdev, &qs->sq[qidx], qidx);
776 nicvf_sq_enable(nic, &qs->sq[qidx], qidx);
777
778 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
779 }
780
781 netif_tx_start_all_queues(nic->netdev);
782 /* Re-enable Qset error interrupt */
783 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
784 }
785
786 static void nicvf_dump_intr_status(struct nicvf *nic)
787 {
788 if (netif_msg_intr(nic))
789 netdev_info(nic->netdev, "%s: interrupt status 0x%llx\n",
790 nic->netdev->name, nicvf_reg_read(nic, NIC_VF_INT));
791 }
792
793 static irqreturn_t nicvf_misc_intr_handler(int irq, void *nicvf_irq)
794 {
795 struct nicvf *nic = (struct nicvf *)nicvf_irq;
796 u64 intr;
797
798 nicvf_dump_intr_status(nic);
799
800 intr = nicvf_reg_read(nic, NIC_VF_INT);
801 /* Check for spurious interrupt */
802 if (!(intr & NICVF_INTR_MBOX_MASK))
803 return IRQ_HANDLED;
804
805 nicvf_handle_mbx_intr(nic);
806
807 return IRQ_HANDLED;
808 }
809
810 static irqreturn_t nicvf_intr_handler(int irq, void *cq_irq)
811 {
812 struct nicvf_cq_poll *cq_poll = (struct nicvf_cq_poll *)cq_irq;
813 struct nicvf *nic = cq_poll->nicvf;
814 int qidx = cq_poll->cq_idx;
815
816 nicvf_dump_intr_status(nic);
817
818 /* Disable interrupts */
819 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
820
821 /* Schedule NAPI */
822 napi_schedule(&cq_poll->napi);
823
824 /* Clear interrupt */
825 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
826
827 return IRQ_HANDLED;
828 }
829
830 static irqreturn_t nicvf_rbdr_intr_handler(int irq, void *nicvf_irq)
831 {
832 struct nicvf *nic = (struct nicvf *)nicvf_irq;
833 u8 qidx;
834
835
836 nicvf_dump_intr_status(nic);
837
838 /* Disable RBDR interrupt and schedule softirq */
839 for (qidx = 0; qidx < nic->qs->rbdr_cnt; qidx++) {
840 if (!nicvf_is_intr_enabled(nic, NICVF_INTR_RBDR, qidx))
841 continue;
842 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
843 tasklet_hi_schedule(&nic->rbdr_task);
844 /* Clear interrupt */
845 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
846 }
847
848 return IRQ_HANDLED;
849 }
850
851 static irqreturn_t nicvf_qs_err_intr_handler(int irq, void *nicvf_irq)
852 {
853 struct nicvf *nic = (struct nicvf *)nicvf_irq;
854
855 nicvf_dump_intr_status(nic);
856
857 /* Disable Qset err interrupt and schedule softirq */
858 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
859 tasklet_hi_schedule(&nic->qs_err_task);
860 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
861
862 return IRQ_HANDLED;
863 }
864
865 static int nicvf_enable_msix(struct nicvf *nic)
866 {
867 int ret, vec;
868
869 nic->num_vec = NIC_VF_MSIX_VECTORS;
870
871 for (vec = 0; vec < nic->num_vec; vec++)
872 nic->msix_entries[vec].entry = vec;
873
874 ret = pci_enable_msix(nic->pdev, nic->msix_entries, nic->num_vec);
875 if (ret) {
876 netdev_err(nic->netdev,
877 "Req for #%d msix vectors failed\n", nic->num_vec);
878 return 0;
879 }
880 nic->msix_enabled = 1;
881 return 1;
882 }
883
884 static void nicvf_disable_msix(struct nicvf *nic)
885 {
886 if (nic->msix_enabled) {
887 pci_disable_msix(nic->pdev);
888 nic->msix_enabled = 0;
889 nic->num_vec = 0;
890 }
891 }
892
893 static int nicvf_register_interrupts(struct nicvf *nic)
894 {
895 int irq, ret = 0;
896 int vector;
897
898 for_each_cq_irq(irq)
899 sprintf(nic->irq_name[irq], "NICVF%d CQ%d",
900 nic->vf_id, irq);
901
902 for_each_sq_irq(irq)
903 sprintf(nic->irq_name[irq], "NICVF%d SQ%d",
904 nic->vf_id, irq - NICVF_INTR_ID_SQ);
905
906 for_each_rbdr_irq(irq)
907 sprintf(nic->irq_name[irq], "NICVF%d RBDR%d",
908 nic->vf_id, irq - NICVF_INTR_ID_RBDR);
909
910 /* Register CQ interrupts */
911 for (irq = 0; irq < nic->qs->cq_cnt; irq++) {
912 vector = nic->msix_entries[irq].vector;
913 ret = request_irq(vector, nicvf_intr_handler,
914 0, nic->irq_name[irq], nic->napi[irq]);
915 if (ret)
916 goto err;
917 nic->irq_allocated[irq] = true;
918 }
919
920 /* Register RBDR interrupt */
921 for (irq = NICVF_INTR_ID_RBDR;
922 irq < (NICVF_INTR_ID_RBDR + nic->qs->rbdr_cnt); irq++) {
923 vector = nic->msix_entries[irq].vector;
924 ret = request_irq(vector, nicvf_rbdr_intr_handler,
925 0, nic->irq_name[irq], nic);
926 if (ret)
927 goto err;
928 nic->irq_allocated[irq] = true;
929 }
930
931 /* Register QS error interrupt */
932 sprintf(nic->irq_name[NICVF_INTR_ID_QS_ERR],
933 "NICVF%d Qset error", nic->vf_id);
934 irq = NICVF_INTR_ID_QS_ERR;
935 ret = request_irq(nic->msix_entries[irq].vector,
936 nicvf_qs_err_intr_handler,
937 0, nic->irq_name[irq], nic);
938 if (!ret)
939 nic->irq_allocated[irq] = true;
940
941 err:
942 if (ret)
943 netdev_err(nic->netdev, "request_irq failed, vector %d\n", irq);
944
945 return ret;
946 }
947
948 static void nicvf_unregister_interrupts(struct nicvf *nic)
949 {
950 int irq;
951
952 /* Free registered interrupts */
953 for (irq = 0; irq < nic->num_vec; irq++) {
954 if (!nic->irq_allocated[irq])
955 continue;
956
957 if (irq < NICVF_INTR_ID_SQ)
958 free_irq(nic->msix_entries[irq].vector, nic->napi[irq]);
959 else
960 free_irq(nic->msix_entries[irq].vector, nic);
961
962 nic->irq_allocated[irq] = false;
963 }
964
965 /* Disable MSI-X */
966 nicvf_disable_msix(nic);
967 }
968
969 /* Initialize MSIX vectors and register MISC interrupt.
970 * Send READY message to PF to check if its alive
971 */
972 static int nicvf_register_misc_interrupt(struct nicvf *nic)
973 {
974 int ret = 0;
975 int irq = NICVF_INTR_ID_MISC;
976
977 /* Return if mailbox interrupt is already registered */
978 if (nic->msix_enabled)
979 return 0;
980
981 /* Enable MSI-X */
982 if (!nicvf_enable_msix(nic))
983 return 1;
984
985 sprintf(nic->irq_name[irq], "%s Mbox", "NICVF");
986 /* Register Misc interrupt */
987 ret = request_irq(nic->msix_entries[irq].vector,
988 nicvf_misc_intr_handler, 0, nic->irq_name[irq], nic);
989
990 if (ret)
991 return ret;
992 nic->irq_allocated[irq] = true;
993
994 /* Enable mailbox interrupt */
995 nicvf_enable_intr(nic, NICVF_INTR_MBOX, 0);
996
997 /* Check if VF is able to communicate with PF */
998 if (!nicvf_check_pf_ready(nic)) {
999 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
1000 nicvf_unregister_interrupts(nic);
1001 return 1;
1002 }
1003
1004 return 0;
1005 }
1006
1007 static netdev_tx_t nicvf_xmit(struct sk_buff *skb, struct net_device *netdev)
1008 {
1009 struct nicvf *nic = netdev_priv(netdev);
1010 int qid = skb_get_queue_mapping(skb);
1011 struct netdev_queue *txq = netdev_get_tx_queue(netdev, qid);
1012
1013 /* Check for minimum packet length */
1014 if (skb->len <= ETH_HLEN) {
1015 dev_kfree_skb(skb);
1016 return NETDEV_TX_OK;
1017 }
1018
1019 if (!netif_tx_queue_stopped(txq) && !nicvf_sq_append_skb(nic, skb)) {
1020 netif_tx_stop_queue(txq);
1021 nic->drv_stats.txq_stop++;
1022 if (netif_msg_tx_err(nic))
1023 netdev_warn(netdev,
1024 "%s: Transmit ring full, stopping SQ%d\n",
1025 netdev->name, qid);
1026 return NETDEV_TX_BUSY;
1027 }
1028
1029 return NETDEV_TX_OK;
1030 }
1031
1032 static inline void nicvf_free_cq_poll(struct nicvf *nic)
1033 {
1034 struct nicvf_cq_poll *cq_poll;
1035 int qidx;
1036
1037 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
1038 cq_poll = nic->napi[qidx];
1039 if (!cq_poll)
1040 continue;
1041 nic->napi[qidx] = NULL;
1042 kfree(cq_poll);
1043 }
1044 }
1045
1046 int nicvf_stop(struct net_device *netdev)
1047 {
1048 int irq, qidx;
1049 struct nicvf *nic = netdev_priv(netdev);
1050 struct queue_set *qs = nic->qs;
1051 struct nicvf_cq_poll *cq_poll = NULL;
1052 union nic_mbx mbx = {};
1053
1054 mbx.msg.msg = NIC_MBOX_MSG_SHUTDOWN;
1055 nicvf_send_msg_to_pf(nic, &mbx);
1056
1057 netif_carrier_off(netdev);
1058 netif_tx_stop_all_queues(nic->netdev);
1059
1060 /* Teardown secondary qsets first */
1061 if (!nic->sqs_mode) {
1062 for (qidx = 0; qidx < nic->sqs_count; qidx++) {
1063 if (!nic->snicvf[qidx])
1064 continue;
1065 nicvf_stop(nic->snicvf[qidx]->netdev);
1066 nic->snicvf[qidx] = NULL;
1067 }
1068 }
1069
1070 /* Disable RBDR & QS error interrupts */
1071 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++) {
1072 nicvf_disable_intr(nic, NICVF_INTR_RBDR, qidx);
1073 nicvf_clear_intr(nic, NICVF_INTR_RBDR, qidx);
1074 }
1075 nicvf_disable_intr(nic, NICVF_INTR_QS_ERR, 0);
1076 nicvf_clear_intr(nic, NICVF_INTR_QS_ERR, 0);
1077
1078 /* Wait for pending IRQ handlers to finish */
1079 for (irq = 0; irq < nic->num_vec; irq++)
1080 synchronize_irq(nic->msix_entries[irq].vector);
1081
1082 tasklet_kill(&nic->rbdr_task);
1083 tasklet_kill(&nic->qs_err_task);
1084 if (nic->rb_work_scheduled)
1085 cancel_delayed_work_sync(&nic->rbdr_work);
1086
1087 for (qidx = 0; qidx < nic->qs->cq_cnt; qidx++) {
1088 cq_poll = nic->napi[qidx];
1089 if (!cq_poll)
1090 continue;
1091 napi_synchronize(&cq_poll->napi);
1092 /* CQ intr is enabled while napi_complete,
1093 * so disable it now
1094 */
1095 nicvf_disable_intr(nic, NICVF_INTR_CQ, qidx);
1096 nicvf_clear_intr(nic, NICVF_INTR_CQ, qidx);
1097 napi_disable(&cq_poll->napi);
1098 netif_napi_del(&cq_poll->napi);
1099 }
1100
1101 netif_tx_disable(netdev);
1102
1103 /* Free resources */
1104 nicvf_config_data_transfer(nic, false);
1105
1106 /* Disable HW Qset */
1107 nicvf_qset_config(nic, false);
1108
1109 /* disable mailbox interrupt */
1110 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
1111
1112 nicvf_unregister_interrupts(nic);
1113
1114 nicvf_free_cq_poll(nic);
1115
1116 /* Clear multiqset info */
1117 nic->pnicvf = nic;
1118 nic->sqs_count = 0;
1119
1120 return 0;
1121 }
1122
1123 int nicvf_open(struct net_device *netdev)
1124 {
1125 int err, qidx;
1126 struct nicvf *nic = netdev_priv(netdev);
1127 struct queue_set *qs = nic->qs;
1128 struct nicvf_cq_poll *cq_poll = NULL;
1129
1130 nic->mtu = netdev->mtu;
1131
1132 netif_carrier_off(netdev);
1133
1134 err = nicvf_register_misc_interrupt(nic);
1135 if (err)
1136 return err;
1137
1138 /* Register NAPI handler for processing CQEs */
1139 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
1140 cq_poll = kzalloc(sizeof(*cq_poll), GFP_KERNEL);
1141 if (!cq_poll) {
1142 err = -ENOMEM;
1143 goto napi_del;
1144 }
1145 cq_poll->cq_idx = qidx;
1146 cq_poll->nicvf = nic;
1147 netif_napi_add(netdev, &cq_poll->napi, nicvf_poll,
1148 NAPI_POLL_WEIGHT);
1149 napi_enable(&cq_poll->napi);
1150 nic->napi[qidx] = cq_poll;
1151 }
1152
1153 /* Check if we got MAC address from PF or else generate a radom MAC */
1154 if (is_zero_ether_addr(netdev->dev_addr)) {
1155 eth_hw_addr_random(netdev);
1156 nicvf_hw_set_mac_addr(nic, netdev);
1157 }
1158
1159 if (nic->set_mac_pending) {
1160 nic->set_mac_pending = false;
1161 nicvf_hw_set_mac_addr(nic, netdev);
1162 }
1163
1164 /* Init tasklet for handling Qset err interrupt */
1165 tasklet_init(&nic->qs_err_task, nicvf_handle_qs_err,
1166 (unsigned long)nic);
1167
1168 /* Init RBDR tasklet which will refill RBDR */
1169 tasklet_init(&nic->rbdr_task, nicvf_rbdr_task,
1170 (unsigned long)nic);
1171 INIT_DELAYED_WORK(&nic->rbdr_work, nicvf_rbdr_work);
1172
1173 /* Configure CPI alorithm */
1174 nic->cpi_alg = cpi_alg;
1175 if (!nic->sqs_mode)
1176 nicvf_config_cpi(nic);
1177
1178 nicvf_request_sqs(nic);
1179 if (nic->sqs_mode)
1180 nicvf_get_primary_vf_struct(nic);
1181
1182 /* Configure receive side scaling */
1183 if (!nic->sqs_mode)
1184 nicvf_rss_init(nic);
1185
1186 err = nicvf_register_interrupts(nic);
1187 if (err)
1188 goto cleanup;
1189
1190 /* Initialize the queues */
1191 err = nicvf_init_resources(nic);
1192 if (err)
1193 goto cleanup;
1194
1195 /* Make sure queue initialization is written */
1196 wmb();
1197
1198 nicvf_reg_write(nic, NIC_VF_INT, -1);
1199 /* Enable Qset err interrupt */
1200 nicvf_enable_intr(nic, NICVF_INTR_QS_ERR, 0);
1201
1202 /* Enable completion queue interrupt */
1203 for (qidx = 0; qidx < qs->cq_cnt; qidx++)
1204 nicvf_enable_intr(nic, NICVF_INTR_CQ, qidx);
1205
1206 /* Enable RBDR threshold interrupt */
1207 for (qidx = 0; qidx < qs->rbdr_cnt; qidx++)
1208 nicvf_enable_intr(nic, NICVF_INTR_RBDR, qidx);
1209
1210 nic->drv_stats.txq_stop = 0;
1211 nic->drv_stats.txq_wake = 0;
1212
1213 netif_carrier_on(netdev);
1214 netif_tx_start_all_queues(netdev);
1215
1216 return 0;
1217 cleanup:
1218 nicvf_disable_intr(nic, NICVF_INTR_MBOX, 0);
1219 nicvf_unregister_interrupts(nic);
1220 tasklet_kill(&nic->qs_err_task);
1221 tasklet_kill(&nic->rbdr_task);
1222 napi_del:
1223 for (qidx = 0; qidx < qs->cq_cnt; qidx++) {
1224 cq_poll = nic->napi[qidx];
1225 if (!cq_poll)
1226 continue;
1227 napi_disable(&cq_poll->napi);
1228 netif_napi_del(&cq_poll->napi);
1229 }
1230 nicvf_free_cq_poll(nic);
1231 return err;
1232 }
1233
1234 static int nicvf_update_hw_max_frs(struct nicvf *nic, int mtu)
1235 {
1236 union nic_mbx mbx = {};
1237
1238 mbx.frs.msg = NIC_MBOX_MSG_SET_MAX_FRS;
1239 mbx.frs.max_frs = mtu;
1240 mbx.frs.vf_id = nic->vf_id;
1241
1242 return nicvf_send_msg_to_pf(nic, &mbx);
1243 }
1244
1245 static int nicvf_change_mtu(struct net_device *netdev, int new_mtu)
1246 {
1247 struct nicvf *nic = netdev_priv(netdev);
1248
1249 if (new_mtu > NIC_HW_MAX_FRS)
1250 return -EINVAL;
1251
1252 if (new_mtu < NIC_HW_MIN_FRS)
1253 return -EINVAL;
1254
1255 if (nicvf_update_hw_max_frs(nic, new_mtu))
1256 return -EINVAL;
1257 netdev->mtu = new_mtu;
1258 nic->mtu = new_mtu;
1259
1260 return 0;
1261 }
1262
1263 static int nicvf_set_mac_address(struct net_device *netdev, void *p)
1264 {
1265 struct sockaddr *addr = p;
1266 struct nicvf *nic = netdev_priv(netdev);
1267
1268 if (!is_valid_ether_addr(addr->sa_data))
1269 return -EADDRNOTAVAIL;
1270
1271 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1272
1273 if (nic->msix_enabled) {
1274 if (nicvf_hw_set_mac_addr(nic, netdev))
1275 return -EBUSY;
1276 } else {
1277 nic->set_mac_pending = true;
1278 }
1279
1280 return 0;
1281 }
1282
1283 void nicvf_update_lmac_stats(struct nicvf *nic)
1284 {
1285 int stat = 0;
1286 union nic_mbx mbx = {};
1287
1288 if (!netif_running(nic->netdev))
1289 return;
1290
1291 mbx.bgx_stats.msg = NIC_MBOX_MSG_BGX_STATS;
1292 mbx.bgx_stats.vf_id = nic->vf_id;
1293 /* Rx stats */
1294 mbx.bgx_stats.rx = 1;
1295 while (stat < BGX_RX_STATS_COUNT) {
1296 mbx.bgx_stats.idx = stat;
1297 if (nicvf_send_msg_to_pf(nic, &mbx))
1298 return;
1299 stat++;
1300 }
1301
1302 stat = 0;
1303
1304 /* Tx stats */
1305 mbx.bgx_stats.rx = 0;
1306 while (stat < BGX_TX_STATS_COUNT) {
1307 mbx.bgx_stats.idx = stat;
1308 if (nicvf_send_msg_to_pf(nic, &mbx))
1309 return;
1310 stat++;
1311 }
1312 }
1313
1314 void nicvf_update_stats(struct nicvf *nic)
1315 {
1316 int qidx;
1317 struct nicvf_hw_stats *stats = &nic->hw_stats;
1318 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1319 struct queue_set *qs = nic->qs;
1320
1321 #define GET_RX_STATS(reg) \
1322 nicvf_reg_read(nic, NIC_VNIC_RX_STAT_0_13 | (reg << 3))
1323 #define GET_TX_STATS(reg) \
1324 nicvf_reg_read(nic, NIC_VNIC_TX_STAT_0_4 | (reg << 3))
1325
1326 stats->rx_bytes = GET_RX_STATS(RX_OCTS);
1327 stats->rx_ucast_frames = GET_RX_STATS(RX_UCAST);
1328 stats->rx_bcast_frames = GET_RX_STATS(RX_BCAST);
1329 stats->rx_mcast_frames = GET_RX_STATS(RX_MCAST);
1330 stats->rx_fcs_errors = GET_RX_STATS(RX_FCS);
1331 stats->rx_l2_errors = GET_RX_STATS(RX_L2ERR);
1332 stats->rx_drop_red = GET_RX_STATS(RX_RED);
1333 stats->rx_drop_red_bytes = GET_RX_STATS(RX_RED_OCTS);
1334 stats->rx_drop_overrun = GET_RX_STATS(RX_ORUN);
1335 stats->rx_drop_overrun_bytes = GET_RX_STATS(RX_ORUN_OCTS);
1336 stats->rx_drop_bcast = GET_RX_STATS(RX_DRP_BCAST);
1337 stats->rx_drop_mcast = GET_RX_STATS(RX_DRP_MCAST);
1338 stats->rx_drop_l3_bcast = GET_RX_STATS(RX_DRP_L3BCAST);
1339 stats->rx_drop_l3_mcast = GET_RX_STATS(RX_DRP_L3MCAST);
1340
1341 stats->tx_bytes_ok = GET_TX_STATS(TX_OCTS);
1342 stats->tx_ucast_frames_ok = GET_TX_STATS(TX_UCAST);
1343 stats->tx_bcast_frames_ok = GET_TX_STATS(TX_BCAST);
1344 stats->tx_mcast_frames_ok = GET_TX_STATS(TX_MCAST);
1345 stats->tx_drops = GET_TX_STATS(TX_DROP);
1346
1347 drv_stats->tx_frames_ok = stats->tx_ucast_frames_ok +
1348 stats->tx_bcast_frames_ok +
1349 stats->tx_mcast_frames_ok;
1350 drv_stats->rx_drops = stats->rx_drop_red +
1351 stats->rx_drop_overrun;
1352 drv_stats->tx_drops = stats->tx_drops;
1353
1354 /* Update RQ and SQ stats */
1355 for (qidx = 0; qidx < qs->rq_cnt; qidx++)
1356 nicvf_update_rq_stats(nic, qidx);
1357 for (qidx = 0; qidx < qs->sq_cnt; qidx++)
1358 nicvf_update_sq_stats(nic, qidx);
1359 }
1360
1361 static struct rtnl_link_stats64 *nicvf_get_stats64(struct net_device *netdev,
1362 struct rtnl_link_stats64 *stats)
1363 {
1364 struct nicvf *nic = netdev_priv(netdev);
1365 struct nicvf_hw_stats *hw_stats = &nic->hw_stats;
1366 struct nicvf_drv_stats *drv_stats = &nic->drv_stats;
1367
1368 nicvf_update_stats(nic);
1369
1370 stats->rx_bytes = hw_stats->rx_bytes;
1371 stats->rx_packets = drv_stats->rx_frames_ok;
1372 stats->rx_dropped = drv_stats->rx_drops;
1373 stats->multicast = hw_stats->rx_mcast_frames;
1374
1375 stats->tx_bytes = hw_stats->tx_bytes_ok;
1376 stats->tx_packets = drv_stats->tx_frames_ok;
1377 stats->tx_dropped = drv_stats->tx_drops;
1378
1379 return stats;
1380 }
1381
1382 static void nicvf_tx_timeout(struct net_device *dev)
1383 {
1384 struct nicvf *nic = netdev_priv(dev);
1385
1386 if (netif_msg_tx_err(nic))
1387 netdev_warn(dev, "%s: Transmit timed out, resetting\n",
1388 dev->name);
1389
1390 schedule_work(&nic->reset_task);
1391 }
1392
1393 static void nicvf_reset_task(struct work_struct *work)
1394 {
1395 struct nicvf *nic;
1396
1397 nic = container_of(work, struct nicvf, reset_task);
1398
1399 if (!netif_running(nic->netdev))
1400 return;
1401
1402 nicvf_stop(nic->netdev);
1403 nicvf_open(nic->netdev);
1404 nic->netdev->trans_start = jiffies;
1405 }
1406
1407 static int nicvf_set_features(struct net_device *netdev,
1408 netdev_features_t features)
1409 {
1410 struct nicvf *nic = netdev_priv(netdev);
1411 netdev_features_t changed = features ^ netdev->features;
1412
1413 if (changed & NETIF_F_HW_VLAN_CTAG_RX)
1414 nicvf_config_vlan_stripping(nic, features);
1415
1416 return 0;
1417 }
1418
1419 static const struct net_device_ops nicvf_netdev_ops = {
1420 .ndo_open = nicvf_open,
1421 .ndo_stop = nicvf_stop,
1422 .ndo_start_xmit = nicvf_xmit,
1423 .ndo_change_mtu = nicvf_change_mtu,
1424 .ndo_set_mac_address = nicvf_set_mac_address,
1425 .ndo_get_stats64 = nicvf_get_stats64,
1426 .ndo_tx_timeout = nicvf_tx_timeout,
1427 .ndo_set_features = nicvf_set_features,
1428 };
1429
1430 static int nicvf_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1431 {
1432 struct device *dev = &pdev->dev;
1433 struct net_device *netdev;
1434 struct nicvf *nic;
1435 int err, qcount;
1436
1437 err = pci_enable_device(pdev);
1438 if (err) {
1439 dev_err(dev, "Failed to enable PCI device\n");
1440 return err;
1441 }
1442
1443 err = pci_request_regions(pdev, DRV_NAME);
1444 if (err) {
1445 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1446 goto err_disable_device;
1447 }
1448
1449 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(48));
1450 if (err) {
1451 dev_err(dev, "Unable to get usable DMA configuration\n");
1452 goto err_release_regions;
1453 }
1454
1455 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(48));
1456 if (err) {
1457 dev_err(dev, "unable to get 48-bit DMA for consistent allocations\n");
1458 goto err_release_regions;
1459 }
1460
1461 qcount = MAX_CMP_QUEUES_PER_QS;
1462
1463 /* Restrict multiqset support only for host bound VFs */
1464 if (pdev->is_virtfn) {
1465 /* Set max number of queues per VF */
1466 qcount = roundup(num_online_cpus(), MAX_CMP_QUEUES_PER_QS);
1467 qcount = min(qcount,
1468 (MAX_SQS_PER_VF + 1) * MAX_CMP_QUEUES_PER_QS);
1469 }
1470
1471 netdev = alloc_etherdev_mqs(sizeof(struct nicvf), qcount, qcount);
1472 if (!netdev) {
1473 err = -ENOMEM;
1474 goto err_release_regions;
1475 }
1476
1477 pci_set_drvdata(pdev, netdev);
1478
1479 SET_NETDEV_DEV(netdev, &pdev->dev);
1480
1481 nic = netdev_priv(netdev);
1482 nic->netdev = netdev;
1483 nic->pdev = pdev;
1484 nic->pnicvf = nic;
1485 nic->max_queues = qcount;
1486
1487 /* MAP VF's configuration registers */
1488 nic->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1489 if (!nic->reg_base) {
1490 dev_err(dev, "Cannot map config register space, aborting\n");
1491 err = -ENOMEM;
1492 goto err_free_netdev;
1493 }
1494
1495 err = nicvf_set_qset_resources(nic);
1496 if (err)
1497 goto err_free_netdev;
1498
1499 /* Check if PF is alive and get MAC address for this VF */
1500 err = nicvf_register_misc_interrupt(nic);
1501 if (err)
1502 goto err_free_netdev;
1503
1504 nicvf_send_vf_struct(nic);
1505
1506 /* Check if this VF is in QS only mode */
1507 if (nic->sqs_mode)
1508 return 0;
1509
1510 err = nicvf_set_real_num_queues(netdev, nic->tx_queues, nic->rx_queues);
1511 if (err)
1512 goto err_unregister_interrupts;
1513
1514 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
1515 NETIF_F_TSO | NETIF_F_GRO |
1516 NETIF_F_HW_VLAN_CTAG_RX);
1517
1518 netdev->hw_features |= NETIF_F_RXHASH;
1519
1520 netdev->features |= netdev->hw_features;
1521
1522 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO;
1523
1524 netdev->netdev_ops = &nicvf_netdev_ops;
1525 netdev->watchdog_timeo = NICVF_TX_TIMEOUT;
1526
1527 INIT_WORK(&nic->reset_task, nicvf_reset_task);
1528
1529 err = register_netdev(netdev);
1530 if (err) {
1531 dev_err(dev, "Failed to register netdevice\n");
1532 goto err_unregister_interrupts;
1533 }
1534
1535 nic->msg_enable = debug;
1536
1537 nicvf_set_ethtool_ops(netdev);
1538
1539 return 0;
1540
1541 err_unregister_interrupts:
1542 nicvf_unregister_interrupts(nic);
1543 err_free_netdev:
1544 pci_set_drvdata(pdev, NULL);
1545 free_netdev(netdev);
1546 err_release_regions:
1547 pci_release_regions(pdev);
1548 err_disable_device:
1549 pci_disable_device(pdev);
1550 return err;
1551 }
1552
1553 static void nicvf_remove(struct pci_dev *pdev)
1554 {
1555 struct net_device *netdev = pci_get_drvdata(pdev);
1556 struct nicvf *nic = netdev_priv(netdev);
1557 struct net_device *pnetdev = nic->pnicvf->netdev;
1558
1559 /* Check if this Qset is assigned to different VF.
1560 * If yes, clean primary and all secondary Qsets.
1561 */
1562 if (pnetdev && (pnetdev->reg_state == NETREG_REGISTERED))
1563 unregister_netdev(pnetdev);
1564 nicvf_unregister_interrupts(nic);
1565 pci_set_drvdata(pdev, NULL);
1566 free_netdev(netdev);
1567 pci_release_regions(pdev);
1568 pci_disable_device(pdev);
1569 }
1570
1571 static void nicvf_shutdown(struct pci_dev *pdev)
1572 {
1573 nicvf_remove(pdev);
1574 }
1575
1576 static struct pci_driver nicvf_driver = {
1577 .name = DRV_NAME,
1578 .id_table = nicvf_id_table,
1579 .probe = nicvf_probe,
1580 .remove = nicvf_remove,
1581 .shutdown = nicvf_shutdown,
1582 };
1583
1584 static int __init nicvf_init_module(void)
1585 {
1586 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1587
1588 return pci_register_driver(&nicvf_driver);
1589 }
1590
1591 static void __exit nicvf_cleanup_module(void)
1592 {
1593 pci_unregister_driver(&nicvf_driver);
1594 }
1595
1596 module_init(nicvf_init_module);
1597 module_exit(nicvf_cleanup_module);
Linux kernel - Deliverables
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