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regmap: irq: Add support to call client specific pre/post interrupt service
[deliverable/linux.git] / drivers / net / ethernet / cavium / thunder / thunder_bgx.c
1 /*
2 * Copyright (C) 2015 Cavium, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of version 2 of the GNU General Public License
6 * as published by the Free Software Foundation.
7 */
8
9 #include <linux/acpi.h>
10 #include <linux/module.h>
11 #include <linux/interrupt.h>
12 #include <linux/pci.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/phy.h>
16 #include <linux/of.h>
17 #include <linux/of_mdio.h>
18 #include <linux/of_net.h>
19
20 #include "nic_reg.h"
21 #include "nic.h"
22 #include "thunder_bgx.h"
23
24 #define DRV_NAME "thunder-BGX"
25 #define DRV_VERSION "1.0"
26
27 struct lmac {
28 struct bgx *bgx;
29 int dmac;
30 u8 mac[ETH_ALEN];
31 bool link_up;
32 int lmacid; /* ID within BGX */
33 int lmacid_bd; /* ID on board */
34 struct net_device netdev;
35 struct phy_device *phydev;
36 unsigned int last_duplex;
37 unsigned int last_link;
38 unsigned int last_speed;
39 bool is_sgmii;
40 struct delayed_work dwork;
41 struct workqueue_struct *check_link;
42 };
43
44 struct bgx {
45 u8 bgx_id;
46 u8 qlm_mode;
47 struct lmac lmac[MAX_LMAC_PER_BGX];
48 int lmac_count;
49 int lmac_type;
50 int lane_to_sds;
51 int use_training;
52 void __iomem *reg_base;
53 struct pci_dev *pdev;
54 };
55
56 static struct bgx *bgx_vnic[MAX_BGX_THUNDER];
57 static int lmac_count; /* Total no of LMACs in system */
58
59 static int bgx_xaui_check_link(struct lmac *lmac);
60
61 /* Supported devices */
62 static const struct pci_device_id bgx_id_table[] = {
63 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVICE_ID_THUNDER_BGX) },
64 { 0, } /* end of table */
65 };
66
67 MODULE_AUTHOR("Cavium Inc");
68 MODULE_DESCRIPTION("Cavium Thunder BGX/MAC Driver");
69 MODULE_LICENSE("GPL v2");
70 MODULE_VERSION(DRV_VERSION);
71 MODULE_DEVICE_TABLE(pci, bgx_id_table);
72
73 /* The Cavium ThunderX network controller can *only* be found in SoCs
74 * containing the ThunderX ARM64 CPU implementation. All accesses to the device
75 * registers on this platform are implicitly strongly ordered with respect
76 * to memory accesses. So writeq_relaxed() and readq_relaxed() are safe to use
77 * with no memory barriers in this driver. The readq()/writeq() functions add
78 * explicit ordering operation which in this case are redundant, and only
79 * add overhead.
80 */
81
82 /* Register read/write APIs */
83 static u64 bgx_reg_read(struct bgx *bgx, u8 lmac, u64 offset)
84 {
85 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
86
87 return readq_relaxed(addr);
88 }
89
90 static void bgx_reg_write(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
91 {
92 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
93
94 writeq_relaxed(val, addr);
95 }
96
97 static void bgx_reg_modify(struct bgx *bgx, u8 lmac, u64 offset, u64 val)
98 {
99 void __iomem *addr = bgx->reg_base + ((u32)lmac << 20) + offset;
100
101 writeq_relaxed(val | readq_relaxed(addr), addr);
102 }
103
104 static int bgx_poll_reg(struct bgx *bgx, u8 lmac, u64 reg, u64 mask, bool zero)
105 {
106 int timeout = 100;
107 u64 reg_val;
108
109 while (timeout) {
110 reg_val = bgx_reg_read(bgx, lmac, reg);
111 if (zero && !(reg_val & mask))
112 return 0;
113 if (!zero && (reg_val & mask))
114 return 0;
115 usleep_range(1000, 2000);
116 timeout--;
117 }
118 return 1;
119 }
120
121 /* Return number of BGX present in HW */
122 unsigned bgx_get_map(int node)
123 {
124 int i;
125 unsigned map = 0;
126
127 for (i = 0; i < MAX_BGX_PER_CN88XX; i++) {
128 if (bgx_vnic[(node * MAX_BGX_PER_CN88XX) + i])
129 map |= (1 << i);
130 }
131
132 return map;
133 }
134 EXPORT_SYMBOL(bgx_get_map);
135
136 /* Return number of LMAC configured for this BGX */
137 int bgx_get_lmac_count(int node, int bgx_idx)
138 {
139 struct bgx *bgx;
140
141 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
142 if (bgx)
143 return bgx->lmac_count;
144
145 return 0;
146 }
147 EXPORT_SYMBOL(bgx_get_lmac_count);
148
149 /* Returns the current link status of LMAC */
150 void bgx_get_lmac_link_state(int node, int bgx_idx, int lmacid, void *status)
151 {
152 struct bgx_link_status *link = (struct bgx_link_status *)status;
153 struct bgx *bgx;
154 struct lmac *lmac;
155
156 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
157 if (!bgx)
158 return;
159
160 lmac = &bgx->lmac[lmacid];
161 link->link_up = lmac->link_up;
162 link->duplex = lmac->last_duplex;
163 link->speed = lmac->last_speed;
164 }
165 EXPORT_SYMBOL(bgx_get_lmac_link_state);
166
167 const u8 *bgx_get_lmac_mac(int node, int bgx_idx, int lmacid)
168 {
169 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
170
171 if (bgx)
172 return bgx->lmac[lmacid].mac;
173
174 return NULL;
175 }
176 EXPORT_SYMBOL(bgx_get_lmac_mac);
177
178 void bgx_set_lmac_mac(int node, int bgx_idx, int lmacid, const u8 *mac)
179 {
180 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
181
182 if (!bgx)
183 return;
184
185 ether_addr_copy(bgx->lmac[lmacid].mac, mac);
186 }
187 EXPORT_SYMBOL(bgx_set_lmac_mac);
188
189 void bgx_lmac_rx_tx_enable(int node, int bgx_idx, int lmacid, bool enable)
190 {
191 struct bgx *bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
192 u64 cfg;
193
194 if (!bgx)
195 return;
196
197 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
198 if (enable)
199 cfg |= CMR_PKT_RX_EN | CMR_PKT_TX_EN;
200 else
201 cfg &= ~(CMR_PKT_RX_EN | CMR_PKT_TX_EN);
202 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
203 }
204 EXPORT_SYMBOL(bgx_lmac_rx_tx_enable);
205
206 static void bgx_sgmii_change_link_state(struct lmac *lmac)
207 {
208 struct bgx *bgx = lmac->bgx;
209 u64 cmr_cfg;
210 u64 port_cfg = 0;
211 u64 misc_ctl = 0;
212
213 cmr_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_CMRX_CFG);
214 cmr_cfg &= ~CMR_EN;
215 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
216
217 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
218 misc_ctl = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL);
219
220 if (lmac->link_up) {
221 misc_ctl &= ~PCS_MISC_CTL_GMX_ENO;
222 port_cfg &= ~GMI_PORT_CFG_DUPLEX;
223 port_cfg |= (lmac->last_duplex << 2);
224 } else {
225 misc_ctl |= PCS_MISC_CTL_GMX_ENO;
226 }
227
228 switch (lmac->last_speed) {
229 case 10:
230 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
231 port_cfg |= GMI_PORT_CFG_SPEED_MSB; /* speed_msb 1 */
232 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
233 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
234 misc_ctl |= 50; /* samp_pt */
235 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
236 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
237 break;
238 case 100:
239 port_cfg &= ~GMI_PORT_CFG_SPEED; /* speed 0 */
240 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
241 port_cfg &= ~GMI_PORT_CFG_SLOT_TIME; /* slottime 0 */
242 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
243 misc_ctl |= 5; /* samp_pt */
244 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 64);
245 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_BURST, 0);
246 break;
247 case 1000:
248 port_cfg |= GMI_PORT_CFG_SPEED; /* speed 1 */
249 port_cfg &= ~GMI_PORT_CFG_SPEED_MSB; /* speed_msb 0 */
250 port_cfg |= GMI_PORT_CFG_SLOT_TIME; /* slottime 1 */
251 misc_ctl &= ~PCS_MISC_CTL_SAMP_PT_MASK;
252 misc_ctl |= 1; /* samp_pt */
253 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_TXX_SLOT, 512);
254 if (lmac->last_duplex)
255 bgx_reg_write(bgx, lmac->lmacid,
256 BGX_GMP_GMI_TXX_BURST, 0);
257 else
258 bgx_reg_write(bgx, lmac->lmacid,
259 BGX_GMP_GMI_TXX_BURST, 8192);
260 break;
261 default:
262 break;
263 }
264 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_PCS_MISCX_CTL, misc_ctl);
265 bgx_reg_write(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG, port_cfg);
266
267 port_cfg = bgx_reg_read(bgx, lmac->lmacid, BGX_GMP_GMI_PRTX_CFG);
268
269 /* renable lmac */
270 cmr_cfg |= CMR_EN;
271 bgx_reg_write(bgx, lmac->lmacid, BGX_CMRX_CFG, cmr_cfg);
272 }
273
274 static void bgx_lmac_handler(struct net_device *netdev)
275 {
276 struct lmac *lmac = container_of(netdev, struct lmac, netdev);
277 struct phy_device *phydev;
278 int link_changed = 0;
279
280 if (!lmac)
281 return;
282
283 phydev = lmac->phydev;
284
285 if (!phydev->link && lmac->last_link)
286 link_changed = -1;
287
288 if (phydev->link &&
289 (lmac->last_duplex != phydev->duplex ||
290 lmac->last_link != phydev->link ||
291 lmac->last_speed != phydev->speed)) {
292 link_changed = 1;
293 }
294
295 lmac->last_link = phydev->link;
296 lmac->last_speed = phydev->speed;
297 lmac->last_duplex = phydev->duplex;
298
299 if (!link_changed)
300 return;
301
302 if (link_changed > 0)
303 lmac->link_up = true;
304 else
305 lmac->link_up = false;
306
307 if (lmac->is_sgmii)
308 bgx_sgmii_change_link_state(lmac);
309 else
310 bgx_xaui_check_link(lmac);
311 }
312
313 u64 bgx_get_rx_stats(int node, int bgx_idx, int lmac, int idx)
314 {
315 struct bgx *bgx;
316
317 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
318 if (!bgx)
319 return 0;
320
321 if (idx > 8)
322 lmac = 0;
323 return bgx_reg_read(bgx, lmac, BGX_CMRX_RX_STAT0 + (idx * 8));
324 }
325 EXPORT_SYMBOL(bgx_get_rx_stats);
326
327 u64 bgx_get_tx_stats(int node, int bgx_idx, int lmac, int idx)
328 {
329 struct bgx *bgx;
330
331 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
332 if (!bgx)
333 return 0;
334
335 return bgx_reg_read(bgx, lmac, BGX_CMRX_TX_STAT0 + (idx * 8));
336 }
337 EXPORT_SYMBOL(bgx_get_tx_stats);
338
339 static void bgx_flush_dmac_addrs(struct bgx *bgx, int lmac)
340 {
341 u64 offset;
342
343 while (bgx->lmac[lmac].dmac > 0) {
344 offset = ((bgx->lmac[lmac].dmac - 1) * sizeof(u64)) +
345 (lmac * MAX_DMAC_PER_LMAC * sizeof(u64));
346 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + offset, 0);
347 bgx->lmac[lmac].dmac--;
348 }
349 }
350
351 /* Configure BGX LMAC in internal loopback mode */
352 void bgx_lmac_internal_loopback(int node, int bgx_idx,
353 int lmac_idx, bool enable)
354 {
355 struct bgx *bgx;
356 struct lmac *lmac;
357 u64 cfg;
358
359 bgx = bgx_vnic[(node * MAX_BGX_PER_CN88XX) + bgx_idx];
360 if (!bgx)
361 return;
362
363 lmac = &bgx->lmac[lmac_idx];
364 if (lmac->is_sgmii) {
365 cfg = bgx_reg_read(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL);
366 if (enable)
367 cfg |= PCS_MRX_CTL_LOOPBACK1;
368 else
369 cfg &= ~PCS_MRX_CTL_LOOPBACK1;
370 bgx_reg_write(bgx, lmac_idx, BGX_GMP_PCS_MRX_CTL, cfg);
371 } else {
372 cfg = bgx_reg_read(bgx, lmac_idx, BGX_SPUX_CONTROL1);
373 if (enable)
374 cfg |= SPU_CTL_LOOPBACK;
375 else
376 cfg &= ~SPU_CTL_LOOPBACK;
377 bgx_reg_write(bgx, lmac_idx, BGX_SPUX_CONTROL1, cfg);
378 }
379 }
380 EXPORT_SYMBOL(bgx_lmac_internal_loopback);
381
382 static int bgx_lmac_sgmii_init(struct bgx *bgx, int lmacid)
383 {
384 u64 cfg;
385
386 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_THRESH, 0x30);
387 /* max packet size */
388 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_RXX_JABBER, MAX_FRAME_SIZE);
389
390 /* Disable frame alignment if using preamble */
391 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
392 if (cfg & 1)
393 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_SGMII_CTL, 0);
394
395 /* Enable lmac */
396 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
397
398 /* PCS reset */
399 bgx_reg_modify(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, PCS_MRX_CTL_RESET);
400 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_CTL,
401 PCS_MRX_CTL_RESET, true)) {
402 dev_err(&bgx->pdev->dev, "BGX PCS reset not completed\n");
403 return -1;
404 }
405
406 /* power down, reset autoneg, autoneg enable */
407 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_PCS_MRX_CTL);
408 cfg &= ~PCS_MRX_CTL_PWR_DN;
409 cfg |= (PCS_MRX_CTL_RST_AN | PCS_MRX_CTL_AN_EN);
410 bgx_reg_write(bgx, lmacid, BGX_GMP_PCS_MRX_CTL, cfg);
411
412 if (bgx_poll_reg(bgx, lmacid, BGX_GMP_PCS_MRX_STATUS,
413 PCS_MRX_STATUS_AN_CPT, false)) {
414 dev_err(&bgx->pdev->dev, "BGX AN_CPT not completed\n");
415 return -1;
416 }
417
418 return 0;
419 }
420
421 static int bgx_lmac_xaui_init(struct bgx *bgx, int lmacid, int lmac_type)
422 {
423 u64 cfg;
424
425 /* Reset SPU */
426 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET);
427 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
428 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
429 return -1;
430 }
431
432 /* Disable LMAC */
433 cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
434 cfg &= ~CMR_EN;
435 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cfg);
436
437 bgx_reg_modify(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_LOW_POWER);
438 /* Set interleaved running disparity for RXAUI */
439 if (bgx->lmac_type != BGX_MODE_RXAUI)
440 bgx_reg_modify(bgx, lmacid,
441 BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
442 else
443 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL,
444 SPU_MISC_CTL_RX_DIS | SPU_MISC_CTL_INTLV_RDISP);
445
446 /* clear all interrupts */
447 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_RX_INT);
448 bgx_reg_write(bgx, lmacid, BGX_SMUX_RX_INT, cfg);
449 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_INT);
450 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_INT, cfg);
451 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
452 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
453
454 if (bgx->use_training) {
455 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LP_CUP, 0x00);
456 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_CUP, 0x00);
457 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_LD_REP, 0x00);
458 /* training enable */
459 bgx_reg_modify(bgx, lmacid,
460 BGX_SPUX_BR_PMD_CRTL, SPU_PMD_CRTL_TRAIN_EN);
461 }
462
463 /* Append FCS to each packet */
464 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, SMU_TX_APPEND_FCS_D);
465
466 /* Disable forward error correction */
467 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_FEC_CONTROL);
468 cfg &= ~SPU_FEC_CTL_FEC_EN;
469 bgx_reg_write(bgx, lmacid, BGX_SPUX_FEC_CONTROL, cfg);
470
471 /* Disable autoneg */
472 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_CONTROL);
473 cfg = cfg & ~(SPU_AN_CTL_AN_EN | SPU_AN_CTL_XNP_EN);
474 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_CONTROL, cfg);
475
476 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_AN_ADV);
477 if (bgx->lmac_type == BGX_MODE_10G_KR)
478 cfg |= (1 << 23);
479 else if (bgx->lmac_type == BGX_MODE_40G_KR)
480 cfg |= (1 << 24);
481 else
482 cfg &= ~((1 << 23) | (1 << 24));
483 cfg = cfg & (~((1ULL << 25) | (1ULL << 22) | (1ULL << 12)));
484 bgx_reg_write(bgx, lmacid, BGX_SPUX_AN_ADV, cfg);
485
486 cfg = bgx_reg_read(bgx, 0, BGX_SPU_DBG_CONTROL);
487 cfg &= ~SPU_DBG_CTL_AN_ARB_LINK_CHK_EN;
488 bgx_reg_write(bgx, 0, BGX_SPU_DBG_CONTROL, cfg);
489
490 /* Enable lmac */
491 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
492
493 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_CONTROL1);
494 cfg &= ~SPU_CTL_LOW_POWER;
495 bgx_reg_write(bgx, lmacid, BGX_SPUX_CONTROL1, cfg);
496
497 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_CTL);
498 cfg &= ~SMU_TX_CTL_UNI_EN;
499 cfg |= SMU_TX_CTL_DIC_EN;
500 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_CTL, cfg);
501
502 /* take lmac_count into account */
503 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_THRESH, (0x100 - 1));
504 /* max packet size */
505 bgx_reg_modify(bgx, lmacid, BGX_SMUX_RX_JABBER, MAX_FRAME_SIZE);
506
507 return 0;
508 }
509
510 static int bgx_xaui_check_link(struct lmac *lmac)
511 {
512 struct bgx *bgx = lmac->bgx;
513 int lmacid = lmac->lmacid;
514 int lmac_type = bgx->lmac_type;
515 u64 cfg;
516
517 bgx_reg_modify(bgx, lmacid, BGX_SPUX_MISC_CONTROL, SPU_MISC_CTL_RX_DIS);
518 if (bgx->use_training) {
519 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
520 if (!(cfg & (1ull << 13))) {
521 cfg = (1ull << 13) | (1ull << 14);
522 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
523 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL);
524 cfg |= (1ull << 0);
525 bgx_reg_write(bgx, lmacid, BGX_SPUX_BR_PMD_CRTL, cfg);
526 return -1;
527 }
528 }
529
530 /* wait for PCS to come out of reset */
531 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_CONTROL1, SPU_CTL_RESET, true)) {
532 dev_err(&bgx->pdev->dev, "BGX SPU reset not completed\n");
533 return -1;
534 }
535
536 if ((lmac_type == BGX_MODE_10G_KR) || (lmac_type == BGX_MODE_XFI) ||
537 (lmac_type == BGX_MODE_40G_KR) || (lmac_type == BGX_MODE_XLAUI)) {
538 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BR_STATUS1,
539 SPU_BR_STATUS_BLK_LOCK, false)) {
540 dev_err(&bgx->pdev->dev,
541 "SPU_BR_STATUS_BLK_LOCK not completed\n");
542 return -1;
543 }
544 } else {
545 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_BX_STATUS,
546 SPU_BX_STATUS_RX_ALIGN, false)) {
547 dev_err(&bgx->pdev->dev,
548 "SPU_BX_STATUS_RX_ALIGN not completed\n");
549 return -1;
550 }
551 }
552
553 /* Clear rcvflt bit (latching high) and read it back */
554 bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS2, SPU_STATUS2_RCVFLT);
555 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
556 dev_err(&bgx->pdev->dev, "Receive fault, retry training\n");
557 if (bgx->use_training) {
558 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_INT);
559 if (!(cfg & (1ull << 13))) {
560 cfg = (1ull << 13) | (1ull << 14);
561 bgx_reg_write(bgx, lmacid, BGX_SPUX_INT, cfg);
562 cfg = bgx_reg_read(bgx, lmacid,
563 BGX_SPUX_BR_PMD_CRTL);
564 cfg |= (1ull << 0);
565 bgx_reg_write(bgx, lmacid,
566 BGX_SPUX_BR_PMD_CRTL, cfg);
567 return -1;
568 }
569 }
570 return -1;
571 }
572
573 /* Wait for MAC RX to be ready */
574 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_RX_CTL,
575 SMU_RX_CTL_STATUS, true)) {
576 dev_err(&bgx->pdev->dev, "SMU RX link not okay\n");
577 return -1;
578 }
579
580 /* Wait for BGX RX to be idle */
581 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_RX_IDLE, false)) {
582 dev_err(&bgx->pdev->dev, "SMU RX not idle\n");
583 return -1;
584 }
585
586 /* Wait for BGX TX to be idle */
587 if (bgx_poll_reg(bgx, lmacid, BGX_SMUX_CTL, SMU_CTL_TX_IDLE, false)) {
588 dev_err(&bgx->pdev->dev, "SMU TX not idle\n");
589 return -1;
590 }
591
592 if (bgx_reg_read(bgx, lmacid, BGX_SPUX_STATUS2) & SPU_STATUS2_RCVFLT) {
593 dev_err(&bgx->pdev->dev, "Receive fault\n");
594 return -1;
595 }
596
597 /* Receive link is latching low. Force it high and verify it */
598 bgx_reg_modify(bgx, lmacid, BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
599 if (bgx_poll_reg(bgx, lmacid, BGX_SPUX_STATUS1,
600 SPU_STATUS1_RCV_LNK, false)) {
601 dev_err(&bgx->pdev->dev, "SPU receive link down\n");
602 return -1;
603 }
604
605 cfg = bgx_reg_read(bgx, lmacid, BGX_SPUX_MISC_CONTROL);
606 cfg &= ~SPU_MISC_CTL_RX_DIS;
607 bgx_reg_write(bgx, lmacid, BGX_SPUX_MISC_CONTROL, cfg);
608 return 0;
609 }
610
611 static void bgx_poll_for_link(struct work_struct *work)
612 {
613 struct lmac *lmac;
614 u64 link;
615
616 lmac = container_of(work, struct lmac, dwork.work);
617
618 /* Receive link is latching low. Force it high and verify it */
619 bgx_reg_modify(lmac->bgx, lmac->lmacid,
620 BGX_SPUX_STATUS1, SPU_STATUS1_RCV_LNK);
621 bgx_poll_reg(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1,
622 SPU_STATUS1_RCV_LNK, false);
623
624 link = bgx_reg_read(lmac->bgx, lmac->lmacid, BGX_SPUX_STATUS1);
625 if (link & SPU_STATUS1_RCV_LNK) {
626 lmac->link_up = 1;
627 if (lmac->bgx->lmac_type == BGX_MODE_XLAUI)
628 lmac->last_speed = 40000;
629 else
630 lmac->last_speed = 10000;
631 lmac->last_duplex = 1;
632 } else {
633 lmac->link_up = 0;
634 lmac->last_speed = SPEED_UNKNOWN;
635 lmac->last_duplex = DUPLEX_UNKNOWN;
636 }
637
638 if (lmac->last_link != lmac->link_up) {
639 lmac->last_link = lmac->link_up;
640 if (lmac->link_up)
641 bgx_xaui_check_link(lmac);
642 }
643
644 queue_delayed_work(lmac->check_link, &lmac->dwork, HZ * 2);
645 }
646
647 static int bgx_lmac_enable(struct bgx *bgx, u8 lmacid)
648 {
649 struct lmac *lmac;
650 u64 cfg;
651
652 lmac = &bgx->lmac[lmacid];
653 lmac->bgx = bgx;
654
655 if (bgx->lmac_type == BGX_MODE_SGMII) {
656 lmac->is_sgmii = 1;
657 if (bgx_lmac_sgmii_init(bgx, lmacid))
658 return -1;
659 } else {
660 lmac->is_sgmii = 0;
661 if (bgx_lmac_xaui_init(bgx, lmacid, bgx->lmac_type))
662 return -1;
663 }
664
665 if (lmac->is_sgmii) {
666 cfg = bgx_reg_read(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND);
667 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
668 bgx_reg_modify(bgx, lmacid, BGX_GMP_GMI_TXX_APPEND, cfg);
669 bgx_reg_write(bgx, lmacid, BGX_GMP_GMI_TXX_MIN_PKT, 60 - 1);
670 } else {
671 cfg = bgx_reg_read(bgx, lmacid, BGX_SMUX_TX_APPEND);
672 cfg |= ((1ull << 2) | (1ull << 1)); /* FCS and PAD */
673 bgx_reg_modify(bgx, lmacid, BGX_SMUX_TX_APPEND, cfg);
674 bgx_reg_write(bgx, lmacid, BGX_SMUX_TX_MIN_PKT, 60 + 4);
675 }
676
677 /* Enable lmac */
678 bgx_reg_modify(bgx, lmacid, BGX_CMRX_CFG, CMR_EN);
679
680 /* Restore default cfg, incase low level firmware changed it */
681 bgx_reg_write(bgx, lmacid, BGX_CMRX_RX_DMAC_CTL, 0x03);
682
683 if ((bgx->lmac_type != BGX_MODE_XFI) &&
684 (bgx->lmac_type != BGX_MODE_XLAUI) &&
685 (bgx->lmac_type != BGX_MODE_40G_KR) &&
686 (bgx->lmac_type != BGX_MODE_10G_KR)) {
687 if (!lmac->phydev)
688 return -ENODEV;
689
690 lmac->phydev->dev_flags = 0;
691
692 if (phy_connect_direct(&lmac->netdev, lmac->phydev,
693 bgx_lmac_handler,
694 PHY_INTERFACE_MODE_SGMII))
695 return -ENODEV;
696
697 phy_start_aneg(lmac->phydev);
698 } else {
699 lmac->check_link = alloc_workqueue("check_link", WQ_UNBOUND |
700 WQ_MEM_RECLAIM, 1);
701 if (!lmac->check_link)
702 return -ENOMEM;
703 INIT_DELAYED_WORK(&lmac->dwork, bgx_poll_for_link);
704 queue_delayed_work(lmac->check_link, &lmac->dwork, 0);
705 }
706
707 return 0;
708 }
709
710 static void bgx_lmac_disable(struct bgx *bgx, u8 lmacid)
711 {
712 struct lmac *lmac;
713 u64 cmrx_cfg;
714
715 lmac = &bgx->lmac[lmacid];
716 if (lmac->check_link) {
717 /* Destroy work queue */
718 cancel_delayed_work_sync(&lmac->dwork);
719 destroy_workqueue(lmac->check_link);
720 }
721
722 cmrx_cfg = bgx_reg_read(bgx, lmacid, BGX_CMRX_CFG);
723 cmrx_cfg &= ~(1 << 15);
724 bgx_reg_write(bgx, lmacid, BGX_CMRX_CFG, cmrx_cfg);
725 bgx_flush_dmac_addrs(bgx, lmacid);
726
727 if ((bgx->lmac_type != BGX_MODE_XFI) &&
728 (bgx->lmac_type != BGX_MODE_XLAUI) &&
729 (bgx->lmac_type != BGX_MODE_40G_KR) &&
730 (bgx->lmac_type != BGX_MODE_10G_KR) && lmac->phydev)
731 phy_disconnect(lmac->phydev);
732
733 lmac->phydev = NULL;
734 }
735
736 static void bgx_set_num_ports(struct bgx *bgx)
737 {
738 u64 lmac_count;
739
740 switch (bgx->qlm_mode) {
741 case QLM_MODE_SGMII:
742 bgx->lmac_count = 4;
743 bgx->lmac_type = BGX_MODE_SGMII;
744 bgx->lane_to_sds = 0;
745 break;
746 case QLM_MODE_XAUI_1X4:
747 bgx->lmac_count = 1;
748 bgx->lmac_type = BGX_MODE_XAUI;
749 bgx->lane_to_sds = 0xE4;
750 break;
751 case QLM_MODE_RXAUI_2X2:
752 bgx->lmac_count = 2;
753 bgx->lmac_type = BGX_MODE_RXAUI;
754 bgx->lane_to_sds = 0xE4;
755 break;
756 case QLM_MODE_XFI_4X1:
757 bgx->lmac_count = 4;
758 bgx->lmac_type = BGX_MODE_XFI;
759 bgx->lane_to_sds = 0;
760 break;
761 case QLM_MODE_XLAUI_1X4:
762 bgx->lmac_count = 1;
763 bgx->lmac_type = BGX_MODE_XLAUI;
764 bgx->lane_to_sds = 0xE4;
765 break;
766 case QLM_MODE_10G_KR_4X1:
767 bgx->lmac_count = 4;
768 bgx->lmac_type = BGX_MODE_10G_KR;
769 bgx->lane_to_sds = 0;
770 bgx->use_training = 1;
771 break;
772 case QLM_MODE_40G_KR4_1X4:
773 bgx->lmac_count = 1;
774 bgx->lmac_type = BGX_MODE_40G_KR;
775 bgx->lane_to_sds = 0xE4;
776 bgx->use_training = 1;
777 break;
778 default:
779 bgx->lmac_count = 0;
780 break;
781 }
782
783 /* Check if low level firmware has programmed LMAC count
784 * based on board type, if yes consider that otherwise
785 * the default static values
786 */
787 lmac_count = bgx_reg_read(bgx, 0, BGX_CMR_RX_LMACS) & 0x7;
788 if (lmac_count != 4)
789 bgx->lmac_count = lmac_count;
790 }
791
792 static void bgx_init_hw(struct bgx *bgx)
793 {
794 int i;
795
796 bgx_set_num_ports(bgx);
797
798 bgx_reg_modify(bgx, 0, BGX_CMR_GLOBAL_CFG, CMR_GLOBAL_CFG_FCS_STRIP);
799 if (bgx_reg_read(bgx, 0, BGX_CMR_BIST_STATUS))
800 dev_err(&bgx->pdev->dev, "BGX%d BIST failed\n", bgx->bgx_id);
801
802 /* Set lmac type and lane2serdes mapping */
803 for (i = 0; i < bgx->lmac_count; i++) {
804 if (bgx->lmac_type == BGX_MODE_RXAUI) {
805 if (i)
806 bgx->lane_to_sds = 0x0e;
807 else
808 bgx->lane_to_sds = 0x04;
809 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
810 (bgx->lmac_type << 8) | bgx->lane_to_sds);
811 continue;
812 }
813 bgx_reg_write(bgx, i, BGX_CMRX_CFG,
814 (bgx->lmac_type << 8) | (bgx->lane_to_sds + i));
815 bgx->lmac[i].lmacid_bd = lmac_count;
816 lmac_count++;
817 }
818
819 bgx_reg_write(bgx, 0, BGX_CMR_TX_LMACS, bgx->lmac_count);
820 bgx_reg_write(bgx, 0, BGX_CMR_RX_LMACS, bgx->lmac_count);
821
822 /* Set the backpressure AND mask */
823 for (i = 0; i < bgx->lmac_count; i++)
824 bgx_reg_modify(bgx, 0, BGX_CMR_CHAN_MSK_AND,
825 ((1ULL << MAX_BGX_CHANS_PER_LMAC) - 1) <<
826 (i * MAX_BGX_CHANS_PER_LMAC));
827
828 /* Disable all MAC filtering */
829 for (i = 0; i < RX_DMAC_COUNT; i++)
830 bgx_reg_write(bgx, 0, BGX_CMR_RX_DMACX_CAM + (i * 8), 0x00);
831
832 /* Disable MAC steering (NCSI traffic) */
833 for (i = 0; i < RX_TRAFFIC_STEER_RULE_COUNT; i++)
834 bgx_reg_write(bgx, 0, BGX_CMR_RX_STREERING + (i * 8), 0x00);
835 }
836
837 static void bgx_get_qlm_mode(struct bgx *bgx)
838 {
839 struct device *dev = &bgx->pdev->dev;
840 int lmac_type;
841 int train_en;
842
843 /* Read LMAC0 type to figure out QLM mode
844 * This is configured by low level firmware
845 */
846 lmac_type = bgx_reg_read(bgx, 0, BGX_CMRX_CFG);
847 lmac_type = (lmac_type >> 8) & 0x07;
848
849 train_en = bgx_reg_read(bgx, 0, BGX_SPUX_BR_PMD_CRTL) &
850 SPU_PMD_CRTL_TRAIN_EN;
851
852 switch (lmac_type) {
853 case BGX_MODE_SGMII:
854 bgx->qlm_mode = QLM_MODE_SGMII;
855 dev_info(dev, "BGX%d QLM mode: SGMII\n", bgx->bgx_id);
856 break;
857 case BGX_MODE_XAUI:
858 bgx->qlm_mode = QLM_MODE_XAUI_1X4;
859 dev_info(dev, "BGX%d QLM mode: XAUI\n", bgx->bgx_id);
860 break;
861 case BGX_MODE_RXAUI:
862 bgx->qlm_mode = QLM_MODE_RXAUI_2X2;
863 dev_info(dev, "BGX%d QLM mode: RXAUI\n", bgx->bgx_id);
864 break;
865 case BGX_MODE_XFI:
866 if (!train_en) {
867 bgx->qlm_mode = QLM_MODE_XFI_4X1;
868 dev_info(dev, "BGX%d QLM mode: XFI\n", bgx->bgx_id);
869 } else {
870 bgx->qlm_mode = QLM_MODE_10G_KR_4X1;
871 dev_info(dev, "BGX%d QLM mode: 10G_KR\n", bgx->bgx_id);
872 }
873 break;
874 case BGX_MODE_XLAUI:
875 if (!train_en) {
876 bgx->qlm_mode = QLM_MODE_XLAUI_1X4;
877 dev_info(dev, "BGX%d QLM mode: XLAUI\n", bgx->bgx_id);
878 } else {
879 bgx->qlm_mode = QLM_MODE_40G_KR4_1X4;
880 dev_info(dev, "BGX%d QLM mode: 40G_KR4\n", bgx->bgx_id);
881 }
882 break;
883 default:
884 bgx->qlm_mode = QLM_MODE_SGMII;
885 dev_info(dev, "BGX%d QLM default mode: SGMII\n", bgx->bgx_id);
886 }
887 }
888
889 #ifdef CONFIG_ACPI
890
891 static int acpi_get_mac_address(struct device *dev, struct acpi_device *adev,
892 u8 *dst)
893 {
894 u8 mac[ETH_ALEN];
895 int ret;
896
897 ret = fwnode_property_read_u8_array(acpi_fwnode_handle(adev),
898 "mac-address", mac, ETH_ALEN);
899 if (ret)
900 goto out;
901
902 if (!is_valid_ether_addr(mac)) {
903 dev_err(dev, "MAC address invalid: %pM\n", mac);
904 ret = -EINVAL;
905 goto out;
906 }
907
908 dev_info(dev, "MAC address set to: %pM\n", mac);
909
910 memcpy(dst, mac, ETH_ALEN);
911 out:
912 return ret;
913 }
914
915 /* Currently only sets the MAC address. */
916 static acpi_status bgx_acpi_register_phy(acpi_handle handle,
917 u32 lvl, void *context, void **rv)
918 {
919 struct bgx *bgx = context;
920 struct device *dev = &bgx->pdev->dev;
921 struct acpi_device *adev;
922
923 if (acpi_bus_get_device(handle, &adev))
924 goto out;
925
926 acpi_get_mac_address(dev, adev, bgx->lmac[bgx->lmac_count].mac);
927
928 SET_NETDEV_DEV(&bgx->lmac[bgx->lmac_count].netdev, dev);
929
930 bgx->lmac[bgx->lmac_count].lmacid = bgx->lmac_count;
931 out:
932 bgx->lmac_count++;
933 return AE_OK;
934 }
935
936 static acpi_status bgx_acpi_match_id(acpi_handle handle, u32 lvl,
937 void *context, void **ret_val)
938 {
939 struct acpi_buffer string = { ACPI_ALLOCATE_BUFFER, NULL };
940 struct bgx *bgx = context;
941 char bgx_sel[5];
942
943 snprintf(bgx_sel, 5, "BGX%d", bgx->bgx_id);
944 if (ACPI_FAILURE(acpi_get_name(handle, ACPI_SINGLE_NAME, &string))) {
945 pr_warn("Invalid link device\n");
946 return AE_OK;
947 }
948
949 if (strncmp(string.pointer, bgx_sel, 4))
950 return AE_OK;
951
952 acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1,
953 bgx_acpi_register_phy, NULL, bgx, NULL);
954
955 kfree(string.pointer);
956 return AE_CTRL_TERMINATE;
957 }
958
959 static int bgx_init_acpi_phy(struct bgx *bgx)
960 {
961 acpi_get_devices(NULL, bgx_acpi_match_id, bgx, (void **)NULL);
962 return 0;
963 }
964
965 #else
966
967 static int bgx_init_acpi_phy(struct bgx *bgx)
968 {
969 return -ENODEV;
970 }
971
972 #endif /* CONFIG_ACPI */
973
974 #if IS_ENABLED(CONFIG_OF_MDIO)
975
976 static int bgx_init_of_phy(struct bgx *bgx)
977 {
978 struct fwnode_handle *fwn;
979 struct device_node *node = NULL;
980 u8 lmac = 0;
981
982 device_for_each_child_node(&bgx->pdev->dev, fwn) {
983 struct phy_device *pd;
984 struct device_node *phy_np;
985 const char *mac;
986
987 /* Should always be an OF node. But if it is not, we
988 * cannot handle it, so exit the loop.
989 */
990 node = to_of_node(fwn);
991 if (!node)
992 break;
993
994 mac = of_get_mac_address(node);
995 if (mac)
996 ether_addr_copy(bgx->lmac[lmac].mac, mac);
997
998 SET_NETDEV_DEV(&bgx->lmac[lmac].netdev, &bgx->pdev->dev);
999 bgx->lmac[lmac].lmacid = lmac;
1000
1001 phy_np = of_parse_phandle(node, "phy-handle", 0);
1002 /* If there is no phy or defective firmware presents
1003 * this cortina phy, for which there is no driver
1004 * support, ignore it.
1005 */
1006 if (phy_np &&
1007 !of_device_is_compatible(phy_np, "cortina,cs4223-slice")) {
1008 /* Wait until the phy drivers are available */
1009 pd = of_phy_find_device(phy_np);
1010 if (!pd)
1011 goto defer;
1012 bgx->lmac[lmac].phydev = pd;
1013 }
1014
1015 lmac++;
1016 if (lmac == MAX_LMAC_PER_BGX) {
1017 of_node_put(node);
1018 break;
1019 }
1020 }
1021 return 0;
1022
1023 defer:
1024 /* We are bailing out, try not to leak device reference counts
1025 * for phy devices we may have already found.
1026 */
1027 while (lmac) {
1028 if (bgx->lmac[lmac].phydev) {
1029 put_device(&bgx->lmac[lmac].phydev->mdio.dev);
1030 bgx->lmac[lmac].phydev = NULL;
1031 }
1032 lmac--;
1033 }
1034 of_node_put(node);
1035 return -EPROBE_DEFER;
1036 }
1037
1038 #else
1039
1040 static int bgx_init_of_phy(struct bgx *bgx)
1041 {
1042 return -ENODEV;
1043 }
1044
1045 #endif /* CONFIG_OF_MDIO */
1046
1047 static int bgx_init_phy(struct bgx *bgx)
1048 {
1049 if (!acpi_disabled)
1050 return bgx_init_acpi_phy(bgx);
1051
1052 return bgx_init_of_phy(bgx);
1053 }
1054
1055 static int bgx_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
1056 {
1057 int err;
1058 struct device *dev = &pdev->dev;
1059 struct bgx *bgx = NULL;
1060 u8 lmac;
1061
1062 bgx = devm_kzalloc(dev, sizeof(*bgx), GFP_KERNEL);
1063 if (!bgx)
1064 return -ENOMEM;
1065 bgx->pdev = pdev;
1066
1067 pci_set_drvdata(pdev, bgx);
1068
1069 err = pci_enable_device(pdev);
1070 if (err) {
1071 dev_err(dev, "Failed to enable PCI device\n");
1072 pci_set_drvdata(pdev, NULL);
1073 return err;
1074 }
1075
1076 err = pci_request_regions(pdev, DRV_NAME);
1077 if (err) {
1078 dev_err(dev, "PCI request regions failed 0x%x\n", err);
1079 goto err_disable_device;
1080 }
1081
1082 /* MAP configuration registers */
1083 bgx->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0);
1084 if (!bgx->reg_base) {
1085 dev_err(dev, "BGX: Cannot map CSR memory space, aborting\n");
1086 err = -ENOMEM;
1087 goto err_release_regions;
1088 }
1089 bgx->bgx_id = (pci_resource_start(pdev, PCI_CFG_REG_BAR_NUM) >> 24) & 1;
1090 bgx->bgx_id += nic_get_node_id(pdev) * MAX_BGX_PER_CN88XX;
1091
1092 bgx_vnic[bgx->bgx_id] = bgx;
1093 bgx_get_qlm_mode(bgx);
1094
1095 err = bgx_init_phy(bgx);
1096 if (err)
1097 goto err_enable;
1098
1099 bgx_init_hw(bgx);
1100
1101 /* Enable all LMACs */
1102 for (lmac = 0; lmac < bgx->lmac_count; lmac++) {
1103 err = bgx_lmac_enable(bgx, lmac);
1104 if (err) {
1105 dev_err(dev, "BGX%d failed to enable lmac%d\n",
1106 bgx->bgx_id, lmac);
1107 goto err_enable;
1108 }
1109 }
1110
1111 return 0;
1112
1113 err_enable:
1114 bgx_vnic[bgx->bgx_id] = NULL;
1115 err_release_regions:
1116 pci_release_regions(pdev);
1117 err_disable_device:
1118 pci_disable_device(pdev);
1119 pci_set_drvdata(pdev, NULL);
1120 return err;
1121 }
1122
1123 static void bgx_remove(struct pci_dev *pdev)
1124 {
1125 struct bgx *bgx = pci_get_drvdata(pdev);
1126 u8 lmac;
1127
1128 /* Disable all LMACs */
1129 for (lmac = 0; lmac < bgx->lmac_count; lmac++)
1130 bgx_lmac_disable(bgx, lmac);
1131
1132 bgx_vnic[bgx->bgx_id] = NULL;
1133 pci_release_regions(pdev);
1134 pci_disable_device(pdev);
1135 pci_set_drvdata(pdev, NULL);
1136 }
1137
1138 static struct pci_driver bgx_driver = {
1139 .name = DRV_NAME,
1140 .id_table = bgx_id_table,
1141 .probe = bgx_probe,
1142 .remove = bgx_remove,
1143 };
1144
1145 static int __init bgx_init_module(void)
1146 {
1147 pr_info("%s, ver %s\n", DRV_NAME, DRV_VERSION);
1148
1149 return pci_register_driver(&bgx_driver);
1150 }
1151
1152 static void __exit bgx_cleanup_module(void)
1153 {
1154 pci_unregister_driver(&bgx_driver);
1155 }
1156
1157 module_init(bgx_init_module);
1158 module_exit(bgx_cleanup_module);
Linux kernel - Deliverables
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