2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
37 #include <linux/bitmap.h>
38 #include <linux/crc32.h>
39 #include <linux/ctype.h>
40 #include <linux/debugfs.h>
41 #include <linux/err.h>
42 #include <linux/etherdevice.h>
43 #include <linux/firmware.h>
45 #include <linux/if_vlan.h>
46 #include <linux/init.h>
47 #include <linux/log2.h>
48 #include <linux/mdio.h>
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/mutex.h>
52 #include <linux/netdevice.h>
53 #include <linux/pci.h>
54 #include <linux/aer.h>
55 #include <linux/rtnetlink.h>
56 #include <linux/sched.h>
57 #include <linux/seq_file.h>
58 #include <linux/sockios.h>
59 #include <linux/vmalloc.h>
60 #include <linux/workqueue.h>
61 #include <net/neighbour.h>
62 #include <net/netevent.h>
63 #include <net/addrconf.h>
64 #include <asm/uaccess.h>
70 #include "cxgb4_dcb.h"
73 #include <../drivers/net/bonding/bonding.h>
78 #define DRV_VERSION "2.0.0-ko"
79 #define DRV_DESC "Chelsio T4/T5 Network Driver"
82 * Max interrupt hold-off timer value in us. Queues fall back to this value
83 * under extreme memory pressure so it's largish to give the system time to
86 #define MAX_SGE_TIMERVAL 200U
90 * Physical Function provisioning constants.
92 PFRES_NVI
= 4, /* # of Virtual Interfaces */
93 PFRES_NETHCTRL
= 128, /* # of EQs used for ETH or CTRL Qs */
94 PFRES_NIQFLINT
= 128, /* # of ingress Qs/w Free List(s)/intr
96 PFRES_NEQ
= 256, /* # of egress queues */
97 PFRES_NIQ
= 0, /* # of ingress queues */
98 PFRES_TC
= 0, /* PCI-E traffic class */
99 PFRES_NEXACTF
= 128, /* # of exact MPS filters */
101 PFRES_R_CAPS
= FW_CMD_CAP_PF
,
102 PFRES_WX_CAPS
= FW_CMD_CAP_PF
,
104 #ifdef CONFIG_PCI_IOV
106 * Virtual Function provisioning constants. We need two extra Ingress
107 * Queues with Interrupt capability to serve as the VF's Firmware
108 * Event Queue and Forwarded Interrupt Queue (when using MSI mode) --
109 * neither will have Free Lists associated with them). For each
110 * Ethernet/Control Egress Queue and for each Free List, we need an
113 VFRES_NPORTS
= 1, /* # of "ports" per VF */
114 VFRES_NQSETS
= 2, /* # of "Queue Sets" per VF */
116 VFRES_NVI
= VFRES_NPORTS
, /* # of Virtual Interfaces */
117 VFRES_NETHCTRL
= VFRES_NQSETS
, /* # of EQs used for ETH or CTRL Qs */
118 VFRES_NIQFLINT
= VFRES_NQSETS
+2,/* # of ingress Qs/w Free List(s)/intr */
119 VFRES_NEQ
= VFRES_NQSETS
*2, /* # of egress queues */
120 VFRES_NIQ
= 0, /* # of non-fl/int ingress queues */
121 VFRES_TC
= 0, /* PCI-E traffic class */
122 VFRES_NEXACTF
= 16, /* # of exact MPS filters */
124 VFRES_R_CAPS
= FW_CMD_CAP_DMAQ
|FW_CMD_CAP_VF
|FW_CMD_CAP_PORT
,
125 VFRES_WX_CAPS
= FW_CMD_CAP_DMAQ
|FW_CMD_CAP_VF
,
130 * Provide a Port Access Rights Mask for the specified PF/VF. This is very
131 * static and likely not to be useful in the long run. We really need to
132 * implement some form of persistent configuration which the firmware
135 static unsigned int pfvfres_pmask(struct adapter
*adapter
,
136 unsigned int pf
, unsigned int vf
)
138 unsigned int portn
, portvec
;
141 * Give PF's access to all of the ports.
144 return FW_PFVF_CMD_PMASK_MASK
;
147 * For VFs, we'll assign them access to the ports based purely on the
148 * PF. We assign active ports in order, wrapping around if there are
149 * fewer active ports than PFs: e.g. active port[pf % nports].
150 * Unfortunately the adapter's port_info structs haven't been
151 * initialized yet so we have to compute this.
153 if (adapter
->params
.nports
== 0)
156 portn
= pf
% adapter
->params
.nports
;
157 portvec
= adapter
->params
.portvec
;
160 * Isolate the lowest set bit in the port vector. If we're at
161 * the port number that we want, return that as the pmask.
162 * otherwise mask that bit out of the port vector and
163 * decrement our port number ...
165 unsigned int pmask
= portvec
^ (portvec
& (portvec
-1));
175 MAX_TXQ_ENTRIES
= 16384,
176 MAX_CTRL_TXQ_ENTRIES
= 1024,
177 MAX_RSPQ_ENTRIES
= 16384,
178 MAX_RX_BUFFERS
= 16384,
179 MIN_TXQ_ENTRIES
= 32,
180 MIN_CTRL_TXQ_ENTRIES
= 32,
181 MIN_RSPQ_ENTRIES
= 128,
185 /* Host shadow copy of ingress filter entry. This is in host native format
186 * and doesn't match the ordering or bit order, etc. of the hardware of the
187 * firmware command. The use of bit-field structure elements is purely to
188 * remind ourselves of the field size limitations and save memory in the case
189 * where the filter table is large.
191 struct filter_entry
{
192 /* Administrative fields for filter.
194 u32 valid
:1; /* filter allocated and valid */
195 u32 locked
:1; /* filter is administratively locked */
197 u32 pending
:1; /* filter action is pending firmware reply */
198 u32 smtidx
:8; /* Source MAC Table index for smac */
199 struct l2t_entry
*l2t
; /* Layer Two Table entry for dmac */
201 /* The filter itself. Most of this is a straight copy of information
202 * provided by the extended ioctl(). Some fields are translated to
203 * internal forms -- for instance the Ingress Queue ID passed in from
204 * the ioctl() is translated into the Absolute Ingress Queue ID.
206 struct ch_filter_specification fs
;
209 #define DFLT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK | \
210 NETIF_MSG_TIMER | NETIF_MSG_IFDOWN | NETIF_MSG_IFUP |\
211 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR)
213 #define CH_DEVICE(devid, data) { PCI_VDEVICE(CHELSIO, devid), (data) }
215 static const struct pci_device_id cxgb4_pci_tbl
[] = {
216 CH_DEVICE(0xa000, 0), /* PE10K */
217 CH_DEVICE(0x4001, -1),
218 CH_DEVICE(0x4002, -1),
219 CH_DEVICE(0x4003, -1),
220 CH_DEVICE(0x4004, -1),
221 CH_DEVICE(0x4005, -1),
222 CH_DEVICE(0x4006, -1),
223 CH_DEVICE(0x4007, -1),
224 CH_DEVICE(0x4008, -1),
225 CH_DEVICE(0x4009, -1),
226 CH_DEVICE(0x400a, -1),
227 CH_DEVICE(0x400d, -1),
228 CH_DEVICE(0x400e, -1),
229 CH_DEVICE(0x4080, -1),
230 CH_DEVICE(0x4081, -1),
231 CH_DEVICE(0x4082, -1),
232 CH_DEVICE(0x4083, -1),
233 CH_DEVICE(0x4084, -1),
234 CH_DEVICE(0x4085, -1),
235 CH_DEVICE(0x4086, -1),
236 CH_DEVICE(0x4087, -1),
237 CH_DEVICE(0x4088, -1),
238 CH_DEVICE(0x4401, 4),
239 CH_DEVICE(0x4402, 4),
240 CH_DEVICE(0x4403, 4),
241 CH_DEVICE(0x4404, 4),
242 CH_DEVICE(0x4405, 4),
243 CH_DEVICE(0x4406, 4),
244 CH_DEVICE(0x4407, 4),
245 CH_DEVICE(0x4408, 4),
246 CH_DEVICE(0x4409, 4),
247 CH_DEVICE(0x440a, 4),
248 CH_DEVICE(0x440d, 4),
249 CH_DEVICE(0x440e, 4),
250 CH_DEVICE(0x4480, 4),
251 CH_DEVICE(0x4481, 4),
252 CH_DEVICE(0x4482, 4),
253 CH_DEVICE(0x4483, 4),
254 CH_DEVICE(0x4484, 4),
255 CH_DEVICE(0x4485, 4),
256 CH_DEVICE(0x4486, 4),
257 CH_DEVICE(0x4487, 4),
258 CH_DEVICE(0x4488, 4),
259 CH_DEVICE(0x5001, 4),
260 CH_DEVICE(0x5002, 4),
261 CH_DEVICE(0x5003, 4),
262 CH_DEVICE(0x5004, 4),
263 CH_DEVICE(0x5005, 4),
264 CH_DEVICE(0x5006, 4),
265 CH_DEVICE(0x5007, 4),
266 CH_DEVICE(0x5008, 4),
267 CH_DEVICE(0x5009, 4),
268 CH_DEVICE(0x500A, 4),
269 CH_DEVICE(0x500B, 4),
270 CH_DEVICE(0x500C, 4),
271 CH_DEVICE(0x500D, 4),
272 CH_DEVICE(0x500E, 4),
273 CH_DEVICE(0x500F, 4),
274 CH_DEVICE(0x5010, 4),
275 CH_DEVICE(0x5011, 4),
276 CH_DEVICE(0x5012, 4),
277 CH_DEVICE(0x5013, 4),
278 CH_DEVICE(0x5014, 4),
279 CH_DEVICE(0x5015, 4),
280 CH_DEVICE(0x5080, 4),
281 CH_DEVICE(0x5081, 4),
282 CH_DEVICE(0x5082, 4),
283 CH_DEVICE(0x5083, 4),
284 CH_DEVICE(0x5084, 4),
285 CH_DEVICE(0x5085, 4),
286 CH_DEVICE(0x5086, 4),
287 CH_DEVICE(0x5087, 4),
288 CH_DEVICE(0x5088, 4),
289 CH_DEVICE(0x5401, 4),
290 CH_DEVICE(0x5402, 4),
291 CH_DEVICE(0x5403, 4),
292 CH_DEVICE(0x5404, 4),
293 CH_DEVICE(0x5405, 4),
294 CH_DEVICE(0x5406, 4),
295 CH_DEVICE(0x5407, 4),
296 CH_DEVICE(0x5408, 4),
297 CH_DEVICE(0x5409, 4),
298 CH_DEVICE(0x540A, 4),
299 CH_DEVICE(0x540B, 4),
300 CH_DEVICE(0x540C, 4),
301 CH_DEVICE(0x540D, 4),
302 CH_DEVICE(0x540E, 4),
303 CH_DEVICE(0x540F, 4),
304 CH_DEVICE(0x5410, 4),
305 CH_DEVICE(0x5411, 4),
306 CH_DEVICE(0x5412, 4),
307 CH_DEVICE(0x5413, 4),
308 CH_DEVICE(0x5414, 4),
309 CH_DEVICE(0x5415, 4),
310 CH_DEVICE(0x5480, 4),
311 CH_DEVICE(0x5481, 4),
312 CH_DEVICE(0x5482, 4),
313 CH_DEVICE(0x5483, 4),
314 CH_DEVICE(0x5484, 4),
315 CH_DEVICE(0x5485, 4),
316 CH_DEVICE(0x5486, 4),
317 CH_DEVICE(0x5487, 4),
318 CH_DEVICE(0x5488, 4),
322 #define FW4_FNAME "cxgb4/t4fw.bin"
323 #define FW5_FNAME "cxgb4/t5fw.bin"
324 #define FW4_CFNAME "cxgb4/t4-config.txt"
325 #define FW5_CFNAME "cxgb4/t5-config.txt"
327 MODULE_DESCRIPTION(DRV_DESC
);
328 MODULE_AUTHOR("Chelsio Communications");
329 MODULE_LICENSE("Dual BSD/GPL");
330 MODULE_VERSION(DRV_VERSION
);
331 MODULE_DEVICE_TABLE(pci
, cxgb4_pci_tbl
);
332 MODULE_FIRMWARE(FW4_FNAME
);
333 MODULE_FIRMWARE(FW5_FNAME
);
336 * Normally we're willing to become the firmware's Master PF but will be happy
337 * if another PF has already become the Master and initialized the adapter.
338 * Setting "force_init" will cause this driver to forcibly establish itself as
339 * the Master PF and initialize the adapter.
341 static uint force_init
;
343 module_param(force_init
, uint
, 0644);
344 MODULE_PARM_DESC(force_init
, "Forcibly become Master PF and initialize adapter");
347 * Normally if the firmware we connect to has Configuration File support, we
348 * use that and only fall back to the old Driver-based initialization if the
349 * Configuration File fails for some reason. If force_old_init is set, then
350 * we'll always use the old Driver-based initialization sequence.
352 static uint force_old_init
;
354 module_param(force_old_init
, uint
, 0644);
355 MODULE_PARM_DESC(force_old_init
, "Force old initialization sequence");
357 static int dflt_msg_enable
= DFLT_MSG_ENABLE
;
359 module_param(dflt_msg_enable
, int, 0644);
360 MODULE_PARM_DESC(dflt_msg_enable
, "Chelsio T4 default message enable bitmap");
363 * The driver uses the best interrupt scheme available on a platform in the
364 * order MSI-X, MSI, legacy INTx interrupts. This parameter determines which
365 * of these schemes the driver may consider as follows:
367 * msi = 2: choose from among all three options
368 * msi = 1: only consider MSI and INTx interrupts
369 * msi = 0: force INTx interrupts
373 module_param(msi
, int, 0644);
374 MODULE_PARM_DESC(msi
, "whether to use INTx (0), MSI (1) or MSI-X (2)");
377 * Queue interrupt hold-off timer values. Queues default to the first of these
380 static unsigned int intr_holdoff
[SGE_NTIMERS
- 1] = { 5, 10, 20, 50, 100 };
382 module_param_array(intr_holdoff
, uint
, NULL
, 0644);
383 MODULE_PARM_DESC(intr_holdoff
, "values for queue interrupt hold-off timers "
384 "0..4 in microseconds");
386 static unsigned int intr_cnt
[SGE_NCOUNTERS
- 1] = { 4, 8, 16 };
388 module_param_array(intr_cnt
, uint
, NULL
, 0644);
389 MODULE_PARM_DESC(intr_cnt
,
390 "thresholds 1..3 for queue interrupt packet counters");
393 * Normally we tell the chip to deliver Ingress Packets into our DMA buffers
394 * offset by 2 bytes in order to have the IP headers line up on 4-byte
395 * boundaries. This is a requirement for many architectures which will throw
396 * a machine check fault if an attempt is made to access one of the 4-byte IP
397 * header fields on a non-4-byte boundary. And it's a major performance issue
398 * even on some architectures which allow it like some implementations of the
399 * x86 ISA. However, some architectures don't mind this and for some very
400 * edge-case performance sensitive applications (like forwarding large volumes
401 * of small packets), setting this DMA offset to 0 will decrease the number of
402 * PCI-E Bus transfers enough to measurably affect performance.
404 static int rx_dma_offset
= 2;
408 #ifdef CONFIG_PCI_IOV
409 module_param(vf_acls
, bool, 0644);
410 MODULE_PARM_DESC(vf_acls
, "if set enable virtualization L2 ACL enforcement");
412 /* Configure the number of PCI-E Virtual Function which are to be instantiated
413 * on SR-IOV Capable Physical Functions.
415 static unsigned int num_vf
[NUM_OF_PF_WITH_SRIOV
];
417 module_param_array(num_vf
, uint
, NULL
, 0644);
418 MODULE_PARM_DESC(num_vf
, "number of VFs for each of PFs 0-3");
421 /* TX Queue select used to determine what algorithm to use for selecting TX
422 * queue. Select between the kernel provided function (select_queue=0) or user
423 * cxgb_select_queue function (select_queue=1)
425 * Default: select_queue=0
427 static int select_queue
;
428 module_param(select_queue
, int, 0644);
429 MODULE_PARM_DESC(select_queue
,
430 "Select between kernel provided method of selecting or driver method of selecting TX queue. Default is kernel method.");
433 * The filter TCAM has a fixed portion and a variable portion. The fixed
434 * portion can match on source/destination IP IPv4/IPv6 addresses and TCP/UDP
435 * ports. The variable portion is 36 bits which can include things like Exact
436 * Match MAC Index (9 bits), Ether Type (16 bits), IP Protocol (8 bits),
437 * [Inner] VLAN Tag (17 bits), etc. which, if all were somehow selected, would
438 * far exceed the 36-bit budget for this "compressed" header portion of the
439 * filter. Thus, we have a scarce resource which must be carefully managed.
441 * By default we set this up to mostly match the set of filter matching
442 * capabilities of T3 but with accommodations for some of T4's more
443 * interesting features:
445 * { IP Fragment (1), MPS Match Type (3), IP Protocol (8),
446 * [Inner] VLAN (17), Port (3), FCoE (1) }
449 TP_VLAN_PRI_MAP_DEFAULT
= HW_TPL_FR_MT_PR_IV_P_FC
,
450 TP_VLAN_PRI_MAP_FIRST
= FCOE_SHIFT
,
451 TP_VLAN_PRI_MAP_LAST
= FRAGMENTATION_SHIFT
,
454 static unsigned int tp_vlan_pri_map
= TP_VLAN_PRI_MAP_DEFAULT
;
456 module_param(tp_vlan_pri_map
, uint
, 0644);
457 MODULE_PARM_DESC(tp_vlan_pri_map
, "global compressed filter configuration");
459 static struct dentry
*cxgb4_debugfs_root
;
461 static LIST_HEAD(adapter_list
);
462 static DEFINE_MUTEX(uld_mutex
);
463 /* Adapter list to be accessed from atomic context */
464 static LIST_HEAD(adap_rcu_list
);
465 static DEFINE_SPINLOCK(adap_rcu_lock
);
466 static struct cxgb4_uld_info ulds
[CXGB4_ULD_MAX
];
467 static const char *uld_str
[] = { "RDMA", "iSCSI" };
469 static void link_report(struct net_device
*dev
)
471 if (!netif_carrier_ok(dev
))
472 netdev_info(dev
, "link down\n");
474 static const char *fc
[] = { "no", "Rx", "Tx", "Tx/Rx" };
476 const char *s
= "10Mbps";
477 const struct port_info
*p
= netdev_priv(dev
);
479 switch (p
->link_cfg
.speed
) {
494 netdev_info(dev
, "link up, %s, full-duplex, %s PAUSE\n", s
,
499 #ifdef CONFIG_CHELSIO_T4_DCB
500 /* Set up/tear down Data Center Bridging Priority mapping for a net device. */
501 static void dcb_tx_queue_prio_enable(struct net_device
*dev
, int enable
)
503 struct port_info
*pi
= netdev_priv(dev
);
504 struct adapter
*adap
= pi
->adapter
;
505 struct sge_eth_txq
*txq
= &adap
->sge
.ethtxq
[pi
->first_qset
];
508 /* We use a simple mapping of Port TX Queue Index to DCB
509 * Priority when we're enabling DCB.
511 for (i
= 0; i
< pi
->nqsets
; i
++, txq
++) {
515 name
= (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ
) |
516 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH
) |
517 FW_PARAMS_PARAM_YZ(txq
->q
.cntxt_id
));
518 value
= enable
? i
: 0xffffffff;
520 /* Since we can be called while atomic (from "interrupt
521 * level") we need to issue the Set Parameters Commannd
522 * without sleeping (timeout < 0).
524 err
= t4_set_params_nosleep(adap
, adap
->mbox
, adap
->fn
, 0, 1,
528 dev_err(adap
->pdev_dev
,
529 "Can't %s DCB Priority on port %d, TX Queue %d: err=%d\n",
530 enable
? "set" : "unset", pi
->port_id
, i
, -err
);
532 txq
->dcb_prio
= value
;
535 #endif /* CONFIG_CHELSIO_T4_DCB */
537 void t4_os_link_changed(struct adapter
*adapter
, int port_id
, int link_stat
)
539 struct net_device
*dev
= adapter
->port
[port_id
];
541 /* Skip changes from disabled ports. */
542 if (netif_running(dev
) && link_stat
!= netif_carrier_ok(dev
)) {
544 netif_carrier_on(dev
);
546 #ifdef CONFIG_CHELSIO_T4_DCB
547 cxgb4_dcb_state_init(dev
);
548 dcb_tx_queue_prio_enable(dev
, false);
549 #endif /* CONFIG_CHELSIO_T4_DCB */
550 netif_carrier_off(dev
);
557 void t4_os_portmod_changed(const struct adapter
*adap
, int port_id
)
559 static const char *mod_str
[] = {
560 NULL
, "LR", "SR", "ER", "passive DA", "active DA", "LRM"
563 const struct net_device
*dev
= adap
->port
[port_id
];
564 const struct port_info
*pi
= netdev_priv(dev
);
566 if (pi
->mod_type
== FW_PORT_MOD_TYPE_NONE
)
567 netdev_info(dev
, "port module unplugged\n");
568 else if (pi
->mod_type
< ARRAY_SIZE(mod_str
))
569 netdev_info(dev
, "%s module inserted\n", mod_str
[pi
->mod_type
]);
573 * Configure the exact and hash address filters to handle a port's multicast
574 * and secondary unicast MAC addresses.
576 static int set_addr_filters(const struct net_device
*dev
, bool sleep
)
584 const struct netdev_hw_addr
*ha
;
585 int uc_cnt
= netdev_uc_count(dev
);
586 int mc_cnt
= netdev_mc_count(dev
);
587 const struct port_info
*pi
= netdev_priv(dev
);
588 unsigned int mb
= pi
->adapter
->fn
;
590 /* first do the secondary unicast addresses */
591 netdev_for_each_uc_addr(ha
, dev
) {
592 addr
[naddr
++] = ha
->addr
;
593 if (--uc_cnt
== 0 || naddr
>= ARRAY_SIZE(addr
)) {
594 ret
= t4_alloc_mac_filt(pi
->adapter
, mb
, pi
->viid
, free
,
595 naddr
, addr
, filt_idx
, &uhash
, sleep
);
604 /* next set up the multicast addresses */
605 netdev_for_each_mc_addr(ha
, dev
) {
606 addr
[naddr
++] = ha
->addr
;
607 if (--mc_cnt
== 0 || naddr
>= ARRAY_SIZE(addr
)) {
608 ret
= t4_alloc_mac_filt(pi
->adapter
, mb
, pi
->viid
, free
,
609 naddr
, addr
, filt_idx
, &mhash
, sleep
);
618 return t4_set_addr_hash(pi
->adapter
, mb
, pi
->viid
, uhash
!= 0,
619 uhash
| mhash
, sleep
);
622 int dbfifo_int_thresh
= 10; /* 10 == 640 entry threshold */
623 module_param(dbfifo_int_thresh
, int, 0644);
624 MODULE_PARM_DESC(dbfifo_int_thresh
, "doorbell fifo interrupt threshold");
627 * usecs to sleep while draining the dbfifo
629 static int dbfifo_drain_delay
= 1000;
630 module_param(dbfifo_drain_delay
, int, 0644);
631 MODULE_PARM_DESC(dbfifo_drain_delay
,
632 "usecs to sleep while draining the dbfifo");
635 * Set Rx properties of a port, such as promiscruity, address filters, and MTU.
636 * If @mtu is -1 it is left unchanged.
638 static int set_rxmode(struct net_device
*dev
, int mtu
, bool sleep_ok
)
641 struct port_info
*pi
= netdev_priv(dev
);
643 ret
= set_addr_filters(dev
, sleep_ok
);
645 ret
= t4_set_rxmode(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, mtu
,
646 (dev
->flags
& IFF_PROMISC
) ? 1 : 0,
647 (dev
->flags
& IFF_ALLMULTI
) ? 1 : 0, 1, -1,
653 * link_start - enable a port
654 * @dev: the port to enable
656 * Performs the MAC and PHY actions needed to enable a port.
658 static int link_start(struct net_device
*dev
)
661 struct port_info
*pi
= netdev_priv(dev
);
662 unsigned int mb
= pi
->adapter
->fn
;
665 * We do not set address filters and promiscuity here, the stack does
666 * that step explicitly.
668 ret
= t4_set_rxmode(pi
->adapter
, mb
, pi
->viid
, dev
->mtu
, -1, -1, -1,
669 !!(dev
->features
& NETIF_F_HW_VLAN_CTAG_RX
), true);
671 ret
= t4_change_mac(pi
->adapter
, mb
, pi
->viid
,
672 pi
->xact_addr_filt
, dev
->dev_addr
, true,
675 pi
->xact_addr_filt
= ret
;
680 ret
= t4_link_start(pi
->adapter
, mb
, pi
->tx_chan
,
684 ret
= t4_enable_vi_params(pi
->adapter
, mb
, pi
->viid
, true,
685 true, CXGB4_DCB_ENABLED
);
692 int cxgb4_dcb_enabled(const struct net_device
*dev
)
694 #ifdef CONFIG_CHELSIO_T4_DCB
695 struct port_info
*pi
= netdev_priv(dev
);
697 return pi
->dcb
.state
== CXGB4_DCB_STATE_FW_ALLSYNCED
;
702 EXPORT_SYMBOL(cxgb4_dcb_enabled
);
704 #ifdef CONFIG_CHELSIO_T4_DCB
705 /* Handle a Data Center Bridging update message from the firmware. */
706 static void dcb_rpl(struct adapter
*adap
, const struct fw_port_cmd
*pcmd
)
708 int port
= FW_PORT_CMD_PORTID_GET(ntohl(pcmd
->op_to_portid
));
709 struct net_device
*dev
= adap
->port
[port
];
710 int old_dcb_enabled
= cxgb4_dcb_enabled(dev
);
713 cxgb4_dcb_handle_fw_update(adap
, pcmd
);
714 new_dcb_enabled
= cxgb4_dcb_enabled(dev
);
716 /* If the DCB has become enabled or disabled on the port then we're
717 * going to need to set up/tear down DCB Priority parameters for the
718 * TX Queues associated with the port.
720 if (new_dcb_enabled
!= old_dcb_enabled
)
721 dcb_tx_queue_prio_enable(dev
, new_dcb_enabled
);
723 #endif /* CONFIG_CHELSIO_T4_DCB */
725 /* Clear a filter and release any of its resources that we own. This also
726 * clears the filter's "pending" status.
728 static void clear_filter(struct adapter
*adap
, struct filter_entry
*f
)
730 /* If the new or old filter have loopback rewriteing rules then we'll
731 * need to free any existing Layer Two Table (L2T) entries of the old
732 * filter rule. The firmware will handle freeing up any Source MAC
733 * Table (SMT) entries used for rewriting Source MAC Addresses in
737 cxgb4_l2t_release(f
->l2t
);
739 /* The zeroing of the filter rule below clears the filter valid,
740 * pending, locked flags, l2t pointer, etc. so it's all we need for
743 memset(f
, 0, sizeof(*f
));
746 /* Handle a filter write/deletion reply.
748 static void filter_rpl(struct adapter
*adap
, const struct cpl_set_tcb_rpl
*rpl
)
750 unsigned int idx
= GET_TID(rpl
);
751 unsigned int nidx
= idx
- adap
->tids
.ftid_base
;
753 struct filter_entry
*f
;
755 if (idx
>= adap
->tids
.ftid_base
&& nidx
<
756 (adap
->tids
.nftids
+ adap
->tids
.nsftids
)) {
758 ret
= GET_TCB_COOKIE(rpl
->cookie
);
759 f
= &adap
->tids
.ftid_tab
[idx
];
761 if (ret
== FW_FILTER_WR_FLT_DELETED
) {
762 /* Clear the filter when we get confirmation from the
763 * hardware that the filter has been deleted.
765 clear_filter(adap
, f
);
766 } else if (ret
== FW_FILTER_WR_SMT_TBL_FULL
) {
767 dev_err(adap
->pdev_dev
, "filter %u setup failed due to full SMT\n",
769 clear_filter(adap
, f
);
770 } else if (ret
== FW_FILTER_WR_FLT_ADDED
) {
771 f
->smtidx
= (be64_to_cpu(rpl
->oldval
) >> 24) & 0xff;
772 f
->pending
= 0; /* asynchronous setup completed */
775 /* Something went wrong. Issue a warning about the
776 * problem and clear everything out.
778 dev_err(adap
->pdev_dev
, "filter %u setup failed with error %u\n",
780 clear_filter(adap
, f
);
785 /* Response queue handler for the FW event queue.
787 static int fwevtq_handler(struct sge_rspq
*q
, const __be64
*rsp
,
788 const struct pkt_gl
*gl
)
790 u8 opcode
= ((const struct rss_header
*)rsp
)->opcode
;
792 rsp
++; /* skip RSS header */
794 /* FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG.
796 if (unlikely(opcode
== CPL_FW4_MSG
&&
797 ((const struct cpl_fw4_msg
*)rsp
)->type
== FW_TYPE_RSSCPL
)) {
799 opcode
= ((const struct rss_header
*)rsp
)->opcode
;
801 if (opcode
!= CPL_SGE_EGR_UPDATE
) {
802 dev_err(q
->adap
->pdev_dev
, "unexpected FW4/CPL %#x on FW event queue\n"
808 if (likely(opcode
== CPL_SGE_EGR_UPDATE
)) {
809 const struct cpl_sge_egr_update
*p
= (void *)rsp
;
810 unsigned int qid
= EGR_QID(ntohl(p
->opcode_qid
));
813 txq
= q
->adap
->sge
.egr_map
[qid
- q
->adap
->sge
.egr_start
];
815 if ((u8
*)txq
< (u8
*)q
->adap
->sge
.ofldtxq
) {
816 struct sge_eth_txq
*eq
;
818 eq
= container_of(txq
, struct sge_eth_txq
, q
);
819 netif_tx_wake_queue(eq
->txq
);
821 struct sge_ofld_txq
*oq
;
823 oq
= container_of(txq
, struct sge_ofld_txq
, q
);
824 tasklet_schedule(&oq
->qresume_tsk
);
826 } else if (opcode
== CPL_FW6_MSG
|| opcode
== CPL_FW4_MSG
) {
827 const struct cpl_fw6_msg
*p
= (void *)rsp
;
829 #ifdef CONFIG_CHELSIO_T4_DCB
830 const struct fw_port_cmd
*pcmd
= (const void *)p
->data
;
831 unsigned int cmd
= FW_CMD_OP_GET(ntohl(pcmd
->op_to_portid
));
832 unsigned int action
=
833 FW_PORT_CMD_ACTION_GET(ntohl(pcmd
->action_to_len16
));
835 if (cmd
== FW_PORT_CMD
&&
836 action
== FW_PORT_ACTION_GET_PORT_INFO
) {
837 int port
= FW_PORT_CMD_PORTID_GET(
838 be32_to_cpu(pcmd
->op_to_portid
));
839 struct net_device
*dev
= q
->adap
->port
[port
];
840 int state_input
= ((pcmd
->u
.info
.dcbxdis_pkd
&
842 ? CXGB4_DCB_INPUT_FW_DISABLED
843 : CXGB4_DCB_INPUT_FW_ENABLED
);
845 cxgb4_dcb_state_fsm(dev
, state_input
);
848 if (cmd
== FW_PORT_CMD
&&
849 action
== FW_PORT_ACTION_L2_DCB_CFG
)
850 dcb_rpl(q
->adap
, pcmd
);
854 t4_handle_fw_rpl(q
->adap
, p
->data
);
855 } else if (opcode
== CPL_L2T_WRITE_RPL
) {
856 const struct cpl_l2t_write_rpl
*p
= (void *)rsp
;
858 do_l2t_write_rpl(q
->adap
, p
);
859 } else if (opcode
== CPL_SET_TCB_RPL
) {
860 const struct cpl_set_tcb_rpl
*p
= (void *)rsp
;
862 filter_rpl(q
->adap
, p
);
864 dev_err(q
->adap
->pdev_dev
,
865 "unexpected CPL %#x on FW event queue\n", opcode
);
871 * uldrx_handler - response queue handler for ULD queues
872 * @q: the response queue that received the packet
873 * @rsp: the response queue descriptor holding the offload message
874 * @gl: the gather list of packet fragments
876 * Deliver an ingress offload packet to a ULD. All processing is done by
877 * the ULD, we just maintain statistics.
879 static int uldrx_handler(struct sge_rspq
*q
, const __be64
*rsp
,
880 const struct pkt_gl
*gl
)
882 struct sge_ofld_rxq
*rxq
= container_of(q
, struct sge_ofld_rxq
, rspq
);
884 /* FW can send CPLs encapsulated in a CPL_FW4_MSG.
886 if (((const struct rss_header
*)rsp
)->opcode
== CPL_FW4_MSG
&&
887 ((const struct cpl_fw4_msg
*)(rsp
+ 1))->type
== FW_TYPE_RSSCPL
)
890 if (ulds
[q
->uld
].rx_handler(q
->adap
->uld_handle
[q
->uld
], rsp
, gl
)) {
896 else if (gl
== CXGB4_MSG_AN
)
903 static void disable_msi(struct adapter
*adapter
)
905 if (adapter
->flags
& USING_MSIX
) {
906 pci_disable_msix(adapter
->pdev
);
907 adapter
->flags
&= ~USING_MSIX
;
908 } else if (adapter
->flags
& USING_MSI
) {
909 pci_disable_msi(adapter
->pdev
);
910 adapter
->flags
&= ~USING_MSI
;
915 * Interrupt handler for non-data events used with MSI-X.
917 static irqreturn_t
t4_nondata_intr(int irq
, void *cookie
)
919 struct adapter
*adap
= cookie
;
921 u32 v
= t4_read_reg(adap
, MYPF_REG(PL_PF_INT_CAUSE
));
924 t4_write_reg(adap
, MYPF_REG(PL_PF_INT_CAUSE
), v
);
926 t4_slow_intr_handler(adap
);
931 * Name the MSI-X interrupts.
933 static void name_msix_vecs(struct adapter
*adap
)
935 int i
, j
, msi_idx
= 2, n
= sizeof(adap
->msix_info
[0].desc
);
937 /* non-data interrupts */
938 snprintf(adap
->msix_info
[0].desc
, n
, "%s", adap
->port
[0]->name
);
941 snprintf(adap
->msix_info
[1].desc
, n
, "%s-FWeventq",
942 adap
->port
[0]->name
);
944 /* Ethernet queues */
945 for_each_port(adap
, j
) {
946 struct net_device
*d
= adap
->port
[j
];
947 const struct port_info
*pi
= netdev_priv(d
);
949 for (i
= 0; i
< pi
->nqsets
; i
++, msi_idx
++)
950 snprintf(adap
->msix_info
[msi_idx
].desc
, n
, "%s-Rx%d",
955 for_each_ofldrxq(&adap
->sge
, i
)
956 snprintf(adap
->msix_info
[msi_idx
++].desc
, n
, "%s-ofld%d",
957 adap
->port
[0]->name
, i
);
959 for_each_rdmarxq(&adap
->sge
, i
)
960 snprintf(adap
->msix_info
[msi_idx
++].desc
, n
, "%s-rdma%d",
961 adap
->port
[0]->name
, i
);
963 for_each_rdmaciq(&adap
->sge
, i
)
964 snprintf(adap
->msix_info
[msi_idx
++].desc
, n
, "%s-rdma-ciq%d",
965 adap
->port
[0]->name
, i
);
968 static int request_msix_queue_irqs(struct adapter
*adap
)
970 struct sge
*s
= &adap
->sge
;
971 int err
, ethqidx
, ofldqidx
= 0, rdmaqidx
= 0, rdmaciqqidx
= 0;
974 err
= request_irq(adap
->msix_info
[1].vec
, t4_sge_intr_msix
, 0,
975 adap
->msix_info
[1].desc
, &s
->fw_evtq
);
979 for_each_ethrxq(s
, ethqidx
) {
980 err
= request_irq(adap
->msix_info
[msi_index
].vec
,
982 adap
->msix_info
[msi_index
].desc
,
983 &s
->ethrxq
[ethqidx
].rspq
);
988 for_each_ofldrxq(s
, ofldqidx
) {
989 err
= request_irq(adap
->msix_info
[msi_index
].vec
,
991 adap
->msix_info
[msi_index
].desc
,
992 &s
->ofldrxq
[ofldqidx
].rspq
);
997 for_each_rdmarxq(s
, rdmaqidx
) {
998 err
= request_irq(adap
->msix_info
[msi_index
].vec
,
1000 adap
->msix_info
[msi_index
].desc
,
1001 &s
->rdmarxq
[rdmaqidx
].rspq
);
1006 for_each_rdmaciq(s
, rdmaciqqidx
) {
1007 err
= request_irq(adap
->msix_info
[msi_index
].vec
,
1008 t4_sge_intr_msix
, 0,
1009 adap
->msix_info
[msi_index
].desc
,
1010 &s
->rdmaciq
[rdmaciqqidx
].rspq
);
1018 while (--rdmaciqqidx
>= 0)
1019 free_irq(adap
->msix_info
[--msi_index
].vec
,
1020 &s
->rdmaciq
[rdmaciqqidx
].rspq
);
1021 while (--rdmaqidx
>= 0)
1022 free_irq(adap
->msix_info
[--msi_index
].vec
,
1023 &s
->rdmarxq
[rdmaqidx
].rspq
);
1024 while (--ofldqidx
>= 0)
1025 free_irq(adap
->msix_info
[--msi_index
].vec
,
1026 &s
->ofldrxq
[ofldqidx
].rspq
);
1027 while (--ethqidx
>= 0)
1028 free_irq(adap
->msix_info
[--msi_index
].vec
,
1029 &s
->ethrxq
[ethqidx
].rspq
);
1030 free_irq(adap
->msix_info
[1].vec
, &s
->fw_evtq
);
1034 static void free_msix_queue_irqs(struct adapter
*adap
)
1036 int i
, msi_index
= 2;
1037 struct sge
*s
= &adap
->sge
;
1039 free_irq(adap
->msix_info
[1].vec
, &s
->fw_evtq
);
1040 for_each_ethrxq(s
, i
)
1041 free_irq(adap
->msix_info
[msi_index
++].vec
, &s
->ethrxq
[i
].rspq
);
1042 for_each_ofldrxq(s
, i
)
1043 free_irq(adap
->msix_info
[msi_index
++].vec
, &s
->ofldrxq
[i
].rspq
);
1044 for_each_rdmarxq(s
, i
)
1045 free_irq(adap
->msix_info
[msi_index
++].vec
, &s
->rdmarxq
[i
].rspq
);
1046 for_each_rdmaciq(s
, i
)
1047 free_irq(adap
->msix_info
[msi_index
++].vec
, &s
->rdmaciq
[i
].rspq
);
1051 * write_rss - write the RSS table for a given port
1053 * @queues: array of queue indices for RSS
1055 * Sets up the portion of the HW RSS table for the port's VI to distribute
1056 * packets to the Rx queues in @queues.
1058 static int write_rss(const struct port_info
*pi
, const u16
*queues
)
1062 const struct sge_eth_rxq
*q
= &pi
->adapter
->sge
.ethrxq
[pi
->first_qset
];
1064 rss
= kmalloc(pi
->rss_size
* sizeof(u16
), GFP_KERNEL
);
1068 /* map the queue indices to queue ids */
1069 for (i
= 0; i
< pi
->rss_size
; i
++, queues
++)
1070 rss
[i
] = q
[*queues
].rspq
.abs_id
;
1072 err
= t4_config_rss_range(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, 0,
1073 pi
->rss_size
, rss
, pi
->rss_size
);
1079 * setup_rss - configure RSS
1080 * @adap: the adapter
1082 * Sets up RSS for each port.
1084 static int setup_rss(struct adapter
*adap
)
1088 for_each_port(adap
, i
) {
1089 const struct port_info
*pi
= adap2pinfo(adap
, i
);
1091 err
= write_rss(pi
, pi
->rss
);
1099 * Return the channel of the ingress queue with the given qid.
1101 static unsigned int rxq_to_chan(const struct sge
*p
, unsigned int qid
)
1103 qid
-= p
->ingr_start
;
1104 return netdev2pinfo(p
->ingr_map
[qid
]->netdev
)->tx_chan
;
1108 * Wait until all NAPI handlers are descheduled.
1110 static void quiesce_rx(struct adapter
*adap
)
1114 for (i
= 0; i
< ARRAY_SIZE(adap
->sge
.ingr_map
); i
++) {
1115 struct sge_rspq
*q
= adap
->sge
.ingr_map
[i
];
1117 if (q
&& q
->handler
)
1118 napi_disable(&q
->napi
);
1123 * Enable NAPI scheduling and interrupt generation for all Rx queues.
1125 static void enable_rx(struct adapter
*adap
)
1129 for (i
= 0; i
< ARRAY_SIZE(adap
->sge
.ingr_map
); i
++) {
1130 struct sge_rspq
*q
= adap
->sge
.ingr_map
[i
];
1135 napi_enable(&q
->napi
);
1136 /* 0-increment GTS to start the timer and enable interrupts */
1137 t4_write_reg(adap
, MYPF_REG(SGE_PF_GTS
),
1138 SEINTARM(q
->intr_params
) |
1139 INGRESSQID(q
->cntxt_id
));
1144 * setup_sge_queues - configure SGE Tx/Rx/response queues
1145 * @adap: the adapter
1147 * Determines how many sets of SGE queues to use and initializes them.
1148 * We support multiple queue sets per port if we have MSI-X, otherwise
1149 * just one queue set per port.
1151 static int setup_sge_queues(struct adapter
*adap
)
1153 int err
, msi_idx
, i
, j
;
1154 struct sge
*s
= &adap
->sge
;
1156 bitmap_zero(s
->starving_fl
, MAX_EGRQ
);
1157 bitmap_zero(s
->txq_maperr
, MAX_EGRQ
);
1159 if (adap
->flags
& USING_MSIX
)
1160 msi_idx
= 1; /* vector 0 is for non-queue interrupts */
1162 err
= t4_sge_alloc_rxq(adap
, &s
->intrq
, false, adap
->port
[0], 0,
1166 msi_idx
= -((int)s
->intrq
.abs_id
+ 1);
1169 err
= t4_sge_alloc_rxq(adap
, &s
->fw_evtq
, true, adap
->port
[0],
1170 msi_idx
, NULL
, fwevtq_handler
);
1172 freeout
: t4_free_sge_resources(adap
);
1176 for_each_port(adap
, i
) {
1177 struct net_device
*dev
= adap
->port
[i
];
1178 struct port_info
*pi
= netdev_priv(dev
);
1179 struct sge_eth_rxq
*q
= &s
->ethrxq
[pi
->first_qset
];
1180 struct sge_eth_txq
*t
= &s
->ethtxq
[pi
->first_qset
];
1182 for (j
= 0; j
< pi
->nqsets
; j
++, q
++) {
1185 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, dev
,
1191 memset(&q
->stats
, 0, sizeof(q
->stats
));
1193 for (j
= 0; j
< pi
->nqsets
; j
++, t
++) {
1194 err
= t4_sge_alloc_eth_txq(adap
, t
, dev
,
1195 netdev_get_tx_queue(dev
, j
),
1196 s
->fw_evtq
.cntxt_id
);
1202 j
= s
->ofldqsets
/ adap
->params
.nports
; /* ofld queues per channel */
1203 for_each_ofldrxq(s
, i
) {
1204 struct sge_ofld_rxq
*q
= &s
->ofldrxq
[i
];
1205 struct net_device
*dev
= adap
->port
[i
/ j
];
1209 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, dev
, msi_idx
,
1210 q
->fl
.size
? &q
->fl
: NULL
,
1214 memset(&q
->stats
, 0, sizeof(q
->stats
));
1215 s
->ofld_rxq
[i
] = q
->rspq
.abs_id
;
1216 err
= t4_sge_alloc_ofld_txq(adap
, &s
->ofldtxq
[i
], dev
,
1217 s
->fw_evtq
.cntxt_id
);
1222 for_each_rdmarxq(s
, i
) {
1223 struct sge_ofld_rxq
*q
= &s
->rdmarxq
[i
];
1227 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, adap
->port
[i
],
1228 msi_idx
, q
->fl
.size
? &q
->fl
: NULL
,
1232 memset(&q
->stats
, 0, sizeof(q
->stats
));
1233 s
->rdma_rxq
[i
] = q
->rspq
.abs_id
;
1236 for_each_rdmaciq(s
, i
) {
1237 struct sge_ofld_rxq
*q
= &s
->rdmaciq
[i
];
1241 err
= t4_sge_alloc_rxq(adap
, &q
->rspq
, false, adap
->port
[i
],
1242 msi_idx
, q
->fl
.size
? &q
->fl
: NULL
,
1246 memset(&q
->stats
, 0, sizeof(q
->stats
));
1247 s
->rdma_ciq
[i
] = q
->rspq
.abs_id
;
1250 for_each_port(adap
, i
) {
1252 * Note that ->rdmarxq[i].rspq.cntxt_id below is 0 if we don't
1253 * have RDMA queues, and that's the right value.
1255 err
= t4_sge_alloc_ctrl_txq(adap
, &s
->ctrlq
[i
], adap
->port
[i
],
1256 s
->fw_evtq
.cntxt_id
,
1257 s
->rdmarxq
[i
].rspq
.cntxt_id
);
1262 t4_write_reg(adap
, is_t4(adap
->params
.chip
) ?
1263 MPS_TRC_RSS_CONTROL
:
1264 MPS_T5_TRC_RSS_CONTROL
,
1265 RSSCONTROL(netdev2pinfo(adap
->port
[0])->tx_chan
) |
1266 QUEUENUMBER(s
->ethrxq
[0].rspq
.abs_id
));
1271 * Allocate a chunk of memory using kmalloc or, if that fails, vmalloc.
1272 * The allocated memory is cleared.
1274 void *t4_alloc_mem(size_t size
)
1276 void *p
= kzalloc(size
, GFP_KERNEL
| __GFP_NOWARN
);
1284 * Free memory allocated through alloc_mem().
1286 static void t4_free_mem(void *addr
)
1288 if (is_vmalloc_addr(addr
))
1294 /* Send a Work Request to write the filter at a specified index. We construct
1295 * a Firmware Filter Work Request to have the work done and put the indicated
1296 * filter into "pending" mode which will prevent any further actions against
1297 * it till we get a reply from the firmware on the completion status of the
1300 static int set_filter_wr(struct adapter
*adapter
, int fidx
)
1302 struct filter_entry
*f
= &adapter
->tids
.ftid_tab
[fidx
];
1303 struct sk_buff
*skb
;
1304 struct fw_filter_wr
*fwr
;
1307 /* If the new filter requires loopback Destination MAC and/or VLAN
1308 * rewriting then we need to allocate a Layer 2 Table (L2T) entry for
1311 if (f
->fs
.newdmac
|| f
->fs
.newvlan
) {
1312 /* allocate L2T entry for new filter */
1313 f
->l2t
= t4_l2t_alloc_switching(adapter
->l2t
);
1316 if (t4_l2t_set_switching(adapter
, f
->l2t
, f
->fs
.vlan
,
1317 f
->fs
.eport
, f
->fs
.dmac
)) {
1318 cxgb4_l2t_release(f
->l2t
);
1324 ftid
= adapter
->tids
.ftid_base
+ fidx
;
1326 skb
= alloc_skb(sizeof(*fwr
), GFP_KERNEL
| __GFP_NOFAIL
);
1327 fwr
= (struct fw_filter_wr
*)__skb_put(skb
, sizeof(*fwr
));
1328 memset(fwr
, 0, sizeof(*fwr
));
1330 /* It would be nice to put most of the following in t4_hw.c but most
1331 * of the work is translating the cxgbtool ch_filter_specification
1332 * into the Work Request and the definition of that structure is
1333 * currently in cxgbtool.h which isn't appropriate to pull into the
1334 * common code. We may eventually try to come up with a more neutral
1335 * filter specification structure but for now it's easiest to simply
1336 * put this fairly direct code in line ...
1338 fwr
->op_pkd
= htonl(FW_WR_OP(FW_FILTER_WR
));
1339 fwr
->len16_pkd
= htonl(FW_WR_LEN16(sizeof(*fwr
)/16));
1341 htonl(V_FW_FILTER_WR_TID(ftid
) |
1342 V_FW_FILTER_WR_RQTYPE(f
->fs
.type
) |
1343 V_FW_FILTER_WR_NOREPLY(0) |
1344 V_FW_FILTER_WR_IQ(f
->fs
.iq
));
1345 fwr
->del_filter_to_l2tix
=
1346 htonl(V_FW_FILTER_WR_RPTTID(f
->fs
.rpttid
) |
1347 V_FW_FILTER_WR_DROP(f
->fs
.action
== FILTER_DROP
) |
1348 V_FW_FILTER_WR_DIRSTEER(f
->fs
.dirsteer
) |
1349 V_FW_FILTER_WR_MASKHASH(f
->fs
.maskhash
) |
1350 V_FW_FILTER_WR_DIRSTEERHASH(f
->fs
.dirsteerhash
) |
1351 V_FW_FILTER_WR_LPBK(f
->fs
.action
== FILTER_SWITCH
) |
1352 V_FW_FILTER_WR_DMAC(f
->fs
.newdmac
) |
1353 V_FW_FILTER_WR_SMAC(f
->fs
.newsmac
) |
1354 V_FW_FILTER_WR_INSVLAN(f
->fs
.newvlan
== VLAN_INSERT
||
1355 f
->fs
.newvlan
== VLAN_REWRITE
) |
1356 V_FW_FILTER_WR_RMVLAN(f
->fs
.newvlan
== VLAN_REMOVE
||
1357 f
->fs
.newvlan
== VLAN_REWRITE
) |
1358 V_FW_FILTER_WR_HITCNTS(f
->fs
.hitcnts
) |
1359 V_FW_FILTER_WR_TXCHAN(f
->fs
.eport
) |
1360 V_FW_FILTER_WR_PRIO(f
->fs
.prio
) |
1361 V_FW_FILTER_WR_L2TIX(f
->l2t
? f
->l2t
->idx
: 0));
1362 fwr
->ethtype
= htons(f
->fs
.val
.ethtype
);
1363 fwr
->ethtypem
= htons(f
->fs
.mask
.ethtype
);
1364 fwr
->frag_to_ovlan_vldm
=
1365 (V_FW_FILTER_WR_FRAG(f
->fs
.val
.frag
) |
1366 V_FW_FILTER_WR_FRAGM(f
->fs
.mask
.frag
) |
1367 V_FW_FILTER_WR_IVLAN_VLD(f
->fs
.val
.ivlan_vld
) |
1368 V_FW_FILTER_WR_OVLAN_VLD(f
->fs
.val
.ovlan_vld
) |
1369 V_FW_FILTER_WR_IVLAN_VLDM(f
->fs
.mask
.ivlan_vld
) |
1370 V_FW_FILTER_WR_OVLAN_VLDM(f
->fs
.mask
.ovlan_vld
));
1372 fwr
->rx_chan_rx_rpl_iq
=
1373 htons(V_FW_FILTER_WR_RX_CHAN(0) |
1374 V_FW_FILTER_WR_RX_RPL_IQ(adapter
->sge
.fw_evtq
.abs_id
));
1375 fwr
->maci_to_matchtypem
=
1376 htonl(V_FW_FILTER_WR_MACI(f
->fs
.val
.macidx
) |
1377 V_FW_FILTER_WR_MACIM(f
->fs
.mask
.macidx
) |
1378 V_FW_FILTER_WR_FCOE(f
->fs
.val
.fcoe
) |
1379 V_FW_FILTER_WR_FCOEM(f
->fs
.mask
.fcoe
) |
1380 V_FW_FILTER_WR_PORT(f
->fs
.val
.iport
) |
1381 V_FW_FILTER_WR_PORTM(f
->fs
.mask
.iport
) |
1382 V_FW_FILTER_WR_MATCHTYPE(f
->fs
.val
.matchtype
) |
1383 V_FW_FILTER_WR_MATCHTYPEM(f
->fs
.mask
.matchtype
));
1384 fwr
->ptcl
= f
->fs
.val
.proto
;
1385 fwr
->ptclm
= f
->fs
.mask
.proto
;
1386 fwr
->ttyp
= f
->fs
.val
.tos
;
1387 fwr
->ttypm
= f
->fs
.mask
.tos
;
1388 fwr
->ivlan
= htons(f
->fs
.val
.ivlan
);
1389 fwr
->ivlanm
= htons(f
->fs
.mask
.ivlan
);
1390 fwr
->ovlan
= htons(f
->fs
.val
.ovlan
);
1391 fwr
->ovlanm
= htons(f
->fs
.mask
.ovlan
);
1392 memcpy(fwr
->lip
, f
->fs
.val
.lip
, sizeof(fwr
->lip
));
1393 memcpy(fwr
->lipm
, f
->fs
.mask
.lip
, sizeof(fwr
->lipm
));
1394 memcpy(fwr
->fip
, f
->fs
.val
.fip
, sizeof(fwr
->fip
));
1395 memcpy(fwr
->fipm
, f
->fs
.mask
.fip
, sizeof(fwr
->fipm
));
1396 fwr
->lp
= htons(f
->fs
.val
.lport
);
1397 fwr
->lpm
= htons(f
->fs
.mask
.lport
);
1398 fwr
->fp
= htons(f
->fs
.val
.fport
);
1399 fwr
->fpm
= htons(f
->fs
.mask
.fport
);
1401 memcpy(fwr
->sma
, f
->fs
.smac
, sizeof(fwr
->sma
));
1403 /* Mark the filter as "pending" and ship off the Filter Work Request.
1404 * When we get the Work Request Reply we'll clear the pending status.
1407 set_wr_txq(skb
, CPL_PRIORITY_CONTROL
, f
->fs
.val
.iport
& 0x3);
1408 t4_ofld_send(adapter
, skb
);
1412 /* Delete the filter at a specified index.
1414 static int del_filter_wr(struct adapter
*adapter
, int fidx
)
1416 struct filter_entry
*f
= &adapter
->tids
.ftid_tab
[fidx
];
1417 struct sk_buff
*skb
;
1418 struct fw_filter_wr
*fwr
;
1419 unsigned int len
, ftid
;
1422 ftid
= adapter
->tids
.ftid_base
+ fidx
;
1424 skb
= alloc_skb(len
, GFP_KERNEL
| __GFP_NOFAIL
);
1425 fwr
= (struct fw_filter_wr
*)__skb_put(skb
, len
);
1426 t4_mk_filtdelwr(ftid
, fwr
, adapter
->sge
.fw_evtq
.abs_id
);
1428 /* Mark the filter as "pending" and ship off the Filter Work Request.
1429 * When we get the Work Request Reply we'll clear the pending status.
1432 t4_mgmt_tx(adapter
, skb
);
1436 static u16
cxgb_select_queue(struct net_device
*dev
, struct sk_buff
*skb
,
1437 void *accel_priv
, select_queue_fallback_t fallback
)
1441 #ifdef CONFIG_CHELSIO_T4_DCB
1442 /* If a Data Center Bridging has been successfully negotiated on this
1443 * link then we'll use the skb's priority to map it to a TX Queue.
1444 * The skb's priority is determined via the VLAN Tag Priority Code
1447 if (cxgb4_dcb_enabled(dev
)) {
1451 err
= vlan_get_tag(skb
, &vlan_tci
);
1452 if (unlikely(err
)) {
1453 if (net_ratelimit())
1455 "TX Packet without VLAN Tag on DCB Link\n");
1458 txq
= (vlan_tci
& VLAN_PRIO_MASK
) >> VLAN_PRIO_SHIFT
;
1462 #endif /* CONFIG_CHELSIO_T4_DCB */
1465 txq
= (skb_rx_queue_recorded(skb
)
1466 ? skb_get_rx_queue(skb
)
1467 : smp_processor_id());
1469 while (unlikely(txq
>= dev
->real_num_tx_queues
))
1470 txq
-= dev
->real_num_tx_queues
;
1475 return fallback(dev
, skb
) % dev
->real_num_tx_queues
;
1478 static inline int is_offload(const struct adapter
*adap
)
1480 return adap
->params
.offload
;
1484 * Implementation of ethtool operations.
1487 static u32
get_msglevel(struct net_device
*dev
)
1489 return netdev2adap(dev
)->msg_enable
;
1492 static void set_msglevel(struct net_device
*dev
, u32 val
)
1494 netdev2adap(dev
)->msg_enable
= val
;
1497 static char stats_strings
[][ETH_GSTRING_LEN
] = {
1500 "TxBroadcastFrames ",
1501 "TxMulticastFrames ",
1507 "TxFrames128To255 ",
1508 "TxFrames256To511 ",
1509 "TxFrames512To1023 ",
1510 "TxFrames1024To1518 ",
1511 "TxFrames1519ToMax ",
1526 "RxBroadcastFrames ",
1527 "RxMulticastFrames ",
1539 "RxFrames128To255 ",
1540 "RxFrames256To511 ",
1541 "RxFrames512To1023 ",
1542 "RxFrames1024To1518 ",
1543 "RxFrames1519ToMax ",
1555 "RxBG0FramesDropped ",
1556 "RxBG1FramesDropped ",
1557 "RxBG2FramesDropped ",
1558 "RxBG3FramesDropped ",
1559 "RxBG0FramesTrunc ",
1560 "RxBG1FramesTrunc ",
1561 "RxBG2FramesTrunc ",
1562 "RxBG3FramesTrunc ",
1571 "WriteCoalSuccess ",
1575 static int get_sset_count(struct net_device
*dev
, int sset
)
1579 return ARRAY_SIZE(stats_strings
);
1585 #define T4_REGMAP_SIZE (160 * 1024)
1586 #define T5_REGMAP_SIZE (332 * 1024)
1588 static int get_regs_len(struct net_device
*dev
)
1590 struct adapter
*adap
= netdev2adap(dev
);
1591 if (is_t4(adap
->params
.chip
))
1592 return T4_REGMAP_SIZE
;
1594 return T5_REGMAP_SIZE
;
1597 static int get_eeprom_len(struct net_device
*dev
)
1602 static void get_drvinfo(struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1604 struct adapter
*adapter
= netdev2adap(dev
);
1606 strlcpy(info
->driver
, KBUILD_MODNAME
, sizeof(info
->driver
));
1607 strlcpy(info
->version
, DRV_VERSION
, sizeof(info
->version
));
1608 strlcpy(info
->bus_info
, pci_name(adapter
->pdev
),
1609 sizeof(info
->bus_info
));
1611 if (adapter
->params
.fw_vers
)
1612 snprintf(info
->fw_version
, sizeof(info
->fw_version
),
1613 "%u.%u.%u.%u, TP %u.%u.%u.%u",
1614 FW_HDR_FW_VER_MAJOR_GET(adapter
->params
.fw_vers
),
1615 FW_HDR_FW_VER_MINOR_GET(adapter
->params
.fw_vers
),
1616 FW_HDR_FW_VER_MICRO_GET(adapter
->params
.fw_vers
),
1617 FW_HDR_FW_VER_BUILD_GET(adapter
->params
.fw_vers
),
1618 FW_HDR_FW_VER_MAJOR_GET(adapter
->params
.tp_vers
),
1619 FW_HDR_FW_VER_MINOR_GET(adapter
->params
.tp_vers
),
1620 FW_HDR_FW_VER_MICRO_GET(adapter
->params
.tp_vers
),
1621 FW_HDR_FW_VER_BUILD_GET(adapter
->params
.tp_vers
));
1624 static void get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1626 if (stringset
== ETH_SS_STATS
)
1627 memcpy(data
, stats_strings
, sizeof(stats_strings
));
1631 * port stats maintained per queue of the port. They should be in the same
1632 * order as in stats_strings above.
1634 struct queue_port_stats
{
1644 static void collect_sge_port_stats(const struct adapter
*adap
,
1645 const struct port_info
*p
, struct queue_port_stats
*s
)
1648 const struct sge_eth_txq
*tx
= &adap
->sge
.ethtxq
[p
->first_qset
];
1649 const struct sge_eth_rxq
*rx
= &adap
->sge
.ethrxq
[p
->first_qset
];
1651 memset(s
, 0, sizeof(*s
));
1652 for (i
= 0; i
< p
->nqsets
; i
++, rx
++, tx
++) {
1654 s
->tx_csum
+= tx
->tx_cso
;
1655 s
->rx_csum
+= rx
->stats
.rx_cso
;
1656 s
->vlan_ex
+= rx
->stats
.vlan_ex
;
1657 s
->vlan_ins
+= tx
->vlan_ins
;
1658 s
->gro_pkts
+= rx
->stats
.lro_pkts
;
1659 s
->gro_merged
+= rx
->stats
.lro_merged
;
1663 static void get_stats(struct net_device
*dev
, struct ethtool_stats
*stats
,
1666 struct port_info
*pi
= netdev_priv(dev
);
1667 struct adapter
*adapter
= pi
->adapter
;
1670 t4_get_port_stats(adapter
, pi
->tx_chan
, (struct port_stats
*)data
);
1672 data
+= sizeof(struct port_stats
) / sizeof(u64
);
1673 collect_sge_port_stats(adapter
, pi
, (struct queue_port_stats
*)data
);
1674 data
+= sizeof(struct queue_port_stats
) / sizeof(u64
);
1675 if (!is_t4(adapter
->params
.chip
)) {
1676 t4_write_reg(adapter
, SGE_STAT_CFG
, STATSOURCE_T5(7));
1677 val1
= t4_read_reg(adapter
, SGE_STAT_TOTAL
);
1678 val2
= t4_read_reg(adapter
, SGE_STAT_MATCH
);
1679 *data
= val1
- val2
;
1684 memset(data
, 0, 2 * sizeof(u64
));
1690 * Return a version number to identify the type of adapter. The scheme is:
1691 * - bits 0..9: chip version
1692 * - bits 10..15: chip revision
1693 * - bits 16..23: register dump version
1695 static inline unsigned int mk_adap_vers(const struct adapter
*ap
)
1697 return CHELSIO_CHIP_VERSION(ap
->params
.chip
) |
1698 (CHELSIO_CHIP_RELEASE(ap
->params
.chip
) << 10) | (1 << 16);
1701 static void reg_block_dump(struct adapter
*ap
, void *buf
, unsigned int start
,
1704 u32
*p
= buf
+ start
;
1706 for ( ; start
<= end
; start
+= sizeof(u32
))
1707 *p
++ = t4_read_reg(ap
, start
);
1710 static void get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
1713 static const unsigned int t4_reg_ranges
[] = {
1934 static const unsigned int t5_reg_ranges
[] = {
2363 struct adapter
*ap
= netdev2adap(dev
);
2364 static const unsigned int *reg_ranges
;
2365 int arr_size
= 0, buf_size
= 0;
2367 if (is_t4(ap
->params
.chip
)) {
2368 reg_ranges
= &t4_reg_ranges
[0];
2369 arr_size
= ARRAY_SIZE(t4_reg_ranges
);
2370 buf_size
= T4_REGMAP_SIZE
;
2372 reg_ranges
= &t5_reg_ranges
[0];
2373 arr_size
= ARRAY_SIZE(t5_reg_ranges
);
2374 buf_size
= T5_REGMAP_SIZE
;
2377 regs
->version
= mk_adap_vers(ap
);
2379 memset(buf
, 0, buf_size
);
2380 for (i
= 0; i
< arr_size
; i
+= 2)
2381 reg_block_dump(ap
, buf
, reg_ranges
[i
], reg_ranges
[i
+ 1]);
2384 static int restart_autoneg(struct net_device
*dev
)
2386 struct port_info
*p
= netdev_priv(dev
);
2388 if (!netif_running(dev
))
2390 if (p
->link_cfg
.autoneg
!= AUTONEG_ENABLE
)
2392 t4_restart_aneg(p
->adapter
, p
->adapter
->fn
, p
->tx_chan
);
2396 static int identify_port(struct net_device
*dev
,
2397 enum ethtool_phys_id_state state
)
2400 struct adapter
*adap
= netdev2adap(dev
);
2402 if (state
== ETHTOOL_ID_ACTIVE
)
2404 else if (state
== ETHTOOL_ID_INACTIVE
)
2409 return t4_identify_port(adap
, adap
->fn
, netdev2pinfo(dev
)->viid
, val
);
2412 static unsigned int from_fw_linkcaps(unsigned int type
, unsigned int caps
)
2416 if (type
== FW_PORT_TYPE_BT_SGMII
|| type
== FW_PORT_TYPE_BT_XFI
||
2417 type
== FW_PORT_TYPE_BT_XAUI
) {
2419 if (caps
& FW_PORT_CAP_SPEED_100M
)
2420 v
|= SUPPORTED_100baseT_Full
;
2421 if (caps
& FW_PORT_CAP_SPEED_1G
)
2422 v
|= SUPPORTED_1000baseT_Full
;
2423 if (caps
& FW_PORT_CAP_SPEED_10G
)
2424 v
|= SUPPORTED_10000baseT_Full
;
2425 } else if (type
== FW_PORT_TYPE_KX4
|| type
== FW_PORT_TYPE_KX
) {
2426 v
|= SUPPORTED_Backplane
;
2427 if (caps
& FW_PORT_CAP_SPEED_1G
)
2428 v
|= SUPPORTED_1000baseKX_Full
;
2429 if (caps
& FW_PORT_CAP_SPEED_10G
)
2430 v
|= SUPPORTED_10000baseKX4_Full
;
2431 } else if (type
== FW_PORT_TYPE_KR
)
2432 v
|= SUPPORTED_Backplane
| SUPPORTED_10000baseKR_Full
;
2433 else if (type
== FW_PORT_TYPE_BP_AP
)
2434 v
|= SUPPORTED_Backplane
| SUPPORTED_10000baseR_FEC
|
2435 SUPPORTED_10000baseKR_Full
| SUPPORTED_1000baseKX_Full
;
2436 else if (type
== FW_PORT_TYPE_BP4_AP
)
2437 v
|= SUPPORTED_Backplane
| SUPPORTED_10000baseR_FEC
|
2438 SUPPORTED_10000baseKR_Full
| SUPPORTED_1000baseKX_Full
|
2439 SUPPORTED_10000baseKX4_Full
;
2440 else if (type
== FW_PORT_TYPE_FIBER_XFI
||
2441 type
== FW_PORT_TYPE_FIBER_XAUI
|| type
== FW_PORT_TYPE_SFP
)
2442 v
|= SUPPORTED_FIBRE
;
2443 else if (type
== FW_PORT_TYPE_BP40_BA
)
2444 v
|= SUPPORTED_40000baseSR4_Full
;
2446 if (caps
& FW_PORT_CAP_ANEG
)
2447 v
|= SUPPORTED_Autoneg
;
2451 static unsigned int to_fw_linkcaps(unsigned int caps
)
2455 if (caps
& ADVERTISED_100baseT_Full
)
2456 v
|= FW_PORT_CAP_SPEED_100M
;
2457 if (caps
& ADVERTISED_1000baseT_Full
)
2458 v
|= FW_PORT_CAP_SPEED_1G
;
2459 if (caps
& ADVERTISED_10000baseT_Full
)
2460 v
|= FW_PORT_CAP_SPEED_10G
;
2461 if (caps
& ADVERTISED_40000baseSR4_Full
)
2462 v
|= FW_PORT_CAP_SPEED_40G
;
2466 static int get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2468 const struct port_info
*p
= netdev_priv(dev
);
2470 if (p
->port_type
== FW_PORT_TYPE_BT_SGMII
||
2471 p
->port_type
== FW_PORT_TYPE_BT_XFI
||
2472 p
->port_type
== FW_PORT_TYPE_BT_XAUI
)
2473 cmd
->port
= PORT_TP
;
2474 else if (p
->port_type
== FW_PORT_TYPE_FIBER_XFI
||
2475 p
->port_type
== FW_PORT_TYPE_FIBER_XAUI
)
2476 cmd
->port
= PORT_FIBRE
;
2477 else if (p
->port_type
== FW_PORT_TYPE_SFP
||
2478 p
->port_type
== FW_PORT_TYPE_QSFP_10G
||
2479 p
->port_type
== FW_PORT_TYPE_QSFP
) {
2480 if (p
->mod_type
== FW_PORT_MOD_TYPE_LR
||
2481 p
->mod_type
== FW_PORT_MOD_TYPE_SR
||
2482 p
->mod_type
== FW_PORT_MOD_TYPE_ER
||
2483 p
->mod_type
== FW_PORT_MOD_TYPE_LRM
)
2484 cmd
->port
= PORT_FIBRE
;
2485 else if (p
->mod_type
== FW_PORT_MOD_TYPE_TWINAX_PASSIVE
||
2486 p
->mod_type
== FW_PORT_MOD_TYPE_TWINAX_ACTIVE
)
2487 cmd
->port
= PORT_DA
;
2489 cmd
->port
= PORT_OTHER
;
2491 cmd
->port
= PORT_OTHER
;
2493 if (p
->mdio_addr
>= 0) {
2494 cmd
->phy_address
= p
->mdio_addr
;
2495 cmd
->transceiver
= XCVR_EXTERNAL
;
2496 cmd
->mdio_support
= p
->port_type
== FW_PORT_TYPE_BT_SGMII
?
2497 MDIO_SUPPORTS_C22
: MDIO_SUPPORTS_C45
;
2499 cmd
->phy_address
= 0; /* not really, but no better option */
2500 cmd
->transceiver
= XCVR_INTERNAL
;
2501 cmd
->mdio_support
= 0;
2504 cmd
->supported
= from_fw_linkcaps(p
->port_type
, p
->link_cfg
.supported
);
2505 cmd
->advertising
= from_fw_linkcaps(p
->port_type
,
2506 p
->link_cfg
.advertising
);
2507 ethtool_cmd_speed_set(cmd
,
2508 netif_carrier_ok(dev
) ? p
->link_cfg
.speed
: 0);
2509 cmd
->duplex
= DUPLEX_FULL
;
2510 cmd
->autoneg
= p
->link_cfg
.autoneg
;
2516 static unsigned int speed_to_caps(int speed
)
2519 return FW_PORT_CAP_SPEED_100M
;
2521 return FW_PORT_CAP_SPEED_1G
;
2523 return FW_PORT_CAP_SPEED_10G
;
2525 return FW_PORT_CAP_SPEED_40G
;
2529 static int set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
2532 struct port_info
*p
= netdev_priv(dev
);
2533 struct link_config
*lc
= &p
->link_cfg
;
2534 u32 speed
= ethtool_cmd_speed(cmd
);
2536 if (cmd
->duplex
!= DUPLEX_FULL
) /* only full-duplex supported */
2539 if (!(lc
->supported
& FW_PORT_CAP_ANEG
)) {
2541 * PHY offers a single speed. See if that's what's
2544 if (cmd
->autoneg
== AUTONEG_DISABLE
&&
2545 (lc
->supported
& speed_to_caps(speed
)))
2550 if (cmd
->autoneg
== AUTONEG_DISABLE
) {
2551 cap
= speed_to_caps(speed
);
2553 if (!(lc
->supported
& cap
) ||
2558 lc
->requested_speed
= cap
;
2559 lc
->advertising
= 0;
2561 cap
= to_fw_linkcaps(cmd
->advertising
);
2562 if (!(lc
->supported
& cap
))
2564 lc
->requested_speed
= 0;
2565 lc
->advertising
= cap
| FW_PORT_CAP_ANEG
;
2567 lc
->autoneg
= cmd
->autoneg
;
2569 if (netif_running(dev
))
2570 return t4_link_start(p
->adapter
, p
->adapter
->fn
, p
->tx_chan
,
2575 static void get_pauseparam(struct net_device
*dev
,
2576 struct ethtool_pauseparam
*epause
)
2578 struct port_info
*p
= netdev_priv(dev
);
2580 epause
->autoneg
= (p
->link_cfg
.requested_fc
& PAUSE_AUTONEG
) != 0;
2581 epause
->rx_pause
= (p
->link_cfg
.fc
& PAUSE_RX
) != 0;
2582 epause
->tx_pause
= (p
->link_cfg
.fc
& PAUSE_TX
) != 0;
2585 static int set_pauseparam(struct net_device
*dev
,
2586 struct ethtool_pauseparam
*epause
)
2588 struct port_info
*p
= netdev_priv(dev
);
2589 struct link_config
*lc
= &p
->link_cfg
;
2591 if (epause
->autoneg
== AUTONEG_DISABLE
)
2592 lc
->requested_fc
= 0;
2593 else if (lc
->supported
& FW_PORT_CAP_ANEG
)
2594 lc
->requested_fc
= PAUSE_AUTONEG
;
2598 if (epause
->rx_pause
)
2599 lc
->requested_fc
|= PAUSE_RX
;
2600 if (epause
->tx_pause
)
2601 lc
->requested_fc
|= PAUSE_TX
;
2602 if (netif_running(dev
))
2603 return t4_link_start(p
->adapter
, p
->adapter
->fn
, p
->tx_chan
,
2608 static void get_sge_param(struct net_device
*dev
, struct ethtool_ringparam
*e
)
2610 const struct port_info
*pi
= netdev_priv(dev
);
2611 const struct sge
*s
= &pi
->adapter
->sge
;
2613 e
->rx_max_pending
= MAX_RX_BUFFERS
;
2614 e
->rx_mini_max_pending
= MAX_RSPQ_ENTRIES
;
2615 e
->rx_jumbo_max_pending
= 0;
2616 e
->tx_max_pending
= MAX_TXQ_ENTRIES
;
2618 e
->rx_pending
= s
->ethrxq
[pi
->first_qset
].fl
.size
- 8;
2619 e
->rx_mini_pending
= s
->ethrxq
[pi
->first_qset
].rspq
.size
;
2620 e
->rx_jumbo_pending
= 0;
2621 e
->tx_pending
= s
->ethtxq
[pi
->first_qset
].q
.size
;
2624 static int set_sge_param(struct net_device
*dev
, struct ethtool_ringparam
*e
)
2627 const struct port_info
*pi
= netdev_priv(dev
);
2628 struct adapter
*adapter
= pi
->adapter
;
2629 struct sge
*s
= &adapter
->sge
;
2631 if (e
->rx_pending
> MAX_RX_BUFFERS
|| e
->rx_jumbo_pending
||
2632 e
->tx_pending
> MAX_TXQ_ENTRIES
||
2633 e
->rx_mini_pending
> MAX_RSPQ_ENTRIES
||
2634 e
->rx_mini_pending
< MIN_RSPQ_ENTRIES
||
2635 e
->rx_pending
< MIN_FL_ENTRIES
|| e
->tx_pending
< MIN_TXQ_ENTRIES
)
2638 if (adapter
->flags
& FULL_INIT_DONE
)
2641 for (i
= 0; i
< pi
->nqsets
; ++i
) {
2642 s
->ethtxq
[pi
->first_qset
+ i
].q
.size
= e
->tx_pending
;
2643 s
->ethrxq
[pi
->first_qset
+ i
].fl
.size
= e
->rx_pending
+ 8;
2644 s
->ethrxq
[pi
->first_qset
+ i
].rspq
.size
= e
->rx_mini_pending
;
2649 static int closest_timer(const struct sge
*s
, int time
)
2651 int i
, delta
, match
= 0, min_delta
= INT_MAX
;
2653 for (i
= 0; i
< ARRAY_SIZE(s
->timer_val
); i
++) {
2654 delta
= time
- s
->timer_val
[i
];
2657 if (delta
< min_delta
) {
2665 static int closest_thres(const struct sge
*s
, int thres
)
2667 int i
, delta
, match
= 0, min_delta
= INT_MAX
;
2669 for (i
= 0; i
< ARRAY_SIZE(s
->counter_val
); i
++) {
2670 delta
= thres
- s
->counter_val
[i
];
2673 if (delta
< min_delta
) {
2682 * Return a queue's interrupt hold-off time in us. 0 means no timer.
2684 static unsigned int qtimer_val(const struct adapter
*adap
,
2685 const struct sge_rspq
*q
)
2687 unsigned int idx
= q
->intr_params
>> 1;
2689 return idx
< SGE_NTIMERS
? adap
->sge
.timer_val
[idx
] : 0;
2693 * set_rspq_intr_params - set a queue's interrupt holdoff parameters
2695 * @us: the hold-off time in us, or 0 to disable timer
2696 * @cnt: the hold-off packet count, or 0 to disable counter
2698 * Sets an Rx queue's interrupt hold-off time and packet count. At least
2699 * one of the two needs to be enabled for the queue to generate interrupts.
2701 static int set_rspq_intr_params(struct sge_rspq
*q
,
2702 unsigned int us
, unsigned int cnt
)
2704 struct adapter
*adap
= q
->adap
;
2706 if ((us
| cnt
) == 0)
2713 new_idx
= closest_thres(&adap
->sge
, cnt
);
2714 if (q
->desc
&& q
->pktcnt_idx
!= new_idx
) {
2715 /* the queue has already been created, update it */
2716 v
= FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ
) |
2717 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH
) |
2718 FW_PARAMS_PARAM_YZ(q
->cntxt_id
);
2719 err
= t4_set_params(adap
, adap
->fn
, adap
->fn
, 0, 1, &v
,
2724 q
->pktcnt_idx
= new_idx
;
2727 us
= us
== 0 ? 6 : closest_timer(&adap
->sge
, us
);
2728 q
->intr_params
= QINTR_TIMER_IDX(us
) | (cnt
> 0 ? QINTR_CNT_EN
: 0);
2733 * set_rx_intr_params - set a net devices's RX interrupt holdoff paramete!
2734 * @dev: the network device
2735 * @us: the hold-off time in us, or 0 to disable timer
2736 * @cnt: the hold-off packet count, or 0 to disable counter
2738 * Set the RX interrupt hold-off parameters for a network device.
2740 static int set_rx_intr_params(struct net_device
*dev
,
2741 unsigned int us
, unsigned int cnt
)
2744 struct port_info
*pi
= netdev_priv(dev
);
2745 struct adapter
*adap
= pi
->adapter
;
2746 struct sge_eth_rxq
*q
= &adap
->sge
.ethrxq
[pi
->first_qset
];
2748 for (i
= 0; i
< pi
->nqsets
; i
++, q
++) {
2749 err
= set_rspq_intr_params(&q
->rspq
, us
, cnt
);
2756 static int set_adaptive_rx_setting(struct net_device
*dev
, int adaptive_rx
)
2759 struct port_info
*pi
= netdev_priv(dev
);
2760 struct adapter
*adap
= pi
->adapter
;
2761 struct sge_eth_rxq
*q
= &adap
->sge
.ethrxq
[pi
->first_qset
];
2763 for (i
= 0; i
< pi
->nqsets
; i
++, q
++)
2764 q
->rspq
.adaptive_rx
= adaptive_rx
;
2769 static int get_adaptive_rx_setting(struct net_device
*dev
)
2771 struct port_info
*pi
= netdev_priv(dev
);
2772 struct adapter
*adap
= pi
->adapter
;
2773 struct sge_eth_rxq
*q
= &adap
->sge
.ethrxq
[pi
->first_qset
];
2775 return q
->rspq
.adaptive_rx
;
2778 static int set_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*c
)
2780 set_adaptive_rx_setting(dev
, c
->use_adaptive_rx_coalesce
);
2781 return set_rx_intr_params(dev
, c
->rx_coalesce_usecs
,
2782 c
->rx_max_coalesced_frames
);
2785 static int get_coalesce(struct net_device
*dev
, struct ethtool_coalesce
*c
)
2787 const struct port_info
*pi
= netdev_priv(dev
);
2788 const struct adapter
*adap
= pi
->adapter
;
2789 const struct sge_rspq
*rq
= &adap
->sge
.ethrxq
[pi
->first_qset
].rspq
;
2791 c
->rx_coalesce_usecs
= qtimer_val(adap
, rq
);
2792 c
->rx_max_coalesced_frames
= (rq
->intr_params
& QINTR_CNT_EN
) ?
2793 adap
->sge
.counter_val
[rq
->pktcnt_idx
] : 0;
2794 c
->use_adaptive_rx_coalesce
= get_adaptive_rx_setting(dev
);
2799 * eeprom_ptov - translate a physical EEPROM address to virtual
2800 * @phys_addr: the physical EEPROM address
2801 * @fn: the PCI function number
2802 * @sz: size of function-specific area
2804 * Translate a physical EEPROM address to virtual. The first 1K is
2805 * accessed through virtual addresses starting at 31K, the rest is
2806 * accessed through virtual addresses starting at 0.
2808 * The mapping is as follows:
2809 * [0..1K) -> [31K..32K)
2810 * [1K..1K+A) -> [31K-A..31K)
2811 * [1K+A..ES) -> [0..ES-A-1K)
2813 * where A = @fn * @sz, and ES = EEPROM size.
2815 static int eeprom_ptov(unsigned int phys_addr
, unsigned int fn
, unsigned int sz
)
2818 if (phys_addr
< 1024)
2819 return phys_addr
+ (31 << 10);
2820 if (phys_addr
< 1024 + fn
)
2821 return 31744 - fn
+ phys_addr
- 1024;
2822 if (phys_addr
< EEPROMSIZE
)
2823 return phys_addr
- 1024 - fn
;
2828 * The next two routines implement eeprom read/write from physical addresses.
2830 static int eeprom_rd_phys(struct adapter
*adap
, unsigned int phys_addr
, u32
*v
)
2832 int vaddr
= eeprom_ptov(phys_addr
, adap
->fn
, EEPROMPFSIZE
);
2835 vaddr
= pci_read_vpd(adap
->pdev
, vaddr
, sizeof(u32
), v
);
2836 return vaddr
< 0 ? vaddr
: 0;
2839 static int eeprom_wr_phys(struct adapter
*adap
, unsigned int phys_addr
, u32 v
)
2841 int vaddr
= eeprom_ptov(phys_addr
, adap
->fn
, EEPROMPFSIZE
);
2844 vaddr
= pci_write_vpd(adap
->pdev
, vaddr
, sizeof(u32
), &v
);
2845 return vaddr
< 0 ? vaddr
: 0;
2848 #define EEPROM_MAGIC 0x38E2F10C
2850 static int get_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*e
,
2854 struct adapter
*adapter
= netdev2adap(dev
);
2856 u8
*buf
= kmalloc(EEPROMSIZE
, GFP_KERNEL
);
2860 e
->magic
= EEPROM_MAGIC
;
2861 for (i
= e
->offset
& ~3; !err
&& i
< e
->offset
+ e
->len
; i
+= 4)
2862 err
= eeprom_rd_phys(adapter
, i
, (u32
*)&buf
[i
]);
2865 memcpy(data
, buf
+ e
->offset
, e
->len
);
2870 static int set_eeprom(struct net_device
*dev
, struct ethtool_eeprom
*eeprom
,
2875 u32 aligned_offset
, aligned_len
, *p
;
2876 struct adapter
*adapter
= netdev2adap(dev
);
2878 if (eeprom
->magic
!= EEPROM_MAGIC
)
2881 aligned_offset
= eeprom
->offset
& ~3;
2882 aligned_len
= (eeprom
->len
+ (eeprom
->offset
& 3) + 3) & ~3;
2884 if (adapter
->fn
> 0) {
2885 u32 start
= 1024 + adapter
->fn
* EEPROMPFSIZE
;
2887 if (aligned_offset
< start
||
2888 aligned_offset
+ aligned_len
> start
+ EEPROMPFSIZE
)
2892 if (aligned_offset
!= eeprom
->offset
|| aligned_len
!= eeprom
->len
) {
2894 * RMW possibly needed for first or last words.
2896 buf
= kmalloc(aligned_len
, GFP_KERNEL
);
2899 err
= eeprom_rd_phys(adapter
, aligned_offset
, (u32
*)buf
);
2900 if (!err
&& aligned_len
> 4)
2901 err
= eeprom_rd_phys(adapter
,
2902 aligned_offset
+ aligned_len
- 4,
2903 (u32
*)&buf
[aligned_len
- 4]);
2906 memcpy(buf
+ (eeprom
->offset
& 3), data
, eeprom
->len
);
2910 err
= t4_seeprom_wp(adapter
, false);
2914 for (p
= (u32
*)buf
; !err
&& aligned_len
; aligned_len
-= 4, p
++) {
2915 err
= eeprom_wr_phys(adapter
, aligned_offset
, *p
);
2916 aligned_offset
+= 4;
2920 err
= t4_seeprom_wp(adapter
, true);
2927 static int set_flash(struct net_device
*netdev
, struct ethtool_flash
*ef
)
2930 const struct firmware
*fw
;
2931 struct adapter
*adap
= netdev2adap(netdev
);
2933 ef
->data
[sizeof(ef
->data
) - 1] = '\0';
2934 ret
= request_firmware(&fw
, ef
->data
, adap
->pdev_dev
);
2938 ret
= t4_load_fw(adap
, fw
->data
, fw
->size
);
2939 release_firmware(fw
);
2941 dev_info(adap
->pdev_dev
, "loaded firmware %s\n", ef
->data
);
2945 #define WOL_SUPPORTED (WAKE_BCAST | WAKE_MAGIC)
2946 #define BCAST_CRC 0xa0ccc1a6
2948 static void get_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2950 wol
->supported
= WAKE_BCAST
| WAKE_MAGIC
;
2951 wol
->wolopts
= netdev2adap(dev
)->wol
;
2952 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
2955 static int set_wol(struct net_device
*dev
, struct ethtool_wolinfo
*wol
)
2958 struct port_info
*pi
= netdev_priv(dev
);
2960 if (wol
->wolopts
& ~WOL_SUPPORTED
)
2962 t4_wol_magic_enable(pi
->adapter
, pi
->tx_chan
,
2963 (wol
->wolopts
& WAKE_MAGIC
) ? dev
->dev_addr
: NULL
);
2964 if (wol
->wolopts
& WAKE_BCAST
) {
2965 err
= t4_wol_pat_enable(pi
->adapter
, pi
->tx_chan
, 0xfe, ~0ULL,
2968 err
= t4_wol_pat_enable(pi
->adapter
, pi
->tx_chan
, 1,
2969 ~6ULL, ~0ULL, BCAST_CRC
, true);
2971 t4_wol_pat_enable(pi
->adapter
, pi
->tx_chan
, 0, 0, 0, 0, false);
2975 static int cxgb_set_features(struct net_device
*dev
, netdev_features_t features
)
2977 const struct port_info
*pi
= netdev_priv(dev
);
2978 netdev_features_t changed
= dev
->features
^ features
;
2981 if (!(changed
& NETIF_F_HW_VLAN_CTAG_RX
))
2984 err
= t4_set_rxmode(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, -1,
2986 !!(features
& NETIF_F_HW_VLAN_CTAG_RX
), true);
2988 dev
->features
= features
^ NETIF_F_HW_VLAN_CTAG_RX
;
2992 static u32
get_rss_table_size(struct net_device
*dev
)
2994 const struct port_info
*pi
= netdev_priv(dev
);
2996 return pi
->rss_size
;
2999 static int get_rss_table(struct net_device
*dev
, u32
*p
, u8
*key
)
3001 const struct port_info
*pi
= netdev_priv(dev
);
3002 unsigned int n
= pi
->rss_size
;
3009 static int set_rss_table(struct net_device
*dev
, const u32
*p
, const u8
*key
)
3012 struct port_info
*pi
= netdev_priv(dev
);
3014 for (i
= 0; i
< pi
->rss_size
; i
++)
3016 if (pi
->adapter
->flags
& FULL_INIT_DONE
)
3017 return write_rss(pi
, pi
->rss
);
3021 static int get_rxnfc(struct net_device
*dev
, struct ethtool_rxnfc
*info
,
3024 const struct port_info
*pi
= netdev_priv(dev
);
3026 switch (info
->cmd
) {
3027 case ETHTOOL_GRXFH
: {
3028 unsigned int v
= pi
->rss_mode
;
3031 switch (info
->flow_type
) {
3033 if (v
& FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN
)
3034 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3035 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3036 else if (v
& FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN
)
3037 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3040 if ((v
& FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN
) &&
3041 (v
& FW_RSS_VI_CONFIG_CMD_UDPEN
))
3042 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3043 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3044 else if (v
& FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN
)
3045 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3048 case AH_ESP_V4_FLOW
:
3050 if (v
& FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN
)
3051 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3054 if (v
& FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN
)
3055 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3056 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3057 else if (v
& FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN
)
3058 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3061 if ((v
& FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN
) &&
3062 (v
& FW_RSS_VI_CONFIG_CMD_UDPEN
))
3063 info
->data
= RXH_IP_SRC
| RXH_IP_DST
|
3064 RXH_L4_B_0_1
| RXH_L4_B_2_3
;
3065 else if (v
& FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN
)
3066 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3069 case AH_ESP_V6_FLOW
:
3071 if (v
& FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN
)
3072 info
->data
= RXH_IP_SRC
| RXH_IP_DST
;
3077 case ETHTOOL_GRXRINGS
:
3078 info
->data
= pi
->nqsets
;
3084 static const struct ethtool_ops cxgb_ethtool_ops
= {
3085 .get_settings
= get_settings
,
3086 .set_settings
= set_settings
,
3087 .get_drvinfo
= get_drvinfo
,
3088 .get_msglevel
= get_msglevel
,
3089 .set_msglevel
= set_msglevel
,
3090 .get_ringparam
= get_sge_param
,
3091 .set_ringparam
= set_sge_param
,
3092 .get_coalesce
= get_coalesce
,
3093 .set_coalesce
= set_coalesce
,
3094 .get_eeprom_len
= get_eeprom_len
,
3095 .get_eeprom
= get_eeprom
,
3096 .set_eeprom
= set_eeprom
,
3097 .get_pauseparam
= get_pauseparam
,
3098 .set_pauseparam
= set_pauseparam
,
3099 .get_link
= ethtool_op_get_link
,
3100 .get_strings
= get_strings
,
3101 .set_phys_id
= identify_port
,
3102 .nway_reset
= restart_autoneg
,
3103 .get_sset_count
= get_sset_count
,
3104 .get_ethtool_stats
= get_stats
,
3105 .get_regs_len
= get_regs_len
,
3106 .get_regs
= get_regs
,
3109 .get_rxnfc
= get_rxnfc
,
3110 .get_rxfh_indir_size
= get_rss_table_size
,
3111 .get_rxfh
= get_rss_table
,
3112 .set_rxfh
= set_rss_table
,
3113 .flash_device
= set_flash
,
3119 static ssize_t
mem_read(struct file
*file
, char __user
*buf
, size_t count
,
3123 loff_t avail
= file_inode(file
)->i_size
;
3124 unsigned int mem
= (uintptr_t)file
->private_data
& 3;
3125 struct adapter
*adap
= file
->private_data
- mem
;
3133 if (count
> avail
- pos
)
3134 count
= avail
- pos
;
3136 data
= t4_alloc_mem(count
);
3140 spin_lock(&adap
->win0_lock
);
3141 ret
= t4_memory_rw(adap
, 0, mem
, pos
, count
, data
, T4_MEMORY_READ
);
3142 spin_unlock(&adap
->win0_lock
);
3147 ret
= copy_to_user(buf
, data
, count
);
3153 *ppos
= pos
+ count
;
3157 static const struct file_operations mem_debugfs_fops
= {
3158 .owner
= THIS_MODULE
,
3159 .open
= simple_open
,
3161 .llseek
= default_llseek
,
3164 static void add_debugfs_mem(struct adapter
*adap
, const char *name
,
3165 unsigned int idx
, unsigned int size_mb
)
3169 de
= debugfs_create_file(name
, S_IRUSR
, adap
->debugfs_root
,
3170 (void *)adap
+ idx
, &mem_debugfs_fops
);
3171 if (de
&& de
->d_inode
)
3172 de
->d_inode
->i_size
= size_mb
<< 20;
3175 static int setup_debugfs(struct adapter
*adap
)
3180 if (IS_ERR_OR_NULL(adap
->debugfs_root
))
3183 i
= t4_read_reg(adap
, MA_TARGET_MEM_ENABLE
);
3184 if (i
& EDRAM0_ENABLE
) {
3185 size
= t4_read_reg(adap
, MA_EDRAM0_BAR
);
3186 add_debugfs_mem(adap
, "edc0", MEM_EDC0
, EDRAM_SIZE_GET(size
));
3188 if (i
& EDRAM1_ENABLE
) {
3189 size
= t4_read_reg(adap
, MA_EDRAM1_BAR
);
3190 add_debugfs_mem(adap
, "edc1", MEM_EDC1
, EDRAM_SIZE_GET(size
));
3192 if (is_t4(adap
->params
.chip
)) {
3193 size
= t4_read_reg(adap
, MA_EXT_MEMORY_BAR
);
3194 if (i
& EXT_MEM_ENABLE
)
3195 add_debugfs_mem(adap
, "mc", MEM_MC
,
3196 EXT_MEM_SIZE_GET(size
));
3198 if (i
& EXT_MEM_ENABLE
) {
3199 size
= t4_read_reg(adap
, MA_EXT_MEMORY_BAR
);
3200 add_debugfs_mem(adap
, "mc0", MEM_MC0
,
3201 EXT_MEM_SIZE_GET(size
));
3203 if (i
& EXT_MEM1_ENABLE
) {
3204 size
= t4_read_reg(adap
, MA_EXT_MEMORY1_BAR
);
3205 add_debugfs_mem(adap
, "mc1", MEM_MC1
,
3206 EXT_MEM_SIZE_GET(size
));
3210 debugfs_create_file("l2t", S_IRUSR
, adap
->debugfs_root
, adap
,
3216 * upper-layer driver support
3220 * Allocate an active-open TID and set it to the supplied value.
3222 int cxgb4_alloc_atid(struct tid_info
*t
, void *data
)
3226 spin_lock_bh(&t
->atid_lock
);
3228 union aopen_entry
*p
= t
->afree
;
3230 atid
= (p
- t
->atid_tab
) + t
->atid_base
;
3235 spin_unlock_bh(&t
->atid_lock
);
3238 EXPORT_SYMBOL(cxgb4_alloc_atid
);
3241 * Release an active-open TID.
3243 void cxgb4_free_atid(struct tid_info
*t
, unsigned int atid
)
3245 union aopen_entry
*p
= &t
->atid_tab
[atid
- t
->atid_base
];
3247 spin_lock_bh(&t
->atid_lock
);
3251 spin_unlock_bh(&t
->atid_lock
);
3253 EXPORT_SYMBOL(cxgb4_free_atid
);
3256 * Allocate a server TID and set it to the supplied value.
3258 int cxgb4_alloc_stid(struct tid_info
*t
, int family
, void *data
)
3262 spin_lock_bh(&t
->stid_lock
);
3263 if (family
== PF_INET
) {
3264 stid
= find_first_zero_bit(t
->stid_bmap
, t
->nstids
);
3265 if (stid
< t
->nstids
)
3266 __set_bit(stid
, t
->stid_bmap
);
3270 stid
= bitmap_find_free_region(t
->stid_bmap
, t
->nstids
, 2);
3275 t
->stid_tab
[stid
].data
= data
;
3276 stid
+= t
->stid_base
;
3277 /* IPv6 requires max of 520 bits or 16 cells in TCAM
3278 * This is equivalent to 4 TIDs. With CLIP enabled it
3281 if (family
== PF_INET
)
3284 t
->stids_in_use
+= 4;
3286 spin_unlock_bh(&t
->stid_lock
);
3289 EXPORT_SYMBOL(cxgb4_alloc_stid
);
3291 /* Allocate a server filter TID and set it to the supplied value.
3293 int cxgb4_alloc_sftid(struct tid_info
*t
, int family
, void *data
)
3297 spin_lock_bh(&t
->stid_lock
);
3298 if (family
== PF_INET
) {
3299 stid
= find_next_zero_bit(t
->stid_bmap
,
3300 t
->nstids
+ t
->nsftids
, t
->nstids
);
3301 if (stid
< (t
->nstids
+ t
->nsftids
))
3302 __set_bit(stid
, t
->stid_bmap
);
3309 t
->stid_tab
[stid
].data
= data
;
3311 stid
+= t
->sftid_base
;
3314 spin_unlock_bh(&t
->stid_lock
);
3317 EXPORT_SYMBOL(cxgb4_alloc_sftid
);
3319 /* Release a server TID.
3321 void cxgb4_free_stid(struct tid_info
*t
, unsigned int stid
, int family
)
3323 /* Is it a server filter TID? */
3324 if (t
->nsftids
&& (stid
>= t
->sftid_base
)) {
3325 stid
-= t
->sftid_base
;
3328 stid
-= t
->stid_base
;
3331 spin_lock_bh(&t
->stid_lock
);
3332 if (family
== PF_INET
)
3333 __clear_bit(stid
, t
->stid_bmap
);
3335 bitmap_release_region(t
->stid_bmap
, stid
, 2);
3336 t
->stid_tab
[stid
].data
= NULL
;
3337 if (family
== PF_INET
)
3340 t
->stids_in_use
-= 4;
3341 spin_unlock_bh(&t
->stid_lock
);
3343 EXPORT_SYMBOL(cxgb4_free_stid
);
3346 * Populate a TID_RELEASE WR. Caller must properly size the skb.
3348 static void mk_tid_release(struct sk_buff
*skb
, unsigned int chan
,
3351 struct cpl_tid_release
*req
;
3353 set_wr_txq(skb
, CPL_PRIORITY_SETUP
, chan
);
3354 req
= (struct cpl_tid_release
*)__skb_put(skb
, sizeof(*req
));
3355 INIT_TP_WR(req
, tid
);
3356 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_TID_RELEASE
, tid
));
3360 * Queue a TID release request and if necessary schedule a work queue to
3363 static void cxgb4_queue_tid_release(struct tid_info
*t
, unsigned int chan
,
3366 void **p
= &t
->tid_tab
[tid
];
3367 struct adapter
*adap
= container_of(t
, struct adapter
, tids
);
3369 spin_lock_bh(&adap
->tid_release_lock
);
3370 *p
= adap
->tid_release_head
;
3371 /* Low 2 bits encode the Tx channel number */
3372 adap
->tid_release_head
= (void **)((uintptr_t)p
| chan
);
3373 if (!adap
->tid_release_task_busy
) {
3374 adap
->tid_release_task_busy
= true;
3375 queue_work(adap
->workq
, &adap
->tid_release_task
);
3377 spin_unlock_bh(&adap
->tid_release_lock
);
3381 * Process the list of pending TID release requests.
3383 static void process_tid_release_list(struct work_struct
*work
)
3385 struct sk_buff
*skb
;
3386 struct adapter
*adap
;
3388 adap
= container_of(work
, struct adapter
, tid_release_task
);
3390 spin_lock_bh(&adap
->tid_release_lock
);
3391 while (adap
->tid_release_head
) {
3392 void **p
= adap
->tid_release_head
;
3393 unsigned int chan
= (uintptr_t)p
& 3;
3394 p
= (void *)p
- chan
;
3396 adap
->tid_release_head
= *p
;
3398 spin_unlock_bh(&adap
->tid_release_lock
);
3400 while (!(skb
= alloc_skb(sizeof(struct cpl_tid_release
),
3402 schedule_timeout_uninterruptible(1);
3404 mk_tid_release(skb
, chan
, p
- adap
->tids
.tid_tab
);
3405 t4_ofld_send(adap
, skb
);
3406 spin_lock_bh(&adap
->tid_release_lock
);
3408 adap
->tid_release_task_busy
= false;
3409 spin_unlock_bh(&adap
->tid_release_lock
);
3413 * Release a TID and inform HW. If we are unable to allocate the release
3414 * message we defer to a work queue.
3416 void cxgb4_remove_tid(struct tid_info
*t
, unsigned int chan
, unsigned int tid
)
3419 struct sk_buff
*skb
;
3420 struct adapter
*adap
= container_of(t
, struct adapter
, tids
);
3422 old
= t
->tid_tab
[tid
];
3423 skb
= alloc_skb(sizeof(struct cpl_tid_release
), GFP_ATOMIC
);
3425 t
->tid_tab
[tid
] = NULL
;
3426 mk_tid_release(skb
, chan
, tid
);
3427 t4_ofld_send(adap
, skb
);
3429 cxgb4_queue_tid_release(t
, chan
, tid
);
3431 atomic_dec(&t
->tids_in_use
);
3433 EXPORT_SYMBOL(cxgb4_remove_tid
);
3436 * Allocate and initialize the TID tables. Returns 0 on success.
3438 static int tid_init(struct tid_info
*t
)
3441 unsigned int stid_bmap_size
;
3442 unsigned int natids
= t
->natids
;
3443 struct adapter
*adap
= container_of(t
, struct adapter
, tids
);
3445 stid_bmap_size
= BITS_TO_LONGS(t
->nstids
+ t
->nsftids
);
3446 size
= t
->ntids
* sizeof(*t
->tid_tab
) +
3447 natids
* sizeof(*t
->atid_tab
) +
3448 t
->nstids
* sizeof(*t
->stid_tab
) +
3449 t
->nsftids
* sizeof(*t
->stid_tab
) +
3450 stid_bmap_size
* sizeof(long) +
3451 t
->nftids
* sizeof(*t
->ftid_tab
) +
3452 t
->nsftids
* sizeof(*t
->ftid_tab
);
3454 t
->tid_tab
= t4_alloc_mem(size
);
3458 t
->atid_tab
= (union aopen_entry
*)&t
->tid_tab
[t
->ntids
];
3459 t
->stid_tab
= (struct serv_entry
*)&t
->atid_tab
[natids
];
3460 t
->stid_bmap
= (unsigned long *)&t
->stid_tab
[t
->nstids
+ t
->nsftids
];
3461 t
->ftid_tab
= (struct filter_entry
*)&t
->stid_bmap
[stid_bmap_size
];
3462 spin_lock_init(&t
->stid_lock
);
3463 spin_lock_init(&t
->atid_lock
);
3465 t
->stids_in_use
= 0;
3467 t
->atids_in_use
= 0;
3468 atomic_set(&t
->tids_in_use
, 0);
3470 /* Setup the free list for atid_tab and clear the stid bitmap. */
3473 t
->atid_tab
[natids
- 1].next
= &t
->atid_tab
[natids
];
3474 t
->afree
= t
->atid_tab
;
3476 bitmap_zero(t
->stid_bmap
, t
->nstids
+ t
->nsftids
);
3477 /* Reserve stid 0 for T4/T5 adapters */
3478 if (!t
->stid_base
&&
3479 (is_t4(adap
->params
.chip
) || is_t5(adap
->params
.chip
)))
3480 __set_bit(0, t
->stid_bmap
);
3485 int cxgb4_clip_get(const struct net_device
*dev
,
3486 const struct in6_addr
*lip
)
3488 struct adapter
*adap
;
3489 struct fw_clip_cmd c
;
3491 adap
= netdev2adap(dev
);
3492 memset(&c
, 0, sizeof(c
));
3493 c
.op_to_write
= htonl(FW_CMD_OP(FW_CLIP_CMD
) |
3494 FW_CMD_REQUEST
| FW_CMD_WRITE
);
3495 c
.alloc_to_len16
= htonl(F_FW_CLIP_CMD_ALLOC
| FW_LEN16(c
));
3496 c
.ip_hi
= *(__be64
*)(lip
->s6_addr
);
3497 c
.ip_lo
= *(__be64
*)(lip
->s6_addr
+ 8);
3498 return t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, false);
3500 EXPORT_SYMBOL(cxgb4_clip_get
);
3502 int cxgb4_clip_release(const struct net_device
*dev
,
3503 const struct in6_addr
*lip
)
3505 struct adapter
*adap
;
3506 struct fw_clip_cmd c
;
3508 adap
= netdev2adap(dev
);
3509 memset(&c
, 0, sizeof(c
));
3510 c
.op_to_write
= htonl(FW_CMD_OP(FW_CLIP_CMD
) |
3511 FW_CMD_REQUEST
| FW_CMD_READ
);
3512 c
.alloc_to_len16
= htonl(F_FW_CLIP_CMD_FREE
| FW_LEN16(c
));
3513 c
.ip_hi
= *(__be64
*)(lip
->s6_addr
);
3514 c
.ip_lo
= *(__be64
*)(lip
->s6_addr
+ 8);
3515 return t4_wr_mbox_meat(adap
, adap
->mbox
, &c
, sizeof(c
), &c
, false);
3517 EXPORT_SYMBOL(cxgb4_clip_release
);
3520 * cxgb4_create_server - create an IP server
3522 * @stid: the server TID
3523 * @sip: local IP address to bind server to
3524 * @sport: the server's TCP port
3525 * @queue: queue to direct messages from this server to
3527 * Create an IP server for the given port and address.
3528 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3530 int cxgb4_create_server(const struct net_device
*dev
, unsigned int stid
,
3531 __be32 sip
, __be16 sport
, __be16 vlan
,
3535 struct sk_buff
*skb
;
3536 struct adapter
*adap
;
3537 struct cpl_pass_open_req
*req
;
3540 skb
= alloc_skb(sizeof(*req
), GFP_KERNEL
);
3544 adap
= netdev2adap(dev
);
3545 req
= (struct cpl_pass_open_req
*)__skb_put(skb
, sizeof(*req
));
3547 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ
, stid
));
3548 req
->local_port
= sport
;
3549 req
->peer_port
= htons(0);
3550 req
->local_ip
= sip
;
3551 req
->peer_ip
= htonl(0);
3552 chan
= rxq_to_chan(&adap
->sge
, queue
);
3553 req
->opt0
= cpu_to_be64(TX_CHAN(chan
));
3554 req
->opt1
= cpu_to_be64(CONN_POLICY_ASK
|
3555 SYN_RSS_ENABLE
| SYN_RSS_QUEUE(queue
));
3556 ret
= t4_mgmt_tx(adap
, skb
);
3557 return net_xmit_eval(ret
);
3559 EXPORT_SYMBOL(cxgb4_create_server
);
3561 /* cxgb4_create_server6 - create an IPv6 server
3563 * @stid: the server TID
3564 * @sip: local IPv6 address to bind server to
3565 * @sport: the server's TCP port
3566 * @queue: queue to direct messages from this server to
3568 * Create an IPv6 server for the given port and address.
3569 * Returns <0 on error and one of the %NET_XMIT_* values on success.
3571 int cxgb4_create_server6(const struct net_device
*dev
, unsigned int stid
,
3572 const struct in6_addr
*sip
, __be16 sport
,
3576 struct sk_buff
*skb
;
3577 struct adapter
*adap
;
3578 struct cpl_pass_open_req6
*req
;
3581 skb
= alloc_skb(sizeof(*req
), GFP_KERNEL
);
3585 adap
= netdev2adap(dev
);
3586 req
= (struct cpl_pass_open_req6
*)__skb_put(skb
, sizeof(*req
));
3588 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_PASS_OPEN_REQ6
, stid
));
3589 req
->local_port
= sport
;
3590 req
->peer_port
= htons(0);
3591 req
->local_ip_hi
= *(__be64
*)(sip
->s6_addr
);
3592 req
->local_ip_lo
= *(__be64
*)(sip
->s6_addr
+ 8);
3593 req
->peer_ip_hi
= cpu_to_be64(0);
3594 req
->peer_ip_lo
= cpu_to_be64(0);
3595 chan
= rxq_to_chan(&adap
->sge
, queue
);
3596 req
->opt0
= cpu_to_be64(TX_CHAN(chan
));
3597 req
->opt1
= cpu_to_be64(CONN_POLICY_ASK
|
3598 SYN_RSS_ENABLE
| SYN_RSS_QUEUE(queue
));
3599 ret
= t4_mgmt_tx(adap
, skb
);
3600 return net_xmit_eval(ret
);
3602 EXPORT_SYMBOL(cxgb4_create_server6
);
3604 int cxgb4_remove_server(const struct net_device
*dev
, unsigned int stid
,
3605 unsigned int queue
, bool ipv6
)
3607 struct sk_buff
*skb
;
3608 struct adapter
*adap
;
3609 struct cpl_close_listsvr_req
*req
;
3612 adap
= netdev2adap(dev
);
3614 skb
= alloc_skb(sizeof(*req
), GFP_KERNEL
);
3618 req
= (struct cpl_close_listsvr_req
*)__skb_put(skb
, sizeof(*req
));
3620 OPCODE_TID(req
) = htonl(MK_OPCODE_TID(CPL_CLOSE_LISTSRV_REQ
, stid
));
3621 req
->reply_ctrl
= htons(NO_REPLY(0) | (ipv6
? LISTSVR_IPV6(1) :
3622 LISTSVR_IPV6(0)) | QUEUENO(queue
));
3623 ret
= t4_mgmt_tx(adap
, skb
);
3624 return net_xmit_eval(ret
);
3626 EXPORT_SYMBOL(cxgb4_remove_server
);
3629 * cxgb4_best_mtu - find the entry in the MTU table closest to an MTU
3630 * @mtus: the HW MTU table
3631 * @mtu: the target MTU
3632 * @idx: index of selected entry in the MTU table
3634 * Returns the index and the value in the HW MTU table that is closest to
3635 * but does not exceed @mtu, unless @mtu is smaller than any value in the
3636 * table, in which case that smallest available value is selected.
3638 unsigned int cxgb4_best_mtu(const unsigned short *mtus
, unsigned short mtu
,
3643 while (i
< NMTUS
- 1 && mtus
[i
+ 1] <= mtu
)
3649 EXPORT_SYMBOL(cxgb4_best_mtu
);
3652 * cxgb4_best_aligned_mtu - find best MTU, [hopefully] data size aligned
3653 * @mtus: the HW MTU table
3654 * @header_size: Header Size
3655 * @data_size_max: maximum Data Segment Size
3656 * @data_size_align: desired Data Segment Size Alignment (2^N)
3657 * @mtu_idxp: HW MTU Table Index return value pointer (possibly NULL)
3659 * Similar to cxgb4_best_mtu() but instead of searching the Hardware
3660 * MTU Table based solely on a Maximum MTU parameter, we break that
3661 * parameter up into a Header Size and Maximum Data Segment Size, and
3662 * provide a desired Data Segment Size Alignment. If we find an MTU in
3663 * the Hardware MTU Table which will result in a Data Segment Size with
3664 * the requested alignment _and_ that MTU isn't "too far" from the
3665 * closest MTU, then we'll return that rather than the closest MTU.
3667 unsigned int cxgb4_best_aligned_mtu(const unsigned short *mtus
,
3668 unsigned short header_size
,
3669 unsigned short data_size_max
,
3670 unsigned short data_size_align
,
3671 unsigned int *mtu_idxp
)
3673 unsigned short max_mtu
= header_size
+ data_size_max
;
3674 unsigned short data_size_align_mask
= data_size_align
- 1;
3675 int mtu_idx
, aligned_mtu_idx
;
3677 /* Scan the MTU Table till we find an MTU which is larger than our
3678 * Maximum MTU or we reach the end of the table. Along the way,
3679 * record the last MTU found, if any, which will result in a Data
3680 * Segment Length matching the requested alignment.
3682 for (mtu_idx
= 0, aligned_mtu_idx
= -1; mtu_idx
< NMTUS
; mtu_idx
++) {
3683 unsigned short data_size
= mtus
[mtu_idx
] - header_size
;
3685 /* If this MTU minus the Header Size would result in a
3686 * Data Segment Size of the desired alignment, remember it.
3688 if ((data_size
& data_size_align_mask
) == 0)
3689 aligned_mtu_idx
= mtu_idx
;
3691 /* If we're not at the end of the Hardware MTU Table and the
3692 * next element is larger than our Maximum MTU, drop out of
3695 if (mtu_idx
+1 < NMTUS
&& mtus
[mtu_idx
+1] > max_mtu
)
3699 /* If we fell out of the loop because we ran to the end of the table,
3700 * then we just have to use the last [largest] entry.
3702 if (mtu_idx
== NMTUS
)
3705 /* If we found an MTU which resulted in the requested Data Segment
3706 * Length alignment and that's "not far" from the largest MTU which is
3707 * less than or equal to the maximum MTU, then use that.
3709 if (aligned_mtu_idx
>= 0 &&
3710 mtu_idx
- aligned_mtu_idx
<= 1)
3711 mtu_idx
= aligned_mtu_idx
;
3713 /* If the caller has passed in an MTU Index pointer, pass the
3714 * MTU Index back. Return the MTU value.
3717 *mtu_idxp
= mtu_idx
;
3718 return mtus
[mtu_idx
];
3720 EXPORT_SYMBOL(cxgb4_best_aligned_mtu
);
3723 * cxgb4_port_chan - get the HW channel of a port
3724 * @dev: the net device for the port
3726 * Return the HW Tx channel of the given port.
3728 unsigned int cxgb4_port_chan(const struct net_device
*dev
)
3730 return netdev2pinfo(dev
)->tx_chan
;
3732 EXPORT_SYMBOL(cxgb4_port_chan
);
3734 unsigned int cxgb4_dbfifo_count(const struct net_device
*dev
, int lpfifo
)
3736 struct adapter
*adap
= netdev2adap(dev
);
3737 u32 v1
, v2
, lp_count
, hp_count
;
3739 v1
= t4_read_reg(adap
, A_SGE_DBFIFO_STATUS
);
3740 v2
= t4_read_reg(adap
, SGE_DBFIFO_STATUS2
);
3741 if (is_t4(adap
->params
.chip
)) {
3742 lp_count
= G_LP_COUNT(v1
);
3743 hp_count
= G_HP_COUNT(v1
);
3745 lp_count
= G_LP_COUNT_T5(v1
);
3746 hp_count
= G_HP_COUNT_T5(v2
);
3748 return lpfifo
? lp_count
: hp_count
;
3750 EXPORT_SYMBOL(cxgb4_dbfifo_count
);
3753 * cxgb4_port_viid - get the VI id of a port
3754 * @dev: the net device for the port
3756 * Return the VI id of the given port.
3758 unsigned int cxgb4_port_viid(const struct net_device
*dev
)
3760 return netdev2pinfo(dev
)->viid
;
3762 EXPORT_SYMBOL(cxgb4_port_viid
);
3765 * cxgb4_port_idx - get the index of a port
3766 * @dev: the net device for the port
3768 * Return the index of the given port.
3770 unsigned int cxgb4_port_idx(const struct net_device
*dev
)
3772 return netdev2pinfo(dev
)->port_id
;
3774 EXPORT_SYMBOL(cxgb4_port_idx
);
3776 void cxgb4_get_tcp_stats(struct pci_dev
*pdev
, struct tp_tcp_stats
*v4
,
3777 struct tp_tcp_stats
*v6
)
3779 struct adapter
*adap
= pci_get_drvdata(pdev
);
3781 spin_lock(&adap
->stats_lock
);
3782 t4_tp_get_tcp_stats(adap
, v4
, v6
);
3783 spin_unlock(&adap
->stats_lock
);
3785 EXPORT_SYMBOL(cxgb4_get_tcp_stats
);
3787 void cxgb4_iscsi_init(struct net_device
*dev
, unsigned int tag_mask
,
3788 const unsigned int *pgsz_order
)
3790 struct adapter
*adap
= netdev2adap(dev
);
3792 t4_write_reg(adap
, ULP_RX_ISCSI_TAGMASK
, tag_mask
);
3793 t4_write_reg(adap
, ULP_RX_ISCSI_PSZ
, HPZ0(pgsz_order
[0]) |
3794 HPZ1(pgsz_order
[1]) | HPZ2(pgsz_order
[2]) |
3795 HPZ3(pgsz_order
[3]));
3797 EXPORT_SYMBOL(cxgb4_iscsi_init
);
3799 int cxgb4_flush_eq_cache(struct net_device
*dev
)
3801 struct adapter
*adap
= netdev2adap(dev
);
3804 ret
= t4_fwaddrspace_write(adap
, adap
->mbox
,
3805 0xe1000000 + A_SGE_CTXT_CMD
, 0x20000000);
3808 EXPORT_SYMBOL(cxgb4_flush_eq_cache
);
3810 static int read_eq_indices(struct adapter
*adap
, u16 qid
, u16
*pidx
, u16
*cidx
)
3812 u32 addr
= t4_read_reg(adap
, A_SGE_DBQ_CTXT_BADDR
) + 24 * qid
+ 8;
3816 spin_lock(&adap
->win0_lock
);
3817 ret
= t4_memory_rw(adap
, 0, MEM_EDC0
, addr
,
3818 sizeof(indices
), (__be32
*)&indices
,
3820 spin_unlock(&adap
->win0_lock
);
3822 *cidx
= (be64_to_cpu(indices
) >> 25) & 0xffff;
3823 *pidx
= (be64_to_cpu(indices
) >> 9) & 0xffff;
3828 int cxgb4_sync_txq_pidx(struct net_device
*dev
, u16 qid
, u16 pidx
,
3831 struct adapter
*adap
= netdev2adap(dev
);
3832 u16 hw_pidx
, hw_cidx
;
3835 ret
= read_eq_indices(adap
, qid
, &hw_pidx
, &hw_cidx
);
3839 if (pidx
!= hw_pidx
) {
3842 if (pidx
>= hw_pidx
)
3843 delta
= pidx
- hw_pidx
;
3845 delta
= size
- hw_pidx
+ pidx
;
3847 t4_write_reg(adap
, MYPF_REG(SGE_PF_KDOORBELL
),
3848 QID(qid
) | PIDX(delta
));
3853 EXPORT_SYMBOL(cxgb4_sync_txq_pidx
);
3855 void cxgb4_disable_db_coalescing(struct net_device
*dev
)
3857 struct adapter
*adap
;
3859 adap
= netdev2adap(dev
);
3860 t4_set_reg_field(adap
, A_SGE_DOORBELL_CONTROL
, F_NOCOALESCE
,
3863 EXPORT_SYMBOL(cxgb4_disable_db_coalescing
);
3865 void cxgb4_enable_db_coalescing(struct net_device
*dev
)
3867 struct adapter
*adap
;
3869 adap
= netdev2adap(dev
);
3870 t4_set_reg_field(adap
, A_SGE_DOORBELL_CONTROL
, F_NOCOALESCE
, 0);
3872 EXPORT_SYMBOL(cxgb4_enable_db_coalescing
);
3874 int cxgb4_read_tpte(struct net_device
*dev
, u32 stag
, __be32
*tpte
)
3876 struct adapter
*adap
;
3877 u32 offset
, memtype
, memaddr
;
3878 u32 edc0_size
, edc1_size
, mc0_size
, mc1_size
;
3879 u32 edc0_end
, edc1_end
, mc0_end
, mc1_end
;
3882 adap
= netdev2adap(dev
);
3884 offset
= ((stag
>> 8) * 32) + adap
->vres
.stag
.start
;
3886 /* Figure out where the offset lands in the Memory Type/Address scheme.
3887 * This code assumes that the memory is laid out starting at offset 0
3888 * with no breaks as: EDC0, EDC1, MC0, MC1. All cards have both EDC0
3889 * and EDC1. Some cards will have neither MC0 nor MC1, most cards have
3890 * MC0, and some have both MC0 and MC1.
3892 edc0_size
= EDRAM_SIZE_GET(t4_read_reg(adap
, MA_EDRAM0_BAR
)) << 20;
3893 edc1_size
= EDRAM_SIZE_GET(t4_read_reg(adap
, MA_EDRAM1_BAR
)) << 20;
3894 mc0_size
= EXT_MEM_SIZE_GET(t4_read_reg(adap
, MA_EXT_MEMORY_BAR
)) << 20;
3896 edc0_end
= edc0_size
;
3897 edc1_end
= edc0_end
+ edc1_size
;
3898 mc0_end
= edc1_end
+ mc0_size
;
3900 if (offset
< edc0_end
) {
3903 } else if (offset
< edc1_end
) {
3905 memaddr
= offset
- edc0_end
;
3907 if (offset
< mc0_end
) {
3909 memaddr
= offset
- edc1_end
;
3910 } else if (is_t4(adap
->params
.chip
)) {
3911 /* T4 only has a single memory channel */
3914 mc1_size
= EXT_MEM_SIZE_GET(
3916 MA_EXT_MEMORY1_BAR
)) << 20;
3917 mc1_end
= mc0_end
+ mc1_size
;
3918 if (offset
< mc1_end
) {
3920 memaddr
= offset
- mc0_end
;
3922 /* offset beyond the end of any memory */
3928 spin_lock(&adap
->win0_lock
);
3929 ret
= t4_memory_rw(adap
, 0, memtype
, memaddr
, 32, tpte
, T4_MEMORY_READ
);
3930 spin_unlock(&adap
->win0_lock
);
3934 dev_err(adap
->pdev_dev
, "stag %#x, offset %#x out of range\n",
3938 EXPORT_SYMBOL(cxgb4_read_tpte
);
3940 u64
cxgb4_read_sge_timestamp(struct net_device
*dev
)
3943 struct adapter
*adap
;
3945 adap
= netdev2adap(dev
);
3946 lo
= t4_read_reg(adap
, SGE_TIMESTAMP_LO
);
3947 hi
= GET_TSVAL(t4_read_reg(adap
, SGE_TIMESTAMP_HI
));
3949 return ((u64
)hi
<< 32) | (u64
)lo
;
3951 EXPORT_SYMBOL(cxgb4_read_sge_timestamp
);
3953 static struct pci_driver cxgb4_driver
;
3955 static void check_neigh_update(struct neighbour
*neigh
)
3957 const struct device
*parent
;
3958 const struct net_device
*netdev
= neigh
->dev
;
3960 if (netdev
->priv_flags
& IFF_802_1Q_VLAN
)
3961 netdev
= vlan_dev_real_dev(netdev
);
3962 parent
= netdev
->dev
.parent
;
3963 if (parent
&& parent
->driver
== &cxgb4_driver
.driver
)
3964 t4_l2t_update(dev_get_drvdata(parent
), neigh
);
3967 static int netevent_cb(struct notifier_block
*nb
, unsigned long event
,
3971 case NETEVENT_NEIGH_UPDATE
:
3972 check_neigh_update(data
);
3974 case NETEVENT_REDIRECT
:
3981 static bool netevent_registered
;
3982 static struct notifier_block cxgb4_netevent_nb
= {
3983 .notifier_call
= netevent_cb
3986 static void drain_db_fifo(struct adapter
*adap
, int usecs
)
3988 u32 v1
, v2
, lp_count
, hp_count
;
3991 v1
= t4_read_reg(adap
, A_SGE_DBFIFO_STATUS
);
3992 v2
= t4_read_reg(adap
, SGE_DBFIFO_STATUS2
);
3993 if (is_t4(adap
->params
.chip
)) {
3994 lp_count
= G_LP_COUNT(v1
);
3995 hp_count
= G_HP_COUNT(v1
);
3997 lp_count
= G_LP_COUNT_T5(v1
);
3998 hp_count
= G_HP_COUNT_T5(v2
);
4001 if (lp_count
== 0 && hp_count
== 0)
4003 set_current_state(TASK_UNINTERRUPTIBLE
);
4004 schedule_timeout(usecs_to_jiffies(usecs
));
4008 static void disable_txq_db(struct sge_txq
*q
)
4010 unsigned long flags
;
4012 spin_lock_irqsave(&q
->db_lock
, flags
);
4014 spin_unlock_irqrestore(&q
->db_lock
, flags
);
4017 static void enable_txq_db(struct adapter
*adap
, struct sge_txq
*q
)
4019 spin_lock_irq(&q
->db_lock
);
4020 if (q
->db_pidx_inc
) {
4021 /* Make sure that all writes to the TX descriptors
4022 * are committed before we tell HW about them.
4025 t4_write_reg(adap
, MYPF_REG(SGE_PF_KDOORBELL
),
4026 QID(q
->cntxt_id
) | PIDX(q
->db_pidx_inc
));
4030 spin_unlock_irq(&q
->db_lock
);
4033 static void disable_dbs(struct adapter
*adap
)
4037 for_each_ethrxq(&adap
->sge
, i
)
4038 disable_txq_db(&adap
->sge
.ethtxq
[i
].q
);
4039 for_each_ofldrxq(&adap
->sge
, i
)
4040 disable_txq_db(&adap
->sge
.ofldtxq
[i
].q
);
4041 for_each_port(adap
, i
)
4042 disable_txq_db(&adap
->sge
.ctrlq
[i
].q
);
4045 static void enable_dbs(struct adapter
*adap
)
4049 for_each_ethrxq(&adap
->sge
, i
)
4050 enable_txq_db(adap
, &adap
->sge
.ethtxq
[i
].q
);
4051 for_each_ofldrxq(&adap
->sge
, i
)
4052 enable_txq_db(adap
, &adap
->sge
.ofldtxq
[i
].q
);
4053 for_each_port(adap
, i
)
4054 enable_txq_db(adap
, &adap
->sge
.ctrlq
[i
].q
);
4057 static void notify_rdma_uld(struct adapter
*adap
, enum cxgb4_control cmd
)
4059 if (adap
->uld_handle
[CXGB4_ULD_RDMA
])
4060 ulds
[CXGB4_ULD_RDMA
].control(adap
->uld_handle
[CXGB4_ULD_RDMA
],
4064 static void process_db_full(struct work_struct
*work
)
4066 struct adapter
*adap
;
4068 adap
= container_of(work
, struct adapter
, db_full_task
);
4070 drain_db_fifo(adap
, dbfifo_drain_delay
);
4072 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_EMPTY
);
4073 t4_set_reg_field(adap
, SGE_INT_ENABLE3
,
4074 DBFIFO_HP_INT
| DBFIFO_LP_INT
,
4075 DBFIFO_HP_INT
| DBFIFO_LP_INT
);
4078 static void sync_txq_pidx(struct adapter
*adap
, struct sge_txq
*q
)
4080 u16 hw_pidx
, hw_cidx
;
4083 spin_lock_irq(&q
->db_lock
);
4084 ret
= read_eq_indices(adap
, (u16
)q
->cntxt_id
, &hw_pidx
, &hw_cidx
);
4087 if (q
->db_pidx
!= hw_pidx
) {
4090 if (q
->db_pidx
>= hw_pidx
)
4091 delta
= q
->db_pidx
- hw_pidx
;
4093 delta
= q
->size
- hw_pidx
+ q
->db_pidx
;
4095 t4_write_reg(adap
, MYPF_REG(SGE_PF_KDOORBELL
),
4096 QID(q
->cntxt_id
) | PIDX(delta
));
4101 spin_unlock_irq(&q
->db_lock
);
4103 CH_WARN(adap
, "DB drop recovery failed.\n");
4105 static void recover_all_queues(struct adapter
*adap
)
4109 for_each_ethrxq(&adap
->sge
, i
)
4110 sync_txq_pidx(adap
, &adap
->sge
.ethtxq
[i
].q
);
4111 for_each_ofldrxq(&adap
->sge
, i
)
4112 sync_txq_pidx(adap
, &adap
->sge
.ofldtxq
[i
].q
);
4113 for_each_port(adap
, i
)
4114 sync_txq_pidx(adap
, &adap
->sge
.ctrlq
[i
].q
);
4117 static void process_db_drop(struct work_struct
*work
)
4119 struct adapter
*adap
;
4121 adap
= container_of(work
, struct adapter
, db_drop_task
);
4123 if (is_t4(adap
->params
.chip
)) {
4124 drain_db_fifo(adap
, dbfifo_drain_delay
);
4125 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_DROP
);
4126 drain_db_fifo(adap
, dbfifo_drain_delay
);
4127 recover_all_queues(adap
);
4128 drain_db_fifo(adap
, dbfifo_drain_delay
);
4130 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_EMPTY
);
4132 u32 dropped_db
= t4_read_reg(adap
, 0x010ac);
4133 u16 qid
= (dropped_db
>> 15) & 0x1ffff;
4134 u16 pidx_inc
= dropped_db
& 0x1fff;
4136 unsigned short udb_density
;
4137 unsigned long qpshift
;
4141 dev_warn(adap
->pdev_dev
,
4142 "Dropped DB 0x%x qid %d bar2 %d coalesce %d pidx %d\n",
4144 (dropped_db
>> 14) & 1,
4145 (dropped_db
>> 13) & 1,
4148 drain_db_fifo(adap
, 1);
4150 s_qpp
= QUEUESPERPAGEPF1
* adap
->fn
;
4151 udb_density
= 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adap
,
4152 SGE_EGRESS_QUEUES_PER_PAGE_PF
) >> s_qpp
);
4153 qpshift
= PAGE_SHIFT
- ilog2(udb_density
);
4154 udb
= qid
<< qpshift
;
4156 page
= udb
/ PAGE_SIZE
;
4157 udb
+= (qid
- (page
* udb_density
)) * 128;
4159 writel(PIDX(pidx_inc
), adap
->bar2
+ udb
+ 8);
4161 /* Re-enable BAR2 WC */
4162 t4_set_reg_field(adap
, 0x10b0, 1<<15, 1<<15);
4165 t4_set_reg_field(adap
, A_SGE_DOORBELL_CONTROL
, F_DROPPED_DB
, 0);
4168 void t4_db_full(struct adapter
*adap
)
4170 if (is_t4(adap
->params
.chip
)) {
4172 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_FULL
);
4173 t4_set_reg_field(adap
, SGE_INT_ENABLE3
,
4174 DBFIFO_HP_INT
| DBFIFO_LP_INT
, 0);
4175 queue_work(adap
->workq
, &adap
->db_full_task
);
4179 void t4_db_dropped(struct adapter
*adap
)
4181 if (is_t4(adap
->params
.chip
)) {
4183 notify_rdma_uld(adap
, CXGB4_CONTROL_DB_FULL
);
4185 queue_work(adap
->workq
, &adap
->db_drop_task
);
4188 static void uld_attach(struct adapter
*adap
, unsigned int uld
)
4191 struct cxgb4_lld_info lli
;
4194 lli
.pdev
= adap
->pdev
;
4196 lli
.l2t
= adap
->l2t
;
4197 lli
.tids
= &adap
->tids
;
4198 lli
.ports
= adap
->port
;
4199 lli
.vr
= &adap
->vres
;
4200 lli
.mtus
= adap
->params
.mtus
;
4201 if (uld
== CXGB4_ULD_RDMA
) {
4202 lli
.rxq_ids
= adap
->sge
.rdma_rxq
;
4203 lli
.ciq_ids
= adap
->sge
.rdma_ciq
;
4204 lli
.nrxq
= adap
->sge
.rdmaqs
;
4205 lli
.nciq
= adap
->sge
.rdmaciqs
;
4206 } else if (uld
== CXGB4_ULD_ISCSI
) {
4207 lli
.rxq_ids
= adap
->sge
.ofld_rxq
;
4208 lli
.nrxq
= adap
->sge
.ofldqsets
;
4210 lli
.ntxq
= adap
->sge
.ofldqsets
;
4211 lli
.nchan
= adap
->params
.nports
;
4212 lli
.nports
= adap
->params
.nports
;
4213 lli
.wr_cred
= adap
->params
.ofldq_wr_cred
;
4214 lli
.adapter_type
= adap
->params
.chip
;
4215 lli
.iscsi_iolen
= MAXRXDATA_GET(t4_read_reg(adap
, TP_PARA_REG2
));
4216 lli
.cclk_ps
= 1000000000 / adap
->params
.vpd
.cclk
;
4217 lli
.udb_density
= 1 << QUEUESPERPAGEPF0_GET(
4218 t4_read_reg(adap
, SGE_EGRESS_QUEUES_PER_PAGE_PF
) >>
4220 lli
.ucq_density
= 1 << QUEUESPERPAGEPF0_GET(
4221 t4_read_reg(adap
, SGE_INGRESS_QUEUES_PER_PAGE_PF
) >>
4223 lli
.filt_mode
= adap
->params
.tp
.vlan_pri_map
;
4224 /* MODQ_REQ_MAP sets queues 0-3 to chan 0-3 */
4225 for (i
= 0; i
< NCHAN
; i
++)
4227 lli
.gts_reg
= adap
->regs
+ MYPF_REG(SGE_PF_GTS
);
4228 lli
.db_reg
= adap
->regs
+ MYPF_REG(SGE_PF_KDOORBELL
);
4229 lli
.fw_vers
= adap
->params
.fw_vers
;
4230 lli
.dbfifo_int_thresh
= dbfifo_int_thresh
;
4231 lli
.sge_ingpadboundary
= adap
->sge
.fl_align
;
4232 lli
.sge_egrstatuspagesize
= adap
->sge
.stat_len
;
4233 lli
.sge_pktshift
= adap
->sge
.pktshift
;
4234 lli
.enable_fw_ofld_conn
= adap
->flags
& FW_OFLD_CONN
;
4235 lli
.max_ordird_qp
= adap
->params
.max_ordird_qp
;
4236 lli
.max_ird_adapter
= adap
->params
.max_ird_adapter
;
4237 lli
.ulptx_memwrite_dsgl
= adap
->params
.ulptx_memwrite_dsgl
;
4239 handle
= ulds
[uld
].add(&lli
);
4240 if (IS_ERR(handle
)) {
4241 dev_warn(adap
->pdev_dev
,
4242 "could not attach to the %s driver, error %ld\n",
4243 uld_str
[uld
], PTR_ERR(handle
));
4247 adap
->uld_handle
[uld
] = handle
;
4249 if (!netevent_registered
) {
4250 register_netevent_notifier(&cxgb4_netevent_nb
);
4251 netevent_registered
= true;
4254 if (adap
->flags
& FULL_INIT_DONE
)
4255 ulds
[uld
].state_change(handle
, CXGB4_STATE_UP
);
4258 static void attach_ulds(struct adapter
*adap
)
4262 spin_lock(&adap_rcu_lock
);
4263 list_add_tail_rcu(&adap
->rcu_node
, &adap_rcu_list
);
4264 spin_unlock(&adap_rcu_lock
);
4266 mutex_lock(&uld_mutex
);
4267 list_add_tail(&adap
->list_node
, &adapter_list
);
4268 for (i
= 0; i
< CXGB4_ULD_MAX
; i
++)
4270 uld_attach(adap
, i
);
4271 mutex_unlock(&uld_mutex
);
4274 static void detach_ulds(struct adapter
*adap
)
4278 mutex_lock(&uld_mutex
);
4279 list_del(&adap
->list_node
);
4280 for (i
= 0; i
< CXGB4_ULD_MAX
; i
++)
4281 if (adap
->uld_handle
[i
]) {
4282 ulds
[i
].state_change(adap
->uld_handle
[i
],
4283 CXGB4_STATE_DETACH
);
4284 adap
->uld_handle
[i
] = NULL
;
4286 if (netevent_registered
&& list_empty(&adapter_list
)) {
4287 unregister_netevent_notifier(&cxgb4_netevent_nb
);
4288 netevent_registered
= false;
4290 mutex_unlock(&uld_mutex
);
4292 spin_lock(&adap_rcu_lock
);
4293 list_del_rcu(&adap
->rcu_node
);
4294 spin_unlock(&adap_rcu_lock
);
4297 static void notify_ulds(struct adapter
*adap
, enum cxgb4_state new_state
)
4301 mutex_lock(&uld_mutex
);
4302 for (i
= 0; i
< CXGB4_ULD_MAX
; i
++)
4303 if (adap
->uld_handle
[i
])
4304 ulds
[i
].state_change(adap
->uld_handle
[i
], new_state
);
4305 mutex_unlock(&uld_mutex
);
4309 * cxgb4_register_uld - register an upper-layer driver
4310 * @type: the ULD type
4311 * @p: the ULD methods
4313 * Registers an upper-layer driver with this driver and notifies the ULD
4314 * about any presently available devices that support its type. Returns
4315 * %-EBUSY if a ULD of the same type is already registered.
4317 int cxgb4_register_uld(enum cxgb4_uld type
, const struct cxgb4_uld_info
*p
)
4320 struct adapter
*adap
;
4322 if (type
>= CXGB4_ULD_MAX
)
4324 mutex_lock(&uld_mutex
);
4325 if (ulds
[type
].add
) {
4330 list_for_each_entry(adap
, &adapter_list
, list_node
)
4331 uld_attach(adap
, type
);
4332 out
: mutex_unlock(&uld_mutex
);
4335 EXPORT_SYMBOL(cxgb4_register_uld
);
4338 * cxgb4_unregister_uld - unregister an upper-layer driver
4339 * @type: the ULD type
4341 * Unregisters an existing upper-layer driver.
4343 int cxgb4_unregister_uld(enum cxgb4_uld type
)
4345 struct adapter
*adap
;
4347 if (type
>= CXGB4_ULD_MAX
)
4349 mutex_lock(&uld_mutex
);
4350 list_for_each_entry(adap
, &adapter_list
, list_node
)
4351 adap
->uld_handle
[type
] = NULL
;
4352 ulds
[type
].add
= NULL
;
4353 mutex_unlock(&uld_mutex
);
4356 EXPORT_SYMBOL(cxgb4_unregister_uld
);
4358 /* Check if netdev on which event is occured belongs to us or not. Return
4359 * success (true) if it belongs otherwise failure (false).
4360 * Called with rcu_read_lock() held.
4362 static bool cxgb4_netdev(const struct net_device
*netdev
)
4364 struct adapter
*adap
;
4367 list_for_each_entry_rcu(adap
, &adap_rcu_list
, rcu_node
)
4368 for (i
= 0; i
< MAX_NPORTS
; i
++)
4369 if (adap
->port
[i
] == netdev
)
4374 static int clip_add(struct net_device
*event_dev
, struct inet6_ifaddr
*ifa
,
4375 unsigned long event
)
4377 int ret
= NOTIFY_DONE
;
4380 if (cxgb4_netdev(event_dev
)) {
4383 ret
= cxgb4_clip_get(event_dev
,
4384 (const struct in6_addr
*)ifa
->addr
.s6_addr
);
4392 cxgb4_clip_release(event_dev
,
4393 (const struct in6_addr
*)ifa
->addr
.s6_addr
);
4404 static int cxgb4_inet6addr_handler(struct notifier_block
*this,
4405 unsigned long event
, void *data
)
4407 struct inet6_ifaddr
*ifa
= data
;
4408 struct net_device
*event_dev
;
4409 int ret
= NOTIFY_DONE
;
4410 struct bonding
*bond
= netdev_priv(ifa
->idev
->dev
);
4411 struct list_head
*iter
;
4412 struct slave
*slave
;
4413 struct pci_dev
*first_pdev
= NULL
;
4415 if (ifa
->idev
->dev
->priv_flags
& IFF_802_1Q_VLAN
) {
4416 event_dev
= vlan_dev_real_dev(ifa
->idev
->dev
);
4417 ret
= clip_add(event_dev
, ifa
, event
);
4418 } else if (ifa
->idev
->dev
->flags
& IFF_MASTER
) {
4419 /* It is possible that two different adapters are bonded in one
4420 * bond. We need to find such different adapters and add clip
4421 * in all of them only once.
4423 bond_for_each_slave(bond
, slave
, iter
) {
4425 ret
= clip_add(slave
->dev
, ifa
, event
);
4426 /* If clip_add is success then only initialize
4427 * first_pdev since it means it is our device
4429 if (ret
== NOTIFY_OK
)
4430 first_pdev
= to_pci_dev(
4431 slave
->dev
->dev
.parent
);
4432 } else if (first_pdev
!=
4433 to_pci_dev(slave
->dev
->dev
.parent
))
4434 ret
= clip_add(slave
->dev
, ifa
, event
);
4437 ret
= clip_add(ifa
->idev
->dev
, ifa
, event
);
4442 static struct notifier_block cxgb4_inet6addr_notifier
= {
4443 .notifier_call
= cxgb4_inet6addr_handler
4446 /* Retrieves IPv6 addresses from a root device (bond, vlan) associated with
4447 * a physical device.
4448 * The physical device reference is needed to send the actul CLIP command.
4450 static int update_dev_clip(struct net_device
*root_dev
, struct net_device
*dev
)
4452 struct inet6_dev
*idev
= NULL
;
4453 struct inet6_ifaddr
*ifa
;
4456 idev
= __in6_dev_get(root_dev
);
4460 read_lock_bh(&idev
->lock
);
4461 list_for_each_entry(ifa
, &idev
->addr_list
, if_list
) {
4462 ret
= cxgb4_clip_get(dev
,
4463 (const struct in6_addr
*)ifa
->addr
.s6_addr
);
4467 read_unlock_bh(&idev
->lock
);
4472 static int update_root_dev_clip(struct net_device
*dev
)
4474 struct net_device
*root_dev
= NULL
;
4477 /* First populate the real net device's IPv6 addresses */
4478 ret
= update_dev_clip(dev
, dev
);
4482 /* Parse all bond and vlan devices layered on top of the physical dev */
4483 for (i
= 0; i
< VLAN_N_VID
; i
++) {
4484 root_dev
= __vlan_find_dev_deep_rcu(dev
, htons(ETH_P_8021Q
), i
);
4488 ret
= update_dev_clip(root_dev
, dev
);
4495 static void update_clip(const struct adapter
*adap
)
4498 struct net_device
*dev
;
4503 for (i
= 0; i
< MAX_NPORTS
; i
++) {
4504 dev
= adap
->port
[i
];
4508 ret
= update_root_dev_clip(dev
);
4517 * cxgb_up - enable the adapter
4518 * @adap: adapter being enabled
4520 * Called when the first port is enabled, this function performs the
4521 * actions necessary to make an adapter operational, such as completing
4522 * the initialization of HW modules, and enabling interrupts.
4524 * Must be called with the rtnl lock held.
4526 static int cxgb_up(struct adapter
*adap
)
4530 err
= setup_sge_queues(adap
);
4533 err
= setup_rss(adap
);
4537 if (adap
->flags
& USING_MSIX
) {
4538 name_msix_vecs(adap
);
4539 err
= request_irq(adap
->msix_info
[0].vec
, t4_nondata_intr
, 0,
4540 adap
->msix_info
[0].desc
, adap
);
4544 err
= request_msix_queue_irqs(adap
);
4546 free_irq(adap
->msix_info
[0].vec
, adap
);
4550 err
= request_irq(adap
->pdev
->irq
, t4_intr_handler(adap
),
4551 (adap
->flags
& USING_MSI
) ? 0 : IRQF_SHARED
,
4552 adap
->port
[0]->name
, adap
);
4558 t4_intr_enable(adap
);
4559 adap
->flags
|= FULL_INIT_DONE
;
4560 notify_ulds(adap
, CXGB4_STATE_UP
);
4565 dev_err(adap
->pdev_dev
, "request_irq failed, err %d\n", err
);
4567 t4_free_sge_resources(adap
);
4571 static void cxgb_down(struct adapter
*adapter
)
4573 t4_intr_disable(adapter
);
4574 cancel_work_sync(&adapter
->tid_release_task
);
4575 cancel_work_sync(&adapter
->db_full_task
);
4576 cancel_work_sync(&adapter
->db_drop_task
);
4577 adapter
->tid_release_task_busy
= false;
4578 adapter
->tid_release_head
= NULL
;
4580 if (adapter
->flags
& USING_MSIX
) {
4581 free_msix_queue_irqs(adapter
);
4582 free_irq(adapter
->msix_info
[0].vec
, adapter
);
4584 free_irq(adapter
->pdev
->irq
, adapter
);
4585 quiesce_rx(adapter
);
4586 t4_sge_stop(adapter
);
4587 t4_free_sge_resources(adapter
);
4588 adapter
->flags
&= ~FULL_INIT_DONE
;
4592 * net_device operations
4594 static int cxgb_open(struct net_device
*dev
)
4597 struct port_info
*pi
= netdev_priv(dev
);
4598 struct adapter
*adapter
= pi
->adapter
;
4600 netif_carrier_off(dev
);
4602 if (!(adapter
->flags
& FULL_INIT_DONE
)) {
4603 err
= cxgb_up(adapter
);
4608 err
= link_start(dev
);
4610 netif_tx_start_all_queues(dev
);
4614 static int cxgb_close(struct net_device
*dev
)
4616 struct port_info
*pi
= netdev_priv(dev
);
4617 struct adapter
*adapter
= pi
->adapter
;
4619 netif_tx_stop_all_queues(dev
);
4620 netif_carrier_off(dev
);
4621 return t4_enable_vi(adapter
, adapter
->fn
, pi
->viid
, false, false);
4624 /* Return an error number if the indicated filter isn't writable ...
4626 static int writable_filter(struct filter_entry
*f
)
4636 /* Delete the filter at the specified index (if valid). The checks for all
4637 * the common problems with doing this like the filter being locked, currently
4638 * pending in another operation, etc.
4640 static int delete_filter(struct adapter
*adapter
, unsigned int fidx
)
4642 struct filter_entry
*f
;
4645 if (fidx
>= adapter
->tids
.nftids
+ adapter
->tids
.nsftids
)
4648 f
= &adapter
->tids
.ftid_tab
[fidx
];
4649 ret
= writable_filter(f
);
4653 return del_filter_wr(adapter
, fidx
);
4658 int cxgb4_create_server_filter(const struct net_device
*dev
, unsigned int stid
,
4659 __be32 sip
, __be16 sport
, __be16 vlan
,
4660 unsigned int queue
, unsigned char port
, unsigned char mask
)
4663 struct filter_entry
*f
;
4664 struct adapter
*adap
;
4668 adap
= netdev2adap(dev
);
4670 /* Adjust stid to correct filter index */
4671 stid
-= adap
->tids
.sftid_base
;
4672 stid
+= adap
->tids
.nftids
;
4674 /* Check to make sure the filter requested is writable ...
4676 f
= &adap
->tids
.ftid_tab
[stid
];
4677 ret
= writable_filter(f
);
4681 /* Clear out any old resources being used by the filter before
4682 * we start constructing the new filter.
4685 clear_filter(adap
, f
);
4687 /* Clear out filter specifications */
4688 memset(&f
->fs
, 0, sizeof(struct ch_filter_specification
));
4689 f
->fs
.val
.lport
= cpu_to_be16(sport
);
4690 f
->fs
.mask
.lport
= ~0;
4692 if ((val
[0] | val
[1] | val
[2] | val
[3]) != 0) {
4693 for (i
= 0; i
< 4; i
++) {
4694 f
->fs
.val
.lip
[i
] = val
[i
];
4695 f
->fs
.mask
.lip
[i
] = ~0;
4697 if (adap
->params
.tp
.vlan_pri_map
& F_PORT
) {
4698 f
->fs
.val
.iport
= port
;
4699 f
->fs
.mask
.iport
= mask
;
4703 if (adap
->params
.tp
.vlan_pri_map
& F_PROTOCOL
) {
4704 f
->fs
.val
.proto
= IPPROTO_TCP
;
4705 f
->fs
.mask
.proto
= ~0;
4710 /* Mark filter as locked */
4714 ret
= set_filter_wr(adap
, stid
);
4716 clear_filter(adap
, f
);
4722 EXPORT_SYMBOL(cxgb4_create_server_filter
);
4724 int cxgb4_remove_server_filter(const struct net_device
*dev
, unsigned int stid
,
4725 unsigned int queue
, bool ipv6
)
4728 struct filter_entry
*f
;
4729 struct adapter
*adap
;
4731 adap
= netdev2adap(dev
);
4733 /* Adjust stid to correct filter index */
4734 stid
-= adap
->tids
.sftid_base
;
4735 stid
+= adap
->tids
.nftids
;
4737 f
= &adap
->tids
.ftid_tab
[stid
];
4738 /* Unlock the filter */
4741 ret
= delete_filter(adap
, stid
);
4747 EXPORT_SYMBOL(cxgb4_remove_server_filter
);
4749 static struct rtnl_link_stats64
*cxgb_get_stats(struct net_device
*dev
,
4750 struct rtnl_link_stats64
*ns
)
4752 struct port_stats stats
;
4753 struct port_info
*p
= netdev_priv(dev
);
4754 struct adapter
*adapter
= p
->adapter
;
4756 /* Block retrieving statistics during EEH error
4757 * recovery. Otherwise, the recovery might fail
4758 * and the PCI device will be removed permanently
4760 spin_lock(&adapter
->stats_lock
);
4761 if (!netif_device_present(dev
)) {
4762 spin_unlock(&adapter
->stats_lock
);
4765 t4_get_port_stats(adapter
, p
->tx_chan
, &stats
);
4766 spin_unlock(&adapter
->stats_lock
);
4768 ns
->tx_bytes
= stats
.tx_octets
;
4769 ns
->tx_packets
= stats
.tx_frames
;
4770 ns
->rx_bytes
= stats
.rx_octets
;
4771 ns
->rx_packets
= stats
.rx_frames
;
4772 ns
->multicast
= stats
.rx_mcast_frames
;
4774 /* detailed rx_errors */
4775 ns
->rx_length_errors
= stats
.rx_jabber
+ stats
.rx_too_long
+
4777 ns
->rx_over_errors
= 0;
4778 ns
->rx_crc_errors
= stats
.rx_fcs_err
;
4779 ns
->rx_frame_errors
= stats
.rx_symbol_err
;
4780 ns
->rx_fifo_errors
= stats
.rx_ovflow0
+ stats
.rx_ovflow1
+
4781 stats
.rx_ovflow2
+ stats
.rx_ovflow3
+
4782 stats
.rx_trunc0
+ stats
.rx_trunc1
+
4783 stats
.rx_trunc2
+ stats
.rx_trunc3
;
4784 ns
->rx_missed_errors
= 0;
4786 /* detailed tx_errors */
4787 ns
->tx_aborted_errors
= 0;
4788 ns
->tx_carrier_errors
= 0;
4789 ns
->tx_fifo_errors
= 0;
4790 ns
->tx_heartbeat_errors
= 0;
4791 ns
->tx_window_errors
= 0;
4793 ns
->tx_errors
= stats
.tx_error_frames
;
4794 ns
->rx_errors
= stats
.rx_symbol_err
+ stats
.rx_fcs_err
+
4795 ns
->rx_length_errors
+ stats
.rx_len_err
+ ns
->rx_fifo_errors
;
4799 static int cxgb_ioctl(struct net_device
*dev
, struct ifreq
*req
, int cmd
)
4802 int ret
= 0, prtad
, devad
;
4803 struct port_info
*pi
= netdev_priv(dev
);
4804 struct mii_ioctl_data
*data
= (struct mii_ioctl_data
*)&req
->ifr_data
;
4808 if (pi
->mdio_addr
< 0)
4810 data
->phy_id
= pi
->mdio_addr
;
4814 if (mdio_phy_id_is_c45(data
->phy_id
)) {
4815 prtad
= mdio_phy_id_prtad(data
->phy_id
);
4816 devad
= mdio_phy_id_devad(data
->phy_id
);
4817 } else if (data
->phy_id
< 32) {
4818 prtad
= data
->phy_id
;
4820 data
->reg_num
&= 0x1f;
4824 mbox
= pi
->adapter
->fn
;
4825 if (cmd
== SIOCGMIIREG
)
4826 ret
= t4_mdio_rd(pi
->adapter
, mbox
, prtad
, devad
,
4827 data
->reg_num
, &data
->val_out
);
4829 ret
= t4_mdio_wr(pi
->adapter
, mbox
, prtad
, devad
,
4830 data
->reg_num
, data
->val_in
);
4838 static void cxgb_set_rxmode(struct net_device
*dev
)
4840 /* unfortunately we can't return errors to the stack */
4841 set_rxmode(dev
, -1, false);
4844 static int cxgb_change_mtu(struct net_device
*dev
, int new_mtu
)
4847 struct port_info
*pi
= netdev_priv(dev
);
4849 if (new_mtu
< 81 || new_mtu
> MAX_MTU
) /* accommodate SACK */
4851 ret
= t4_set_rxmode(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
, new_mtu
, -1,
4858 static int cxgb_set_mac_addr(struct net_device
*dev
, void *p
)
4861 struct sockaddr
*addr
= p
;
4862 struct port_info
*pi
= netdev_priv(dev
);
4864 if (!is_valid_ether_addr(addr
->sa_data
))
4865 return -EADDRNOTAVAIL
;
4867 ret
= t4_change_mac(pi
->adapter
, pi
->adapter
->fn
, pi
->viid
,
4868 pi
->xact_addr_filt
, addr
->sa_data
, true, true);
4872 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
4873 pi
->xact_addr_filt
= ret
;
4877 #ifdef CONFIG_NET_POLL_CONTROLLER
4878 static void cxgb_netpoll(struct net_device
*dev
)
4880 struct port_info
*pi
= netdev_priv(dev
);
4881 struct adapter
*adap
= pi
->adapter
;
4883 if (adap
->flags
& USING_MSIX
) {
4885 struct sge_eth_rxq
*rx
= &adap
->sge
.ethrxq
[pi
->first_qset
];
4887 for (i
= pi
->nqsets
; i
; i
--, rx
++)
4888 t4_sge_intr_msix(0, &rx
->rspq
);
4890 t4_intr_handler(adap
)(0, adap
);
4894 static const struct net_device_ops cxgb4_netdev_ops
= {
4895 .ndo_open
= cxgb_open
,
4896 .ndo_stop
= cxgb_close
,
4897 .ndo_start_xmit
= t4_eth_xmit
,
4898 .ndo_select_queue
= cxgb_select_queue
,
4899 .ndo_get_stats64
= cxgb_get_stats
,
4900 .ndo_set_rx_mode
= cxgb_set_rxmode
,
4901 .ndo_set_mac_address
= cxgb_set_mac_addr
,
4902 .ndo_set_features
= cxgb_set_features
,
4903 .ndo_validate_addr
= eth_validate_addr
,
4904 .ndo_do_ioctl
= cxgb_ioctl
,
4905 .ndo_change_mtu
= cxgb_change_mtu
,
4906 #ifdef CONFIG_NET_POLL_CONTROLLER
4907 .ndo_poll_controller
= cxgb_netpoll
,
4911 void t4_fatal_err(struct adapter
*adap
)
4913 t4_set_reg_field(adap
, SGE_CONTROL
, GLOBALENABLE
, 0);
4914 t4_intr_disable(adap
);
4915 dev_alert(adap
->pdev_dev
, "encountered fatal error, adapter stopped\n");
4918 /* Return the specified PCI-E Configuration Space register from our Physical
4919 * Function. We try first via a Firmware LDST Command since we prefer to let
4920 * the firmware own all of these registers, but if that fails we go for it
4921 * directly ourselves.
4923 static u32
t4_read_pcie_cfg4(struct adapter
*adap
, int reg
)
4925 struct fw_ldst_cmd ldst_cmd
;
4929 /* Construct and send the Firmware LDST Command to retrieve the
4930 * specified PCI-E Configuration Space register.
4932 memset(&ldst_cmd
, 0, sizeof(ldst_cmd
));
4933 ldst_cmd
.op_to_addrspace
=
4934 htonl(FW_CMD_OP(FW_LDST_CMD
) |
4937 FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FUNC_PCIE
));
4938 ldst_cmd
.cycles_to_len16
= htonl(FW_LEN16(ldst_cmd
));
4939 ldst_cmd
.u
.pcie
.select_naccess
= FW_LDST_CMD_NACCESS(1);
4940 ldst_cmd
.u
.pcie
.ctrl_to_fn
=
4941 (FW_LDST_CMD_LC
| FW_LDST_CMD_FN(adap
->fn
));
4942 ldst_cmd
.u
.pcie
.r
= reg
;
4943 ret
= t4_wr_mbox(adap
, adap
->mbox
, &ldst_cmd
, sizeof(ldst_cmd
),
4946 /* If the LDST Command suucceeded, exctract the returned register
4947 * value. Otherwise read it directly ourself.
4950 val
= ntohl(ldst_cmd
.u
.pcie
.data
[0]);
4952 t4_hw_pci_read_cfg4(adap
, reg
, &val
);
4957 static void setup_memwin(struct adapter
*adap
)
4959 u32 mem_win0_base
, mem_win1_base
, mem_win2_base
, mem_win2_aperture
;
4961 if (is_t4(adap
->params
.chip
)) {
4964 /* Truncation intentional: we only read the bottom 32-bits of
4965 * the 64-bit BAR0/BAR1 ... We use the hardware backdoor
4966 * mechanism to read BAR0 instead of using
4967 * pci_resource_start() because we could be operating from
4968 * within a Virtual Machine which is trapping our accesses to
4969 * our Configuration Space and we need to set up the PCI-E
4970 * Memory Window decoders with the actual addresses which will
4971 * be coming across the PCI-E link.
4973 bar0
= t4_read_pcie_cfg4(adap
, PCI_BASE_ADDRESS_0
);
4974 bar0
&= PCI_BASE_ADDRESS_MEM_MASK
;
4975 adap
->t4_bar0
= bar0
;
4977 mem_win0_base
= bar0
+ MEMWIN0_BASE
;
4978 mem_win1_base
= bar0
+ MEMWIN1_BASE
;
4979 mem_win2_base
= bar0
+ MEMWIN2_BASE
;
4980 mem_win2_aperture
= MEMWIN2_APERTURE
;
4982 /* For T5, only relative offset inside the PCIe BAR is passed */
4983 mem_win0_base
= MEMWIN0_BASE
;
4984 mem_win1_base
= MEMWIN1_BASE
;
4985 mem_win2_base
= MEMWIN2_BASE_T5
;
4986 mem_win2_aperture
= MEMWIN2_APERTURE_T5
;
4988 t4_write_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 0),
4989 mem_win0_base
| BIR(0) |
4990 WINDOW(ilog2(MEMWIN0_APERTURE
) - 10));
4991 t4_write_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 1),
4992 mem_win1_base
| BIR(0) |
4993 WINDOW(ilog2(MEMWIN1_APERTURE
) - 10));
4994 t4_write_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 2),
4995 mem_win2_base
| BIR(0) |
4996 WINDOW(ilog2(mem_win2_aperture
) - 10));
4997 t4_read_reg(adap
, PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 2));
5000 static void setup_memwin_rdma(struct adapter
*adap
)
5002 if (adap
->vres
.ocq
.size
) {
5006 start
= t4_read_pcie_cfg4(adap
, PCI_BASE_ADDRESS_2
);
5007 start
&= PCI_BASE_ADDRESS_MEM_MASK
;
5008 start
+= OCQ_WIN_OFFSET(adap
->pdev
, &adap
->vres
);
5009 sz_kb
= roundup_pow_of_two(adap
->vres
.ocq
.size
) >> 10;
5011 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN
, 3),
5012 start
| BIR(1) | WINDOW(ilog2(sz_kb
)));
5014 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET
, 3),
5015 adap
->vres
.ocq
.start
);
5017 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET
, 3));
5021 static int adap_init1(struct adapter
*adap
, struct fw_caps_config_cmd
*c
)
5026 /* get device capabilities */
5027 memset(c
, 0, sizeof(*c
));
5028 c
->op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5029 FW_CMD_REQUEST
| FW_CMD_READ
);
5030 c
->cfvalid_to_len16
= htonl(FW_LEN16(*c
));
5031 ret
= t4_wr_mbox(adap
, adap
->fn
, c
, sizeof(*c
), c
);
5035 /* select capabilities we'll be using */
5036 if (c
->niccaps
& htons(FW_CAPS_CONFIG_NIC_VM
)) {
5038 c
->niccaps
^= htons(FW_CAPS_CONFIG_NIC_VM
);
5040 c
->niccaps
= htons(FW_CAPS_CONFIG_NIC_VM
);
5041 } else if (vf_acls
) {
5042 dev_err(adap
->pdev_dev
, "virtualization ACLs not supported");
5045 c
->op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5046 FW_CMD_REQUEST
| FW_CMD_WRITE
);
5047 ret
= t4_wr_mbox(adap
, adap
->fn
, c
, sizeof(*c
), NULL
);
5051 ret
= t4_config_glbl_rss(adap
, adap
->fn
,
5052 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
,
5053 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN
|
5054 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP
);
5058 ret
= t4_cfg_pfvf(adap
, adap
->fn
, adap
->fn
, 0, MAX_EGRQ
, 64, MAX_INGQ
,
5059 0, 0, 4, 0xf, 0xf, 16, FW_CMD_CAP_PF
, FW_CMD_CAP_PF
);
5065 /* tweak some settings */
5066 t4_write_reg(adap
, TP_SHIFT_CNT
, 0x64f8849);
5067 t4_write_reg(adap
, ULP_RX_TDDP_PSZ
, HPZ0(PAGE_SHIFT
- 12));
5068 t4_write_reg(adap
, TP_PIO_ADDR
, TP_INGRESS_CONFIG
);
5069 v
= t4_read_reg(adap
, TP_PIO_DATA
);
5070 t4_write_reg(adap
, TP_PIO_DATA
, v
& ~CSUM_HAS_PSEUDO_HDR
);
5072 /* first 4 Tx modulation queues point to consecutive Tx channels */
5073 adap
->params
.tp
.tx_modq_map
= 0xE4;
5074 t4_write_reg(adap
, A_TP_TX_MOD_QUEUE_REQ_MAP
,
5075 V_TX_MOD_QUEUE_REQ_MAP(adap
->params
.tp
.tx_modq_map
));
5077 /* associate each Tx modulation queue with consecutive Tx channels */
5079 t4_write_indirect(adap
, TP_PIO_ADDR
, TP_PIO_DATA
,
5080 &v
, 1, A_TP_TX_SCHED_HDR
);
5081 t4_write_indirect(adap
, TP_PIO_ADDR
, TP_PIO_DATA
,
5082 &v
, 1, A_TP_TX_SCHED_FIFO
);
5083 t4_write_indirect(adap
, TP_PIO_ADDR
, TP_PIO_DATA
,
5084 &v
, 1, A_TP_TX_SCHED_PCMD
);
5086 #define T4_TX_MODQ_10G_WEIGHT_DEFAULT 16 /* in KB units */
5087 if (is_offload(adap
)) {
5088 t4_write_reg(adap
, A_TP_TX_MOD_QUEUE_WEIGHT0
,
5089 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5090 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5091 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5092 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT
));
5093 t4_write_reg(adap
, A_TP_TX_MOD_CHANNEL_WEIGHT
,
5094 V_TX_MODQ_WEIGHT0(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5095 V_TX_MODQ_WEIGHT1(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5096 V_TX_MODQ_WEIGHT2(T4_TX_MODQ_10G_WEIGHT_DEFAULT
) |
5097 V_TX_MODQ_WEIGHT3(T4_TX_MODQ_10G_WEIGHT_DEFAULT
));
5100 /* get basic stuff going */
5101 return t4_early_init(adap
, adap
->fn
);
5105 * Max # of ATIDs. The absolute HW max is 16K but we keep it lower.
5107 #define MAX_ATIDS 8192U
5110 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5112 * If the firmware we're dealing with has Configuration File support, then
5113 * we use that to perform all configuration
5117 * Tweak configuration based on module parameters, etc. Most of these have
5118 * defaults assigned to them by Firmware Configuration Files (if we're using
5119 * them) but need to be explicitly set if we're using hard-coded
5120 * initialization. But even in the case of using Firmware Configuration
5121 * Files, we'd like to expose the ability to change these via module
5122 * parameters so these are essentially common tweaks/settings for
5123 * Configuration Files and hard-coded initialization ...
5125 static int adap_init0_tweaks(struct adapter
*adapter
)
5128 * Fix up various Host-Dependent Parameters like Page Size, Cache
5129 * Line Size, etc. The firmware default is for a 4KB Page Size and
5130 * 64B Cache Line Size ...
5132 t4_fixup_host_params(adapter
, PAGE_SIZE
, L1_CACHE_BYTES
);
5135 * Process module parameters which affect early initialization.
5137 if (rx_dma_offset
!= 2 && rx_dma_offset
!= 0) {
5138 dev_err(&adapter
->pdev
->dev
,
5139 "Ignoring illegal rx_dma_offset=%d, using 2\n",
5143 t4_set_reg_field(adapter
, SGE_CONTROL
,
5145 PKTSHIFT(rx_dma_offset
));
5148 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux
5149 * adds the pseudo header itself.
5151 t4_tp_wr_bits_indirect(adapter
, TP_INGRESS_CONFIG
,
5152 CSUM_HAS_PSEUDO_HDR
, 0);
5158 * Attempt to initialize the adapter via a Firmware Configuration File.
5160 static int adap_init0_config(struct adapter
*adapter
, int reset
)
5162 struct fw_caps_config_cmd caps_cmd
;
5163 const struct firmware
*cf
;
5164 unsigned long mtype
= 0, maddr
= 0;
5165 u32 finiver
, finicsum
, cfcsum
;
5167 int config_issued
= 0;
5168 char *fw_config_file
, fw_config_file_path
[256];
5169 char *config_name
= NULL
;
5172 * Reset device if necessary.
5175 ret
= t4_fw_reset(adapter
, adapter
->mbox
,
5176 PIORSTMODE
| PIORST
);
5182 * If we have a T4 configuration file under /lib/firmware/cxgb4/,
5183 * then use that. Otherwise, use the configuration file stored
5184 * in the adapter flash ...
5186 switch (CHELSIO_CHIP_VERSION(adapter
->params
.chip
)) {
5188 fw_config_file
= FW4_CFNAME
;
5191 fw_config_file
= FW5_CFNAME
;
5194 dev_err(adapter
->pdev_dev
, "Device %d is not supported\n",
5195 adapter
->pdev
->device
);
5200 ret
= request_firmware(&cf
, fw_config_file
, adapter
->pdev_dev
);
5202 config_name
= "On FLASH";
5203 mtype
= FW_MEMTYPE_CF_FLASH
;
5204 maddr
= t4_flash_cfg_addr(adapter
);
5206 u32 params
[7], val
[7];
5208 sprintf(fw_config_file_path
,
5209 "/lib/firmware/%s", fw_config_file
);
5210 config_name
= fw_config_file_path
;
5212 if (cf
->size
>= FLASH_CFG_MAX_SIZE
)
5215 params
[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV
) |
5216 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF
));
5217 ret
= t4_query_params(adapter
, adapter
->mbox
,
5218 adapter
->fn
, 0, 1, params
, val
);
5221 * For t4_memory_rw() below addresses and
5222 * sizes have to be in terms of multiples of 4
5223 * bytes. So, if the Configuration File isn't
5224 * a multiple of 4 bytes in length we'll have
5225 * to write that out separately since we can't
5226 * guarantee that the bytes following the
5227 * residual byte in the buffer returned by
5228 * request_firmware() are zeroed out ...
5230 size_t resid
= cf
->size
& 0x3;
5231 size_t size
= cf
->size
& ~0x3;
5232 __be32
*data
= (__be32
*)cf
->data
;
5234 mtype
= FW_PARAMS_PARAM_Y_GET(val
[0]);
5235 maddr
= FW_PARAMS_PARAM_Z_GET(val
[0]) << 16;
5237 spin_lock(&adapter
->win0_lock
);
5238 ret
= t4_memory_rw(adapter
, 0, mtype
, maddr
,
5239 size
, data
, T4_MEMORY_WRITE
);
5240 if (ret
== 0 && resid
!= 0) {
5247 last
.word
= data
[size
>> 2];
5248 for (i
= resid
; i
< 4; i
++)
5250 ret
= t4_memory_rw(adapter
, 0, mtype
,
5255 spin_unlock(&adapter
->win0_lock
);
5259 release_firmware(cf
);
5265 * Issue a Capability Configuration command to the firmware to get it
5266 * to parse the Configuration File. We don't use t4_fw_config_file()
5267 * because we want the ability to modify various features after we've
5268 * processed the configuration file ...
5270 memset(&caps_cmd
, 0, sizeof(caps_cmd
));
5271 caps_cmd
.op_to_write
=
5272 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5275 caps_cmd
.cfvalid_to_len16
=
5276 htonl(FW_CAPS_CONFIG_CMD_CFVALID
|
5277 FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype
) |
5278 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr
>> 16) |
5279 FW_LEN16(caps_cmd
));
5280 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5283 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
5284 * Configuration File in FLASH), our last gasp effort is to use the
5285 * Firmware Configuration File which is embedded in the firmware. A
5286 * very few early versions of the firmware didn't have one embedded
5287 * but we can ignore those.
5289 if (ret
== -ENOENT
) {
5290 memset(&caps_cmd
, 0, sizeof(caps_cmd
));
5291 caps_cmd
.op_to_write
=
5292 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5295 caps_cmd
.cfvalid_to_len16
= htonl(FW_LEN16(caps_cmd
));
5296 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
,
5297 sizeof(caps_cmd
), &caps_cmd
);
5298 config_name
= "Firmware Default";
5305 finiver
= ntohl(caps_cmd
.finiver
);
5306 finicsum
= ntohl(caps_cmd
.finicsum
);
5307 cfcsum
= ntohl(caps_cmd
.cfcsum
);
5308 if (finicsum
!= cfcsum
)
5309 dev_warn(adapter
->pdev_dev
, "Configuration File checksum "\
5310 "mismatch: [fini] csum=%#x, computed csum=%#x\n",
5314 * And now tell the firmware to use the configuration we just loaded.
5316 caps_cmd
.op_to_write
=
5317 htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5320 caps_cmd
.cfvalid_to_len16
= htonl(FW_LEN16(caps_cmd
));
5321 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5327 * Tweak configuration based on system architecture, module
5330 ret
= adap_init0_tweaks(adapter
);
5335 * And finally tell the firmware to initialize itself using the
5336 * parameters from the Configuration File.
5338 ret
= t4_fw_initialize(adapter
, adapter
->mbox
);
5343 * Return successfully and note that we're operating with parameters
5344 * not supplied by the driver, rather than from hard-wired
5345 * initialization constants burried in the driver.
5347 adapter
->flags
|= USING_SOFT_PARAMS
;
5348 dev_info(adapter
->pdev_dev
, "Successfully configured using Firmware "\
5349 "Configuration File \"%s\", version %#x, computed checksum %#x\n",
5350 config_name
, finiver
, cfcsum
);
5354 * Something bad happened. Return the error ... (If the "error"
5355 * is that there's no Configuration File on the adapter we don't
5356 * want to issue a warning since this is fairly common.)
5359 if (config_issued
&& ret
!= -ENOENT
)
5360 dev_warn(adapter
->pdev_dev
, "\"%s\" configuration file error %d\n",
5366 * Attempt to initialize the adapter via hard-coded, driver supplied
5369 static int adap_init0_no_config(struct adapter
*adapter
, int reset
)
5371 struct sge
*s
= &adapter
->sge
;
5372 struct fw_caps_config_cmd caps_cmd
;
5377 * Reset device if necessary
5380 ret
= t4_fw_reset(adapter
, adapter
->mbox
,
5381 PIORSTMODE
| PIORST
);
5387 * Get device capabilities and select which we'll be using.
5389 memset(&caps_cmd
, 0, sizeof(caps_cmd
));
5390 caps_cmd
.op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5391 FW_CMD_REQUEST
| FW_CMD_READ
);
5392 caps_cmd
.cfvalid_to_len16
= htonl(FW_LEN16(caps_cmd
));
5393 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5398 if (caps_cmd
.niccaps
& htons(FW_CAPS_CONFIG_NIC_VM
)) {
5400 caps_cmd
.niccaps
^= htons(FW_CAPS_CONFIG_NIC_VM
);
5402 caps_cmd
.niccaps
= htons(FW_CAPS_CONFIG_NIC_VM
);
5403 } else if (vf_acls
) {
5404 dev_err(adapter
->pdev_dev
, "virtualization ACLs not supported");
5407 caps_cmd
.op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5408 FW_CMD_REQUEST
| FW_CMD_WRITE
);
5409 ret
= t4_wr_mbox(adapter
, adapter
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5415 * Tweak configuration based on system architecture, module
5418 ret
= adap_init0_tweaks(adapter
);
5423 * Select RSS Global Mode we want to use. We use "Basic Virtual"
5424 * mode which maps each Virtual Interface to its own section of
5425 * the RSS Table and we turn on all map and hash enables ...
5427 adapter
->flags
|= RSS_TNLALLLOOKUP
;
5428 ret
= t4_config_glbl_rss(adapter
, adapter
->mbox
,
5429 FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
,
5430 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN
|
5431 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ
|
5432 ((adapter
->flags
& RSS_TNLALLLOOKUP
) ?
5433 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP
: 0));
5438 * Set up our own fundamental resource provisioning ...
5440 ret
= t4_cfg_pfvf(adapter
, adapter
->mbox
, adapter
->fn
, 0,
5441 PFRES_NEQ
, PFRES_NETHCTRL
,
5442 PFRES_NIQFLINT
, PFRES_NIQ
,
5443 PFRES_TC
, PFRES_NVI
,
5444 FW_PFVF_CMD_CMASK_MASK
,
5445 pfvfres_pmask(adapter
, adapter
->fn
, 0),
5447 PFRES_R_CAPS
, PFRES_WX_CAPS
);
5452 * Perform low level SGE initialization. We need to do this before we
5453 * send the firmware the INITIALIZE command because that will cause
5454 * any other PF Drivers which are waiting for the Master
5455 * Initialization to proceed forward.
5457 for (i
= 0; i
< SGE_NTIMERS
- 1; i
++)
5458 s
->timer_val
[i
] = min(intr_holdoff
[i
], MAX_SGE_TIMERVAL
);
5459 s
->timer_val
[SGE_NTIMERS
- 1] = MAX_SGE_TIMERVAL
;
5460 s
->counter_val
[0] = 1;
5461 for (i
= 1; i
< SGE_NCOUNTERS
; i
++)
5462 s
->counter_val
[i
] = min(intr_cnt
[i
- 1],
5463 THRESHOLD_0_GET(THRESHOLD_0_MASK
));
5464 t4_sge_init(adapter
);
5466 #ifdef CONFIG_PCI_IOV
5468 * Provision resource limits for Virtual Functions. We currently
5469 * grant them all the same static resource limits except for the Port
5470 * Access Rights Mask which we're assigning based on the PF. All of
5471 * the static provisioning stuff for both the PF and VF really needs
5472 * to be managed in a persistent manner for each device which the
5473 * firmware controls.
5478 for (pf
= 0; pf
< ARRAY_SIZE(num_vf
); pf
++) {
5479 if (num_vf
[pf
] <= 0)
5482 /* VF numbering starts at 1! */
5483 for (vf
= 1; vf
<= num_vf
[pf
]; vf
++) {
5484 ret
= t4_cfg_pfvf(adapter
, adapter
->mbox
,
5486 VFRES_NEQ
, VFRES_NETHCTRL
,
5487 VFRES_NIQFLINT
, VFRES_NIQ
,
5488 VFRES_TC
, VFRES_NVI
,
5489 FW_PFVF_CMD_CMASK_MASK
,
5493 VFRES_R_CAPS
, VFRES_WX_CAPS
);
5495 dev_warn(adapter
->pdev_dev
,
5497 "provision pf/vf=%d/%d; "
5498 "err=%d\n", pf
, vf
, ret
);
5505 * Set up the default filter mode. Later we'll want to implement this
5506 * via a firmware command, etc. ... This needs to be done before the
5507 * firmare initialization command ... If the selected set of fields
5508 * isn't equal to the default value, we'll need to make sure that the
5509 * field selections will fit in the 36-bit budget.
5511 if (tp_vlan_pri_map
!= TP_VLAN_PRI_MAP_DEFAULT
) {
5514 for (j
= TP_VLAN_PRI_MAP_FIRST
; j
<= TP_VLAN_PRI_MAP_LAST
; j
++)
5515 switch (tp_vlan_pri_map
& (1 << j
)) {
5517 /* compressed filter field not enabled */
5537 case ETHERTYPE_MASK
:
5543 case MPSHITTYPE_MASK
:
5546 case FRAGMENTATION_MASK
:
5552 dev_err(adapter
->pdev_dev
,
5553 "tp_vlan_pri_map=%#x needs %d bits > 36;"\
5554 " using %#x\n", tp_vlan_pri_map
, bits
,
5555 TP_VLAN_PRI_MAP_DEFAULT
);
5556 tp_vlan_pri_map
= TP_VLAN_PRI_MAP_DEFAULT
;
5559 v
= tp_vlan_pri_map
;
5560 t4_write_indirect(adapter
, TP_PIO_ADDR
, TP_PIO_DATA
,
5561 &v
, 1, TP_VLAN_PRI_MAP
);
5564 * We need Five Tuple Lookup mode to be set in TP_GLOBAL_CONFIG order
5565 * to support any of the compressed filter fields above. Newer
5566 * versions of the firmware do this automatically but it doesn't hurt
5567 * to set it here. Meanwhile, we do _not_ need to set Lookup Every
5568 * Packet in TP_INGRESS_CONFIG to support matching non-TCP packets
5569 * since the firmware automatically turns this on and off when we have
5570 * a non-zero number of filters active (since it does have a
5571 * performance impact).
5573 if (tp_vlan_pri_map
)
5574 t4_set_reg_field(adapter
, TP_GLOBAL_CONFIG
,
5575 FIVETUPLELOOKUP_MASK
,
5576 FIVETUPLELOOKUP_MASK
);
5579 * Tweak some settings.
5581 t4_write_reg(adapter
, TP_SHIFT_CNT
, SYNSHIFTMAX(6) |
5582 RXTSHIFTMAXR1(4) | RXTSHIFTMAXR2(15) |
5583 PERSHIFTBACKOFFMAX(8) | PERSHIFTMAX(8) |
5584 KEEPALIVEMAXR1(4) | KEEPALIVEMAXR2(9));
5587 * Get basic stuff going by issuing the Firmware Initialize command.
5588 * Note that this _must_ be after all PFVF commands ...
5590 ret
= t4_fw_initialize(adapter
, adapter
->mbox
);
5595 * Return successfully!
5597 dev_info(adapter
->pdev_dev
, "Successfully configured using built-in "\
5598 "driver parameters\n");
5602 * Something bad happened. Return the error ...
5608 static struct fw_info fw_info_array
[] = {
5611 .fs_name
= FW4_CFNAME
,
5612 .fw_mod_name
= FW4_FNAME
,
5614 .chip
= FW_HDR_CHIP_T4
,
5615 .fw_ver
= __cpu_to_be32(FW_VERSION(T4
)),
5616 .intfver_nic
= FW_INTFVER(T4
, NIC
),
5617 .intfver_vnic
= FW_INTFVER(T4
, VNIC
),
5618 .intfver_ri
= FW_INTFVER(T4
, RI
),
5619 .intfver_iscsi
= FW_INTFVER(T4
, ISCSI
),
5620 .intfver_fcoe
= FW_INTFVER(T4
, FCOE
),
5624 .fs_name
= FW5_CFNAME
,
5625 .fw_mod_name
= FW5_FNAME
,
5627 .chip
= FW_HDR_CHIP_T5
,
5628 .fw_ver
= __cpu_to_be32(FW_VERSION(T5
)),
5629 .intfver_nic
= FW_INTFVER(T5
, NIC
),
5630 .intfver_vnic
= FW_INTFVER(T5
, VNIC
),
5631 .intfver_ri
= FW_INTFVER(T5
, RI
),
5632 .intfver_iscsi
= FW_INTFVER(T5
, ISCSI
),
5633 .intfver_fcoe
= FW_INTFVER(T5
, FCOE
),
5638 static struct fw_info
*find_fw_info(int chip
)
5642 for (i
= 0; i
< ARRAY_SIZE(fw_info_array
); i
++) {
5643 if (fw_info_array
[i
].chip
== chip
)
5644 return &fw_info_array
[i
];
5650 * Phase 0 of initialization: contact FW, obtain config, perform basic init.
5652 static int adap_init0(struct adapter
*adap
)
5656 enum dev_state state
;
5657 u32 params
[7], val
[7];
5658 struct fw_caps_config_cmd caps_cmd
;
5662 * Contact FW, advertising Master capability (and potentially forcing
5663 * ourselves as the Master PF if our module parameter force_init is
5666 ret
= t4_fw_hello(adap
, adap
->mbox
, adap
->fn
,
5667 force_init
? MASTER_MUST
: MASTER_MAY
,
5670 dev_err(adap
->pdev_dev
, "could not connect to FW, error %d\n",
5674 if (ret
== adap
->mbox
)
5675 adap
->flags
|= MASTER_PF
;
5676 if (force_init
&& state
== DEV_STATE_INIT
)
5677 state
= DEV_STATE_UNINIT
;
5680 * If we're the Master PF Driver and the device is uninitialized,
5681 * then let's consider upgrading the firmware ... (We always want
5682 * to check the firmware version number in order to A. get it for
5683 * later reporting and B. to warn if the currently loaded firmware
5684 * is excessively mismatched relative to the driver.)
5686 t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
5687 t4_get_tp_version(adap
, &adap
->params
.tp_vers
);
5688 if ((adap
->flags
& MASTER_PF
) && state
!= DEV_STATE_INIT
) {
5689 struct fw_info
*fw_info
;
5690 struct fw_hdr
*card_fw
;
5691 const struct firmware
*fw
;
5692 const u8
*fw_data
= NULL
;
5693 unsigned int fw_size
= 0;
5695 /* This is the firmware whose headers the driver was compiled
5698 fw_info
= find_fw_info(CHELSIO_CHIP_VERSION(adap
->params
.chip
));
5699 if (fw_info
== NULL
) {
5700 dev_err(adap
->pdev_dev
,
5701 "unable to get firmware info for chip %d.\n",
5702 CHELSIO_CHIP_VERSION(adap
->params
.chip
));
5706 /* allocate memory to read the header of the firmware on the
5709 card_fw
= t4_alloc_mem(sizeof(*card_fw
));
5711 /* Get FW from from /lib/firmware/ */
5712 ret
= request_firmware(&fw
, fw_info
->fw_mod_name
,
5715 dev_err(adap
->pdev_dev
,
5716 "unable to load firmware image %s, error %d\n",
5717 fw_info
->fw_mod_name
, ret
);
5723 /* upgrade FW logic */
5724 ret
= t4_prep_fw(adap
, fw_info
, fw_data
, fw_size
, card_fw
,
5729 release_firmware(fw
);
5730 t4_free_mem(card_fw
);
5737 * Grab VPD parameters. This should be done after we establish a
5738 * connection to the firmware since some of the VPD parameters
5739 * (notably the Core Clock frequency) are retrieved via requests to
5740 * the firmware. On the other hand, we need these fairly early on
5741 * so we do this right after getting ahold of the firmware.
5743 ret
= get_vpd_params(adap
, &adap
->params
.vpd
);
5748 * Find out what ports are available to us. Note that we need to do
5749 * this before calling adap_init0_no_config() since it needs nports
5753 FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV
) |
5754 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC
);
5755 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 1, &v
, &port_vec
);
5759 adap
->params
.nports
= hweight32(port_vec
);
5760 adap
->params
.portvec
= port_vec
;
5763 * If the firmware is initialized already (and we're not forcing a
5764 * master initialization), note that we're living with existing
5765 * adapter parameters. Otherwise, it's time to try initializing the
5768 if (state
== DEV_STATE_INIT
) {
5769 dev_info(adap
->pdev_dev
, "Coming up as %s: "\
5770 "Adapter already initialized\n",
5771 adap
->flags
& MASTER_PF
? "MASTER" : "SLAVE");
5772 adap
->flags
|= USING_SOFT_PARAMS
;
5774 dev_info(adap
->pdev_dev
, "Coming up as MASTER: "\
5775 "Initializing adapter\n");
5778 * If the firmware doesn't support Configuration
5779 * Files warn user and exit,
5782 dev_warn(adap
->pdev_dev
, "Firmware doesn't support "
5783 "configuration file.\n");
5785 ret
= adap_init0_no_config(adap
, reset
);
5788 * Find out whether we're dealing with a version of
5789 * the firmware which has configuration file support.
5791 params
[0] = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV
) |
5792 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CF
));
5793 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 1,
5797 * If the firmware doesn't support Configuration
5798 * Files, use the old Driver-based, hard-wired
5799 * initialization. Otherwise, try using the
5800 * Configuration File support and fall back to the
5801 * Driver-based initialization if there's no
5802 * Configuration File found.
5805 ret
= adap_init0_no_config(adap
, reset
);
5808 * The firmware provides us with a memory
5809 * buffer where we can load a Configuration
5810 * File from the host if we want to override
5811 * the Configuration File in flash.
5814 ret
= adap_init0_config(adap
, reset
);
5815 if (ret
== -ENOENT
) {
5816 dev_info(adap
->pdev_dev
,
5817 "No Configuration File present "
5818 "on adapter. Using hard-wired "
5819 "configuration parameters.\n");
5820 ret
= adap_init0_no_config(adap
, reset
);
5825 dev_err(adap
->pdev_dev
,
5826 "could not initialize adapter, error %d\n",
5833 * If we're living with non-hard-coded parameters (either from a
5834 * Firmware Configuration File or values programmed by a different PF
5835 * Driver), give the SGE code a chance to pull in anything that it
5836 * needs ... Note that this must be called after we retrieve our VPD
5837 * parameters in order to know how to convert core ticks to seconds.
5839 if (adap
->flags
& USING_SOFT_PARAMS
) {
5840 ret
= t4_sge_init(adap
);
5845 if (is_bypass_device(adap
->pdev
->device
))
5846 adap
->params
.bypass
= 1;
5849 * Grab some of our basic fundamental operating parameters.
5851 #define FW_PARAM_DEV(param) \
5852 (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
5853 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
5855 #define FW_PARAM_PFVF(param) \
5856 FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
5857 FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param)| \
5858 FW_PARAMS_PARAM_Y(0) | \
5859 FW_PARAMS_PARAM_Z(0)
5861 params
[0] = FW_PARAM_PFVF(EQ_START
);
5862 params
[1] = FW_PARAM_PFVF(L2T_START
);
5863 params
[2] = FW_PARAM_PFVF(L2T_END
);
5864 params
[3] = FW_PARAM_PFVF(FILTER_START
);
5865 params
[4] = FW_PARAM_PFVF(FILTER_END
);
5866 params
[5] = FW_PARAM_PFVF(IQFLINT_START
);
5867 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 6, params
, val
);
5870 adap
->sge
.egr_start
= val
[0];
5871 adap
->l2t_start
= val
[1];
5872 adap
->l2t_end
= val
[2];
5873 adap
->tids
.ftid_base
= val
[3];
5874 adap
->tids
.nftids
= val
[4] - val
[3] + 1;
5875 adap
->sge
.ingr_start
= val
[5];
5877 /* query params related to active filter region */
5878 params
[0] = FW_PARAM_PFVF(ACTIVE_FILTER_START
);
5879 params
[1] = FW_PARAM_PFVF(ACTIVE_FILTER_END
);
5880 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 2, params
, val
);
5881 /* If Active filter size is set we enable establishing
5882 * offload connection through firmware work request
5884 if ((val
[0] != val
[1]) && (ret
>= 0)) {
5885 adap
->flags
|= FW_OFLD_CONN
;
5886 adap
->tids
.aftid_base
= val
[0];
5887 adap
->tids
.aftid_end
= val
[1];
5890 /* If we're running on newer firmware, let it know that we're
5891 * prepared to deal with encapsulated CPL messages. Older
5892 * firmware won't understand this and we'll just get
5893 * unencapsulated messages ...
5895 params
[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP
);
5897 (void) t4_set_params(adap
, adap
->mbox
, adap
->fn
, 0, 1, params
, val
);
5900 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL
5901 * capability. Earlier versions of the firmware didn't have the
5902 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no
5903 * permission to use ULPTX MEMWRITE DSGL.
5905 if (is_t4(adap
->params
.chip
)) {
5906 adap
->params
.ulptx_memwrite_dsgl
= false;
5908 params
[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL
);
5909 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0,
5911 adap
->params
.ulptx_memwrite_dsgl
= (ret
== 0 && val
[0] != 0);
5915 * Get device capabilities so we can determine what resources we need
5918 memset(&caps_cmd
, 0, sizeof(caps_cmd
));
5919 caps_cmd
.op_to_write
= htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD
) |
5920 FW_CMD_REQUEST
| FW_CMD_READ
);
5921 caps_cmd
.cfvalid_to_len16
= htonl(FW_LEN16(caps_cmd
));
5922 ret
= t4_wr_mbox(adap
, adap
->mbox
, &caps_cmd
, sizeof(caps_cmd
),
5927 if (caps_cmd
.ofldcaps
) {
5928 /* query offload-related parameters */
5929 params
[0] = FW_PARAM_DEV(NTID
);
5930 params
[1] = FW_PARAM_PFVF(SERVER_START
);
5931 params
[2] = FW_PARAM_PFVF(SERVER_END
);
5932 params
[3] = FW_PARAM_PFVF(TDDP_START
);
5933 params
[4] = FW_PARAM_PFVF(TDDP_END
);
5934 params
[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ
);
5935 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 6,
5939 adap
->tids
.ntids
= val
[0];
5940 adap
->tids
.natids
= min(adap
->tids
.ntids
/ 2, MAX_ATIDS
);
5941 adap
->tids
.stid_base
= val
[1];
5942 adap
->tids
.nstids
= val
[2] - val
[1] + 1;
5944 * Setup server filter region. Divide the availble filter
5945 * region into two parts. Regular filters get 1/3rd and server
5946 * filters get 2/3rd part. This is only enabled if workarond
5948 * 1. For regular filters.
5949 * 2. Server filter: This are special filters which are used
5950 * to redirect SYN packets to offload queue.
5952 if (adap
->flags
& FW_OFLD_CONN
&& !is_bypass(adap
)) {
5953 adap
->tids
.sftid_base
= adap
->tids
.ftid_base
+
5954 DIV_ROUND_UP(adap
->tids
.nftids
, 3);
5955 adap
->tids
.nsftids
= adap
->tids
.nftids
-
5956 DIV_ROUND_UP(adap
->tids
.nftids
, 3);
5957 adap
->tids
.nftids
= adap
->tids
.sftid_base
-
5958 adap
->tids
.ftid_base
;
5960 adap
->vres
.ddp
.start
= val
[3];
5961 adap
->vres
.ddp
.size
= val
[4] - val
[3] + 1;
5962 adap
->params
.ofldq_wr_cred
= val
[5];
5964 adap
->params
.offload
= 1;
5966 if (caps_cmd
.rdmacaps
) {
5967 params
[0] = FW_PARAM_PFVF(STAG_START
);
5968 params
[1] = FW_PARAM_PFVF(STAG_END
);
5969 params
[2] = FW_PARAM_PFVF(RQ_START
);
5970 params
[3] = FW_PARAM_PFVF(RQ_END
);
5971 params
[4] = FW_PARAM_PFVF(PBL_START
);
5972 params
[5] = FW_PARAM_PFVF(PBL_END
);
5973 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 6,
5977 adap
->vres
.stag
.start
= val
[0];
5978 adap
->vres
.stag
.size
= val
[1] - val
[0] + 1;
5979 adap
->vres
.rq
.start
= val
[2];
5980 adap
->vres
.rq
.size
= val
[3] - val
[2] + 1;
5981 adap
->vres
.pbl
.start
= val
[4];
5982 adap
->vres
.pbl
.size
= val
[5] - val
[4] + 1;
5984 params
[0] = FW_PARAM_PFVF(SQRQ_START
);
5985 params
[1] = FW_PARAM_PFVF(SQRQ_END
);
5986 params
[2] = FW_PARAM_PFVF(CQ_START
);
5987 params
[3] = FW_PARAM_PFVF(CQ_END
);
5988 params
[4] = FW_PARAM_PFVF(OCQ_START
);
5989 params
[5] = FW_PARAM_PFVF(OCQ_END
);
5990 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 6, params
,
5994 adap
->vres
.qp
.start
= val
[0];
5995 adap
->vres
.qp
.size
= val
[1] - val
[0] + 1;
5996 adap
->vres
.cq
.start
= val
[2];
5997 adap
->vres
.cq
.size
= val
[3] - val
[2] + 1;
5998 adap
->vres
.ocq
.start
= val
[4];
5999 adap
->vres
.ocq
.size
= val
[5] - val
[4] + 1;
6001 params
[0] = FW_PARAM_DEV(MAXORDIRD_QP
);
6002 params
[1] = FW_PARAM_DEV(MAXIRD_ADAPTER
);
6003 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 2, params
,
6006 adap
->params
.max_ordird_qp
= 8;
6007 adap
->params
.max_ird_adapter
= 32 * adap
->tids
.ntids
;
6010 adap
->params
.max_ordird_qp
= val
[0];
6011 adap
->params
.max_ird_adapter
= val
[1];
6013 dev_info(adap
->pdev_dev
,
6014 "max_ordird_qp %d max_ird_adapter %d\n",
6015 adap
->params
.max_ordird_qp
,
6016 adap
->params
.max_ird_adapter
);
6018 if (caps_cmd
.iscsicaps
) {
6019 params
[0] = FW_PARAM_PFVF(ISCSI_START
);
6020 params
[1] = FW_PARAM_PFVF(ISCSI_END
);
6021 ret
= t4_query_params(adap
, adap
->mbox
, adap
->fn
, 0, 2,
6025 adap
->vres
.iscsi
.start
= val
[0];
6026 adap
->vres
.iscsi
.size
= val
[1] - val
[0] + 1;
6028 #undef FW_PARAM_PFVF
6031 /* The MTU/MSS Table is initialized by now, so load their values. If
6032 * we're initializing the adapter, then we'll make any modifications
6033 * we want to the MTU/MSS Table and also initialize the congestion
6036 t4_read_mtu_tbl(adap
, adap
->params
.mtus
, NULL
);
6037 if (state
!= DEV_STATE_INIT
) {
6040 /* The default MTU Table contains values 1492 and 1500.
6041 * However, for TCP, it's better to have two values which are
6042 * a multiple of 8 +/- 4 bytes apart near this popular MTU.
6043 * This allows us to have a TCP Data Payload which is a
6044 * multiple of 8 regardless of what combination of TCP Options
6045 * are in use (always a multiple of 4 bytes) which is
6046 * important for performance reasons. For instance, if no
6047 * options are in use, then we have a 20-byte IP header and a
6048 * 20-byte TCP header. In this case, a 1500-byte MSS would
6049 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes
6050 * which is not a multiple of 8. So using an MSS of 1488 in
6051 * this case results in a TCP Data Payload of 1448 bytes which
6052 * is a multiple of 8. On the other hand, if 12-byte TCP Time
6053 * Stamps have been negotiated, then an MTU of 1500 bytes
6054 * results in a TCP Data Payload of 1448 bytes which, as
6055 * above, is a multiple of 8 bytes ...
6057 for (i
= 0; i
< NMTUS
; i
++)
6058 if (adap
->params
.mtus
[i
] == 1492) {
6059 adap
->params
.mtus
[i
] = 1488;
6063 t4_load_mtus(adap
, adap
->params
.mtus
, adap
->params
.a_wnd
,
6064 adap
->params
.b_wnd
);
6066 t4_init_tp_params(adap
);
6067 adap
->flags
|= FW_OK
;
6071 * Something bad happened. If a command timed out or failed with EIO
6072 * FW does not operate within its spec or something catastrophic
6073 * happened to HW/FW, stop issuing commands.
6076 if (ret
!= -ETIMEDOUT
&& ret
!= -EIO
)
6077 t4_fw_bye(adap
, adap
->mbox
);
6083 static pci_ers_result_t
eeh_err_detected(struct pci_dev
*pdev
,
6084 pci_channel_state_t state
)
6087 struct adapter
*adap
= pci_get_drvdata(pdev
);
6093 adap
->flags
&= ~FW_OK
;
6094 notify_ulds(adap
, CXGB4_STATE_START_RECOVERY
);
6095 spin_lock(&adap
->stats_lock
);
6096 for_each_port(adap
, i
) {
6097 struct net_device
*dev
= adap
->port
[i
];
6099 netif_device_detach(dev
);
6100 netif_carrier_off(dev
);
6102 spin_unlock(&adap
->stats_lock
);
6103 if (adap
->flags
& FULL_INIT_DONE
)
6106 if ((adap
->flags
& DEV_ENABLED
)) {
6107 pci_disable_device(pdev
);
6108 adap
->flags
&= ~DEV_ENABLED
;
6110 out
: return state
== pci_channel_io_perm_failure
?
6111 PCI_ERS_RESULT_DISCONNECT
: PCI_ERS_RESULT_NEED_RESET
;
6114 static pci_ers_result_t
eeh_slot_reset(struct pci_dev
*pdev
)
6117 struct fw_caps_config_cmd c
;
6118 struct adapter
*adap
= pci_get_drvdata(pdev
);
6121 pci_restore_state(pdev
);
6122 pci_save_state(pdev
);
6123 return PCI_ERS_RESULT_RECOVERED
;
6126 if (!(adap
->flags
& DEV_ENABLED
)) {
6127 if (pci_enable_device(pdev
)) {
6128 dev_err(&pdev
->dev
, "Cannot reenable PCI "
6129 "device after reset\n");
6130 return PCI_ERS_RESULT_DISCONNECT
;
6132 adap
->flags
|= DEV_ENABLED
;
6135 pci_set_master(pdev
);
6136 pci_restore_state(pdev
);
6137 pci_save_state(pdev
);
6138 pci_cleanup_aer_uncorrect_error_status(pdev
);
6140 if (t4_wait_dev_ready(adap
->regs
) < 0)
6141 return PCI_ERS_RESULT_DISCONNECT
;
6142 if (t4_fw_hello(adap
, adap
->fn
, adap
->fn
, MASTER_MUST
, NULL
) < 0)
6143 return PCI_ERS_RESULT_DISCONNECT
;
6144 adap
->flags
|= FW_OK
;
6145 if (adap_init1(adap
, &c
))
6146 return PCI_ERS_RESULT_DISCONNECT
;
6148 for_each_port(adap
, i
) {
6149 struct port_info
*p
= adap2pinfo(adap
, i
);
6151 ret
= t4_alloc_vi(adap
, adap
->fn
, p
->tx_chan
, adap
->fn
, 0, 1,
6154 return PCI_ERS_RESULT_DISCONNECT
;
6156 p
->xact_addr_filt
= -1;
6159 t4_load_mtus(adap
, adap
->params
.mtus
, adap
->params
.a_wnd
,
6160 adap
->params
.b_wnd
);
6163 return PCI_ERS_RESULT_DISCONNECT
;
6164 return PCI_ERS_RESULT_RECOVERED
;
6167 static void eeh_resume(struct pci_dev
*pdev
)
6170 struct adapter
*adap
= pci_get_drvdata(pdev
);
6176 for_each_port(adap
, i
) {
6177 struct net_device
*dev
= adap
->port
[i
];
6179 if (netif_running(dev
)) {
6181 cxgb_set_rxmode(dev
);
6183 netif_device_attach(dev
);
6188 static const struct pci_error_handlers cxgb4_eeh
= {
6189 .error_detected
= eeh_err_detected
,
6190 .slot_reset
= eeh_slot_reset
,
6191 .resume
= eeh_resume
,
6194 static inline bool is_x_10g_port(const struct link_config
*lc
)
6196 return (lc
->supported
& FW_PORT_CAP_SPEED_10G
) != 0 ||
6197 (lc
->supported
& FW_PORT_CAP_SPEED_40G
) != 0;
6200 static inline void init_rspq(struct adapter
*adap
, struct sge_rspq
*q
,
6201 unsigned int us
, unsigned int cnt
,
6202 unsigned int size
, unsigned int iqe_size
)
6205 set_rspq_intr_params(q
, us
, cnt
);
6206 q
->iqe_len
= iqe_size
;
6211 * Perform default configuration of DMA queues depending on the number and type
6212 * of ports we found and the number of available CPUs. Most settings can be
6213 * modified by the admin prior to actual use.
6215 static void cfg_queues(struct adapter
*adap
)
6217 struct sge
*s
= &adap
->sge
;
6218 int i
, n10g
= 0, qidx
= 0;
6219 #ifndef CONFIG_CHELSIO_T4_DCB
6224 for_each_port(adap
, i
)
6225 n10g
+= is_x_10g_port(&adap2pinfo(adap
, i
)->link_cfg
);
6226 #ifdef CONFIG_CHELSIO_T4_DCB
6227 /* For Data Center Bridging support we need to be able to support up
6228 * to 8 Traffic Priorities; each of which will be assigned to its
6229 * own TX Queue in order to prevent Head-Of-Line Blocking.
6231 if (adap
->params
.nports
* 8 > MAX_ETH_QSETS
) {
6232 dev_err(adap
->pdev_dev
, "MAX_ETH_QSETS=%d < %d!\n",
6233 MAX_ETH_QSETS
, adap
->params
.nports
* 8);
6237 for_each_port(adap
, i
) {
6238 struct port_info
*pi
= adap2pinfo(adap
, i
);
6240 pi
->first_qset
= qidx
;
6244 #else /* !CONFIG_CHELSIO_T4_DCB */
6246 * We default to 1 queue per non-10G port and up to # of cores queues
6250 q10g
= (MAX_ETH_QSETS
- (adap
->params
.nports
- n10g
)) / n10g
;
6251 if (q10g
> netif_get_num_default_rss_queues())
6252 q10g
= netif_get_num_default_rss_queues();
6254 for_each_port(adap
, i
) {
6255 struct port_info
*pi
= adap2pinfo(adap
, i
);
6257 pi
->first_qset
= qidx
;
6258 pi
->nqsets
= is_x_10g_port(&pi
->link_cfg
) ? q10g
: 1;
6261 #endif /* !CONFIG_CHELSIO_T4_DCB */
6264 s
->max_ethqsets
= qidx
; /* MSI-X may lower it later */
6266 if (is_offload(adap
)) {
6268 * For offload we use 1 queue/channel if all ports are up to 1G,
6269 * otherwise we divide all available queues amongst the channels
6270 * capped by the number of available cores.
6273 i
= min_t(int, ARRAY_SIZE(s
->ofldrxq
),
6275 s
->ofldqsets
= roundup(i
, adap
->params
.nports
);
6277 s
->ofldqsets
= adap
->params
.nports
;
6278 /* For RDMA one Rx queue per channel suffices */
6279 s
->rdmaqs
= adap
->params
.nports
;
6280 s
->rdmaciqs
= adap
->params
.nports
;
6283 for (i
= 0; i
< ARRAY_SIZE(s
->ethrxq
); i
++) {
6284 struct sge_eth_rxq
*r
= &s
->ethrxq
[i
];
6286 init_rspq(adap
, &r
->rspq
, 5, 10, 1024, 64);
6290 for (i
= 0; i
< ARRAY_SIZE(s
->ethtxq
); i
++)
6291 s
->ethtxq
[i
].q
.size
= 1024;
6293 for (i
= 0; i
< ARRAY_SIZE(s
->ctrlq
); i
++)
6294 s
->ctrlq
[i
].q
.size
= 512;
6296 for (i
= 0; i
< ARRAY_SIZE(s
->ofldtxq
); i
++)
6297 s
->ofldtxq
[i
].q
.size
= 1024;
6299 for (i
= 0; i
< ARRAY_SIZE(s
->ofldrxq
); i
++) {
6300 struct sge_ofld_rxq
*r
= &s
->ofldrxq
[i
];
6302 init_rspq(adap
, &r
->rspq
, 5, 1, 1024, 64);
6303 r
->rspq
.uld
= CXGB4_ULD_ISCSI
;
6307 for (i
= 0; i
< ARRAY_SIZE(s
->rdmarxq
); i
++) {
6308 struct sge_ofld_rxq
*r
= &s
->rdmarxq
[i
];
6310 init_rspq(adap
, &r
->rspq
, 5, 1, 511, 64);
6311 r
->rspq
.uld
= CXGB4_ULD_RDMA
;
6315 ciq_size
= 64 + adap
->vres
.cq
.size
+ adap
->tids
.nftids
;
6316 if (ciq_size
> SGE_MAX_IQ_SIZE
) {
6317 CH_WARN(adap
, "CIQ size too small for available IQs\n");
6318 ciq_size
= SGE_MAX_IQ_SIZE
;
6321 for (i
= 0; i
< ARRAY_SIZE(s
->rdmaciq
); i
++) {
6322 struct sge_ofld_rxq
*r
= &s
->rdmaciq
[i
];
6324 init_rspq(adap
, &r
->rspq
, 5, 1, ciq_size
, 64);
6325 r
->rspq
.uld
= CXGB4_ULD_RDMA
;
6328 init_rspq(adap
, &s
->fw_evtq
, 0, 1, 1024, 64);
6329 init_rspq(adap
, &s
->intrq
, 0, 1, 2 * MAX_INGQ
, 64);
6333 * Reduce the number of Ethernet queues across all ports to at most n.
6334 * n provides at least one queue per port.
6336 static void reduce_ethqs(struct adapter
*adap
, int n
)
6339 struct port_info
*pi
;
6341 while (n
< adap
->sge
.ethqsets
)
6342 for_each_port(adap
, i
) {
6343 pi
= adap2pinfo(adap
, i
);
6344 if (pi
->nqsets
> 1) {
6346 adap
->sge
.ethqsets
--;
6347 if (adap
->sge
.ethqsets
<= n
)
6353 for_each_port(adap
, i
) {
6354 pi
= adap2pinfo(adap
, i
);
6360 /* 2 MSI-X vectors needed for the FW queue and non-data interrupts */
6361 #define EXTRA_VECS 2
6363 static int enable_msix(struct adapter
*adap
)
6367 struct sge
*s
= &adap
->sge
;
6368 unsigned int nchan
= adap
->params
.nports
;
6369 struct msix_entry entries
[MAX_INGQ
+ 1];
6371 for (i
= 0; i
< ARRAY_SIZE(entries
); ++i
)
6372 entries
[i
].entry
= i
;
6374 want
= s
->max_ethqsets
+ EXTRA_VECS
;
6375 if (is_offload(adap
)) {
6376 want
+= s
->rdmaqs
+ s
->rdmaciqs
+ s
->ofldqsets
;
6377 /* need nchan for each possible ULD */
6378 ofld_need
= 3 * nchan
;
6380 #ifdef CONFIG_CHELSIO_T4_DCB
6381 /* For Data Center Bridging we need 8 Ethernet TX Priority Queues for
6384 need
= 8 * adap
->params
.nports
+ EXTRA_VECS
+ ofld_need
;
6386 need
= adap
->params
.nports
+ EXTRA_VECS
+ ofld_need
;
6388 want
= pci_enable_msix_range(adap
->pdev
, entries
, need
, want
);
6393 * Distribute available vectors to the various queue groups.
6394 * Every group gets its minimum requirement and NIC gets top
6395 * priority for leftovers.
6397 i
= want
- EXTRA_VECS
- ofld_need
;
6398 if (i
< s
->max_ethqsets
) {
6399 s
->max_ethqsets
= i
;
6400 if (i
< s
->ethqsets
)
6401 reduce_ethqs(adap
, i
);
6403 if (is_offload(adap
)) {
6404 i
= want
- EXTRA_VECS
- s
->max_ethqsets
;
6405 i
-= ofld_need
- nchan
;
6406 s
->ofldqsets
= (i
/ nchan
) * nchan
; /* round down */
6408 for (i
= 0; i
< want
; ++i
)
6409 adap
->msix_info
[i
].vec
= entries
[i
].vector
;
6416 static int init_rss(struct adapter
*adap
)
6420 for_each_port(adap
, i
) {
6421 struct port_info
*pi
= adap2pinfo(adap
, i
);
6423 pi
->rss
= kcalloc(pi
->rss_size
, sizeof(u16
), GFP_KERNEL
);
6426 for (j
= 0; j
< pi
->rss_size
; j
++)
6427 pi
->rss
[j
] = ethtool_rxfh_indir_default(j
, pi
->nqsets
);
6432 static void print_port_info(const struct net_device
*dev
)
6436 const char *spd
= "";
6437 const struct port_info
*pi
= netdev_priv(dev
);
6438 const struct adapter
*adap
= pi
->adapter
;
6440 if (adap
->params
.pci
.speed
== PCI_EXP_LNKSTA_CLS_2_5GB
)
6442 else if (adap
->params
.pci
.speed
== PCI_EXP_LNKSTA_CLS_5_0GB
)
6444 else if (adap
->params
.pci
.speed
== PCI_EXP_LNKSTA_CLS_8_0GB
)
6447 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_100M
)
6448 bufp
+= sprintf(bufp
, "100/");
6449 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_1G
)
6450 bufp
+= sprintf(bufp
, "1000/");
6451 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_10G
)
6452 bufp
+= sprintf(bufp
, "10G/");
6453 if (pi
->link_cfg
.supported
& FW_PORT_CAP_SPEED_40G
)
6454 bufp
+= sprintf(bufp
, "40G/");
6457 sprintf(bufp
, "BASE-%s", t4_get_port_type_description(pi
->port_type
));
6459 netdev_info(dev
, "Chelsio %s rev %d %s %sNIC PCIe x%d%s%s\n",
6460 adap
->params
.vpd
.id
,
6461 CHELSIO_CHIP_RELEASE(adap
->params
.chip
), buf
,
6462 is_offload(adap
) ? "R" : "", adap
->params
.pci
.width
, spd
,
6463 (adap
->flags
& USING_MSIX
) ? " MSI-X" :
6464 (adap
->flags
& USING_MSI
) ? " MSI" : "");
6465 netdev_info(dev
, "S/N: %s, P/N: %s\n",
6466 adap
->params
.vpd
.sn
, adap
->params
.vpd
.pn
);
6469 static void enable_pcie_relaxed_ordering(struct pci_dev
*dev
)
6471 pcie_capability_set_word(dev
, PCI_EXP_DEVCTL
, PCI_EXP_DEVCTL_RELAX_EN
);
6475 * Free the following resources:
6476 * - memory used for tables
6479 * - resources FW is holding for us
6481 static void free_some_resources(struct adapter
*adapter
)
6485 t4_free_mem(adapter
->l2t
);
6486 t4_free_mem(adapter
->tids
.tid_tab
);
6487 disable_msi(adapter
);
6489 for_each_port(adapter
, i
)
6490 if (adapter
->port
[i
]) {
6491 kfree(adap2pinfo(adapter
, i
)->rss
);
6492 free_netdev(adapter
->port
[i
]);
6494 if (adapter
->flags
& FW_OK
)
6495 t4_fw_bye(adapter
, adapter
->fn
);
6498 #define TSO_FLAGS (NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_TSO_ECN)
6499 #define VLAN_FEAT (NETIF_F_SG | NETIF_F_IP_CSUM | TSO_FLAGS | \
6500 NETIF_F_IPV6_CSUM | NETIF_F_HIGHDMA)
6501 #define SEGMENT_SIZE 128
6503 static int init_one(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
6505 int func
, i
, err
, s_qpp
, qpp
, num_seg
;
6506 struct port_info
*pi
;
6507 bool highdma
= false;
6508 struct adapter
*adapter
= NULL
;
6511 printk_once(KERN_INFO
"%s - version %s\n", DRV_DESC
, DRV_VERSION
);
6513 err
= pci_request_regions(pdev
, KBUILD_MODNAME
);
6515 /* Just info, some other driver may have claimed the device. */
6516 dev_info(&pdev
->dev
, "cannot obtain PCI resources\n");
6520 err
= pci_enable_device(pdev
);
6522 dev_err(&pdev
->dev
, "cannot enable PCI device\n");
6523 goto out_release_regions
;
6526 regs
= pci_ioremap_bar(pdev
, 0);
6528 dev_err(&pdev
->dev
, "cannot map device registers\n");
6530 goto out_disable_device
;
6533 err
= t4_wait_dev_ready(regs
);
6535 goto out_unmap_bar0
;
6537 /* We control everything through one PF */
6538 func
= SOURCEPF_GET(readl(regs
+ PL_WHOAMI
));
6539 if (func
!= ent
->driver_data
) {
6541 pci_disable_device(pdev
);
6542 pci_save_state(pdev
); /* to restore SR-IOV later */
6546 if (!pci_set_dma_mask(pdev
, DMA_BIT_MASK(64))) {
6548 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(64));
6550 dev_err(&pdev
->dev
, "unable to obtain 64-bit DMA for "
6551 "coherent allocations\n");
6552 goto out_unmap_bar0
;
6555 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
6557 dev_err(&pdev
->dev
, "no usable DMA configuration\n");
6558 goto out_unmap_bar0
;
6562 pci_enable_pcie_error_reporting(pdev
);
6563 enable_pcie_relaxed_ordering(pdev
);
6564 pci_set_master(pdev
);
6565 pci_save_state(pdev
);
6567 adapter
= kzalloc(sizeof(*adapter
), GFP_KERNEL
);
6570 goto out_unmap_bar0
;
6573 adapter
->workq
= create_singlethread_workqueue("cxgb4");
6574 if (!adapter
->workq
) {
6576 goto out_free_adapter
;
6579 /* PCI device has been enabled */
6580 adapter
->flags
|= DEV_ENABLED
;
6582 adapter
->regs
= regs
;
6583 adapter
->pdev
= pdev
;
6584 adapter
->pdev_dev
= &pdev
->dev
;
6585 adapter
->mbox
= func
;
6587 adapter
->msg_enable
= dflt_msg_enable
;
6588 memset(adapter
->chan_map
, 0xff, sizeof(adapter
->chan_map
));
6590 spin_lock_init(&adapter
->stats_lock
);
6591 spin_lock_init(&adapter
->tid_release_lock
);
6593 INIT_WORK(&adapter
->tid_release_task
, process_tid_release_list
);
6594 INIT_WORK(&adapter
->db_full_task
, process_db_full
);
6595 INIT_WORK(&adapter
->db_drop_task
, process_db_drop
);
6597 err
= t4_prep_adapter(adapter
);
6599 goto out_free_adapter
;
6602 if (!is_t4(adapter
->params
.chip
)) {
6603 s_qpp
= QUEUESPERPAGEPF1
* adapter
->fn
;
6604 qpp
= 1 << QUEUESPERPAGEPF0_GET(t4_read_reg(adapter
,
6605 SGE_EGRESS_QUEUES_PER_PAGE_PF
) >> s_qpp
);
6606 num_seg
= PAGE_SIZE
/ SEGMENT_SIZE
;
6608 /* Each segment size is 128B. Write coalescing is enabled only
6609 * when SGE_EGRESS_QUEUES_PER_PAGE_PF reg value for the
6610 * queue is less no of segments that can be accommodated in
6613 if (qpp
> num_seg
) {
6615 "Incorrect number of egress queues per page\n");
6617 goto out_free_adapter
;
6619 adapter
->bar2
= ioremap_wc(pci_resource_start(pdev
, 2),
6620 pci_resource_len(pdev
, 2));
6621 if (!adapter
->bar2
) {
6622 dev_err(&pdev
->dev
, "cannot map device bar2 region\n");
6624 goto out_free_adapter
;
6628 setup_memwin(adapter
);
6629 err
= adap_init0(adapter
);
6630 setup_memwin_rdma(adapter
);
6634 for_each_port(adapter
, i
) {
6635 struct net_device
*netdev
;
6637 netdev
= alloc_etherdev_mq(sizeof(struct port_info
),
6644 SET_NETDEV_DEV(netdev
, &pdev
->dev
);
6646 adapter
->port
[i
] = netdev
;
6647 pi
= netdev_priv(netdev
);
6648 pi
->adapter
= adapter
;
6649 pi
->xact_addr_filt
= -1;
6651 netdev
->irq
= pdev
->irq
;
6653 netdev
->hw_features
= NETIF_F_SG
| TSO_FLAGS
|
6654 NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
6655 NETIF_F_RXCSUM
| NETIF_F_RXHASH
|
6656 NETIF_F_HW_VLAN_CTAG_TX
| NETIF_F_HW_VLAN_CTAG_RX
;
6658 netdev
->hw_features
|= NETIF_F_HIGHDMA
;
6659 netdev
->features
|= netdev
->hw_features
;
6660 netdev
->vlan_features
= netdev
->features
& VLAN_FEAT
;
6662 netdev
->priv_flags
|= IFF_UNICAST_FLT
;
6664 netdev
->netdev_ops
= &cxgb4_netdev_ops
;
6665 #ifdef CONFIG_CHELSIO_T4_DCB
6666 netdev
->dcbnl_ops
= &cxgb4_dcb_ops
;
6667 cxgb4_dcb_state_init(netdev
);
6669 netdev
->ethtool_ops
= &cxgb_ethtool_ops
;
6672 pci_set_drvdata(pdev
, adapter
);
6674 if (adapter
->flags
& FW_OK
) {
6675 err
= t4_port_init(adapter
, func
, func
, 0);
6681 * Configure queues and allocate tables now, they can be needed as
6682 * soon as the first register_netdev completes.
6684 cfg_queues(adapter
);
6686 adapter
->l2t
= t4_init_l2t();
6687 if (!adapter
->l2t
) {
6688 /* We tolerate a lack of L2T, giving up some functionality */
6689 dev_warn(&pdev
->dev
, "could not allocate L2T, continuing\n");
6690 adapter
->params
.offload
= 0;
6693 if (is_offload(adapter
) && tid_init(&adapter
->tids
) < 0) {
6694 dev_warn(&pdev
->dev
, "could not allocate TID table, "
6696 adapter
->params
.offload
= 0;
6699 /* See what interrupts we'll be using */
6700 if (msi
> 1 && enable_msix(adapter
) == 0)
6701 adapter
->flags
|= USING_MSIX
;
6702 else if (msi
> 0 && pci_enable_msi(pdev
) == 0)
6703 adapter
->flags
|= USING_MSI
;
6705 err
= init_rss(adapter
);
6710 * The card is now ready to go. If any errors occur during device
6711 * registration we do not fail the whole card but rather proceed only
6712 * with the ports we manage to register successfully. However we must
6713 * register at least one net device.
6715 for_each_port(adapter
, i
) {
6716 pi
= adap2pinfo(adapter
, i
);
6717 netif_set_real_num_tx_queues(adapter
->port
[i
], pi
->nqsets
);
6718 netif_set_real_num_rx_queues(adapter
->port
[i
], pi
->nqsets
);
6720 err
= register_netdev(adapter
->port
[i
]);
6723 adapter
->chan_map
[pi
->tx_chan
] = i
;
6724 print_port_info(adapter
->port
[i
]);
6727 dev_err(&pdev
->dev
, "could not register any net devices\n");
6731 dev_warn(&pdev
->dev
, "only %d net devices registered\n", i
);
6735 if (cxgb4_debugfs_root
) {
6736 adapter
->debugfs_root
= debugfs_create_dir(pci_name(pdev
),
6737 cxgb4_debugfs_root
);
6738 setup_debugfs(adapter
);
6741 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
6742 pdev
->needs_freset
= 1;
6744 if (is_offload(adapter
))
6745 attach_ulds(adapter
);
6748 #ifdef CONFIG_PCI_IOV
6749 if (func
< ARRAY_SIZE(num_vf
) && num_vf
[func
] > 0)
6750 if (pci_enable_sriov(pdev
, num_vf
[func
]) == 0)
6751 dev_info(&pdev
->dev
,
6752 "instantiated %u virtual functions\n",
6758 free_some_resources(adapter
);
6760 if (!is_t4(adapter
->params
.chip
))
6761 iounmap(adapter
->bar2
);
6764 destroy_workqueue(adapter
->workq
);
6770 pci_disable_pcie_error_reporting(pdev
);
6771 pci_disable_device(pdev
);
6772 out_release_regions
:
6773 pci_release_regions(pdev
);
6777 static void remove_one(struct pci_dev
*pdev
)
6779 struct adapter
*adapter
= pci_get_drvdata(pdev
);
6781 #ifdef CONFIG_PCI_IOV
6782 pci_disable_sriov(pdev
);
6789 /* Tear down per-adapter Work Queue first since it can contain
6790 * references to our adapter data structure.
6792 destroy_workqueue(adapter
->workq
);
6794 if (is_offload(adapter
))
6795 detach_ulds(adapter
);
6797 for_each_port(adapter
, i
)
6798 if (adapter
->port
[i
]->reg_state
== NETREG_REGISTERED
)
6799 unregister_netdev(adapter
->port
[i
]);
6801 debugfs_remove_recursive(adapter
->debugfs_root
);
6803 /* If we allocated filters, free up state associated with any
6806 if (adapter
->tids
.ftid_tab
) {
6807 struct filter_entry
*f
= &adapter
->tids
.ftid_tab
[0];
6808 for (i
= 0; i
< (adapter
->tids
.nftids
+
6809 adapter
->tids
.nsftids
); i
++, f
++)
6811 clear_filter(adapter
, f
);
6814 if (adapter
->flags
& FULL_INIT_DONE
)
6817 free_some_resources(adapter
);
6818 iounmap(adapter
->regs
);
6819 if (!is_t4(adapter
->params
.chip
))
6820 iounmap(adapter
->bar2
);
6821 pci_disable_pcie_error_reporting(pdev
);
6822 if ((adapter
->flags
& DEV_ENABLED
)) {
6823 pci_disable_device(pdev
);
6824 adapter
->flags
&= ~DEV_ENABLED
;
6826 pci_release_regions(pdev
);
6830 pci_release_regions(pdev
);
6833 static struct pci_driver cxgb4_driver
= {
6834 .name
= KBUILD_MODNAME
,
6835 .id_table
= cxgb4_pci_tbl
,
6837 .remove
= remove_one
,
6838 .shutdown
= remove_one
,
6839 .err_handler
= &cxgb4_eeh
,
6842 static int __init
cxgb4_init_module(void)
6846 /* Debugfs support is optional, just warn if this fails */
6847 cxgb4_debugfs_root
= debugfs_create_dir(KBUILD_MODNAME
, NULL
);
6848 if (!cxgb4_debugfs_root
)
6849 pr_warn("could not create debugfs entry, continuing\n");
6851 ret
= pci_register_driver(&cxgb4_driver
);
6853 debugfs_remove(cxgb4_debugfs_root
);
6855 register_inet6addr_notifier(&cxgb4_inet6addr_notifier
);
6860 static void __exit
cxgb4_cleanup_module(void)
6862 unregister_inet6addr_notifier(&cxgb4_inet6addr_notifier
);
6863 pci_unregister_driver(&cxgb4_driver
);
6864 debugfs_remove(cxgb4_debugfs_root
); /* NULL ok */
6867 module_init(cxgb4_init_module
);
6868 module_exit(cxgb4_cleanup_module
);