2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 #include <linux/delay.h>
38 #include "t4_values.h"
42 * t4_wait_op_done_val - wait until an operation is completed
43 * @adapter: the adapter performing the operation
44 * @reg: the register to check for completion
45 * @mask: a single-bit field within @reg that indicates completion
46 * @polarity: the value of the field when the operation is completed
47 * @attempts: number of check iterations
48 * @delay: delay in usecs between iterations
49 * @valp: where to store the value of the register at completion time
51 * Wait until an operation is completed by checking a bit in a register
52 * up to @attempts times. If @valp is not NULL the value of the register
53 * at the time it indicated completion is stored there. Returns 0 if the
54 * operation completes and -EAGAIN otherwise.
56 static int t4_wait_op_done_val(struct adapter
*adapter
, int reg
, u32 mask
,
57 int polarity
, int attempts
, int delay
, u32
*valp
)
60 u32 val
= t4_read_reg(adapter
, reg
);
62 if (!!(val
& mask
) == polarity
) {
74 static inline int t4_wait_op_done(struct adapter
*adapter
, int reg
, u32 mask
,
75 int polarity
, int attempts
, int delay
)
77 return t4_wait_op_done_val(adapter
, reg
, mask
, polarity
, attempts
,
82 * t4_set_reg_field - set a register field to a value
83 * @adapter: the adapter to program
84 * @addr: the register address
85 * @mask: specifies the portion of the register to modify
86 * @val: the new value for the register field
88 * Sets a register field specified by the supplied mask to the
91 void t4_set_reg_field(struct adapter
*adapter
, unsigned int addr
, u32 mask
,
94 u32 v
= t4_read_reg(adapter
, addr
) & ~mask
;
96 t4_write_reg(adapter
, addr
, v
| val
);
97 (void) t4_read_reg(adapter
, addr
); /* flush */
101 * t4_read_indirect - read indirectly addressed registers
103 * @addr_reg: register holding the indirect address
104 * @data_reg: register holding the value of the indirect register
105 * @vals: where the read register values are stored
106 * @nregs: how many indirect registers to read
107 * @start_idx: index of first indirect register to read
109 * Reads registers that are accessed indirectly through an address/data
112 void t4_read_indirect(struct adapter
*adap
, unsigned int addr_reg
,
113 unsigned int data_reg
, u32
*vals
,
114 unsigned int nregs
, unsigned int start_idx
)
117 t4_write_reg(adap
, addr_reg
, start_idx
);
118 *vals
++ = t4_read_reg(adap
, data_reg
);
124 * t4_write_indirect - write indirectly addressed registers
126 * @addr_reg: register holding the indirect addresses
127 * @data_reg: register holding the value for the indirect registers
128 * @vals: values to write
129 * @nregs: how many indirect registers to write
130 * @start_idx: address of first indirect register to write
132 * Writes a sequential block of registers that are accessed indirectly
133 * through an address/data register pair.
135 void t4_write_indirect(struct adapter
*adap
, unsigned int addr_reg
,
136 unsigned int data_reg
, const u32
*vals
,
137 unsigned int nregs
, unsigned int start_idx
)
140 t4_write_reg(adap
, addr_reg
, start_idx
++);
141 t4_write_reg(adap
, data_reg
, *vals
++);
146 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
147 * mechanism. This guarantees that we get the real value even if we're
148 * operating within a Virtual Machine and the Hypervisor is trapping our
149 * Configuration Space accesses.
151 void t4_hw_pci_read_cfg4(struct adapter
*adap
, int reg
, u32
*val
)
153 u32 req
= ENABLE_F
| FUNCTION_V(adap
->fn
) | REGISTER_V(reg
);
155 if (is_t4(adap
->params
.chip
))
158 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, req
);
159 *val
= t4_read_reg(adap
, PCIE_CFG_SPACE_DATA_A
);
161 /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
162 * Configuration Space read. (None of the other fields matter when
163 * ENABLE is 0 so a simple register write is easier than a
164 * read-modify-write via t4_set_reg_field().)
166 t4_write_reg(adap
, PCIE_CFG_SPACE_REQ_A
, 0);
170 * t4_report_fw_error - report firmware error
173 * The adapter firmware can indicate error conditions to the host.
174 * If the firmware has indicated an error, print out the reason for
175 * the firmware error.
177 static void t4_report_fw_error(struct adapter
*adap
)
179 static const char *const reason
[] = {
180 "Crash", /* PCIE_FW_EVAL_CRASH */
181 "During Device Preparation", /* PCIE_FW_EVAL_PREP */
182 "During Device Configuration", /* PCIE_FW_EVAL_CONF */
183 "During Device Initialization", /* PCIE_FW_EVAL_INIT */
184 "Unexpected Event", /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
185 "Insufficient Airflow", /* PCIE_FW_EVAL_OVERHEAT */
186 "Device Shutdown", /* PCIE_FW_EVAL_DEVICESHUTDOWN */
187 "Reserved", /* reserved */
191 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
192 if (pcie_fw
& PCIE_FW_ERR_F
)
193 dev_err(adap
->pdev_dev
, "Firmware reports adapter error: %s\n",
194 reason
[PCIE_FW_EVAL_G(pcie_fw
)]);
198 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
200 static void get_mbox_rpl(struct adapter
*adap
, __be64
*rpl
, int nflit
,
203 for ( ; nflit
; nflit
--, mbox_addr
+= 8)
204 *rpl
++ = cpu_to_be64(t4_read_reg64(adap
, mbox_addr
));
208 * Handle a FW assertion reported in a mailbox.
210 static void fw_asrt(struct adapter
*adap
, u32 mbox_addr
)
212 struct fw_debug_cmd asrt
;
214 get_mbox_rpl(adap
, (__be64
*)&asrt
, sizeof(asrt
) / 8, mbox_addr
);
215 dev_alert(adap
->pdev_dev
,
216 "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
217 asrt
.u
.assert.filename_0_7
, ntohl(asrt
.u
.assert.line
),
218 ntohl(asrt
.u
.assert.x
), ntohl(asrt
.u
.assert.y
));
221 static void dump_mbox(struct adapter
*adap
, int mbox
, u32 data_reg
)
223 dev_err(adap
->pdev_dev
,
224 "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox
,
225 (unsigned long long)t4_read_reg64(adap
, data_reg
),
226 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 8),
227 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 16),
228 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 24),
229 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 32),
230 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 40),
231 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 48),
232 (unsigned long long)t4_read_reg64(adap
, data_reg
+ 56));
236 * t4_wr_mbox_meat - send a command to FW through the given mailbox
238 * @mbox: index of the mailbox to use
239 * @cmd: the command to write
240 * @size: command length in bytes
241 * @rpl: where to optionally store the reply
242 * @sleep_ok: if true we may sleep while awaiting command completion
244 * Sends the given command to FW through the selected mailbox and waits
245 * for the FW to execute the command. If @rpl is not %NULL it is used to
246 * store the FW's reply to the command. The command and its optional
247 * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
248 * to respond. @sleep_ok determines whether we may sleep while awaiting
249 * the response. If sleeping is allowed we use progressive backoff
252 * The return value is 0 on success or a negative errno on failure. A
253 * failure can happen either because we are not able to execute the
254 * command or FW executes it but signals an error. In the latter case
255 * the return value is the error code indicated by FW (negated).
257 int t4_wr_mbox_meat(struct adapter
*adap
, int mbox
, const void *cmd
, int size
,
258 void *rpl
, bool sleep_ok
)
260 static const int delay
[] = {
261 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
266 int i
, ms
, delay_idx
;
267 const __be64
*p
= cmd
;
268 u32 data_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_DATA_A
);
269 u32 ctl_reg
= PF_REG(mbox
, CIM_PF_MAILBOX_CTRL_A
);
271 if ((size
& 15) || size
> MBOX_LEN
)
275 * If the device is off-line, as in EEH, commands will time out.
276 * Fail them early so we don't waste time waiting.
278 if (adap
->pdev
->error_state
!= pci_channel_io_normal
)
281 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
282 for (i
= 0; v
== MBOX_OWNER_NONE
&& i
< 3; i
++)
283 v
= MBOWNER_G(t4_read_reg(adap
, ctl_reg
));
285 if (v
!= MBOX_OWNER_DRV
)
286 return v
? -EBUSY
: -ETIMEDOUT
;
288 for (i
= 0; i
< size
; i
+= 8)
289 t4_write_reg64(adap
, data_reg
+ i
, be64_to_cpu(*p
++));
291 t4_write_reg(adap
, ctl_reg
, MBMSGVALID_F
| MBOWNER_V(MBOX_OWNER_FW
));
292 t4_read_reg(adap
, ctl_reg
); /* flush write */
297 for (i
= 0; i
< FW_CMD_MAX_TIMEOUT
; i
+= ms
) {
299 ms
= delay
[delay_idx
]; /* last element may repeat */
300 if (delay_idx
< ARRAY_SIZE(delay
) - 1)
306 v
= t4_read_reg(adap
, ctl_reg
);
307 if (MBOWNER_G(v
) == MBOX_OWNER_DRV
) {
308 if (!(v
& MBMSGVALID_F
)) {
309 t4_write_reg(adap
, ctl_reg
, 0);
313 res
= t4_read_reg64(adap
, data_reg
);
314 if (FW_CMD_OP_G(res
>> 32) == FW_DEBUG_CMD
) {
315 fw_asrt(adap
, data_reg
);
316 res
= FW_CMD_RETVAL_V(EIO
);
318 get_mbox_rpl(adap
, rpl
, size
/ 8, data_reg
);
321 if (FW_CMD_RETVAL_G((int)res
))
322 dump_mbox(adap
, mbox
, data_reg
);
323 t4_write_reg(adap
, ctl_reg
, 0);
324 return -FW_CMD_RETVAL_G((int)res
);
328 dump_mbox(adap
, mbox
, data_reg
);
329 dev_err(adap
->pdev_dev
, "command %#x in mailbox %d timed out\n",
330 *(const u8
*)cmd
, mbox
);
331 t4_report_fw_error(adap
);
336 * t4_mc_read - read from MC through backdoor accesses
338 * @addr: address of first byte requested
339 * @idx: which MC to access
340 * @data: 64 bytes of data containing the requested address
341 * @ecc: where to store the corresponding 64-bit ECC word
343 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
344 * that covers the requested address @addr. If @parity is not %NULL it
345 * is assigned the 64-bit ECC word for the read data.
347 int t4_mc_read(struct adapter
*adap
, int idx
, u32 addr
, __be32
*data
, u64
*ecc
)
350 u32 mc_bist_cmd
, mc_bist_cmd_addr
, mc_bist_cmd_len
;
351 u32 mc_bist_status_rdata
, mc_bist_data_pattern
;
353 if (is_t4(adap
->params
.chip
)) {
354 mc_bist_cmd
= MC_BIST_CMD_A
;
355 mc_bist_cmd_addr
= MC_BIST_CMD_ADDR_A
;
356 mc_bist_cmd_len
= MC_BIST_CMD_LEN_A
;
357 mc_bist_status_rdata
= MC_BIST_STATUS_RDATA_A
;
358 mc_bist_data_pattern
= MC_BIST_DATA_PATTERN_A
;
360 mc_bist_cmd
= MC_REG(MC_P_BIST_CMD_A
, idx
);
361 mc_bist_cmd_addr
= MC_REG(MC_P_BIST_CMD_ADDR_A
, idx
);
362 mc_bist_cmd_len
= MC_REG(MC_P_BIST_CMD_LEN_A
, idx
);
363 mc_bist_status_rdata
= MC_REG(MC_P_BIST_STATUS_RDATA_A
, idx
);
364 mc_bist_data_pattern
= MC_REG(MC_P_BIST_DATA_PATTERN_A
, idx
);
367 if (t4_read_reg(adap
, mc_bist_cmd
) & START_BIST_F
)
369 t4_write_reg(adap
, mc_bist_cmd_addr
, addr
& ~0x3fU
);
370 t4_write_reg(adap
, mc_bist_cmd_len
, 64);
371 t4_write_reg(adap
, mc_bist_data_pattern
, 0xc);
372 t4_write_reg(adap
, mc_bist_cmd
, BIST_OPCODE_V(1) | START_BIST_F
|
374 i
= t4_wait_op_done(adap
, mc_bist_cmd
, START_BIST_F
, 0, 10, 1);
378 #define MC_DATA(i) MC_BIST_STATUS_REG(mc_bist_status_rdata, i)
380 for (i
= 15; i
>= 0; i
--)
381 *data
++ = htonl(t4_read_reg(adap
, MC_DATA(i
)));
383 *ecc
= t4_read_reg64(adap
, MC_DATA(16));
389 * t4_edc_read - read from EDC through backdoor accesses
391 * @idx: which EDC to access
392 * @addr: address of first byte requested
393 * @data: 64 bytes of data containing the requested address
394 * @ecc: where to store the corresponding 64-bit ECC word
396 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
397 * that covers the requested address @addr. If @parity is not %NULL it
398 * is assigned the 64-bit ECC word for the read data.
400 int t4_edc_read(struct adapter
*adap
, int idx
, u32 addr
, __be32
*data
, u64
*ecc
)
403 u32 edc_bist_cmd
, edc_bist_cmd_addr
, edc_bist_cmd_len
;
404 u32 edc_bist_cmd_data_pattern
, edc_bist_status_rdata
;
406 if (is_t4(adap
->params
.chip
)) {
407 edc_bist_cmd
= EDC_REG(EDC_BIST_CMD_A
, idx
);
408 edc_bist_cmd_addr
= EDC_REG(EDC_BIST_CMD_ADDR_A
, idx
);
409 edc_bist_cmd_len
= EDC_REG(EDC_BIST_CMD_LEN_A
, idx
);
410 edc_bist_cmd_data_pattern
= EDC_REG(EDC_BIST_DATA_PATTERN_A
,
412 edc_bist_status_rdata
= EDC_REG(EDC_BIST_STATUS_RDATA_A
,
415 edc_bist_cmd
= EDC_REG_T5(EDC_H_BIST_CMD_A
, idx
);
416 edc_bist_cmd_addr
= EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A
, idx
);
417 edc_bist_cmd_len
= EDC_REG_T5(EDC_H_BIST_CMD_LEN_A
, idx
);
418 edc_bist_cmd_data_pattern
=
419 EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A
, idx
);
420 edc_bist_status_rdata
=
421 EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A
, idx
);
424 if (t4_read_reg(adap
, edc_bist_cmd
) & START_BIST_F
)
426 t4_write_reg(adap
, edc_bist_cmd_addr
, addr
& ~0x3fU
);
427 t4_write_reg(adap
, edc_bist_cmd_len
, 64);
428 t4_write_reg(adap
, edc_bist_cmd_data_pattern
, 0xc);
429 t4_write_reg(adap
, edc_bist_cmd
,
430 BIST_OPCODE_V(1) | BIST_CMD_GAP_V(1) | START_BIST_F
);
431 i
= t4_wait_op_done(adap
, edc_bist_cmd
, START_BIST_F
, 0, 10, 1);
435 #define EDC_DATA(i) (EDC_BIST_STATUS_REG(edc_bist_status_rdata, i))
437 for (i
= 15; i
>= 0; i
--)
438 *data
++ = htonl(t4_read_reg(adap
, EDC_DATA(i
)));
440 *ecc
= t4_read_reg64(adap
, EDC_DATA(16));
446 * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
448 * @win: PCI-E Memory Window to use
449 * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
450 * @addr: address within indicated memory type
451 * @len: amount of memory to transfer
452 * @buf: host memory buffer
453 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
455 * Reads/writes an [almost] arbitrary memory region in the firmware: the
456 * firmware memory address and host buffer must be aligned on 32-bit
457 * boudaries; the length may be arbitrary. The memory is transferred as
458 * a raw byte sequence from/to the firmware's memory. If this memory
459 * contains data structures which contain multi-byte integers, it's the
460 * caller's responsibility to perform appropriate byte order conversions.
462 int t4_memory_rw(struct adapter
*adap
, int win
, int mtype
, u32 addr
,
463 u32 len
, __be32
*buf
, int dir
)
465 u32 pos
, offset
, resid
, memoffset
;
466 u32 edc_size
, mc_size
, win_pf
, mem_reg
, mem_aperture
, mem_base
;
468 /* Argument sanity checks ...
473 /* It's convenient to be able to handle lengths which aren't a
474 * multiple of 32-bits because we often end up transferring files to
475 * the firmware. So we'll handle that by normalizing the length here
476 * and then handling any residual transfer at the end.
481 /* Offset into the region of memory which is being accessed
485 * MEM_MC0 = 2 -- For T5
486 * MEM_MC1 = 3 -- For T5
488 edc_size
= EDRAM0_SIZE_G(t4_read_reg(adap
, MA_EDRAM0_BAR_A
));
489 if (mtype
!= MEM_MC1
)
490 memoffset
= (mtype
* (edc_size
* 1024 * 1024));
492 mc_size
= EXT_MEM0_SIZE_G(t4_read_reg(adap
,
493 MA_EXT_MEMORY1_BAR_A
));
494 memoffset
= (MEM_MC0
* edc_size
+ mc_size
) * 1024 * 1024;
497 /* Determine the PCIE_MEM_ACCESS_OFFSET */
498 addr
= addr
+ memoffset
;
500 /* Each PCI-E Memory Window is programmed with a window size -- or
501 * "aperture" -- which controls the granularity of its mapping onto
502 * adapter memory. We need to grab that aperture in order to know
503 * how to use the specified window. The window is also programmed
504 * with the base address of the Memory Window in BAR0's address
505 * space. For T4 this is an absolute PCI-E Bus Address. For T5
506 * the address is relative to BAR0.
508 mem_reg
= t4_read_reg(adap
,
509 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A
,
511 mem_aperture
= 1 << (WINDOW_G(mem_reg
) + WINDOW_SHIFT_X
);
512 mem_base
= PCIEOFST_G(mem_reg
) << PCIEOFST_SHIFT_X
;
513 if (is_t4(adap
->params
.chip
))
514 mem_base
-= adap
->t4_bar0
;
515 win_pf
= is_t4(adap
->params
.chip
) ? 0 : PFNUM_V(adap
->fn
);
517 /* Calculate our initial PCI-E Memory Window Position and Offset into
520 pos
= addr
& ~(mem_aperture
-1);
523 /* Set up initial PCI-E Memory Window to cover the start of our
524 * transfer. (Read it back to ensure that changes propagate before we
525 * attempt to use the new value.)
528 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
),
531 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
, win
));
533 /* Transfer data to/from the adapter as long as there's an integral
534 * number of 32-bit transfers to complete.
537 if (dir
== T4_MEMORY_READ
)
538 *buf
++ = (__force __be32
) t4_read_reg(adap
,
541 t4_write_reg(adap
, mem_base
+ offset
,
542 (__force u32
) *buf
++);
543 offset
+= sizeof(__be32
);
544 len
-= sizeof(__be32
);
546 /* If we've reached the end of our current window aperture,
547 * move the PCI-E Memory Window on to the next. Note that
548 * doing this here after "len" may be 0 allows us to set up
549 * the PCI-E Memory Window for a possible final residual
552 if (offset
== mem_aperture
) {
556 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
,
559 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A
,
564 /* If the original transfer had a length which wasn't a multiple of
565 * 32-bits, now's where we need to finish off the transfer of the
566 * residual amount. The PCI-E Memory Window has already been moved
567 * above (if necessary) to cover this final transfer.
577 if (dir
== T4_MEMORY_READ
) {
578 last
.word
= (__force __be32
) t4_read_reg(adap
,
580 for (bp
= (unsigned char *)buf
, i
= resid
; i
< 4; i
++)
581 bp
[i
] = last
.byte
[i
];
584 for (i
= resid
; i
< 4; i
++)
586 t4_write_reg(adap
, mem_base
+ offset
,
587 (__force u32
) last
.word
);
594 #define EEPROM_STAT_ADDR 0x7bfc
595 #define VPD_BASE 0x400
596 #define VPD_BASE_OLD 0
598 #define CHELSIO_VPD_UNIQUE_ID 0x82
601 * t4_seeprom_wp - enable/disable EEPROM write protection
602 * @adapter: the adapter
603 * @enable: whether to enable or disable write protection
605 * Enables or disables write protection on the serial EEPROM.
607 int t4_seeprom_wp(struct adapter
*adapter
, bool enable
)
609 unsigned int v
= enable
? 0xc : 0;
610 int ret
= pci_write_vpd(adapter
->pdev
, EEPROM_STAT_ADDR
, 4, &v
);
611 return ret
< 0 ? ret
: 0;
615 * get_vpd_params - read VPD parameters from VPD EEPROM
616 * @adapter: adapter to read
617 * @p: where to store the parameters
619 * Reads card parameters stored in VPD EEPROM.
621 int get_vpd_params(struct adapter
*adapter
, struct vpd_params
*p
)
623 u32 cclk_param
, cclk_val
;
627 unsigned int vpdr_len
, kw_offset
, id_len
;
629 vpd
= vmalloc(VPD_LEN
);
633 ret
= pci_read_vpd(adapter
->pdev
, VPD_BASE
, sizeof(u32
), vpd
);
637 /* The VPD shall have a unique identifier specified by the PCI SIG.
638 * For chelsio adapters, the identifier is 0x82. The first byte of a VPD
639 * shall be CHELSIO_VPD_UNIQUE_ID (0x82). The VPD programming software
640 * is expected to automatically put this entry at the
641 * beginning of the VPD.
643 addr
= *vpd
== CHELSIO_VPD_UNIQUE_ID
? VPD_BASE
: VPD_BASE_OLD
;
645 ret
= pci_read_vpd(adapter
->pdev
, addr
, VPD_LEN
, vpd
);
649 if (vpd
[0] != PCI_VPD_LRDT_ID_STRING
) {
650 dev_err(adapter
->pdev_dev
, "missing VPD ID string\n");
655 id_len
= pci_vpd_lrdt_size(vpd
);
659 i
= pci_vpd_find_tag(vpd
, 0, VPD_LEN
, PCI_VPD_LRDT_RO_DATA
);
661 dev_err(adapter
->pdev_dev
, "missing VPD-R section\n");
666 vpdr_len
= pci_vpd_lrdt_size(&vpd
[i
]);
667 kw_offset
= i
+ PCI_VPD_LRDT_TAG_SIZE
;
668 if (vpdr_len
+ kw_offset
> VPD_LEN
) {
669 dev_err(adapter
->pdev_dev
, "bad VPD-R length %u\n", vpdr_len
);
674 #define FIND_VPD_KW(var, name) do { \
675 var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
677 dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
681 var += PCI_VPD_INFO_FLD_HDR_SIZE; \
684 FIND_VPD_KW(i
, "RV");
685 for (csum
= 0; i
>= 0; i
--)
689 dev_err(adapter
->pdev_dev
,
690 "corrupted VPD EEPROM, actual csum %u\n", csum
);
695 FIND_VPD_KW(ec
, "EC");
696 FIND_VPD_KW(sn
, "SN");
697 FIND_VPD_KW(pn
, "PN");
700 memcpy(p
->id
, vpd
+ PCI_VPD_LRDT_TAG_SIZE
, id_len
);
702 memcpy(p
->ec
, vpd
+ ec
, EC_LEN
);
704 i
= pci_vpd_info_field_size(vpd
+ sn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
705 memcpy(p
->sn
, vpd
+ sn
, min(i
, SERNUM_LEN
));
707 i
= pci_vpd_info_field_size(vpd
+ pn
- PCI_VPD_INFO_FLD_HDR_SIZE
);
708 memcpy(p
->pn
, vpd
+ pn
, min(i
, PN_LEN
));
712 * Ask firmware for the Core Clock since it knows how to translate the
713 * Reference Clock ('V2') VPD field into a Core Clock value ...
715 cclk_param
= (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
716 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK
));
717 ret
= t4_query_params(adapter
, adapter
->mbox
, 0, 0,
718 1, &cclk_param
, &cclk_val
);
729 /* serial flash and firmware constants */
731 SF_ATTEMPTS
= 10, /* max retries for SF operations */
733 /* flash command opcodes */
734 SF_PROG_PAGE
= 2, /* program page */
735 SF_WR_DISABLE
= 4, /* disable writes */
736 SF_RD_STATUS
= 5, /* read status register */
737 SF_WR_ENABLE
= 6, /* enable writes */
738 SF_RD_DATA_FAST
= 0xb, /* read flash */
739 SF_RD_ID
= 0x9f, /* read ID */
740 SF_ERASE_SECTOR
= 0xd8, /* erase sector */
742 FW_MAX_SIZE
= 16 * SF_SEC_SIZE
,
746 * sf1_read - read data from the serial flash
747 * @adapter: the adapter
748 * @byte_cnt: number of bytes to read
749 * @cont: whether another operation will be chained
750 * @lock: whether to lock SF for PL access only
751 * @valp: where to store the read data
753 * Reads up to 4 bytes of data from the serial flash. The location of
754 * the read needs to be specified prior to calling this by issuing the
755 * appropriate commands to the serial flash.
757 static int sf1_read(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
762 if (!byte_cnt
|| byte_cnt
> 4)
764 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
766 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
767 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1));
768 ret
= t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
770 *valp
= t4_read_reg(adapter
, SF_DATA_A
);
775 * sf1_write - write data to the serial flash
776 * @adapter: the adapter
777 * @byte_cnt: number of bytes to write
778 * @cont: whether another operation will be chained
779 * @lock: whether to lock SF for PL access only
780 * @val: value to write
782 * Writes up to 4 bytes of data to the serial flash. The location of
783 * the write needs to be specified prior to calling this by issuing the
784 * appropriate commands to the serial flash.
786 static int sf1_write(struct adapter
*adapter
, unsigned int byte_cnt
, int cont
,
789 if (!byte_cnt
|| byte_cnt
> 4)
791 if (t4_read_reg(adapter
, SF_OP_A
) & SF_BUSY_F
)
793 t4_write_reg(adapter
, SF_DATA_A
, val
);
794 t4_write_reg(adapter
, SF_OP_A
, SF_LOCK_V(lock
) |
795 SF_CONT_V(cont
) | BYTECNT_V(byte_cnt
- 1) | OP_V(1));
796 return t4_wait_op_done(adapter
, SF_OP_A
, SF_BUSY_F
, 0, SF_ATTEMPTS
, 5);
800 * flash_wait_op - wait for a flash operation to complete
801 * @adapter: the adapter
802 * @attempts: max number of polls of the status register
803 * @delay: delay between polls in ms
805 * Wait for a flash operation to complete by polling the status register.
807 static int flash_wait_op(struct adapter
*adapter
, int attempts
, int delay
)
813 if ((ret
= sf1_write(adapter
, 1, 1, 1, SF_RD_STATUS
)) != 0 ||
814 (ret
= sf1_read(adapter
, 1, 0, 1, &status
)) != 0)
826 * t4_read_flash - read words from serial flash
827 * @adapter: the adapter
828 * @addr: the start address for the read
829 * @nwords: how many 32-bit words to read
830 * @data: where to store the read data
831 * @byte_oriented: whether to store data as bytes or as words
833 * Read the specified number of 32-bit words from the serial flash.
834 * If @byte_oriented is set the read data is stored as a byte array
835 * (i.e., big-endian), otherwise as 32-bit words in the platform's
838 int t4_read_flash(struct adapter
*adapter
, unsigned int addr
,
839 unsigned int nwords
, u32
*data
, int byte_oriented
)
843 if (addr
+ nwords
* sizeof(u32
) > adapter
->params
.sf_size
|| (addr
& 3))
846 addr
= swab32(addr
) | SF_RD_DATA_FAST
;
848 if ((ret
= sf1_write(adapter
, 4, 1, 0, addr
)) != 0 ||
849 (ret
= sf1_read(adapter
, 1, 1, 0, data
)) != 0)
852 for ( ; nwords
; nwords
--, data
++) {
853 ret
= sf1_read(adapter
, 4, nwords
> 1, nwords
== 1, data
);
855 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
859 *data
= (__force __u32
) (htonl(*data
));
865 * t4_write_flash - write up to a page of data to the serial flash
866 * @adapter: the adapter
867 * @addr: the start address to write
868 * @n: length of data to write in bytes
869 * @data: the data to write
871 * Writes up to a page of data (256 bytes) to the serial flash starting
872 * at the given address. All the data must be written to the same page.
874 static int t4_write_flash(struct adapter
*adapter
, unsigned int addr
,
875 unsigned int n
, const u8
*data
)
879 unsigned int i
, c
, left
, val
, offset
= addr
& 0xff;
881 if (addr
>= adapter
->params
.sf_size
|| offset
+ n
> SF_PAGE_SIZE
)
884 val
= swab32(addr
) | SF_PROG_PAGE
;
886 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
887 (ret
= sf1_write(adapter
, 4, 1, 1, val
)) != 0)
890 for (left
= n
; left
; left
-= c
) {
892 for (val
= 0, i
= 0; i
< c
; ++i
)
893 val
= (val
<< 8) + *data
++;
895 ret
= sf1_write(adapter
, c
, c
!= left
, 1, val
);
899 ret
= flash_wait_op(adapter
, 8, 1);
903 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
905 /* Read the page to verify the write succeeded */
906 ret
= t4_read_flash(adapter
, addr
& ~0xff, ARRAY_SIZE(buf
), buf
, 1);
910 if (memcmp(data
- n
, (u8
*)buf
+ offset
, n
)) {
911 dev_err(adapter
->pdev_dev
,
912 "failed to correctly write the flash page at %#x\n",
919 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
924 * t4_get_fw_version - read the firmware version
925 * @adapter: the adapter
926 * @vers: where to place the version
928 * Reads the FW version from flash.
930 int t4_get_fw_version(struct adapter
*adapter
, u32
*vers
)
932 return t4_read_flash(adapter
, FLASH_FW_START
+
933 offsetof(struct fw_hdr
, fw_ver
), 1,
938 * t4_get_tp_version - read the TP microcode version
939 * @adapter: the adapter
940 * @vers: where to place the version
942 * Reads the TP microcode version from flash.
944 int t4_get_tp_version(struct adapter
*adapter
, u32
*vers
)
946 return t4_read_flash(adapter
, FLASH_FW_START
+
947 offsetof(struct fw_hdr
, tp_microcode_ver
),
951 /* Is the given firmware API compatible with the one the driver was compiled
954 static int fw_compatible(const struct fw_hdr
*hdr1
, const struct fw_hdr
*hdr2
)
957 /* short circuit if it's the exact same firmware version */
958 if (hdr1
->chip
== hdr2
->chip
&& hdr1
->fw_ver
== hdr2
->fw_ver
)
961 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
962 if (hdr1
->chip
== hdr2
->chip
&& SAME_INTF(nic
) && SAME_INTF(vnic
) &&
963 SAME_INTF(ri
) && SAME_INTF(iscsi
) && SAME_INTF(fcoe
))
970 /* The firmware in the filesystem is usable, but should it be installed?
971 * This routine explains itself in detail if it indicates the filesystem
972 * firmware should be installed.
974 static int should_install_fs_fw(struct adapter
*adap
, int card_fw_usable
,
979 if (!card_fw_usable
) {
980 reason
= "incompatible or unusable";
985 reason
= "older than the version supported with this driver";
992 dev_err(adap
->pdev_dev
, "firmware on card (%u.%u.%u.%u) is %s, "
993 "installing firmware %u.%u.%u.%u on card.\n",
994 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
995 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
), reason
,
996 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
997 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
1002 int t4_prep_fw(struct adapter
*adap
, struct fw_info
*fw_info
,
1003 const u8
*fw_data
, unsigned int fw_size
,
1004 struct fw_hdr
*card_fw
, enum dev_state state
,
1007 int ret
, card_fw_usable
, fs_fw_usable
;
1008 const struct fw_hdr
*fs_fw
;
1009 const struct fw_hdr
*drv_fw
;
1011 drv_fw
= &fw_info
->fw_hdr
;
1013 /* Read the header of the firmware on the card */
1014 ret
= -t4_read_flash(adap
, FLASH_FW_START
,
1015 sizeof(*card_fw
) / sizeof(uint32_t),
1016 (uint32_t *)card_fw
, 1);
1018 card_fw_usable
= fw_compatible(drv_fw
, (const void *)card_fw
);
1020 dev_err(adap
->pdev_dev
,
1021 "Unable to read card's firmware header: %d\n", ret
);
1025 if (fw_data
!= NULL
) {
1026 fs_fw
= (const void *)fw_data
;
1027 fs_fw_usable
= fw_compatible(drv_fw
, fs_fw
);
1033 if (card_fw_usable
&& card_fw
->fw_ver
== drv_fw
->fw_ver
&&
1034 (!fs_fw_usable
|| fs_fw
->fw_ver
== drv_fw
->fw_ver
)) {
1035 /* Common case: the firmware on the card is an exact match and
1036 * the filesystem one is an exact match too, or the filesystem
1037 * one is absent/incompatible.
1039 } else if (fs_fw_usable
&& state
== DEV_STATE_UNINIT
&&
1040 should_install_fs_fw(adap
, card_fw_usable
,
1041 be32_to_cpu(fs_fw
->fw_ver
),
1042 be32_to_cpu(card_fw
->fw_ver
))) {
1043 ret
= -t4_fw_upgrade(adap
, adap
->mbox
, fw_data
,
1046 dev_err(adap
->pdev_dev
,
1047 "failed to install firmware: %d\n", ret
);
1051 /* Installed successfully, update the cached header too. */
1052 memcpy(card_fw
, fs_fw
, sizeof(*card_fw
));
1054 *reset
= 0; /* already reset as part of load_fw */
1057 if (!card_fw_usable
) {
1060 d
= be32_to_cpu(drv_fw
->fw_ver
);
1061 c
= be32_to_cpu(card_fw
->fw_ver
);
1062 k
= fs_fw
? be32_to_cpu(fs_fw
->fw_ver
) : 0;
1064 dev_err(adap
->pdev_dev
, "Cannot find a usable firmware: "
1066 "driver compiled with %d.%d.%d.%d, "
1067 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
1069 FW_HDR_FW_VER_MAJOR_G(d
), FW_HDR_FW_VER_MINOR_G(d
),
1070 FW_HDR_FW_VER_MICRO_G(d
), FW_HDR_FW_VER_BUILD_G(d
),
1071 FW_HDR_FW_VER_MAJOR_G(c
), FW_HDR_FW_VER_MINOR_G(c
),
1072 FW_HDR_FW_VER_MICRO_G(c
), FW_HDR_FW_VER_BUILD_G(c
),
1073 FW_HDR_FW_VER_MAJOR_G(k
), FW_HDR_FW_VER_MINOR_G(k
),
1074 FW_HDR_FW_VER_MICRO_G(k
), FW_HDR_FW_VER_BUILD_G(k
));
1079 /* We're using whatever's on the card and it's known to be good. */
1080 adap
->params
.fw_vers
= be32_to_cpu(card_fw
->fw_ver
);
1081 adap
->params
.tp_vers
= be32_to_cpu(card_fw
->tp_microcode_ver
);
1088 * t4_flash_erase_sectors - erase a range of flash sectors
1089 * @adapter: the adapter
1090 * @start: the first sector to erase
1091 * @end: the last sector to erase
1093 * Erases the sectors in the given inclusive range.
1095 static int t4_flash_erase_sectors(struct adapter
*adapter
, int start
, int end
)
1099 if (end
>= adapter
->params
.sf_nsec
)
1102 while (start
<= end
) {
1103 if ((ret
= sf1_write(adapter
, 1, 0, 1, SF_WR_ENABLE
)) != 0 ||
1104 (ret
= sf1_write(adapter
, 4, 0, 1,
1105 SF_ERASE_SECTOR
| (start
<< 8))) != 0 ||
1106 (ret
= flash_wait_op(adapter
, 14, 500)) != 0) {
1107 dev_err(adapter
->pdev_dev
,
1108 "erase of flash sector %d failed, error %d\n",
1114 t4_write_reg(adapter
, SF_OP_A
, 0); /* unlock SF */
1119 * t4_flash_cfg_addr - return the address of the flash configuration file
1120 * @adapter: the adapter
1122 * Return the address within the flash where the Firmware Configuration
1125 unsigned int t4_flash_cfg_addr(struct adapter
*adapter
)
1127 if (adapter
->params
.sf_size
== 0x100000)
1128 return FLASH_FPGA_CFG_START
;
1130 return FLASH_CFG_START
;
1133 /* Return TRUE if the specified firmware matches the adapter. I.e. T4
1134 * firmware for T4 adapters, T5 firmware for T5 adapters, etc. We go ahead
1135 * and emit an error message for mismatched firmware to save our caller the
1138 static bool t4_fw_matches_chip(const struct adapter
*adap
,
1139 const struct fw_hdr
*hdr
)
1141 /* The expression below will return FALSE for any unsupported adapter
1142 * which will keep us "honest" in the future ...
1144 if ((is_t4(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T4
) ||
1145 (is_t5(adap
->params
.chip
) && hdr
->chip
== FW_HDR_CHIP_T5
))
1148 dev_err(adap
->pdev_dev
,
1149 "FW image (%d) is not suitable for this adapter (%d)\n",
1150 hdr
->chip
, CHELSIO_CHIP_VERSION(adap
->params
.chip
));
1155 * t4_load_fw - download firmware
1156 * @adap: the adapter
1157 * @fw_data: the firmware image to write
1160 * Write the supplied firmware image to the card's serial flash.
1162 int t4_load_fw(struct adapter
*adap
, const u8
*fw_data
, unsigned int size
)
1167 u8 first_page
[SF_PAGE_SIZE
];
1168 const __be32
*p
= (const __be32
*)fw_data
;
1169 const struct fw_hdr
*hdr
= (const struct fw_hdr
*)fw_data
;
1170 unsigned int sf_sec_size
= adap
->params
.sf_size
/ adap
->params
.sf_nsec
;
1171 unsigned int fw_img_start
= adap
->params
.sf_fw_start
;
1172 unsigned int fw_start_sec
= fw_img_start
/ sf_sec_size
;
1175 dev_err(adap
->pdev_dev
, "FW image has no data\n");
1179 dev_err(adap
->pdev_dev
,
1180 "FW image size not multiple of 512 bytes\n");
1183 if (ntohs(hdr
->len512
) * 512 != size
) {
1184 dev_err(adap
->pdev_dev
,
1185 "FW image size differs from size in FW header\n");
1188 if (size
> FW_MAX_SIZE
) {
1189 dev_err(adap
->pdev_dev
, "FW image too large, max is %u bytes\n",
1193 if (!t4_fw_matches_chip(adap
, hdr
))
1196 for (csum
= 0, i
= 0; i
< size
/ sizeof(csum
); i
++)
1197 csum
+= ntohl(p
[i
]);
1199 if (csum
!= 0xffffffff) {
1200 dev_err(adap
->pdev_dev
,
1201 "corrupted firmware image, checksum %#x\n", csum
);
1205 i
= DIV_ROUND_UP(size
, sf_sec_size
); /* # of sectors spanned */
1206 ret
= t4_flash_erase_sectors(adap
, fw_start_sec
, fw_start_sec
+ i
- 1);
1211 * We write the correct version at the end so the driver can see a bad
1212 * version if the FW write fails. Start by writing a copy of the
1213 * first page with a bad version.
1215 memcpy(first_page
, fw_data
, SF_PAGE_SIZE
);
1216 ((struct fw_hdr
*)first_page
)->fw_ver
= htonl(0xffffffff);
1217 ret
= t4_write_flash(adap
, fw_img_start
, SF_PAGE_SIZE
, first_page
);
1221 addr
= fw_img_start
;
1222 for (size
-= SF_PAGE_SIZE
; size
; size
-= SF_PAGE_SIZE
) {
1223 addr
+= SF_PAGE_SIZE
;
1224 fw_data
+= SF_PAGE_SIZE
;
1225 ret
= t4_write_flash(adap
, addr
, SF_PAGE_SIZE
, fw_data
);
1230 ret
= t4_write_flash(adap
,
1231 fw_img_start
+ offsetof(struct fw_hdr
, fw_ver
),
1232 sizeof(hdr
->fw_ver
), (const u8
*)&hdr
->fw_ver
);
1235 dev_err(adap
->pdev_dev
, "firmware download failed, error %d\n",
1238 ret
= t4_get_fw_version(adap
, &adap
->params
.fw_vers
);
1243 * t4_fwcache - firmware cache operation
1244 * @adap: the adapter
1245 * @op : the operation (flush or flush and invalidate)
1247 int t4_fwcache(struct adapter
*adap
, enum fw_params_param_dev_fwcache op
)
1249 struct fw_params_cmd c
;
1251 memset(&c
, 0, sizeof(c
));
1253 cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
1254 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
1255 FW_PARAMS_CMD_PFN_V(adap
->fn
) |
1256 FW_PARAMS_CMD_VFN_V(0));
1257 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
1259 cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV
) |
1260 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE
));
1261 c
.param
[0].val
= (__force __be32
)op
;
1263 return t4_wr_mbox(adap
, adap
->mbox
, &c
, sizeof(c
), NULL
);
1266 #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
1267 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G | \
1271 * t4_link_start - apply link configuration to MAC/PHY
1272 * @phy: the PHY to setup
1273 * @mac: the MAC to setup
1274 * @lc: the requested link configuration
1276 * Set up a port's MAC and PHY according to a desired link configuration.
1277 * - If the PHY can auto-negotiate first decide what to advertise, then
1278 * enable/disable auto-negotiation as desired, and reset.
1279 * - If the PHY does not auto-negotiate just reset it.
1280 * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
1281 * otherwise do it later based on the outcome of auto-negotiation.
1283 int t4_link_start(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
1284 struct link_config
*lc
)
1286 struct fw_port_cmd c
;
1287 unsigned int fc
= 0, mdi
= FW_PORT_CAP_MDI_V(FW_PORT_CAP_MDI_AUTO
);
1290 if (lc
->requested_fc
& PAUSE_RX
)
1291 fc
|= FW_PORT_CAP_FC_RX
;
1292 if (lc
->requested_fc
& PAUSE_TX
)
1293 fc
|= FW_PORT_CAP_FC_TX
;
1295 memset(&c
, 0, sizeof(c
));
1296 c
.op_to_portid
= htonl(FW_CMD_OP_V(FW_PORT_CMD
) | FW_CMD_REQUEST_F
|
1297 FW_CMD_EXEC_F
| FW_PORT_CMD_PORTID_V(port
));
1298 c
.action_to_len16
= htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG
) |
1301 if (!(lc
->supported
& FW_PORT_CAP_ANEG
)) {
1302 c
.u
.l1cfg
.rcap
= htonl((lc
->supported
& ADVERT_MASK
) | fc
);
1303 lc
->fc
= lc
->requested_fc
& (PAUSE_RX
| PAUSE_TX
);
1304 } else if (lc
->autoneg
== AUTONEG_DISABLE
) {
1305 c
.u
.l1cfg
.rcap
= htonl(lc
->requested_speed
| fc
| mdi
);
1306 lc
->fc
= lc
->requested_fc
& (PAUSE_RX
| PAUSE_TX
);
1308 c
.u
.l1cfg
.rcap
= htonl(lc
->advertising
| fc
| mdi
);
1310 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
1314 * t4_restart_aneg - restart autonegotiation
1315 * @adap: the adapter
1316 * @mbox: mbox to use for the FW command
1317 * @port: the port id
1319 * Restarts autonegotiation for the selected port.
1321 int t4_restart_aneg(struct adapter
*adap
, unsigned int mbox
, unsigned int port
)
1323 struct fw_port_cmd c
;
1325 memset(&c
, 0, sizeof(c
));
1326 c
.op_to_portid
= htonl(FW_CMD_OP_V(FW_PORT_CMD
) | FW_CMD_REQUEST_F
|
1327 FW_CMD_EXEC_F
| FW_PORT_CMD_PORTID_V(port
));
1328 c
.action_to_len16
= htonl(FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_L1_CFG
) |
1330 c
.u
.l1cfg
.rcap
= htonl(FW_PORT_CAP_ANEG
);
1331 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
1334 typedef void (*int_handler_t
)(struct adapter
*adap
);
1337 unsigned int mask
; /* bits to check in interrupt status */
1338 const char *msg
; /* message to print or NULL */
1339 short stat_idx
; /* stat counter to increment or -1 */
1340 unsigned short fatal
; /* whether the condition reported is fatal */
1341 int_handler_t int_handler
; /* platform-specific int handler */
1345 * t4_handle_intr_status - table driven interrupt handler
1346 * @adapter: the adapter that generated the interrupt
1347 * @reg: the interrupt status register to process
1348 * @acts: table of interrupt actions
1350 * A table driven interrupt handler that applies a set of masks to an
1351 * interrupt status word and performs the corresponding actions if the
1352 * interrupts described by the mask have occurred. The actions include
1353 * optionally emitting a warning or alert message. The table is terminated
1354 * by an entry specifying mask 0. Returns the number of fatal interrupt
1357 static int t4_handle_intr_status(struct adapter
*adapter
, unsigned int reg
,
1358 const struct intr_info
*acts
)
1361 unsigned int mask
= 0;
1362 unsigned int status
= t4_read_reg(adapter
, reg
);
1364 for ( ; acts
->mask
; ++acts
) {
1365 if (!(status
& acts
->mask
))
1369 dev_alert(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
1370 status
& acts
->mask
);
1371 } else if (acts
->msg
&& printk_ratelimit())
1372 dev_warn(adapter
->pdev_dev
, "%s (0x%x)\n", acts
->msg
,
1373 status
& acts
->mask
);
1374 if (acts
->int_handler
)
1375 acts
->int_handler(adapter
);
1379 if (status
) /* clear processed interrupts */
1380 t4_write_reg(adapter
, reg
, status
);
1385 * Interrupt handler for the PCIE module.
1387 static void pcie_intr_handler(struct adapter
*adapter
)
1389 static const struct intr_info sysbus_intr_info
[] = {
1390 { RNPP_F
, "RXNP array parity error", -1, 1 },
1391 { RPCP_F
, "RXPC array parity error", -1, 1 },
1392 { RCIP_F
, "RXCIF array parity error", -1, 1 },
1393 { RCCP_F
, "Rx completions control array parity error", -1, 1 },
1394 { RFTP_F
, "RXFT array parity error", -1, 1 },
1397 static const struct intr_info pcie_port_intr_info
[] = {
1398 { TPCP_F
, "TXPC array parity error", -1, 1 },
1399 { TNPP_F
, "TXNP array parity error", -1, 1 },
1400 { TFTP_F
, "TXFT array parity error", -1, 1 },
1401 { TCAP_F
, "TXCA array parity error", -1, 1 },
1402 { TCIP_F
, "TXCIF array parity error", -1, 1 },
1403 { RCAP_F
, "RXCA array parity error", -1, 1 },
1404 { OTDD_F
, "outbound request TLP discarded", -1, 1 },
1405 { RDPE_F
, "Rx data parity error", -1, 1 },
1406 { TDUE_F
, "Tx uncorrectable data error", -1, 1 },
1409 static const struct intr_info pcie_intr_info
[] = {
1410 { MSIADDRLPERR_F
, "MSI AddrL parity error", -1, 1 },
1411 { MSIADDRHPERR_F
, "MSI AddrH parity error", -1, 1 },
1412 { MSIDATAPERR_F
, "MSI data parity error", -1, 1 },
1413 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
1414 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
1415 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
1416 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
1417 { PIOCPLPERR_F
, "PCI PIO completion FIFO parity error", -1, 1 },
1418 { PIOREQPERR_F
, "PCI PIO request FIFO parity error", -1, 1 },
1419 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
1420 { CCNTPERR_F
, "PCI CMD channel count parity error", -1, 1 },
1421 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
1422 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
1423 { DCNTPERR_F
, "PCI DMA channel count parity error", -1, 1 },
1424 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
1425 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
1426 { HCNTPERR_F
, "PCI HMA channel count parity error", -1, 1 },
1427 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
1428 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
1429 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
1430 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
1431 { INTXCLRPERR_F
, "PCI INTx clear parity error", -1, 1 },
1432 { MATAGPERR_F
, "PCI MA tag parity error", -1, 1 },
1433 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
1434 { RXCPLPERR_F
, "PCI Rx completion parity error", -1, 1 },
1435 { RXWRPERR_F
, "PCI Rx write parity error", -1, 1 },
1436 { RPLPERR_F
, "PCI replay buffer parity error", -1, 1 },
1437 { PCIESINT_F
, "PCI core secondary fault", -1, 1 },
1438 { PCIEPINT_F
, "PCI core primary fault", -1, 1 },
1439 { UNXSPLCPLERR_F
, "PCI unexpected split completion error",
1444 static struct intr_info t5_pcie_intr_info
[] = {
1445 { MSTGRPPERR_F
, "Master Response Read Queue parity error",
1447 { MSTTIMEOUTPERR_F
, "Master Timeout FIFO parity error", -1, 1 },
1448 { MSIXSTIPERR_F
, "MSI-X STI SRAM parity error", -1, 1 },
1449 { MSIXADDRLPERR_F
, "MSI-X AddrL parity error", -1, 1 },
1450 { MSIXADDRHPERR_F
, "MSI-X AddrH parity error", -1, 1 },
1451 { MSIXDATAPERR_F
, "MSI-X data parity error", -1, 1 },
1452 { MSIXDIPERR_F
, "MSI-X DI parity error", -1, 1 },
1453 { PIOCPLGRPPERR_F
, "PCI PIO completion Group FIFO parity error",
1455 { PIOREQGRPPERR_F
, "PCI PIO request Group FIFO parity error",
1457 { TARTAGPERR_F
, "PCI PCI target tag FIFO parity error", -1, 1 },
1458 { MSTTAGQPERR_F
, "PCI master tag queue parity error", -1, 1 },
1459 { CREQPERR_F
, "PCI CMD channel request parity error", -1, 1 },
1460 { CRSPPERR_F
, "PCI CMD channel response parity error", -1, 1 },
1461 { DREQWRPERR_F
, "PCI DMA channel write request parity error",
1463 { DREQPERR_F
, "PCI DMA channel request parity error", -1, 1 },
1464 { DRSPPERR_F
, "PCI DMA channel response parity error", -1, 1 },
1465 { HREQWRPERR_F
, "PCI HMA channel count parity error", -1, 1 },
1466 { HREQPERR_F
, "PCI HMA channel request parity error", -1, 1 },
1467 { HRSPPERR_F
, "PCI HMA channel response parity error", -1, 1 },
1468 { CFGSNPPERR_F
, "PCI config snoop FIFO parity error", -1, 1 },
1469 { FIDPERR_F
, "PCI FID parity error", -1, 1 },
1470 { VFIDPERR_F
, "PCI INTx clear parity error", -1, 1 },
1471 { MAGRPPERR_F
, "PCI MA group FIFO parity error", -1, 1 },
1472 { PIOTAGPERR_F
, "PCI PIO tag parity error", -1, 1 },
1473 { IPRXHDRGRPPERR_F
, "PCI IP Rx header group parity error",
1475 { IPRXDATAGRPPERR_F
, "PCI IP Rx data group parity error",
1477 { RPLPERR_F
, "PCI IP replay buffer parity error", -1, 1 },
1478 { IPSOTPERR_F
, "PCI IP SOT buffer parity error", -1, 1 },
1479 { TRGT1GRPPERR_F
, "PCI TRGT1 group FIFOs parity error", -1, 1 },
1480 { READRSPERR_F
, "Outbound read error", -1, 0 },
1486 if (is_t4(adapter
->params
.chip
))
1487 fat
= t4_handle_intr_status(adapter
,
1488 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A
,
1490 t4_handle_intr_status(adapter
,
1491 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A
,
1492 pcie_port_intr_info
) +
1493 t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
1496 fat
= t4_handle_intr_status(adapter
, PCIE_INT_CAUSE_A
,
1500 t4_fatal_err(adapter
);
1504 * TP interrupt handler.
1506 static void tp_intr_handler(struct adapter
*adapter
)
1508 static const struct intr_info tp_intr_info
[] = {
1509 { 0x3fffffff, "TP parity error", -1, 1 },
1510 { FLMTXFLSTEMPTY_F
, "TP out of Tx pages", -1, 1 },
1514 if (t4_handle_intr_status(adapter
, TP_INT_CAUSE_A
, tp_intr_info
))
1515 t4_fatal_err(adapter
);
1519 * SGE interrupt handler.
1521 static void sge_intr_handler(struct adapter
*adapter
)
1525 static const struct intr_info sge_intr_info
[] = {
1526 { ERR_CPL_EXCEED_IQE_SIZE_F
,
1527 "SGE received CPL exceeding IQE size", -1, 1 },
1528 { ERR_INVALID_CIDX_INC_F
,
1529 "SGE GTS CIDX increment too large", -1, 0 },
1530 { ERR_CPL_OPCODE_0_F
, "SGE received 0-length CPL", -1, 0 },
1531 { DBFIFO_LP_INT_F
, NULL
, -1, 0, t4_db_full
},
1532 { DBFIFO_HP_INT_F
, NULL
, -1, 0, t4_db_full
},
1533 { ERR_DROPPED_DB_F
, NULL
, -1, 0, t4_db_dropped
},
1534 { ERR_DATA_CPL_ON_HIGH_QID1_F
| ERR_DATA_CPL_ON_HIGH_QID0_F
,
1535 "SGE IQID > 1023 received CPL for FL", -1, 0 },
1536 { ERR_BAD_DB_PIDX3_F
, "SGE DBP 3 pidx increment too large", -1,
1538 { ERR_BAD_DB_PIDX2_F
, "SGE DBP 2 pidx increment too large", -1,
1540 { ERR_BAD_DB_PIDX1_F
, "SGE DBP 1 pidx increment too large", -1,
1542 { ERR_BAD_DB_PIDX0_F
, "SGE DBP 0 pidx increment too large", -1,
1544 { ERR_ING_CTXT_PRIO_F
,
1545 "SGE too many priority ingress contexts", -1, 0 },
1546 { ERR_EGR_CTXT_PRIO_F
,
1547 "SGE too many priority egress contexts", -1, 0 },
1548 { INGRESS_SIZE_ERR_F
, "SGE illegal ingress QID", -1, 0 },
1549 { EGRESS_SIZE_ERR_F
, "SGE illegal egress QID", -1, 0 },
1553 v
= (u64
)t4_read_reg(adapter
, SGE_INT_CAUSE1_A
) |
1554 ((u64
)t4_read_reg(adapter
, SGE_INT_CAUSE2_A
) << 32);
1556 dev_alert(adapter
->pdev_dev
, "SGE parity error (%#llx)\n",
1557 (unsigned long long)v
);
1558 t4_write_reg(adapter
, SGE_INT_CAUSE1_A
, v
);
1559 t4_write_reg(adapter
, SGE_INT_CAUSE2_A
, v
>> 32);
1562 if (t4_handle_intr_status(adapter
, SGE_INT_CAUSE3_A
, sge_intr_info
) ||
1564 t4_fatal_err(adapter
);
1567 #define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
1568 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
1569 #define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
1570 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
1573 * CIM interrupt handler.
1575 static void cim_intr_handler(struct adapter
*adapter
)
1577 static const struct intr_info cim_intr_info
[] = {
1578 { PREFDROPINT_F
, "CIM control register prefetch drop", -1, 1 },
1579 { CIM_OBQ_INTR
, "CIM OBQ parity error", -1, 1 },
1580 { CIM_IBQ_INTR
, "CIM IBQ parity error", -1, 1 },
1581 { MBUPPARERR_F
, "CIM mailbox uP parity error", -1, 1 },
1582 { MBHOSTPARERR_F
, "CIM mailbox host parity error", -1, 1 },
1583 { TIEQINPARERRINT_F
, "CIM TIEQ outgoing parity error", -1, 1 },
1584 { TIEQOUTPARERRINT_F
, "CIM TIEQ incoming parity error", -1, 1 },
1587 static const struct intr_info cim_upintr_info
[] = {
1588 { RSVDSPACEINT_F
, "CIM reserved space access", -1, 1 },
1589 { ILLTRANSINT_F
, "CIM illegal transaction", -1, 1 },
1590 { ILLWRINT_F
, "CIM illegal write", -1, 1 },
1591 { ILLRDINT_F
, "CIM illegal read", -1, 1 },
1592 { ILLRDBEINT_F
, "CIM illegal read BE", -1, 1 },
1593 { ILLWRBEINT_F
, "CIM illegal write BE", -1, 1 },
1594 { SGLRDBOOTINT_F
, "CIM single read from boot space", -1, 1 },
1595 { SGLWRBOOTINT_F
, "CIM single write to boot space", -1, 1 },
1596 { BLKWRBOOTINT_F
, "CIM block write to boot space", -1, 1 },
1597 { SGLRDFLASHINT_F
, "CIM single read from flash space", -1, 1 },
1598 { SGLWRFLASHINT_F
, "CIM single write to flash space", -1, 1 },
1599 { BLKWRFLASHINT_F
, "CIM block write to flash space", -1, 1 },
1600 { SGLRDEEPROMINT_F
, "CIM single EEPROM read", -1, 1 },
1601 { SGLWREEPROMINT_F
, "CIM single EEPROM write", -1, 1 },
1602 { BLKRDEEPROMINT_F
, "CIM block EEPROM read", -1, 1 },
1603 { BLKWREEPROMINT_F
, "CIM block EEPROM write", -1, 1 },
1604 { SGLRDCTLINT_F
, "CIM single read from CTL space", -1, 1 },
1605 { SGLWRCTLINT_F
, "CIM single write to CTL space", -1, 1 },
1606 { BLKRDCTLINT_F
, "CIM block read from CTL space", -1, 1 },
1607 { BLKWRCTLINT_F
, "CIM block write to CTL space", -1, 1 },
1608 { SGLRDPLINT_F
, "CIM single read from PL space", -1, 1 },
1609 { SGLWRPLINT_F
, "CIM single write to PL space", -1, 1 },
1610 { BLKRDPLINT_F
, "CIM block read from PL space", -1, 1 },
1611 { BLKWRPLINT_F
, "CIM block write to PL space", -1, 1 },
1612 { REQOVRLOOKUPINT_F
, "CIM request FIFO overwrite", -1, 1 },
1613 { RSPOVRLOOKUPINT_F
, "CIM response FIFO overwrite", -1, 1 },
1614 { TIMEOUTINT_F
, "CIM PIF timeout", -1, 1 },
1615 { TIMEOUTMAINT_F
, "CIM PIF MA timeout", -1, 1 },
1621 if (t4_read_reg(adapter
, PCIE_FW_A
) & PCIE_FW_ERR_F
)
1622 t4_report_fw_error(adapter
);
1624 fat
= t4_handle_intr_status(adapter
, CIM_HOST_INT_CAUSE_A
,
1626 t4_handle_intr_status(adapter
, CIM_HOST_UPACC_INT_CAUSE_A
,
1629 t4_fatal_err(adapter
);
1633 * ULP RX interrupt handler.
1635 static void ulprx_intr_handler(struct adapter
*adapter
)
1637 static const struct intr_info ulprx_intr_info
[] = {
1638 { 0x1800000, "ULPRX context error", -1, 1 },
1639 { 0x7fffff, "ULPRX parity error", -1, 1 },
1643 if (t4_handle_intr_status(adapter
, ULP_RX_INT_CAUSE_A
, ulprx_intr_info
))
1644 t4_fatal_err(adapter
);
1648 * ULP TX interrupt handler.
1650 static void ulptx_intr_handler(struct adapter
*adapter
)
1652 static const struct intr_info ulptx_intr_info
[] = {
1653 { PBL_BOUND_ERR_CH3_F
, "ULPTX channel 3 PBL out of bounds", -1,
1655 { PBL_BOUND_ERR_CH2_F
, "ULPTX channel 2 PBL out of bounds", -1,
1657 { PBL_BOUND_ERR_CH1_F
, "ULPTX channel 1 PBL out of bounds", -1,
1659 { PBL_BOUND_ERR_CH0_F
, "ULPTX channel 0 PBL out of bounds", -1,
1661 { 0xfffffff, "ULPTX parity error", -1, 1 },
1665 if (t4_handle_intr_status(adapter
, ULP_TX_INT_CAUSE_A
, ulptx_intr_info
))
1666 t4_fatal_err(adapter
);
1670 * PM TX interrupt handler.
1672 static void pmtx_intr_handler(struct adapter
*adapter
)
1674 static const struct intr_info pmtx_intr_info
[] = {
1675 { PCMD_LEN_OVFL0_F
, "PMTX channel 0 pcmd too large", -1, 1 },
1676 { PCMD_LEN_OVFL1_F
, "PMTX channel 1 pcmd too large", -1, 1 },
1677 { PCMD_LEN_OVFL2_F
, "PMTX channel 2 pcmd too large", -1, 1 },
1678 { ZERO_C_CMD_ERROR_F
, "PMTX 0-length pcmd", -1, 1 },
1679 { PMTX_FRAMING_ERROR_F
, "PMTX framing error", -1, 1 },
1680 { OESPI_PAR_ERROR_F
, "PMTX oespi parity error", -1, 1 },
1681 { DB_OPTIONS_PAR_ERROR_F
, "PMTX db_options parity error",
1683 { ICSPI_PAR_ERROR_F
, "PMTX icspi parity error", -1, 1 },
1684 { PMTX_C_PCMD_PAR_ERROR_F
, "PMTX c_pcmd parity error", -1, 1},
1688 if (t4_handle_intr_status(adapter
, PM_TX_INT_CAUSE_A
, pmtx_intr_info
))
1689 t4_fatal_err(adapter
);
1693 * PM RX interrupt handler.
1695 static void pmrx_intr_handler(struct adapter
*adapter
)
1697 static const struct intr_info pmrx_intr_info
[] = {
1698 { ZERO_E_CMD_ERROR_F
, "PMRX 0-length pcmd", -1, 1 },
1699 { PMRX_FRAMING_ERROR_F
, "PMRX framing error", -1, 1 },
1700 { OCSPI_PAR_ERROR_F
, "PMRX ocspi parity error", -1, 1 },
1701 { DB_OPTIONS_PAR_ERROR_F
, "PMRX db_options parity error",
1703 { IESPI_PAR_ERROR_F
, "PMRX iespi parity error", -1, 1 },
1704 { PMRX_E_PCMD_PAR_ERROR_F
, "PMRX e_pcmd parity error", -1, 1},
1708 if (t4_handle_intr_status(adapter
, PM_RX_INT_CAUSE_A
, pmrx_intr_info
))
1709 t4_fatal_err(adapter
);
1713 * CPL switch interrupt handler.
1715 static void cplsw_intr_handler(struct adapter
*adapter
)
1717 static const struct intr_info cplsw_intr_info
[] = {
1718 { CIM_OP_MAP_PERR_F
, "CPLSW CIM op_map parity error", -1, 1 },
1719 { CIM_OVFL_ERROR_F
, "CPLSW CIM overflow", -1, 1 },
1720 { TP_FRAMING_ERROR_F
, "CPLSW TP framing error", -1, 1 },
1721 { SGE_FRAMING_ERROR_F
, "CPLSW SGE framing error", -1, 1 },
1722 { CIM_FRAMING_ERROR_F
, "CPLSW CIM framing error", -1, 1 },
1723 { ZERO_SWITCH_ERROR_F
, "CPLSW no-switch error", -1, 1 },
1727 if (t4_handle_intr_status(adapter
, CPL_INTR_CAUSE_A
, cplsw_intr_info
))
1728 t4_fatal_err(adapter
);
1732 * LE interrupt handler.
1734 static void le_intr_handler(struct adapter
*adap
)
1736 static const struct intr_info le_intr_info
[] = {
1737 { LIPMISS_F
, "LE LIP miss", -1, 0 },
1738 { LIP0_F
, "LE 0 LIP error", -1, 0 },
1739 { PARITYERR_F
, "LE parity error", -1, 1 },
1740 { UNKNOWNCMD_F
, "LE unknown command", -1, 1 },
1741 { REQQPARERR_F
, "LE request queue parity error", -1, 1 },
1745 if (t4_handle_intr_status(adap
, LE_DB_INT_CAUSE_A
, le_intr_info
))
1750 * MPS interrupt handler.
1752 static void mps_intr_handler(struct adapter
*adapter
)
1754 static const struct intr_info mps_rx_intr_info
[] = {
1755 { 0xffffff, "MPS Rx parity error", -1, 1 },
1758 static const struct intr_info mps_tx_intr_info
[] = {
1759 { TPFIFO_V(TPFIFO_M
), "MPS Tx TP FIFO parity error", -1, 1 },
1760 { NCSIFIFO_F
, "MPS Tx NC-SI FIFO parity error", -1, 1 },
1761 { TXDATAFIFO_V(TXDATAFIFO_M
), "MPS Tx data FIFO parity error",
1763 { TXDESCFIFO_V(TXDESCFIFO_M
), "MPS Tx desc FIFO parity error",
1765 { BUBBLE_F
, "MPS Tx underflow", -1, 1 },
1766 { SECNTERR_F
, "MPS Tx SOP/EOP error", -1, 1 },
1767 { FRMERR_F
, "MPS Tx framing error", -1, 1 },
1770 static const struct intr_info mps_trc_intr_info
[] = {
1771 { FILTMEM_V(FILTMEM_M
), "MPS TRC filter parity error", -1, 1 },
1772 { PKTFIFO_V(PKTFIFO_M
), "MPS TRC packet FIFO parity error",
1774 { MISCPERR_F
, "MPS TRC misc parity error", -1, 1 },
1777 static const struct intr_info mps_stat_sram_intr_info
[] = {
1778 { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
1781 static const struct intr_info mps_stat_tx_intr_info
[] = {
1782 { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
1785 static const struct intr_info mps_stat_rx_intr_info
[] = {
1786 { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
1789 static const struct intr_info mps_cls_intr_info
[] = {
1790 { MATCHSRAM_F
, "MPS match SRAM parity error", -1, 1 },
1791 { MATCHTCAM_F
, "MPS match TCAM parity error", -1, 1 },
1792 { HASHSRAM_F
, "MPS hash SRAM parity error", -1, 1 },
1798 fat
= t4_handle_intr_status(adapter
, MPS_RX_PERR_INT_CAUSE_A
,
1800 t4_handle_intr_status(adapter
, MPS_TX_INT_CAUSE_A
,
1802 t4_handle_intr_status(adapter
, MPS_TRC_INT_CAUSE_A
,
1803 mps_trc_intr_info
) +
1804 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_SRAM_A
,
1805 mps_stat_sram_intr_info
) +
1806 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A
,
1807 mps_stat_tx_intr_info
) +
1808 t4_handle_intr_status(adapter
, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A
,
1809 mps_stat_rx_intr_info
) +
1810 t4_handle_intr_status(adapter
, MPS_CLS_INT_CAUSE_A
,
1813 t4_write_reg(adapter
, MPS_INT_CAUSE_A
, 0);
1814 t4_read_reg(adapter
, MPS_INT_CAUSE_A
); /* flush */
1816 t4_fatal_err(adapter
);
1819 #define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
1823 * EDC/MC interrupt handler.
1825 static void mem_intr_handler(struct adapter
*adapter
, int idx
)
1827 static const char name
[4][7] = { "EDC0", "EDC1", "MC/MC0", "MC1" };
1829 unsigned int addr
, cnt_addr
, v
;
1831 if (idx
<= MEM_EDC1
) {
1832 addr
= EDC_REG(EDC_INT_CAUSE_A
, idx
);
1833 cnt_addr
= EDC_REG(EDC_ECC_STATUS_A
, idx
);
1834 } else if (idx
== MEM_MC
) {
1835 if (is_t4(adapter
->params
.chip
)) {
1836 addr
= MC_INT_CAUSE_A
;
1837 cnt_addr
= MC_ECC_STATUS_A
;
1839 addr
= MC_P_INT_CAUSE_A
;
1840 cnt_addr
= MC_P_ECC_STATUS_A
;
1843 addr
= MC_REG(MC_P_INT_CAUSE_A
, 1);
1844 cnt_addr
= MC_REG(MC_P_ECC_STATUS_A
, 1);
1847 v
= t4_read_reg(adapter
, addr
) & MEM_INT_MASK
;
1848 if (v
& PERR_INT_CAUSE_F
)
1849 dev_alert(adapter
->pdev_dev
, "%s FIFO parity error\n",
1851 if (v
& ECC_CE_INT_CAUSE_F
) {
1852 u32 cnt
= ECC_CECNT_G(t4_read_reg(adapter
, cnt_addr
));
1854 t4_write_reg(adapter
, cnt_addr
, ECC_CECNT_V(ECC_CECNT_M
));
1855 if (printk_ratelimit())
1856 dev_warn(adapter
->pdev_dev
,
1857 "%u %s correctable ECC data error%s\n",
1858 cnt
, name
[idx
], cnt
> 1 ? "s" : "");
1860 if (v
& ECC_UE_INT_CAUSE_F
)
1861 dev_alert(adapter
->pdev_dev
,
1862 "%s uncorrectable ECC data error\n", name
[idx
]);
1864 t4_write_reg(adapter
, addr
, v
);
1865 if (v
& (PERR_INT_CAUSE_F
| ECC_UE_INT_CAUSE_F
))
1866 t4_fatal_err(adapter
);
1870 * MA interrupt handler.
1872 static void ma_intr_handler(struct adapter
*adap
)
1874 u32 v
, status
= t4_read_reg(adap
, MA_INT_CAUSE_A
);
1876 if (status
& MEM_PERR_INT_CAUSE_F
) {
1877 dev_alert(adap
->pdev_dev
,
1878 "MA parity error, parity status %#x\n",
1879 t4_read_reg(adap
, MA_PARITY_ERROR_STATUS1_A
));
1880 if (is_t5(adap
->params
.chip
))
1881 dev_alert(adap
->pdev_dev
,
1882 "MA parity error, parity status %#x\n",
1884 MA_PARITY_ERROR_STATUS2_A
));
1886 if (status
& MEM_WRAP_INT_CAUSE_F
) {
1887 v
= t4_read_reg(adap
, MA_INT_WRAP_STATUS_A
);
1888 dev_alert(adap
->pdev_dev
, "MA address wrap-around error by "
1889 "client %u to address %#x\n",
1890 MEM_WRAP_CLIENT_NUM_G(v
),
1891 MEM_WRAP_ADDRESS_G(v
) << 4);
1893 t4_write_reg(adap
, MA_INT_CAUSE_A
, status
);
1898 * SMB interrupt handler.
1900 static void smb_intr_handler(struct adapter
*adap
)
1902 static const struct intr_info smb_intr_info
[] = {
1903 { MSTTXFIFOPARINT_F
, "SMB master Tx FIFO parity error", -1, 1 },
1904 { MSTRXFIFOPARINT_F
, "SMB master Rx FIFO parity error", -1, 1 },
1905 { SLVFIFOPARINT_F
, "SMB slave FIFO parity error", -1, 1 },
1909 if (t4_handle_intr_status(adap
, SMB_INT_CAUSE_A
, smb_intr_info
))
1914 * NC-SI interrupt handler.
1916 static void ncsi_intr_handler(struct adapter
*adap
)
1918 static const struct intr_info ncsi_intr_info
[] = {
1919 { CIM_DM_PRTY_ERR_F
, "NC-SI CIM parity error", -1, 1 },
1920 { MPS_DM_PRTY_ERR_F
, "NC-SI MPS parity error", -1, 1 },
1921 { TXFIFO_PRTY_ERR_F
, "NC-SI Tx FIFO parity error", -1, 1 },
1922 { RXFIFO_PRTY_ERR_F
, "NC-SI Rx FIFO parity error", -1, 1 },
1926 if (t4_handle_intr_status(adap
, NCSI_INT_CAUSE_A
, ncsi_intr_info
))
1931 * XGMAC interrupt handler.
1933 static void xgmac_intr_handler(struct adapter
*adap
, int port
)
1935 u32 v
, int_cause_reg
;
1937 if (is_t4(adap
->params
.chip
))
1938 int_cause_reg
= PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
);
1940 int_cause_reg
= T5_PORT_REG(port
, MAC_PORT_INT_CAUSE_A
);
1942 v
= t4_read_reg(adap
, int_cause_reg
);
1944 v
&= TXFIFO_PRTY_ERR_F
| RXFIFO_PRTY_ERR_F
;
1948 if (v
& TXFIFO_PRTY_ERR_F
)
1949 dev_alert(adap
->pdev_dev
, "XGMAC %d Tx FIFO parity error\n",
1951 if (v
& RXFIFO_PRTY_ERR_F
)
1952 dev_alert(adap
->pdev_dev
, "XGMAC %d Rx FIFO parity error\n",
1954 t4_write_reg(adap
, PORT_REG(port
, XGMAC_PORT_INT_CAUSE_A
), v
);
1959 * PL interrupt handler.
1961 static void pl_intr_handler(struct adapter
*adap
)
1963 static const struct intr_info pl_intr_info
[] = {
1964 { FATALPERR_F
, "T4 fatal parity error", -1, 1 },
1965 { PERRVFID_F
, "PL VFID_MAP parity error", -1, 1 },
1969 if (t4_handle_intr_status(adap
, PL_PL_INT_CAUSE_A
, pl_intr_info
))
1973 #define PF_INTR_MASK (PFSW_F)
1974 #define GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | EDC0_F | \
1975 EDC1_F | LE_F | TP_F | MA_F | PM_TX_F | PM_RX_F | ULP_RX_F | \
1976 CPL_SWITCH_F | SGE_F | ULP_TX_F)
1979 * t4_slow_intr_handler - control path interrupt handler
1980 * @adapter: the adapter
1982 * T4 interrupt handler for non-data global interrupt events, e.g., errors.
1983 * The designation 'slow' is because it involves register reads, while
1984 * data interrupts typically don't involve any MMIOs.
1986 int t4_slow_intr_handler(struct adapter
*adapter
)
1988 u32 cause
= t4_read_reg(adapter
, PL_INT_CAUSE_A
);
1990 if (!(cause
& GLBL_INTR_MASK
))
1993 cim_intr_handler(adapter
);
1995 mps_intr_handler(adapter
);
1997 ncsi_intr_handler(adapter
);
1999 pl_intr_handler(adapter
);
2001 smb_intr_handler(adapter
);
2002 if (cause
& XGMAC0_F
)
2003 xgmac_intr_handler(adapter
, 0);
2004 if (cause
& XGMAC1_F
)
2005 xgmac_intr_handler(adapter
, 1);
2006 if (cause
& XGMAC_KR0_F
)
2007 xgmac_intr_handler(adapter
, 2);
2008 if (cause
& XGMAC_KR1_F
)
2009 xgmac_intr_handler(adapter
, 3);
2011 pcie_intr_handler(adapter
);
2013 mem_intr_handler(adapter
, MEM_MC
);
2014 if (!is_t4(adapter
->params
.chip
) && (cause
& MC1_S
))
2015 mem_intr_handler(adapter
, MEM_MC1
);
2017 mem_intr_handler(adapter
, MEM_EDC0
);
2019 mem_intr_handler(adapter
, MEM_EDC1
);
2021 le_intr_handler(adapter
);
2023 tp_intr_handler(adapter
);
2025 ma_intr_handler(adapter
);
2026 if (cause
& PM_TX_F
)
2027 pmtx_intr_handler(adapter
);
2028 if (cause
& PM_RX_F
)
2029 pmrx_intr_handler(adapter
);
2030 if (cause
& ULP_RX_F
)
2031 ulprx_intr_handler(adapter
);
2032 if (cause
& CPL_SWITCH_F
)
2033 cplsw_intr_handler(adapter
);
2035 sge_intr_handler(adapter
);
2036 if (cause
& ULP_TX_F
)
2037 ulptx_intr_handler(adapter
);
2039 /* Clear the interrupts just processed for which we are the master. */
2040 t4_write_reg(adapter
, PL_INT_CAUSE_A
, cause
& GLBL_INTR_MASK
);
2041 (void)t4_read_reg(adapter
, PL_INT_CAUSE_A
); /* flush */
2046 * t4_intr_enable - enable interrupts
2047 * @adapter: the adapter whose interrupts should be enabled
2049 * Enable PF-specific interrupts for the calling function and the top-level
2050 * interrupt concentrator for global interrupts. Interrupts are already
2051 * enabled at each module, here we just enable the roots of the interrupt
2054 * Note: this function should be called only when the driver manages
2055 * non PF-specific interrupts from the various HW modules. Only one PCI
2056 * function at a time should be doing this.
2058 void t4_intr_enable(struct adapter
*adapter
)
2060 u32 pf
= SOURCEPF_G(t4_read_reg(adapter
, PL_WHOAMI_A
));
2062 t4_write_reg(adapter
, SGE_INT_ENABLE3_A
, ERR_CPL_EXCEED_IQE_SIZE_F
|
2063 ERR_INVALID_CIDX_INC_F
| ERR_CPL_OPCODE_0_F
|
2064 ERR_DROPPED_DB_F
| ERR_DATA_CPL_ON_HIGH_QID1_F
|
2065 ERR_DATA_CPL_ON_HIGH_QID0_F
| ERR_BAD_DB_PIDX3_F
|
2066 ERR_BAD_DB_PIDX2_F
| ERR_BAD_DB_PIDX1_F
|
2067 ERR_BAD_DB_PIDX0_F
| ERR_ING_CTXT_PRIO_F
|
2068 ERR_EGR_CTXT_PRIO_F
| INGRESS_SIZE_ERR_F
|
2069 DBFIFO_HP_INT_F
| DBFIFO_LP_INT_F
|
2071 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), PF_INTR_MASK
);
2072 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 0, 1 << pf
);
2076 * t4_intr_disable - disable interrupts
2077 * @adapter: the adapter whose interrupts should be disabled
2079 * Disable interrupts. We only disable the top-level interrupt
2080 * concentrators. The caller must be a PCI function managing global
2083 void t4_intr_disable(struct adapter
*adapter
)
2085 u32 pf
= SOURCEPF_G(t4_read_reg(adapter
, PL_WHOAMI_A
));
2087 t4_write_reg(adapter
, MYPF_REG(PL_PF_INT_ENABLE_A
), 0);
2088 t4_set_reg_field(adapter
, PL_INT_MAP0_A
, 1 << pf
, 0);
2092 * hash_mac_addr - return the hash value of a MAC address
2093 * @addr: the 48-bit Ethernet MAC address
2095 * Hashes a MAC address according to the hash function used by HW inexact
2096 * (hash) address matching.
2098 static int hash_mac_addr(const u8
*addr
)
2100 u32 a
= ((u32
)addr
[0] << 16) | ((u32
)addr
[1] << 8) | addr
[2];
2101 u32 b
= ((u32
)addr
[3] << 16) | ((u32
)addr
[4] << 8) | addr
[5];
2109 * t4_config_rss_range - configure a portion of the RSS mapping table
2110 * @adapter: the adapter
2111 * @mbox: mbox to use for the FW command
2112 * @viid: virtual interface whose RSS subtable is to be written
2113 * @start: start entry in the table to write
2114 * @n: how many table entries to write
2115 * @rspq: values for the response queue lookup table
2116 * @nrspq: number of values in @rspq
2118 * Programs the selected part of the VI's RSS mapping table with the
2119 * provided values. If @nrspq < @n the supplied values are used repeatedly
2120 * until the full table range is populated.
2122 * The caller must ensure the values in @rspq are in the range allowed for
2125 int t4_config_rss_range(struct adapter
*adapter
, int mbox
, unsigned int viid
,
2126 int start
, int n
, const u16
*rspq
, unsigned int nrspq
)
2129 const u16
*rsp
= rspq
;
2130 const u16
*rsp_end
= rspq
+ nrspq
;
2131 struct fw_rss_ind_tbl_cmd cmd
;
2133 memset(&cmd
, 0, sizeof(cmd
));
2134 cmd
.op_to_viid
= htonl(FW_CMD_OP_V(FW_RSS_IND_TBL_CMD
) |
2135 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
2136 FW_RSS_IND_TBL_CMD_VIID_V(viid
));
2137 cmd
.retval_len16
= htonl(FW_LEN16(cmd
));
2139 /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
2141 int nq
= min(n
, 32);
2142 __be32
*qp
= &cmd
.iq0_to_iq2
;
2144 cmd
.niqid
= htons(nq
);
2145 cmd
.startidx
= htons(start
);
2153 v
= FW_RSS_IND_TBL_CMD_IQ0_V(*rsp
);
2154 if (++rsp
>= rsp_end
)
2156 v
|= FW_RSS_IND_TBL_CMD_IQ1_V(*rsp
);
2157 if (++rsp
>= rsp_end
)
2159 v
|= FW_RSS_IND_TBL_CMD_IQ2_V(*rsp
);
2160 if (++rsp
>= rsp_end
)
2167 ret
= t4_wr_mbox(adapter
, mbox
, &cmd
, sizeof(cmd
), NULL
);
2175 * t4_config_glbl_rss - configure the global RSS mode
2176 * @adapter: the adapter
2177 * @mbox: mbox to use for the FW command
2178 * @mode: global RSS mode
2179 * @flags: mode-specific flags
2181 * Sets the global RSS mode.
2183 int t4_config_glbl_rss(struct adapter
*adapter
, int mbox
, unsigned int mode
,
2186 struct fw_rss_glb_config_cmd c
;
2188 memset(&c
, 0, sizeof(c
));
2189 c
.op_to_write
= htonl(FW_CMD_OP_V(FW_RSS_GLB_CONFIG_CMD
) |
2190 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
);
2191 c
.retval_len16
= htonl(FW_LEN16(c
));
2192 if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL
) {
2193 c
.u
.manual
.mode_pkd
= htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
2194 } else if (mode
== FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL
) {
2195 c
.u
.basicvirtual
.mode_pkd
=
2196 htonl(FW_RSS_GLB_CONFIG_CMD_MODE_V(mode
));
2197 c
.u
.basicvirtual
.synmapen_to_hashtoeplitz
= htonl(flags
);
2200 return t4_wr_mbox(adapter
, mbox
, &c
, sizeof(c
), NULL
);
2204 * t4_tp_get_tcp_stats - read TP's TCP MIB counters
2205 * @adap: the adapter
2206 * @v4: holds the TCP/IP counter values
2207 * @v6: holds the TCP/IPv6 counter values
2209 * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
2210 * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
2212 void t4_tp_get_tcp_stats(struct adapter
*adap
, struct tp_tcp_stats
*v4
,
2213 struct tp_tcp_stats
*v6
)
2215 u32 val
[TP_MIB_TCP_RXT_SEG_LO_A
- TP_MIB_TCP_OUT_RST_A
+ 1];
2217 #define STAT_IDX(x) ((TP_MIB_TCP_##x##_A) - TP_MIB_TCP_OUT_RST_A)
2218 #define STAT(x) val[STAT_IDX(x)]
2219 #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
2222 t4_read_indirect(adap
, TP_MIB_INDEX_A
, TP_MIB_DATA_A
, val
,
2223 ARRAY_SIZE(val
), TP_MIB_TCP_OUT_RST_A
);
2224 v4
->tcpOutRsts
= STAT(OUT_RST
);
2225 v4
->tcpInSegs
= STAT64(IN_SEG
);
2226 v4
->tcpOutSegs
= STAT64(OUT_SEG
);
2227 v4
->tcpRetransSegs
= STAT64(RXT_SEG
);
2230 t4_read_indirect(adap
, TP_MIB_INDEX_A
, TP_MIB_DATA_A
, val
,
2231 ARRAY_SIZE(val
), TP_MIB_TCP_V6OUT_RST_A
);
2232 v6
->tcpOutRsts
= STAT(OUT_RST
);
2233 v6
->tcpInSegs
= STAT64(IN_SEG
);
2234 v6
->tcpOutSegs
= STAT64(OUT_SEG
);
2235 v6
->tcpRetransSegs
= STAT64(RXT_SEG
);
2243 * t4_read_mtu_tbl - returns the values in the HW path MTU table
2244 * @adap: the adapter
2245 * @mtus: where to store the MTU values
2246 * @mtu_log: where to store the MTU base-2 log (may be %NULL)
2248 * Reads the HW path MTU table.
2250 void t4_read_mtu_tbl(struct adapter
*adap
, u16
*mtus
, u8
*mtu_log
)
2255 for (i
= 0; i
< NMTUS
; ++i
) {
2256 t4_write_reg(adap
, TP_MTU_TABLE_A
,
2257 MTUINDEX_V(0xff) | MTUVALUE_V(i
));
2258 v
= t4_read_reg(adap
, TP_MTU_TABLE_A
);
2259 mtus
[i
] = MTUVALUE_G(v
);
2261 mtu_log
[i
] = MTUWIDTH_G(v
);
2266 * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
2267 * @adap: the adapter
2268 * @addr: the indirect TP register address
2269 * @mask: specifies the field within the register to modify
2270 * @val: new value for the field
2272 * Sets a field of an indirect TP register to the given value.
2274 void t4_tp_wr_bits_indirect(struct adapter
*adap
, unsigned int addr
,
2275 unsigned int mask
, unsigned int val
)
2277 t4_write_reg(adap
, TP_PIO_ADDR_A
, addr
);
2278 val
|= t4_read_reg(adap
, TP_PIO_DATA_A
) & ~mask
;
2279 t4_write_reg(adap
, TP_PIO_DATA_A
, val
);
2283 * init_cong_ctrl - initialize congestion control parameters
2284 * @a: the alpha values for congestion control
2285 * @b: the beta values for congestion control
2287 * Initialize the congestion control parameters.
2289 static void init_cong_ctrl(unsigned short *a
, unsigned short *b
)
2291 a
[0] = a
[1] = a
[2] = a
[3] = a
[4] = a
[5] = a
[6] = a
[7] = a
[8] = 1;
2316 b
[0] = b
[1] = b
[2] = b
[3] = b
[4] = b
[5] = b
[6] = b
[7] = b
[8] = 0;
2319 b
[13] = b
[14] = b
[15] = b
[16] = 3;
2320 b
[17] = b
[18] = b
[19] = b
[20] = b
[21] = 4;
2321 b
[22] = b
[23] = b
[24] = b
[25] = b
[26] = b
[27] = 5;
2326 /* The minimum additive increment value for the congestion control table */
2327 #define CC_MIN_INCR 2U
2330 * t4_load_mtus - write the MTU and congestion control HW tables
2331 * @adap: the adapter
2332 * @mtus: the values for the MTU table
2333 * @alpha: the values for the congestion control alpha parameter
2334 * @beta: the values for the congestion control beta parameter
2336 * Write the HW MTU table with the supplied MTUs and the high-speed
2337 * congestion control table with the supplied alpha, beta, and MTUs.
2338 * We write the two tables together because the additive increments
2339 * depend on the MTUs.
2341 void t4_load_mtus(struct adapter
*adap
, const unsigned short *mtus
,
2342 const unsigned short *alpha
, const unsigned short *beta
)
2344 static const unsigned int avg_pkts
[NCCTRL_WIN
] = {
2345 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
2346 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
2347 28672, 40960, 57344, 81920, 114688, 163840, 229376
2352 for (i
= 0; i
< NMTUS
; ++i
) {
2353 unsigned int mtu
= mtus
[i
];
2354 unsigned int log2
= fls(mtu
);
2356 if (!(mtu
& ((1 << log2
) >> 2))) /* round */
2358 t4_write_reg(adap
, TP_MTU_TABLE_A
, MTUINDEX_V(i
) |
2359 MTUWIDTH_V(log2
) | MTUVALUE_V(mtu
));
2361 for (w
= 0; w
< NCCTRL_WIN
; ++w
) {
2364 inc
= max(((mtu
- 40) * alpha
[w
]) / avg_pkts
[w
],
2367 t4_write_reg(adap
, TP_CCTRL_TABLE_A
, (i
<< 21) |
2368 (w
<< 16) | (beta
[w
] << 13) | inc
);
2374 * get_mps_bg_map - return the buffer groups associated with a port
2375 * @adap: the adapter
2376 * @idx: the port index
2378 * Returns a bitmap indicating which MPS buffer groups are associated
2379 * with the given port. Bit i is set if buffer group i is used by the
2382 static unsigned int get_mps_bg_map(struct adapter
*adap
, int idx
)
2384 u32 n
= NUMPORTS_G(t4_read_reg(adap
, MPS_CMN_CTL_A
));
2387 return idx
== 0 ? 0xf : 0;
2389 return idx
< 2 ? (3 << (2 * idx
)) : 0;
2394 * t4_get_port_type_description - return Port Type string description
2395 * @port_type: firmware Port Type enumeration
2397 const char *t4_get_port_type_description(enum fw_port_type port_type
)
2399 static const char *const port_type_description
[] = {
2418 if (port_type
< ARRAY_SIZE(port_type_description
))
2419 return port_type_description
[port_type
];
2424 * t4_get_port_stats - collect port statistics
2425 * @adap: the adapter
2426 * @idx: the port index
2427 * @p: the stats structure to fill
2429 * Collect statistics related to the given port from HW.
2431 void t4_get_port_stats(struct adapter
*adap
, int idx
, struct port_stats
*p
)
2433 u32 bgmap
= get_mps_bg_map(adap
, idx
);
2435 #define GET_STAT(name) \
2436 t4_read_reg64(adap, \
2437 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \
2438 T5_PORT_REG(idx, MPS_PORT_STAT_##name##_L)))
2439 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
2441 p
->tx_octets
= GET_STAT(TX_PORT_BYTES
);
2442 p
->tx_frames
= GET_STAT(TX_PORT_FRAMES
);
2443 p
->tx_bcast_frames
= GET_STAT(TX_PORT_BCAST
);
2444 p
->tx_mcast_frames
= GET_STAT(TX_PORT_MCAST
);
2445 p
->tx_ucast_frames
= GET_STAT(TX_PORT_UCAST
);
2446 p
->tx_error_frames
= GET_STAT(TX_PORT_ERROR
);
2447 p
->tx_frames_64
= GET_STAT(TX_PORT_64B
);
2448 p
->tx_frames_65_127
= GET_STAT(TX_PORT_65B_127B
);
2449 p
->tx_frames_128_255
= GET_STAT(TX_PORT_128B_255B
);
2450 p
->tx_frames_256_511
= GET_STAT(TX_PORT_256B_511B
);
2451 p
->tx_frames_512_1023
= GET_STAT(TX_PORT_512B_1023B
);
2452 p
->tx_frames_1024_1518
= GET_STAT(TX_PORT_1024B_1518B
);
2453 p
->tx_frames_1519_max
= GET_STAT(TX_PORT_1519B_MAX
);
2454 p
->tx_drop
= GET_STAT(TX_PORT_DROP
);
2455 p
->tx_pause
= GET_STAT(TX_PORT_PAUSE
);
2456 p
->tx_ppp0
= GET_STAT(TX_PORT_PPP0
);
2457 p
->tx_ppp1
= GET_STAT(TX_PORT_PPP1
);
2458 p
->tx_ppp2
= GET_STAT(TX_PORT_PPP2
);
2459 p
->tx_ppp3
= GET_STAT(TX_PORT_PPP3
);
2460 p
->tx_ppp4
= GET_STAT(TX_PORT_PPP4
);
2461 p
->tx_ppp5
= GET_STAT(TX_PORT_PPP5
);
2462 p
->tx_ppp6
= GET_STAT(TX_PORT_PPP6
);
2463 p
->tx_ppp7
= GET_STAT(TX_PORT_PPP7
);
2465 p
->rx_octets
= GET_STAT(RX_PORT_BYTES
);
2466 p
->rx_frames
= GET_STAT(RX_PORT_FRAMES
);
2467 p
->rx_bcast_frames
= GET_STAT(RX_PORT_BCAST
);
2468 p
->rx_mcast_frames
= GET_STAT(RX_PORT_MCAST
);
2469 p
->rx_ucast_frames
= GET_STAT(RX_PORT_UCAST
);
2470 p
->rx_too_long
= GET_STAT(RX_PORT_MTU_ERROR
);
2471 p
->rx_jabber
= GET_STAT(RX_PORT_MTU_CRC_ERROR
);
2472 p
->rx_fcs_err
= GET_STAT(RX_PORT_CRC_ERROR
);
2473 p
->rx_len_err
= GET_STAT(RX_PORT_LEN_ERROR
);
2474 p
->rx_symbol_err
= GET_STAT(RX_PORT_SYM_ERROR
);
2475 p
->rx_runt
= GET_STAT(RX_PORT_LESS_64B
);
2476 p
->rx_frames_64
= GET_STAT(RX_PORT_64B
);
2477 p
->rx_frames_65_127
= GET_STAT(RX_PORT_65B_127B
);
2478 p
->rx_frames_128_255
= GET_STAT(RX_PORT_128B_255B
);
2479 p
->rx_frames_256_511
= GET_STAT(RX_PORT_256B_511B
);
2480 p
->rx_frames_512_1023
= GET_STAT(RX_PORT_512B_1023B
);
2481 p
->rx_frames_1024_1518
= GET_STAT(RX_PORT_1024B_1518B
);
2482 p
->rx_frames_1519_max
= GET_STAT(RX_PORT_1519B_MAX
);
2483 p
->rx_pause
= GET_STAT(RX_PORT_PAUSE
);
2484 p
->rx_ppp0
= GET_STAT(RX_PORT_PPP0
);
2485 p
->rx_ppp1
= GET_STAT(RX_PORT_PPP1
);
2486 p
->rx_ppp2
= GET_STAT(RX_PORT_PPP2
);
2487 p
->rx_ppp3
= GET_STAT(RX_PORT_PPP3
);
2488 p
->rx_ppp4
= GET_STAT(RX_PORT_PPP4
);
2489 p
->rx_ppp5
= GET_STAT(RX_PORT_PPP5
);
2490 p
->rx_ppp6
= GET_STAT(RX_PORT_PPP6
);
2491 p
->rx_ppp7
= GET_STAT(RX_PORT_PPP7
);
2493 p
->rx_ovflow0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME
) : 0;
2494 p
->rx_ovflow1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME
) : 0;
2495 p
->rx_ovflow2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME
) : 0;
2496 p
->rx_ovflow3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME
) : 0;
2497 p
->rx_trunc0
= (bgmap
& 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME
) : 0;
2498 p
->rx_trunc1
= (bgmap
& 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME
) : 0;
2499 p
->rx_trunc2
= (bgmap
& 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME
) : 0;
2500 p
->rx_trunc3
= (bgmap
& 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME
) : 0;
2507 * t4_wol_magic_enable - enable/disable magic packet WoL
2508 * @adap: the adapter
2509 * @port: the physical port index
2510 * @addr: MAC address expected in magic packets, %NULL to disable
2512 * Enables/disables magic packet wake-on-LAN for the selected port.
2514 void t4_wol_magic_enable(struct adapter
*adap
, unsigned int port
,
2517 u32 mag_id_reg_l
, mag_id_reg_h
, port_cfg_reg
;
2519 if (is_t4(adap
->params
.chip
)) {
2520 mag_id_reg_l
= PORT_REG(port
, XGMAC_PORT_MAGIC_MACID_LO
);
2521 mag_id_reg_h
= PORT_REG(port
, XGMAC_PORT_MAGIC_MACID_HI
);
2522 port_cfg_reg
= PORT_REG(port
, XGMAC_PORT_CFG2_A
);
2524 mag_id_reg_l
= T5_PORT_REG(port
, MAC_PORT_MAGIC_MACID_LO
);
2525 mag_id_reg_h
= T5_PORT_REG(port
, MAC_PORT_MAGIC_MACID_HI
);
2526 port_cfg_reg
= T5_PORT_REG(port
, MAC_PORT_CFG2_A
);
2530 t4_write_reg(adap
, mag_id_reg_l
,
2531 (addr
[2] << 24) | (addr
[3] << 16) |
2532 (addr
[4] << 8) | addr
[5]);
2533 t4_write_reg(adap
, mag_id_reg_h
,
2534 (addr
[0] << 8) | addr
[1]);
2536 t4_set_reg_field(adap
, port_cfg_reg
, MAGICEN_F
,
2537 addr
? MAGICEN_F
: 0);
2541 * t4_wol_pat_enable - enable/disable pattern-based WoL
2542 * @adap: the adapter
2543 * @port: the physical port index
2544 * @map: bitmap of which HW pattern filters to set
2545 * @mask0: byte mask for bytes 0-63 of a packet
2546 * @mask1: byte mask for bytes 64-127 of a packet
2547 * @crc: Ethernet CRC for selected bytes
2548 * @enable: enable/disable switch
2550 * Sets the pattern filters indicated in @map to mask out the bytes
2551 * specified in @mask0/@mask1 in received packets and compare the CRC of
2552 * the resulting packet against @crc. If @enable is %true pattern-based
2553 * WoL is enabled, otherwise disabled.
2555 int t4_wol_pat_enable(struct adapter
*adap
, unsigned int port
, unsigned int map
,
2556 u64 mask0
, u64 mask1
, unsigned int crc
, bool enable
)
2561 if (is_t4(adap
->params
.chip
))
2562 port_cfg_reg
= PORT_REG(port
, XGMAC_PORT_CFG2_A
);
2564 port_cfg_reg
= T5_PORT_REG(port
, MAC_PORT_CFG2_A
);
2567 t4_set_reg_field(adap
, port_cfg_reg
, PATEN_F
, 0);
2573 #define EPIO_REG(name) \
2574 (is_t4(adap->params.chip) ? \
2575 PORT_REG(port, XGMAC_PORT_EPIO_##name##_A) : \
2576 T5_PORT_REG(port, MAC_PORT_EPIO_##name##_A))
2578 t4_write_reg(adap
, EPIO_REG(DATA1
), mask0
>> 32);
2579 t4_write_reg(adap
, EPIO_REG(DATA2
), mask1
);
2580 t4_write_reg(adap
, EPIO_REG(DATA3
), mask1
>> 32);
2582 for (i
= 0; i
< NWOL_PAT
; i
++, map
>>= 1) {
2586 /* write byte masks */
2587 t4_write_reg(adap
, EPIO_REG(DATA0
), mask0
);
2588 t4_write_reg(adap
, EPIO_REG(OP
), ADDRESS_V(i
) | EPIOWR_F
);
2589 t4_read_reg(adap
, EPIO_REG(OP
)); /* flush */
2590 if (t4_read_reg(adap
, EPIO_REG(OP
)) & SF_BUSY_F
)
2594 t4_write_reg(adap
, EPIO_REG(DATA0
), crc
);
2595 t4_write_reg(adap
, EPIO_REG(OP
), ADDRESS_V(i
+ 32) | EPIOWR_F
);
2596 t4_read_reg(adap
, EPIO_REG(OP
)); /* flush */
2597 if (t4_read_reg(adap
, EPIO_REG(OP
)) & SF_BUSY_F
)
2602 t4_set_reg_field(adap
, PORT_REG(port
, XGMAC_PORT_CFG2_A
), 0, PATEN_F
);
2606 /* t4_mk_filtdelwr - create a delete filter WR
2607 * @ftid: the filter ID
2608 * @wr: the filter work request to populate
2609 * @qid: ingress queue to receive the delete notification
2611 * Creates a filter work request to delete the supplied filter. If @qid is
2612 * negative the delete notification is suppressed.
2614 void t4_mk_filtdelwr(unsigned int ftid
, struct fw_filter_wr
*wr
, int qid
)
2616 memset(wr
, 0, sizeof(*wr
));
2617 wr
->op_pkd
= htonl(FW_WR_OP_V(FW_FILTER_WR
));
2618 wr
->len16_pkd
= htonl(FW_WR_LEN16_V(sizeof(*wr
) / 16));
2619 wr
->tid_to_iq
= htonl(FW_FILTER_WR_TID_V(ftid
) |
2620 FW_FILTER_WR_NOREPLY_V(qid
< 0));
2621 wr
->del_filter_to_l2tix
= htonl(FW_FILTER_WR_DEL_FILTER_F
);
2623 wr
->rx_chan_rx_rpl_iq
= htons(FW_FILTER_WR_RX_RPL_IQ_V(qid
));
2626 #define INIT_CMD(var, cmd, rd_wr) do { \
2627 (var).op_to_write = htonl(FW_CMD_OP_V(FW_##cmd##_CMD) | \
2628 FW_CMD_REQUEST_F | FW_CMD_##rd_wr##_F); \
2629 (var).retval_len16 = htonl(FW_LEN16(var)); \
2632 int t4_fwaddrspace_write(struct adapter
*adap
, unsigned int mbox
,
2635 struct fw_ldst_cmd c
;
2637 memset(&c
, 0, sizeof(c
));
2638 c
.op_to_addrspace
= htonl(FW_CMD_OP_V(FW_LDST_CMD
) | FW_CMD_REQUEST_F
|
2640 FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FIRMWARE
));
2641 c
.cycles_to_len16
= htonl(FW_LEN16(c
));
2642 c
.u
.addrval
.addr
= htonl(addr
);
2643 c
.u
.addrval
.val
= htonl(val
);
2645 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
2649 * t4_mdio_rd - read a PHY register through MDIO
2650 * @adap: the adapter
2651 * @mbox: mailbox to use for the FW command
2652 * @phy_addr: the PHY address
2653 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2654 * @reg: the register to read
2655 * @valp: where to store the value
2657 * Issues a FW command through the given mailbox to read a PHY register.
2659 int t4_mdio_rd(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
2660 unsigned int mmd
, unsigned int reg
, u16
*valp
)
2663 struct fw_ldst_cmd c
;
2665 memset(&c
, 0, sizeof(c
));
2666 c
.op_to_addrspace
= htonl(FW_CMD_OP_V(FW_LDST_CMD
) | FW_CMD_REQUEST_F
|
2667 FW_CMD_READ_F
| FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
));
2668 c
.cycles_to_len16
= htonl(FW_LEN16(c
));
2669 c
.u
.mdio
.paddr_mmd
= htons(FW_LDST_CMD_PADDR_V(phy_addr
) |
2670 FW_LDST_CMD_MMD_V(mmd
));
2671 c
.u
.mdio
.raddr
= htons(reg
);
2673 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
2675 *valp
= ntohs(c
.u
.mdio
.rval
);
2680 * t4_mdio_wr - write a PHY register through MDIO
2681 * @adap: the adapter
2682 * @mbox: mailbox to use for the FW command
2683 * @phy_addr: the PHY address
2684 * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
2685 * @reg: the register to write
2686 * @valp: value to write
2688 * Issues a FW command through the given mailbox to write a PHY register.
2690 int t4_mdio_wr(struct adapter
*adap
, unsigned int mbox
, unsigned int phy_addr
,
2691 unsigned int mmd
, unsigned int reg
, u16 val
)
2693 struct fw_ldst_cmd c
;
2695 memset(&c
, 0, sizeof(c
));
2696 c
.op_to_addrspace
= htonl(FW_CMD_OP_V(FW_LDST_CMD
) | FW_CMD_REQUEST_F
|
2697 FW_CMD_WRITE_F
| FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MDIO
));
2698 c
.cycles_to_len16
= htonl(FW_LEN16(c
));
2699 c
.u
.mdio
.paddr_mmd
= htons(FW_LDST_CMD_PADDR_V(phy_addr
) |
2700 FW_LDST_CMD_MMD_V(mmd
));
2701 c
.u
.mdio
.raddr
= htons(reg
);
2702 c
.u
.mdio
.rval
= htons(val
);
2704 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
2708 * t4_sge_decode_idma_state - decode the idma state
2709 * @adap: the adapter
2710 * @state: the state idma is stuck in
2712 void t4_sge_decode_idma_state(struct adapter
*adapter
, int state
)
2714 static const char * const t4_decode
[] = {
2716 "IDMA_PUSH_MORE_CPL_FIFO",
2717 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
2719 "IDMA_PHYSADDR_SEND_PCIEHDR",
2720 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
2721 "IDMA_PHYSADDR_SEND_PAYLOAD",
2722 "IDMA_SEND_FIFO_TO_IMSG",
2723 "IDMA_FL_REQ_DATA_FL_PREP",
2724 "IDMA_FL_REQ_DATA_FL",
2726 "IDMA_FL_H_REQ_HEADER_FL",
2727 "IDMA_FL_H_SEND_PCIEHDR",
2728 "IDMA_FL_H_PUSH_CPL_FIFO",
2729 "IDMA_FL_H_SEND_CPL",
2730 "IDMA_FL_H_SEND_IP_HDR_FIRST",
2731 "IDMA_FL_H_SEND_IP_HDR",
2732 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
2733 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
2734 "IDMA_FL_H_SEND_IP_HDR_PADDING",
2735 "IDMA_FL_D_SEND_PCIEHDR",
2736 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
2737 "IDMA_FL_D_REQ_NEXT_DATA_FL",
2738 "IDMA_FL_SEND_PCIEHDR",
2739 "IDMA_FL_PUSH_CPL_FIFO",
2741 "IDMA_FL_SEND_PAYLOAD_FIRST",
2742 "IDMA_FL_SEND_PAYLOAD",
2743 "IDMA_FL_REQ_NEXT_DATA_FL",
2744 "IDMA_FL_SEND_NEXT_PCIEHDR",
2745 "IDMA_FL_SEND_PADDING",
2746 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
2747 "IDMA_FL_SEND_FIFO_TO_IMSG",
2748 "IDMA_FL_REQ_DATAFL_DONE",
2749 "IDMA_FL_REQ_HEADERFL_DONE",
2751 static const char * const t5_decode
[] = {
2754 "IDMA_PUSH_MORE_CPL_FIFO",
2755 "IDMA_PUSH_CPL_MSG_HEADER_TO_FIFO",
2756 "IDMA_SGEFLRFLUSH_SEND_PCIEHDR",
2757 "IDMA_PHYSADDR_SEND_PCIEHDR",
2758 "IDMA_PHYSADDR_SEND_PAYLOAD_FIRST",
2759 "IDMA_PHYSADDR_SEND_PAYLOAD",
2760 "IDMA_SEND_FIFO_TO_IMSG",
2761 "IDMA_FL_REQ_DATA_FL",
2763 "IDMA_FL_DROP_SEND_INC",
2764 "IDMA_FL_H_REQ_HEADER_FL",
2765 "IDMA_FL_H_SEND_PCIEHDR",
2766 "IDMA_FL_H_PUSH_CPL_FIFO",
2767 "IDMA_FL_H_SEND_CPL",
2768 "IDMA_FL_H_SEND_IP_HDR_FIRST",
2769 "IDMA_FL_H_SEND_IP_HDR",
2770 "IDMA_FL_H_REQ_NEXT_HEADER_FL",
2771 "IDMA_FL_H_SEND_NEXT_PCIEHDR",
2772 "IDMA_FL_H_SEND_IP_HDR_PADDING",
2773 "IDMA_FL_D_SEND_PCIEHDR",
2774 "IDMA_FL_D_SEND_CPL_AND_IP_HDR",
2775 "IDMA_FL_D_REQ_NEXT_DATA_FL",
2776 "IDMA_FL_SEND_PCIEHDR",
2777 "IDMA_FL_PUSH_CPL_FIFO",
2779 "IDMA_FL_SEND_PAYLOAD_FIRST",
2780 "IDMA_FL_SEND_PAYLOAD",
2781 "IDMA_FL_REQ_NEXT_DATA_FL",
2782 "IDMA_FL_SEND_NEXT_PCIEHDR",
2783 "IDMA_FL_SEND_PADDING",
2784 "IDMA_FL_SEND_COMPLETION_TO_IMSG",
2786 static const u32 sge_regs
[] = {
2787 SGE_DEBUG_DATA_LOW_INDEX_2_A
,
2788 SGE_DEBUG_DATA_LOW_INDEX_3_A
,
2789 SGE_DEBUG_DATA_HIGH_INDEX_10_A
,
2791 const char **sge_idma_decode
;
2792 int sge_idma_decode_nstates
;
2795 if (is_t4(adapter
->params
.chip
)) {
2796 sge_idma_decode
= (const char **)t4_decode
;
2797 sge_idma_decode_nstates
= ARRAY_SIZE(t4_decode
);
2799 sge_idma_decode
= (const char **)t5_decode
;
2800 sge_idma_decode_nstates
= ARRAY_SIZE(t5_decode
);
2803 if (state
< sge_idma_decode_nstates
)
2804 CH_WARN(adapter
, "idma state %s\n", sge_idma_decode
[state
]);
2806 CH_WARN(adapter
, "idma state %d unknown\n", state
);
2808 for (i
= 0; i
< ARRAY_SIZE(sge_regs
); i
++)
2809 CH_WARN(adapter
, "SGE register %#x value %#x\n",
2810 sge_regs
[i
], t4_read_reg(adapter
, sge_regs
[i
]));
2814 * t4_fw_hello - establish communication with FW
2815 * @adap: the adapter
2816 * @mbox: mailbox to use for the FW command
2817 * @evt_mbox: mailbox to receive async FW events
2818 * @master: specifies the caller's willingness to be the device master
2819 * @state: returns the current device state (if non-NULL)
2821 * Issues a command to establish communication with FW. Returns either
2822 * an error (negative integer) or the mailbox of the Master PF.
2824 int t4_fw_hello(struct adapter
*adap
, unsigned int mbox
, unsigned int evt_mbox
,
2825 enum dev_master master
, enum dev_state
*state
)
2828 struct fw_hello_cmd c
;
2830 unsigned int master_mbox
;
2831 int retries
= FW_CMD_HELLO_RETRIES
;
2834 memset(&c
, 0, sizeof(c
));
2835 INIT_CMD(c
, HELLO
, WRITE
);
2836 c
.err_to_clearinit
= htonl(
2837 FW_HELLO_CMD_MASTERDIS_V(master
== MASTER_CANT
) |
2838 FW_HELLO_CMD_MASTERFORCE_V(master
== MASTER_MUST
) |
2839 FW_HELLO_CMD_MBMASTER_V(master
== MASTER_MUST
? mbox
:
2840 FW_HELLO_CMD_MBMASTER_M
) |
2841 FW_HELLO_CMD_MBASYNCNOT_V(evt_mbox
) |
2842 FW_HELLO_CMD_STAGE_V(fw_hello_cmd_stage_os
) |
2843 FW_HELLO_CMD_CLEARINIT_F
);
2846 * Issue the HELLO command to the firmware. If it's not successful
2847 * but indicates that we got a "busy" or "timeout" condition, retry
2848 * the HELLO until we exhaust our retry limit. If we do exceed our
2849 * retry limit, check to see if the firmware left us any error
2850 * information and report that if so.
2852 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
2854 if ((ret
== -EBUSY
|| ret
== -ETIMEDOUT
) && retries
-- > 0)
2856 if (t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_ERR_F
)
2857 t4_report_fw_error(adap
);
2861 v
= ntohl(c
.err_to_clearinit
);
2862 master_mbox
= FW_HELLO_CMD_MBMASTER_G(v
);
2864 if (v
& FW_HELLO_CMD_ERR_F
)
2865 *state
= DEV_STATE_ERR
;
2866 else if (v
& FW_HELLO_CMD_INIT_F
)
2867 *state
= DEV_STATE_INIT
;
2869 *state
= DEV_STATE_UNINIT
;
2873 * If we're not the Master PF then we need to wait around for the
2874 * Master PF Driver to finish setting up the adapter.
2876 * Note that we also do this wait if we're a non-Master-capable PF and
2877 * there is no current Master PF; a Master PF may show up momentarily
2878 * and we wouldn't want to fail pointlessly. (This can happen when an
2879 * OS loads lots of different drivers rapidly at the same time). In
2880 * this case, the Master PF returned by the firmware will be
2881 * PCIE_FW_MASTER_M so the test below will work ...
2883 if ((v
& (FW_HELLO_CMD_ERR_F
|FW_HELLO_CMD_INIT_F
)) == 0 &&
2884 master_mbox
!= mbox
) {
2885 int waiting
= FW_CMD_HELLO_TIMEOUT
;
2888 * Wait for the firmware to either indicate an error or
2889 * initialized state. If we see either of these we bail out
2890 * and report the issue to the caller. If we exhaust the
2891 * "hello timeout" and we haven't exhausted our retries, try
2892 * again. Otherwise bail with a timeout error.
2901 * If neither Error nor Initialialized are indicated
2902 * by the firmware keep waiting till we exaust our
2903 * timeout ... and then retry if we haven't exhausted
2906 pcie_fw
= t4_read_reg(adap
, PCIE_FW_A
);
2907 if (!(pcie_fw
& (PCIE_FW_ERR_F
|PCIE_FW_INIT_F
))) {
2918 * We either have an Error or Initialized condition
2919 * report errors preferentially.
2922 if (pcie_fw
& PCIE_FW_ERR_F
)
2923 *state
= DEV_STATE_ERR
;
2924 else if (pcie_fw
& PCIE_FW_INIT_F
)
2925 *state
= DEV_STATE_INIT
;
2929 * If we arrived before a Master PF was selected and
2930 * there's not a valid Master PF, grab its identity
2933 if (master_mbox
== PCIE_FW_MASTER_M
&&
2934 (pcie_fw
& PCIE_FW_MASTER_VLD_F
))
2935 master_mbox
= PCIE_FW_MASTER_G(pcie_fw
);
2944 * t4_fw_bye - end communication with FW
2945 * @adap: the adapter
2946 * @mbox: mailbox to use for the FW command
2948 * Issues a command to terminate communication with FW.
2950 int t4_fw_bye(struct adapter
*adap
, unsigned int mbox
)
2952 struct fw_bye_cmd c
;
2954 memset(&c
, 0, sizeof(c
));
2955 INIT_CMD(c
, BYE
, WRITE
);
2956 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
2960 * t4_init_cmd - ask FW to initialize the device
2961 * @adap: the adapter
2962 * @mbox: mailbox to use for the FW command
2964 * Issues a command to FW to partially initialize the device. This
2965 * performs initialization that generally doesn't depend on user input.
2967 int t4_early_init(struct adapter
*adap
, unsigned int mbox
)
2969 struct fw_initialize_cmd c
;
2971 memset(&c
, 0, sizeof(c
));
2972 INIT_CMD(c
, INITIALIZE
, WRITE
);
2973 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
2977 * t4_fw_reset - issue a reset to FW
2978 * @adap: the adapter
2979 * @mbox: mailbox to use for the FW command
2980 * @reset: specifies the type of reset to perform
2982 * Issues a reset command of the specified type to FW.
2984 int t4_fw_reset(struct adapter
*adap
, unsigned int mbox
, int reset
)
2986 struct fw_reset_cmd c
;
2988 memset(&c
, 0, sizeof(c
));
2989 INIT_CMD(c
, RESET
, WRITE
);
2990 c
.val
= htonl(reset
);
2991 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
2995 * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
2996 * @adap: the adapter
2997 * @mbox: mailbox to use for the FW RESET command (if desired)
2998 * @force: force uP into RESET even if FW RESET command fails
3000 * Issues a RESET command to firmware (if desired) with a HALT indication
3001 * and then puts the microprocessor into RESET state. The RESET command
3002 * will only be issued if a legitimate mailbox is provided (mbox <=
3003 * PCIE_FW_MASTER_M).
3005 * This is generally used in order for the host to safely manipulate the
3006 * adapter without fear of conflicting with whatever the firmware might
3007 * be doing. The only way out of this state is to RESTART the firmware
3010 static int t4_fw_halt(struct adapter
*adap
, unsigned int mbox
, int force
)
3015 * If a legitimate mailbox is provided, issue a RESET command
3016 * with a HALT indication.
3018 if (mbox
<= PCIE_FW_MASTER_M
) {
3019 struct fw_reset_cmd c
;
3021 memset(&c
, 0, sizeof(c
));
3022 INIT_CMD(c
, RESET
, WRITE
);
3023 c
.val
= htonl(PIORST_F
| PIORSTMODE_F
);
3024 c
.halt_pkd
= htonl(FW_RESET_CMD_HALT_F
);
3025 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3029 * Normally we won't complete the operation if the firmware RESET
3030 * command fails but if our caller insists we'll go ahead and put the
3031 * uP into RESET. This can be useful if the firmware is hung or even
3032 * missing ... We'll have to take the risk of putting the uP into
3033 * RESET without the cooperation of firmware in that case.
3035 * We also force the firmware's HALT flag to be on in case we bypassed
3036 * the firmware RESET command above or we're dealing with old firmware
3037 * which doesn't have the HALT capability. This will serve as a flag
3038 * for the incoming firmware to know that it's coming out of a HALT
3039 * rather than a RESET ... if it's new enough to understand that ...
3041 if (ret
== 0 || force
) {
3042 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, UPCRST_F
);
3043 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
,
3048 * And we always return the result of the firmware RESET command
3049 * even when we force the uP into RESET ...
3055 * t4_fw_restart - restart the firmware by taking the uP out of RESET
3056 * @adap: the adapter
3057 * @reset: if we want to do a RESET to restart things
3059 * Restart firmware previously halted by t4_fw_halt(). On successful
3060 * return the previous PF Master remains as the new PF Master and there
3061 * is no need to issue a new HELLO command, etc.
3063 * We do this in two ways:
3065 * 1. If we're dealing with newer firmware we'll simply want to take
3066 * the chip's microprocessor out of RESET. This will cause the
3067 * firmware to start up from its start vector. And then we'll loop
3068 * until the firmware indicates it's started again (PCIE_FW.HALT
3069 * reset to 0) or we timeout.
3071 * 2. If we're dealing with older firmware then we'll need to RESET
3072 * the chip since older firmware won't recognize the PCIE_FW.HALT
3073 * flag and automatically RESET itself on startup.
3075 static int t4_fw_restart(struct adapter
*adap
, unsigned int mbox
, int reset
)
3079 * Since we're directing the RESET instead of the firmware
3080 * doing it automatically, we need to clear the PCIE_FW.HALT
3083 t4_set_reg_field(adap
, PCIE_FW_A
, PCIE_FW_HALT_F
, 0);
3086 * If we've been given a valid mailbox, first try to get the
3087 * firmware to do the RESET. If that works, great and we can
3088 * return success. Otherwise, if we haven't been given a
3089 * valid mailbox or the RESET command failed, fall back to
3090 * hitting the chip with a hammer.
3092 if (mbox
<= PCIE_FW_MASTER_M
) {
3093 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
3095 if (t4_fw_reset(adap
, mbox
,
3096 PIORST_F
| PIORSTMODE_F
) == 0)
3100 t4_write_reg(adap
, PL_RST_A
, PIORST_F
| PIORSTMODE_F
);
3105 t4_set_reg_field(adap
, CIM_BOOT_CFG_A
, UPCRST_F
, 0);
3106 for (ms
= 0; ms
< FW_CMD_MAX_TIMEOUT
; ) {
3107 if (!(t4_read_reg(adap
, PCIE_FW_A
) & PCIE_FW_HALT_F
))
3118 * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
3119 * @adap: the adapter
3120 * @mbox: mailbox to use for the FW RESET command (if desired)
3121 * @fw_data: the firmware image to write
3123 * @force: force upgrade even if firmware doesn't cooperate
3125 * Perform all of the steps necessary for upgrading an adapter's
3126 * firmware image. Normally this requires the cooperation of the
3127 * existing firmware in order to halt all existing activities
3128 * but if an invalid mailbox token is passed in we skip that step
3129 * (though we'll still put the adapter microprocessor into RESET in
3132 * On successful return the new firmware will have been loaded and
3133 * the adapter will have been fully RESET losing all previous setup
3134 * state. On unsuccessful return the adapter may be completely hosed ...
3135 * positive errno indicates that the adapter is ~probably~ intact, a
3136 * negative errno indicates that things are looking bad ...
3138 int t4_fw_upgrade(struct adapter
*adap
, unsigned int mbox
,
3139 const u8
*fw_data
, unsigned int size
, int force
)
3141 const struct fw_hdr
*fw_hdr
= (const struct fw_hdr
*)fw_data
;
3144 if (!t4_fw_matches_chip(adap
, fw_hdr
))
3147 ret
= t4_fw_halt(adap
, mbox
, force
);
3148 if (ret
< 0 && !force
)
3151 ret
= t4_load_fw(adap
, fw_data
, size
);
3156 * Older versions of the firmware don't understand the new
3157 * PCIE_FW.HALT flag and so won't know to perform a RESET when they
3158 * restart. So for newly loaded older firmware we'll have to do the
3159 * RESET for it so it starts up on a clean slate. We can tell if
3160 * the newly loaded firmware will handle this right by checking
3161 * its header flags to see if it advertises the capability.
3163 reset
= ((ntohl(fw_hdr
->flags
) & FW_HDR_FLAGS_RESET_HALT
) == 0);
3164 return t4_fw_restart(adap
, mbox
, reset
);
3168 * t4_fixup_host_params - fix up host-dependent parameters
3169 * @adap: the adapter
3170 * @page_size: the host's Base Page Size
3171 * @cache_line_size: the host's Cache Line Size
3173 * Various registers in T4 contain values which are dependent on the
3174 * host's Base Page and Cache Line Sizes. This function will fix all of
3175 * those registers with the appropriate values as passed in ...
3177 int t4_fixup_host_params(struct adapter
*adap
, unsigned int page_size
,
3178 unsigned int cache_line_size
)
3180 unsigned int page_shift
= fls(page_size
) - 1;
3181 unsigned int sge_hps
= page_shift
- 10;
3182 unsigned int stat_len
= cache_line_size
> 64 ? 128 : 64;
3183 unsigned int fl_align
= cache_line_size
< 32 ? 32 : cache_line_size
;
3184 unsigned int fl_align_log
= fls(fl_align
) - 1;
3186 t4_write_reg(adap
, SGE_HOST_PAGE_SIZE_A
,
3187 HOSTPAGESIZEPF0_V(sge_hps
) |
3188 HOSTPAGESIZEPF1_V(sge_hps
) |
3189 HOSTPAGESIZEPF2_V(sge_hps
) |
3190 HOSTPAGESIZEPF3_V(sge_hps
) |
3191 HOSTPAGESIZEPF4_V(sge_hps
) |
3192 HOSTPAGESIZEPF5_V(sge_hps
) |
3193 HOSTPAGESIZEPF6_V(sge_hps
) |
3194 HOSTPAGESIZEPF7_V(sge_hps
));
3196 if (is_t4(adap
->params
.chip
)) {
3197 t4_set_reg_field(adap
, SGE_CONTROL_A
,
3198 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
3199 EGRSTATUSPAGESIZE_F
,
3200 INGPADBOUNDARY_V(fl_align_log
-
3201 INGPADBOUNDARY_SHIFT_X
) |
3202 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
3204 /* T5 introduced the separation of the Free List Padding and
3205 * Packing Boundaries. Thus, we can select a smaller Padding
3206 * Boundary to avoid uselessly chewing up PCIe Link and Memory
3207 * Bandwidth, and use a Packing Boundary which is large enough
3208 * to avoid false sharing between CPUs, etc.
3210 * For the PCI Link, the smaller the Padding Boundary the
3211 * better. For the Memory Controller, a smaller Padding
3212 * Boundary is better until we cross under the Memory Line
3213 * Size (the minimum unit of transfer to/from Memory). If we
3214 * have a Padding Boundary which is smaller than the Memory
3215 * Line Size, that'll involve a Read-Modify-Write cycle on the
3216 * Memory Controller which is never good. For T5 the smallest
3217 * Padding Boundary which we can select is 32 bytes which is
3218 * larger than any known Memory Controller Line Size so we'll
3221 * T5 has a different interpretation of the "0" value for the
3222 * Packing Boundary. This corresponds to 16 bytes instead of
3223 * the expected 32 bytes. We never have a Packing Boundary
3224 * less than 32 bytes so we can't use that special value but
3225 * on the other hand, if we wanted 32 bytes, the best we can
3226 * really do is 64 bytes.
3228 if (fl_align
<= 32) {
3232 t4_set_reg_field(adap
, SGE_CONTROL_A
,
3233 INGPADBOUNDARY_V(INGPADBOUNDARY_M
) |
3234 EGRSTATUSPAGESIZE_F
,
3235 INGPADBOUNDARY_V(INGPCIEBOUNDARY_32B_X
) |
3236 EGRSTATUSPAGESIZE_V(stat_len
!= 64));
3237 t4_set_reg_field(adap
, SGE_CONTROL2_A
,
3238 INGPACKBOUNDARY_V(INGPACKBOUNDARY_M
),
3239 INGPACKBOUNDARY_V(fl_align_log
-
3240 INGPACKBOUNDARY_SHIFT_X
));
3243 * Adjust various SGE Free List Host Buffer Sizes.
3245 * This is something of a crock since we're using fixed indices into
3246 * the array which are also known by the sge.c code and the T4
3247 * Firmware Configuration File. We need to come up with a much better
3248 * approach to managing this array. For now, the first four entries
3253 * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
3254 * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
3256 * For the single-MTU buffers in unpacked mode we need to include
3257 * space for the SGE Control Packet Shift, 14 byte Ethernet header,
3258 * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
3259 * Padding boundry. All of these are accommodated in the Factory
3260 * Default Firmware Configuration File but we need to adjust it for
3261 * this host's cache line size.
3263 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE0_A
, page_size
);
3264 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE2_A
,
3265 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE2_A
) + fl_align
-1)
3267 t4_write_reg(adap
, SGE_FL_BUFFER_SIZE3_A
,
3268 (t4_read_reg(adap
, SGE_FL_BUFFER_SIZE3_A
) + fl_align
-1)
3271 t4_write_reg(adap
, ULP_RX_TDDP_PSZ_A
, HPZ0_V(page_shift
- 12));
3277 * t4_fw_initialize - ask FW to initialize the device
3278 * @adap: the adapter
3279 * @mbox: mailbox to use for the FW command
3281 * Issues a command to FW to partially initialize the device. This
3282 * performs initialization that generally doesn't depend on user input.
3284 int t4_fw_initialize(struct adapter
*adap
, unsigned int mbox
)
3286 struct fw_initialize_cmd c
;
3288 memset(&c
, 0, sizeof(c
));
3289 INIT_CMD(c
, INITIALIZE
, WRITE
);
3290 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3294 * t4_query_params - query FW or device parameters
3295 * @adap: the adapter
3296 * @mbox: mailbox to use for the FW command
3299 * @nparams: the number of parameters
3300 * @params: the parameter names
3301 * @val: the parameter values
3303 * Reads the value of FW or device parameters. Up to 7 parameters can be
3306 int t4_query_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
3307 unsigned int vf
, unsigned int nparams
, const u32
*params
,
3311 struct fw_params_cmd c
;
3312 __be32
*p
= &c
.param
[0].mnem
;
3317 memset(&c
, 0, sizeof(c
));
3318 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_PARAMS_CMD
) | FW_CMD_REQUEST_F
|
3319 FW_CMD_READ_F
| FW_PARAMS_CMD_PFN_V(pf
) |
3320 FW_PARAMS_CMD_VFN_V(vf
));
3321 c
.retval_len16
= htonl(FW_LEN16(c
));
3322 for (i
= 0; i
< nparams
; i
++, p
+= 2)
3323 *p
= htonl(*params
++);
3325 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
3327 for (i
= 0, p
= &c
.param
[0].val
; i
< nparams
; i
++, p
+= 2)
3333 * t4_set_params_nosleep - sets FW or device parameters
3334 * @adap: the adapter
3335 * @mbox: mailbox to use for the FW command
3338 * @nparams: the number of parameters
3339 * @params: the parameter names
3340 * @val: the parameter values
3342 * Does not ever sleep
3343 * Sets the value of FW or device parameters. Up to 7 parameters can be
3344 * specified at once.
3346 int t4_set_params_nosleep(struct adapter
*adap
, unsigned int mbox
,
3347 unsigned int pf
, unsigned int vf
,
3348 unsigned int nparams
, const u32
*params
,
3351 struct fw_params_cmd c
;
3352 __be32
*p
= &c
.param
[0].mnem
;
3357 memset(&c
, 0, sizeof(c
));
3358 c
.op_to_vfn
= cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD
) |
3359 FW_CMD_REQUEST_F
| FW_CMD_WRITE_F
|
3360 FW_PARAMS_CMD_PFN_V(pf
) |
3361 FW_PARAMS_CMD_VFN_V(vf
));
3362 c
.retval_len16
= cpu_to_be32(FW_LEN16(c
));
3365 *p
++ = cpu_to_be32(*params
++);
3366 *p
++ = cpu_to_be32(*val
++);
3369 return t4_wr_mbox_ns(adap
, mbox
, &c
, sizeof(c
), NULL
);
3373 * t4_set_params - sets FW or device parameters
3374 * @adap: the adapter
3375 * @mbox: mailbox to use for the FW command
3378 * @nparams: the number of parameters
3379 * @params: the parameter names
3380 * @val: the parameter values
3382 * Sets the value of FW or device parameters. Up to 7 parameters can be
3383 * specified at once.
3385 int t4_set_params(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
3386 unsigned int vf
, unsigned int nparams
, const u32
*params
,
3389 struct fw_params_cmd c
;
3390 __be32
*p
= &c
.param
[0].mnem
;
3395 memset(&c
, 0, sizeof(c
));
3396 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_PARAMS_CMD
) | FW_CMD_REQUEST_F
|
3397 FW_CMD_WRITE_F
| FW_PARAMS_CMD_PFN_V(pf
) |
3398 FW_PARAMS_CMD_VFN_V(vf
));
3399 c
.retval_len16
= htonl(FW_LEN16(c
));
3401 *p
++ = htonl(*params
++);
3402 *p
++ = htonl(*val
++);
3405 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3409 * t4_cfg_pfvf - configure PF/VF resource limits
3410 * @adap: the adapter
3411 * @mbox: mailbox to use for the FW command
3412 * @pf: the PF being configured
3413 * @vf: the VF being configured
3414 * @txq: the max number of egress queues
3415 * @txq_eth_ctrl: the max number of egress Ethernet or control queues
3416 * @rxqi: the max number of interrupt-capable ingress queues
3417 * @rxq: the max number of interruptless ingress queues
3418 * @tc: the PCI traffic class
3419 * @vi: the max number of virtual interfaces
3420 * @cmask: the channel access rights mask for the PF/VF
3421 * @pmask: the port access rights mask for the PF/VF
3422 * @nexact: the maximum number of exact MPS filters
3423 * @rcaps: read capabilities
3424 * @wxcaps: write/execute capabilities
3426 * Configures resource limits and capabilities for a physical or virtual
3429 int t4_cfg_pfvf(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
3430 unsigned int vf
, unsigned int txq
, unsigned int txq_eth_ctrl
,
3431 unsigned int rxqi
, unsigned int rxq
, unsigned int tc
,
3432 unsigned int vi
, unsigned int cmask
, unsigned int pmask
,
3433 unsigned int nexact
, unsigned int rcaps
, unsigned int wxcaps
)
3435 struct fw_pfvf_cmd c
;
3437 memset(&c
, 0, sizeof(c
));
3438 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_PFVF_CMD
) | FW_CMD_REQUEST_F
|
3439 FW_CMD_WRITE_F
| FW_PFVF_CMD_PFN_V(pf
) |
3440 FW_PFVF_CMD_VFN_V(vf
));
3441 c
.retval_len16
= htonl(FW_LEN16(c
));
3442 c
.niqflint_niq
= htonl(FW_PFVF_CMD_NIQFLINT_V(rxqi
) |
3443 FW_PFVF_CMD_NIQ_V(rxq
));
3444 c
.type_to_neq
= htonl(FW_PFVF_CMD_CMASK_V(cmask
) |
3445 FW_PFVF_CMD_PMASK_V(pmask
) |
3446 FW_PFVF_CMD_NEQ_V(txq
));
3447 c
.tc_to_nexactf
= htonl(FW_PFVF_CMD_TC_V(tc
) | FW_PFVF_CMD_NVI_V(vi
) |
3448 FW_PFVF_CMD_NEXACTF_V(nexact
));
3449 c
.r_caps_to_nethctrl
= htonl(FW_PFVF_CMD_R_CAPS_V(rcaps
) |
3450 FW_PFVF_CMD_WX_CAPS_V(wxcaps
) |
3451 FW_PFVF_CMD_NETHCTRL_V(txq_eth_ctrl
));
3452 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3456 * t4_alloc_vi - allocate a virtual interface
3457 * @adap: the adapter
3458 * @mbox: mailbox to use for the FW command
3459 * @port: physical port associated with the VI
3460 * @pf: the PF owning the VI
3461 * @vf: the VF owning the VI
3462 * @nmac: number of MAC addresses needed (1 to 5)
3463 * @mac: the MAC addresses of the VI
3464 * @rss_size: size of RSS table slice associated with this VI
3466 * Allocates a virtual interface for the given physical port. If @mac is
3467 * not %NULL it contains the MAC addresses of the VI as assigned by FW.
3468 * @mac should be large enough to hold @nmac Ethernet addresses, they are
3469 * stored consecutively so the space needed is @nmac * 6 bytes.
3470 * Returns a negative error number or the non-negative VI id.
3472 int t4_alloc_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int port
,
3473 unsigned int pf
, unsigned int vf
, unsigned int nmac
, u8
*mac
,
3474 unsigned int *rss_size
)
3479 memset(&c
, 0, sizeof(c
));
3480 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_VI_CMD
) | FW_CMD_REQUEST_F
|
3481 FW_CMD_WRITE_F
| FW_CMD_EXEC_F
|
3482 FW_VI_CMD_PFN_V(pf
) | FW_VI_CMD_VFN_V(vf
));
3483 c
.alloc_to_len16
= htonl(FW_VI_CMD_ALLOC_F
| FW_LEN16(c
));
3484 c
.portid_pkd
= FW_VI_CMD_PORTID_V(port
);
3487 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
3492 memcpy(mac
, c
.mac
, sizeof(c
.mac
));
3495 memcpy(mac
+ 24, c
.nmac3
, sizeof(c
.nmac3
));
3497 memcpy(mac
+ 18, c
.nmac2
, sizeof(c
.nmac2
));
3499 memcpy(mac
+ 12, c
.nmac1
, sizeof(c
.nmac1
));
3501 memcpy(mac
+ 6, c
.nmac0
, sizeof(c
.nmac0
));
3505 *rss_size
= FW_VI_CMD_RSSSIZE_G(ntohs(c
.rsssize_pkd
));
3506 return FW_VI_CMD_VIID_G(ntohs(c
.type_viid
));
3510 * t4_set_rxmode - set Rx properties of a virtual interface
3511 * @adap: the adapter
3512 * @mbox: mailbox to use for the FW command
3514 * @mtu: the new MTU or -1
3515 * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
3516 * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
3517 * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
3518 * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
3519 * @sleep_ok: if true we may sleep while awaiting command completion
3521 * Sets Rx properties of a virtual interface.
3523 int t4_set_rxmode(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
3524 int mtu
, int promisc
, int all_multi
, int bcast
, int vlanex
,
3527 struct fw_vi_rxmode_cmd c
;
3529 /* convert to FW values */
3531 mtu
= FW_RXMODE_MTU_NO_CHG
;
3533 promisc
= FW_VI_RXMODE_CMD_PROMISCEN_M
;
3535 all_multi
= FW_VI_RXMODE_CMD_ALLMULTIEN_M
;
3537 bcast
= FW_VI_RXMODE_CMD_BROADCASTEN_M
;
3539 vlanex
= FW_VI_RXMODE_CMD_VLANEXEN_M
;
3541 memset(&c
, 0, sizeof(c
));
3542 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_RXMODE_CMD
) | FW_CMD_REQUEST_F
|
3543 FW_CMD_WRITE_F
| FW_VI_RXMODE_CMD_VIID_V(viid
));
3544 c
.retval_len16
= htonl(FW_LEN16(c
));
3545 c
.mtu_to_vlanexen
= htonl(FW_VI_RXMODE_CMD_MTU_V(mtu
) |
3546 FW_VI_RXMODE_CMD_PROMISCEN_V(promisc
) |
3547 FW_VI_RXMODE_CMD_ALLMULTIEN_V(all_multi
) |
3548 FW_VI_RXMODE_CMD_BROADCASTEN_V(bcast
) |
3549 FW_VI_RXMODE_CMD_VLANEXEN_V(vlanex
));
3550 return t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
3554 * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
3555 * @adap: the adapter
3556 * @mbox: mailbox to use for the FW command
3558 * @free: if true any existing filters for this VI id are first removed
3559 * @naddr: the number of MAC addresses to allocate filters for (up to 7)
3560 * @addr: the MAC address(es)
3561 * @idx: where to store the index of each allocated filter
3562 * @hash: pointer to hash address filter bitmap
3563 * @sleep_ok: call is allowed to sleep
3565 * Allocates an exact-match filter for each of the supplied addresses and
3566 * sets it to the corresponding address. If @idx is not %NULL it should
3567 * have at least @naddr entries, each of which will be set to the index of
3568 * the filter allocated for the corresponding MAC address. If a filter
3569 * could not be allocated for an address its index is set to 0xffff.
3570 * If @hash is not %NULL addresses that fail to allocate an exact filter
3571 * are hashed and update the hash filter bitmap pointed at by @hash.
3573 * Returns a negative error number or the number of filters allocated.
3575 int t4_alloc_mac_filt(struct adapter
*adap
, unsigned int mbox
,
3576 unsigned int viid
, bool free
, unsigned int naddr
,
3577 const u8
**addr
, u16
*idx
, u64
*hash
, bool sleep_ok
)
3580 struct fw_vi_mac_cmd c
;
3581 struct fw_vi_mac_exact
*p
;
3582 unsigned int max_naddr
= is_t4(adap
->params
.chip
) ?
3583 NUM_MPS_CLS_SRAM_L_INSTANCES
:
3584 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
3589 memset(&c
, 0, sizeof(c
));
3590 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_MAC_CMD
) | FW_CMD_REQUEST_F
|
3591 FW_CMD_WRITE_F
| (free
? FW_CMD_EXEC_F
: 0) |
3592 FW_VI_MAC_CMD_VIID_V(viid
));
3593 c
.freemacs_to_len16
= htonl(FW_VI_MAC_CMD_FREEMACS_V(free
) |
3594 FW_CMD_LEN16_V((naddr
+ 2) / 2));
3596 for (i
= 0, p
= c
.u
.exact
; i
< naddr
; i
++, p
++) {
3597 p
->valid_to_idx
= htons(FW_VI_MAC_CMD_VALID_F
|
3598 FW_VI_MAC_CMD_IDX_V(FW_VI_MAC_ADD_MAC
));
3599 memcpy(p
->macaddr
, addr
[i
], sizeof(p
->macaddr
));
3602 ret
= t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), &c
, sleep_ok
);
3606 for (i
= 0, p
= c
.u
.exact
; i
< naddr
; i
++, p
++) {
3607 u16 index
= FW_VI_MAC_CMD_IDX_G(ntohs(p
->valid_to_idx
));
3610 idx
[i
] = index
>= max_naddr
? 0xffff : index
;
3611 if (index
< max_naddr
)
3614 *hash
|= (1ULL << hash_mac_addr(addr
[i
]));
3620 * t4_change_mac - modifies the exact-match filter for a MAC address
3621 * @adap: the adapter
3622 * @mbox: mailbox to use for the FW command
3624 * @idx: index of existing filter for old value of MAC address, or -1
3625 * @addr: the new MAC address value
3626 * @persist: whether a new MAC allocation should be persistent
3627 * @add_smt: if true also add the address to the HW SMT
3629 * Modifies an exact-match filter and sets it to the new MAC address.
3630 * Note that in general it is not possible to modify the value of a given
3631 * filter so the generic way to modify an address filter is to free the one
3632 * being used by the old address value and allocate a new filter for the
3633 * new address value. @idx can be -1 if the address is a new addition.
3635 * Returns a negative error number or the index of the filter with the new
3638 int t4_change_mac(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
3639 int idx
, const u8
*addr
, bool persist
, bool add_smt
)
3642 struct fw_vi_mac_cmd c
;
3643 struct fw_vi_mac_exact
*p
= c
.u
.exact
;
3644 unsigned int max_mac_addr
= is_t4(adap
->params
.chip
) ?
3645 NUM_MPS_CLS_SRAM_L_INSTANCES
:
3646 NUM_MPS_T5_CLS_SRAM_L_INSTANCES
;
3648 if (idx
< 0) /* new allocation */
3649 idx
= persist
? FW_VI_MAC_ADD_PERSIST_MAC
: FW_VI_MAC_ADD_MAC
;
3650 mode
= add_smt
? FW_VI_MAC_SMT_AND_MPSTCAM
: FW_VI_MAC_MPS_TCAM_ENTRY
;
3652 memset(&c
, 0, sizeof(c
));
3653 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_MAC_CMD
) | FW_CMD_REQUEST_F
|
3654 FW_CMD_WRITE_F
| FW_VI_MAC_CMD_VIID_V(viid
));
3655 c
.freemacs_to_len16
= htonl(FW_CMD_LEN16_V(1));
3656 p
->valid_to_idx
= htons(FW_VI_MAC_CMD_VALID_F
|
3657 FW_VI_MAC_CMD_SMAC_RESULT_V(mode
) |
3658 FW_VI_MAC_CMD_IDX_V(idx
));
3659 memcpy(p
->macaddr
, addr
, sizeof(p
->macaddr
));
3661 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
3663 ret
= FW_VI_MAC_CMD_IDX_G(ntohs(p
->valid_to_idx
));
3664 if (ret
>= max_mac_addr
)
3671 * t4_set_addr_hash - program the MAC inexact-match hash filter
3672 * @adap: the adapter
3673 * @mbox: mailbox to use for the FW command
3675 * @ucast: whether the hash filter should also match unicast addresses
3676 * @vec: the value to be written to the hash filter
3677 * @sleep_ok: call is allowed to sleep
3679 * Sets the 64-bit inexact-match hash filter for a virtual interface.
3681 int t4_set_addr_hash(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
3682 bool ucast
, u64 vec
, bool sleep_ok
)
3684 struct fw_vi_mac_cmd c
;
3686 memset(&c
, 0, sizeof(c
));
3687 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_MAC_CMD
) | FW_CMD_REQUEST_F
|
3688 FW_CMD_WRITE_F
| FW_VI_ENABLE_CMD_VIID_V(viid
));
3689 c
.freemacs_to_len16
= htonl(FW_VI_MAC_CMD_HASHVECEN_F
|
3690 FW_VI_MAC_CMD_HASHUNIEN_V(ucast
) |
3692 c
.u
.hash
.hashvec
= cpu_to_be64(vec
);
3693 return t4_wr_mbox_meat(adap
, mbox
, &c
, sizeof(c
), NULL
, sleep_ok
);
3697 * t4_enable_vi_params - enable/disable a virtual interface
3698 * @adap: the adapter
3699 * @mbox: mailbox to use for the FW command
3701 * @rx_en: 1=enable Rx, 0=disable Rx
3702 * @tx_en: 1=enable Tx, 0=disable Tx
3703 * @dcb_en: 1=enable delivery of Data Center Bridging messages.
3705 * Enables/disables a virtual interface. Note that setting DCB Enable
3706 * only makes sense when enabling a Virtual Interface ...
3708 int t4_enable_vi_params(struct adapter
*adap
, unsigned int mbox
,
3709 unsigned int viid
, bool rx_en
, bool tx_en
, bool dcb_en
)
3711 struct fw_vi_enable_cmd c
;
3713 memset(&c
, 0, sizeof(c
));
3714 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) | FW_CMD_REQUEST_F
|
3715 FW_CMD_EXEC_F
| FW_VI_ENABLE_CMD_VIID_V(viid
));
3717 c
.ien_to_len16
= htonl(FW_VI_ENABLE_CMD_IEN_V(rx_en
) |
3718 FW_VI_ENABLE_CMD_EEN_V(tx_en
) | FW_LEN16(c
) |
3719 FW_VI_ENABLE_CMD_DCB_INFO_V(dcb_en
));
3720 return t4_wr_mbox_ns(adap
, mbox
, &c
, sizeof(c
), NULL
);
3724 * t4_enable_vi - enable/disable a virtual interface
3725 * @adap: the adapter
3726 * @mbox: mailbox to use for the FW command
3728 * @rx_en: 1=enable Rx, 0=disable Rx
3729 * @tx_en: 1=enable Tx, 0=disable Tx
3731 * Enables/disables a virtual interface.
3733 int t4_enable_vi(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
3734 bool rx_en
, bool tx_en
)
3736 return t4_enable_vi_params(adap
, mbox
, viid
, rx_en
, tx_en
, 0);
3740 * t4_identify_port - identify a VI's port by blinking its LED
3741 * @adap: the adapter
3742 * @mbox: mailbox to use for the FW command
3744 * @nblinks: how many times to blink LED at 2.5 Hz
3746 * Identifies a VI's port by blinking its LED.
3748 int t4_identify_port(struct adapter
*adap
, unsigned int mbox
, unsigned int viid
,
3749 unsigned int nblinks
)
3751 struct fw_vi_enable_cmd c
;
3753 memset(&c
, 0, sizeof(c
));
3754 c
.op_to_viid
= htonl(FW_CMD_OP_V(FW_VI_ENABLE_CMD
) | FW_CMD_REQUEST_F
|
3755 FW_CMD_EXEC_F
| FW_VI_ENABLE_CMD_VIID_V(viid
));
3756 c
.ien_to_len16
= htonl(FW_VI_ENABLE_CMD_LED_F
| FW_LEN16(c
));
3757 c
.blinkdur
= htons(nblinks
);
3758 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3762 * t4_iq_free - free an ingress queue and its FLs
3763 * @adap: the adapter
3764 * @mbox: mailbox to use for the FW command
3765 * @pf: the PF owning the queues
3766 * @vf: the VF owning the queues
3767 * @iqtype: the ingress queue type
3768 * @iqid: ingress queue id
3769 * @fl0id: FL0 queue id or 0xffff if no attached FL0
3770 * @fl1id: FL1 queue id or 0xffff if no attached FL1
3772 * Frees an ingress queue and its associated FLs, if any.
3774 int t4_iq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
3775 unsigned int vf
, unsigned int iqtype
, unsigned int iqid
,
3776 unsigned int fl0id
, unsigned int fl1id
)
3780 memset(&c
, 0, sizeof(c
));
3781 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_IQ_CMD
) | FW_CMD_REQUEST_F
|
3782 FW_CMD_EXEC_F
| FW_IQ_CMD_PFN_V(pf
) |
3783 FW_IQ_CMD_VFN_V(vf
));
3784 c
.alloc_to_len16
= htonl(FW_IQ_CMD_FREE_F
| FW_LEN16(c
));
3785 c
.type_to_iqandstindex
= htonl(FW_IQ_CMD_TYPE_V(iqtype
));
3786 c
.iqid
= htons(iqid
);
3787 c
.fl0id
= htons(fl0id
);
3788 c
.fl1id
= htons(fl1id
);
3789 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3793 * t4_eth_eq_free - free an Ethernet egress queue
3794 * @adap: the adapter
3795 * @mbox: mailbox to use for the FW command
3796 * @pf: the PF owning the queue
3797 * @vf: the VF owning the queue
3798 * @eqid: egress queue id
3800 * Frees an Ethernet egress queue.
3802 int t4_eth_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
3803 unsigned int vf
, unsigned int eqid
)
3805 struct fw_eq_eth_cmd c
;
3807 memset(&c
, 0, sizeof(c
));
3808 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_EQ_ETH_CMD
) | FW_CMD_REQUEST_F
|
3809 FW_CMD_EXEC_F
| FW_EQ_ETH_CMD_PFN_V(pf
) |
3810 FW_EQ_ETH_CMD_VFN_V(vf
));
3811 c
.alloc_to_len16
= htonl(FW_EQ_ETH_CMD_FREE_F
| FW_LEN16(c
));
3812 c
.eqid_pkd
= htonl(FW_EQ_ETH_CMD_EQID_V(eqid
));
3813 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3817 * t4_ctrl_eq_free - free a control egress queue
3818 * @adap: the adapter
3819 * @mbox: mailbox to use for the FW command
3820 * @pf: the PF owning the queue
3821 * @vf: the VF owning the queue
3822 * @eqid: egress queue id
3824 * Frees a control egress queue.
3826 int t4_ctrl_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
3827 unsigned int vf
, unsigned int eqid
)
3829 struct fw_eq_ctrl_cmd c
;
3831 memset(&c
, 0, sizeof(c
));
3832 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_EQ_CTRL_CMD
) | FW_CMD_REQUEST_F
|
3833 FW_CMD_EXEC_F
| FW_EQ_CTRL_CMD_PFN_V(pf
) |
3834 FW_EQ_CTRL_CMD_VFN_V(vf
));
3835 c
.alloc_to_len16
= htonl(FW_EQ_CTRL_CMD_FREE_F
| FW_LEN16(c
));
3836 c
.cmpliqid_eqid
= htonl(FW_EQ_CTRL_CMD_EQID_V(eqid
));
3837 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3841 * t4_ofld_eq_free - free an offload egress queue
3842 * @adap: the adapter
3843 * @mbox: mailbox to use for the FW command
3844 * @pf: the PF owning the queue
3845 * @vf: the VF owning the queue
3846 * @eqid: egress queue id
3848 * Frees a control egress queue.
3850 int t4_ofld_eq_free(struct adapter
*adap
, unsigned int mbox
, unsigned int pf
,
3851 unsigned int vf
, unsigned int eqid
)
3853 struct fw_eq_ofld_cmd c
;
3855 memset(&c
, 0, sizeof(c
));
3856 c
.op_to_vfn
= htonl(FW_CMD_OP_V(FW_EQ_OFLD_CMD
) | FW_CMD_REQUEST_F
|
3857 FW_CMD_EXEC_F
| FW_EQ_OFLD_CMD_PFN_V(pf
) |
3858 FW_EQ_OFLD_CMD_VFN_V(vf
));
3859 c
.alloc_to_len16
= htonl(FW_EQ_OFLD_CMD_FREE_F
| FW_LEN16(c
));
3860 c
.eqid_pkd
= htonl(FW_EQ_OFLD_CMD_EQID_V(eqid
));
3861 return t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), NULL
);
3865 * t4_handle_fw_rpl - process a FW reply message
3866 * @adap: the adapter
3867 * @rpl: start of the FW message
3869 * Processes a FW message, such as link state change messages.
3871 int t4_handle_fw_rpl(struct adapter
*adap
, const __be64
*rpl
)
3873 u8 opcode
= *(const u8
*)rpl
;
3875 if (opcode
== FW_PORT_CMD
) { /* link/module state change message */
3876 int speed
= 0, fc
= 0;
3877 const struct fw_port_cmd
*p
= (void *)rpl
;
3878 int chan
= FW_PORT_CMD_PORTID_G(ntohl(p
->op_to_portid
));
3879 int port
= adap
->chan_map
[chan
];
3880 struct port_info
*pi
= adap2pinfo(adap
, port
);
3881 struct link_config
*lc
= &pi
->link_cfg
;
3882 u32 stat
= ntohl(p
->u
.info
.lstatus_to_modtype
);
3883 int link_ok
= (stat
& FW_PORT_CMD_LSTATUS_F
) != 0;
3884 u32 mod
= FW_PORT_CMD_MODTYPE_G(stat
);
3886 if (stat
& FW_PORT_CMD_RXPAUSE_F
)
3888 if (stat
& FW_PORT_CMD_TXPAUSE_F
)
3890 if (stat
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_100M
))
3892 else if (stat
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_1G
))
3894 else if (stat
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_10G
))
3896 else if (stat
& FW_PORT_CMD_LSPEED_V(FW_PORT_CAP_SPEED_40G
))
3899 if (link_ok
!= lc
->link_ok
|| speed
!= lc
->speed
||
3900 fc
!= lc
->fc
) { /* something changed */
3901 lc
->link_ok
= link_ok
;
3904 lc
->supported
= be16_to_cpu(p
->u
.info
.pcap
);
3905 t4_os_link_changed(adap
, port
, link_ok
);
3907 if (mod
!= pi
->mod_type
) {
3909 t4_os_portmod_changed(adap
, port
);
3915 static void get_pci_mode(struct adapter
*adapter
, struct pci_params
*p
)
3919 if (pci_is_pcie(adapter
->pdev
)) {
3920 pcie_capability_read_word(adapter
->pdev
, PCI_EXP_LNKSTA
, &val
);
3921 p
->speed
= val
& PCI_EXP_LNKSTA_CLS
;
3922 p
->width
= (val
& PCI_EXP_LNKSTA_NLW
) >> 4;
3927 * init_link_config - initialize a link's SW state
3928 * @lc: structure holding the link state
3929 * @caps: link capabilities
3931 * Initializes the SW state maintained for each link, including the link's
3932 * capabilities and default speed/flow-control/autonegotiation settings.
3934 static void init_link_config(struct link_config
*lc
, unsigned int caps
)
3936 lc
->supported
= caps
;
3937 lc
->requested_speed
= 0;
3939 lc
->requested_fc
= lc
->fc
= PAUSE_RX
| PAUSE_TX
;
3940 if (lc
->supported
& FW_PORT_CAP_ANEG
) {
3941 lc
->advertising
= lc
->supported
& ADVERT_MASK
;
3942 lc
->autoneg
= AUTONEG_ENABLE
;
3943 lc
->requested_fc
|= PAUSE_AUTONEG
;
3945 lc
->advertising
= 0;
3946 lc
->autoneg
= AUTONEG_DISABLE
;
3950 #define CIM_PF_NOACCESS 0xeeeeeeee
3952 int t4_wait_dev_ready(void __iomem
*regs
)
3956 whoami
= readl(regs
+ PL_WHOAMI_A
);
3957 if (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
)
3961 whoami
= readl(regs
+ PL_WHOAMI_A
);
3962 return (whoami
!= 0xffffffff && whoami
!= CIM_PF_NOACCESS
? 0 : -EIO
);
3966 u32 vendor_and_model_id
;
3970 static int get_flash_params(struct adapter
*adap
)
3972 /* Table for non-Numonix supported flash parts. Numonix parts are left
3973 * to the preexisting code. All flash parts have 64KB sectors.
3975 static struct flash_desc supported_flash
[] = {
3976 { 0x150201, 4 << 20 }, /* Spansion 4MB S25FL032P */
3982 ret
= sf1_write(adap
, 1, 1, 0, SF_RD_ID
);
3984 ret
= sf1_read(adap
, 3, 0, 1, &info
);
3985 t4_write_reg(adap
, SF_OP_A
, 0); /* unlock SF */
3989 for (ret
= 0; ret
< ARRAY_SIZE(supported_flash
); ++ret
)
3990 if (supported_flash
[ret
].vendor_and_model_id
== info
) {
3991 adap
->params
.sf_size
= supported_flash
[ret
].size_mb
;
3992 adap
->params
.sf_nsec
=
3993 adap
->params
.sf_size
/ SF_SEC_SIZE
;
3997 if ((info
& 0xff) != 0x20) /* not a Numonix flash */
3999 info
>>= 16; /* log2 of size */
4000 if (info
>= 0x14 && info
< 0x18)
4001 adap
->params
.sf_nsec
= 1 << (info
- 16);
4002 else if (info
== 0x18)
4003 adap
->params
.sf_nsec
= 64;
4006 adap
->params
.sf_size
= 1 << info
;
4007 adap
->params
.sf_fw_start
=
4008 t4_read_reg(adap
, CIM_BOOT_CFG_A
) & BOOTADDR_M
;
4010 if (adap
->params
.sf_size
< FLASH_MIN_SIZE
)
4011 dev_warn(adap
->pdev_dev
, "WARNING!!! FLASH size %#x < %#x!!!\n",
4012 adap
->params
.sf_size
, FLASH_MIN_SIZE
);
4017 * t4_prep_adapter - prepare SW and HW for operation
4018 * @adapter: the adapter
4019 * @reset: if true perform a HW reset
4021 * Initialize adapter SW state for the various HW modules, set initial
4022 * values for some adapter tunables, take PHYs out of reset, and
4023 * initialize the MDIO interface.
4025 int t4_prep_adapter(struct adapter
*adapter
)
4031 get_pci_mode(adapter
, &adapter
->params
.pci
);
4032 pl_rev
= REV_G(t4_read_reg(adapter
, PL_REV_A
));
4034 ret
= get_flash_params(adapter
);
4036 dev_err(adapter
->pdev_dev
, "error %d identifying flash\n", ret
);
4040 /* Retrieve adapter's device ID
4042 pci_read_config_word(adapter
->pdev
, PCI_DEVICE_ID
, &device_id
);
4043 ver
= device_id
>> 12;
4044 adapter
->params
.chip
= 0;
4047 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T4
, pl_rev
);
4050 adapter
->params
.chip
|= CHELSIO_CHIP_CODE(CHELSIO_T5
, pl_rev
);
4053 dev_err(adapter
->pdev_dev
, "Device %d is not supported\n",
4058 adapter
->params
.cim_la_size
= CIMLA_SIZE
;
4059 init_cong_ctrl(adapter
->params
.a_wnd
, adapter
->params
.b_wnd
);
4062 * Default port for debugging in case we can't reach FW.
4064 adapter
->params
.nports
= 1;
4065 adapter
->params
.portvec
= 1;
4066 adapter
->params
.vpd
.cclk
= 50000;
4071 * cxgb4_t4_bar2_sge_qregs - return BAR2 SGE Queue register information
4072 * @adapter: the adapter
4073 * @qid: the Queue ID
4074 * @qtype: the Ingress or Egress type for @qid
4075 * @pbar2_qoffset: BAR2 Queue Offset
4076 * @pbar2_qid: BAR2 Queue ID or 0 for Queue ID inferred SGE Queues
4078 * Returns the BAR2 SGE Queue Registers information associated with the
4079 * indicated Absolute Queue ID. These are passed back in return value
4080 * pointers. @qtype should be T4_BAR2_QTYPE_EGRESS for Egress Queue
4081 * and T4_BAR2_QTYPE_INGRESS for Ingress Queues.
4083 * This may return an error which indicates that BAR2 SGE Queue
4084 * registers aren't available. If an error is not returned, then the
4085 * following values are returned:
4087 * *@pbar2_qoffset: the BAR2 Offset of the @qid Registers
4088 * *@pbar2_qid: the BAR2 SGE Queue ID or 0 of @qid
4090 * If the returned BAR2 Queue ID is 0, then BAR2 SGE registers which
4091 * require the "Inferred Queue ID" ability may be used. E.g. the
4092 * Write Combining Doorbell Buffer. If the BAR2 Queue ID is not 0,
4093 * then these "Inferred Queue ID" register may not be used.
4095 int cxgb4_t4_bar2_sge_qregs(struct adapter
*adapter
,
4097 enum t4_bar2_qtype qtype
,
4099 unsigned int *pbar2_qid
)
4101 unsigned int page_shift
, page_size
, qpp_shift
, qpp_mask
;
4102 u64 bar2_page_offset
, bar2_qoffset
;
4103 unsigned int bar2_qid
, bar2_qid_offset
, bar2_qinferred
;
4105 /* T4 doesn't support BAR2 SGE Queue registers.
4107 if (is_t4(adapter
->params
.chip
))
4110 /* Get our SGE Page Size parameters.
4112 page_shift
= adapter
->params
.sge
.hps
+ 10;
4113 page_size
= 1 << page_shift
;
4115 /* Get the right Queues per Page parameters for our Queue.
4117 qpp_shift
= (qtype
== T4_BAR2_QTYPE_EGRESS
4118 ? adapter
->params
.sge
.eq_qpp
4119 : adapter
->params
.sge
.iq_qpp
);
4120 qpp_mask
= (1 << qpp_shift
) - 1;
4122 /* Calculate the basics of the BAR2 SGE Queue register area:
4123 * o The BAR2 page the Queue registers will be in.
4124 * o The BAR2 Queue ID.
4125 * o The BAR2 Queue ID Offset into the BAR2 page.
4127 bar2_page_offset
= ((qid
>> qpp_shift
) << page_shift
);
4128 bar2_qid
= qid
& qpp_mask
;
4129 bar2_qid_offset
= bar2_qid
* SGE_UDB_SIZE
;
4131 /* If the BAR2 Queue ID Offset is less than the Page Size, then the
4132 * hardware will infer the Absolute Queue ID simply from the writes to
4133 * the BAR2 Queue ID Offset within the BAR2 Page (and we need to use a
4134 * BAR2 Queue ID of 0 for those writes). Otherwise, we'll simply
4135 * write to the first BAR2 SGE Queue Area within the BAR2 Page with
4136 * the BAR2 Queue ID and the hardware will infer the Absolute Queue ID
4137 * from the BAR2 Page and BAR2 Queue ID.
4139 * One important censequence of this is that some BAR2 SGE registers
4140 * have a "Queue ID" field and we can write the BAR2 SGE Queue ID
4141 * there. But other registers synthesize the SGE Queue ID purely
4142 * from the writes to the registers -- the Write Combined Doorbell
4143 * Buffer is a good example. These BAR2 SGE Registers are only
4144 * available for those BAR2 SGE Register areas where the SGE Absolute
4145 * Queue ID can be inferred from simple writes.
4147 bar2_qoffset
= bar2_page_offset
;
4148 bar2_qinferred
= (bar2_qid_offset
< page_size
);
4149 if (bar2_qinferred
) {
4150 bar2_qoffset
+= bar2_qid_offset
;
4154 *pbar2_qoffset
= bar2_qoffset
;
4155 *pbar2_qid
= bar2_qid
;
4160 * t4_init_sge_params - initialize adap->params.sge
4161 * @adapter: the adapter
4163 * Initialize various fields of the adapter's SGE Parameters structure.
4165 int t4_init_sge_params(struct adapter
*adapter
)
4167 struct sge_params
*sge_params
= &adapter
->params
.sge
;
4169 unsigned int s_hps
, s_qpp
;
4171 /* Extract the SGE Page Size for our PF.
4173 hps
= t4_read_reg(adapter
, SGE_HOST_PAGE_SIZE_A
);
4174 s_hps
= (HOSTPAGESIZEPF0_S
+
4175 (HOSTPAGESIZEPF1_S
- HOSTPAGESIZEPF0_S
) * adapter
->fn
);
4176 sge_params
->hps
= ((hps
>> s_hps
) & HOSTPAGESIZEPF0_M
);
4178 /* Extract the SGE Egress and Ingess Queues Per Page for our PF.
4180 s_qpp
= (QUEUESPERPAGEPF0_S
+
4181 (QUEUESPERPAGEPF1_S
- QUEUESPERPAGEPF0_S
) * adapter
->fn
);
4182 qpp
= t4_read_reg(adapter
, SGE_EGRESS_QUEUES_PER_PAGE_PF_A
);
4183 sge_params
->eq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
4184 qpp
= t4_read_reg(adapter
, SGE_INGRESS_QUEUES_PER_PAGE_PF_A
);
4185 sge_params
->iq_qpp
= ((qpp
>> s_qpp
) & QUEUESPERPAGEPF0_M
);
4191 * t4_init_tp_params - initialize adap->params.tp
4192 * @adap: the adapter
4194 * Initialize various fields of the adapter's TP Parameters structure.
4196 int t4_init_tp_params(struct adapter
*adap
)
4201 v
= t4_read_reg(adap
, TP_TIMER_RESOLUTION_A
);
4202 adap
->params
.tp
.tre
= TIMERRESOLUTION_G(v
);
4203 adap
->params
.tp
.dack_re
= DELAYEDACKRESOLUTION_G(v
);
4205 /* MODQ_REQ_MAP defaults to setting queues 0-3 to chan 0-3 */
4206 for (chan
= 0; chan
< NCHAN
; chan
++)
4207 adap
->params
.tp
.tx_modq
[chan
] = chan
;
4209 /* Cache the adapter's Compressed Filter Mode and global Incress
4212 t4_read_indirect(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
,
4213 &adap
->params
.tp
.vlan_pri_map
, 1,
4215 t4_read_indirect(adap
, TP_PIO_ADDR_A
, TP_PIO_DATA_A
,
4216 &adap
->params
.tp
.ingress_config
, 1,
4217 TP_INGRESS_CONFIG_A
);
4219 /* Now that we have TP_VLAN_PRI_MAP cached, we can calculate the field
4220 * shift positions of several elements of the Compressed Filter Tuple
4221 * for this adapter which we need frequently ...
4223 adap
->params
.tp
.vlan_shift
= t4_filter_field_shift(adap
, VLAN_F
);
4224 adap
->params
.tp
.vnic_shift
= t4_filter_field_shift(adap
, VNIC_ID_F
);
4225 adap
->params
.tp
.port_shift
= t4_filter_field_shift(adap
, PORT_F
);
4226 adap
->params
.tp
.protocol_shift
= t4_filter_field_shift(adap
,
4229 /* If TP_INGRESS_CONFIG.VNID == 0, then TP_VLAN_PRI_MAP.VNIC_ID
4230 * represents the presense of an Outer VLAN instead of a VNIC ID.
4232 if ((adap
->params
.tp
.ingress_config
& VNIC_F
) == 0)
4233 adap
->params
.tp
.vnic_shift
= -1;
4239 * t4_filter_field_shift - calculate filter field shift
4240 * @adap: the adapter
4241 * @filter_sel: the desired field (from TP_VLAN_PRI_MAP bits)
4243 * Return the shift position of a filter field within the Compressed
4244 * Filter Tuple. The filter field is specified via its selection bit
4245 * within TP_VLAN_PRI_MAL (filter mode). E.g. F_VLAN.
4247 int t4_filter_field_shift(const struct adapter
*adap
, int filter_sel
)
4249 unsigned int filter_mode
= adap
->params
.tp
.vlan_pri_map
;
4253 if ((filter_mode
& filter_sel
) == 0)
4256 for (sel
= 1, field_shift
= 0; sel
< filter_sel
; sel
<<= 1) {
4257 switch (filter_mode
& sel
) {
4259 field_shift
+= FT_FCOE_W
;
4262 field_shift
+= FT_PORT_W
;
4265 field_shift
+= FT_VNIC_ID_W
;
4268 field_shift
+= FT_VLAN_W
;
4271 field_shift
+= FT_TOS_W
;
4274 field_shift
+= FT_PROTOCOL_W
;
4277 field_shift
+= FT_ETHERTYPE_W
;
4280 field_shift
+= FT_MACMATCH_W
;
4283 field_shift
+= FT_MPSHITTYPE_W
;
4285 case FRAGMENTATION_F
:
4286 field_shift
+= FT_FRAGMENTATION_W
;
4293 int t4_port_init(struct adapter
*adap
, int mbox
, int pf
, int vf
)
4297 struct fw_port_cmd c
;
4298 struct fw_rss_vi_config_cmd rvc
;
4300 memset(&c
, 0, sizeof(c
));
4301 memset(&rvc
, 0, sizeof(rvc
));
4303 for_each_port(adap
, i
) {
4304 unsigned int rss_size
;
4305 struct port_info
*p
= adap2pinfo(adap
, i
);
4307 while ((adap
->params
.portvec
& (1 << j
)) == 0)
4310 c
.op_to_portid
= htonl(FW_CMD_OP_V(FW_PORT_CMD
) |
4311 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
4312 FW_PORT_CMD_PORTID_V(j
));
4313 c
.action_to_len16
= htonl(
4314 FW_PORT_CMD_ACTION_V(FW_PORT_ACTION_GET_PORT_INFO
) |
4316 ret
= t4_wr_mbox(adap
, mbox
, &c
, sizeof(c
), &c
);
4320 ret
= t4_alloc_vi(adap
, mbox
, j
, pf
, vf
, 1, addr
, &rss_size
);
4327 p
->rss_size
= rss_size
;
4328 memcpy(adap
->port
[i
]->dev_addr
, addr
, ETH_ALEN
);
4329 adap
->port
[i
]->dev_port
= j
;
4331 ret
= ntohl(c
.u
.info
.lstatus_to_modtype
);
4332 p
->mdio_addr
= (ret
& FW_PORT_CMD_MDIOCAP_F
) ?
4333 FW_PORT_CMD_MDIOADDR_G(ret
) : -1;
4334 p
->port_type
= FW_PORT_CMD_PTYPE_G(ret
);
4335 p
->mod_type
= FW_PORT_MOD_TYPE_NA
;
4337 rvc
.op_to_viid
= htonl(FW_CMD_OP_V(FW_RSS_VI_CONFIG_CMD
) |
4338 FW_CMD_REQUEST_F
| FW_CMD_READ_F
|
4339 FW_RSS_VI_CONFIG_CMD_VIID(p
->viid
));
4340 rvc
.retval_len16
= htonl(FW_LEN16(rvc
));
4341 ret
= t4_wr_mbox(adap
, mbox
, &rvc
, sizeof(rvc
), &rvc
);
4344 p
->rss_mode
= ntohl(rvc
.u
.basicvirtual
.defaultq_to_udpen
);
4346 init_link_config(&p
->link_cfg
, ntohs(c
.u
.info
.pcap
));
4353 * t4_read_cimq_cfg - read CIM queue configuration
4354 * @adap: the adapter
4355 * @base: holds the queue base addresses in bytes
4356 * @size: holds the queue sizes in bytes
4357 * @thres: holds the queue full thresholds in bytes
4359 * Returns the current configuration of the CIM queues, starting with
4360 * the IBQs, then the OBQs.
4362 void t4_read_cimq_cfg(struct adapter
*adap
, u16
*base
, u16
*size
, u16
*thres
)
4365 int cim_num_obq
= is_t4(adap
->params
.chip
) ?
4366 CIM_NUM_OBQ
: CIM_NUM_OBQ_T5
;
4368 for (i
= 0; i
< CIM_NUM_IBQ
; i
++) {
4369 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, IBQSELECT_F
|
4371 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
4372 /* value is in 256-byte units */
4373 *base
++ = CIMQBASE_G(v
) * 256;
4374 *size
++ = CIMQSIZE_G(v
) * 256;
4375 *thres
++ = QUEFULLTHRSH_G(v
) * 8; /* 8-byte unit */
4377 for (i
= 0; i
< cim_num_obq
; i
++) {
4378 t4_write_reg(adap
, CIM_QUEUE_CONFIG_REF_A
, OBQSELECT_F
|
4380 v
= t4_read_reg(adap
, CIM_QUEUE_CONFIG_CTRL_A
);
4381 /* value is in 256-byte units */
4382 *base
++ = CIMQBASE_G(v
) * 256;
4383 *size
++ = CIMQSIZE_G(v
) * 256;
4388 * t4_cim_read - read a block from CIM internal address space
4389 * @adap: the adapter
4390 * @addr: the start address within the CIM address space
4391 * @n: number of words to read
4392 * @valp: where to store the result
4394 * Reads a block of 4-byte words from the CIM intenal address space.
4396 int t4_cim_read(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
4401 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
4404 for ( ; !ret
&& n
--; addr
+= 4) {
4405 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
);
4406 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
4409 *valp
++ = t4_read_reg(adap
, CIM_HOST_ACC_DATA_A
);
4415 * t4_cim_write - write a block into CIM internal address space
4416 * @adap: the adapter
4417 * @addr: the start address within the CIM address space
4418 * @n: number of words to write
4419 * @valp: set of values to write
4421 * Writes a block of 4-byte words into the CIM intenal address space.
4423 int t4_cim_write(struct adapter
*adap
, unsigned int addr
, unsigned int n
,
4424 const unsigned int *valp
)
4428 if (t4_read_reg(adap
, CIM_HOST_ACC_CTRL_A
) & HOSTBUSY_F
)
4431 for ( ; !ret
&& n
--; addr
+= 4) {
4432 t4_write_reg(adap
, CIM_HOST_ACC_DATA_A
, *valp
++);
4433 t4_write_reg(adap
, CIM_HOST_ACC_CTRL_A
, addr
| HOSTWRITE_F
);
4434 ret
= t4_wait_op_done(adap
, CIM_HOST_ACC_CTRL_A
, HOSTBUSY_F
,
4440 static int t4_cim_write1(struct adapter
*adap
, unsigned int addr
,
4443 return t4_cim_write(adap
, addr
, 1, &val
);
4447 * t4_cim_read_la - read CIM LA capture buffer
4448 * @adap: the adapter
4449 * @la_buf: where to store the LA data
4450 * @wrptr: the HW write pointer within the capture buffer
4452 * Reads the contents of the CIM LA buffer with the most recent entry at
4453 * the end of the returned data and with the entry at @wrptr first.
4454 * We try to leave the LA in the running state we find it in.
4456 int t4_cim_read_la(struct adapter
*adap
, u32
*la_buf
, unsigned int *wrptr
)
4459 unsigned int cfg
, val
, idx
;
4461 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &cfg
);
4465 if (cfg
& UPDBGLAEN_F
) { /* LA is running, freeze it */
4466 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
, 0);
4471 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
4475 idx
= UPDBGLAWRPTR_G(val
);
4479 for (i
= 0; i
< adap
->params
.cim_la_size
; i
++) {
4480 ret
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
4481 UPDBGLARDPTR_V(idx
) | UPDBGLARDEN_F
);
4484 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_CFG_A
, 1, &val
);
4487 if (val
& UPDBGLARDEN_F
) {
4491 ret
= t4_cim_read(adap
, UP_UP_DBG_LA_DATA_A
, 1, &la_buf
[i
]);
4494 idx
= (idx
+ 1) & UPDBGLARDPTR_M
;
4497 if (cfg
& UPDBGLAEN_F
) {
4498 int r
= t4_cim_write1(adap
, UP_UP_DBG_LA_CFG_A
,
4499 cfg
& ~UPDBGLARDEN_F
);