drivers/net/ethernet/chelsio/cxgb4/t4_hw.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef __T4_HW_H
  36 #define __T4_HW_H
  37
  38 #include <linux/types.h>
  39
  40 enum {
  41         NCHAN          = 4,     /* # of HW channels */
  42         MAX_MTU        = 9600,  /* max MAC MTU, excluding header + FCS */
  43         EEPROMSIZE     = 17408, /* Serial EEPROM physical size */
  44         EEPROMVSIZE    = 32768, /* Serial EEPROM virtual address space size */
  45         EEPROMPFSIZE   = 1024,  /* EEPROM writable area size for PFn, n>0 */
  46         RSS_NENTRIES   = 2048,  /* # of entries in RSS mapping table */
  47         TCB_SIZE       = 128,   /* TCB size */
  48         NMTUS          = 16,    /* size of MTU table */
  49         NCCTRL_WIN     = 32,    /* # of congestion control windows */
  50         L2T_SIZE       = 4096,  /* # of L2T entries */
  51         MBOX_LEN       = 64,    /* mailbox size in bytes */
  52         TRACE_LEN      = 112,   /* length of trace data and mask */
  53         FILTER_OPT_LEN = 36,    /* filter tuple width for optional components */
  54         NWOL_PAT       = 8,     /* # of WoL patterns */
  55         WOL_PAT_LEN    = 128,   /* length of WoL patterns */
  56 };
  57
  58 enum {
  59         CIM_NUM_IBQ    = 6,     /* # of CIM IBQs */
  60         CIM_NUM_OBQ    = 6,     /* # of CIM OBQs */
  61         CIM_NUM_OBQ_T5 = 8,     /* # of CIM OBQs for T5 adapter */
  62         CIMLA_SIZE     = 2048,  /* # of 32-bit words in CIM LA */
  63         CIM_IBQ_SIZE   = 128,   /* # of 128-bit words in a CIM IBQ */
  64 };
  65
  66 enum {
  67         SF_PAGE_SIZE = 256,           /* serial flash page size */
  68         SF_SEC_SIZE = 64 * 1024,      /* serial flash sector size */
  69 };
  70
  71 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
  72
  73 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV };    /* mailbox owners */
  74
  75 enum {
  76         SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
  77         SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
  78         SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
  79         SGE_MAX_IQ_SIZE = 65520,
  80
  81         SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */
  82         SGE_TIMER_UPD_CIDX = 7,   /* update cidx only */
  83
  84         SGE_EQ_IDXSIZE = 64,      /* egress queue pidx/cidx unit size */
  85
  86         SGE_INTRDST_PCI = 0,      /* interrupt destination is PCI-E */
  87         SGE_INTRDST_IQ = 1,       /*   destination is an ingress queue */
  88
  89         SGE_UPDATEDEL_NONE = 0,   /* ingress queue pidx update delivery */
  90         SGE_UPDATEDEL_INTR = 1,   /*   interrupt */
  91         SGE_UPDATEDEL_STPG = 2,   /*   status page */
  92         SGE_UPDATEDEL_BOTH = 3,   /*   interrupt and status page */
  93
  94         SGE_HOSTFCMODE_NONE = 0,  /* egress queue cidx updates */
  95         SGE_HOSTFCMODE_IQ = 1,    /*   sent to ingress queue */
  96         SGE_HOSTFCMODE_STPG = 2,  /*   sent to status page */
  97         SGE_HOSTFCMODE_BOTH = 3,  /*   ingress queue and status page */
  98
  99         SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */
 100         SGE_FETCHBURSTMIN_32B = 1,
 101         SGE_FETCHBURSTMIN_64B = 2,
 102         SGE_FETCHBURSTMIN_128B = 3,
 103
 104         SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */
 105         SGE_FETCHBURSTMAX_128B = 1,
 106         SGE_FETCHBURSTMAX_256B = 2,
 107         SGE_FETCHBURSTMAX_512B = 3,
 108
 109         SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */
 110         SGE_CIDXFLUSHTHRESH_2 = 1,
 111         SGE_CIDXFLUSHTHRESH_4 = 2,
 112         SGE_CIDXFLUSHTHRESH_8 = 3,
 113         SGE_CIDXFLUSHTHRESH_16 = 4,
 114         SGE_CIDXFLUSHTHRESH_32 = 5,
 115         SGE_CIDXFLUSHTHRESH_64 = 6,
 116         SGE_CIDXFLUSHTHRESH_128 = 7,
 117
 118         SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
 119 };
 120
 121 /* PCI-e memory window access */
 122 enum pcie_memwin {
 123         MEMWIN_NIC      = 0,
 124         MEMWIN_RSVD1    = 1,
 125         MEMWIN_RSVD2    = 2,
 126         MEMWIN_RDMA     = 3,
 127         MEMWIN_RSVD4    = 4,
 128         MEMWIN_FOISCSI  = 5,
 129         MEMWIN_CSIOSTOR = 6,
 130         MEMWIN_RSVD7    = 7,
 131 };
 132
 133 struct sge_qstat {                /* data written to SGE queue status entries */
 134         __be32 qid;
 135         __be16 cidx;
 136         __be16 pidx;
 137 };
 138
 139 /*
 140  * Structure for last 128 bits of response descriptors
 141  */
 142 struct rsp_ctrl {
 143         __be32 hdrbuflen_pidx;
 144         __be32 pldbuflen_qid;
 145         union {
 146                 u8 type_gen;
 147                 __be64 last_flit;
 148         };
 149 };
 150
 151 #define RSPD_NEWBUF 0x80000000U
 152 #define RSPD_LEN(x) (((x) >> 0) & 0x7fffffffU)
 153 #define RSPD_QID(x) RSPD_LEN(x)
 154
 155 #define RSPD_GEN(x)  ((x) >> 7)
 156 #define RSPD_TYPE(x) (((x) >> 4) & 3)
 157
 158 #define V_QINTR_CNT_EN     0x0
 159 #define QINTR_CNT_EN       0x1
 160 #define QINTR_TIMER_IDX(x) ((x) << 1)
 161 #define QINTR_TIMER_IDX_GET(x) (((x) >> 1) & 0x7)
 162
 163 /*
 164  * Flash layout.
 165  */
 166 #define FLASH_START(start)      ((start) * SF_SEC_SIZE)
 167 #define FLASH_MAX_SIZE(nsecs)   ((nsecs) * SF_SEC_SIZE)
 168
 169 enum {
 170         /*
 171          * Various Expansion-ROM boot images, etc.
 172          */
 173         FLASH_EXP_ROM_START_SEC = 0,
 174         FLASH_EXP_ROM_NSECS = 6,
 175         FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
 176         FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
 177
 178         /*
 179          * iSCSI Boot Firmware Table (iBFT) and other driver-related
 180          * parameters ...
 181          */
 182         FLASH_IBFT_START_SEC = 6,
 183         FLASH_IBFT_NSECS = 1,
 184         FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
 185         FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
 186
 187         /*
 188          * Boot configuration data.
 189          */
 190         FLASH_BOOTCFG_START_SEC = 7,
 191         FLASH_BOOTCFG_NSECS = 1,
 192         FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
 193         FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
 194
 195         /*
 196          * Location of firmware image in FLASH.
 197          */
 198         FLASH_FW_START_SEC = 8,
 199         FLASH_FW_NSECS = 16,
 200         FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
 201         FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
 202
 203         /*
 204          * iSCSI persistent/crash information.
 205          */
 206         FLASH_ISCSI_CRASH_START_SEC = 29,
 207         FLASH_ISCSI_CRASH_NSECS = 1,
 208         FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
 209         FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
 210
 211         /*
 212          * FCoE persistent/crash information.
 213          */
 214         FLASH_FCOE_CRASH_START_SEC = 30,
 215         FLASH_FCOE_CRASH_NSECS = 1,
 216         FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
 217         FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
 218
 219         /*
 220          * Location of Firmware Configuration File in FLASH.  Since the FPGA
 221          * "FLASH" is smaller we need to store the Configuration File in a
 222          * different location -- which will overlap the end of the firmware
 223          * image if firmware ever gets that large ...
 224          */
 225         FLASH_CFG_START_SEC = 31,
 226         FLASH_CFG_NSECS = 1,
 227         FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
 228         FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
 229
 230         /* We don't support FLASH devices which can't support the full
 231          * standard set of sections which we need for normal
 232          * operations.
 233          */
 234         FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
 235
 236         FLASH_FPGA_CFG_START_SEC = 15,
 237         FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
 238
 239         /*
 240          * Sectors 32-63 are reserved for FLASH failover.
 241          */
 242 };
 243
 244 #undef FLASH_START
 245 #undef FLASH_MAX_SIZE
 246
 247 #endif /* __T4_HW_H */