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cxgb4, cxgb4i: move struct cpl_rx_data_ddp definition
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / t4_msg.h
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef __T4_MSG_H
36 #define __T4_MSG_H
37
38 #include <linux/types.h>
39
40 enum {
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
45 CPL_GET_TCB = 0x6,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
48 CPL_ABORT_REQ = 0xA,
49 CPL_ABORT_RPL = 0xB,
50 CPL_RX_DATA_ACK = 0xD,
51 CPL_TX_PKT = 0xE,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_TID_RELEASE = 0x1A,
54
55 CPL_CLOSE_LISTSRV_RPL = 0x20,
56 CPL_L2T_WRITE_RPL = 0x23,
57 CPL_PASS_OPEN_RPL = 0x24,
58 CPL_ACT_OPEN_RPL = 0x25,
59 CPL_PEER_CLOSE = 0x26,
60 CPL_ABORT_REQ_RSS = 0x2B,
61 CPL_ABORT_RPL_RSS = 0x2D,
62
63 CPL_CLOSE_CON_RPL = 0x32,
64 CPL_ISCSI_HDR = 0x33,
65 CPL_RDMA_CQE = 0x35,
66 CPL_RDMA_CQE_READ_RSP = 0x36,
67 CPL_RDMA_CQE_ERR = 0x37,
68 CPL_RX_DATA = 0x39,
69 CPL_SET_TCB_RPL = 0x3A,
70 CPL_RX_PKT = 0x3B,
71 CPL_RX_DDP_COMPLETE = 0x3F,
72
73 CPL_ACT_ESTABLISH = 0x40,
74 CPL_PASS_ESTABLISH = 0x41,
75 CPL_RX_DATA_DDP = 0x42,
76 CPL_PASS_ACCEPT_REQ = 0x44,
77 CPL_TRACE_PKT_T5 = 0x48,
78 CPL_RX_ISCSI_DDP = 0x49,
79
80 CPL_RDMA_READ_REQ = 0x60,
81
82 CPL_PASS_OPEN_REQ6 = 0x81,
83 CPL_ACT_OPEN_REQ6 = 0x83,
84
85 CPL_RDMA_TERMINATE = 0xA2,
86 CPL_RDMA_WRITE = 0xA4,
87 CPL_SGE_EGR_UPDATE = 0xA5,
88
89 CPL_TRACE_PKT = 0xB0,
90 CPL_ISCSI_DATA = 0xB2,
91
92 CPL_FW4_MSG = 0xC0,
93 CPL_FW4_PLD = 0xC1,
94 CPL_FW4_ACK = 0xC3,
95
96 CPL_FW6_MSG = 0xE0,
97 CPL_FW6_PLD = 0xE1,
98 CPL_TX_PKT_LSO = 0xED,
99 CPL_TX_PKT_XT = 0xEE,
100
101 NUM_CPL_CMDS
102 };
103
104 enum CPL_error {
105 CPL_ERR_NONE = 0,
106 CPL_ERR_TCAM_FULL = 3,
107 CPL_ERR_BAD_LENGTH = 15,
108 CPL_ERR_BAD_ROUTE = 18,
109 CPL_ERR_CONN_RESET = 20,
110 CPL_ERR_CONN_EXIST_SYNRECV = 21,
111 CPL_ERR_CONN_EXIST = 22,
112 CPL_ERR_ARP_MISS = 23,
113 CPL_ERR_BAD_SYN = 24,
114 CPL_ERR_CONN_TIMEDOUT = 30,
115 CPL_ERR_XMIT_TIMEDOUT = 31,
116 CPL_ERR_PERSIST_TIMEDOUT = 32,
117 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
118 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
119 CPL_ERR_RTX_NEG_ADVICE = 35,
120 CPL_ERR_PERSIST_NEG_ADVICE = 36,
121 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
122 CPL_ERR_ABORT_FAILED = 42,
123 CPL_ERR_IWARP_FLM = 50,
124 };
125
126 enum {
127 CPL_CONN_POLICY_AUTO = 0,
128 CPL_CONN_POLICY_ASK = 1,
129 CPL_CONN_POLICY_FILTER = 2,
130 CPL_CONN_POLICY_DENY = 3
131 };
132
133 enum {
134 ULP_MODE_NONE = 0,
135 ULP_MODE_ISCSI = 2,
136 ULP_MODE_RDMA = 4,
137 ULP_MODE_TCPDDP = 5,
138 ULP_MODE_FCOE = 6,
139 };
140
141 enum {
142 ULP_CRC_HEADER = 1 << 0,
143 ULP_CRC_DATA = 1 << 1
144 };
145
146 enum {
147 CPL_ABORT_SEND_RST = 0,
148 CPL_ABORT_NO_RST,
149 };
150
151 enum { /* TX_PKT_XT checksum types */
152 TX_CSUM_TCP = 0,
153 TX_CSUM_UDP = 1,
154 TX_CSUM_CRC16 = 4,
155 TX_CSUM_CRC32 = 5,
156 TX_CSUM_CRC32C = 6,
157 TX_CSUM_FCOE = 7,
158 TX_CSUM_TCPIP = 8,
159 TX_CSUM_UDPIP = 9,
160 TX_CSUM_TCPIP6 = 10,
161 TX_CSUM_UDPIP6 = 11,
162 TX_CSUM_IP = 12,
163 };
164
165 union opcode_tid {
166 __be32 opcode_tid;
167 u8 opcode;
168 };
169
170 #define CPL_OPCODE_S 24
171 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
172 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
173 #define TID_G(x) ((x) & 0xFFFFFF)
174
175 /* tid is assumed to be 24-bits */
176 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
177
178 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
179
180 /* extract the TID from a CPL command */
181 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
182
183 /* partitioning of TID fields that also carry a queue id */
184 #define TID_TID_S 0
185 #define TID_TID_M 0x3fff
186 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
187
188 #define TID_QID_S 14
189 #define TID_QID_M 0x3ff
190 #define TID_QID_V(x) ((x) << TID_QID_S)
191 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
192
193 struct rss_header {
194 u8 opcode;
195 #if defined(__LITTLE_ENDIAN_BITFIELD)
196 u8 channel:2;
197 u8 filter_hit:1;
198 u8 filter_tid:1;
199 u8 hash_type:2;
200 u8 ipv6:1;
201 u8 send2fw:1;
202 #else
203 u8 send2fw:1;
204 u8 ipv6:1;
205 u8 hash_type:2;
206 u8 filter_tid:1;
207 u8 filter_hit:1;
208 u8 channel:2;
209 #endif
210 __be16 qid;
211 __be32 hash_val;
212 };
213
214 struct work_request_hdr {
215 __be32 wr_hi;
216 __be32 wr_mid;
217 __be64 wr_lo;
218 };
219
220 /* wr_hi fields */
221 #define WR_OP_S 24
222 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
223
224 #define WR_HDR struct work_request_hdr wr
225
226 /* option 0 fields */
227 #define TX_CHAN_S 2
228 #define TX_CHAN_V(x) ((x) << TX_CHAN_S)
229
230 #define ULP_MODE_S 8
231 #define ULP_MODE_V(x) ((x) << ULP_MODE_S)
232
233 #define RCV_BUFSIZ_S 12
234 #define RCV_BUFSIZ_M 0x3FFU
235 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
236
237 #define SMAC_SEL_S 28
238 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
239
240 #define L2T_IDX_S 36
241 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
242
243 #define WND_SCALE_S 50
244 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
245
246 #define KEEP_ALIVE_S 54
247 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
248 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
249
250 #define MSS_IDX_S 60
251 #define MSS_IDX_M 0xF
252 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
253 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
254
255 /* option 2 fields */
256 #define RSS_QUEUE_S 0
257 #define RSS_QUEUE_M 0x3FF
258 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
259 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
260
261 #define RSS_QUEUE_VALID_S 10
262 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
263 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
264
265 #define RX_FC_DISABLE_S 20
266 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
267 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
268
269 #define RX_FC_VALID_S 22
270 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
271 #define RX_FC_VALID_F RX_FC_VALID_V(1U)
272
273 #define RX_CHANNEL_S 26
274 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
275
276 #define WND_SCALE_EN_S 28
277 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
278 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
279
280 #define T5_OPT_2_VALID_S 31
281 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
282 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
283
284 struct cpl_pass_open_req {
285 WR_HDR;
286 union opcode_tid ot;
287 __be16 local_port;
288 __be16 peer_port;
289 __be32 local_ip;
290 __be32 peer_ip;
291 __be64 opt0;
292 __be64 opt1;
293 };
294
295 /* option 0 fields */
296 #define NO_CONG_S 4
297 #define NO_CONG_V(x) ((x) << NO_CONG_S)
298 #define NO_CONG_F NO_CONG_V(1U)
299
300 #define DELACK_S 5
301 #define DELACK_V(x) ((x) << DELACK_S)
302 #define DELACK_F DELACK_V(1U)
303
304 #define DSCP_S 22
305 #define DSCP_M 0x3F
306 #define DSCP_V(x) ((x) << DSCP_S)
307 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
308
309 #define TCAM_BYPASS_S 48
310 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
311 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
312
313 #define NAGLE_S 49
314 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
315 #define NAGLE_F NAGLE_V(1ULL)
316
317 /* option 1 fields */
318 #define SYN_RSS_ENABLE_S 0
319 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
320 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
321
322 #define SYN_RSS_QUEUE_S 2
323 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
324
325 #define CONN_POLICY_S 22
326 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
327
328 struct cpl_pass_open_req6 {
329 WR_HDR;
330 union opcode_tid ot;
331 __be16 local_port;
332 __be16 peer_port;
333 __be64 local_ip_hi;
334 __be64 local_ip_lo;
335 __be64 peer_ip_hi;
336 __be64 peer_ip_lo;
337 __be64 opt0;
338 __be64 opt1;
339 };
340
341 struct cpl_pass_open_rpl {
342 union opcode_tid ot;
343 u8 rsvd[3];
344 u8 status;
345 };
346
347 struct tcp_options {
348 __be16 mss;
349 __u8 wsf;
350 #if defined(__LITTLE_ENDIAN_BITFIELD)
351 __u8:4;
352 __u8 unknown:1;
353 __u8:1;
354 __u8 sack:1;
355 __u8 tstamp:1;
356 #else
357 __u8 tstamp:1;
358 __u8 sack:1;
359 __u8:1;
360 __u8 unknown:1;
361 __u8:4;
362 #endif
363 };
364
365 struct cpl_pass_accept_req {
366 union opcode_tid ot;
367 __be16 rsvd;
368 __be16 len;
369 __be32 hdr_len;
370 __be16 vlan;
371 __be16 l2info;
372 __be32 tos_stid;
373 struct tcp_options tcpopt;
374 };
375
376 /* cpl_pass_accept_req.hdr_len fields */
377 #define SYN_RX_CHAN_S 0
378 #define SYN_RX_CHAN_M 0xF
379 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)
380 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)
381
382 #define TCP_HDR_LEN_S 10
383 #define TCP_HDR_LEN_M 0x3F
384 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)
385 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
386
387 #define IP_HDR_LEN_S 16
388 #define IP_HDR_LEN_M 0x3FF
389 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)
390 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)
391
392 #define ETH_HDR_LEN_S 26
393 #define ETH_HDR_LEN_M 0x1F
394 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)
395 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)
396
397 /* cpl_pass_accept_req.l2info fields */
398 #define SYN_MAC_IDX_S 0
399 #define SYN_MAC_IDX_M 0x1FF
400 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)
401 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)
402
403 #define SYN_XACT_MATCH_S 9
404 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)
405 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U)
406
407 #define SYN_INTF_S 12
408 #define SYN_INTF_M 0xF
409 #define SYN_INTF_V(x) ((x) << SYN_INTF_S)
410 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
411
412 enum { /* TCP congestion control algorithms */
413 CONG_ALG_RENO,
414 CONG_ALG_TAHOE,
415 CONG_ALG_NEWRENO,
416 CONG_ALG_HIGHSPEED
417 };
418
419 #define CONG_CNTRL_S 14
420 #define CONG_CNTRL_M 0x3
421 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)
422 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)
423
424 #define T5_ISS_S 18
425 #define T5_ISS_V(x) ((x) << T5_ISS_S)
426 #define T5_ISS_F T5_ISS_V(1U)
427
428 struct cpl_pass_accept_rpl {
429 WR_HDR;
430 union opcode_tid ot;
431 __be32 opt2;
432 __be64 opt0;
433 };
434
435 /* option 2 fields */
436 #define RX_COALESCE_VALID_S 11
437 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
438 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
439
440 #define RX_COALESCE_S 12
441 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
442
443 #define PACE_S 16
444 #define PACE_V(x) ((x) << PACE_S)
445
446 #define TX_QUEUE_S 23
447 #define TX_QUEUE_M 0x7
448 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
449 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
450
451 #define CCTRL_ECN_S 27
452 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
453 #define CCTRL_ECN_F CCTRL_ECN_V(1U)
454
455 #define TSTAMPS_EN_S 29
456 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
457 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
458
459 #define SACK_EN_S 30
460 #define SACK_EN_V(x) ((x) << SACK_EN_S)
461 #define SACK_EN_F SACK_EN_V(1U)
462
463 struct cpl_t5_pass_accept_rpl {
464 WR_HDR;
465 union opcode_tid ot;
466 __be32 opt2;
467 __be64 opt0;
468 __be32 iss;
469 __be32 rsvd;
470 };
471
472 struct cpl_act_open_req {
473 WR_HDR;
474 union opcode_tid ot;
475 __be16 local_port;
476 __be16 peer_port;
477 __be32 local_ip;
478 __be32 peer_ip;
479 __be64 opt0;
480 __be32 params;
481 __be32 opt2;
482 };
483
484 #define FILTER_TUPLE_S 24
485 #define FILTER_TUPLE_M 0xFFFFFFFFFF
486 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
487 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
488 struct cpl_t5_act_open_req {
489 WR_HDR;
490 union opcode_tid ot;
491 __be16 local_port;
492 __be16 peer_port;
493 __be32 local_ip;
494 __be32 peer_ip;
495 __be64 opt0;
496 __be32 rsvd;
497 __be32 opt2;
498 __be64 params;
499 };
500
501 struct cpl_t6_act_open_req {
502 WR_HDR;
503 union opcode_tid ot;
504 __be16 local_port;
505 __be16 peer_port;
506 __be32 local_ip;
507 __be32 peer_ip;
508 __be64 opt0;
509 __be32 rsvd;
510 __be32 opt2;
511 __be64 params;
512 __be32 rsvd2;
513 __be32 opt3;
514 };
515
516 struct cpl_act_open_req6 {
517 WR_HDR;
518 union opcode_tid ot;
519 __be16 local_port;
520 __be16 peer_port;
521 __be64 local_ip_hi;
522 __be64 local_ip_lo;
523 __be64 peer_ip_hi;
524 __be64 peer_ip_lo;
525 __be64 opt0;
526 __be32 params;
527 __be32 opt2;
528 };
529
530 struct cpl_t5_act_open_req6 {
531 WR_HDR;
532 union opcode_tid ot;
533 __be16 local_port;
534 __be16 peer_port;
535 __be64 local_ip_hi;
536 __be64 local_ip_lo;
537 __be64 peer_ip_hi;
538 __be64 peer_ip_lo;
539 __be64 opt0;
540 __be32 rsvd;
541 __be32 opt2;
542 __be64 params;
543 };
544
545 struct cpl_t6_act_open_req6 {
546 WR_HDR;
547 union opcode_tid ot;
548 __be16 local_port;
549 __be16 peer_port;
550 __be64 local_ip_hi;
551 __be64 local_ip_lo;
552 __be64 peer_ip_hi;
553 __be64 peer_ip_lo;
554 __be64 opt0;
555 __be32 rsvd;
556 __be32 opt2;
557 __be64 params;
558 __be32 rsvd2;
559 __be32 opt3;
560 };
561
562 struct cpl_act_open_rpl {
563 union opcode_tid ot;
564 __be32 atid_status;
565 };
566
567 /* cpl_act_open_rpl.atid_status fields */
568 #define AOPEN_STATUS_S 0
569 #define AOPEN_STATUS_M 0xFF
570 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
571
572 #define AOPEN_ATID_S 8
573 #define AOPEN_ATID_M 0xFFFFFF
574 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
575
576 struct cpl_pass_establish {
577 union opcode_tid ot;
578 __be32 rsvd;
579 __be32 tos_stid;
580 __be16 mac_idx;
581 __be16 tcp_opt;
582 __be32 snd_isn;
583 __be32 rcv_isn;
584 };
585
586 /* cpl_pass_establish.tos_stid fields */
587 #define PASS_OPEN_TID_S 0
588 #define PASS_OPEN_TID_M 0xFFFFFF
589 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
590 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
591
592 #define PASS_OPEN_TOS_S 24
593 #define PASS_OPEN_TOS_M 0xFF
594 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
595 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
596
597 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
598 #define TCPOPT_WSCALE_OK_S 5
599 #define TCPOPT_WSCALE_OK_M 0x1
600 #define TCPOPT_WSCALE_OK_G(x) \
601 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
602
603 #define TCPOPT_SACK_S 6
604 #define TCPOPT_SACK_M 0x1
605 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
606
607 #define TCPOPT_TSTAMP_S 7
608 #define TCPOPT_TSTAMP_M 0x1
609 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
610
611 #define TCPOPT_SND_WSCALE_S 8
612 #define TCPOPT_SND_WSCALE_M 0xF
613 #define TCPOPT_SND_WSCALE_G(x) \
614 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
615
616 #define TCPOPT_MSS_S 12
617 #define TCPOPT_MSS_M 0xF
618 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
619
620 #define T6_TCP_HDR_LEN_S 8
621 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
622 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
623
624 #define T6_IP_HDR_LEN_S 14
625 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
626 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
627
628 #define T6_ETH_HDR_LEN_S 24
629 #define T6_ETH_HDR_LEN_M 0xFF
630 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
631 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
632
633 struct cpl_act_establish {
634 union opcode_tid ot;
635 __be32 rsvd;
636 __be32 tos_atid;
637 __be16 mac_idx;
638 __be16 tcp_opt;
639 __be32 snd_isn;
640 __be32 rcv_isn;
641 };
642
643 struct cpl_get_tcb {
644 WR_HDR;
645 union opcode_tid ot;
646 __be16 reply_ctrl;
647 __be16 cookie;
648 };
649
650 /* cpl_get_tcb.reply_ctrl fields */
651 #define QUEUENO_S 0
652 #define QUEUENO_V(x) ((x) << QUEUENO_S)
653
654 #define REPLY_CHAN_S 14
655 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
656 #define REPLY_CHAN_F REPLY_CHAN_V(1U)
657
658 #define NO_REPLY_S 15
659 #define NO_REPLY_V(x) ((x) << NO_REPLY_S)
660 #define NO_REPLY_F NO_REPLY_V(1U)
661
662 struct cpl_set_tcb_field {
663 WR_HDR;
664 union opcode_tid ot;
665 __be16 reply_ctrl;
666 __be16 word_cookie;
667 __be64 mask;
668 __be64 val;
669 };
670
671 /* cpl_set_tcb_field.word_cookie fields */
672 #define TCB_WORD_S 0
673 #define TCB_WORD(x) ((x) << TCB_WORD_S)
674
675 #define TCB_COOKIE_S 5
676 #define TCB_COOKIE_M 0x7
677 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
678 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
679
680 struct cpl_set_tcb_rpl {
681 union opcode_tid ot;
682 __be16 rsvd;
683 u8 cookie;
684 u8 status;
685 __be64 oldval;
686 };
687
688 struct cpl_close_con_req {
689 WR_HDR;
690 union opcode_tid ot;
691 __be32 rsvd;
692 };
693
694 struct cpl_close_con_rpl {
695 union opcode_tid ot;
696 u8 rsvd[3];
697 u8 status;
698 __be32 snd_nxt;
699 __be32 rcv_nxt;
700 };
701
702 struct cpl_close_listsvr_req {
703 WR_HDR;
704 union opcode_tid ot;
705 __be16 reply_ctrl;
706 __be16 rsvd;
707 };
708
709 /* additional cpl_close_listsvr_req.reply_ctrl field */
710 #define LISTSVR_IPV6_S 14
711 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
712 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
713
714 struct cpl_close_listsvr_rpl {
715 union opcode_tid ot;
716 u8 rsvd[3];
717 u8 status;
718 };
719
720 struct cpl_abort_req_rss {
721 union opcode_tid ot;
722 u8 rsvd[3];
723 u8 status;
724 };
725
726 struct cpl_abort_req {
727 WR_HDR;
728 union opcode_tid ot;
729 __be32 rsvd0;
730 u8 rsvd1;
731 u8 cmd;
732 u8 rsvd2[6];
733 };
734
735 struct cpl_abort_rpl_rss {
736 union opcode_tid ot;
737 u8 rsvd[3];
738 u8 status;
739 };
740
741 struct cpl_abort_rpl {
742 WR_HDR;
743 union opcode_tid ot;
744 __be32 rsvd0;
745 u8 rsvd1;
746 u8 cmd;
747 u8 rsvd2[6];
748 };
749
750 struct cpl_peer_close {
751 union opcode_tid ot;
752 __be32 rcv_nxt;
753 };
754
755 struct cpl_tid_release {
756 WR_HDR;
757 union opcode_tid ot;
758 __be32 rsvd;
759 };
760
761 struct cpl_tx_pkt_core {
762 __be32 ctrl0;
763 __be16 pack;
764 __be16 len;
765 __be64 ctrl1;
766 };
767
768 struct cpl_tx_pkt {
769 WR_HDR;
770 struct cpl_tx_pkt_core c;
771 };
772
773 #define cpl_tx_pkt_xt cpl_tx_pkt
774
775 /* cpl_tx_pkt_core.ctrl0 fields */
776 #define TXPKT_VF_S 0
777 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
778
779 #define TXPKT_PF_S 8
780 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
781
782 #define TXPKT_VF_VLD_S 11
783 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
784 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
785
786 #define TXPKT_OVLAN_IDX_S 12
787 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
788
789 #define TXPKT_T5_OVLAN_IDX_S 12
790 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
791
792 #define TXPKT_INTF_S 16
793 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
794
795 #define TXPKT_INS_OVLAN_S 21
796 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
797 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
798
799 #define TXPKT_OPCODE_S 24
800 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
801
802 /* cpl_tx_pkt_core.ctrl1 fields */
803 #define TXPKT_CSUM_END_S 12
804 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
805
806 #define TXPKT_CSUM_START_S 20
807 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
808
809 #define TXPKT_IPHDR_LEN_S 20
810 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
811
812 #define TXPKT_CSUM_LOC_S 30
813 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
814
815 #define TXPKT_ETHHDR_LEN_S 34
816 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
817
818 #define T6_TXPKT_ETHHDR_LEN_S 32
819 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
820
821 #define TXPKT_CSUM_TYPE_S 40
822 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
823
824 #define TXPKT_VLAN_S 44
825 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
826
827 #define TXPKT_VLAN_VLD_S 60
828 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
829 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
830
831 #define TXPKT_IPCSUM_DIS_S 62
832 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
833 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
834
835 #define TXPKT_L4CSUM_DIS_S 63
836 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
837 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
838
839 struct cpl_tx_pkt_lso_core {
840 __be32 lso_ctrl;
841 __be16 ipid_ofst;
842 __be16 mss;
843 __be32 seqno_offset;
844 __be32 len;
845 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
846 };
847
848 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
849 #define LSO_TCPHDR_LEN_S 0
850 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
851
852 #define LSO_IPHDR_LEN_S 4
853 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
854
855 #define LSO_ETHHDR_LEN_S 16
856 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
857
858 #define LSO_IPV6_S 20
859 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
860 #define LSO_IPV6_F LSO_IPV6_V(1U)
861
862 #define LSO_LAST_SLICE_S 22
863 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
864 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
865
866 #define LSO_FIRST_SLICE_S 23
867 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
868 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
869
870 #define LSO_OPCODE_S 24
871 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
872
873 #define LSO_T5_XFER_SIZE_S 0
874 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
875
876 struct cpl_tx_pkt_lso {
877 WR_HDR;
878 struct cpl_tx_pkt_lso_core c;
879 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
880 };
881
882 struct cpl_iscsi_hdr {
883 union opcode_tid ot;
884 __be16 pdu_len_ddp;
885 __be16 len;
886 __be32 seq;
887 __be16 urg;
888 u8 rsvd;
889 u8 status;
890 };
891
892 /* cpl_iscsi_hdr.pdu_len_ddp fields */
893 #define ISCSI_PDU_LEN_S 0
894 #define ISCSI_PDU_LEN_M 0x7FFF
895 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
896 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
897
898 #define ISCSI_DDP_S 15
899 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
900 #define ISCSI_DDP_F ISCSI_DDP_V(1U)
901
902 struct cpl_rx_data_ddp {
903 union opcode_tid ot;
904 __be16 urg;
905 __be16 len;
906 __be32 seq;
907 union {
908 __be32 nxt_seq;
909 __be32 ddp_report;
910 };
911 __be32 ulp_crc;
912 __be32 ddpvld;
913 };
914
915 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp
916
917 struct cpl_rx_data {
918 union opcode_tid ot;
919 __be16 rsvd;
920 __be16 len;
921 __be32 seq;
922 __be16 urg;
923 #if defined(__LITTLE_ENDIAN_BITFIELD)
924 u8 dack_mode:2;
925 u8 psh:1;
926 u8 heartbeat:1;
927 u8 ddp_off:1;
928 u8 :3;
929 #else
930 u8 :3;
931 u8 ddp_off:1;
932 u8 heartbeat:1;
933 u8 psh:1;
934 u8 dack_mode:2;
935 #endif
936 u8 status;
937 };
938
939 struct cpl_rx_data_ack {
940 WR_HDR;
941 union opcode_tid ot;
942 __be32 credit_dack;
943 };
944
945 /* cpl_rx_data_ack.ack_seq fields */
946 #define RX_CREDITS_S 0
947 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
948
949 #define RX_FORCE_ACK_S 28
950 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
951 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
952
953 struct cpl_rx_pkt {
954 struct rss_header rsshdr;
955 u8 opcode;
956 #if defined(__LITTLE_ENDIAN_BITFIELD)
957 u8 iff:4;
958 u8 csum_calc:1;
959 u8 ipmi_pkt:1;
960 u8 vlan_ex:1;
961 u8 ip_frag:1;
962 #else
963 u8 ip_frag:1;
964 u8 vlan_ex:1;
965 u8 ipmi_pkt:1;
966 u8 csum_calc:1;
967 u8 iff:4;
968 #endif
969 __be16 csum;
970 __be16 vlan;
971 __be16 len;
972 __be32 l2info;
973 __be16 hdr_len;
974 __be16 err_vec;
975 };
976
977 #define RX_T6_ETHHDR_LEN_M 0xFF
978 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
979
980 #define RXF_PSH_S 20
981 #define RXF_PSH_V(x) ((x) << RXF_PSH_S)
982 #define RXF_PSH_F RXF_PSH_V(1U)
983
984 #define RXF_SYN_S 21
985 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
986 #define RXF_SYN_F RXF_SYN_V(1U)
987
988 #define RXF_UDP_S 22
989 #define RXF_UDP_V(x) ((x) << RXF_UDP_S)
990 #define RXF_UDP_F RXF_UDP_V(1U)
991
992 #define RXF_TCP_S 23
993 #define RXF_TCP_V(x) ((x) << RXF_TCP_S)
994 #define RXF_TCP_F RXF_TCP_V(1U)
995
996 #define RXF_IP_S 24
997 #define RXF_IP_V(x) ((x) << RXF_IP_S)
998 #define RXF_IP_F RXF_IP_V(1U)
999
1000 #define RXF_IP6_S 25
1001 #define RXF_IP6_V(x) ((x) << RXF_IP6_S)
1002 #define RXF_IP6_F RXF_IP6_V(1U)
1003
1004 #define RXF_SYN_COOKIE_S 26
1005 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
1006 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
1007
1008 #define RXF_FCOE_S 26
1009 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
1010 #define RXF_FCOE_F RXF_FCOE_V(1U)
1011
1012 #define RXF_LRO_S 27
1013 #define RXF_LRO_V(x) ((x) << RXF_LRO_S)
1014 #define RXF_LRO_F RXF_LRO_V(1U)
1015
1016 /* rx_pkt.l2info fields */
1017 #define RX_ETHHDR_LEN_S 0
1018 #define RX_ETHHDR_LEN_M 0x1F
1019 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
1020 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
1021
1022 #define RX_T5_ETHHDR_LEN_S 0
1023 #define RX_T5_ETHHDR_LEN_M 0x3F
1024 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
1025 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
1026
1027 #define RX_MACIDX_S 8
1028 #define RX_MACIDX_M 0x1FF
1029 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
1030 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
1031
1032 #define RXF_SYN_S 21
1033 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1034 #define RXF_SYN_F RXF_SYN_V(1U)
1035
1036 #define RX_CHAN_S 28
1037 #define RX_CHAN_M 0xF
1038 #define RX_CHAN_V(x) ((x) << RX_CHAN_S)
1039 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
1040
1041 /* rx_pkt.hdr_len fields */
1042 #define RX_TCPHDR_LEN_S 0
1043 #define RX_TCPHDR_LEN_M 0x3F
1044 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
1045 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
1046
1047 #define RX_IPHDR_LEN_S 6
1048 #define RX_IPHDR_LEN_M 0x3FF
1049 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
1050 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
1051
1052 /* rx_pkt.err_vec fields */
1053 #define RXERR_CSUM_S 13
1054 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
1055 #define RXERR_CSUM_F RXERR_CSUM_V(1U)
1056
1057 struct cpl_trace_pkt {
1058 u8 opcode;
1059 u8 intf;
1060 #if defined(__LITTLE_ENDIAN_BITFIELD)
1061 u8 runt:4;
1062 u8 filter_hit:4;
1063 u8 :6;
1064 u8 err:1;
1065 u8 trunc:1;
1066 #else
1067 u8 filter_hit:4;
1068 u8 runt:4;
1069 u8 trunc:1;
1070 u8 err:1;
1071 u8 :6;
1072 #endif
1073 __be16 rsvd;
1074 __be16 len;
1075 __be64 tstamp;
1076 };
1077
1078 struct cpl_t5_trace_pkt {
1079 __u8 opcode;
1080 __u8 intf;
1081 #if defined(__LITTLE_ENDIAN_BITFIELD)
1082 __u8 runt:4;
1083 __u8 filter_hit:4;
1084 __u8:6;
1085 __u8 err:1;
1086 __u8 trunc:1;
1087 #else
1088 __u8 filter_hit:4;
1089 __u8 runt:4;
1090 __u8 trunc:1;
1091 __u8 err:1;
1092 __u8:6;
1093 #endif
1094 __be16 rsvd;
1095 __be16 len;
1096 __be64 tstamp;
1097 __be64 rsvd1;
1098 };
1099
1100 struct cpl_l2t_write_req {
1101 WR_HDR;
1102 union opcode_tid ot;
1103 __be16 params;
1104 __be16 l2t_idx;
1105 __be16 vlan;
1106 u8 dst_mac[6];
1107 };
1108
1109 /* cpl_l2t_write_req.params fields */
1110 #define L2T_W_INFO_S 2
1111 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1112
1113 #define L2T_W_PORT_S 8
1114 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1115
1116 #define L2T_W_NOREPLY_S 15
1117 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1118 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1119
1120 struct cpl_l2t_write_rpl {
1121 union opcode_tid ot;
1122 u8 status;
1123 u8 rsvd[3];
1124 };
1125
1126 struct cpl_rdma_terminate {
1127 union opcode_tid ot;
1128 __be16 rsvd;
1129 __be16 len;
1130 };
1131
1132 struct cpl_sge_egr_update {
1133 __be32 opcode_qid;
1134 __be16 cidx;
1135 __be16 pidx;
1136 };
1137
1138 /* cpl_sge_egr_update.ot fields */
1139 #define EGR_QID_S 0
1140 #define EGR_QID_M 0x1FFFF
1141 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1142
1143 /* cpl_fw*.type values */
1144 enum {
1145 FW_TYPE_CMD_RPL = 0,
1146 FW_TYPE_WR_RPL = 1,
1147 FW_TYPE_CQE = 2,
1148 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1149 FW_TYPE_RSSCPL = 4,
1150 };
1151
1152 struct cpl_fw4_pld {
1153 u8 opcode;
1154 u8 rsvd0[3];
1155 u8 type;
1156 u8 rsvd1;
1157 __be16 len;
1158 __be64 data;
1159 __be64 rsvd2;
1160 };
1161
1162 struct cpl_fw6_pld {
1163 u8 opcode;
1164 u8 rsvd[5];
1165 __be16 len;
1166 __be64 data[4];
1167 };
1168
1169 struct cpl_fw4_msg {
1170 u8 opcode;
1171 u8 type;
1172 __be16 rsvd0;
1173 __be32 rsvd1;
1174 __be64 data[2];
1175 };
1176
1177 struct cpl_fw4_ack {
1178 union opcode_tid ot;
1179 u8 credits;
1180 u8 rsvd0[2];
1181 u8 seq_vld;
1182 __be32 snd_nxt;
1183 __be32 snd_una;
1184 __be64 rsvd1;
1185 };
1186
1187 struct cpl_fw6_msg {
1188 u8 opcode;
1189 u8 type;
1190 __be16 rsvd0;
1191 __be32 rsvd1;
1192 __be64 data[4];
1193 };
1194
1195 /* cpl_fw6_msg.type values */
1196 enum {
1197 FW6_TYPE_CMD_RPL = 0,
1198 FW6_TYPE_WR_RPL = 1,
1199 FW6_TYPE_CQE = 2,
1200 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1201 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
1202 };
1203
1204 struct cpl_fw6_msg_ofld_connection_wr_rpl {
1205 __u64 cookie;
1206 __be32 tid; /* or atid in case of active failure */
1207 __u8 t_state;
1208 __u8 retval;
1209 __u8 rsvd[2];
1210 };
1211
1212 enum {
1213 ULP_TX_MEM_READ = 2,
1214 ULP_TX_MEM_WRITE = 3,
1215 ULP_TX_PKT = 4
1216 };
1217
1218 enum {
1219 ULP_TX_SC_NOOP = 0x80,
1220 ULP_TX_SC_IMM = 0x81,
1221 ULP_TX_SC_DSGL = 0x82,
1222 ULP_TX_SC_ISGL = 0x83
1223 };
1224
1225 #define ULPTX_CMD_S 24
1226 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1227
1228 struct ulptx_sge_pair {
1229 __be32 len[2];
1230 __be64 addr[2];
1231 };
1232
1233 struct ulptx_sgl {
1234 __be32 cmd_nsge;
1235 __be32 len0;
1236 __be64 addr0;
1237 struct ulptx_sge_pair sge[0];
1238 };
1239
1240 struct ulptx_idata {
1241 __be32 cmd_more;
1242 __be32 len;
1243 };
1244
1245 #define ULPTX_NSGE_S 0
1246 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1247
1248 #define ULPTX_MORE_S 23
1249 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1250 #define ULPTX_MORE_F ULPTX_MORE_V(1U)
1251
1252 struct ulp_mem_io {
1253 WR_HDR;
1254 __be32 cmd;
1255 __be32 len16; /* command length */
1256 __be32 dlen; /* data length in 32-byte units */
1257 __be32 lock_addr;
1258 };
1259
1260 #define ULP_MEMIO_LOCK_S 31
1261 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1262 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1263
1264 /* additional ulp_mem_io.cmd fields */
1265 #define ULP_MEMIO_ORDER_S 23
1266 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1267 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1268
1269 #define T5_ULP_MEMIO_IMM_S 23
1270 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1271 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1272
1273 #define T5_ULP_MEMIO_ORDER_S 22
1274 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1275 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
1276
1277 /* ulp_mem_io.lock_addr fields */
1278 #define ULP_MEMIO_ADDR_S 0
1279 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1280
1281 /* ulp_mem_io.dlen fields */
1282 #define ULP_MEMIO_DATA_LEN_S 0
1283 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1284
1285 #endif /* __T4_MSG_H */
Linux kernel - Deliverables
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