2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ
= 0x1,
42 CPL_PASS_ACCEPT_RPL
= 0x2,
43 CPL_ACT_OPEN_REQ
= 0x3,
44 CPL_SET_TCB_FIELD
= 0x5,
46 CPL_CLOSE_CON_REQ
= 0x8,
47 CPL_CLOSE_LISTSRV_REQ
= 0x9,
50 CPL_RX_DATA_ACK
= 0xD,
52 CPL_L2T_WRITE_REQ
= 0x12,
53 CPL_TID_RELEASE
= 0x1A,
55 CPL_CLOSE_LISTSRV_RPL
= 0x20,
56 CPL_L2T_WRITE_RPL
= 0x23,
57 CPL_PASS_OPEN_RPL
= 0x24,
58 CPL_ACT_OPEN_RPL
= 0x25,
59 CPL_PEER_CLOSE
= 0x26,
60 CPL_ABORT_REQ_RSS
= 0x2B,
61 CPL_ABORT_RPL_RSS
= 0x2D,
63 CPL_CLOSE_CON_RPL
= 0x32,
66 CPL_RDMA_CQE_READ_RSP
= 0x36,
67 CPL_RDMA_CQE_ERR
= 0x37,
69 CPL_SET_TCB_RPL
= 0x3A,
71 CPL_RX_DDP_COMPLETE
= 0x3F,
73 CPL_ACT_ESTABLISH
= 0x40,
74 CPL_PASS_ESTABLISH
= 0x41,
75 CPL_RX_DATA_DDP
= 0x42,
76 CPL_PASS_ACCEPT_REQ
= 0x44,
77 CPL_TRACE_PKT_T5
= 0x48,
78 CPL_RX_ISCSI_DDP
= 0x49,
80 CPL_RDMA_READ_REQ
= 0x60,
82 CPL_PASS_OPEN_REQ6
= 0x81,
83 CPL_ACT_OPEN_REQ6
= 0x83,
85 CPL_RDMA_TERMINATE
= 0xA2,
86 CPL_RDMA_WRITE
= 0xA4,
87 CPL_SGE_EGR_UPDATE
= 0xA5,
90 CPL_ISCSI_DATA
= 0xB2,
98 CPL_TX_PKT_LSO
= 0xED,
106 CPL_ERR_TCAM_FULL
= 3,
107 CPL_ERR_BAD_LENGTH
= 15,
108 CPL_ERR_BAD_ROUTE
= 18,
109 CPL_ERR_CONN_RESET
= 20,
110 CPL_ERR_CONN_EXIST_SYNRECV
= 21,
111 CPL_ERR_CONN_EXIST
= 22,
112 CPL_ERR_ARP_MISS
= 23,
113 CPL_ERR_BAD_SYN
= 24,
114 CPL_ERR_CONN_TIMEDOUT
= 30,
115 CPL_ERR_XMIT_TIMEDOUT
= 31,
116 CPL_ERR_PERSIST_TIMEDOUT
= 32,
117 CPL_ERR_FINWAIT2_TIMEDOUT
= 33,
118 CPL_ERR_KEEPALIVE_TIMEDOUT
= 34,
119 CPL_ERR_RTX_NEG_ADVICE
= 35,
120 CPL_ERR_PERSIST_NEG_ADVICE
= 36,
121 CPL_ERR_KEEPALV_NEG_ADVICE
= 37,
122 CPL_ERR_ABORT_FAILED
= 42,
123 CPL_ERR_IWARP_FLM
= 50,
127 CPL_CONN_POLICY_AUTO
= 0,
128 CPL_CONN_POLICY_ASK
= 1,
129 CPL_CONN_POLICY_FILTER
= 2,
130 CPL_CONN_POLICY_DENY
= 3
142 ULP_CRC_HEADER
= 1 << 0,
143 ULP_CRC_DATA
= 1 << 1
147 CPL_ABORT_SEND_RST
= 0,
151 enum { /* TX_PKT_XT checksum types */
170 #define CPL_OPCODE_S 24
171 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
172 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
173 #define TID_G(x) ((x) & 0xFFFFFF)
175 /* tid is assumed to be 24-bits */
176 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
178 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
180 /* extract the TID from a CPL command */
181 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
183 /* partitioning of TID fields that also carry a queue id */
185 #define TID_TID_M 0x3fff
186 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
189 #define TID_QID_M 0x3ff
190 #define TID_QID_V(x) ((x) << TID_QID_S)
191 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
195 #if defined(__LITTLE_ENDIAN_BITFIELD)
214 struct work_request_hdr
{
222 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
224 #define WR_HDR struct work_request_hdr wr
226 /* option 0 fields */
228 #define TX_CHAN_V(x) ((x) << TX_CHAN_S)
231 #define ULP_MODE_V(x) ((x) << ULP_MODE_S)
233 #define RCV_BUFSIZ_S 12
234 #define RCV_BUFSIZ_M 0x3FFU
235 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
237 #define SMAC_SEL_S 28
238 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
241 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
243 #define WND_SCALE_S 50
244 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
246 #define KEEP_ALIVE_S 54
247 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
248 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
251 #define MSS_IDX_M 0xF
252 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
253 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
255 /* option 2 fields */
256 #define RSS_QUEUE_S 0
257 #define RSS_QUEUE_M 0x3FF
258 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
259 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
261 #define RSS_QUEUE_VALID_S 10
262 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
263 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
265 #define RX_FC_DISABLE_S 20
266 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
267 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
269 #define RX_FC_VALID_S 22
270 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
271 #define RX_FC_VALID_F RX_FC_VALID_V(1U)
273 #define RX_CHANNEL_S 26
274 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
276 #define WND_SCALE_EN_S 28
277 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
278 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
280 #define T5_OPT_2_VALID_S 31
281 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
282 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
284 struct cpl_pass_open_req
{
295 /* option 0 fields */
297 #define NO_CONG_V(x) ((x) << NO_CONG_S)
298 #define NO_CONG_F NO_CONG_V(1U)
301 #define DELACK_V(x) ((x) << DELACK_S)
302 #define DELACK_F DELACK_V(1U)
306 #define DSCP_V(x) ((x) << DSCP_S)
307 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
309 #define TCAM_BYPASS_S 48
310 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
311 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
314 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
315 #define NAGLE_F NAGLE_V(1ULL)
317 /* option 1 fields */
318 #define SYN_RSS_ENABLE_S 0
319 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
320 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
322 #define SYN_RSS_QUEUE_S 2
323 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
325 #define CONN_POLICY_S 22
326 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
328 struct cpl_pass_open_req6
{
341 struct cpl_pass_open_rpl
{
347 struct cpl_pass_accept_rpl
{
354 /* option 2 fields */
355 #define RX_COALESCE_VALID_S 11
356 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
357 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
359 #define RX_COALESCE_S 12
360 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
363 #define PACE_V(x) ((x) << PACE_S)
365 #define TX_QUEUE_S 23
366 #define TX_QUEUE_M 0x7
367 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
368 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
370 #define CCTRL_ECN_S 27
371 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
372 #define CCTRL_ECN_F CCTRL_ECN_V(1U)
374 #define TSTAMPS_EN_S 29
375 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
376 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
379 #define SACK_EN_V(x) ((x) << SACK_EN_S)
380 #define SACK_EN_F SACK_EN_V(1U)
382 struct cpl_t5_pass_accept_rpl
{
391 struct cpl_act_open_req
{
403 #define FILTER_TUPLE_S 24
404 #define FILTER_TUPLE_M 0xFFFFFFFFFF
405 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
406 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
407 struct cpl_t5_act_open_req
{
420 struct cpl_t6_act_open_req
{
435 struct cpl_act_open_req6
{
449 struct cpl_t5_act_open_req6
{
464 struct cpl_t6_act_open_req6
{
481 struct cpl_act_open_rpl
{
486 /* cpl_act_open_rpl.atid_status fields */
487 #define AOPEN_STATUS_S 0
488 #define AOPEN_STATUS_M 0xFF
489 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
491 #define AOPEN_ATID_S 8
492 #define AOPEN_ATID_M 0xFFFFFF
493 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
495 struct cpl_pass_establish
{
505 /* cpl_pass_establish.tos_stid fields */
506 #define PASS_OPEN_TID_S 0
507 #define PASS_OPEN_TID_M 0xFFFFFF
508 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
509 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
511 #define PASS_OPEN_TOS_S 24
512 #define PASS_OPEN_TOS_M 0xFF
513 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
514 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
516 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
517 #define TCPOPT_WSCALE_OK_S 5
518 #define TCPOPT_WSCALE_OK_M 0x1
519 #define TCPOPT_WSCALE_OK_G(x) \
520 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
522 #define TCPOPT_SACK_S 6
523 #define TCPOPT_SACK_M 0x1
524 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
526 #define TCPOPT_TSTAMP_S 7
527 #define TCPOPT_TSTAMP_M 0x1
528 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
530 #define TCPOPT_SND_WSCALE_S 8
531 #define TCPOPT_SND_WSCALE_M 0xF
532 #define TCPOPT_SND_WSCALE_G(x) \
533 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
535 #define TCPOPT_MSS_S 12
536 #define TCPOPT_MSS_M 0xF
537 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
539 #define T6_TCP_HDR_LEN_S 8
540 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
541 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
543 #define T6_IP_HDR_LEN_S 14
544 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
545 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
547 #define T6_ETH_HDR_LEN_S 24
548 #define T6_ETH_HDR_LEN_M 0xFF
549 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
550 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
552 struct cpl_act_establish
{
569 /* cpl_get_tcb.reply_ctrl fields */
571 #define QUEUENO_V(x) ((x) << QUEUENO_S)
573 #define REPLY_CHAN_S 14
574 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
575 #define REPLY_CHAN_F REPLY_CHAN_V(1U)
577 #define NO_REPLY_S 15
578 #define NO_REPLY_V(x) ((x) << NO_REPLY_S)
579 #define NO_REPLY_F NO_REPLY_V(1U)
581 struct cpl_set_tcb_field
{
590 /* cpl_set_tcb_field.word_cookie fields */
592 #define TCB_WORD(x) ((x) << TCB_WORD_S)
594 #define TCB_COOKIE_S 5
595 #define TCB_COOKIE_M 0x7
596 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
597 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
599 struct cpl_set_tcb_rpl
{
607 struct cpl_close_con_req
{
613 struct cpl_close_con_rpl
{
621 struct cpl_close_listsvr_req
{
628 /* additional cpl_close_listsvr_req.reply_ctrl field */
629 #define LISTSVR_IPV6_S 14
630 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
631 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
633 struct cpl_close_listsvr_rpl
{
639 struct cpl_abort_req_rss
{
645 struct cpl_abort_req
{
654 struct cpl_abort_rpl_rss
{
660 struct cpl_abort_rpl
{
669 struct cpl_peer_close
{
674 struct cpl_tid_release
{
680 struct cpl_tx_pkt_core
{
689 struct cpl_tx_pkt_core c
;
692 #define cpl_tx_pkt_xt cpl_tx_pkt
694 /* cpl_tx_pkt_core.ctrl0 fields */
696 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
699 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
701 #define TXPKT_VF_VLD_S 11
702 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
703 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
705 #define TXPKT_OVLAN_IDX_S 12
706 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
708 #define TXPKT_T5_OVLAN_IDX_S 12
709 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
711 #define TXPKT_INTF_S 16
712 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
714 #define TXPKT_INS_OVLAN_S 21
715 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
716 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
718 #define TXPKT_OPCODE_S 24
719 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
721 /* cpl_tx_pkt_core.ctrl1 fields */
722 #define TXPKT_CSUM_END_S 12
723 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
725 #define TXPKT_CSUM_START_S 20
726 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
728 #define TXPKT_IPHDR_LEN_S 20
729 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
731 #define TXPKT_CSUM_LOC_S 30
732 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
734 #define TXPKT_ETHHDR_LEN_S 34
735 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
737 #define T6_TXPKT_ETHHDR_LEN_S 32
738 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
740 #define TXPKT_CSUM_TYPE_S 40
741 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
743 #define TXPKT_VLAN_S 44
744 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
746 #define TXPKT_VLAN_VLD_S 60
747 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
748 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
750 #define TXPKT_IPCSUM_DIS_S 62
751 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
752 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
754 #define TXPKT_L4CSUM_DIS_S 63
755 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
756 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
758 struct cpl_tx_pkt_lso_core
{
764 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
767 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
768 #define LSO_TCPHDR_LEN_S 0
769 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
771 #define LSO_IPHDR_LEN_S 4
772 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
774 #define LSO_ETHHDR_LEN_S 16
775 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
777 #define LSO_IPV6_S 20
778 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
779 #define LSO_IPV6_F LSO_IPV6_V(1U)
781 #define LSO_LAST_SLICE_S 22
782 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
783 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
785 #define LSO_FIRST_SLICE_S 23
786 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
787 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
789 #define LSO_OPCODE_S 24
790 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
792 #define LSO_T5_XFER_SIZE_S 0
793 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
795 struct cpl_tx_pkt_lso
{
797 struct cpl_tx_pkt_lso_core c
;
798 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
801 struct cpl_iscsi_hdr
{
811 /* cpl_iscsi_hdr.pdu_len_ddp fields */
812 #define ISCSI_PDU_LEN_S 0
813 #define ISCSI_PDU_LEN_M 0x7FFF
814 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
815 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
817 #define ISCSI_DDP_S 15
818 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
819 #define ISCSI_DDP_F ISCSI_DDP_V(1U)
827 #if defined(__LITTLE_ENDIAN_BITFIELD)
843 struct cpl_rx_data_ack
{
849 /* cpl_rx_data_ack.ack_seq fields */
850 #define RX_CREDITS_S 0
851 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
853 #define RX_FORCE_ACK_S 28
854 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
855 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
858 struct rss_header rsshdr
;
860 #if defined(__LITTLE_ENDIAN_BITFIELD)
881 #define RX_T6_ETHHDR_LEN_M 0xFF
882 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
885 #define RXF_PSH_V(x) ((x) << RXF_PSH_S)
886 #define RXF_PSH_F RXF_PSH_V(1U)
889 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
890 #define RXF_SYN_F RXF_SYN_V(1U)
893 #define RXF_UDP_V(x) ((x) << RXF_UDP_S)
894 #define RXF_UDP_F RXF_UDP_V(1U)
897 #define RXF_TCP_V(x) ((x) << RXF_TCP_S)
898 #define RXF_TCP_F RXF_TCP_V(1U)
901 #define RXF_IP_V(x) ((x) << RXF_IP_S)
902 #define RXF_IP_F RXF_IP_V(1U)
905 #define RXF_IP6_V(x) ((x) << RXF_IP6_S)
906 #define RXF_IP6_F RXF_IP6_V(1U)
908 #define RXF_SYN_COOKIE_S 26
909 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
910 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
912 #define RXF_FCOE_S 26
913 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
914 #define RXF_FCOE_F RXF_FCOE_V(1U)
917 #define RXF_LRO_V(x) ((x) << RXF_LRO_S)
918 #define RXF_LRO_F RXF_LRO_V(1U)
920 /* rx_pkt.l2info fields */
921 #define RX_ETHHDR_LEN_S 0
922 #define RX_ETHHDR_LEN_M 0x1F
923 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
924 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
926 #define RX_T5_ETHHDR_LEN_S 0
927 #define RX_T5_ETHHDR_LEN_M 0x3F
928 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
929 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
931 #define RX_MACIDX_S 8
932 #define RX_MACIDX_M 0x1FF
933 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
934 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
937 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
938 #define RXF_SYN_F RXF_SYN_V(1U)
941 #define RX_CHAN_M 0xF
942 #define RX_CHAN_V(x) ((x) << RX_CHAN_S)
943 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
945 /* rx_pkt.hdr_len fields */
946 #define RX_TCPHDR_LEN_S 0
947 #define RX_TCPHDR_LEN_M 0x3F
948 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
949 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
951 #define RX_IPHDR_LEN_S 6
952 #define RX_IPHDR_LEN_M 0x3FF
953 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
954 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
956 /* rx_pkt.err_vec fields */
957 #define RXERR_CSUM_S 13
958 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
959 #define RXERR_CSUM_F RXERR_CSUM_V(1U)
961 struct cpl_trace_pkt
{
964 #if defined(__LITTLE_ENDIAN_BITFIELD)
982 struct cpl_t5_trace_pkt
{
985 #if defined(__LITTLE_ENDIAN_BITFIELD)
1004 struct cpl_l2t_write_req
{
1006 union opcode_tid ot
;
1013 /* cpl_l2t_write_req.params fields */
1014 #define L2T_W_INFO_S 2
1015 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1017 #define L2T_W_PORT_S 8
1018 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1020 #define L2T_W_NOREPLY_S 15
1021 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1022 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1024 struct cpl_l2t_write_rpl
{
1025 union opcode_tid ot
;
1030 struct cpl_rdma_terminate
{
1031 union opcode_tid ot
;
1036 struct cpl_sge_egr_update
{
1042 /* cpl_sge_egr_update.ot fields */
1044 #define EGR_QID_M 0x1FFFF
1045 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1047 /* cpl_fw*.type values */
1049 FW_TYPE_CMD_RPL
= 0,
1052 FW_TYPE_OFLD_CONNECTION_WR_RPL
= 3,
1056 struct cpl_fw4_pld
{
1066 struct cpl_fw6_pld
{
1073 struct cpl_fw4_msg
{
1081 struct cpl_fw4_ack
{
1082 union opcode_tid ot
;
1091 struct cpl_fw6_msg
{
1099 /* cpl_fw6_msg.type values */
1101 FW6_TYPE_CMD_RPL
= 0,
1102 FW6_TYPE_WR_RPL
= 1,
1104 FW6_TYPE_OFLD_CONNECTION_WR_RPL
= 3,
1105 FW6_TYPE_RSSCPL
= FW_TYPE_RSSCPL
,
1108 struct cpl_fw6_msg_ofld_connection_wr_rpl
{
1110 __be32 tid
; /* or atid in case of active failure */
1117 ULP_TX_MEM_READ
= 2,
1118 ULP_TX_MEM_WRITE
= 3,
1123 ULP_TX_SC_NOOP
= 0x80,
1124 ULP_TX_SC_IMM
= 0x81,
1125 ULP_TX_SC_DSGL
= 0x82,
1126 ULP_TX_SC_ISGL
= 0x83
1129 #define ULPTX_CMD_S 24
1130 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1132 struct ulptx_sge_pair
{
1141 struct ulptx_sge_pair sge
[0];
1144 #define ULPTX_NSGE_S 0
1145 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1147 #define ULPTX_MORE_S 23
1148 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1149 #define ULPTX_MORE_F ULPTX_MORE_V(1U)
1154 __be32 len16
; /* command length */
1155 __be32 dlen
; /* data length in 32-byte units */
1159 #define ULP_MEMIO_LOCK_S 31
1160 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1161 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1163 /* additional ulp_mem_io.cmd fields */
1164 #define ULP_MEMIO_ORDER_S 23
1165 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1166 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1168 #define T5_ULP_MEMIO_IMM_S 23
1169 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1170 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1172 #define T5_ULP_MEMIO_ORDER_S 22
1173 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1174 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
1176 /* ulp_mem_io.lock_addr fields */
1177 #define ULP_MEMIO_ADDR_S 0
1178 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1180 /* ulp_mem_io.dlen fields */
1181 #define ULP_MEMIO_DATA_LEN_S 0
1182 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1184 #endif /* __T4_MSG_H */