drivers/net/ethernet/chelsio/cxgb4/t4_msg.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef __T4_MSG_H
  36 #define __T4_MSG_H
  37
  38 #include <linux/types.h>
  39
  40 enum {
  41         CPL_PASS_OPEN_REQ     = 0x1,
  42         CPL_PASS_ACCEPT_RPL   = 0x2,
  43         CPL_ACT_OPEN_REQ      = 0x3,
  44         CPL_SET_TCB_FIELD     = 0x5,
  45         CPL_GET_TCB           = 0x6,
  46         CPL_CLOSE_CON_REQ     = 0x8,
  47         CPL_CLOSE_LISTSRV_REQ = 0x9,
  48         CPL_ABORT_REQ         = 0xA,
  49         CPL_ABORT_RPL         = 0xB,
  50         CPL_RX_DATA_ACK       = 0xD,
  51         CPL_TX_PKT            = 0xE,
  52         CPL_L2T_WRITE_REQ     = 0x12,
  53         CPL_TID_RELEASE       = 0x1A,
  54
  55         CPL_CLOSE_LISTSRV_RPL = 0x20,
  56         CPL_L2T_WRITE_RPL     = 0x23,
  57         CPL_PASS_OPEN_RPL     = 0x24,
  58         CPL_ACT_OPEN_RPL      = 0x25,
  59         CPL_PEER_CLOSE        = 0x26,
  60         CPL_ABORT_REQ_RSS     = 0x2B,
  61         CPL_ABORT_RPL_RSS     = 0x2D,
  62
  63         CPL_CLOSE_CON_RPL     = 0x32,
  64         CPL_ISCSI_HDR         = 0x33,
  65         CPL_RDMA_CQE          = 0x35,
  66         CPL_RDMA_CQE_READ_RSP = 0x36,
  67         CPL_RDMA_CQE_ERR      = 0x37,
  68         CPL_RX_DATA           = 0x39,
  69         CPL_SET_TCB_RPL       = 0x3A,
  70         CPL_RX_PKT            = 0x3B,
  71         CPL_RX_DDP_COMPLETE   = 0x3F,
  72
  73         CPL_ACT_ESTABLISH     = 0x40,
  74         CPL_PASS_ESTABLISH    = 0x41,
  75         CPL_RX_DATA_DDP       = 0x42,
  76         CPL_PASS_ACCEPT_REQ   = 0x44,
  77         CPL_TRACE_PKT_T5      = 0x48,
  78         CPL_RX_ISCSI_DDP      = 0x49,
  79
  80         CPL_RDMA_READ_REQ     = 0x60,
  81
  82         CPL_PASS_OPEN_REQ6    = 0x81,
  83         CPL_ACT_OPEN_REQ6     = 0x83,
  84
  85         CPL_RDMA_TERMINATE    = 0xA2,
  86         CPL_RDMA_WRITE        = 0xA4,
  87         CPL_SGE_EGR_UPDATE    = 0xA5,
  88
  89         CPL_TRACE_PKT         = 0xB0,
  90         CPL_ISCSI_DATA        = 0xB2,
  91
  92         CPL_FW4_MSG           = 0xC0,
  93         CPL_FW4_PLD           = 0xC1,
  94         CPL_FW4_ACK           = 0xC3,
  95
  96         CPL_FW6_MSG           = 0xE0,
  97         CPL_FW6_PLD           = 0xE1,
  98         CPL_TX_PKT_LSO        = 0xED,
  99         CPL_TX_PKT_XT         = 0xEE,
 100
 101         NUM_CPL_CMDS
 102 };
 103
 104 enum CPL_error {
 105         CPL_ERR_NONE               = 0,
 106         CPL_ERR_TCAM_FULL          = 3,
 107         CPL_ERR_BAD_LENGTH         = 15,
 108         CPL_ERR_BAD_ROUTE          = 18,
 109         CPL_ERR_CONN_RESET         = 20,
 110         CPL_ERR_CONN_EXIST_SYNRECV = 21,
 111         CPL_ERR_CONN_EXIST         = 22,
 112         CPL_ERR_ARP_MISS           = 23,
 113         CPL_ERR_BAD_SYN            = 24,
 114         CPL_ERR_CONN_TIMEDOUT      = 30,
 115         CPL_ERR_XMIT_TIMEDOUT      = 31,
 116         CPL_ERR_PERSIST_TIMEDOUT   = 32,
 117         CPL_ERR_FINWAIT2_TIMEDOUT  = 33,
 118         CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
 119         CPL_ERR_RTX_NEG_ADVICE     = 35,
 120         CPL_ERR_PERSIST_NEG_ADVICE = 36,
 121         CPL_ERR_KEEPALV_NEG_ADVICE = 37,
 122         CPL_ERR_ABORT_FAILED       = 42,
 123         CPL_ERR_IWARP_FLM          = 50,
 124 };
 125
 126 enum {
 127         CPL_CONN_POLICY_AUTO = 0,
 128         CPL_CONN_POLICY_ASK  = 1,
 129         CPL_CONN_POLICY_FILTER = 2,
 130         CPL_CONN_POLICY_DENY = 3
 131 };
 132
 133 enum {
 134         ULP_MODE_NONE          = 0,
 135         ULP_MODE_ISCSI         = 2,
 136         ULP_MODE_RDMA          = 4,
 137         ULP_MODE_TCPDDP        = 5,
 138         ULP_MODE_FCOE          = 6,
 139 };
 140
 141 enum {
 142         ULP_CRC_HEADER = 1 << 0,
 143         ULP_CRC_DATA   = 1 << 1
 144 };
 145
 146 enum {
 147         CPL_ABORT_SEND_RST = 0,
 148         CPL_ABORT_NO_RST,
 149 };
 150
 151 enum {                     /* TX_PKT_XT checksum types */
 152         TX_CSUM_TCP    = 0,
 153         TX_CSUM_UDP    = 1,
 154         TX_CSUM_CRC16  = 4,
 155         TX_CSUM_CRC32  = 5,
 156         TX_CSUM_CRC32C = 6,
 157         TX_CSUM_FCOE   = 7,
 158         TX_CSUM_TCPIP  = 8,
 159         TX_CSUM_UDPIP  = 9,
 160         TX_CSUM_TCPIP6 = 10,
 161         TX_CSUM_UDPIP6 = 11,
 162         TX_CSUM_IP     = 12,
 163 };
 164
 165 union opcode_tid {
 166         __be32 opcode_tid;
 167         u8 opcode;
 168 };
 169
 170 #define CPL_OPCODE_S    24
 171 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
 172 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
 173 #define TID_G(x)    ((x) & 0xFFFFFF)
 174
 175 /* tid is assumed to be 24-bits */
 176 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
 177
 178 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
 179
 180 /* extract the TID from a CPL command */
 181 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
 182
 183 /* partitioning of TID fields that also carry a queue id */
 184 #define TID_TID_S    0
 185 #define TID_TID_M    0x3fff
 186 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
 187
 188 #define TID_QID_S    14
 189 #define TID_QID_M    0x3ff
 190 #define TID_QID_V(x) ((x) << TID_QID_S)
 191 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
 192
 193 struct rss_header {
 194         u8 opcode;
 195 #if defined(__LITTLE_ENDIAN_BITFIELD)
 196         u8 channel:2;
 197         u8 filter_hit:1;
 198         u8 filter_tid:1;
 199         u8 hash_type:2;
 200         u8 ipv6:1;
 201         u8 send2fw:1;
 202 #else
 203         u8 send2fw:1;
 204         u8 ipv6:1;
 205         u8 hash_type:2;
 206         u8 filter_tid:1;
 207         u8 filter_hit:1;
 208         u8 channel:2;
 209 #endif
 210         __be16 qid;
 211         __be32 hash_val;
 212 };
 213
 214 struct work_request_hdr {
 215         __be32 wr_hi;
 216         __be32 wr_mid;
 217         __be64 wr_lo;
 218 };
 219
 220 /* wr_hi fields */
 221 #define WR_OP_S    24
 222 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
 223
 224 #define WR_HDR struct work_request_hdr wr
 225
 226 /* option 0 fields */
 227 #define TX_CHAN_S    2
 228 #define TX_CHAN_V(x) ((x) << TX_CHAN_S)
 229
 230 #define ULP_MODE_S    8
 231 #define ULP_MODE_V(x) ((x) << ULP_MODE_S)
 232
 233 #define RCV_BUFSIZ_S    12
 234 #define RCV_BUFSIZ_M    0x3FFU
 235 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
 236
 237 #define SMAC_SEL_S    28
 238 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
 239
 240 #define L2T_IDX_S    36
 241 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
 242
 243 #define WND_SCALE_S    50
 244 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
 245
 246 #define KEEP_ALIVE_S    54
 247 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
 248 #define KEEP_ALIVE_F    KEEP_ALIVE_V(1ULL)
 249
 250 #define MSS_IDX_S    60
 251 #define MSS_IDX_M    0xF
 252 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
 253 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
 254
 255 /* option 2 fields */
 256 #define RSS_QUEUE_S    0
 257 #define RSS_QUEUE_M    0x3FF
 258 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
 259 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
 260
 261 #define RSS_QUEUE_VALID_S    10
 262 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
 263 #define RSS_QUEUE_VALID_F    RSS_QUEUE_VALID_V(1U)
 264
 265 #define RX_FC_DISABLE_S    20
 266 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
 267 #define RX_FC_DISABLE_F    RX_FC_DISABLE_V(1U)
 268
 269 #define RX_FC_VALID_S    22
 270 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
 271 #define RX_FC_VALID_F    RX_FC_VALID_V(1U)
 272
 273 #define RX_CHANNEL_S    26
 274 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
 275
 276 #define WND_SCALE_EN_S    28
 277 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
 278 #define WND_SCALE_EN_F    WND_SCALE_EN_V(1U)
 279
 280 #define T5_OPT_2_VALID_S    31
 281 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
 282 #define T5_OPT_2_VALID_F    T5_OPT_2_VALID_V(1U)
 283
 284 struct cpl_pass_open_req {
 285         WR_HDR;
 286         union opcode_tid ot;
 287         __be16 local_port;
 288         __be16 peer_port;
 289         __be32 local_ip;
 290         __be32 peer_ip;
 291         __be64 opt0;
 292         __be64 opt1;
 293 };
 294
 295 /* option 0 fields */
 296 #define NO_CONG_S    4
 297 #define NO_CONG_V(x) ((x) << NO_CONG_S)
 298 #define NO_CONG_F    NO_CONG_V(1U)
 299
 300 #define DELACK_S    5
 301 #define DELACK_V(x) ((x) << DELACK_S)
 302 #define DELACK_F    DELACK_V(1U)
 303
 304 #define DSCP_S    22
 305 #define DSCP_M    0x3F
 306 #define DSCP_V(x) ((x) << DSCP_S)
 307 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
 308
 309 #define TCAM_BYPASS_S    48
 310 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
 311 #define TCAM_BYPASS_F    TCAM_BYPASS_V(1ULL)
 312
 313 #define NAGLE_S    49
 314 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
 315 #define NAGLE_F    NAGLE_V(1ULL)
 316
 317 /* option 1 fields */
 318 #define SYN_RSS_ENABLE_S    0
 319 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
 320 #define SYN_RSS_ENABLE_F    SYN_RSS_ENABLE_V(1U)
 321
 322 #define SYN_RSS_QUEUE_S    2
 323 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
 324
 325 #define CONN_POLICY_S    22
 326 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
 327
 328 struct cpl_pass_open_req6 {
 329         WR_HDR;
 330         union opcode_tid ot;
 331         __be16 local_port;
 332         __be16 peer_port;
 333         __be64 local_ip_hi;
 334         __be64 local_ip_lo;
 335         __be64 peer_ip_hi;
 336         __be64 peer_ip_lo;
 337         __be64 opt0;
 338         __be64 opt1;
 339 };
 340
 341 struct cpl_pass_open_rpl {
 342         union opcode_tid ot;
 343         u8 rsvd[3];
 344         u8 status;
 345 };
 346
 347 struct cpl_pass_accept_rpl {
 348         WR_HDR;
 349         union opcode_tid ot;
 350         __be32 opt2;
 351         __be64 opt0;
 352 };
 353
 354 /* option 2 fields */
 355 #define RX_COALESCE_VALID_S    11
 356 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
 357 #define RX_COALESCE_VALID_F    RX_COALESCE_VALID_V(1U)
 358
 359 #define RX_COALESCE_S    12
 360 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
 361
 362 #define PACE_S    16
 363 #define PACE_V(x) ((x) << PACE_S)
 364
 365 #define TX_QUEUE_S    23
 366 #define TX_QUEUE_M    0x7
 367 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
 368 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
 369
 370 #define CCTRL_ECN_S    27
 371 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
 372 #define CCTRL_ECN_F    CCTRL_ECN_V(1U)
 373
 374 #define TSTAMPS_EN_S    29
 375 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
 376 #define TSTAMPS_EN_F    TSTAMPS_EN_V(1U)
 377
 378 #define SACK_EN_S    30
 379 #define SACK_EN_V(x) ((x) << SACK_EN_S)
 380 #define SACK_EN_F    SACK_EN_V(1U)
 381
 382 struct cpl_t5_pass_accept_rpl {
 383         WR_HDR;
 384         union opcode_tid ot;
 385         __be32 opt2;
 386         __be64 opt0;
 387         __be32 iss;
 388         __be32 rsvd;
 389 };
 390
 391 struct cpl_act_open_req {
 392         WR_HDR;
 393         union opcode_tid ot;
 394         __be16 local_port;
 395         __be16 peer_port;
 396         __be32 local_ip;
 397         __be32 peer_ip;
 398         __be64 opt0;
 399         __be32 params;
 400         __be32 opt2;
 401 };
 402
 403 #define FILTER_TUPLE_S  24
 404 #define FILTER_TUPLE_M  0xFFFFFFFFFF
 405 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
 406 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
 407 struct cpl_t5_act_open_req {
 408         WR_HDR;
 409         union opcode_tid ot;
 410         __be16 local_port;
 411         __be16 peer_port;
 412         __be32 local_ip;
 413         __be32 peer_ip;
 414         __be64 opt0;
 415         __be32 rsvd;
 416         __be32 opt2;
 417         __be64 params;
 418 };
 419
 420 struct cpl_t6_act_open_req {
 421         WR_HDR;
 422         union opcode_tid ot;
 423         __be16 local_port;
 424         __be16 peer_port;
 425         __be32 local_ip;
 426         __be32 peer_ip;
 427         __be64 opt0;
 428         __be32 rsvd;
 429         __be32 opt2;
 430         __be64 params;
 431         __be32 rsvd2;
 432         __be32 opt3;
 433 };
 434
 435 struct cpl_act_open_req6 {
 436         WR_HDR;
 437         union opcode_tid ot;
 438         __be16 local_port;
 439         __be16 peer_port;
 440         __be64 local_ip_hi;
 441         __be64 local_ip_lo;
 442         __be64 peer_ip_hi;
 443         __be64 peer_ip_lo;
 444         __be64 opt0;
 445         __be32 params;
 446         __be32 opt2;
 447 };
 448
 449 struct cpl_t5_act_open_req6 {
 450         WR_HDR;
 451         union opcode_tid ot;
 452         __be16 local_port;
 453         __be16 peer_port;
 454         __be64 local_ip_hi;
 455         __be64 local_ip_lo;
 456         __be64 peer_ip_hi;
 457         __be64 peer_ip_lo;
 458         __be64 opt0;
 459         __be32 rsvd;
 460         __be32 opt2;
 461         __be64 params;
 462 };
 463
 464 struct cpl_t6_act_open_req6 {
 465         WR_HDR;
 466         union opcode_tid ot;
 467         __be16 local_port;
 468         __be16 peer_port;
 469         __be64 local_ip_hi;
 470         __be64 local_ip_lo;
 471         __be64 peer_ip_hi;
 472         __be64 peer_ip_lo;
 473         __be64 opt0;
 474         __be32 rsvd;
 475         __be32 opt2;
 476         __be64 params;
 477         __be32 rsvd2;
 478         __be32 opt3;
 479 };
 480
 481 struct cpl_act_open_rpl {
 482         union opcode_tid ot;
 483         __be32 atid_status;
 484 };
 485
 486 /* cpl_act_open_rpl.atid_status fields */
 487 #define AOPEN_STATUS_S    0
 488 #define AOPEN_STATUS_M    0xFF
 489 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
 490
 491 #define AOPEN_ATID_S    8
 492 #define AOPEN_ATID_M    0xFFFFFF
 493 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
 494
 495 struct cpl_pass_establish {
 496         union opcode_tid ot;
 497         __be32 rsvd;
 498         __be32 tos_stid;
 499         __be16 mac_idx;
 500         __be16 tcp_opt;
 501         __be32 snd_isn;
 502         __be32 rcv_isn;
 503 };
 504
 505 /* cpl_pass_establish.tos_stid fields */
 506 #define PASS_OPEN_TID_S    0
 507 #define PASS_OPEN_TID_M    0xFFFFFF
 508 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
 509 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
 510
 511 #define PASS_OPEN_TOS_S    24
 512 #define PASS_OPEN_TOS_M    0xFF
 513 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
 514 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
 515
 516 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
 517 #define TCPOPT_WSCALE_OK_S      5
 518 #define TCPOPT_WSCALE_OK_M      0x1
 519 #define TCPOPT_WSCALE_OK_G(x)   \
 520         (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
 521
 522 #define TCPOPT_SACK_S           6
 523 #define TCPOPT_SACK_M           0x1
 524 #define TCPOPT_SACK_G(x)        (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
 525
 526 #define TCPOPT_TSTAMP_S         7
 527 #define TCPOPT_TSTAMP_M         0x1
 528 #define TCPOPT_TSTAMP_G(x)      (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
 529
 530 #define TCPOPT_SND_WSCALE_S     8
 531 #define TCPOPT_SND_WSCALE_M     0xF
 532 #define TCPOPT_SND_WSCALE_G(x)  \
 533         (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
 534
 535 #define TCPOPT_MSS_S    12
 536 #define TCPOPT_MSS_M    0xF
 537 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
 538
 539 #define T6_TCP_HDR_LEN_S   8
 540 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
 541 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
 542
 543 #define T6_IP_HDR_LEN_S    14
 544 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
 545 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
 546
 547 #define T6_ETH_HDR_LEN_S    24
 548 #define T6_ETH_HDR_LEN_M    0xFF
 549 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
 550 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
 551
 552 struct cpl_act_establish {
 553         union opcode_tid ot;
 554         __be32 rsvd;
 555         __be32 tos_atid;
 556         __be16 mac_idx;
 557         __be16 tcp_opt;
 558         __be32 snd_isn;
 559         __be32 rcv_isn;
 560 };
 561
 562 struct cpl_get_tcb {
 563         WR_HDR;
 564         union opcode_tid ot;
 565         __be16 reply_ctrl;
 566         __be16 cookie;
 567 };
 568
 569 /* cpl_get_tcb.reply_ctrl fields */
 570 #define QUEUENO_S    0
 571 #define QUEUENO_V(x) ((x) << QUEUENO_S)
 572
 573 #define REPLY_CHAN_S    14
 574 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
 575 #define REPLY_CHAN_F    REPLY_CHAN_V(1U)
 576
 577 #define NO_REPLY_S    15
 578 #define NO_REPLY_V(x) ((x) << NO_REPLY_S)
 579 #define NO_REPLY_F    NO_REPLY_V(1U)
 580
 581 struct cpl_set_tcb_field {
 582         WR_HDR;
 583         union opcode_tid ot;
 584         __be16 reply_ctrl;
 585         __be16 word_cookie;
 586         __be64 mask;
 587         __be64 val;
 588 };
 589
 590 /* cpl_set_tcb_field.word_cookie fields */
 591 #define TCB_WORD_S    0
 592 #define TCB_WORD(x)   ((x) << TCB_WORD_S)
 593
 594 #define TCB_COOKIE_S    5
 595 #define TCB_COOKIE_M    0x7
 596 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
 597 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
 598
 599 struct cpl_set_tcb_rpl {
 600         union opcode_tid ot;
 601         __be16 rsvd;
 602         u8 cookie;
 603         u8 status;
 604         __be64 oldval;
 605 };
 606
 607 struct cpl_close_con_req {
 608         WR_HDR;
 609         union opcode_tid ot;
 610         __be32 rsvd;
 611 };
 612
 613 struct cpl_close_con_rpl {
 614         union opcode_tid ot;
 615         u8 rsvd[3];
 616         u8 status;
 617         __be32 snd_nxt;
 618         __be32 rcv_nxt;
 619 };
 620
 621 struct cpl_close_listsvr_req {
 622         WR_HDR;
 623         union opcode_tid ot;
 624         __be16 reply_ctrl;
 625         __be16 rsvd;
 626 };
 627
 628 /* additional cpl_close_listsvr_req.reply_ctrl field */
 629 #define LISTSVR_IPV6_S    14
 630 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
 631 #define LISTSVR_IPV6_F    LISTSVR_IPV6_V(1U)
 632
 633 struct cpl_close_listsvr_rpl {
 634         union opcode_tid ot;
 635         u8 rsvd[3];
 636         u8 status;
 637 };
 638
 639 struct cpl_abort_req_rss {
 640         union opcode_tid ot;
 641         u8 rsvd[3];
 642         u8 status;
 643 };
 644
 645 struct cpl_abort_req {
 646         WR_HDR;
 647         union opcode_tid ot;
 648         __be32 rsvd0;
 649         u8 rsvd1;
 650         u8 cmd;
 651         u8 rsvd2[6];
 652 };
 653
 654 struct cpl_abort_rpl_rss {
 655         union opcode_tid ot;
 656         u8 rsvd[3];
 657         u8 status;
 658 };
 659
 660 struct cpl_abort_rpl {
 661         WR_HDR;
 662         union opcode_tid ot;
 663         __be32 rsvd0;
 664         u8 rsvd1;
 665         u8 cmd;
 666         u8 rsvd2[6];
 667 };
 668
 669 struct cpl_peer_close {
 670         union opcode_tid ot;
 671         __be32 rcv_nxt;
 672 };
 673
 674 struct cpl_tid_release {
 675         WR_HDR;
 676         union opcode_tid ot;
 677         __be32 rsvd;
 678 };
 679
 680 struct cpl_tx_pkt_core {
 681         __be32 ctrl0;
 682         __be16 pack;
 683         __be16 len;
 684         __be64 ctrl1;
 685 };
 686
 687 struct cpl_tx_pkt {
 688         WR_HDR;
 689         struct cpl_tx_pkt_core c;
 690 };
 691
 692 #define cpl_tx_pkt_xt cpl_tx_pkt
 693
 694 /* cpl_tx_pkt_core.ctrl0 fields */
 695 #define TXPKT_VF_S    0
 696 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
 697
 698 #define TXPKT_PF_S    8
 699 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
 700
 701 #define TXPKT_VF_VLD_S    11
 702 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
 703 #define TXPKT_VF_VLD_F    TXPKT_VF_VLD_V(1U)
 704
 705 #define TXPKT_OVLAN_IDX_S    12
 706 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
 707
 708 #define TXPKT_T5_OVLAN_IDX_S    12
 709 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
 710
 711 #define TXPKT_INTF_S    16
 712 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
 713
 714 #define TXPKT_INS_OVLAN_S    21
 715 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
 716 #define TXPKT_INS_OVLAN_F    TXPKT_INS_OVLAN_V(1U)
 717
 718 #define TXPKT_OPCODE_S    24
 719 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
 720
 721 /* cpl_tx_pkt_core.ctrl1 fields */
 722 #define TXPKT_CSUM_END_S    12
 723 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
 724
 725 #define TXPKT_CSUM_START_S    20
 726 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
 727
 728 #define TXPKT_IPHDR_LEN_S    20
 729 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
 730
 731 #define TXPKT_CSUM_LOC_S    30
 732 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
 733
 734 #define TXPKT_ETHHDR_LEN_S    34
 735 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
 736
 737 #define T6_TXPKT_ETHHDR_LEN_S    32
 738 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
 739
 740 #define TXPKT_CSUM_TYPE_S    40
 741 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
 742
 743 #define TXPKT_VLAN_S    44
 744 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
 745
 746 #define TXPKT_VLAN_VLD_S    60
 747 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
 748 #define TXPKT_VLAN_VLD_F    TXPKT_VLAN_VLD_V(1ULL)
 749
 750 #define TXPKT_IPCSUM_DIS_S    62
 751 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
 752 #define TXPKT_IPCSUM_DIS_F    TXPKT_IPCSUM_DIS_V(1ULL)
 753
 754 #define TXPKT_L4CSUM_DIS_S    63
 755 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
 756 #define TXPKT_L4CSUM_DIS_F    TXPKT_L4CSUM_DIS_V(1ULL)
 757
 758 struct cpl_tx_pkt_lso_core {
 759         __be32 lso_ctrl;
 760         __be16 ipid_ofst;
 761         __be16 mss;
 762         __be32 seqno_offset;
 763         __be32 len;
 764         /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
 765 };
 766
 767 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
 768 #define LSO_TCPHDR_LEN_S    0
 769 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
 770
 771 #define LSO_IPHDR_LEN_S    4
 772 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
 773
 774 #define LSO_ETHHDR_LEN_S    16
 775 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
 776
 777 #define LSO_IPV6_S    20
 778 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
 779 #define LSO_IPV6_F    LSO_IPV6_V(1U)
 780
 781 #define LSO_LAST_SLICE_S    22
 782 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
 783 #define LSO_LAST_SLICE_F    LSO_LAST_SLICE_V(1U)
 784
 785 #define LSO_FIRST_SLICE_S    23
 786 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
 787 #define LSO_FIRST_SLICE_F    LSO_FIRST_SLICE_V(1U)
 788
 789 #define LSO_OPCODE_S    24
 790 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
 791
 792 #define LSO_T5_XFER_SIZE_S         0
 793 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
 794
 795 struct cpl_tx_pkt_lso {
 796         WR_HDR;
 797         struct cpl_tx_pkt_lso_core c;
 798         /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
 799 };
 800
 801 struct cpl_iscsi_hdr {
 802         union opcode_tid ot;
 803         __be16 pdu_len_ddp;
 804         __be16 len;
 805         __be32 seq;
 806         __be16 urg;
 807         u8 rsvd;
 808         u8 status;
 809 };
 810
 811 /* cpl_iscsi_hdr.pdu_len_ddp fields */
 812 #define ISCSI_PDU_LEN_S    0
 813 #define ISCSI_PDU_LEN_M    0x7FFF
 814 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
 815 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
 816
 817 #define ISCSI_DDP_S    15
 818 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
 819 #define ISCSI_DDP_F    ISCSI_DDP_V(1U)
 820
 821 struct cpl_rx_data {
 822         union opcode_tid ot;
 823         __be16 rsvd;
 824         __be16 len;
 825         __be32 seq;
 826         __be16 urg;
 827 #if defined(__LITTLE_ENDIAN_BITFIELD)
 828         u8 dack_mode:2;
 829         u8 psh:1;
 830         u8 heartbeat:1;
 831         u8 ddp_off:1;
 832         u8 :3;
 833 #else
 834         u8 :3;
 835         u8 ddp_off:1;
 836         u8 heartbeat:1;
 837         u8 psh:1;
 838         u8 dack_mode:2;
 839 #endif
 840         u8 status;
 841 };
 842
 843 struct cpl_rx_data_ack {
 844         WR_HDR;
 845         union opcode_tid ot;
 846         __be32 credit_dack;
 847 };
 848
 849 /* cpl_rx_data_ack.ack_seq fields */
 850 #define RX_CREDITS_S    0
 851 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
 852
 853 #define RX_FORCE_ACK_S    28
 854 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
 855 #define RX_FORCE_ACK_F    RX_FORCE_ACK_V(1U)
 856
 857 struct cpl_rx_pkt {
 858         struct rss_header rsshdr;
 859         u8 opcode;
 860 #if defined(__LITTLE_ENDIAN_BITFIELD)
 861         u8 iff:4;
 862         u8 csum_calc:1;
 863         u8 ipmi_pkt:1;
 864         u8 vlan_ex:1;
 865         u8 ip_frag:1;
 866 #else
 867         u8 ip_frag:1;
 868         u8 vlan_ex:1;
 869         u8 ipmi_pkt:1;
 870         u8 csum_calc:1;
 871         u8 iff:4;
 872 #endif
 873         __be16 csum;
 874         __be16 vlan;
 875         __be16 len;
 876         __be32 l2info;
 877         __be16 hdr_len;
 878         __be16 err_vec;
 879 };
 880
 881 #define RX_T6_ETHHDR_LEN_M    0xFF
 882 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
 883
 884 #define RXF_PSH_S    20
 885 #define RXF_PSH_V(x) ((x) << RXF_PSH_S)
 886 #define RXF_PSH_F    RXF_PSH_V(1U)
 887
 888 #define RXF_SYN_S    21
 889 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
 890 #define RXF_SYN_F    RXF_SYN_V(1U)
 891
 892 #define RXF_UDP_S    22
 893 #define RXF_UDP_V(x) ((x) << RXF_UDP_S)
 894 #define RXF_UDP_F    RXF_UDP_V(1U)
 895
 896 #define RXF_TCP_S    23
 897 #define RXF_TCP_V(x) ((x) << RXF_TCP_S)
 898 #define RXF_TCP_F    RXF_TCP_V(1U)
 899
 900 #define RXF_IP_S    24
 901 #define RXF_IP_V(x) ((x) << RXF_IP_S)
 902 #define RXF_IP_F    RXF_IP_V(1U)
 903
 904 #define RXF_IP6_S    25
 905 #define RXF_IP6_V(x) ((x) << RXF_IP6_S)
 906 #define RXF_IP6_F    RXF_IP6_V(1U)
 907
 908 #define RXF_SYN_COOKIE_S    26
 909 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
 910 #define RXF_SYN_COOKIE_F    RXF_SYN_COOKIE_V(1U)
 911
 912 #define RXF_FCOE_S    26
 913 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
 914 #define RXF_FCOE_F    RXF_FCOE_V(1U)
 915
 916 #define RXF_LRO_S    27
 917 #define RXF_LRO_V(x) ((x) << RXF_LRO_S)
 918 #define RXF_LRO_F    RXF_LRO_V(1U)
 919
 920 /* rx_pkt.l2info fields */
 921 #define RX_ETHHDR_LEN_S    0
 922 #define RX_ETHHDR_LEN_M    0x1F
 923 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
 924 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
 925
 926 #define RX_T5_ETHHDR_LEN_S    0
 927 #define RX_T5_ETHHDR_LEN_M    0x3F
 928 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
 929 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
 930
 931 #define RX_MACIDX_S    8
 932 #define RX_MACIDX_M    0x1FF
 933 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
 934 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
 935
 936 #define RXF_SYN_S    21
 937 #define RXF_SYN_V(x) ((x) << RXF_SYN_S)
 938 #define RXF_SYN_F    RXF_SYN_V(1U)
 939
 940 #define RX_CHAN_S    28
 941 #define RX_CHAN_M    0xF
 942 #define RX_CHAN_V(x) ((x) << RX_CHAN_S)
 943 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
 944
 945 /* rx_pkt.hdr_len fields */
 946 #define RX_TCPHDR_LEN_S    0
 947 #define RX_TCPHDR_LEN_M    0x3F
 948 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
 949 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
 950
 951 #define RX_IPHDR_LEN_S    6
 952 #define RX_IPHDR_LEN_M    0x3FF
 953 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
 954 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
 955
 956 /* rx_pkt.err_vec fields */
 957 #define RXERR_CSUM_S    13
 958 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
 959 #define RXERR_CSUM_F    RXERR_CSUM_V(1U)
 960
 961 struct cpl_trace_pkt {
 962         u8 opcode;
 963         u8 intf;
 964 #if defined(__LITTLE_ENDIAN_BITFIELD)
 965         u8 runt:4;
 966         u8 filter_hit:4;
 967         u8 :6;
 968         u8 err:1;
 969         u8 trunc:1;
 970 #else
 971         u8 filter_hit:4;
 972         u8 runt:4;
 973         u8 trunc:1;
 974         u8 err:1;
 975         u8 :6;
 976 #endif
 977         __be16 rsvd;
 978         __be16 len;
 979         __be64 tstamp;
 980 };
 981
 982 struct cpl_t5_trace_pkt {
 983         __u8 opcode;
 984         __u8 intf;
 985 #if defined(__LITTLE_ENDIAN_BITFIELD)
 986         __u8 runt:4;
 987         __u8 filter_hit:4;
 988         __u8:6;
 989         __u8 err:1;
 990         __u8 trunc:1;
 991 #else
 992         __u8 filter_hit:4;
 993         __u8 runt:4;
 994         __u8 trunc:1;
 995         __u8 err:1;
 996         __u8:6;
 997 #endif
 998         __be16 rsvd;
 999         __be16 len;
1000         __be64 tstamp;
1001         __be64 rsvd1;
1002 };
1003
1004 struct cpl_l2t_write_req {
1005         WR_HDR;
1006         union opcode_tid ot;
1007         __be16 params;
1008         __be16 l2t_idx;
1009         __be16 vlan;
1010         u8 dst_mac[6];
1011 };
1012
1013 /* cpl_l2t_write_req.params fields */
1014 #define L2T_W_INFO_S    2
1015 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1016
1017 #define L2T_W_PORT_S    8
1018 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1019
1020 #define L2T_W_NOREPLY_S    15
1021 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1022 #define L2T_W_NOREPLY_F    L2T_W_NOREPLY_V(1U)
1023
1024 struct cpl_l2t_write_rpl {
1025         union opcode_tid ot;
1026         u8 status;
1027         u8 rsvd[3];
1028 };
1029
1030 struct cpl_rdma_terminate {
1031         union opcode_tid ot;
1032         __be16 rsvd;
1033         __be16 len;
1034 };
1035
1036 struct cpl_sge_egr_update {
1037         __be32 opcode_qid;
1038         __be16 cidx;
1039         __be16 pidx;
1040 };
1041
1042 /* cpl_sge_egr_update.ot fields */
1043 #define EGR_QID_S    0
1044 #define EGR_QID_M    0x1FFFF
1045 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1046
1047 /* cpl_fw*.type values */
1048 enum {
1049         FW_TYPE_CMD_RPL = 0,
1050         FW_TYPE_WR_RPL = 1,
1051         FW_TYPE_CQE = 2,
1052         FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1053         FW_TYPE_RSSCPL = 4,
1054 };
1055
1056 struct cpl_fw4_pld {
1057         u8 opcode;
1058         u8 rsvd0[3];
1059         u8 type;
1060         u8 rsvd1;
1061         __be16 len;
1062         __be64 data;
1063         __be64 rsvd2;
1064 };
1065
1066 struct cpl_fw6_pld {
1067         u8 opcode;
1068         u8 rsvd[5];
1069         __be16 len;
1070         __be64 data[4];
1071 };
1072
1073 struct cpl_fw4_msg {
1074         u8 opcode;
1075         u8 type;
1076         __be16 rsvd0;
1077         __be32 rsvd1;
1078         __be64 data[2];
1079 };
1080
1081 struct cpl_fw4_ack {
1082         union opcode_tid ot;
1083         u8 credits;
1084         u8 rsvd0[2];
1085         u8 seq_vld;
1086         __be32 snd_nxt;
1087         __be32 snd_una;
1088         __be64 rsvd1;
1089 };
1090
1091 struct cpl_fw6_msg {
1092         u8 opcode;
1093         u8 type;
1094         __be16 rsvd0;
1095         __be32 rsvd1;
1096         __be64 data[4];
1097 };
1098
1099 /* cpl_fw6_msg.type values */
1100 enum {
1101         FW6_TYPE_CMD_RPL = 0,
1102         FW6_TYPE_WR_RPL = 1,
1103         FW6_TYPE_CQE = 2,
1104         FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1105         FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
1106 };
1107
1108 struct cpl_fw6_msg_ofld_connection_wr_rpl {
1109         __u64   cookie;
1110         __be32  tid;    /* or atid in case of active failure */
1111         __u8    t_state;
1112         __u8    retval;
1113         __u8    rsvd[2];
1114 };
1115
1116 enum {
1117         ULP_TX_MEM_READ = 2,
1118         ULP_TX_MEM_WRITE = 3,
1119         ULP_TX_PKT = 4
1120 };
1121
1122 enum {
1123         ULP_TX_SC_NOOP = 0x80,
1124         ULP_TX_SC_IMM  = 0x81,
1125         ULP_TX_SC_DSGL = 0x82,
1126         ULP_TX_SC_ISGL = 0x83
1127 };
1128
1129 #define ULPTX_CMD_S    24
1130 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1131
1132 struct ulptx_sge_pair {
1133         __be32 len[2];
1134         __be64 addr[2];
1135 };
1136
1137 struct ulptx_sgl {
1138         __be32 cmd_nsge;
1139         __be32 len0;
1140         __be64 addr0;
1141         struct ulptx_sge_pair sge[0];
1142 };
1143
1144 #define ULPTX_NSGE_S    0
1145 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1146
1147 #define ULPTX_MORE_S    23
1148 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1149 #define ULPTX_MORE_F    ULPTX_MORE_V(1U)
1150
1151 struct ulp_mem_io {
1152         WR_HDR;
1153         __be32 cmd;
1154         __be32 len16;             /* command length */
1155         __be32 dlen;              /* data length in 32-byte units */
1156         __be32 lock_addr;
1157 };
1158
1159 #define ULP_MEMIO_LOCK_S    31
1160 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1161 #define ULP_MEMIO_LOCK_F    ULP_MEMIO_LOCK_V(1U)
1162
1163 /* additional ulp_mem_io.cmd fields */
1164 #define ULP_MEMIO_ORDER_S    23
1165 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1166 #define ULP_MEMIO_ORDER_F    ULP_MEMIO_ORDER_V(1U)
1167
1168 #define T5_ULP_MEMIO_IMM_S    23
1169 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1170 #define T5_ULP_MEMIO_IMM_F    T5_ULP_MEMIO_IMM_V(1U)
1171
1172 #define T5_ULP_MEMIO_ORDER_S    22
1173 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1174 #define T5_ULP_MEMIO_ORDER_F    T5_ULP_MEMIO_ORDER_V(1U)
1175
1176 /* ulp_mem_io.lock_addr fields */
1177 #define ULP_MEMIO_ADDR_S    0
1178 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1179
1180 /* ulp_mem_io.dlen fields */
1181 #define ULP_MEMIO_DATA_LEN_S    0
1182 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1183
1184 #endif  /* __T4_MSG_H */