2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #include <linux/types.h>
41 CPL_PASS_OPEN_REQ
= 0x1,
42 CPL_PASS_ACCEPT_RPL
= 0x2,
43 CPL_ACT_OPEN_REQ
= 0x3,
44 CPL_SET_TCB_FIELD
= 0x5,
46 CPL_CLOSE_CON_REQ
= 0x8,
47 CPL_CLOSE_LISTSRV_REQ
= 0x9,
50 CPL_RX_DATA_ACK
= 0xD,
52 CPL_L2T_WRITE_REQ
= 0x12,
53 CPL_TID_RELEASE
= 0x1A,
55 CPL_CLOSE_LISTSRV_RPL
= 0x20,
56 CPL_L2T_WRITE_RPL
= 0x23,
57 CPL_PASS_OPEN_RPL
= 0x24,
58 CPL_ACT_OPEN_RPL
= 0x25,
59 CPL_PEER_CLOSE
= 0x26,
60 CPL_ABORT_REQ_RSS
= 0x2B,
61 CPL_ABORT_RPL_RSS
= 0x2D,
63 CPL_CLOSE_CON_RPL
= 0x32,
66 CPL_RDMA_CQE_READ_RSP
= 0x36,
67 CPL_RDMA_CQE_ERR
= 0x37,
69 CPL_SET_TCB_RPL
= 0x3A,
71 CPL_RX_DDP_COMPLETE
= 0x3F,
73 CPL_ACT_ESTABLISH
= 0x40,
74 CPL_PASS_ESTABLISH
= 0x41,
75 CPL_RX_DATA_DDP
= 0x42,
76 CPL_PASS_ACCEPT_REQ
= 0x44,
77 CPL_TRACE_PKT_T5
= 0x48,
79 CPL_RDMA_READ_REQ
= 0x60,
81 CPL_PASS_OPEN_REQ6
= 0x81,
82 CPL_ACT_OPEN_REQ6
= 0x83,
84 CPL_RDMA_TERMINATE
= 0xA2,
85 CPL_RDMA_WRITE
= 0xA4,
86 CPL_SGE_EGR_UPDATE
= 0xA5,
96 CPL_TX_PKT_LSO
= 0xED,
104 CPL_ERR_TCAM_FULL
= 3,
105 CPL_ERR_BAD_LENGTH
= 15,
106 CPL_ERR_BAD_ROUTE
= 18,
107 CPL_ERR_CONN_RESET
= 20,
108 CPL_ERR_CONN_EXIST_SYNRECV
= 21,
109 CPL_ERR_CONN_EXIST
= 22,
110 CPL_ERR_ARP_MISS
= 23,
111 CPL_ERR_BAD_SYN
= 24,
112 CPL_ERR_CONN_TIMEDOUT
= 30,
113 CPL_ERR_XMIT_TIMEDOUT
= 31,
114 CPL_ERR_PERSIST_TIMEDOUT
= 32,
115 CPL_ERR_FINWAIT2_TIMEDOUT
= 33,
116 CPL_ERR_KEEPALIVE_TIMEDOUT
= 34,
117 CPL_ERR_RTX_NEG_ADVICE
= 35,
118 CPL_ERR_PERSIST_NEG_ADVICE
= 36,
119 CPL_ERR_ABORT_FAILED
= 42,
120 CPL_ERR_IWARP_FLM
= 50,
132 ULP_CRC_HEADER
= 1 << 0,
133 ULP_CRC_DATA
= 1 << 1
137 CPL_ABORT_SEND_RST
= 0,
141 enum { /* TX_PKT_XT checksum types */
160 #define CPL_OPCODE(x) ((x) << 24)
161 #define G_CPL_OPCODE(x) (((x) >> 24) & 0xFF)
162 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE(opcode) | (tid))
163 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
164 #define GET_TID(cmd) (ntohl(OPCODE_TID(cmd)) & 0xFFFFFF)
166 /* partitioning of TID fields that also carry a queue id */
167 #define GET_TID_TID(x) ((x) & 0x3fff)
168 #define GET_TID_QID(x) (((x) >> 14) & 0x3ff)
169 #define TID_QID(x) ((x) << 14)
173 #if defined(__LITTLE_ENDIAN_BITFIELD)
192 struct work_request_hdr
{
200 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
202 #define WR_HDR struct work_request_hdr wr
204 /* option 0 fields */
206 #define M_MSS_IDX 0xF
207 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
208 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
210 /* option 2 fields */
211 #define S_RSS_QUEUE 0
212 #define M_RSS_QUEUE 0x3FF
213 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
214 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
216 struct cpl_pass_open_req
{
224 #define TX_CHAN(x) ((x) << 2)
225 #define NO_CONG(x) ((x) << 4)
226 #define DELACK(x) ((x) << 5)
227 #define ULP_MODE(x) ((x) << 8)
228 #define RCV_BUFSIZ(x) ((x) << 12)
229 #define DSCP(x) ((x) << 22)
230 #define SMAC_SEL(x) ((u64)(x) << 28)
231 #define L2T_IDX(x) ((u64)(x) << 36)
232 #define TCAM_BYPASS(x) ((u64)(x) << 48)
233 #define NAGLE(x) ((u64)(x) << 49)
234 #define WND_SCALE(x) ((u64)(x) << 50)
235 #define KEEP_ALIVE(x) ((u64)(x) << 54)
236 #define MSS_IDX(x) ((u64)(x) << 60)
238 #define SYN_RSS_ENABLE (1 << 0)
239 #define SYN_RSS_QUEUE(x) ((x) << 2)
240 #define CONN_POLICY_ASK (1 << 22)
243 struct cpl_pass_open_req6
{
256 struct cpl_pass_open_rpl
{
262 struct cpl_pass_accept_rpl
{
266 #define RSS_QUEUE(x) ((x) << 0)
267 #define RSS_QUEUE_VALID (1 << 10)
268 #define RX_COALESCE_VALID(x) ((x) << 11)
269 #define RX_COALESCE(x) ((x) << 12)
270 #define PACE(x) ((x) << 16)
271 #define TX_QUEUE(x) ((x) << 23)
272 #define RX_CHANNEL(x) ((x) << 26)
273 #define CCTRL_ECN(x) ((x) << 27)
274 #define WND_SCALE_EN(x) ((x) << 28)
275 #define TSTAMPS_EN(x) ((x) << 29)
276 #define SACK_EN(x) ((x) << 30)
280 struct cpl_act_open_req
{
292 #define S_FILTER_TUPLE 24
293 #define M_FILTER_TUPLE 0xFFFFFFFFFF
294 #define V_FILTER_TUPLE(x) ((x) << S_FILTER_TUPLE)
295 #define G_FILTER_TUPLE(x) (((x) >> S_FILTER_TUPLE) & M_FILTER_TUPLE)
296 struct cpl_t5_act_open_req
{
309 struct cpl_act_open_req6
{
323 struct cpl_t5_act_open_req6
{
338 struct cpl_act_open_rpl
{
341 #define GET_AOPEN_STATUS(x) ((x) & 0xff)
342 #define GET_AOPEN_ATID(x) (((x) >> 8) & 0xffffff)
345 struct cpl_pass_establish
{
349 #define PASS_OPEN_TID(x) ((x) << 0)
350 #define PASS_OPEN_TOS(x) ((x) << 24)
351 #define GET_PASS_OPEN_TID(x) (((x) >> 0) & 0xFFFFFF)
352 #define GET_POPEN_TID(x) ((x) & 0xffffff)
353 #define GET_POPEN_TOS(x) (((x) >> 24) & 0xff)
356 #define GET_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
357 #define GET_TCPOPT_SACK(x) (((x) >> 6) & 1)
358 #define GET_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
359 #define GET_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
360 #define GET_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
365 struct cpl_act_establish
{
379 #define QUEUENO(x) ((x) << 0)
380 #define REPLY_CHAN(x) ((x) << 14)
381 #define NO_REPLY(x) ((x) << 15)
385 struct cpl_set_tcb_field
{
390 #define TCB_WORD(x) ((x) << 0)
391 #define TCB_COOKIE(x) ((x) << 5)
392 #define GET_TCB_COOKIE(x) (((x) >> 5) & 7)
397 struct cpl_set_tcb_rpl
{
405 struct cpl_close_con_req
{
411 struct cpl_close_con_rpl
{
419 struct cpl_close_listsvr_req
{
423 #define LISTSVR_IPV6(x) ((x) << 14)
427 struct cpl_close_listsvr_rpl
{
433 struct cpl_abort_req_rss
{
439 struct cpl_abort_req
{
448 struct cpl_abort_rpl_rss
{
454 struct cpl_abort_rpl
{
463 struct cpl_peer_close
{
468 struct cpl_tid_release
{
474 struct cpl_tx_pkt_core
{
476 #define TXPKT_VF(x) ((x) << 0)
477 #define TXPKT_PF(x) ((x) << 8)
478 #define TXPKT_VF_VLD (1 << 11)
479 #define TXPKT_OVLAN_IDX(x) ((x) << 12)
480 #define TXPKT_INTF(x) ((x) << 16)
481 #define TXPKT_INS_OVLAN (1 << 21)
482 #define TXPKT_OPCODE(x) ((x) << 24)
486 #define TXPKT_CSUM_END(x) ((x) << 12)
487 #define TXPKT_CSUM_START(x) ((x) << 20)
488 #define TXPKT_IPHDR_LEN(x) ((u64)(x) << 20)
489 #define TXPKT_CSUM_LOC(x) ((u64)(x) << 30)
490 #define TXPKT_ETHHDR_LEN(x) ((u64)(x) << 34)
491 #define TXPKT_CSUM_TYPE(x) ((u64)(x) << 40)
492 #define TXPKT_VLAN(x) ((u64)(x) << 44)
493 #define TXPKT_VLAN_VLD (1ULL << 60)
494 #define TXPKT_IPCSUM_DIS (1ULL << 62)
495 #define TXPKT_L4CSUM_DIS (1ULL << 63)
500 struct cpl_tx_pkt_core c
;
503 #define cpl_tx_pkt_xt cpl_tx_pkt
505 struct cpl_tx_pkt_lso_core
{
507 #define LSO_TCPHDR_LEN(x) ((x) << 0)
508 #define LSO_IPHDR_LEN(x) ((x) << 4)
509 #define LSO_ETHHDR_LEN(x) ((x) << 16)
510 #define LSO_IPV6(x) ((x) << 20)
511 #define LSO_LAST_SLICE (1 << 22)
512 #define LSO_FIRST_SLICE (1 << 23)
513 #define LSO_OPCODE(x) ((x) << 24)
518 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
521 struct cpl_tx_pkt_lso
{
523 struct cpl_tx_pkt_lso_core c
;
524 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
527 struct cpl_iscsi_hdr
{
530 #define ISCSI_PDU_LEN(x) ((x) & 0x7FFF)
531 #define ISCSI_DDP (1 << 15)
545 #if defined(__LITTLE_ENDIAN_BITFIELD)
561 struct cpl_rx_data_ack
{
565 #define RX_CREDITS(x) ((x) << 0)
566 #define RX_FORCE_ACK(x) ((x) << 28)
570 struct rss_header rsshdr
;
572 #if defined(__LITTLE_ENDIAN_BITFIELD)
589 #define RXF_UDP (1 << 22)
590 #define RXF_TCP (1 << 23)
591 #define RXF_IP (1 << 24)
592 #define RXF_IP6 (1 << 25)
597 /* rx_pkt.l2info fields */
598 #define S_RX_ETHHDR_LEN 0
599 #define M_RX_ETHHDR_LEN 0x1F
600 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
601 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
603 #define S_RX_T5_ETHHDR_LEN 0
604 #define M_RX_T5_ETHHDR_LEN 0x3F
605 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
606 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
608 #define S_RX_MACIDX 8
609 #define M_RX_MACIDX 0x1FF
610 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
611 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
614 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
615 #define F_RXF_SYN V_RXF_SYN(1U)
618 #define M_RX_CHAN 0xF
619 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
620 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
622 /* rx_pkt.hdr_len fields */
623 #define S_RX_TCPHDR_LEN 0
624 #define M_RX_TCPHDR_LEN 0x3F
625 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
626 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
628 #define S_RX_IPHDR_LEN 6
629 #define M_RX_IPHDR_LEN 0x3FF
630 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
631 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
633 struct cpl_trace_pkt
{
636 #if defined(__LITTLE_ENDIAN_BITFIELD)
654 struct cpl_t5_trace_pkt
{
657 #if defined(__LITTLE_ENDIAN_BITFIELD)
676 struct cpl_l2t_write_req
{
680 #define L2T_W_INFO(x) ((x) << 2)
681 #define L2T_W_PORT(x) ((x) << 8)
682 #define L2T_W_NOREPLY(x) ((x) << 15)
688 struct cpl_l2t_write_rpl
{
694 struct cpl_rdma_terminate
{
700 struct cpl_sge_egr_update
{
702 #define EGR_QID(x) ((x) & 0x1FFFF)
707 /* cpl_fw*.type values */
712 FW_TYPE_OFLD_CONNECTION_WR_RPL
= 3,
759 /* cpl_fw6_msg.type values */
761 FW6_TYPE_CMD_RPL
= 0,
764 FW6_TYPE_OFLD_CONNECTION_WR_RPL
= 3,
765 FW6_TYPE_RSSCPL
= FW_TYPE_RSSCPL
,
768 struct cpl_fw6_msg_ofld_connection_wr_rpl
{
770 __be32 tid
; /* or atid in case of active failure */
778 ULP_TX_MEM_WRITE
= 3,
783 ULP_TX_SC_NOOP
= 0x80,
784 ULP_TX_SC_IMM
= 0x81,
785 ULP_TX_SC_DSGL
= 0x82,
786 ULP_TX_SC_ISGL
= 0x83
789 struct ulptx_sge_pair
{
796 #define ULPTX_CMD(x) ((x) << 24)
797 #define ULPTX_NSGE(x) ((x) << 0)
798 #define ULPTX_MORE (1U << 23)
801 struct ulptx_sge_pair sge
[0];
807 #define ULP_MEMIO_ORDER(x) ((x) << 23)
808 __be32 len16
; /* command length */
809 __be32 dlen
; /* data length in 32-byte units */
810 #define ULP_MEMIO_DATA_LEN(x) ((x) << 0)
812 #define ULP_MEMIO_ADDR(x) ((x) << 0)
813 #define ULP_MEMIO_LOCK(x) ((x) << 31)
816 #define S_T5_ULP_MEMIO_IMM 23
817 #define V_T5_ULP_MEMIO_IMM(x) ((x) << S_T5_ULP_MEMIO_IMM)
818 #define F_T5_ULP_MEMIO_IMM V_T5_ULP_MEMIO_IMM(1U)
820 #define S_T5_ULP_MEMIO_ORDER 22
821 #define V_T5_ULP_MEMIO_ORDER(x) ((x) << S_T5_ULP_MEMIO_ORDER)
822 #define F_T5_ULP_MEMIO_ORDER V_T5_ULP_MEMIO_ORDER(1U)
824 #endif /* __T4_MSG_H */