drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef __T4_REGS_H
  36 #define __T4_REGS_H
  37
  38 #define MYPF_BASE 0x1b000
  39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
  40
  41 #define PF0_BASE 0x1e000
  42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
  43
  44 #define PF_STRIDE 0x400
  45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
  46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
  47
  48 #define MYPORT_BASE 0x1c000
  49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
  50
  51 #define PORT0_BASE 0x20000
  52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
  53
  54 #define PORT_STRIDE 0x2000
  55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
  56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
  57
  58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
  59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
  60
  61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
  62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
  63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
  64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
  65
  66 #define SGE_PF_KDOORBELL 0x0
  67 #define  QID_MASK    0xffff8000U
  68 #define  QID_SHIFT   15
  69 #define  QID(x)      ((x) << QID_SHIFT)
  70 #define  DBPRIO(x)   ((x) << 14)
  71 #define  DBTYPE(x)   ((x) << 13)
  72 #define  PIDX_MASK   0x00003fffU
  73 #define  PIDX_SHIFT  0
  74 #define  PIDX(x)     ((x) << PIDX_SHIFT)
  75 #define  S_PIDX_T5   0
  76 #define  M_PIDX_T5   0x1fffU
  77 #define  PIDX_T5(x)  (((x) >> S_PIDX_T5) & M_PIDX_T5)
  78
  79
  80 #define SGE_PF_GTS 0x4
  81 #define  INGRESSQID_MASK   0xffff0000U
  82 #define  INGRESSQID_SHIFT  16
  83 #define  INGRESSQID(x)     ((x) << INGRESSQID_SHIFT)
  84 #define  TIMERREG_MASK     0x0000e000U
  85 #define  TIMERREG_SHIFT    13
  86 #define  TIMERREG(x)       ((x) << TIMERREG_SHIFT)
  87 #define  SEINTARM_MASK     0x00001000U
  88 #define  SEINTARM_SHIFT    12
  89 #define  SEINTARM(x)       ((x) << SEINTARM_SHIFT)
  90 #define  CIDXINC_MASK      0x00000fffU
  91 #define  CIDXINC_SHIFT     0
  92 #define  CIDXINC(x)        ((x) << CIDXINC_SHIFT)
  93
  94 #define X_RXPKTCPLMODE_SPLIT     1
  95 #define X_INGPADBOUNDARY_SHIFT 5
  96
  97 #define SGE_CONTROL 0x1008
  98 #define  DCASYSTYPE             0x00080000U
  99 #define  RXPKTCPLMODE_MASK      0x00040000U
 100 #define  RXPKTCPLMODE_SHIFT     18
 101 #define  RXPKTCPLMODE(x)        ((x) << RXPKTCPLMODE_SHIFT)
 102 #define  EGRSTATUSPAGESIZE_MASK  0x00020000U
 103 #define  EGRSTATUSPAGESIZE_SHIFT 17
 104 #define  EGRSTATUSPAGESIZE(x)    ((x) << EGRSTATUSPAGESIZE_SHIFT)
 105 #define  PKTSHIFT_MASK          0x00001c00U
 106 #define  PKTSHIFT_SHIFT         10
 107 #define  PKTSHIFT(x)            ((x) << PKTSHIFT_SHIFT)
 108 #define  PKTSHIFT_GET(x)        (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT)
 109 #define  INGPCIEBOUNDARY_MASK   0x00000380U
 110 #define  INGPCIEBOUNDARY_SHIFT  7
 111 #define  INGPCIEBOUNDARY(x)     ((x) << INGPCIEBOUNDARY_SHIFT)
 112 #define  INGPADBOUNDARY_MASK    0x00000070U
 113 #define  INGPADBOUNDARY_SHIFT   4
 114 #define  INGPADBOUNDARY(x)      ((x) << INGPADBOUNDARY_SHIFT)
 115 #define  INGPADBOUNDARY_GET(x)  (((x) & INGPADBOUNDARY_MASK) \
 116                                  >> INGPADBOUNDARY_SHIFT)
 117 #define  EGRPCIEBOUNDARY_MASK   0x0000000eU
 118 #define  EGRPCIEBOUNDARY_SHIFT  1
 119 #define  EGRPCIEBOUNDARY(x)     ((x) << EGRPCIEBOUNDARY_SHIFT)
 120 #define  GLOBALENABLE           0x00000001U
 121
 122 #define SGE_HOST_PAGE_SIZE 0x100c
 123
 124 #define  HOSTPAGESIZEPF7_MASK   0x0000000fU
 125 #define  HOSTPAGESIZEPF7_SHIFT  28
 126 #define  HOSTPAGESIZEPF7(x)     ((x) << HOSTPAGESIZEPF7_SHIFT)
 127
 128 #define  HOSTPAGESIZEPF6_MASK   0x0000000fU
 129 #define  HOSTPAGESIZEPF6_SHIFT  24
 130 #define  HOSTPAGESIZEPF6(x)     ((x) << HOSTPAGESIZEPF6_SHIFT)
 131
 132 #define  HOSTPAGESIZEPF5_MASK   0x0000000fU
 133 #define  HOSTPAGESIZEPF5_SHIFT  20
 134 #define  HOSTPAGESIZEPF5(x)     ((x) << HOSTPAGESIZEPF5_SHIFT)
 135
 136 #define  HOSTPAGESIZEPF4_MASK   0x0000000fU
 137 #define  HOSTPAGESIZEPF4_SHIFT  16
 138 #define  HOSTPAGESIZEPF4(x)     ((x) << HOSTPAGESIZEPF4_SHIFT)
 139
 140 #define  HOSTPAGESIZEPF3_MASK   0x0000000fU
 141 #define  HOSTPAGESIZEPF3_SHIFT  12
 142 #define  HOSTPAGESIZEPF3(x)     ((x) << HOSTPAGESIZEPF3_SHIFT)
 143
 144 #define  HOSTPAGESIZEPF2_MASK   0x0000000fU
 145 #define  HOSTPAGESIZEPF2_SHIFT  8
 146 #define  HOSTPAGESIZEPF2(x)     ((x) << HOSTPAGESIZEPF2_SHIFT)
 147
 148 #define  HOSTPAGESIZEPF1_MASK   0x0000000fU
 149 #define  HOSTPAGESIZEPF1_SHIFT  4
 150 #define  HOSTPAGESIZEPF1(x)     ((x) << HOSTPAGESIZEPF1_SHIFT)
 151
 152 #define  HOSTPAGESIZEPF0_MASK   0x0000000fU
 153 #define  HOSTPAGESIZEPF0_SHIFT  0
 154 #define  HOSTPAGESIZEPF0(x)     ((x) << HOSTPAGESIZEPF0_SHIFT)
 155
 156 #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
 157 #define  QUEUESPERPAGEPF0_MASK   0x0000000fU
 158 #define  QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK)
 159
 160 #define QUEUESPERPAGEPF1    4
 161
 162 #define SGE_INT_CAUSE1 0x1024
 163 #define SGE_INT_CAUSE2 0x1030
 164 #define SGE_INT_CAUSE3 0x103c
 165 #define  ERR_FLM_DBP               0x80000000U
 166 #define  ERR_FLM_IDMA1             0x40000000U
 167 #define  ERR_FLM_IDMA0             0x20000000U
 168 #define  ERR_FLM_HINT              0x10000000U
 169 #define  ERR_PCIE_ERROR3           0x08000000U
 170 #define  ERR_PCIE_ERROR2           0x04000000U
 171 #define  ERR_PCIE_ERROR1           0x02000000U
 172 #define  ERR_PCIE_ERROR0           0x01000000U
 173 #define  ERR_TIMER_ABOVE_MAX_QID   0x00800000U
 174 #define  ERR_CPL_EXCEED_IQE_SIZE   0x00400000U
 175 #define  ERR_INVALID_CIDX_INC      0x00200000U
 176 #define  ERR_ITP_TIME_PAUSED       0x00100000U
 177 #define  ERR_CPL_OPCODE_0          0x00080000U
 178 #define  ERR_DROPPED_DB            0x00040000U
 179 #define  ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U
 180 #define  ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U
 181 #define  ERR_BAD_DB_PIDX3          0x00008000U
 182 #define  ERR_BAD_DB_PIDX2          0x00004000U
 183 #define  ERR_BAD_DB_PIDX1          0x00002000U
 184 #define  ERR_BAD_DB_PIDX0          0x00001000U
 185 #define  ERR_ING_PCIE_CHAN         0x00000800U
 186 #define  ERR_ING_CTXT_PRIO         0x00000400U
 187 #define  ERR_EGR_CTXT_PRIO         0x00000200U
 188 #define  DBFIFO_HP_INT             0x00000100U
 189 #define  DBFIFO_LP_INT             0x00000080U
 190 #define  REG_ADDRESS_ERR           0x00000040U
 191 #define  INGRESS_SIZE_ERR          0x00000020U
 192 #define  EGRESS_SIZE_ERR           0x00000010U
 193 #define  ERR_INV_CTXT3             0x00000008U
 194 #define  ERR_INV_CTXT2             0x00000004U
 195 #define  ERR_INV_CTXT1             0x00000002U
 196 #define  ERR_INV_CTXT0             0x00000001U
 197
 198 #define SGE_INT_ENABLE3 0x1040
 199 #define SGE_FL_BUFFER_SIZE0 0x1044
 200 #define SGE_FL_BUFFER_SIZE1 0x1048
 201 #define SGE_FL_BUFFER_SIZE2 0x104c
 202 #define SGE_FL_BUFFER_SIZE3 0x1050
 203 #define SGE_FL_BUFFER_SIZE4 0x1054
 204 #define SGE_FL_BUFFER_SIZE5 0x1058
 205 #define SGE_FL_BUFFER_SIZE6 0x105c
 206 #define SGE_FL_BUFFER_SIZE7 0x1060
 207 #define SGE_FL_BUFFER_SIZE8 0x1064
 208
 209 #define SGE_INGRESS_RX_THRESHOLD 0x10a0
 210 #define  THRESHOLD_0_MASK   0x3f000000U
 211 #define  THRESHOLD_0_SHIFT  24
 212 #define  THRESHOLD_0(x)     ((x) << THRESHOLD_0_SHIFT)
 213 #define  THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)
 214 #define  THRESHOLD_1_MASK   0x003f0000U
 215 #define  THRESHOLD_1_SHIFT  16
 216 #define  THRESHOLD_1(x)     ((x) << THRESHOLD_1_SHIFT)
 217 #define  THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)
 218 #define  THRESHOLD_2_MASK   0x00003f00U
 219 #define  THRESHOLD_2_SHIFT  8
 220 #define  THRESHOLD_2(x)     ((x) << THRESHOLD_2_SHIFT)
 221 #define  THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)
 222 #define  THRESHOLD_3_MASK   0x0000003fU
 223 #define  THRESHOLD_3_SHIFT  0
 224 #define  THRESHOLD_3(x)     ((x) << THRESHOLD_3_SHIFT)
 225 #define  THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
 226
 227 #define SGE_CONM_CTRL 0x1094
 228 #define  EGRTHRESHOLD_MASK   0x00003f00U
 229 #define  EGRTHRESHOLDshift   8
 230 #define  EGRTHRESHOLD(x)     ((x) << EGRTHRESHOLDshift)
 231 #define  EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
 232
 233 #define EGRTHRESHOLDPACKING_MASK        0x3fU
 234 #define EGRTHRESHOLDPACKING_SHIFT       14
 235 #define EGRTHRESHOLDPACKING(x)          ((x) << EGRTHRESHOLDPACKING_SHIFT)
 236 #define EGRTHRESHOLDPACKING_GET(x)      (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \
 237                                           EGRTHRESHOLDPACKING_MASK)
 238
 239 #define SGE_DBFIFO_STATUS 0x10a4
 240 #define  HP_INT_THRESH_SHIFT 28
 241 #define  HP_INT_THRESH_MASK  0xfU
 242 #define  HP_INT_THRESH(x)    ((x) << HP_INT_THRESH_SHIFT)
 243 #define  LP_INT_THRESH_SHIFT 12
 244 #define  LP_INT_THRESH_MASK  0xfU
 245 #define  LP_INT_THRESH(x)    ((x) << LP_INT_THRESH_SHIFT)
 246
 247 #define SGE_DOORBELL_CONTROL 0x10a8
 248 #define  ENABLE_DROP        (1 << 13)
 249
 250 #define S_NOCOALESCE    26
 251 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
 252 #define F_NOCOALESCE    V_NOCOALESCE(1U)
 253
 254 #define SGE_TIMESTAMP_LO 0x1098
 255 #define SGE_TIMESTAMP_HI 0x109c
 256 #define S_TSVAL    0
 257 #define M_TSVAL    0xfffffffU
 258 #define GET_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
 259
 260 #define SGE_TIMER_VALUE_0_AND_1 0x10b8
 261 #define  TIMERVALUE0_MASK   0xffff0000U
 262 #define  TIMERVALUE0_SHIFT  16
 263 #define  TIMERVALUE0(x)     ((x) << TIMERVALUE0_SHIFT)
 264 #define  TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
 265 #define  TIMERVALUE1_MASK   0x0000ffffU
 266 #define  TIMERVALUE1_SHIFT  0
 267 #define  TIMERVALUE1(x)     ((x) << TIMERVALUE1_SHIFT)
 268 #define  TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
 269
 270 #define SGE_TIMER_VALUE_2_AND_3 0x10bc
 271 #define  TIMERVALUE2_MASK   0xffff0000U
 272 #define  TIMERVALUE2_SHIFT  16
 273 #define  TIMERVALUE2(x)     ((x) << TIMERVALUE2_SHIFT)
 274 #define  TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
 275 #define  TIMERVALUE3_MASK   0x0000ffffU
 276 #define  TIMERVALUE3_SHIFT  0
 277 #define  TIMERVALUE3(x)     ((x) << TIMERVALUE3_SHIFT)
 278 #define  TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
 279
 280 #define SGE_TIMER_VALUE_4_AND_5 0x10c0
 281 #define  TIMERVALUE4_MASK   0xffff0000U
 282 #define  TIMERVALUE4_SHIFT  16
 283 #define  TIMERVALUE4(x)     ((x) << TIMERVALUE4_SHIFT)
 284 #define  TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
 285 #define  TIMERVALUE5_MASK   0x0000ffffU
 286 #define  TIMERVALUE5_SHIFT  0
 287 #define  TIMERVALUE5(x)     ((x) << TIMERVALUE5_SHIFT)
 288 #define  TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
 289
 290 #define SGE_DEBUG_INDEX 0x10cc
 291 #define SGE_DEBUG_DATA_HIGH 0x10d0
 292 #define SGE_DEBUG_DATA_LOW 0x10d4
 293 #define SGE_DEBUG_DATA_LOW_INDEX_2      0x12c8
 294 #define SGE_DEBUG_DATA_LOW_INDEX_3      0x12cc
 295 #define SGE_DEBUG_DATA_HIGH_INDEX_10    0x12a8
 296 #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
 297
 298 #define S_HP_INT_THRESH    28
 299 #define M_HP_INT_THRESH 0xfU
 300 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
 301 #define S_LP_INT_THRESH_T5    18
 302 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
 303 #define M_LP_COUNT_T5    0x3ffffU
 304 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5)
 305 #define M_HP_COUNT 0x7ffU
 306 #define S_HP_COUNT 16
 307 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
 308 #define S_LP_INT_THRESH    12
 309 #define M_LP_INT_THRESH 0xfU
 310 #define M_LP_INT_THRESH_T5    0xfffU
 311 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
 312 #define M_LP_COUNT 0x7ffU
 313 #define S_LP_COUNT 0
 314 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
 315 #define A_SGE_DBFIFO_STATUS 0x10a4
 316
 317 #define SGE_STAT_TOTAL 0x10e4
 318 #define SGE_STAT_MATCH 0x10e8
 319
 320 #define SGE_STAT_CFG   0x10ec
 321 #define S_STATSOURCE_T5    9
 322 #define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
 323
 324 #define SGE_DBFIFO_STATUS2 0x1118
 325 #define M_HP_COUNT_T5    0x3ffU
 326 #define G_HP_COUNT_T5(x) ((x)  & M_HP_COUNT_T5)
 327 #define S_HP_INT_THRESH_T5    10
 328 #define M_HP_INT_THRESH_T5    0xfU
 329 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
 330
 331 #define S_ENABLE_DROP    13
 332 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
 333 #define F_ENABLE_DROP    V_ENABLE_DROP(1U)
 334 #define S_DROPPED_DB 0
 335 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
 336 #define F_DROPPED_DB V_DROPPED_DB(1U)
 337 #define A_SGE_DOORBELL_CONTROL 0x10a8
 338
 339 #define A_SGE_CTXT_CMD 0x11fc
 340 #define A_SGE_DBQ_CTXT_BADDR 0x1084
 341
 342 #define PCIE_PF_CFG 0x40
 343 #define  AIVEC(x)       ((x) << 4)
 344 #define  AIVEC_MASK     0x3ffU
 345
 346 #define PCIE_PF_CLI 0x44
 347 #define PCIE_INT_CAUSE 0x3004
 348 #define  UNXSPLCPLERR  0x20000000U
 349 #define  PCIEPINT      0x10000000U
 350 #define  PCIESINT      0x08000000U
 351 #define  RPLPERR       0x04000000U
 352 #define  RXWRPERR      0x02000000U
 353 #define  RXCPLPERR     0x01000000U
 354 #define  PIOTAGPERR    0x00800000U
 355 #define  MATAGPERR     0x00400000U
 356 #define  INTXCLRPERR   0x00200000U
 357 #define  FIDPERR       0x00100000U
 358 #define  CFGSNPPERR    0x00080000U
 359 #define  HRSPPERR      0x00040000U
 360 #define  HREQPERR      0x00020000U
 361 #define  HCNTPERR      0x00010000U
 362 #define  DRSPPERR      0x00008000U
 363 #define  DREQPERR      0x00004000U
 364 #define  DCNTPERR      0x00002000U
 365 #define  CRSPPERR      0x00001000U
 366 #define  CREQPERR      0x00000800U
 367 #define  CCNTPERR      0x00000400U
 368 #define  TARTAGPERR    0x00000200U
 369 #define  PIOREQPERR    0x00000100U
 370 #define  PIOCPLPERR    0x00000080U
 371 #define  MSIXDIPERR    0x00000040U
 372 #define  MSIXDATAPERR  0x00000020U
 373 #define  MSIXADDRHPERR 0x00000010U
 374 #define  MSIXADDRLPERR 0x00000008U
 375 #define  MSIDATAPERR   0x00000004U
 376 #define  MSIADDRHPERR  0x00000002U
 377 #define  MSIADDRLPERR  0x00000001U
 378
 379 #define  READRSPERR      0x20000000U
 380 #define  TRGT1GRPPERR    0x10000000U
 381 #define  IPSOTPERR       0x08000000U
 382 #define  IPRXDATAGRPPERR 0x02000000U
 383 #define  IPRXHDRGRPPERR  0x01000000U
 384 #define  MAGRPPERR       0x00400000U
 385 #define  VFIDPERR        0x00200000U
 386 #define  HREQWRPERR      0x00010000U
 387 #define  DREQWRPERR      0x00002000U
 388 #define  MSTTAGQPERR     0x00000400U
 389 #define  PIOREQGRPPERR   0x00000100U
 390 #define  PIOCPLGRPPERR   0x00000080U
 391 #define  MSIXSTIPERR     0x00000004U
 392 #define  MSTTIMEOUTPERR  0x00000002U
 393 #define  MSTGRPPERR      0x00000001U
 394
 395 #define PCIE_NONFAT_ERR 0x3010
 396 #define PCIE_CFG_SPACE_REQ 0x3060
 397 #define PCIE_CFG_SPACE_DATA 0x3064
 398 #define PCIE_MEM_ACCESS_BASE_WIN 0x3068
 399 #define S_PCIEOFST       10
 400 #define M_PCIEOFST       0x3fffffU
 401 #define GET_PCIEOFST(x)  (((x) >> S_PCIEOFST) & M_PCIEOFST)
 402 #define  PCIEOFST_MASK   0xfffffc00U
 403 #define  BIR_MASK        0x00000300U
 404 #define  BIR_SHIFT       8
 405 #define  BIR(x)          ((x) << BIR_SHIFT)
 406 #define  WINDOW_MASK     0x000000ffU
 407 #define  WINDOW_SHIFT    0
 408 #define  WINDOW(x)       ((x) << WINDOW_SHIFT)
 409 #define  GET_WINDOW(x)   (((x) >> WINDOW_SHIFT) & WINDOW_MASK)
 410 #define PCIE_MEM_ACCESS_OFFSET 0x306c
 411 #define ENABLE  (1U << 30)
 412 #define FUNCTION(x) ((x) << 12)
 413 #define F_LOCALCFG    (1U << 28)
 414
 415 #define S_PFNUM    0
 416 #define V_PFNUM(x) ((x) << S_PFNUM)
 417
 418 #define PCIE_FW 0x30b8
 419 #define  PCIE_FW_ERR            0x80000000U
 420 #define  PCIE_FW_INIT           0x40000000U
 421 #define  PCIE_FW_HALT           0x20000000U
 422 #define  PCIE_FW_MASTER_VLD     0x00008000U
 423 #define  PCIE_FW_MASTER(x)      ((x) << 12)
 424 #define  PCIE_FW_MASTER_MASK    0x7
 425 #define  PCIE_FW_MASTER_GET(x)  (((x) >> 12) & PCIE_FW_MASTER_MASK)
 426
 427 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
 428 #define  RNPP 0x80000000U
 429 #define  RPCP 0x20000000U
 430 #define  RCIP 0x08000000U
 431 #define  RCCP 0x04000000U
 432 #define  RFTP 0x00800000U
 433 #define  PTRP 0x00100000U
 434
 435 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
 436 #define  TPCP 0x40000000U
 437 #define  TNPP 0x20000000U
 438 #define  TFTP 0x10000000U
 439 #define  TCAP 0x08000000U
 440 #define  TCIP 0x04000000U
 441 #define  RCAP 0x02000000U
 442 #define  PLUP 0x00800000U
 443 #define  PLDN 0x00400000U
 444 #define  OTDD 0x00200000U
 445 #define  GTRP 0x00100000U
 446 #define  RDPE 0x00040000U
 447 #define  TDCE 0x00020000U
 448 #define  TDUE 0x00010000U
 449
 450 #define MC_INT_CAUSE 0x7518
 451 #define  ECC_UE_INT_CAUSE 0x00000004U
 452 #define  ECC_CE_INT_CAUSE 0x00000002U
 453 #define  PERR_INT_CAUSE   0x00000001U
 454
 455 #define MC_ECC_STATUS 0x751c
 456 #define  ECC_CECNT_MASK   0xffff0000U
 457 #define  ECC_CECNT_SHIFT  16
 458 #define  ECC_CECNT(x)     ((x) << ECC_CECNT_SHIFT)
 459 #define  ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)
 460 #define  ECC_UECNT_MASK   0x0000ffffU
 461 #define  ECC_UECNT_SHIFT  0
 462 #define  ECC_UECNT(x)     ((x) << ECC_UECNT_SHIFT)
 463 #define  ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)
 464
 465 #define MC_BIST_CMD 0x7600
 466 #define  START_BIST          0x80000000U
 467 #define  BIST_CMD_GAP_MASK   0x0000ff00U
 468 #define  BIST_CMD_GAP_SHIFT  8
 469 #define  BIST_CMD_GAP(x)     ((x) << BIST_CMD_GAP_SHIFT)
 470 #define  BIST_OPCODE_MASK    0x00000003U
 471 #define  BIST_OPCODE_SHIFT   0
 472 #define  BIST_OPCODE(x)      ((x) << BIST_OPCODE_SHIFT)
 473
 474 #define MC_BIST_CMD_ADDR 0x7604
 475 #define MC_BIST_CMD_LEN 0x7608
 476 #define MC_BIST_DATA_PATTERN 0x760c
 477 #define  BIST_DATA_TYPE_MASK   0x0000000fU
 478 #define  BIST_DATA_TYPE_SHIFT  0
 479 #define  BIST_DATA_TYPE(x)     ((x) << BIST_DATA_TYPE_SHIFT)
 480
 481 #define MC_BIST_STATUS_RDATA 0x7688
 482
 483 #define MA_EDRAM0_BAR 0x77c0
 484 #define MA_EDRAM1_BAR 0x77c4
 485 #define EDRAM_SIZE_MASK   0xfffU
 486 #define EDRAM_SIZE_GET(x) ((x) & EDRAM_SIZE_MASK)
 487
 488 #define MA_EXT_MEMORY_BAR 0x77c8
 489 #define  EXT_MEM_SIZE_MASK   0x00000fffU
 490 #define  EXT_MEM_SIZE_SHIFT  0
 491 #define  EXT_MEM_SIZE_GET(x) (((x) & EXT_MEM_SIZE_MASK) >> EXT_MEM_SIZE_SHIFT)
 492
 493 #define MA_TARGET_MEM_ENABLE 0x77d8
 494 #define  EXT_MEM1_ENABLE 0x00000010U
 495 #define  EXT_MEM_ENABLE 0x00000004U
 496 #define  EDRAM1_ENABLE  0x00000002U
 497 #define  EDRAM0_ENABLE  0x00000001U
 498
 499 #define MA_INT_CAUSE 0x77e0
 500 #define  MEM_PERR_INT_CAUSE 0x00000002U
 501 #define  MEM_WRAP_INT_CAUSE 0x00000001U
 502
 503 #define MA_INT_WRAP_STATUS 0x77e4
 504 #define  MEM_WRAP_ADDRESS_MASK   0xfffffff0U
 505 #define  MEM_WRAP_ADDRESS_SHIFT  4
 506 #define  MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)
 507 #define  MEM_WRAP_CLIENT_NUM_MASK   0x0000000fU
 508 #define  MEM_WRAP_CLIENT_NUM_SHIFT  0
 509 #define  MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
 510 #define MA_PCIE_FW 0x30b8
 511 #define MA_PARITY_ERROR_STATUS 0x77f4
 512
 513 #define MA_EXT_MEMORY1_BAR 0x7808
 514 #define EDC_0_BASE_ADDR 0x7900
 515
 516 #define EDC_BIST_CMD 0x7904
 517 #define EDC_BIST_CMD_ADDR 0x7908
 518 #define EDC_BIST_CMD_LEN 0x790c
 519 #define EDC_BIST_DATA_PATTERN 0x7910
 520 #define EDC_BIST_STATUS_RDATA 0x7928
 521 #define EDC_INT_CAUSE 0x7978
 522 #define  ECC_UE_PAR     0x00000020U
 523 #define  ECC_CE_PAR     0x00000010U
 524 #define  PERR_PAR_CAUSE 0x00000008U
 525
 526 #define EDC_ECC_STATUS 0x797c
 527
 528 #define EDC_1_BASE_ADDR 0x7980
 529
 530 #define CIM_BOOT_CFG 0x7b00
 531 #define  BOOTADDR_MASK 0xffffff00U
 532 #define  UPCRST        0x1U
 533
 534 #define CIM_PF_MAILBOX_DATA 0x240
 535 #define CIM_PF_MAILBOX_CTRL 0x280
 536 #define  MBMSGVALID     0x00000008U
 537 #define  MBINTREQ       0x00000004U
 538 #define  MBOWNER_MASK   0x00000003U
 539 #define  MBOWNER_SHIFT  0
 540 #define  MBOWNER(x)     ((x) << MBOWNER_SHIFT)
 541 #define  MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
 542
 543 #define CIM_PF_HOST_INT_ENABLE 0x288
 544 #define  MBMSGRDYINTEN(x) ((x) << 19)
 545
 546 #define CIM_PF_HOST_INT_CAUSE 0x28c
 547 #define  MBMSGRDYINT 0x00080000U
 548
 549 #define CIM_HOST_INT_CAUSE 0x7b2c
 550 #define  TIEQOUTPARERRINT  0x00100000U
 551 #define  TIEQINPARERRINT   0x00080000U
 552 #define  MBHOSTPARERR      0x00040000U
 553 #define  MBUPPARERR        0x00020000U
 554 #define  IBQPARERR         0x0001f800U
 555 #define  IBQTP0PARERR      0x00010000U
 556 #define  IBQTP1PARERR      0x00008000U
 557 #define  IBQULPPARERR      0x00004000U
 558 #define  IBQSGELOPARERR    0x00002000U
 559 #define  IBQSGEHIPARERR    0x00001000U
 560 #define  IBQNCSIPARERR     0x00000800U
 561 #define  OBQPARERR         0x000007e0U
 562 #define  OBQULP0PARERR     0x00000400U
 563 #define  OBQULP1PARERR     0x00000200U
 564 #define  OBQULP2PARERR     0x00000100U
 565 #define  OBQULP3PARERR     0x00000080U
 566 #define  OBQSGEPARERR      0x00000040U
 567 #define  OBQNCSIPARERR     0x00000020U
 568 #define  PREFDROPINT       0x00000002U
 569 #define  UPACCNONZERO      0x00000001U
 570
 571 #define CIM_HOST_UPACC_INT_CAUSE 0x7b34
 572 #define  EEPROMWRINT      0x40000000U
 573 #define  TIMEOUTMAINT     0x20000000U
 574 #define  TIMEOUTINT       0x10000000U
 575 #define  RSPOVRLOOKUPINT  0x08000000U
 576 #define  REQOVRLOOKUPINT  0x04000000U
 577 #define  BLKWRPLINT       0x02000000U
 578 #define  BLKRDPLINT       0x01000000U
 579 #define  SGLWRPLINT       0x00800000U
 580 #define  SGLRDPLINT       0x00400000U
 581 #define  BLKWRCTLINT      0x00200000U
 582 #define  BLKRDCTLINT      0x00100000U
 583 #define  SGLWRCTLINT      0x00080000U
 584 #define  SGLRDCTLINT      0x00040000U
 585 #define  BLKWREEPROMINT   0x00020000U
 586 #define  BLKRDEEPROMINT   0x00010000U
 587 #define  SGLWREEPROMINT   0x00008000U
 588 #define  SGLRDEEPROMINT   0x00004000U
 589 #define  BLKWRFLASHINT    0x00002000U
 590 #define  BLKRDFLASHINT    0x00001000U
 591 #define  SGLWRFLASHINT    0x00000800U
 592 #define  SGLRDFLASHINT    0x00000400U
 593 #define  BLKWRBOOTINT     0x00000200U
 594 #define  BLKRDBOOTINT     0x00000100U
 595 #define  SGLWRBOOTINT     0x00000080U
 596 #define  SGLRDBOOTINT     0x00000040U
 597 #define  ILLWRBEINT       0x00000020U
 598 #define  ILLRDBEINT       0x00000010U
 599 #define  ILLRDINT         0x00000008U
 600 #define  ILLWRINT         0x00000004U
 601 #define  ILLTRANSINT      0x00000002U
 602 #define  RSVDSPACEINT     0x00000001U
 603
 604 #define TP_OUT_CONFIG 0x7d04
 605 #define  VLANEXTENABLE_MASK  0x0000f000U
 606 #define  VLANEXTENABLE_SHIFT 12
 607
 608 #define TP_GLOBAL_CONFIG 0x7d08
 609 #define  FIVETUPLELOOKUP_SHIFT  17
 610 #define  FIVETUPLELOOKUP_MASK   0x00060000U
 611 #define  FIVETUPLELOOKUP(x)     ((x) << FIVETUPLELOOKUP_SHIFT)
 612 #define  FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \
 613                                 FIVETUPLELOOKUP_SHIFT)
 614
 615 #define TP_PARA_REG2 0x7d68
 616 #define  MAXRXDATA_MASK    0xffff0000U
 617 #define  MAXRXDATA_SHIFT   16
 618 #define  MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)
 619
 620 #define TP_TIMER_RESOLUTION 0x7d90
 621 #define  TIMERRESOLUTION_MASK   0x00ff0000U
 622 #define  TIMERRESOLUTION_SHIFT  16
 623 #define  TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
 624 #define  DELAYEDACKRESOLUTION_MASK 0x000000ffU
 625 #define  DELAYEDACKRESOLUTION_SHIFT     0
 626 #define  DELAYEDACKRESOLUTION_GET(x) \
 627         (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)
 628
 629 #define TP_SHIFT_CNT 0x7dc0
 630 #define  SYNSHIFTMAX_SHIFT         24
 631 #define  SYNSHIFTMAX_MASK          0xff000000U
 632 #define  SYNSHIFTMAX(x)            ((x) << SYNSHIFTMAX_SHIFT)
 633 #define  SYNSHIFTMAX_GET(x)        (((x) & SYNSHIFTMAX_MASK) >> \
 634                                    SYNSHIFTMAX_SHIFT)
 635 #define  RXTSHIFTMAXR1_SHIFT       20
 636 #define  RXTSHIFTMAXR1_MASK        0x00f00000U
 637 #define  RXTSHIFTMAXR1(x)          ((x) << RXTSHIFTMAXR1_SHIFT)
 638 #define  RXTSHIFTMAXR1_GET(x)      (((x) & RXTSHIFTMAXR1_MASK) >> \
 639                                    RXTSHIFTMAXR1_SHIFT)
 640 #define  RXTSHIFTMAXR2_SHIFT       16
 641 #define  RXTSHIFTMAXR2_MASK        0x000f0000U
 642 #define  RXTSHIFTMAXR2(x)          ((x) << RXTSHIFTMAXR2_SHIFT)
 643 #define  RXTSHIFTMAXR2_GET(x)      (((x) & RXTSHIFTMAXR2_MASK) >> \
 644                                    RXTSHIFTMAXR2_SHIFT)
 645 #define  PERSHIFTBACKOFFMAX_SHIFT  12
 646 #define  PERSHIFTBACKOFFMAX_MASK   0x0000f000U
 647 #define  PERSHIFTBACKOFFMAX(x)     ((x) << PERSHIFTBACKOFFMAX_SHIFT)
 648 #define  PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \
 649                                    PERSHIFTBACKOFFMAX_SHIFT)
 650 #define  PERSHIFTMAX_SHIFT         8
 651 #define  PERSHIFTMAX_MASK          0x00000f00U
 652 #define  PERSHIFTMAX(x)            ((x) << PERSHIFTMAX_SHIFT)
 653 #define  PERSHIFTMAX_GET(x)        (((x) & PERSHIFTMAX_MASK) >> \
 654                                    PERSHIFTMAX_SHIFT)
 655 #define  KEEPALIVEMAXR1_SHIFT      4
 656 #define  KEEPALIVEMAXR1_MASK       0x000000f0U
 657 #define  KEEPALIVEMAXR1(x)         ((x) << KEEPALIVEMAXR1_SHIFT)
 658 #define  KEEPALIVEMAXR1_GET(x)     (((x) & KEEPALIVEMAXR1_MASK) >> \
 659                                    KEEPALIVEMAXR1_SHIFT)
 660 #define KEEPALIVEMAXR2_SHIFT       0
 661 #define KEEPALIVEMAXR2_MASK        0x0000000fU
 662 #define KEEPALIVEMAXR2(x)          ((x) << KEEPALIVEMAXR2_SHIFT)
 663 #define KEEPALIVEMAXR2_GET(x)      (((x) & KEEPALIVEMAXR2_MASK) >> \
 664                                    KEEPALIVEMAXR2_SHIFT)
 665
 666 #define TP_CCTRL_TABLE 0x7ddc
 667 #define TP_MTU_TABLE 0x7de4
 668 #define  MTUINDEX_MASK   0xff000000U
 669 #define  MTUINDEX_SHIFT  24
 670 #define  MTUINDEX(x)     ((x) << MTUINDEX_SHIFT)
 671 #define  MTUWIDTH_MASK   0x000f0000U
 672 #define  MTUWIDTH_SHIFT  16
 673 #define  MTUWIDTH(x)     ((x) << MTUWIDTH_SHIFT)
 674 #define  MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)
 675 #define  MTUVALUE_MASK   0x00003fffU
 676 #define  MTUVALUE_SHIFT  0
 677 #define  MTUVALUE(x)     ((x) << MTUVALUE_SHIFT)
 678 #define  MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)
 679
 680 #define TP_RSS_LKP_TABLE 0x7dec
 681 #define  LKPTBLROWVLD        0x80000000U
 682 #define  LKPTBLQUEUE1_MASK   0x000ffc00U
 683 #define  LKPTBLQUEUE1_SHIFT  10
 684 #define  LKPTBLQUEUE1(x)     ((x) << LKPTBLQUEUE1_SHIFT)
 685 #define  LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)
 686 #define  LKPTBLQUEUE0_MASK   0x000003ffU
 687 #define  LKPTBLQUEUE0_SHIFT  0
 688 #define  LKPTBLQUEUE0(x)     ((x) << LKPTBLQUEUE0_SHIFT)
 689 #define  LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)
 690
 691 #define TP_PIO_ADDR 0x7e40
 692 #define TP_PIO_DATA 0x7e44
 693 #define TP_MIB_INDEX 0x7e50
 694 #define TP_MIB_DATA 0x7e54
 695 #define TP_INT_CAUSE 0x7e74
 696 #define  FLMTXFLSTEMPTY 0x40000000U
 697
 698 #define TP_VLAN_PRI_MAP 0x140
 699 #define  FRAGMENTATION_SHIFT 9
 700 #define  FRAGMENTATION_MASK  0x00000200U
 701 #define  MPSHITTYPE_MASK     0x00000100U
 702 #define  MACMATCH_MASK       0x00000080U
 703 #define  ETHERTYPE_MASK      0x00000040U
 704 #define  PROTOCOL_MASK       0x00000020U
 705 #define  TOS_MASK            0x00000010U
 706 #define  VLAN_MASK           0x00000008U
 707 #define  VNIC_ID_MASK        0x00000004U
 708 #define  PORT_MASK           0x00000002U
 709 #define  FCOE_SHIFT          0
 710 #define  FCOE_MASK           0x00000001U
 711
 712 #define TP_INGRESS_CONFIG 0x141
 713 #define  VNIC                0x00000800U
 714 #define  CSUM_HAS_PSEUDO_HDR 0x00000400U
 715 #define  RM_OVLAN            0x00000200U
 716 #define  LOOKUPEVERYPKT      0x00000100U
 717
 718 #define TP_MIB_MAC_IN_ERR_0 0x0
 719 #define TP_MIB_TCP_OUT_RST 0xc
 720 #define TP_MIB_TCP_IN_SEG_HI 0x10
 721 #define TP_MIB_TCP_IN_SEG_LO 0x11
 722 #define TP_MIB_TCP_OUT_SEG_HI 0x12
 723 #define TP_MIB_TCP_OUT_SEG_LO 0x13
 724 #define TP_MIB_TCP_RXT_SEG_HI 0x14
 725 #define TP_MIB_TCP_RXT_SEG_LO 0x15
 726 #define TP_MIB_TNL_CNG_DROP_0 0x18
 727 #define TP_MIB_TCP_V6IN_ERR_0 0x28
 728 #define TP_MIB_TCP_V6OUT_RST 0x2c
 729 #define TP_MIB_OFD_ARP_DROP 0x36
 730 #define TP_MIB_TNL_DROP_0 0x44
 731 #define TP_MIB_OFD_VLN_DROP_0 0x58
 732
 733 #define ULP_TX_INT_CAUSE 0x8dcc
 734 #define  PBL_BOUND_ERR_CH3 0x80000000U
 735 #define  PBL_BOUND_ERR_CH2 0x40000000U
 736 #define  PBL_BOUND_ERR_CH1 0x20000000U
 737 #define  PBL_BOUND_ERR_CH0 0x10000000U
 738
 739 #define PM_RX_INT_CAUSE 0x8fdc
 740 #define  ZERO_E_CMD_ERROR     0x00400000U
 741 #define  PMRX_FRAMING_ERROR   0x003ffff0U
 742 #define  OCSPI_PAR_ERROR      0x00000008U
 743 #define  DB_OPTIONS_PAR_ERROR 0x00000004U
 744 #define  IESPI_PAR_ERROR      0x00000002U
 745 #define  E_PCMD_PAR_ERROR     0x00000001U
 746
 747 #define PM_TX_INT_CAUSE 0x8ffc
 748 #define  PCMD_LEN_OVFL0     0x80000000U
 749 #define  PCMD_LEN_OVFL1     0x40000000U
 750 #define  PCMD_LEN_OVFL2     0x20000000U
 751 #define  ZERO_C_CMD_ERROR   0x10000000U
 752 #define  PMTX_FRAMING_ERROR 0x0ffffff0U
 753 #define  OESPI_PAR_ERROR    0x00000008U
 754 #define  ICSPI_PAR_ERROR    0x00000002U
 755 #define  C_PCMD_PAR_ERROR   0x00000001U
 756
 757 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
 758 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
 759 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
 760 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
 761 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
 762 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
 763 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
 764 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
 765 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
 766 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
 767 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
 768 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
 769 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
 770 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
 771 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
 772 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
 773 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
 774 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
 775 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
 776 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
 777 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
 778 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
 779 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
 780 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
 781 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
 782 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
 783 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
 784 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
 785 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
 786 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
 787 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
 788 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
 789 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
 790 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
 791 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
 792 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
 793 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
 794 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
 795 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
 796 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
 797 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
 798 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
 799 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
 800 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
 801 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
 802 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
 803 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
 804 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
 805 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
 806 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
 807 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
 808 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
 809 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
 810 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
 811 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
 812 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
 813 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
 814 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
 815 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
 816 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
 817 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
 818 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
 819 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
 820 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
 821 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
 822 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
 823 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
 824 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
 825 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
 826 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
 827 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
 828 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
 829 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
 830 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
 831 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
 832 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
 833 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
 834 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
 835 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
 836 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
 837 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
 838 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
 839 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
 840 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
 841 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
 842 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
 843 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
 844 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
 845 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
 846 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
 847 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
 848 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
 849 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
 850 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
 851 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
 852 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
 853 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
 854 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
 855 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
 856 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
 857 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
 858 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
 859 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
 860 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
 861 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
 862 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
 863 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
 864 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
 865 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
 866 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
 867 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
 868 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
 869 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
 870 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
 871 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
 872 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
 873 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
 874 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
 875 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
 876 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
 877 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
 878 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
 879 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
 880 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
 881 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
 882 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
 883 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
 884 #define MAC_PORT_CFG2 0x818
 885 #define MAC_PORT_MAGIC_MACID_LO 0x824
 886 #define MAC_PORT_MAGIC_MACID_HI 0x828
 887 #define MAC_PORT_EPIO_DATA0 0x8c0
 888 #define MAC_PORT_EPIO_DATA1 0x8c4
 889 #define MAC_PORT_EPIO_DATA2 0x8c8
 890 #define MAC_PORT_EPIO_DATA3 0x8cc
 891 #define MAC_PORT_EPIO_OP 0x8d0
 892
 893 #define MPS_CMN_CTL 0x9000
 894 #define  NUMPORTS_MASK   0x00000003U
 895 #define  NUMPORTS_SHIFT  0
 896 #define  NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)
 897
 898 #define MPS_INT_CAUSE 0x9008
 899 #define  STATINT 0x00000020U
 900 #define  TXINT   0x00000010U
 901 #define  RXINT   0x00000008U
 902 #define  TRCINT  0x00000004U
 903 #define  CLSINT  0x00000002U
 904 #define  PLINT   0x00000001U
 905
 906 #define MPS_TX_INT_CAUSE 0x9408
 907 #define  PORTERR    0x00010000U
 908 #define  FRMERR     0x00008000U
 909 #define  SECNTERR   0x00004000U
 910 #define  BUBBLE     0x00002000U
 911 #define  TXDESCFIFO 0x00001e00U
 912 #define  TXDATAFIFO 0x000001e0U
 913 #define  NCSIFIFO   0x00000010U
 914 #define  TPFIFO     0x0000000fU
 915
 916 #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
 917 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
 918 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
 919
 920 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
 921 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
 922 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
 923 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
 924 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
 925 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
 926 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
 927 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
 928 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
 929 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
 930 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
 931 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
 932 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
 933 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
 934 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
 935 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
 936 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
 937 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
 938 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
 939 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
 940 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
 941 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
 942 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
 943 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
 944 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
 945 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
 946 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
 947 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
 948 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
 949 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
 950 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
 951 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
 952 #define MPS_TRC_CFG 0x9800
 953 #define  TRCFIFOEMPTY       0x00000010U
 954 #define  TRCIGNOREDROPINPUT 0x00000008U
 955 #define  TRCKEEPDUPLICATES  0x00000004U
 956 #define  TRCEN              0x00000002U
 957 #define  TRCMULTIFILTER     0x00000001U
 958
 959 #define MPS_TRC_RSS_CONTROL 0x9808
 960 #define  RSSCONTROL_MASK    0x00ff0000U
 961 #define  RSSCONTROL_SHIFT   16
 962 #define  RSSCONTROL(x)      ((x) << RSSCONTROL_SHIFT)
 963 #define  QUEUENUMBER_MASK   0x0000ffffU
 964 #define  QUEUENUMBER_SHIFT  0
 965 #define  QUEUENUMBER(x)     ((x) << QUEUENUMBER_SHIFT)
 966
 967 #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810
 968 #define  TFINVERTMATCH   0x01000000U
 969 #define  TFPKTTOOLARGE   0x00800000U
 970 #define  TFEN            0x00400000U
 971 #define  TFPORT_MASK     0x003c0000U
 972 #define  TFPORT_SHIFT    18
 973 #define  TFPORT(x)       ((x) << TFPORT_SHIFT)
 974 #define  TFPORT_GET(x)   (((x) & TFPORT_MASK) >> TFPORT_SHIFT)
 975 #define  TFDROP          0x00020000U
 976 #define  TFSOPEOPERR     0x00010000U
 977 #define  TFLENGTH_MASK   0x00001f00U
 978 #define  TFLENGTH_SHIFT  8
 979 #define  TFLENGTH(x)     ((x) << TFLENGTH_SHIFT)
 980 #define  TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)
 981 #define  TFOFFSET_MASK   0x0000001fU
 982 #define  TFOFFSET_SHIFT  0
 983 #define  TFOFFSET(x)     ((x) << TFOFFSET_SHIFT)
 984 #define  TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)
 985
 986 #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820
 987 #define  TFMINPKTSIZE_MASK   0x01ff0000U
 988 #define  TFMINPKTSIZE_SHIFT  16
 989 #define  TFMINPKTSIZE(x)     ((x) << TFMINPKTSIZE_SHIFT)
 990 #define  TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)
 991 #define  TFCAPTUREMAX_MASK   0x00003fffU
 992 #define  TFCAPTUREMAX_SHIFT  0
 993 #define  TFCAPTUREMAX(x)     ((x) << TFCAPTUREMAX_SHIFT)
 994 #define  TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)
 995
 996 #define MPS_TRC_INT_CAUSE 0x985c
 997 #define  MISCPERR 0x00000100U
 998 #define  PKTFIFO  0x000000f0U
 999 #define  FILTMEM  0x0000000fU
1000
1001 #define MPS_TRC_FILTER0_MATCH 0x9c00
1002 #define MPS_TRC_FILTER0_DONT_CARE 0x9c80
1003 #define MPS_TRC_FILTER1_MATCH 0x9d00
1004 #define MPS_CLS_INT_CAUSE 0xd028
1005 #define  PLERRENB  0x00000008U
1006 #define  HASHSRAM  0x00000004U
1007 #define  MATCHTCAM 0x00000002U
1008 #define  MATCHSRAM 0x00000001U
1009
1010 #define MPS_RX_PERR_INT_CAUSE 0x11074
1011
1012 #define CPL_INTR_CAUSE 0x19054
1013 #define  CIM_OP_MAP_PERR   0x00000020U
1014 #define  CIM_OVFL_ERROR    0x00000010U
1015 #define  TP_FRAMING_ERROR  0x00000008U
1016 #define  SGE_FRAMING_ERROR 0x00000004U
1017 #define  CIM_FRAMING_ERROR 0x00000002U
1018 #define  ZERO_SWITCH_ERROR 0x00000001U
1019
1020 #define SMB_INT_CAUSE 0x19090
1021 #define  MSTTXFIFOPARINT 0x00200000U
1022 #define  MSTRXFIFOPARINT 0x00100000U
1023 #define  SLVFIFOPARINT   0x00080000U
1024
1025 #define ULP_RX_INT_CAUSE 0x19158
1026 #define ULP_RX_ISCSI_TAGMASK 0x19164
1027 #define ULP_RX_ISCSI_PSZ 0x19168
1028 #define  HPZ3_MASK   0x0f000000U
1029 #define  HPZ3_SHIFT  24
1030 #define  HPZ3(x)     ((x) << HPZ3_SHIFT)
1031 #define  HPZ2_MASK   0x000f0000U
1032 #define  HPZ2_SHIFT  16
1033 #define  HPZ2(x)     ((x) << HPZ2_SHIFT)
1034 #define  HPZ1_MASK   0x00000f00U
1035 #define  HPZ1_SHIFT  8
1036 #define  HPZ1(x)     ((x) << HPZ1_SHIFT)
1037 #define  HPZ0_MASK   0x0000000fU
1038 #define  HPZ0_SHIFT  0
1039 #define  HPZ0(x)     ((x) << HPZ0_SHIFT)
1040
1041 #define ULP_RX_TDDP_PSZ 0x19178
1042
1043 #define SF_DATA 0x193f8
1044 #define SF_OP 0x193fc
1045 #define  SF_BUSY       0x80000000U
1046 #define  SF_LOCK       0x00000010U
1047 #define  SF_CONT       0x00000008U
1048 #define  BYTECNT_MASK  0x00000006U
1049 #define  BYTECNT_SHIFT 1
1050 #define  BYTECNT(x)    ((x) << BYTECNT_SHIFT)
1051 #define  OP_WR         0x00000001U
1052
1053 #define PL_PF_INT_CAUSE 0x3c0
1054 #define  PFSW  0x00000008U
1055 #define  PFSGE 0x00000004U
1056 #define  PFCIM 0x00000002U
1057 #define  PFMPS 0x00000001U
1058
1059 #define PL_PF_INT_ENABLE 0x3c4
1060 #define PL_PF_CTL 0x3c8
1061 #define  SWINT 0x00000001U
1062
1063 #define PL_WHOAMI 0x19400
1064 #define  SOURCEPF_MASK   0x00000700U
1065 #define  SOURCEPF_SHIFT  8
1066 #define  SOURCEPF(x)     ((x) << SOURCEPF_SHIFT)
1067 #define  SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
1068 #define  ISVF            0x00000080U
1069 #define  VFID_MASK       0x0000007fU
1070 #define  VFID_SHIFT      0
1071 #define  VFID(x)         ((x) << VFID_SHIFT)
1072 #define  VFID_GET(x)     (((x) & VFID_MASK) >> VFID_SHIFT)
1073
1074 #define PL_INT_CAUSE 0x1940c
1075 #define  ULP_TX     0x08000000U
1076 #define  SGE        0x04000000U
1077 #define  HMA        0x02000000U
1078 #define  CPL_SWITCH 0x01000000U
1079 #define  ULP_RX     0x00800000U
1080 #define  PM_RX      0x00400000U
1081 #define  PM_TX      0x00200000U
1082 #define  MA         0x00100000U
1083 #define  TP         0x00080000U
1084 #define  LE         0x00040000U
1085 #define  EDC1       0x00020000U
1086 #define  EDC0       0x00010000U
1087 #define  MC         0x00008000U
1088 #define  PCIE       0x00004000U
1089 #define  PMU        0x00002000U
1090 #define  XGMAC_KR1  0x00001000U
1091 #define  XGMAC_KR0  0x00000800U
1092 #define  XGMAC1     0x00000400U
1093 #define  XGMAC0     0x00000200U
1094 #define  SMB        0x00000100U
1095 #define  SF         0x00000080U
1096 #define  PL         0x00000040U
1097 #define  NCSI       0x00000020U
1098 #define  MPS        0x00000010U
1099 #define  MI         0x00000008U
1100 #define  DBG        0x00000004U
1101 #define  I2CM       0x00000002U
1102 #define  CIM        0x00000001U
1103
1104 #define PL_INT_ENABLE 0x19410
1105 #define PL_INT_MAP0 0x19414
1106 #define PL_RST 0x19428
1107 #define  PIORST     0x00000002U
1108 #define  PIORSTMODE 0x00000001U
1109
1110 #define PL_PL_INT_CAUSE 0x19430
1111 #define  FATALPERR 0x00000010U
1112 #define  PERRVFID  0x00000001U
1113
1114 #define PL_REV 0x1943c
1115
1116 #define S_REV    0
1117 #define M_REV    0xfU
1118 #define V_REV(x) ((x) << S_REV)
1119 #define G_REV(x) (((x) >> S_REV) & M_REV)
1120
1121 #define LE_DB_CONFIG 0x19c04
1122 #define  HASHEN 0x00100000U
1123
1124 #define LE_DB_SERVER_INDEX 0x19c18
1125 #define LE_DB_ACT_CNT_IPV4 0x19c20
1126 #define LE_DB_ACT_CNT_IPV6 0x19c24
1127
1128 #define LE_DB_INT_CAUSE 0x19c3c
1129 #define  REQQPARERR 0x00010000U
1130 #define  UNKNOWNCMD 0x00008000U
1131 #define  PARITYERR  0x00000040U
1132 #define  LIPMISS    0x00000020U
1133 #define  LIP0       0x00000010U
1134
1135 #define LE_DB_TID_HASHBASE 0x19df8
1136
1137 #define NCSI_INT_CAUSE 0x1a0d8
1138 #define  CIM_DM_PRTY_ERR 0x00000100U
1139 #define  MPS_DM_PRTY_ERR 0x00000080U
1140 #define  TXFIFO_PRTY_ERR 0x00000002U
1141 #define  RXFIFO_PRTY_ERR 0x00000001U
1142
1143 #define XGMAC_PORT_CFG2 0x1018
1144 #define  PATEN   0x00040000U
1145 #define  MAGICEN 0x00020000U
1146
1147 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
1148 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
1149
1150 #define XGMAC_PORT_EPIO_DATA0 0x10c0
1151 #define XGMAC_PORT_EPIO_DATA1 0x10c4
1152 #define XGMAC_PORT_EPIO_DATA2 0x10c8
1153 #define XGMAC_PORT_EPIO_DATA3 0x10cc
1154 #define XGMAC_PORT_EPIO_OP 0x10d0
1155 #define  EPIOWR         0x00000100U
1156 #define  ADDRESS_MASK   0x000000ffU
1157 #define  ADDRESS_SHIFT  0
1158 #define  ADDRESS(x)     ((x) << ADDRESS_SHIFT)
1159
1160 #define MAC_PORT_INT_CAUSE 0x8dc
1161 #define XGMAC_PORT_INT_CAUSE 0x10dc
1162
1163 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
1164
1165 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
1166
1167 #define S_TX_MOD_QUEUE_REQ_MAP    0
1168 #define M_TX_MOD_QUEUE_REQ_MAP    0xffffU
1169 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1170
1171 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
1172
1173 #define S_TX_MODQ_WEIGHT3    24
1174 #define M_TX_MODQ_WEIGHT3    0xffU
1175 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
1176
1177 #define S_TX_MODQ_WEIGHT2    16
1178 #define M_TX_MODQ_WEIGHT2    0xffU
1179 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
1180
1181 #define S_TX_MODQ_WEIGHT1    8
1182 #define M_TX_MODQ_WEIGHT1    0xffU
1183 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
1184
1185 #define S_TX_MODQ_WEIGHT0    0
1186 #define M_TX_MODQ_WEIGHT0    0xffU
1187 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
1188
1189 #define A_TP_TX_SCHED_HDR 0x23
1190
1191 #define A_TP_TX_SCHED_FIFO 0x24
1192
1193 #define A_TP_TX_SCHED_PCMD 0x25
1194
1195 #define S_VNIC    11
1196 #define V_VNIC(x) ((x) << S_VNIC)
1197 #define F_VNIC    V_VNIC(1U)
1198
1199 #define S_FRAGMENTATION    9
1200 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
1201 #define F_FRAGMENTATION    V_FRAGMENTATION(1U)
1202
1203 #define S_MPSHITTYPE    8
1204 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
1205 #define F_MPSHITTYPE    V_MPSHITTYPE(1U)
1206
1207 #define S_MACMATCH    7
1208 #define V_MACMATCH(x) ((x) << S_MACMATCH)
1209 #define F_MACMATCH    V_MACMATCH(1U)
1210
1211 #define S_ETHERTYPE    6
1212 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
1213 #define F_ETHERTYPE    V_ETHERTYPE(1U)
1214
1215 #define S_PROTOCOL    5
1216 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
1217 #define F_PROTOCOL    V_PROTOCOL(1U)
1218
1219 #define S_TOS    4
1220 #define V_TOS(x) ((x) << S_TOS)
1221 #define F_TOS    V_TOS(1U)
1222
1223 #define S_VLAN    3
1224 #define V_VLAN(x) ((x) << S_VLAN)
1225 #define F_VLAN    V_VLAN(1U)
1226
1227 #define S_VNIC_ID    2
1228 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
1229 #define F_VNIC_ID    V_VNIC_ID(1U)
1230
1231 #define S_PORT    1
1232 #define V_PORT(x) ((x) << S_PORT)
1233 #define F_PORT    V_PORT(1U)
1234
1235 #define S_FCOE    0
1236 #define V_FCOE(x) ((x) << S_FCOE)
1237 #define F_FCOE    V_FCOE(1U)
1238
1239 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
1240 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
1241
1242 #define T5_PORT0_BASE 0x30000
1243 #define T5_PORT_STRIDE 0x4000
1244 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
1245 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
1246
1247 #define MC_0_BASE_ADDR 0x40000
1248 #define MC_1_BASE_ADDR 0x48000
1249 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
1250 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
1251
1252 #define MC_P_BIST_CMD 0x41400
1253 #define MC_P_BIST_CMD_ADDR 0x41404
1254 #define MC_P_BIST_CMD_LEN 0x41408
1255 #define MC_P_BIST_DATA_PATTERN 0x4140c
1256 #define MC_P_BIST_STATUS_RDATA 0x41488
1257 #define EDC_T50_BASE_ADDR 0x50000
1258 #define EDC_H_BIST_CMD 0x50004
1259 #define EDC_H_BIST_CMD_ADDR 0x50008
1260 #define EDC_H_BIST_CMD_LEN 0x5000c
1261 #define EDC_H_BIST_DATA_PATTERN 0x50010
1262 #define EDC_H_BIST_STATUS_RDATA 0x50028
1263
1264 #define EDC_T51_BASE_ADDR 0x50800
1265 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
1266 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
1267
1268 #define A_PL_VF_REV 0x4
1269 #define A_PL_VF_WHOAMI 0x0
1270 #define A_PL_VF_REVISION 0x8
1271
1272 #define S_CHIPID    4
1273 #define M_CHIPID    0xfU
1274 #define V_CHIPID(x) ((x) << S_CHIPID)
1275 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
1276
1277 /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
1278  * Compressed Filter Tuple for LE filters.  Each bit set in TP_VLAN_PRI_MAP
1279  * selects for a particular field being present.  These fields, when present
1280  * in the Compressed Filter Tuple, have the following widths in bits.
1281  */
1282 #define W_FT_FCOE                       1
1283 #define W_FT_PORT                       3
1284 #define W_FT_VNIC_ID                    17
1285 #define W_FT_VLAN                       17
1286 #define W_FT_TOS                        8
1287 #define W_FT_PROTOCOL                   8
1288 #define W_FT_ETHERTYPE                  16
1289 #define W_FT_MACMATCH                   9
1290 #define W_FT_MPSHITTYPE                 3
1291 #define W_FT_FRAGMENTATION              1
1292
1293 /* Some of the Compressed Filter Tuple fields have internal structure.  These
1294  * bit shifts/masks describe those structures.  All shifts are relative to the
1295  * base position of the fields within the Compressed Filter Tuple
1296  */
1297 #define S_FT_VLAN_VLD                   16
1298 #define V_FT_VLAN_VLD(x)                ((x) << S_FT_VLAN_VLD)
1299 #define F_FT_VLAN_VLD                   V_FT_VLAN_VLD(1U)
1300
1301 #define S_FT_VNID_ID_VF                 0
1302 #define V_FT_VNID_ID_VF(x)              ((x) << S_FT_VNID_ID_VF)
1303
1304 #define S_FT_VNID_ID_PF                 7
1305 #define V_FT_VNID_ID_PF(x)              ((x) << S_FT_VNID_ID_PF)
1306
1307 #define S_FT_VNID_ID_VLD                16
1308 #define V_FT_VNID_ID_VLD(x)             ((x) << S_FT_VNID_ID_VLD)
1309
1310 #endif /* __T4_REGS_H */