drivers/net/ethernet/chelsio/cxgb4/t4_regs.h

   1 /*
   2  * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3  *
   4  * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
   5  *
   6  * This software is available to you under a choice of one of two
   7  * licenses.  You may choose to be licensed under the terms of the GNU
   8  * General Public License (GPL) Version 2, available from the file
   9  * COPYING in the main directory of this source tree, or the
  10  * OpenIB.org BSD license below:
  11  *
  12  *     Redistribution and use in source and binary forms, with or
  13  *     without modification, are permitted provided that the following
  14  *     conditions are met:
  15  *
  16  *      - Redistributions of source code must retain the above
  17  *        copyright notice, this list of conditions and the following
  18  *        disclaimer.
  19  *
  20  *      - Redistributions in binary form must reproduce the above
  21  *        copyright notice, this list of conditions and the following
  22  *        disclaimer in the documentation and/or other materials
  23  *        provided with the distribution.
  24  *
  25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32  * SOFTWARE.
  33  */
  34
  35 #ifndef __T4_REGS_H
  36 #define __T4_REGS_H
  37
  38 #define MYPF_BASE 0x1b000
  39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
  40
  41 #define PF0_BASE 0x1e000
  42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
  43
  44 #define PF_STRIDE 0x400
  45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
  46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
  47
  48 #define MYPORT_BASE 0x1c000
  49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
  50
  51 #define PORT0_BASE 0x20000
  52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
  53
  54 #define PORT_STRIDE 0x2000
  55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
  56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
  57
  58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
  59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
  60
  61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
  62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
  63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
  64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
  65
  66 #define SGE_PF_KDOORBELL 0x0
  67 #define  QID_MASK    0xffff8000U
  68 #define  QID_SHIFT   15
  69 #define  QID(x)      ((x) << QID_SHIFT)
  70 #define  DBPRIO(x)   ((x) << 14)
  71 #define  DBTYPE(x)   ((x) << 13)
  72 #define  PIDX_MASK   0x00003fffU
  73 #define  PIDX_SHIFT  0
  74 #define  PIDX(x)     ((x) << PIDX_SHIFT)
  75 #define  PIDX_SHIFT_T5   0
  76 #define  PIDX_T5(x)  ((x) << PIDX_SHIFT_T5)
  77
  78
  79 #define SGE_TIMERREGS   6
  80 #define SGE_PF_GTS 0x4
  81 #define  INGRESSQID_MASK   0xffff0000U
  82 #define  INGRESSQID_SHIFT  16
  83 #define  INGRESSQID(x)     ((x) << INGRESSQID_SHIFT)
  84 #define  TIMERREG_MASK     0x0000e000U
  85 #define  TIMERREG_SHIFT    13
  86 #define  TIMERREG(x)       ((x) << TIMERREG_SHIFT)
  87 #define  SEINTARM_MASK     0x00001000U
  88 #define  SEINTARM_SHIFT    12
  89 #define  SEINTARM(x)       ((x) << SEINTARM_SHIFT)
  90 #define  CIDXINC_MASK      0x00000fffU
  91 #define  CIDXINC_SHIFT     0
  92 #define  CIDXINC(x)        ((x) << CIDXINC_SHIFT)
  93
  94 #define X_RXPKTCPLMODE_SPLIT     1
  95 #define X_INGPADBOUNDARY_SHIFT 5
  96
  97 #define SGE_CONTROL 0x1008
  98 #define SGE_CONTROL2_A          0x1124
  99 #define  DCASYSTYPE             0x00080000U
 100 #define  RXPKTCPLMODE_MASK      0x00040000U
 101 #define  RXPKTCPLMODE_SHIFT     18
 102 #define  RXPKTCPLMODE(x)        ((x) << RXPKTCPLMODE_SHIFT)
 103 #define  EGRSTATUSPAGESIZE_MASK  0x00020000U
 104 #define  EGRSTATUSPAGESIZE_SHIFT 17
 105 #define  EGRSTATUSPAGESIZE(x)    ((x) << EGRSTATUSPAGESIZE_SHIFT)
 106 #define  PKTSHIFT_MASK          0x00001c00U
 107 #define  PKTSHIFT_SHIFT         10
 108 #define  PKTSHIFT(x)            ((x) << PKTSHIFT_SHIFT)
 109 #define  PKTSHIFT_GET(x)        (((x) & PKTSHIFT_MASK) >> PKTSHIFT_SHIFT)
 110 #define  INGPCIEBOUNDARY_32B_X  0
 111 #define  INGPCIEBOUNDARY_MASK   0x00000380U
 112 #define  INGPCIEBOUNDARY_SHIFT  7
 113 #define  INGPCIEBOUNDARY(x)     ((x) << INGPCIEBOUNDARY_SHIFT)
 114 #define  INGPADBOUNDARY_MASK    0x00000070U
 115 #define  INGPADBOUNDARY_SHIFT   4
 116 #define  INGPADBOUNDARY(x)      ((x) << INGPADBOUNDARY_SHIFT)
 117 #define  INGPADBOUNDARY_GET(x)  (((x) & INGPADBOUNDARY_MASK) \
 118                                  >> INGPADBOUNDARY_SHIFT)
 119 #define  INGPACKBOUNDARY_16B_X  0
 120 #define  INGPACKBOUNDARY_SHIFT_X 5
 121
 122 #define  INGPACKBOUNDARY_S      16
 123 #define  INGPACKBOUNDARY_M      0x7U
 124 #define  INGPACKBOUNDARY_V(x)   ((x) << INGPACKBOUNDARY_S)
 125 #define  INGPACKBOUNDARY_G(x)   (((x) >> INGPACKBOUNDARY_S) \
 126                                  & INGPACKBOUNDARY_M)
 127 #define  EGRPCIEBOUNDARY_MASK   0x0000000eU
 128 #define  EGRPCIEBOUNDARY_SHIFT  1
 129 #define  EGRPCIEBOUNDARY(x)     ((x) << EGRPCIEBOUNDARY_SHIFT)
 130 #define  GLOBALENABLE           0x00000001U
 131
 132 #define SGE_HOST_PAGE_SIZE 0x100c
 133
 134 #define  HOSTPAGESIZEPF7_MASK   0x0000000fU
 135 #define  HOSTPAGESIZEPF7_SHIFT  28
 136 #define  HOSTPAGESIZEPF7(x)     ((x) << HOSTPAGESIZEPF7_SHIFT)
 137
 138 #define  HOSTPAGESIZEPF6_MASK   0x0000000fU
 139 #define  HOSTPAGESIZEPF6_SHIFT  24
 140 #define  HOSTPAGESIZEPF6(x)     ((x) << HOSTPAGESIZEPF6_SHIFT)
 141
 142 #define  HOSTPAGESIZEPF5_MASK   0x0000000fU
 143 #define  HOSTPAGESIZEPF5_SHIFT  20
 144 #define  HOSTPAGESIZEPF5(x)     ((x) << HOSTPAGESIZEPF5_SHIFT)
 145
 146 #define  HOSTPAGESIZEPF4_MASK   0x0000000fU
 147 #define  HOSTPAGESIZEPF4_SHIFT  16
 148 #define  HOSTPAGESIZEPF4(x)     ((x) << HOSTPAGESIZEPF4_SHIFT)
 149
 150 #define  HOSTPAGESIZEPF3_MASK   0x0000000fU
 151 #define  HOSTPAGESIZEPF3_SHIFT  12
 152 #define  HOSTPAGESIZEPF3(x)     ((x) << HOSTPAGESIZEPF3_SHIFT)
 153
 154 #define  HOSTPAGESIZEPF2_MASK   0x0000000fU
 155 #define  HOSTPAGESIZEPF2_SHIFT  8
 156 #define  HOSTPAGESIZEPF2(x)     ((x) << HOSTPAGESIZEPF2_SHIFT)
 157
 158 #define  HOSTPAGESIZEPF1_MASK   0x0000000fU
 159 #define  HOSTPAGESIZEPF1_SHIFT  4
 160 #define  HOSTPAGESIZEPF1(x)     ((x) << HOSTPAGESIZEPF1_SHIFT)
 161
 162 #define  HOSTPAGESIZEPF0_MASK   0x0000000fU
 163 #define  HOSTPAGESIZEPF0_SHIFT  0
 164 #define  HOSTPAGESIZEPF0(x)     ((x) << HOSTPAGESIZEPF0_SHIFT)
 165
 166 #define SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
 167 #define  QUEUESPERPAGEPF0_MASK   0x0000000fU
 168 #define  QUEUESPERPAGEPF0_GET(x) ((x) & QUEUESPERPAGEPF0_MASK)
 169
 170 #define QUEUESPERPAGEPF0    0
 171 #define QUEUESPERPAGEPF1    4
 172
 173 /* T5 and later support a new BAR2-based doorbell mechanism for Egress Queues.
 174  * The User Doorbells are each 128 bytes in length with a Simple Doorbell at
 175  * offsets 8x and a Write Combining single 64-byte Egress Queue Unit
 176  * (X_IDXSIZE_UNIT) Gather Buffer interface at offset 64.  For Ingress Queues,
 177  * we have a Going To Sleep register at offsets 8x+4.
 178  *
 179  * As noted above, we have many instances of the Simple Doorbell and Going To
 180  * Sleep registers at offsets 8x and 8x+4, respectively.  We want to use a
 181  * non-64-byte aligned offset for the Simple Doorbell in order to attempt to
 182  * avoid buffering of the writes to the Simple Doorbell and we want to use a
 183  * non-contiguous offset for the Going To Sleep writes in order to avoid
 184  * possible combining between them.
 185  */
 186 #define SGE_UDB_SIZE            128
 187 #define SGE_UDB_KDOORBELL       8
 188 #define SGE_UDB_GTS             20
 189 #define SGE_UDB_WCDOORBELL      64
 190
 191 #define SGE_INT_CAUSE1 0x1024
 192 #define SGE_INT_CAUSE2 0x1030
 193 #define SGE_INT_CAUSE3 0x103c
 194 #define  ERR_FLM_DBP               0x80000000U
 195 #define  ERR_FLM_IDMA1             0x40000000U
 196 #define  ERR_FLM_IDMA0             0x20000000U
 197 #define  ERR_FLM_HINT              0x10000000U
 198 #define  ERR_PCIE_ERROR3           0x08000000U
 199 #define  ERR_PCIE_ERROR2           0x04000000U
 200 #define  ERR_PCIE_ERROR1           0x02000000U
 201 #define  ERR_PCIE_ERROR0           0x01000000U
 202 #define  ERR_TIMER_ABOVE_MAX_QID   0x00800000U
 203 #define  ERR_CPL_EXCEED_IQE_SIZE   0x00400000U
 204 #define  ERR_INVALID_CIDX_INC      0x00200000U
 205 #define  ERR_ITP_TIME_PAUSED       0x00100000U
 206 #define  ERR_CPL_OPCODE_0          0x00080000U
 207 #define  ERR_DROPPED_DB            0x00040000U
 208 #define  ERR_DATA_CPL_ON_HIGH_QID1 0x00020000U
 209 #define  ERR_DATA_CPL_ON_HIGH_QID0 0x00010000U
 210 #define  ERR_BAD_DB_PIDX3          0x00008000U
 211 #define  ERR_BAD_DB_PIDX2          0x00004000U
 212 #define  ERR_BAD_DB_PIDX1          0x00002000U
 213 #define  ERR_BAD_DB_PIDX0          0x00001000U
 214 #define  ERR_ING_PCIE_CHAN         0x00000800U
 215 #define  ERR_ING_CTXT_PRIO         0x00000400U
 216 #define  ERR_EGR_CTXT_PRIO         0x00000200U
 217 #define  DBFIFO_HP_INT             0x00000100U
 218 #define  DBFIFO_LP_INT             0x00000080U
 219 #define  REG_ADDRESS_ERR           0x00000040U
 220 #define  INGRESS_SIZE_ERR          0x00000020U
 221 #define  EGRESS_SIZE_ERR           0x00000010U
 222 #define  ERR_INV_CTXT3             0x00000008U
 223 #define  ERR_INV_CTXT2             0x00000004U
 224 #define  ERR_INV_CTXT1             0x00000002U
 225 #define  ERR_INV_CTXT0             0x00000001U
 226
 227 #define SGE_INT_ENABLE3 0x1040
 228 #define SGE_FL_BUFFER_SIZE0 0x1044
 229 #define SGE_FL_BUFFER_SIZE1 0x1048
 230 #define SGE_FL_BUFFER_SIZE2 0x104c
 231 #define SGE_FL_BUFFER_SIZE3 0x1050
 232 #define SGE_FL_BUFFER_SIZE4 0x1054
 233 #define SGE_FL_BUFFER_SIZE5 0x1058
 234 #define SGE_FL_BUFFER_SIZE6 0x105c
 235 #define SGE_FL_BUFFER_SIZE7 0x1060
 236 #define SGE_FL_BUFFER_SIZE8 0x1064
 237
 238 #define SGE_INGRESS_RX_THRESHOLD 0x10a0
 239 #define  THRESHOLD_0_MASK   0x3f000000U
 240 #define  THRESHOLD_0_SHIFT  24
 241 #define  THRESHOLD_0(x)     ((x) << THRESHOLD_0_SHIFT)
 242 #define  THRESHOLD_0_GET(x) (((x) & THRESHOLD_0_MASK) >> THRESHOLD_0_SHIFT)
 243 #define  THRESHOLD_1_MASK   0x003f0000U
 244 #define  THRESHOLD_1_SHIFT  16
 245 #define  THRESHOLD_1(x)     ((x) << THRESHOLD_1_SHIFT)
 246 #define  THRESHOLD_1_GET(x) (((x) & THRESHOLD_1_MASK) >> THRESHOLD_1_SHIFT)
 247 #define  THRESHOLD_2_MASK   0x00003f00U
 248 #define  THRESHOLD_2_SHIFT  8
 249 #define  THRESHOLD_2(x)     ((x) << THRESHOLD_2_SHIFT)
 250 #define  THRESHOLD_2_GET(x) (((x) & THRESHOLD_2_MASK) >> THRESHOLD_2_SHIFT)
 251 #define  THRESHOLD_3_MASK   0x0000003fU
 252 #define  THRESHOLD_3_SHIFT  0
 253 #define  THRESHOLD_3(x)     ((x) << THRESHOLD_3_SHIFT)
 254 #define  THRESHOLD_3_GET(x) (((x) & THRESHOLD_3_MASK) >> THRESHOLD_3_SHIFT)
 255
 256 #define SGE_CONM_CTRL 0x1094
 257 #define  EGRTHRESHOLD_MASK   0x00003f00U
 258 #define  EGRTHRESHOLDshift   8
 259 #define  EGRTHRESHOLD(x)     ((x) << EGRTHRESHOLDshift)
 260 #define  EGRTHRESHOLD_GET(x) (((x) & EGRTHRESHOLD_MASK) >> EGRTHRESHOLDshift)
 261
 262 #define EGRTHRESHOLDPACKING_MASK        0x3fU
 263 #define EGRTHRESHOLDPACKING_SHIFT       14
 264 #define EGRTHRESHOLDPACKING(x)          ((x) << EGRTHRESHOLDPACKING_SHIFT)
 265 #define EGRTHRESHOLDPACKING_GET(x)      (((x) >> EGRTHRESHOLDPACKING_SHIFT) & \
 266                                           EGRTHRESHOLDPACKING_MASK)
 267
 268 #define SGE_DBFIFO_STATUS 0x10a4
 269 #define  HP_INT_THRESH_SHIFT 28
 270 #define  HP_INT_THRESH_MASK  0xfU
 271 #define  HP_INT_THRESH(x)    ((x) << HP_INT_THRESH_SHIFT)
 272 #define  LP_INT_THRESH_SHIFT 12
 273 #define  LP_INT_THRESH_MASK  0xfU
 274 #define  LP_INT_THRESH(x)    ((x) << LP_INT_THRESH_SHIFT)
 275
 276 #define SGE_DOORBELL_CONTROL 0x10a8
 277 #define  ENABLE_DROP        (1 << 13)
 278
 279 #define S_NOCOALESCE    26
 280 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
 281 #define F_NOCOALESCE    V_NOCOALESCE(1U)
 282
 283 #define SGE_TIMESTAMP_LO 0x1098
 284 #define SGE_TIMESTAMP_HI 0x109c
 285 #define S_TSVAL    0
 286 #define M_TSVAL    0xfffffffU
 287 #define GET_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
 288
 289 #define SGE_TIMER_VALUE_0_AND_1 0x10b8
 290 #define  TIMERVALUE0_MASK   0xffff0000U
 291 #define  TIMERVALUE0_SHIFT  16
 292 #define  TIMERVALUE0(x)     ((x) << TIMERVALUE0_SHIFT)
 293 #define  TIMERVALUE0_GET(x) (((x) & TIMERVALUE0_MASK) >> TIMERVALUE0_SHIFT)
 294 #define  TIMERVALUE1_MASK   0x0000ffffU
 295 #define  TIMERVALUE1_SHIFT  0
 296 #define  TIMERVALUE1(x)     ((x) << TIMERVALUE1_SHIFT)
 297 #define  TIMERVALUE1_GET(x) (((x) & TIMERVALUE1_MASK) >> TIMERVALUE1_SHIFT)
 298
 299 #define SGE_TIMER_VALUE_2_AND_3 0x10bc
 300 #define  TIMERVALUE2_MASK   0xffff0000U
 301 #define  TIMERVALUE2_SHIFT  16
 302 #define  TIMERVALUE2(x)     ((x) << TIMERVALUE2_SHIFT)
 303 #define  TIMERVALUE2_GET(x) (((x) & TIMERVALUE2_MASK) >> TIMERVALUE2_SHIFT)
 304 #define  TIMERVALUE3_MASK   0x0000ffffU
 305 #define  TIMERVALUE3_SHIFT  0
 306 #define  TIMERVALUE3(x)     ((x) << TIMERVALUE3_SHIFT)
 307 #define  TIMERVALUE3_GET(x) (((x) & TIMERVALUE3_MASK) >> TIMERVALUE3_SHIFT)
 308
 309 #define SGE_TIMER_VALUE_4_AND_5 0x10c0
 310 #define  TIMERVALUE4_MASK   0xffff0000U
 311 #define  TIMERVALUE4_SHIFT  16
 312 #define  TIMERVALUE4(x)     ((x) << TIMERVALUE4_SHIFT)
 313 #define  TIMERVALUE4_GET(x) (((x) & TIMERVALUE4_MASK) >> TIMERVALUE4_SHIFT)
 314 #define  TIMERVALUE5_MASK   0x0000ffffU
 315 #define  TIMERVALUE5_SHIFT  0
 316 #define  TIMERVALUE5(x)     ((x) << TIMERVALUE5_SHIFT)
 317 #define  TIMERVALUE5_GET(x) (((x) & TIMERVALUE5_MASK) >> TIMERVALUE5_SHIFT)
 318
 319 #define SGE_DEBUG_INDEX 0x10cc
 320 #define SGE_DEBUG_DATA_HIGH 0x10d0
 321 #define SGE_DEBUG_DATA_LOW 0x10d4
 322 #define SGE_DEBUG_DATA_LOW_INDEX_2      0x12c8
 323 #define SGE_DEBUG_DATA_LOW_INDEX_3      0x12cc
 324 #define SGE_DEBUG_DATA_HIGH_INDEX_10    0x12a8
 325 #define SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
 326
 327 #define S_HP_INT_THRESH    28
 328 #define M_HP_INT_THRESH 0xfU
 329 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
 330 #define S_LP_INT_THRESH_T5    18
 331 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
 332 #define M_LP_COUNT_T5    0x3ffffU
 333 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT) & M_LP_COUNT_T5)
 334 #define M_HP_COUNT 0x7ffU
 335 #define S_HP_COUNT 16
 336 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
 337 #define S_LP_INT_THRESH    12
 338 #define M_LP_INT_THRESH 0xfU
 339 #define M_LP_INT_THRESH_T5    0xfffU
 340 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
 341 #define M_LP_COUNT 0x7ffU
 342 #define S_LP_COUNT 0
 343 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
 344 #define A_SGE_DBFIFO_STATUS 0x10a4
 345
 346 #define SGE_STAT_TOTAL 0x10e4
 347 #define SGE_STAT_MATCH 0x10e8
 348
 349 #define SGE_STAT_CFG   0x10ec
 350 #define S_STATSOURCE_T5    9
 351 #define STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
 352
 353 #define SGE_DBFIFO_STATUS2 0x1118
 354 #define M_HP_COUNT_T5    0x3ffU
 355 #define G_HP_COUNT_T5(x) ((x)  & M_HP_COUNT_T5)
 356 #define S_HP_INT_THRESH_T5    10
 357 #define M_HP_INT_THRESH_T5    0xfU
 358 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
 359
 360 #define S_ENABLE_DROP    13
 361 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
 362 #define F_ENABLE_DROP    V_ENABLE_DROP(1U)
 363 #define S_DROPPED_DB 0
 364 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
 365 #define F_DROPPED_DB V_DROPPED_DB(1U)
 366 #define A_SGE_DOORBELL_CONTROL 0x10a8
 367
 368 #define A_SGE_CTXT_CMD 0x11fc
 369 #define A_SGE_DBQ_CTXT_BADDR 0x1084
 370
 371 #define PCIE_PF_CFG 0x40
 372 #define  AIVEC(x)       ((x) << 4)
 373 #define  AIVEC_MASK     0x3ffU
 374
 375 #define PCIE_PF_CLI 0x44
 376 #define PCIE_INT_CAUSE 0x3004
 377 #define  UNXSPLCPLERR  0x20000000U
 378 #define  PCIEPINT      0x10000000U
 379 #define  PCIESINT      0x08000000U
 380 #define  RPLPERR       0x04000000U
 381 #define  RXWRPERR      0x02000000U
 382 #define  RXCPLPERR     0x01000000U
 383 #define  PIOTAGPERR    0x00800000U
 384 #define  MATAGPERR     0x00400000U
 385 #define  INTXCLRPERR   0x00200000U
 386 #define  FIDPERR       0x00100000U
 387 #define  CFGSNPPERR    0x00080000U
 388 #define  HRSPPERR      0x00040000U
 389 #define  HREQPERR      0x00020000U
 390 #define  HCNTPERR      0x00010000U
 391 #define  DRSPPERR      0x00008000U
 392 #define  DREQPERR      0x00004000U
 393 #define  DCNTPERR      0x00002000U
 394 #define  CRSPPERR      0x00001000U
 395 #define  CREQPERR      0x00000800U
 396 #define  CCNTPERR      0x00000400U
 397 #define  TARTAGPERR    0x00000200U
 398 #define  PIOREQPERR    0x00000100U
 399 #define  PIOCPLPERR    0x00000080U
 400 #define  MSIXDIPERR    0x00000040U
 401 #define  MSIXDATAPERR  0x00000020U
 402 #define  MSIXADDRHPERR 0x00000010U
 403 #define  MSIXADDRLPERR 0x00000008U
 404 #define  MSIDATAPERR   0x00000004U
 405 #define  MSIADDRHPERR  0x00000002U
 406 #define  MSIADDRLPERR  0x00000001U
 407
 408 #define  READRSPERR      0x20000000U
 409 #define  TRGT1GRPPERR    0x10000000U
 410 #define  IPSOTPERR       0x08000000U
 411 #define  IPRXDATAGRPPERR 0x02000000U
 412 #define  IPRXHDRGRPPERR  0x01000000U
 413 #define  MAGRPPERR       0x00400000U
 414 #define  VFIDPERR        0x00200000U
 415 #define  HREQWRPERR      0x00010000U
 416 #define  DREQWRPERR      0x00002000U
 417 #define  MSTTAGQPERR     0x00000400U
 418 #define  PIOREQGRPPERR   0x00000100U
 419 #define  PIOCPLGRPPERR   0x00000080U
 420 #define  MSIXSTIPERR     0x00000004U
 421 #define  MSTTIMEOUTPERR  0x00000002U
 422 #define  MSTGRPPERR      0x00000001U
 423
 424 #define PCIE_NONFAT_ERR 0x3010
 425 #define PCIE_CFG_SPACE_REQ 0x3060
 426 #define PCIE_CFG_SPACE_DATA 0x3064
 427 #define PCIE_MEM_ACCESS_BASE_WIN 0x3068
 428 #define S_PCIEOFST       10
 429 #define M_PCIEOFST       0x3fffffU
 430 #define GET_PCIEOFST(x)  (((x) >> S_PCIEOFST) & M_PCIEOFST)
 431 #define  PCIEOFST_MASK   0xfffffc00U
 432 #define  BIR_MASK        0x00000300U
 433 #define  BIR_SHIFT       8
 434 #define  BIR(x)          ((x) << BIR_SHIFT)
 435 #define  WINDOW_MASK     0x000000ffU
 436 #define  WINDOW_SHIFT    0
 437 #define  WINDOW(x)       ((x) << WINDOW_SHIFT)
 438 #define  GET_WINDOW(x)   (((x) >> WINDOW_SHIFT) & WINDOW_MASK)
 439 #define PCIE_MEM_ACCESS_OFFSET 0x306c
 440 #define ENABLE  (1U << 30)
 441 #define FUNCTION(x) ((x) << 12)
 442 #define F_LOCALCFG    (1U << 28)
 443
 444 #define S_PFNUM    0
 445 #define V_PFNUM(x) ((x) << S_PFNUM)
 446
 447 #define PCIE_FW 0x30b8
 448 #define  PCIE_FW_ERR            0x80000000U
 449 #define  PCIE_FW_INIT           0x40000000U
 450 #define  PCIE_FW_HALT           0x20000000U
 451 #define  PCIE_FW_MASTER_VLD     0x00008000U
 452 #define  PCIE_FW_MASTER(x)      ((x) << 12)
 453 #define  PCIE_FW_MASTER_MASK    0x7
 454 #define  PCIE_FW_MASTER_GET(x)  (((x) >> 12) & PCIE_FW_MASTER_MASK)
 455
 456 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
 457 #define  RNPP 0x80000000U
 458 #define  RPCP 0x20000000U
 459 #define  RCIP 0x08000000U
 460 #define  RCCP 0x04000000U
 461 #define  RFTP 0x00800000U
 462 #define  PTRP 0x00100000U
 463
 464 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
 465 #define  TPCP 0x40000000U
 466 #define  TNPP 0x20000000U
 467 #define  TFTP 0x10000000U
 468 #define  TCAP 0x08000000U
 469 #define  TCIP 0x04000000U
 470 #define  RCAP 0x02000000U
 471 #define  PLUP 0x00800000U
 472 #define  PLDN 0x00400000U
 473 #define  OTDD 0x00200000U
 474 #define  GTRP 0x00100000U
 475 #define  RDPE 0x00040000U
 476 #define  TDCE 0x00020000U
 477 #define  TDUE 0x00010000U
 478
 479 #define MC_INT_CAUSE 0x7518
 480 #define MC_P_INT_CAUSE 0x41318
 481 #define  ECC_UE_INT_CAUSE 0x00000004U
 482 #define  ECC_CE_INT_CAUSE 0x00000002U
 483 #define  PERR_INT_CAUSE   0x00000001U
 484
 485 #define MC_ECC_STATUS 0x751c
 486 #define MC_P_ECC_STATUS 0x4131c
 487 #define  ECC_CECNT_MASK   0xffff0000U
 488 #define  ECC_CECNT_SHIFT  16
 489 #define  ECC_CECNT(x)     ((x) << ECC_CECNT_SHIFT)
 490 #define  ECC_CECNT_GET(x) (((x) & ECC_CECNT_MASK) >> ECC_CECNT_SHIFT)
 491 #define  ECC_UECNT_MASK   0x0000ffffU
 492 #define  ECC_UECNT_SHIFT  0
 493 #define  ECC_UECNT(x)     ((x) << ECC_UECNT_SHIFT)
 494 #define  ECC_UECNT_GET(x) (((x) & ECC_UECNT_MASK) >> ECC_UECNT_SHIFT)
 495
 496 #define MC_BIST_CMD 0x7600
 497 #define  START_BIST          0x80000000U
 498 #define  BIST_CMD_GAP_MASK   0x0000ff00U
 499 #define  BIST_CMD_GAP_SHIFT  8
 500 #define  BIST_CMD_GAP(x)     ((x) << BIST_CMD_GAP_SHIFT)
 501 #define  BIST_OPCODE_MASK    0x00000003U
 502 #define  BIST_OPCODE_SHIFT   0
 503 #define  BIST_OPCODE(x)      ((x) << BIST_OPCODE_SHIFT)
 504
 505 #define MC_BIST_CMD_ADDR 0x7604
 506 #define MC_BIST_CMD_LEN 0x7608
 507 #define MC_BIST_DATA_PATTERN 0x760c
 508 #define  BIST_DATA_TYPE_MASK   0x0000000fU
 509 #define  BIST_DATA_TYPE_SHIFT  0
 510 #define  BIST_DATA_TYPE(x)     ((x) << BIST_DATA_TYPE_SHIFT)
 511
 512 #define MC_BIST_STATUS_RDATA 0x7688
 513
 514 #define MA_EDRAM0_BAR_A 0x77c0
 515
 516 #define EDRAM0_SIZE_S    0
 517 #define EDRAM0_SIZE_M    0xfffU
 518 #define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
 519 #define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
 520
 521 #define MA_EDRAM1_BAR_A 0x77c4
 522
 523 #define EDRAM1_SIZE_S    0
 524 #define EDRAM1_SIZE_M    0xfffU
 525 #define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
 526 #define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
 527
 528 #define MA_EXT_MEMORY_BAR_A 0x77c8
 529
 530 #define EXT_MEM_SIZE_S    0
 531 #define EXT_MEM_SIZE_M    0xfffU
 532 #define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
 533 #define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
 534
 535 #define MA_EXT_MEMORY1_BAR_A 0x7808
 536
 537 #define EXT_MEM1_SIZE_S    0
 538 #define EXT_MEM1_SIZE_M    0xfffU
 539 #define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
 540 #define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
 541
 542 #define MA_EXT_MEMORY0_BAR_A 0x77c8
 543
 544 #define EXT_MEM0_SIZE_S    0
 545 #define EXT_MEM0_SIZE_M    0xfffU
 546 #define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
 547 #define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
 548
 549 #define MA_TARGET_MEM_ENABLE_A 0x77d8
 550
 551 #define EXT_MEM_ENABLE_S    2
 552 #define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
 553 #define EXT_MEM_ENABLE_F    EXT_MEM_ENABLE_V(1U)
 554
 555 #define EDRAM1_ENABLE_S    1
 556 #define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
 557 #define EDRAM1_ENABLE_F    EDRAM1_ENABLE_V(1U)
 558
 559 #define EDRAM0_ENABLE_S    0
 560 #define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
 561 #define EDRAM0_ENABLE_F    EDRAM0_ENABLE_V(1U)
 562
 563 #define EXT_MEM1_ENABLE_S    4
 564 #define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
 565 #define EXT_MEM1_ENABLE_F    EXT_MEM1_ENABLE_V(1U)
 566
 567 #define EXT_MEM0_ENABLE_S    2
 568 #define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
 569 #define EXT_MEM0_ENABLE_F    EXT_MEM0_ENABLE_V(1U)
 570
 571 #define MA_INT_CAUSE 0x77e0
 572 #define  MEM_PERR_INT_CAUSE 0x00000002U
 573 #define  MEM_WRAP_INT_CAUSE 0x00000001U
 574
 575 #define MA_INT_WRAP_STATUS 0x77e4
 576 #define  MEM_WRAP_ADDRESS_MASK   0xfffffff0U
 577 #define  MEM_WRAP_ADDRESS_SHIFT  4
 578 #define  MEM_WRAP_ADDRESS_GET(x) (((x) & MEM_WRAP_ADDRESS_MASK) >> MEM_WRAP_ADDRESS_SHIFT)
 579 #define  MEM_WRAP_CLIENT_NUM_MASK   0x0000000fU
 580 #define  MEM_WRAP_CLIENT_NUM_SHIFT  0
 581 #define  MEM_WRAP_CLIENT_NUM_GET(x) (((x) & MEM_WRAP_CLIENT_NUM_MASK) >> MEM_WRAP_CLIENT_NUM_SHIFT)
 582 #define MA_PCIE_FW 0x30b8
 583 #define MA_PARITY_ERROR_STATUS 0x77f4
 584 #define MA_PARITY_ERROR_STATUS2 0x7804
 585
 586 #define EDC_0_BASE_ADDR 0x7900
 587
 588 #define EDC_BIST_CMD 0x7904
 589 #define EDC_BIST_CMD_ADDR 0x7908
 590 #define EDC_BIST_CMD_LEN 0x790c
 591 #define EDC_BIST_DATA_PATTERN 0x7910
 592 #define EDC_BIST_STATUS_RDATA 0x7928
 593 #define EDC_INT_CAUSE 0x7978
 594 #define  ECC_UE_PAR     0x00000020U
 595 #define  ECC_CE_PAR     0x00000010U
 596 #define  PERR_PAR_CAUSE 0x00000008U
 597
 598 #define EDC_ECC_STATUS 0x797c
 599
 600 #define EDC_1_BASE_ADDR 0x7980
 601
 602 #define CIM_BOOT_CFG 0x7b00
 603 #define  BOOTADDR_MASK 0xffffff00U
 604 #define  UPCRST        0x1U
 605
 606 #define CIM_PF_MAILBOX_DATA 0x240
 607 #define CIM_PF_MAILBOX_CTRL 0x280
 608 #define  MBMSGVALID     0x00000008U
 609 #define  MBINTREQ       0x00000004U
 610 #define  MBOWNER_MASK   0x00000003U
 611 #define  MBOWNER_SHIFT  0
 612 #define  MBOWNER(x)     ((x) << MBOWNER_SHIFT)
 613 #define  MBOWNER_GET(x) (((x) & MBOWNER_MASK) >> MBOWNER_SHIFT)
 614
 615 #define CIM_PF_HOST_INT_ENABLE 0x288
 616 #define  MBMSGRDYINTEN(x) ((x) << 19)
 617
 618 #define CIM_PF_HOST_INT_CAUSE 0x28c
 619 #define  MBMSGRDYINT 0x00080000U
 620
 621 #define CIM_HOST_INT_CAUSE 0x7b2c
 622 #define  TIEQOUTPARERRINT  0x00100000U
 623 #define  TIEQINPARERRINT   0x00080000U
 624 #define  MBHOSTPARERR      0x00040000U
 625 #define  MBUPPARERR        0x00020000U
 626 #define  IBQPARERR         0x0001f800U
 627 #define  IBQTP0PARERR      0x00010000U
 628 #define  IBQTP1PARERR      0x00008000U
 629 #define  IBQULPPARERR      0x00004000U
 630 #define  IBQSGELOPARERR    0x00002000U
 631 #define  IBQSGEHIPARERR    0x00001000U
 632 #define  IBQNCSIPARERR     0x00000800U
 633 #define  OBQPARERR         0x000007e0U
 634 #define  OBQULP0PARERR     0x00000400U
 635 #define  OBQULP1PARERR     0x00000200U
 636 #define  OBQULP2PARERR     0x00000100U
 637 #define  OBQULP3PARERR     0x00000080U
 638 #define  OBQSGEPARERR      0x00000040U
 639 #define  OBQNCSIPARERR     0x00000020U
 640 #define  PREFDROPINT       0x00000002U
 641 #define  UPACCNONZERO      0x00000001U
 642
 643 #define CIM_HOST_UPACC_INT_CAUSE 0x7b34
 644 #define  EEPROMWRINT      0x40000000U
 645 #define  TIMEOUTMAINT     0x20000000U
 646 #define  TIMEOUTINT       0x10000000U
 647 #define  RSPOVRLOOKUPINT  0x08000000U
 648 #define  REQOVRLOOKUPINT  0x04000000U
 649 #define  BLKWRPLINT       0x02000000U
 650 #define  BLKRDPLINT       0x01000000U
 651 #define  SGLWRPLINT       0x00800000U
 652 #define  SGLRDPLINT       0x00400000U
 653 #define  BLKWRCTLINT      0x00200000U
 654 #define  BLKRDCTLINT      0x00100000U
 655 #define  SGLWRCTLINT      0x00080000U
 656 #define  SGLRDCTLINT      0x00040000U
 657 #define  BLKWREEPROMINT   0x00020000U
 658 #define  BLKRDEEPROMINT   0x00010000U
 659 #define  SGLWREEPROMINT   0x00008000U
 660 #define  SGLRDEEPROMINT   0x00004000U
 661 #define  BLKWRFLASHINT    0x00002000U
 662 #define  BLKRDFLASHINT    0x00001000U
 663 #define  SGLWRFLASHINT    0x00000800U
 664 #define  SGLRDFLASHINT    0x00000400U
 665 #define  BLKWRBOOTINT     0x00000200U
 666 #define  BLKRDBOOTINT     0x00000100U
 667 #define  SGLWRBOOTINT     0x00000080U
 668 #define  SGLRDBOOTINT     0x00000040U
 669 #define  ILLWRBEINT       0x00000020U
 670 #define  ILLRDBEINT       0x00000010U
 671 #define  ILLRDINT         0x00000008U
 672 #define  ILLWRINT         0x00000004U
 673 #define  ILLTRANSINT      0x00000002U
 674 #define  RSVDSPACEINT     0x00000001U
 675
 676 #define TP_OUT_CONFIG 0x7d04
 677 #define  VLANEXTENABLE_MASK  0x0000f000U
 678 #define  VLANEXTENABLE_SHIFT 12
 679
 680 #define TP_GLOBAL_CONFIG 0x7d08
 681 #define  FIVETUPLELOOKUP_SHIFT  17
 682 #define  FIVETUPLELOOKUP_MASK   0x00060000U
 683 #define  FIVETUPLELOOKUP(x)     ((x) << FIVETUPLELOOKUP_SHIFT)
 684 #define  FIVETUPLELOOKUP_GET(x) (((x) & FIVETUPLELOOKUP_MASK) >> \
 685                                 FIVETUPLELOOKUP_SHIFT)
 686
 687 #define TP_PARA_REG2 0x7d68
 688 #define  MAXRXDATA_MASK    0xffff0000U
 689 #define  MAXRXDATA_SHIFT   16
 690 #define  MAXRXDATA_GET(x) (((x) & MAXRXDATA_MASK) >> MAXRXDATA_SHIFT)
 691
 692 #define TP_TIMER_RESOLUTION 0x7d90
 693 #define  TIMERRESOLUTION_MASK   0x00ff0000U
 694 #define  TIMERRESOLUTION_SHIFT  16
 695 #define  TIMERRESOLUTION_GET(x) (((x) & TIMERRESOLUTION_MASK) >> TIMERRESOLUTION_SHIFT)
 696 #define  DELAYEDACKRESOLUTION_MASK 0x000000ffU
 697 #define  DELAYEDACKRESOLUTION_SHIFT     0
 698 #define  DELAYEDACKRESOLUTION_GET(x) \
 699         (((x) & DELAYEDACKRESOLUTION_MASK) >> DELAYEDACKRESOLUTION_SHIFT)
 700
 701 #define TP_SHIFT_CNT 0x7dc0
 702 #define  SYNSHIFTMAX_SHIFT         24
 703 #define  SYNSHIFTMAX_MASK          0xff000000U
 704 #define  SYNSHIFTMAX(x)            ((x) << SYNSHIFTMAX_SHIFT)
 705 #define  SYNSHIFTMAX_GET(x)        (((x) & SYNSHIFTMAX_MASK) >> \
 706                                    SYNSHIFTMAX_SHIFT)
 707 #define  RXTSHIFTMAXR1_SHIFT       20
 708 #define  RXTSHIFTMAXR1_MASK        0x00f00000U
 709 #define  RXTSHIFTMAXR1(x)          ((x) << RXTSHIFTMAXR1_SHIFT)
 710 #define  RXTSHIFTMAXR1_GET(x)      (((x) & RXTSHIFTMAXR1_MASK) >> \
 711                                    RXTSHIFTMAXR1_SHIFT)
 712 #define  RXTSHIFTMAXR2_SHIFT       16
 713 #define  RXTSHIFTMAXR2_MASK        0x000f0000U
 714 #define  RXTSHIFTMAXR2(x)          ((x) << RXTSHIFTMAXR2_SHIFT)
 715 #define  RXTSHIFTMAXR2_GET(x)      (((x) & RXTSHIFTMAXR2_MASK) >> \
 716                                    RXTSHIFTMAXR2_SHIFT)
 717 #define  PERSHIFTBACKOFFMAX_SHIFT  12
 718 #define  PERSHIFTBACKOFFMAX_MASK   0x0000f000U
 719 #define  PERSHIFTBACKOFFMAX(x)     ((x) << PERSHIFTBACKOFFMAX_SHIFT)
 720 #define  PERSHIFTBACKOFFMAX_GET(x) (((x) & PERSHIFTBACKOFFMAX_MASK) >> \
 721                                    PERSHIFTBACKOFFMAX_SHIFT)
 722 #define  PERSHIFTMAX_SHIFT         8
 723 #define  PERSHIFTMAX_MASK          0x00000f00U
 724 #define  PERSHIFTMAX(x)            ((x) << PERSHIFTMAX_SHIFT)
 725 #define  PERSHIFTMAX_GET(x)        (((x) & PERSHIFTMAX_MASK) >> \
 726                                    PERSHIFTMAX_SHIFT)
 727 #define  KEEPALIVEMAXR1_SHIFT      4
 728 #define  KEEPALIVEMAXR1_MASK       0x000000f0U
 729 #define  KEEPALIVEMAXR1(x)         ((x) << KEEPALIVEMAXR1_SHIFT)
 730 #define  KEEPALIVEMAXR1_GET(x)     (((x) & KEEPALIVEMAXR1_MASK) >> \
 731                                    KEEPALIVEMAXR1_SHIFT)
 732 #define KEEPALIVEMAXR2_SHIFT       0
 733 #define KEEPALIVEMAXR2_MASK        0x0000000fU
 734 #define KEEPALIVEMAXR2(x)          ((x) << KEEPALIVEMAXR2_SHIFT)
 735 #define KEEPALIVEMAXR2_GET(x)      (((x) & KEEPALIVEMAXR2_MASK) >> \
 736                                    KEEPALIVEMAXR2_SHIFT)
 737
 738 #define TP_CCTRL_TABLE 0x7ddc
 739 #define TP_MTU_TABLE 0x7de4
 740 #define  MTUINDEX_MASK   0xff000000U
 741 #define  MTUINDEX_SHIFT  24
 742 #define  MTUINDEX(x)     ((x) << MTUINDEX_SHIFT)
 743 #define  MTUWIDTH_MASK   0x000f0000U
 744 #define  MTUWIDTH_SHIFT  16
 745 #define  MTUWIDTH(x)     ((x) << MTUWIDTH_SHIFT)
 746 #define  MTUWIDTH_GET(x) (((x) & MTUWIDTH_MASK) >> MTUWIDTH_SHIFT)
 747 #define  MTUVALUE_MASK   0x00003fffU
 748 #define  MTUVALUE_SHIFT  0
 749 #define  MTUVALUE(x)     ((x) << MTUVALUE_SHIFT)
 750 #define  MTUVALUE_GET(x) (((x) & MTUVALUE_MASK) >> MTUVALUE_SHIFT)
 751
 752 #define TP_RSS_LKP_TABLE 0x7dec
 753 #define  LKPTBLROWVLD        0x80000000U
 754 #define  LKPTBLQUEUE1_MASK   0x000ffc00U
 755 #define  LKPTBLQUEUE1_SHIFT  10
 756 #define  LKPTBLQUEUE1(x)     ((x) << LKPTBLQUEUE1_SHIFT)
 757 #define  LKPTBLQUEUE1_GET(x) (((x) & LKPTBLQUEUE1_MASK) >> LKPTBLQUEUE1_SHIFT)
 758 #define  LKPTBLQUEUE0_MASK   0x000003ffU
 759 #define  LKPTBLQUEUE0_SHIFT  0
 760 #define  LKPTBLQUEUE0(x)     ((x) << LKPTBLQUEUE0_SHIFT)
 761 #define  LKPTBLQUEUE0_GET(x) (((x) & LKPTBLQUEUE0_MASK) >> LKPTBLQUEUE0_SHIFT)
 762
 763 #define TP_PIO_ADDR 0x7e40
 764 #define TP_PIO_DATA 0x7e44
 765 #define TP_MIB_INDEX 0x7e50
 766 #define TP_MIB_DATA 0x7e54
 767 #define TP_INT_CAUSE 0x7e74
 768 #define  FLMTXFLSTEMPTY 0x40000000U
 769
 770 #define TP_VLAN_PRI_MAP 0x140
 771 #define  FRAGMENTATION_SHIFT 9
 772 #define  FRAGMENTATION_MASK  0x00000200U
 773 #define  MPSHITTYPE_MASK     0x00000100U
 774 #define  MACMATCH_MASK       0x00000080U
 775 #define  ETHERTYPE_MASK      0x00000040U
 776 #define  PROTOCOL_MASK       0x00000020U
 777 #define  TOS_MASK            0x00000010U
 778 #define  VLAN_MASK           0x00000008U
 779 #define  VNIC_ID_MASK        0x00000004U
 780 #define  PORT_MASK           0x00000002U
 781 #define  FCOE_SHIFT          0
 782 #define  FCOE_MASK           0x00000001U
 783
 784 #define TP_INGRESS_CONFIG 0x141
 785 #define  VNIC                0x00000800U
 786 #define  CSUM_HAS_PSEUDO_HDR 0x00000400U
 787 #define  RM_OVLAN            0x00000200U
 788 #define  LOOKUPEVERYPKT      0x00000100U
 789
 790 #define TP_MIB_MAC_IN_ERR_0 0x0
 791 #define TP_MIB_TCP_OUT_RST 0xc
 792 #define TP_MIB_TCP_IN_SEG_HI 0x10
 793 #define TP_MIB_TCP_IN_SEG_LO 0x11
 794 #define TP_MIB_TCP_OUT_SEG_HI 0x12
 795 #define TP_MIB_TCP_OUT_SEG_LO 0x13
 796 #define TP_MIB_TCP_RXT_SEG_HI 0x14
 797 #define TP_MIB_TCP_RXT_SEG_LO 0x15
 798 #define TP_MIB_TNL_CNG_DROP_0 0x18
 799 #define TP_MIB_TCP_V6IN_ERR_0 0x28
 800 #define TP_MIB_TCP_V6OUT_RST 0x2c
 801 #define TP_MIB_OFD_ARP_DROP 0x36
 802 #define TP_MIB_TNL_DROP_0 0x44
 803 #define TP_MIB_OFD_VLN_DROP_0 0x58
 804
 805 #define ULP_TX_INT_CAUSE 0x8dcc
 806 #define  PBL_BOUND_ERR_CH3 0x80000000U
 807 #define  PBL_BOUND_ERR_CH2 0x40000000U
 808 #define  PBL_BOUND_ERR_CH1 0x20000000U
 809 #define  PBL_BOUND_ERR_CH0 0x10000000U
 810
 811 #define PM_RX_INT_CAUSE 0x8fdc
 812 #define  ZERO_E_CMD_ERROR     0x00400000U
 813 #define  PMRX_FRAMING_ERROR   0x003ffff0U
 814 #define  OCSPI_PAR_ERROR      0x00000008U
 815 #define  DB_OPTIONS_PAR_ERROR 0x00000004U
 816 #define  IESPI_PAR_ERROR      0x00000002U
 817 #define  E_PCMD_PAR_ERROR     0x00000001U
 818
 819 #define PM_TX_INT_CAUSE 0x8ffc
 820 #define  PCMD_LEN_OVFL0     0x80000000U
 821 #define  PCMD_LEN_OVFL1     0x40000000U
 822 #define  PCMD_LEN_OVFL2     0x20000000U
 823 #define  ZERO_C_CMD_ERROR   0x10000000U
 824 #define  PMTX_FRAMING_ERROR 0x0ffffff0U
 825 #define  OESPI_PAR_ERROR    0x00000008U
 826 #define  ICSPI_PAR_ERROR    0x00000002U
 827 #define  C_PCMD_PAR_ERROR   0x00000001U
 828
 829 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
 830 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
 831 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
 832 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
 833 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
 834 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
 835 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
 836 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
 837 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
 838 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
 839 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
 840 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
 841 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
 842 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
 843 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
 844 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
 845 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
 846 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
 847 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
 848 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
 849 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
 850 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
 851 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
 852 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
 853 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
 854 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
 855 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
 856 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
 857 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
 858 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
 859 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
 860 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
 861 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
 862 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
 863 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
 864 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
 865 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
 866 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
 867 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
 868 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
 869 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
 870 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
 871 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
 872 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
 873 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
 874 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
 875 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
 876 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
 877 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
 878 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
 879 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
 880 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
 881 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
 882 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
 883 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
 884 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
 885 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
 886 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
 887 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
 888 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
 889 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
 890 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
 891 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
 892 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
 893 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
 894 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
 895 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
 896 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
 897 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
 898 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
 899 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
 900 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
 901 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
 902 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
 903 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
 904 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
 905 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
 906 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
 907 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
 908 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
 909 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
 910 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
 911 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
 912 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
 913 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
 914 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
 915 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
 916 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
 917 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
 918 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
 919 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
 920 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
 921 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
 922 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
 923 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
 924 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
 925 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
 926 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
 927 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
 928 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
 929 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
 930 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
 931 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
 932 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
 933 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
 934 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
 935 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
 936 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
 937 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
 938 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
 939 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
 940 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
 941 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
 942 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
 943 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
 944 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
 945 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
 946 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
 947 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
 948 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
 949 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
 950 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
 951 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
 952 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
 953 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
 954 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
 955 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
 956 #define MAC_PORT_CFG2 0x818
 957 #define MAC_PORT_MAGIC_MACID_LO 0x824
 958 #define MAC_PORT_MAGIC_MACID_HI 0x828
 959 #define MAC_PORT_EPIO_DATA0 0x8c0
 960 #define MAC_PORT_EPIO_DATA1 0x8c4
 961 #define MAC_PORT_EPIO_DATA2 0x8c8
 962 #define MAC_PORT_EPIO_DATA3 0x8cc
 963 #define MAC_PORT_EPIO_OP 0x8d0
 964
 965 #define MPS_CMN_CTL 0x9000
 966 #define  NUMPORTS_MASK   0x00000003U
 967 #define  NUMPORTS_SHIFT  0
 968 #define  NUMPORTS_GET(x) (((x) & NUMPORTS_MASK) >> NUMPORTS_SHIFT)
 969
 970 #define MPS_INT_CAUSE 0x9008
 971 #define  STATINT 0x00000020U
 972 #define  TXINT   0x00000010U
 973 #define  RXINT   0x00000008U
 974 #define  TRCINT  0x00000004U
 975 #define  CLSINT  0x00000002U
 976 #define  PLINT   0x00000001U
 977
 978 #define MPS_TX_INT_CAUSE 0x9408
 979 #define  PORTERR    0x00010000U
 980 #define  FRMERR     0x00008000U
 981 #define  SECNTERR   0x00004000U
 982 #define  BUBBLE     0x00002000U
 983 #define  TXDESCFIFO 0x00001e00U
 984 #define  TXDATAFIFO 0x000001e0U
 985 #define  NCSIFIFO   0x00000010U
 986 #define  TPFIFO     0x0000000fU
 987
 988 #define MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
 989 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
 990 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
 991
 992 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
 993 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
 994 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
 995 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
 996 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
 997 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
 998 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
 999 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1000 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1001 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1002 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1003 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1004 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1005 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1006 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1007 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1008 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1009 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1010 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1011 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1012 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1013 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1014 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1015 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1016 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1017 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1018 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1019 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1020 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1021 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1022 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1023 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1024 #define MPS_TRC_CFG 0x9800
1025 #define  TRCFIFOEMPTY       0x00000010U
1026 #define  TRCIGNOREDROPINPUT 0x00000008U
1027 #define  TRCKEEPDUPLICATES  0x00000004U
1028 #define  TRCEN              0x00000002U
1029 #define  TRCMULTIFILTER     0x00000001U
1030
1031 #define MPS_TRC_RSS_CONTROL 0x9808
1032 #define MPS_T5_TRC_RSS_CONTROL 0xa00c
1033 #define  RSSCONTROL_MASK    0x00ff0000U
1034 #define  RSSCONTROL_SHIFT   16
1035 #define  RSSCONTROL(x)      ((x) << RSSCONTROL_SHIFT)
1036 #define  QUEUENUMBER_MASK   0x0000ffffU
1037 #define  QUEUENUMBER_SHIFT  0
1038 #define  QUEUENUMBER(x)     ((x) << QUEUENUMBER_SHIFT)
1039
1040 #define MPS_TRC_FILTER_MATCH_CTL_A 0x9810
1041 #define  TFINVERTMATCH   0x01000000U
1042 #define  TFPKTTOOLARGE   0x00800000U
1043 #define  TFEN            0x00400000U
1044 #define  TFPORT_MASK     0x003c0000U
1045 #define  TFPORT_SHIFT    18
1046 #define  TFPORT(x)       ((x) << TFPORT_SHIFT)
1047 #define  TFPORT_GET(x)   (((x) & TFPORT_MASK) >> TFPORT_SHIFT)
1048 #define  TFDROP          0x00020000U
1049 #define  TFSOPEOPERR     0x00010000U
1050 #define  TFLENGTH_MASK   0x00001f00U
1051 #define  TFLENGTH_SHIFT  8
1052 #define  TFLENGTH(x)     ((x) << TFLENGTH_SHIFT)
1053 #define  TFLENGTH_GET(x) (((x) & TFLENGTH_MASK) >> TFLENGTH_SHIFT)
1054 #define  TFOFFSET_MASK   0x0000001fU
1055 #define  TFOFFSET_SHIFT  0
1056 #define  TFOFFSET(x)     ((x) << TFOFFSET_SHIFT)
1057 #define  TFOFFSET_GET(x) (((x) & TFOFFSET_MASK) >> TFOFFSET_SHIFT)
1058
1059 #define MPS_TRC_FILTER_MATCH_CTL_B 0x9820
1060 #define  TFMINPKTSIZE_MASK   0x01ff0000U
1061 #define  TFMINPKTSIZE_SHIFT  16
1062 #define  TFMINPKTSIZE(x)     ((x) << TFMINPKTSIZE_SHIFT)
1063 #define  TFMINPKTSIZE_GET(x) (((x) & TFMINPKTSIZE_MASK) >> TFMINPKTSIZE_SHIFT)
1064 #define  TFCAPTUREMAX_MASK   0x00003fffU
1065 #define  TFCAPTUREMAX_SHIFT  0
1066 #define  TFCAPTUREMAX(x)     ((x) << TFCAPTUREMAX_SHIFT)
1067 #define  TFCAPTUREMAX_GET(x) (((x) & TFCAPTUREMAX_MASK) >> TFCAPTUREMAX_SHIFT)
1068
1069 #define MPS_TRC_INT_CAUSE 0x985c
1070 #define  MISCPERR 0x00000100U
1071 #define  PKTFIFO  0x000000f0U
1072 #define  FILTMEM  0x0000000fU
1073
1074 #define MPS_TRC_FILTER0_MATCH 0x9c00
1075 #define MPS_TRC_FILTER0_DONT_CARE 0x9c80
1076 #define MPS_TRC_FILTER1_MATCH 0x9d00
1077 #define MPS_CLS_INT_CAUSE 0xd028
1078 #define  PLERRENB  0x00000008U
1079 #define  HASHSRAM  0x00000004U
1080 #define  MATCHTCAM 0x00000002U
1081 #define  MATCHSRAM 0x00000001U
1082
1083 #define MPS_RX_PERR_INT_CAUSE 0x11074
1084
1085 #define CPL_INTR_CAUSE 0x19054
1086 #define  CIM_OP_MAP_PERR   0x00000020U
1087 #define  CIM_OVFL_ERROR    0x00000010U
1088 #define  TP_FRAMING_ERROR  0x00000008U
1089 #define  SGE_FRAMING_ERROR 0x00000004U
1090 #define  CIM_FRAMING_ERROR 0x00000002U
1091 #define  ZERO_SWITCH_ERROR 0x00000001U
1092
1093 #define SMB_INT_CAUSE 0x19090
1094 #define  MSTTXFIFOPARINT 0x00200000U
1095 #define  MSTRXFIFOPARINT 0x00100000U
1096 #define  SLVFIFOPARINT   0x00080000U
1097
1098 #define ULP_RX_INT_CAUSE 0x19158
1099 #define ULP_RX_ISCSI_TAGMASK 0x19164
1100 #define ULP_RX_ISCSI_PSZ 0x19168
1101 #define  HPZ3_MASK   0x0f000000U
1102 #define  HPZ3_SHIFT  24
1103 #define  HPZ3(x)     ((x) << HPZ3_SHIFT)
1104 #define  HPZ2_MASK   0x000f0000U
1105 #define  HPZ2_SHIFT  16
1106 #define  HPZ2(x)     ((x) << HPZ2_SHIFT)
1107 #define  HPZ1_MASK   0x00000f00U
1108 #define  HPZ1_SHIFT  8
1109 #define  HPZ1(x)     ((x) << HPZ1_SHIFT)
1110 #define  HPZ0_MASK   0x0000000fU
1111 #define  HPZ0_SHIFT  0
1112 #define  HPZ0(x)     ((x) << HPZ0_SHIFT)
1113
1114 #define ULP_RX_TDDP_PSZ 0x19178
1115
1116 #define SF_DATA 0x193f8
1117 #define SF_OP 0x193fc
1118 #define  SF_BUSY       0x80000000U
1119 #define  SF_LOCK       0x00000010U
1120 #define  SF_CONT       0x00000008U
1121 #define  BYTECNT_MASK  0x00000006U
1122 #define  BYTECNT_SHIFT 1
1123 #define  BYTECNT(x)    ((x) << BYTECNT_SHIFT)
1124 #define  OP_WR         0x00000001U
1125
1126 #define PL_PF_INT_CAUSE 0x3c0
1127 #define  PFSW  0x00000008U
1128 #define  PFSGE 0x00000004U
1129 #define  PFCIM 0x00000002U
1130 #define  PFMPS 0x00000001U
1131
1132 #define PL_PF_INT_ENABLE 0x3c4
1133 #define PL_PF_CTL 0x3c8
1134 #define  SWINT 0x00000001U
1135
1136 #define PL_WHOAMI 0x19400
1137 #define  SOURCEPF_MASK   0x00000700U
1138 #define  SOURCEPF_SHIFT  8
1139 #define  SOURCEPF(x)     ((x) << SOURCEPF_SHIFT)
1140 #define  SOURCEPF_GET(x) (((x) & SOURCEPF_MASK) >> SOURCEPF_SHIFT)
1141 #define  ISVF            0x00000080U
1142 #define  VFID_MASK       0x0000007fU
1143 #define  VFID_SHIFT      0
1144 #define  VFID(x)         ((x) << VFID_SHIFT)
1145 #define  VFID_GET(x)     (((x) & VFID_MASK) >> VFID_SHIFT)
1146
1147 #define PL_INT_CAUSE 0x1940c
1148 #define  ULP_TX     0x08000000U
1149 #define  SGE        0x04000000U
1150 #define  HMA        0x02000000U
1151 #define  CPL_SWITCH 0x01000000U
1152 #define  ULP_RX     0x00800000U
1153 #define  PM_RX      0x00400000U
1154 #define  PM_TX      0x00200000U
1155 #define  MA         0x00100000U
1156 #define  TP         0x00080000U
1157 #define  LE         0x00040000U
1158 #define  EDC1       0x00020000U
1159 #define  EDC0       0x00010000U
1160 #define  MC         0x00008000U
1161 #define  PCIE       0x00004000U
1162 #define  PMU        0x00002000U
1163 #define  XGMAC_KR1  0x00001000U
1164 #define  XGMAC_KR0  0x00000800U
1165 #define  XGMAC1     0x00000400U
1166 #define  XGMAC0     0x00000200U
1167 #define  SMB        0x00000100U
1168 #define  SF         0x00000080U
1169 #define  PL         0x00000040U
1170 #define  NCSI       0x00000020U
1171 #define  MPS        0x00000010U
1172 #define  MI         0x00000008U
1173 #define  DBG        0x00000004U
1174 #define  I2CM       0x00000002U
1175 #define  CIM        0x00000001U
1176
1177 #define MC1 0x31
1178 #define PL_INT_ENABLE 0x19410
1179 #define PL_INT_MAP0 0x19414
1180 #define PL_RST 0x19428
1181 #define  PIORST     0x00000002U
1182 #define  PIORSTMODE 0x00000001U
1183
1184 #define PL_PL_INT_CAUSE 0x19430
1185 #define  FATALPERR 0x00000010U
1186 #define  PERRVFID  0x00000001U
1187
1188 #define PL_REV 0x1943c
1189
1190 #define S_REV    0
1191 #define M_REV    0xfU
1192 #define V_REV(x) ((x) << S_REV)
1193 #define G_REV(x) (((x) >> S_REV) & M_REV)
1194
1195 #define LE_DB_CONFIG 0x19c04
1196 #define  HASHEN 0x00100000U
1197
1198 #define LE_DB_SERVER_INDEX 0x19c18
1199 #define LE_DB_ACT_CNT_IPV4 0x19c20
1200 #define LE_DB_ACT_CNT_IPV6 0x19c24
1201
1202 #define LE_DB_INT_CAUSE 0x19c3c
1203 #define  REQQPARERR 0x00010000U
1204 #define  UNKNOWNCMD 0x00008000U
1205 #define  PARITYERR  0x00000040U
1206 #define  LIPMISS    0x00000020U
1207 #define  LIP0       0x00000010U
1208
1209 #define LE_DB_TID_HASHBASE 0x19df8
1210
1211 #define NCSI_INT_CAUSE 0x1a0d8
1212 #define  CIM_DM_PRTY_ERR 0x00000100U
1213 #define  MPS_DM_PRTY_ERR 0x00000080U
1214 #define  TXFIFO_PRTY_ERR 0x00000002U
1215 #define  RXFIFO_PRTY_ERR 0x00000001U
1216
1217 #define XGMAC_PORT_CFG2 0x1018
1218 #define  PATEN   0x00040000U
1219 #define  MAGICEN 0x00020000U
1220
1221 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
1222 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
1223
1224 #define XGMAC_PORT_EPIO_DATA0 0x10c0
1225 #define XGMAC_PORT_EPIO_DATA1 0x10c4
1226 #define XGMAC_PORT_EPIO_DATA2 0x10c8
1227 #define XGMAC_PORT_EPIO_DATA3 0x10cc
1228 #define XGMAC_PORT_EPIO_OP 0x10d0
1229 #define  EPIOWR         0x00000100U
1230 #define  ADDRESS_MASK   0x000000ffU
1231 #define  ADDRESS_SHIFT  0
1232 #define  ADDRESS(x)     ((x) << ADDRESS_SHIFT)
1233
1234 #define MAC_PORT_INT_CAUSE 0x8dc
1235 #define XGMAC_PORT_INT_CAUSE 0x10dc
1236
1237 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
1238
1239 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
1240
1241 #define S_TX_MOD_QUEUE_REQ_MAP    0
1242 #define M_TX_MOD_QUEUE_REQ_MAP    0xffffU
1243 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
1244
1245 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
1246
1247 #define S_TX_MODQ_WEIGHT3    24
1248 #define M_TX_MODQ_WEIGHT3    0xffU
1249 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
1250
1251 #define S_TX_MODQ_WEIGHT2    16
1252 #define M_TX_MODQ_WEIGHT2    0xffU
1253 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
1254
1255 #define S_TX_MODQ_WEIGHT1    8
1256 #define M_TX_MODQ_WEIGHT1    0xffU
1257 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
1258
1259 #define S_TX_MODQ_WEIGHT0    0
1260 #define M_TX_MODQ_WEIGHT0    0xffU
1261 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
1262
1263 #define A_TP_TX_SCHED_HDR 0x23
1264
1265 #define A_TP_TX_SCHED_FIFO 0x24
1266
1267 #define A_TP_TX_SCHED_PCMD 0x25
1268
1269 #define S_VNIC    11
1270 #define V_VNIC(x) ((x) << S_VNIC)
1271 #define F_VNIC    V_VNIC(1U)
1272
1273 #define S_FRAGMENTATION    9
1274 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
1275 #define F_FRAGMENTATION    V_FRAGMENTATION(1U)
1276
1277 #define S_MPSHITTYPE    8
1278 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
1279 #define F_MPSHITTYPE    V_MPSHITTYPE(1U)
1280
1281 #define S_MACMATCH    7
1282 #define V_MACMATCH(x) ((x) << S_MACMATCH)
1283 #define F_MACMATCH    V_MACMATCH(1U)
1284
1285 #define S_ETHERTYPE    6
1286 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
1287 #define F_ETHERTYPE    V_ETHERTYPE(1U)
1288
1289 #define S_PROTOCOL    5
1290 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
1291 #define F_PROTOCOL    V_PROTOCOL(1U)
1292
1293 #define S_TOS    4
1294 #define V_TOS(x) ((x) << S_TOS)
1295 #define F_TOS    V_TOS(1U)
1296
1297 #define S_VLAN    3
1298 #define V_VLAN(x) ((x) << S_VLAN)
1299 #define F_VLAN    V_VLAN(1U)
1300
1301 #define S_VNIC_ID    2
1302 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
1303 #define F_VNIC_ID    V_VNIC_ID(1U)
1304
1305 #define S_PORT    1
1306 #define V_PORT(x) ((x) << S_PORT)
1307 #define F_PORT    V_PORT(1U)
1308
1309 #define S_FCOE    0
1310 #define V_FCOE(x) ((x) << S_FCOE)
1311 #define F_FCOE    V_FCOE(1U)
1312
1313 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
1314 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
1315
1316 #define T5_PORT0_BASE 0x30000
1317 #define T5_PORT_STRIDE 0x4000
1318 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
1319 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
1320
1321 #define MC_0_BASE_ADDR 0x40000
1322 #define MC_1_BASE_ADDR 0x48000
1323 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
1324 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
1325
1326 #define MC_P_BIST_CMD 0x41400
1327 #define MC_P_BIST_CMD_ADDR 0x41404
1328 #define MC_P_BIST_CMD_LEN 0x41408
1329 #define MC_P_BIST_DATA_PATTERN 0x4140c
1330 #define MC_P_BIST_STATUS_RDATA 0x41488
1331 #define EDC_T50_BASE_ADDR 0x50000
1332 #define EDC_H_BIST_CMD 0x50004
1333 #define EDC_H_BIST_CMD_ADDR 0x50008
1334 #define EDC_H_BIST_CMD_LEN 0x5000c
1335 #define EDC_H_BIST_DATA_PATTERN 0x50010
1336 #define EDC_H_BIST_STATUS_RDATA 0x50028
1337
1338 #define EDC_T51_BASE_ADDR 0x50800
1339 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
1340 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
1341
1342 #define A_PL_VF_REV 0x4
1343 #define A_PL_VF_WHOAMI 0x0
1344 #define A_PL_VF_REVISION 0x8
1345
1346 #define S_CHIPID    4
1347 #define M_CHIPID    0xfU
1348 #define V_CHIPID(x) ((x) << S_CHIPID)
1349 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
1350
1351 /* TP_VLAN_PRI_MAP controls which subset of fields will be present in the
1352  * Compressed Filter Tuple for LE filters.  Each bit set in TP_VLAN_PRI_MAP
1353  * selects for a particular field being present.  These fields, when present
1354  * in the Compressed Filter Tuple, have the following widths in bits.
1355  */
1356 #define W_FT_FCOE                       1
1357 #define W_FT_PORT                       3
1358 #define W_FT_VNIC_ID                    17
1359 #define W_FT_VLAN                       17
1360 #define W_FT_TOS                        8
1361 #define W_FT_PROTOCOL                   8
1362 #define W_FT_ETHERTYPE                  16
1363 #define W_FT_MACMATCH                   9
1364 #define W_FT_MPSHITTYPE                 3
1365 #define W_FT_FRAGMENTATION              1
1366
1367 /* Some of the Compressed Filter Tuple fields have internal structure.  These
1368  * bit shifts/masks describe those structures.  All shifts are relative to the
1369  * base position of the fields within the Compressed Filter Tuple
1370  */
1371 #define S_FT_VLAN_VLD                   16
1372 #define V_FT_VLAN_VLD(x)                ((x) << S_FT_VLAN_VLD)
1373 #define F_FT_VLAN_VLD                   V_FT_VLAN_VLD(1U)
1374
1375 #define S_FT_VNID_ID_VF                 0
1376 #define V_FT_VNID_ID_VF(x)              ((x) << S_FT_VNID_ID_VF)
1377
1378 #define S_FT_VNID_ID_PF                 7
1379 #define V_FT_VNID_ID_PF(x)              ((x) << S_FT_VNID_ID_PF)
1380
1381 #define S_FT_VNID_ID_VLD                16
1382 #define V_FT_VNID_ID_VLD(x)             ((x) << S_FT_VNID_ID_VLD)
1383
1384 #endif /* __T4_REGS_H */