2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 #define MYPF_BASE 0x1b000
39 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
41 #define PF0_BASE 0x1e000
42 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
44 #define PF_STRIDE 0x400
45 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
46 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
48 #define MYPORT_BASE 0x1c000
49 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
51 #define PORT0_BASE 0x20000
52 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
54 #define PORT_STRIDE 0x2000
55 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
58 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
59 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
61 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
62 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
63 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
64 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
66 #define SGE_PF_KDOORBELL_A 0x0
69 #define QID_V(x) ((x) << QID_S)
72 #define DBPRIO_V(x) ((x) << DBPRIO_S)
73 #define DBPRIO_F DBPRIO_V(1U)
76 #define PIDX_V(x) ((x) << PIDX_S)
78 #define SGE_VF_KDOORBELL_A 0x0
81 #define DBTYPE_V(x) ((x) << DBTYPE_S)
82 #define DBTYPE_F DBTYPE_V(1U)
85 #define PIDX_T5_M 0x1fffU
86 #define PIDX_T5_V(x) ((x) << PIDX_T5_S)
87 #define PIDX_T5_G(x) (((x) >> PIDX_T5_S) & PIDX_T5_M)
89 #define SGE_PF_GTS_A 0x4
91 #define INGRESSQID_S 16
92 #define INGRESSQID_V(x) ((x) << INGRESSQID_S)
95 #define TIMERREG_V(x) ((x) << TIMERREG_S)
98 #define SEINTARM_V(x) ((x) << SEINTARM_S)
101 #define CIDXINC_M 0xfffU
102 #define CIDXINC_V(x) ((x) << CIDXINC_S)
104 #define SGE_CONTROL_A 0x1008
105 #define SGE_CONTROL2_A 0x1124
107 #define RXPKTCPLMODE_S 18
108 #define RXPKTCPLMODE_V(x) ((x) << RXPKTCPLMODE_S)
109 #define RXPKTCPLMODE_F RXPKTCPLMODE_V(1U)
111 #define EGRSTATUSPAGESIZE_S 17
112 #define EGRSTATUSPAGESIZE_V(x) ((x) << EGRSTATUSPAGESIZE_S)
113 #define EGRSTATUSPAGESIZE_F EGRSTATUSPAGESIZE_V(1U)
115 #define PKTSHIFT_S 10
116 #define PKTSHIFT_M 0x7U
117 #define PKTSHIFT_V(x) ((x) << PKTSHIFT_S)
118 #define PKTSHIFT_G(x) (((x) >> PKTSHIFT_S) & PKTSHIFT_M)
120 #define INGPCIEBOUNDARY_S 7
121 #define INGPCIEBOUNDARY_V(x) ((x) << INGPCIEBOUNDARY_S)
123 #define INGPADBOUNDARY_S 4
124 #define INGPADBOUNDARY_M 0x7U
125 #define INGPADBOUNDARY_V(x) ((x) << INGPADBOUNDARY_S)
126 #define INGPADBOUNDARY_G(x) (((x) >> INGPADBOUNDARY_S) & INGPADBOUNDARY_M)
128 #define EGRPCIEBOUNDARY_S 1
129 #define EGRPCIEBOUNDARY_V(x) ((x) << EGRPCIEBOUNDARY_S)
131 #define INGPACKBOUNDARY_S 16
132 #define INGPACKBOUNDARY_M 0x7U
133 #define INGPACKBOUNDARY_V(x) ((x) << INGPACKBOUNDARY_S)
134 #define INGPACKBOUNDARY_G(x) (((x) >> INGPACKBOUNDARY_S) \
137 #define GLOBALENABLE_S 0
138 #define GLOBALENABLE_V(x) ((x) << GLOBALENABLE_S)
139 #define GLOBALENABLE_F GLOBALENABLE_V(1U)
141 #define SGE_HOST_PAGE_SIZE_A 0x100c
143 #define HOSTPAGESIZEPF7_S 28
144 #define HOSTPAGESIZEPF7_M 0xfU
145 #define HOSTPAGESIZEPF7_V(x) ((x) << HOSTPAGESIZEPF7_S)
146 #define HOSTPAGESIZEPF7_G(x) (((x) >> HOSTPAGESIZEPF7_S) & HOSTPAGESIZEPF7_M)
148 #define HOSTPAGESIZEPF6_S 24
149 #define HOSTPAGESIZEPF6_M 0xfU
150 #define HOSTPAGESIZEPF6_V(x) ((x) << HOSTPAGESIZEPF6_S)
151 #define HOSTPAGESIZEPF6_G(x) (((x) >> HOSTPAGESIZEPF6_S) & HOSTPAGESIZEPF6_M)
153 #define HOSTPAGESIZEPF5_S 20
154 #define HOSTPAGESIZEPF5_M 0xfU
155 #define HOSTPAGESIZEPF5_V(x) ((x) << HOSTPAGESIZEPF5_S)
156 #define HOSTPAGESIZEPF5_G(x) (((x) >> HOSTPAGESIZEPF5_S) & HOSTPAGESIZEPF5_M)
158 #define HOSTPAGESIZEPF4_S 16
159 #define HOSTPAGESIZEPF4_M 0xfU
160 #define HOSTPAGESIZEPF4_V(x) ((x) << HOSTPAGESIZEPF4_S)
161 #define HOSTPAGESIZEPF4_G(x) (((x) >> HOSTPAGESIZEPF4_S) & HOSTPAGESIZEPF4_M)
163 #define HOSTPAGESIZEPF3_S 12
164 #define HOSTPAGESIZEPF3_M 0xfU
165 #define HOSTPAGESIZEPF3_V(x) ((x) << HOSTPAGESIZEPF3_S)
166 #define HOSTPAGESIZEPF3_G(x) (((x) >> HOSTPAGESIZEPF3_S) & HOSTPAGESIZEPF3_M)
168 #define HOSTPAGESIZEPF2_S 8
169 #define HOSTPAGESIZEPF2_M 0xfU
170 #define HOSTPAGESIZEPF2_V(x) ((x) << HOSTPAGESIZEPF2_S)
171 #define HOSTPAGESIZEPF2_G(x) (((x) >> HOSTPAGESIZEPF2_S) & HOSTPAGESIZEPF2_M)
173 #define HOSTPAGESIZEPF1_S 4
174 #define HOSTPAGESIZEPF1_M 0xfU
175 #define HOSTPAGESIZEPF1_V(x) ((x) << HOSTPAGESIZEPF1_S)
176 #define HOSTPAGESIZEPF1_G(x) (((x) >> HOSTPAGESIZEPF1_S) & HOSTPAGESIZEPF1_M)
178 #define HOSTPAGESIZEPF0_S 0
179 #define HOSTPAGESIZEPF0_M 0xfU
180 #define HOSTPAGESIZEPF0_V(x) ((x) << HOSTPAGESIZEPF0_S)
181 #define HOSTPAGESIZEPF0_G(x) (((x) >> HOSTPAGESIZEPF0_S) & HOSTPAGESIZEPF0_M)
183 #define SGE_EGRESS_QUEUES_PER_PAGE_PF_A 0x1010
184 #define SGE_EGRESS_QUEUES_PER_PAGE_VF_A 0x1014
186 #define QUEUESPERPAGEPF1_S 4
188 #define QUEUESPERPAGEPF0_S 0
189 #define QUEUESPERPAGEPF0_M 0xfU
190 #define QUEUESPERPAGEPF0_V(x) ((x) << QUEUESPERPAGEPF0_S)
191 #define QUEUESPERPAGEPF0_G(x) (((x) >> QUEUESPERPAGEPF0_S) & QUEUESPERPAGEPF0_M)
193 #define SGE_INT_CAUSE1_A 0x1024
194 #define SGE_INT_CAUSE2_A 0x1030
195 #define SGE_INT_CAUSE3_A 0x103c
197 #define ERR_FLM_DBP_S 31
198 #define ERR_FLM_DBP_V(x) ((x) << ERR_FLM_DBP_S)
199 #define ERR_FLM_DBP_F ERR_FLM_DBP_V(1U)
201 #define ERR_FLM_IDMA1_S 30
202 #define ERR_FLM_IDMA1_V(x) ((x) << ERR_FLM_IDMA1_S)
203 #define ERR_FLM_IDMA1_F ERR_FLM_IDMA1_V(1U)
205 #define ERR_FLM_IDMA0_S 29
206 #define ERR_FLM_IDMA0_V(x) ((x) << ERR_FLM_IDMA0_S)
207 #define ERR_FLM_IDMA0_F ERR_FLM_IDMA0_V(1U)
209 #define ERR_FLM_HINT_S 28
210 #define ERR_FLM_HINT_V(x) ((x) << ERR_FLM_HINT_S)
211 #define ERR_FLM_HINT_F ERR_FLM_HINT_V(1U)
213 #define ERR_PCIE_ERROR3_S 27
214 #define ERR_PCIE_ERROR3_V(x) ((x) << ERR_PCIE_ERROR3_S)
215 #define ERR_PCIE_ERROR3_F ERR_PCIE_ERROR3_V(1U)
217 #define ERR_PCIE_ERROR2_S 26
218 #define ERR_PCIE_ERROR2_V(x) ((x) << ERR_PCIE_ERROR2_S)
219 #define ERR_PCIE_ERROR2_F ERR_PCIE_ERROR2_V(1U)
221 #define ERR_PCIE_ERROR1_S 25
222 #define ERR_PCIE_ERROR1_V(x) ((x) << ERR_PCIE_ERROR1_S)
223 #define ERR_PCIE_ERROR1_F ERR_PCIE_ERROR1_V(1U)
225 #define ERR_PCIE_ERROR0_S 24
226 #define ERR_PCIE_ERROR0_V(x) ((x) << ERR_PCIE_ERROR0_S)
227 #define ERR_PCIE_ERROR0_F ERR_PCIE_ERROR0_V(1U)
229 #define ERR_CPL_EXCEED_IQE_SIZE_S 22
230 #define ERR_CPL_EXCEED_IQE_SIZE_V(x) ((x) << ERR_CPL_EXCEED_IQE_SIZE_S)
231 #define ERR_CPL_EXCEED_IQE_SIZE_F ERR_CPL_EXCEED_IQE_SIZE_V(1U)
233 #define ERR_INVALID_CIDX_INC_S 21
234 #define ERR_INVALID_CIDX_INC_V(x) ((x) << ERR_INVALID_CIDX_INC_S)
235 #define ERR_INVALID_CIDX_INC_F ERR_INVALID_CIDX_INC_V(1U)
237 #define ERR_CPL_OPCODE_0_S 19
238 #define ERR_CPL_OPCODE_0_V(x) ((x) << ERR_CPL_OPCODE_0_S)
239 #define ERR_CPL_OPCODE_0_F ERR_CPL_OPCODE_0_V(1U)
241 #define ERR_DROPPED_DB_S 18
242 #define ERR_DROPPED_DB_V(x) ((x) << ERR_DROPPED_DB_S)
243 #define ERR_DROPPED_DB_F ERR_DROPPED_DB_V(1U)
245 #define ERR_DATA_CPL_ON_HIGH_QID1_S 17
246 #define ERR_DATA_CPL_ON_HIGH_QID1_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID1_S)
247 #define ERR_DATA_CPL_ON_HIGH_QID1_F ERR_DATA_CPL_ON_HIGH_QID1_V(1U)
249 #define ERR_DATA_CPL_ON_HIGH_QID0_S 16
250 #define ERR_DATA_CPL_ON_HIGH_QID0_V(x) ((x) << ERR_DATA_CPL_ON_HIGH_QID0_S)
251 #define ERR_DATA_CPL_ON_HIGH_QID0_F ERR_DATA_CPL_ON_HIGH_QID0_V(1U)
253 #define ERR_BAD_DB_PIDX3_S 15
254 #define ERR_BAD_DB_PIDX3_V(x) ((x) << ERR_BAD_DB_PIDX3_S)
255 #define ERR_BAD_DB_PIDX3_F ERR_BAD_DB_PIDX3_V(1U)
257 #define ERR_BAD_DB_PIDX2_S 14
258 #define ERR_BAD_DB_PIDX2_V(x) ((x) << ERR_BAD_DB_PIDX2_S)
259 #define ERR_BAD_DB_PIDX2_F ERR_BAD_DB_PIDX2_V(1U)
261 #define ERR_BAD_DB_PIDX1_S 13
262 #define ERR_BAD_DB_PIDX1_V(x) ((x) << ERR_BAD_DB_PIDX1_S)
263 #define ERR_BAD_DB_PIDX1_F ERR_BAD_DB_PIDX1_V(1U)
265 #define ERR_BAD_DB_PIDX0_S 12
266 #define ERR_BAD_DB_PIDX0_V(x) ((x) << ERR_BAD_DB_PIDX0_S)
267 #define ERR_BAD_DB_PIDX0_F ERR_BAD_DB_PIDX0_V(1U)
269 #define ERR_ING_CTXT_PRIO_S 10
270 #define ERR_ING_CTXT_PRIO_V(x) ((x) << ERR_ING_CTXT_PRIO_S)
271 #define ERR_ING_CTXT_PRIO_F ERR_ING_CTXT_PRIO_V(1U)
273 #define ERR_EGR_CTXT_PRIO_S 9
274 #define ERR_EGR_CTXT_PRIO_V(x) ((x) << ERR_EGR_CTXT_PRIO_S)
275 #define ERR_EGR_CTXT_PRIO_F ERR_EGR_CTXT_PRIO_V(1U)
277 #define DBFIFO_HP_INT_S 8
278 #define DBFIFO_HP_INT_V(x) ((x) << DBFIFO_HP_INT_S)
279 #define DBFIFO_HP_INT_F DBFIFO_HP_INT_V(1U)
281 #define DBFIFO_LP_INT_S 7
282 #define DBFIFO_LP_INT_V(x) ((x) << DBFIFO_LP_INT_S)
283 #define DBFIFO_LP_INT_F DBFIFO_LP_INT_V(1U)
285 #define INGRESS_SIZE_ERR_S 5
286 #define INGRESS_SIZE_ERR_V(x) ((x) << INGRESS_SIZE_ERR_S)
287 #define INGRESS_SIZE_ERR_F INGRESS_SIZE_ERR_V(1U)
289 #define EGRESS_SIZE_ERR_S 4
290 #define EGRESS_SIZE_ERR_V(x) ((x) << EGRESS_SIZE_ERR_S)
291 #define EGRESS_SIZE_ERR_F EGRESS_SIZE_ERR_V(1U)
293 #define SGE_INT_ENABLE3_A 0x1040
294 #define SGE_FL_BUFFER_SIZE0_A 0x1044
295 #define SGE_FL_BUFFER_SIZE1_A 0x1048
296 #define SGE_FL_BUFFER_SIZE2_A 0x104c
297 #define SGE_FL_BUFFER_SIZE3_A 0x1050
298 #define SGE_FL_BUFFER_SIZE4_A 0x1054
299 #define SGE_FL_BUFFER_SIZE5_A 0x1058
300 #define SGE_FL_BUFFER_SIZE6_A 0x105c
301 #define SGE_FL_BUFFER_SIZE7_A 0x1060
302 #define SGE_FL_BUFFER_SIZE8_A 0x1064
304 #define SGE_INGRESS_RX_THRESHOLD_A 0x10a0
306 #define THRESHOLD_0_S 24
307 #define THRESHOLD_0_M 0x3fU
308 #define THRESHOLD_0_V(x) ((x) << THRESHOLD_0_S)
309 #define THRESHOLD_0_G(x) (((x) >> THRESHOLD_0_S) & THRESHOLD_0_M)
311 #define THRESHOLD_1_S 16
312 #define THRESHOLD_1_M 0x3fU
313 #define THRESHOLD_1_V(x) ((x) << THRESHOLD_1_S)
314 #define THRESHOLD_1_G(x) (((x) >> THRESHOLD_1_S) & THRESHOLD_1_M)
316 #define THRESHOLD_2_S 8
317 #define THRESHOLD_2_M 0x3fU
318 #define THRESHOLD_2_V(x) ((x) << THRESHOLD_2_S)
319 #define THRESHOLD_2_G(x) (((x) >> THRESHOLD_2_S) & THRESHOLD_2_M)
321 #define THRESHOLD_3_S 0
322 #define THRESHOLD_3_M 0x3fU
323 #define THRESHOLD_3_V(x) ((x) << THRESHOLD_3_S)
324 #define THRESHOLD_3_G(x) (((x) >> THRESHOLD_3_S) & THRESHOLD_3_M)
326 #define SGE_CONM_CTRL_A 0x1094
328 #define EGRTHRESHOLD_S 8
329 #define EGRTHRESHOLD_M 0x3fU
330 #define EGRTHRESHOLD_V(x) ((x) << EGRTHRESHOLD_S)
331 #define EGRTHRESHOLD_G(x) (((x) >> EGRTHRESHOLD_S) & EGRTHRESHOLD_M)
333 #define EGRTHRESHOLDPACKING_S 14
334 #define EGRTHRESHOLDPACKING_M 0x3fU
335 #define EGRTHRESHOLDPACKING_V(x) ((x) << EGRTHRESHOLDPACKING_S)
336 #define EGRTHRESHOLDPACKING_G(x) \
337 (((x) >> EGRTHRESHOLDPACKING_S) & EGRTHRESHOLDPACKING_M)
339 #define SGE_TIMESTAMP_LO_A 0x1098
340 #define SGE_TIMESTAMP_HI_A 0x109c
344 #define TSOP_V(x) ((x) << TSOP_S)
345 #define TSOP_G(x) (((x) >> TSOP_S) & TSOP_M)
348 #define TSVAL_M 0xfffffffU
349 #define TSVAL_V(x) ((x) << TSVAL_S)
350 #define TSVAL_G(x) (((x) >> TSVAL_S) & TSVAL_M)
352 #define SGE_DBFIFO_STATUS_A 0x10a4
354 #define HP_INT_THRESH_S 28
355 #define HP_INT_THRESH_M 0xfU
356 #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
358 #define LP_INT_THRESH_S 12
359 #define LP_INT_THRESH_M 0xfU
360 #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
362 #define SGE_DOORBELL_CONTROL_A 0x10a8
364 #define NOCOALESCE_S 26
365 #define NOCOALESCE_V(x) ((x) << NOCOALESCE_S)
366 #define NOCOALESCE_F NOCOALESCE_V(1U)
368 #define ENABLE_DROP_S 13
369 #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
370 #define ENABLE_DROP_F ENABLE_DROP_V(1U)
372 #define SGE_TIMER_VALUE_0_AND_1_A 0x10b8
374 #define TIMERVALUE0_S 16
375 #define TIMERVALUE0_M 0xffffU
376 #define TIMERVALUE0_V(x) ((x) << TIMERVALUE0_S)
377 #define TIMERVALUE0_G(x) (((x) >> TIMERVALUE0_S) & TIMERVALUE0_M)
379 #define TIMERVALUE1_S 0
380 #define TIMERVALUE1_M 0xffffU
381 #define TIMERVALUE1_V(x) ((x) << TIMERVALUE1_S)
382 #define TIMERVALUE1_G(x) (((x) >> TIMERVALUE1_S) & TIMERVALUE1_M)
384 #define SGE_TIMER_VALUE_2_AND_3_A 0x10bc
386 #define TIMERVALUE2_S 16
387 #define TIMERVALUE2_M 0xffffU
388 #define TIMERVALUE2_V(x) ((x) << TIMERVALUE2_S)
389 #define TIMERVALUE2_G(x) (((x) >> TIMERVALUE2_S) & TIMERVALUE2_M)
391 #define TIMERVALUE3_S 0
392 #define TIMERVALUE3_M 0xffffU
393 #define TIMERVALUE3_V(x) ((x) << TIMERVALUE3_S)
394 #define TIMERVALUE3_G(x) (((x) >> TIMERVALUE3_S) & TIMERVALUE3_M)
396 #define SGE_TIMER_VALUE_4_AND_5_A 0x10c0
398 #define TIMERVALUE4_S 16
399 #define TIMERVALUE4_M 0xffffU
400 #define TIMERVALUE4_V(x) ((x) << TIMERVALUE4_S)
401 #define TIMERVALUE4_G(x) (((x) >> TIMERVALUE4_S) & TIMERVALUE4_M)
403 #define TIMERVALUE5_S 0
404 #define TIMERVALUE5_M 0xffffU
405 #define TIMERVALUE5_V(x) ((x) << TIMERVALUE5_S)
406 #define TIMERVALUE5_G(x) (((x) >> TIMERVALUE5_S) & TIMERVALUE5_M)
408 #define SGE_DEBUG_INDEX_A 0x10cc
409 #define SGE_DEBUG_DATA_HIGH_A 0x10d0
410 #define SGE_DEBUG_DATA_LOW_A 0x10d4
412 #define SGE_DEBUG_DATA_LOW_INDEX_2_A 0x12c8
413 #define SGE_DEBUG_DATA_LOW_INDEX_3_A 0x12cc
414 #define SGE_DEBUG_DATA_HIGH_INDEX_10_A 0x12a8
416 #define SGE_INGRESS_QUEUES_PER_PAGE_PF_A 0x10f4
417 #define SGE_INGRESS_QUEUES_PER_PAGE_VF_A 0x10f8
419 #define HP_INT_THRESH_S 28
420 #define HP_INT_THRESH_M 0xfU
421 #define HP_INT_THRESH_V(x) ((x) << HP_INT_THRESH_S)
423 #define HP_COUNT_S 16
424 #define HP_COUNT_M 0x7ffU
425 #define HP_COUNT_G(x) (((x) >> HP_COUNT_S) & HP_COUNT_M)
427 #define LP_INT_THRESH_S 12
428 #define LP_INT_THRESH_M 0xfU
429 #define LP_INT_THRESH_V(x) ((x) << LP_INT_THRESH_S)
432 #define LP_COUNT_M 0x7ffU
433 #define LP_COUNT_G(x) (((x) >> LP_COUNT_S) & LP_COUNT_M)
435 #define LP_INT_THRESH_T5_S 18
436 #define LP_INT_THRESH_T5_M 0xfffU
437 #define LP_INT_THRESH_T5_V(x) ((x) << LP_INT_THRESH_T5_S)
439 #define LP_COUNT_T5_S 0
440 #define LP_COUNT_T5_M 0x3ffffU
441 #define LP_COUNT_T5_G(x) (((x) >> LP_COUNT_T5_S) & LP_COUNT_T5_M)
443 #define SGE_DOORBELL_CONTROL_A 0x10a8
445 #define SGE_STAT_TOTAL_A 0x10e4
446 #define SGE_STAT_MATCH_A 0x10e8
447 #define SGE_STAT_CFG_A 0x10ec
449 #define STATSOURCE_T5_S 9
450 #define STATSOURCE_T5_V(x) ((x) << STATSOURCE_T5_S)
452 #define SGE_DBFIFO_STATUS2_A 0x1118
454 #define HP_INT_THRESH_T5_S 10
455 #define HP_INT_THRESH_T5_M 0xfU
456 #define HP_INT_THRESH_T5_V(x) ((x) << HP_INT_THRESH_T5_S)
458 #define HP_COUNT_T5_S 0
459 #define HP_COUNT_T5_M 0x3ffU
460 #define HP_COUNT_T5_G(x) (((x) >> HP_COUNT_T5_S) & HP_COUNT_T5_M)
462 #define ENABLE_DROP_S 13
463 #define ENABLE_DROP_V(x) ((x) << ENABLE_DROP_S)
464 #define ENABLE_DROP_F ENABLE_DROP_V(1U)
466 #define DROPPED_DB_S 0
467 #define DROPPED_DB_V(x) ((x) << DROPPED_DB_S)
468 #define DROPPED_DB_F DROPPED_DB_V(1U)
470 #define SGE_CTXT_CMD_A 0x11fc
471 #define SGE_DBQ_CTXT_BADDR_A 0x1084
473 /* registers for module PCIE */
474 #define PCIE_PF_CFG_A 0x40
477 #define AIVEC_M 0x3ffU
478 #define AIVEC_V(x) ((x) << AIVEC_S)
480 #define PCIE_PF_CLI_A 0x44
481 #define PCIE_INT_CAUSE_A 0x3004
483 #define UNXSPLCPLERR_S 29
484 #define UNXSPLCPLERR_V(x) ((x) << UNXSPLCPLERR_S)
485 #define UNXSPLCPLERR_F UNXSPLCPLERR_V(1U)
487 #define PCIEPINT_S 28
488 #define PCIEPINT_V(x) ((x) << PCIEPINT_S)
489 #define PCIEPINT_F PCIEPINT_V(1U)
491 #define PCIESINT_S 27
492 #define PCIESINT_V(x) ((x) << PCIESINT_S)
493 #define PCIESINT_F PCIESINT_V(1U)
496 #define RPLPERR_V(x) ((x) << RPLPERR_S)
497 #define RPLPERR_F RPLPERR_V(1U)
499 #define RXWRPERR_S 25
500 #define RXWRPERR_V(x) ((x) << RXWRPERR_S)
501 #define RXWRPERR_F RXWRPERR_V(1U)
503 #define RXCPLPERR_S 24
504 #define RXCPLPERR_V(x) ((x) << RXCPLPERR_S)
505 #define RXCPLPERR_F RXCPLPERR_V(1U)
507 #define PIOTAGPERR_S 23
508 #define PIOTAGPERR_V(x) ((x) << PIOTAGPERR_S)
509 #define PIOTAGPERR_F PIOTAGPERR_V(1U)
511 #define MATAGPERR_S 22
512 #define MATAGPERR_V(x) ((x) << MATAGPERR_S)
513 #define MATAGPERR_F MATAGPERR_V(1U)
515 #define INTXCLRPERR_S 21
516 #define INTXCLRPERR_V(x) ((x) << INTXCLRPERR_S)
517 #define INTXCLRPERR_F INTXCLRPERR_V(1U)
520 #define FIDPERR_V(x) ((x) << FIDPERR_S)
521 #define FIDPERR_F FIDPERR_V(1U)
523 #define CFGSNPPERR_S 19
524 #define CFGSNPPERR_V(x) ((x) << CFGSNPPERR_S)
525 #define CFGSNPPERR_F CFGSNPPERR_V(1U)
527 #define HRSPPERR_S 18
528 #define HRSPPERR_V(x) ((x) << HRSPPERR_S)
529 #define HRSPPERR_F HRSPPERR_V(1U)
531 #define HREQPERR_S 17
532 #define HREQPERR_V(x) ((x) << HREQPERR_S)
533 #define HREQPERR_F HREQPERR_V(1U)
535 #define HCNTPERR_S 16
536 #define HCNTPERR_V(x) ((x) << HCNTPERR_S)
537 #define HCNTPERR_F HCNTPERR_V(1U)
539 #define DRSPPERR_S 15
540 #define DRSPPERR_V(x) ((x) << DRSPPERR_S)
541 #define DRSPPERR_F DRSPPERR_V(1U)
543 #define DREQPERR_S 14
544 #define DREQPERR_V(x) ((x) << DREQPERR_S)
545 #define DREQPERR_F DREQPERR_V(1U)
547 #define DCNTPERR_S 13
548 #define DCNTPERR_V(x) ((x) << DCNTPERR_S)
549 #define DCNTPERR_F DCNTPERR_V(1U)
551 #define CRSPPERR_S 12
552 #define CRSPPERR_V(x) ((x) << CRSPPERR_S)
553 #define CRSPPERR_F CRSPPERR_V(1U)
555 #define CREQPERR_S 11
556 #define CREQPERR_V(x) ((x) << CREQPERR_S)
557 #define CREQPERR_F CREQPERR_V(1U)
559 #define CCNTPERR_S 10
560 #define CCNTPERR_V(x) ((x) << CCNTPERR_S)
561 #define CCNTPERR_F CCNTPERR_V(1U)
563 #define TARTAGPERR_S 9
564 #define TARTAGPERR_V(x) ((x) << TARTAGPERR_S)
565 #define TARTAGPERR_F TARTAGPERR_V(1U)
567 #define PIOREQPERR_S 8
568 #define PIOREQPERR_V(x) ((x) << PIOREQPERR_S)
569 #define PIOREQPERR_F PIOREQPERR_V(1U)
571 #define PIOCPLPERR_S 7
572 #define PIOCPLPERR_V(x) ((x) << PIOCPLPERR_S)
573 #define PIOCPLPERR_F PIOCPLPERR_V(1U)
575 #define MSIXDIPERR_S 6
576 #define MSIXDIPERR_V(x) ((x) << MSIXDIPERR_S)
577 #define MSIXDIPERR_F MSIXDIPERR_V(1U)
579 #define MSIXDATAPERR_S 5
580 #define MSIXDATAPERR_V(x) ((x) << MSIXDATAPERR_S)
581 #define MSIXDATAPERR_F MSIXDATAPERR_V(1U)
583 #define MSIXADDRHPERR_S 4
584 #define MSIXADDRHPERR_V(x) ((x) << MSIXADDRHPERR_S)
585 #define MSIXADDRHPERR_F MSIXADDRHPERR_V(1U)
587 #define MSIXADDRLPERR_S 3
588 #define MSIXADDRLPERR_V(x) ((x) << MSIXADDRLPERR_S)
589 #define MSIXADDRLPERR_F MSIXADDRLPERR_V(1U)
591 #define MSIDATAPERR_S 2
592 #define MSIDATAPERR_V(x) ((x) << MSIDATAPERR_S)
593 #define MSIDATAPERR_F MSIDATAPERR_V(1U)
595 #define MSIADDRHPERR_S 1
596 #define MSIADDRHPERR_V(x) ((x) << MSIADDRHPERR_S)
597 #define MSIADDRHPERR_F MSIADDRHPERR_V(1U)
599 #define MSIADDRLPERR_S 0
600 #define MSIADDRLPERR_V(x) ((x) << MSIADDRLPERR_S)
601 #define MSIADDRLPERR_F MSIADDRLPERR_V(1U)
603 #define READRSPERR_S 29
604 #define READRSPERR_V(x) ((x) << READRSPERR_S)
605 #define READRSPERR_F READRSPERR_V(1U)
607 #define TRGT1GRPPERR_S 28
608 #define TRGT1GRPPERR_V(x) ((x) << TRGT1GRPPERR_S)
609 #define TRGT1GRPPERR_F TRGT1GRPPERR_V(1U)
611 #define IPSOTPERR_S 27
612 #define IPSOTPERR_V(x) ((x) << IPSOTPERR_S)
613 #define IPSOTPERR_F IPSOTPERR_V(1U)
615 #define IPRETRYPERR_S 26
616 #define IPRETRYPERR_V(x) ((x) << IPRETRYPERR_S)
617 #define IPRETRYPERR_F IPRETRYPERR_V(1U)
619 #define IPRXDATAGRPPERR_S 25
620 #define IPRXDATAGRPPERR_V(x) ((x) << IPRXDATAGRPPERR_S)
621 #define IPRXDATAGRPPERR_F IPRXDATAGRPPERR_V(1U)
623 #define IPRXHDRGRPPERR_S 24
624 #define IPRXHDRGRPPERR_V(x) ((x) << IPRXHDRGRPPERR_S)
625 #define IPRXHDRGRPPERR_F IPRXHDRGRPPERR_V(1U)
627 #define MAGRPPERR_S 22
628 #define MAGRPPERR_V(x) ((x) << MAGRPPERR_S)
629 #define MAGRPPERR_F MAGRPPERR_V(1U)
631 #define VFIDPERR_S 21
632 #define VFIDPERR_V(x) ((x) << VFIDPERR_S)
633 #define VFIDPERR_F VFIDPERR_V(1U)
635 #define HREQWRPERR_S 16
636 #define HREQWRPERR_V(x) ((x) << HREQWRPERR_S)
637 #define HREQWRPERR_F HREQWRPERR_V(1U)
639 #define DREQWRPERR_S 13
640 #define DREQWRPERR_V(x) ((x) << DREQWRPERR_S)
641 #define DREQWRPERR_F DREQWRPERR_V(1U)
643 #define CREQRDPERR_S 11
644 #define CREQRDPERR_V(x) ((x) << CREQRDPERR_S)
645 #define CREQRDPERR_F CREQRDPERR_V(1U)
647 #define MSTTAGQPERR_S 10
648 #define MSTTAGQPERR_V(x) ((x) << MSTTAGQPERR_S)
649 #define MSTTAGQPERR_F MSTTAGQPERR_V(1U)
651 #define PIOREQGRPPERR_S 8
652 #define PIOREQGRPPERR_V(x) ((x) << PIOREQGRPPERR_S)
653 #define PIOREQGRPPERR_F PIOREQGRPPERR_V(1U)
655 #define PIOCPLGRPPERR_S 7
656 #define PIOCPLGRPPERR_V(x) ((x) << PIOCPLGRPPERR_S)
657 #define PIOCPLGRPPERR_F PIOCPLGRPPERR_V(1U)
659 #define MSIXSTIPERR_S 2
660 #define MSIXSTIPERR_V(x) ((x) << MSIXSTIPERR_S)
661 #define MSIXSTIPERR_F MSIXSTIPERR_V(1U)
663 #define MSTTIMEOUTPERR_S 1
664 #define MSTTIMEOUTPERR_V(x) ((x) << MSTTIMEOUTPERR_S)
665 #define MSTTIMEOUTPERR_F MSTTIMEOUTPERR_V(1U)
667 #define MSTGRPPERR_S 0
668 #define MSTGRPPERR_V(x) ((x) << MSTGRPPERR_S)
669 #define MSTGRPPERR_F MSTGRPPERR_V(1U)
671 #define PCIE_NONFAT_ERR_A 0x3010
672 #define PCIE_CFG_SPACE_REQ_A 0x3060
673 #define PCIE_CFG_SPACE_DATA_A 0x3064
674 #define PCIE_MEM_ACCESS_BASE_WIN_A 0x3068
676 #define PCIEOFST_S 10
677 #define PCIEOFST_M 0x3fffffU
678 #define PCIEOFST_G(x) (((x) >> PCIEOFST_S) & PCIEOFST_M)
682 #define BIR_V(x) ((x) << BIR_S)
683 #define BIR_G(x) (((x) >> BIR_S) & BIR_M)
686 #define WINDOW_M 0xffU
687 #define WINDOW_V(x) ((x) << WINDOW_S)
688 #define WINDOW_G(x) (((x) >> WINDOW_S) & WINDOW_M)
690 #define PCIE_MEM_ACCESS_OFFSET_A 0x306c
693 #define ENABLE_V(x) ((x) << ENABLE_S)
694 #define ENABLE_F ENABLE_V(1U)
696 #define LOCALCFG_S 28
697 #define LOCALCFG_V(x) ((x) << LOCALCFG_S)
698 #define LOCALCFG_F LOCALCFG_V(1U)
700 #define FUNCTION_S 12
701 #define FUNCTION_V(x) ((x) << FUNCTION_S)
704 #define REGISTER_V(x) ((x) << REGISTER_S)
707 #define PFNUM_V(x) ((x) << PFNUM_S)
709 #define PCIE_FW_A 0x30b8
711 #define PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A 0x5908
714 #define RNPP_V(x) ((x) << RNPP_S)
715 #define RNPP_F RNPP_V(1U)
718 #define RPCP_V(x) ((x) << RPCP_S)
719 #define RPCP_F RPCP_V(1U)
722 #define RCIP_V(x) ((x) << RCIP_S)
723 #define RCIP_F RCIP_V(1U)
726 #define RCCP_V(x) ((x) << RCCP_S)
727 #define RCCP_F RCCP_V(1U)
730 #define RFTP_V(x) ((x) << RFTP_S)
731 #define RFTP_F RFTP_V(1U)
734 #define PTRP_V(x) ((x) << PTRP_S)
735 #define PTRP_F PTRP_V(1U)
737 #define PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A 0x59a4
740 #define TPCP_V(x) ((x) << TPCP_S)
741 #define TPCP_F TPCP_V(1U)
744 #define TNPP_V(x) ((x) << TNPP_S)
745 #define TNPP_F TNPP_V(1U)
748 #define TFTP_V(x) ((x) << TFTP_S)
749 #define TFTP_F TFTP_V(1U)
752 #define TCAP_V(x) ((x) << TCAP_S)
753 #define TCAP_F TCAP_V(1U)
756 #define TCIP_V(x) ((x) << TCIP_S)
757 #define TCIP_F TCIP_V(1U)
760 #define RCAP_V(x) ((x) << RCAP_S)
761 #define RCAP_F RCAP_V(1U)
764 #define PLUP_V(x) ((x) << PLUP_S)
765 #define PLUP_F PLUP_V(1U)
768 #define PLDN_V(x) ((x) << PLDN_S)
769 #define PLDN_F PLDN_V(1U)
772 #define OTDD_V(x) ((x) << OTDD_S)
773 #define OTDD_F OTDD_V(1U)
776 #define GTRP_V(x) ((x) << GTRP_S)
777 #define GTRP_F GTRP_V(1U)
780 #define RDPE_V(x) ((x) << RDPE_S)
781 #define RDPE_F RDPE_V(1U)
784 #define TDCE_V(x) ((x) << TDCE_S)
785 #define TDCE_F TDCE_V(1U)
788 #define TDUE_V(x) ((x) << TDUE_S)
789 #define TDUE_F TDUE_V(1U)
791 /* registers for module MC */
792 #define MC_INT_CAUSE_A 0x7518
793 #define MC_P_INT_CAUSE_A 0x41318
795 #define ECC_UE_INT_CAUSE_S 2
796 #define ECC_UE_INT_CAUSE_V(x) ((x) << ECC_UE_INT_CAUSE_S)
797 #define ECC_UE_INT_CAUSE_F ECC_UE_INT_CAUSE_V(1U)
799 #define ECC_CE_INT_CAUSE_S 1
800 #define ECC_CE_INT_CAUSE_V(x) ((x) << ECC_CE_INT_CAUSE_S)
801 #define ECC_CE_INT_CAUSE_F ECC_CE_INT_CAUSE_V(1U)
803 #define PERR_INT_CAUSE_S 0
804 #define PERR_INT_CAUSE_V(x) ((x) << PERR_INT_CAUSE_S)
805 #define PERR_INT_CAUSE_F PERR_INT_CAUSE_V(1U)
807 #define MC_ECC_STATUS_A 0x751c
808 #define MC_P_ECC_STATUS_A 0x4131c
810 #define ECC_CECNT_S 16
811 #define ECC_CECNT_M 0xffffU
812 #define ECC_CECNT_V(x) ((x) << ECC_CECNT_S)
813 #define ECC_CECNT_G(x) (((x) >> ECC_CECNT_S) & ECC_CECNT_M)
815 #define ECC_UECNT_S 0
816 #define ECC_UECNT_M 0xffffU
817 #define ECC_UECNT_V(x) ((x) << ECC_UECNT_S)
818 #define ECC_UECNT_G(x) (((x) >> ECC_UECNT_S) & ECC_UECNT_M)
820 #define MC_BIST_CMD_A 0x7600
822 #define START_BIST_S 31
823 #define START_BIST_V(x) ((x) << START_BIST_S)
824 #define START_BIST_F START_BIST_V(1U)
826 #define BIST_CMD_GAP_S 8
827 #define BIST_CMD_GAP_V(x) ((x) << BIST_CMD_GAP_S)
829 #define BIST_OPCODE_S 0
830 #define BIST_OPCODE_V(x) ((x) << BIST_OPCODE_S)
832 #define MC_BIST_CMD_ADDR_A 0x7604
833 #define MC_BIST_CMD_LEN_A 0x7608
834 #define MC_BIST_DATA_PATTERN_A 0x760c
836 #define MC_BIST_STATUS_RDATA_A 0x7688
838 /* registers for module MA */
839 #define MA_EDRAM0_BAR_A 0x77c0
841 #define EDRAM0_SIZE_S 0
842 #define EDRAM0_SIZE_M 0xfffU
843 #define EDRAM0_SIZE_V(x) ((x) << EDRAM0_SIZE_S)
844 #define EDRAM0_SIZE_G(x) (((x) >> EDRAM0_SIZE_S) & EDRAM0_SIZE_M)
846 #define MA_EDRAM1_BAR_A 0x77c4
848 #define EDRAM1_SIZE_S 0
849 #define EDRAM1_SIZE_M 0xfffU
850 #define EDRAM1_SIZE_V(x) ((x) << EDRAM1_SIZE_S)
851 #define EDRAM1_SIZE_G(x) (((x) >> EDRAM1_SIZE_S) & EDRAM1_SIZE_M)
853 #define MA_EXT_MEMORY_BAR_A 0x77c8
855 #define EXT_MEM_SIZE_S 0
856 #define EXT_MEM_SIZE_M 0xfffU
857 #define EXT_MEM_SIZE_V(x) ((x) << EXT_MEM_SIZE_S)
858 #define EXT_MEM_SIZE_G(x) (((x) >> EXT_MEM_SIZE_S) & EXT_MEM_SIZE_M)
860 #define MA_EXT_MEMORY1_BAR_A 0x7808
862 #define EXT_MEM1_SIZE_S 0
863 #define EXT_MEM1_SIZE_M 0xfffU
864 #define EXT_MEM1_SIZE_V(x) ((x) << EXT_MEM1_SIZE_S)
865 #define EXT_MEM1_SIZE_G(x) (((x) >> EXT_MEM1_SIZE_S) & EXT_MEM1_SIZE_M)
867 #define MA_EXT_MEMORY0_BAR_A 0x77c8
869 #define EXT_MEM0_SIZE_S 0
870 #define EXT_MEM0_SIZE_M 0xfffU
871 #define EXT_MEM0_SIZE_V(x) ((x) << EXT_MEM0_SIZE_S)
872 #define EXT_MEM0_SIZE_G(x) (((x) >> EXT_MEM0_SIZE_S) & EXT_MEM0_SIZE_M)
874 #define MA_TARGET_MEM_ENABLE_A 0x77d8
876 #define EXT_MEM_ENABLE_S 2
877 #define EXT_MEM_ENABLE_V(x) ((x) << EXT_MEM_ENABLE_S)
878 #define EXT_MEM_ENABLE_F EXT_MEM_ENABLE_V(1U)
880 #define EDRAM1_ENABLE_S 1
881 #define EDRAM1_ENABLE_V(x) ((x) << EDRAM1_ENABLE_S)
882 #define EDRAM1_ENABLE_F EDRAM1_ENABLE_V(1U)
884 #define EDRAM0_ENABLE_S 0
885 #define EDRAM0_ENABLE_V(x) ((x) << EDRAM0_ENABLE_S)
886 #define EDRAM0_ENABLE_F EDRAM0_ENABLE_V(1U)
888 #define EXT_MEM1_ENABLE_S 4
889 #define EXT_MEM1_ENABLE_V(x) ((x) << EXT_MEM1_ENABLE_S)
890 #define EXT_MEM1_ENABLE_F EXT_MEM1_ENABLE_V(1U)
892 #define EXT_MEM0_ENABLE_S 2
893 #define EXT_MEM0_ENABLE_V(x) ((x) << EXT_MEM0_ENABLE_S)
894 #define EXT_MEM0_ENABLE_F EXT_MEM0_ENABLE_V(1U)
896 #define MA_INT_CAUSE_A 0x77e0
898 #define MEM_PERR_INT_CAUSE_S 1
899 #define MEM_PERR_INT_CAUSE_V(x) ((x) << MEM_PERR_INT_CAUSE_S)
900 #define MEM_PERR_INT_CAUSE_F MEM_PERR_INT_CAUSE_V(1U)
902 #define MEM_WRAP_INT_CAUSE_S 0
903 #define MEM_WRAP_INT_CAUSE_V(x) ((x) << MEM_WRAP_INT_CAUSE_S)
904 #define MEM_WRAP_INT_CAUSE_F MEM_WRAP_INT_CAUSE_V(1U)
906 #define MA_INT_WRAP_STATUS_A 0x77e4
908 #define MEM_WRAP_ADDRESS_S 4
909 #define MEM_WRAP_ADDRESS_M 0xfffffffU
910 #define MEM_WRAP_ADDRESS_G(x) (((x) >> MEM_WRAP_ADDRESS_S) & MEM_WRAP_ADDRESS_M)
912 #define MEM_WRAP_CLIENT_NUM_S 0
913 #define MEM_WRAP_CLIENT_NUM_M 0xfU
914 #define MEM_WRAP_CLIENT_NUM_G(x) \
915 (((x) >> MEM_WRAP_CLIENT_NUM_S) & MEM_WRAP_CLIENT_NUM_M)
917 #define MA_PARITY_ERROR_STATUS_A 0x77f4
918 #define MA_PARITY_ERROR_STATUS1_A 0x77f4
919 #define MA_PARITY_ERROR_STATUS2_A 0x7804
921 /* registers for module EDC_0 */
922 #define EDC_0_BASE_ADDR 0x7900
924 #define EDC_BIST_CMD_A 0x7904
925 #define EDC_BIST_CMD_ADDR_A 0x7908
926 #define EDC_BIST_CMD_LEN_A 0x790c
927 #define EDC_BIST_DATA_PATTERN_A 0x7910
928 #define EDC_BIST_STATUS_RDATA_A 0x7928
929 #define EDC_INT_CAUSE_A 0x7978
931 #define ECC_UE_PAR_S 5
932 #define ECC_UE_PAR_V(x) ((x) << ECC_UE_PAR_S)
933 #define ECC_UE_PAR_F ECC_UE_PAR_V(1U)
935 #define ECC_CE_PAR_S 4
936 #define ECC_CE_PAR_V(x) ((x) << ECC_CE_PAR_S)
937 #define ECC_CE_PAR_F ECC_CE_PAR_V(1U)
939 #define PERR_PAR_CAUSE_S 3
940 #define PERR_PAR_CAUSE_V(x) ((x) << PERR_PAR_CAUSE_S)
941 #define PERR_PAR_CAUSE_F PERR_PAR_CAUSE_V(1U)
943 #define EDC_ECC_STATUS_A 0x797c
945 /* registers for module EDC_1 */
946 #define EDC_1_BASE_ADDR 0x7980
948 /* registers for module CIM */
949 #define CIM_BOOT_CFG_A 0x7b00
950 #define CIM_PF_MAILBOX_CTRL_SHADOW_COPY_A 0x290
952 #define BOOTADDR_M 0xffffff00U
955 #define UPCRST_V(x) ((x) << UPCRST_S)
956 #define UPCRST_F UPCRST_V(1U)
958 #define CIM_PF_MAILBOX_DATA_A 0x240
959 #define CIM_PF_MAILBOX_CTRL_A 0x280
961 #define MBMSGVALID_S 3
962 #define MBMSGVALID_V(x) ((x) << MBMSGVALID_S)
963 #define MBMSGVALID_F MBMSGVALID_V(1U)
966 #define MBINTREQ_V(x) ((x) << MBINTREQ_S)
967 #define MBINTREQ_F MBINTREQ_V(1U)
970 #define MBOWNER_M 0x3U
971 #define MBOWNER_V(x) ((x) << MBOWNER_S)
972 #define MBOWNER_G(x) (((x) >> MBOWNER_S) & MBOWNER_M)
974 #define CIM_PF_HOST_INT_ENABLE_A 0x288
976 #define MBMSGRDYINTEN_S 19
977 #define MBMSGRDYINTEN_V(x) ((x) << MBMSGRDYINTEN_S)
978 #define MBMSGRDYINTEN_F MBMSGRDYINTEN_V(1U)
980 #define CIM_PF_HOST_INT_CAUSE_A 0x28c
982 #define MBMSGRDYINT_S 19
983 #define MBMSGRDYINT_V(x) ((x) << MBMSGRDYINT_S)
984 #define MBMSGRDYINT_F MBMSGRDYINT_V(1U)
986 #define CIM_HOST_INT_CAUSE_A 0x7b2c
988 #define TIEQOUTPARERRINT_S 20
989 #define TIEQOUTPARERRINT_V(x) ((x) << TIEQOUTPARERRINT_S)
990 #define TIEQOUTPARERRINT_F TIEQOUTPARERRINT_V(1U)
992 #define TIEQINPARERRINT_S 19
993 #define TIEQINPARERRINT_V(x) ((x) << TIEQINPARERRINT_S)
994 #define TIEQINPARERRINT_F TIEQINPARERRINT_V(1U)
996 #define PREFDROPINT_S 1
997 #define PREFDROPINT_V(x) ((x) << PREFDROPINT_S)
998 #define PREFDROPINT_F PREFDROPINT_V(1U)
1000 #define UPACCNONZERO_S 0
1001 #define UPACCNONZERO_V(x) ((x) << UPACCNONZERO_S)
1002 #define UPACCNONZERO_F UPACCNONZERO_V(1U)
1004 #define MBHOSTPARERR_S 18
1005 #define MBHOSTPARERR_V(x) ((x) << MBHOSTPARERR_S)
1006 #define MBHOSTPARERR_F MBHOSTPARERR_V(1U)
1008 #define MBUPPARERR_S 17
1009 #define MBUPPARERR_V(x) ((x) << MBUPPARERR_S)
1010 #define MBUPPARERR_F MBUPPARERR_V(1U)
1012 #define IBQTP0PARERR_S 16
1013 #define IBQTP0PARERR_V(x) ((x) << IBQTP0PARERR_S)
1014 #define IBQTP0PARERR_F IBQTP0PARERR_V(1U)
1016 #define IBQTP1PARERR_S 15
1017 #define IBQTP1PARERR_V(x) ((x) << IBQTP1PARERR_S)
1018 #define IBQTP1PARERR_F IBQTP1PARERR_V(1U)
1020 #define IBQULPPARERR_S 14
1021 #define IBQULPPARERR_V(x) ((x) << IBQULPPARERR_S)
1022 #define IBQULPPARERR_F IBQULPPARERR_V(1U)
1024 #define IBQSGELOPARERR_S 13
1025 #define IBQSGELOPARERR_V(x) ((x) << IBQSGELOPARERR_S)
1026 #define IBQSGELOPARERR_F IBQSGELOPARERR_V(1U)
1028 #define IBQSGEHIPARERR_S 12
1029 #define IBQSGEHIPARERR_V(x) ((x) << IBQSGEHIPARERR_S)
1030 #define IBQSGEHIPARERR_F IBQSGEHIPARERR_V(1U)
1032 #define IBQNCSIPARERR_S 11
1033 #define IBQNCSIPARERR_V(x) ((x) << IBQNCSIPARERR_S)
1034 #define IBQNCSIPARERR_F IBQNCSIPARERR_V(1U)
1036 #define OBQULP0PARERR_S 10
1037 #define OBQULP0PARERR_V(x) ((x) << OBQULP0PARERR_S)
1038 #define OBQULP0PARERR_F OBQULP0PARERR_V(1U)
1040 #define OBQULP1PARERR_S 9
1041 #define OBQULP1PARERR_V(x) ((x) << OBQULP1PARERR_S)
1042 #define OBQULP1PARERR_F OBQULP1PARERR_V(1U)
1044 #define OBQULP2PARERR_S 8
1045 #define OBQULP2PARERR_V(x) ((x) << OBQULP2PARERR_S)
1046 #define OBQULP2PARERR_F OBQULP2PARERR_V(1U)
1048 #define OBQULP3PARERR_S 7
1049 #define OBQULP3PARERR_V(x) ((x) << OBQULP3PARERR_S)
1050 #define OBQULP3PARERR_F OBQULP3PARERR_V(1U)
1052 #define OBQSGEPARERR_S 6
1053 #define OBQSGEPARERR_V(x) ((x) << OBQSGEPARERR_S)
1054 #define OBQSGEPARERR_F OBQSGEPARERR_V(1U)
1056 #define OBQNCSIPARERR_S 5
1057 #define OBQNCSIPARERR_V(x) ((x) << OBQNCSIPARERR_S)
1058 #define OBQNCSIPARERR_F OBQNCSIPARERR_V(1U)
1060 #define CIM_HOST_UPACC_INT_CAUSE_A 0x7b34
1062 #define EEPROMWRINT_S 30
1063 #define EEPROMWRINT_V(x) ((x) << EEPROMWRINT_S)
1064 #define EEPROMWRINT_F EEPROMWRINT_V(1U)
1066 #define TIMEOUTMAINT_S 29
1067 #define TIMEOUTMAINT_V(x) ((x) << TIMEOUTMAINT_S)
1068 #define TIMEOUTMAINT_F TIMEOUTMAINT_V(1U)
1070 #define TIMEOUTINT_S 28
1071 #define TIMEOUTINT_V(x) ((x) << TIMEOUTINT_S)
1072 #define TIMEOUTINT_F TIMEOUTINT_V(1U)
1074 #define RSPOVRLOOKUPINT_S 27
1075 #define RSPOVRLOOKUPINT_V(x) ((x) << RSPOVRLOOKUPINT_S)
1076 #define RSPOVRLOOKUPINT_F RSPOVRLOOKUPINT_V(1U)
1078 #define REQOVRLOOKUPINT_S 26
1079 #define REQOVRLOOKUPINT_V(x) ((x) << REQOVRLOOKUPINT_S)
1080 #define REQOVRLOOKUPINT_F REQOVRLOOKUPINT_V(1U)
1082 #define BLKWRPLINT_S 25
1083 #define BLKWRPLINT_V(x) ((x) << BLKWRPLINT_S)
1084 #define BLKWRPLINT_F BLKWRPLINT_V(1U)
1086 #define BLKRDPLINT_S 24
1087 #define BLKRDPLINT_V(x) ((x) << BLKRDPLINT_S)
1088 #define BLKRDPLINT_F BLKRDPLINT_V(1U)
1090 #define SGLWRPLINT_S 23
1091 #define SGLWRPLINT_V(x) ((x) << SGLWRPLINT_S)
1092 #define SGLWRPLINT_F SGLWRPLINT_V(1U)
1094 #define SGLRDPLINT_S 22
1095 #define SGLRDPLINT_V(x) ((x) << SGLRDPLINT_S)
1096 #define SGLRDPLINT_F SGLRDPLINT_V(1U)
1098 #define BLKWRCTLINT_S 21
1099 #define BLKWRCTLINT_V(x) ((x) << BLKWRCTLINT_S)
1100 #define BLKWRCTLINT_F BLKWRCTLINT_V(1U)
1102 #define BLKRDCTLINT_S 20
1103 #define BLKRDCTLINT_V(x) ((x) << BLKRDCTLINT_S)
1104 #define BLKRDCTLINT_F BLKRDCTLINT_V(1U)
1106 #define SGLWRCTLINT_S 19
1107 #define SGLWRCTLINT_V(x) ((x) << SGLWRCTLINT_S)
1108 #define SGLWRCTLINT_F SGLWRCTLINT_V(1U)
1110 #define SGLRDCTLINT_S 18
1111 #define SGLRDCTLINT_V(x) ((x) << SGLRDCTLINT_S)
1112 #define SGLRDCTLINT_F SGLRDCTLINT_V(1U)
1114 #define BLKWREEPROMINT_S 17
1115 #define BLKWREEPROMINT_V(x) ((x) << BLKWREEPROMINT_S)
1116 #define BLKWREEPROMINT_F BLKWREEPROMINT_V(1U)
1118 #define BLKRDEEPROMINT_S 16
1119 #define BLKRDEEPROMINT_V(x) ((x) << BLKRDEEPROMINT_S)
1120 #define BLKRDEEPROMINT_F BLKRDEEPROMINT_V(1U)
1122 #define SGLWREEPROMINT_S 15
1123 #define SGLWREEPROMINT_V(x) ((x) << SGLWREEPROMINT_S)
1124 #define SGLWREEPROMINT_F SGLWREEPROMINT_V(1U)
1126 #define SGLRDEEPROMINT_S 14
1127 #define SGLRDEEPROMINT_V(x) ((x) << SGLRDEEPROMINT_S)
1128 #define SGLRDEEPROMINT_F SGLRDEEPROMINT_V(1U)
1130 #define BLKWRFLASHINT_S 13
1131 #define BLKWRFLASHINT_V(x) ((x) << BLKWRFLASHINT_S)
1132 #define BLKWRFLASHINT_F BLKWRFLASHINT_V(1U)
1134 #define BLKRDFLASHINT_S 12
1135 #define BLKRDFLASHINT_V(x) ((x) << BLKRDFLASHINT_S)
1136 #define BLKRDFLASHINT_F BLKRDFLASHINT_V(1U)
1138 #define SGLWRFLASHINT_S 11
1139 #define SGLWRFLASHINT_V(x) ((x) << SGLWRFLASHINT_S)
1140 #define SGLWRFLASHINT_F SGLWRFLASHINT_V(1U)
1142 #define SGLRDFLASHINT_S 10
1143 #define SGLRDFLASHINT_V(x) ((x) << SGLRDFLASHINT_S)
1144 #define SGLRDFLASHINT_F SGLRDFLASHINT_V(1U)
1146 #define BLKWRBOOTINT_S 9
1147 #define BLKWRBOOTINT_V(x) ((x) << BLKWRBOOTINT_S)
1148 #define BLKWRBOOTINT_F BLKWRBOOTINT_V(1U)
1150 #define BLKRDBOOTINT_S 8
1151 #define BLKRDBOOTINT_V(x) ((x) << BLKRDBOOTINT_S)
1152 #define BLKRDBOOTINT_F BLKRDBOOTINT_V(1U)
1154 #define SGLWRBOOTINT_S 7
1155 #define SGLWRBOOTINT_V(x) ((x) << SGLWRBOOTINT_S)
1156 #define SGLWRBOOTINT_F SGLWRBOOTINT_V(1U)
1158 #define SGLRDBOOTINT_S 6
1159 #define SGLRDBOOTINT_V(x) ((x) << SGLRDBOOTINT_S)
1160 #define SGLRDBOOTINT_F SGLRDBOOTINT_V(1U)
1162 #define ILLWRBEINT_S 5
1163 #define ILLWRBEINT_V(x) ((x) << ILLWRBEINT_S)
1164 #define ILLWRBEINT_F ILLWRBEINT_V(1U)
1166 #define ILLRDBEINT_S 4
1167 #define ILLRDBEINT_V(x) ((x) << ILLRDBEINT_S)
1168 #define ILLRDBEINT_F ILLRDBEINT_V(1U)
1170 #define ILLRDINT_S 3
1171 #define ILLRDINT_V(x) ((x) << ILLRDINT_S)
1172 #define ILLRDINT_F ILLRDINT_V(1U)
1174 #define ILLWRINT_S 2
1175 #define ILLWRINT_V(x) ((x) << ILLWRINT_S)
1176 #define ILLWRINT_F ILLWRINT_V(1U)
1178 #define ILLTRANSINT_S 1
1179 #define ILLTRANSINT_V(x) ((x) << ILLTRANSINT_S)
1180 #define ILLTRANSINT_F ILLTRANSINT_V(1U)
1182 #define RSVDSPACEINT_S 0
1183 #define RSVDSPACEINT_V(x) ((x) << RSVDSPACEINT_S)
1184 #define RSVDSPACEINT_F RSVDSPACEINT_V(1U)
1186 /* registers for module TP */
1187 #define DBGLAWHLF_S 23
1188 #define DBGLAWHLF_V(x) ((x) << DBGLAWHLF_S)
1189 #define DBGLAWHLF_F DBGLAWHLF_V(1U)
1191 #define DBGLAWPTR_S 16
1192 #define DBGLAWPTR_M 0x7fU
1193 #define DBGLAWPTR_G(x) (((x) >> DBGLAWPTR_S) & DBGLAWPTR_M)
1195 #define DBGLAENABLE_S 12
1196 #define DBGLAENABLE_V(x) ((x) << DBGLAENABLE_S)
1197 #define DBGLAENABLE_F DBGLAENABLE_V(1U)
1199 #define DBGLARPTR_S 0
1200 #define DBGLARPTR_M 0x7fU
1201 #define DBGLARPTR_V(x) ((x) << DBGLARPTR_S)
1203 #define TP_DBG_LA_DATAL_A 0x7ed8
1204 #define TP_DBG_LA_CONFIG_A 0x7ed4
1205 #define TP_OUT_CONFIG_A 0x7d04
1206 #define TP_GLOBAL_CONFIG_A 0x7d08
1208 #define DBGLAMODE_S 14
1209 #define DBGLAMODE_M 0x3U
1210 #define DBGLAMODE_G(x) (((x) >> DBGLAMODE_S) & DBGLAMODE_M)
1212 #define FIVETUPLELOOKUP_S 17
1213 #define FIVETUPLELOOKUP_M 0x3U
1214 #define FIVETUPLELOOKUP_V(x) ((x) << FIVETUPLELOOKUP_S)
1215 #define FIVETUPLELOOKUP_G(x) (((x) >> FIVETUPLELOOKUP_S) & FIVETUPLELOOKUP_M)
1217 #define TP_PARA_REG2_A 0x7d68
1219 #define MAXRXDATA_S 16
1220 #define MAXRXDATA_M 0xffffU
1221 #define MAXRXDATA_G(x) (((x) >> MAXRXDATA_S) & MAXRXDATA_M)
1223 #define TP_TIMER_RESOLUTION_A 0x7d90
1225 #define TIMERRESOLUTION_S 16
1226 #define TIMERRESOLUTION_M 0xffU
1227 #define TIMERRESOLUTION_G(x) (((x) >> TIMERRESOLUTION_S) & TIMERRESOLUTION_M)
1229 #define TIMESTAMPRESOLUTION_S 8
1230 #define TIMESTAMPRESOLUTION_M 0xffU
1231 #define TIMESTAMPRESOLUTION_G(x) \
1232 (((x) >> TIMESTAMPRESOLUTION_S) & TIMESTAMPRESOLUTION_M)
1234 #define DELAYEDACKRESOLUTION_S 0
1235 #define DELAYEDACKRESOLUTION_M 0xffU
1236 #define DELAYEDACKRESOLUTION_G(x) \
1237 (((x) >> DELAYEDACKRESOLUTION_S) & DELAYEDACKRESOLUTION_M)
1239 #define TP_SHIFT_CNT_A 0x7dc0
1240 #define TP_RXT_MIN_A 0x7d98
1241 #define TP_RXT_MAX_A 0x7d9c
1242 #define TP_PERS_MIN_A 0x7da0
1243 #define TP_PERS_MAX_A 0x7da4
1244 #define TP_KEEP_IDLE_A 0x7da8
1245 #define TP_KEEP_INTVL_A 0x7dac
1246 #define TP_INIT_SRTT_A 0x7db0
1247 #define TP_DACK_TIMER_A 0x7db4
1248 #define TP_FINWAIT2_TIMER_A 0x7db8
1250 #define INITSRTT_S 0
1251 #define INITSRTT_M 0xffffU
1252 #define INITSRTT_G(x) (((x) >> INITSRTT_S) & INITSRTT_M)
1255 #define PERSMAX_M 0x3fffffffU
1256 #define PERSMAX_V(x) ((x) << PERSMAX_S)
1257 #define PERSMAX_G(x) (((x) >> PERSMAX_S) & PERSMAX_M)
1259 #define SYNSHIFTMAX_S 24
1260 #define SYNSHIFTMAX_M 0xffU
1261 #define SYNSHIFTMAX_V(x) ((x) << SYNSHIFTMAX_S)
1262 #define SYNSHIFTMAX_G(x) (((x) >> SYNSHIFTMAX_S) & SYNSHIFTMAX_M)
1264 #define RXTSHIFTMAXR1_S 20
1265 #define RXTSHIFTMAXR1_M 0xfU
1266 #define RXTSHIFTMAXR1_V(x) ((x) << RXTSHIFTMAXR1_S)
1267 #define RXTSHIFTMAXR1_G(x) (((x) >> RXTSHIFTMAXR1_S) & RXTSHIFTMAXR1_M)
1269 #define RXTSHIFTMAXR2_S 16
1270 #define RXTSHIFTMAXR2_M 0xfU
1271 #define RXTSHIFTMAXR2_V(x) ((x) << RXTSHIFTMAXR2_S)
1272 #define RXTSHIFTMAXR2_G(x) (((x) >> RXTSHIFTMAXR2_S) & RXTSHIFTMAXR2_M)
1274 #define PERSHIFTBACKOFFMAX_S 12
1275 #define PERSHIFTBACKOFFMAX_M 0xfU
1276 #define PERSHIFTBACKOFFMAX_V(x) ((x) << PERSHIFTBACKOFFMAX_S)
1277 #define PERSHIFTBACKOFFMAX_G(x) \
1278 (((x) >> PERSHIFTBACKOFFMAX_S) & PERSHIFTBACKOFFMAX_M)
1280 #define PERSHIFTMAX_S 8
1281 #define PERSHIFTMAX_M 0xfU
1282 #define PERSHIFTMAX_V(x) ((x) << PERSHIFTMAX_S)
1283 #define PERSHIFTMAX_G(x) (((x) >> PERSHIFTMAX_S) & PERSHIFTMAX_M)
1285 #define KEEPALIVEMAXR1_S 4
1286 #define KEEPALIVEMAXR1_M 0xfU
1287 #define KEEPALIVEMAXR1_V(x) ((x) << KEEPALIVEMAXR1_S)
1288 #define KEEPALIVEMAXR1_G(x) (((x) >> KEEPALIVEMAXR1_S) & KEEPALIVEMAXR1_M)
1290 #define KEEPALIVEMAXR2_S 0
1291 #define KEEPALIVEMAXR2_M 0xfU
1292 #define KEEPALIVEMAXR2_V(x) ((x) << KEEPALIVEMAXR2_S)
1293 #define KEEPALIVEMAXR2_G(x) (((x) >> KEEPALIVEMAXR2_S) & KEEPALIVEMAXR2_M)
1295 #define ROWINDEX_S 16
1296 #define ROWINDEX_V(x) ((x) << ROWINDEX_S)
1298 #define TP_CCTRL_TABLE_A 0x7ddc
1299 #define TP_MTU_TABLE_A 0x7de4
1301 #define MTUINDEX_S 24
1302 #define MTUINDEX_V(x) ((x) << MTUINDEX_S)
1304 #define MTUWIDTH_S 16
1305 #define MTUWIDTH_M 0xfU
1306 #define MTUWIDTH_V(x) ((x) << MTUWIDTH_S)
1307 #define MTUWIDTH_G(x) (((x) >> MTUWIDTH_S) & MTUWIDTH_M)
1309 #define MTUVALUE_S 0
1310 #define MTUVALUE_M 0x3fffU
1311 #define MTUVALUE_V(x) ((x) << MTUVALUE_S)
1312 #define MTUVALUE_G(x) (((x) >> MTUVALUE_S) & MTUVALUE_M)
1314 #define TP_RSS_LKP_TABLE_A 0x7dec
1316 #define LKPTBLROWVLD_S 31
1317 #define LKPTBLROWVLD_V(x) ((x) << LKPTBLROWVLD_S)
1318 #define LKPTBLROWVLD_F LKPTBLROWVLD_V(1U)
1320 #define LKPTBLQUEUE1_S 10
1321 #define LKPTBLQUEUE1_M 0x3ffU
1322 #define LKPTBLQUEUE1_G(x) (((x) >> LKPTBLQUEUE1_S) & LKPTBLQUEUE1_M)
1324 #define LKPTBLQUEUE0_S 0
1325 #define LKPTBLQUEUE0_M 0x3ffU
1326 #define LKPTBLQUEUE0_G(x) (((x) >> LKPTBLQUEUE0_S) & LKPTBLQUEUE0_M)
1328 #define TP_PIO_ADDR_A 0x7e40
1329 #define TP_PIO_DATA_A 0x7e44
1330 #define TP_MIB_INDEX_A 0x7e50
1331 #define TP_MIB_DATA_A 0x7e54
1332 #define TP_INT_CAUSE_A 0x7e74
1334 #define FLMTXFLSTEMPTY_S 30
1335 #define FLMTXFLSTEMPTY_V(x) ((x) << FLMTXFLSTEMPTY_S)
1336 #define FLMTXFLSTEMPTY_F FLMTXFLSTEMPTY_V(1U)
1338 #define TP_VLAN_PRI_MAP_A 0x140
1340 #define FRAGMENTATION_S 9
1341 #define FRAGMENTATION_V(x) ((x) << FRAGMENTATION_S)
1342 #define FRAGMENTATION_F FRAGMENTATION_V(1U)
1344 #define MPSHITTYPE_S 8
1345 #define MPSHITTYPE_V(x) ((x) << MPSHITTYPE_S)
1346 #define MPSHITTYPE_F MPSHITTYPE_V(1U)
1348 #define MACMATCH_S 7
1349 #define MACMATCH_V(x) ((x) << MACMATCH_S)
1350 #define MACMATCH_F MACMATCH_V(1U)
1352 #define ETHERTYPE_S 6
1353 #define ETHERTYPE_V(x) ((x) << ETHERTYPE_S)
1354 #define ETHERTYPE_F ETHERTYPE_V(1U)
1356 #define PROTOCOL_S 5
1357 #define PROTOCOL_V(x) ((x) << PROTOCOL_S)
1358 #define PROTOCOL_F PROTOCOL_V(1U)
1361 #define TOS_V(x) ((x) << TOS_S)
1362 #define TOS_F TOS_V(1U)
1365 #define VLAN_V(x) ((x) << VLAN_S)
1366 #define VLAN_F VLAN_V(1U)
1369 #define VNIC_ID_V(x) ((x) << VNIC_ID_S)
1370 #define VNIC_ID_F VNIC_ID_V(1U)
1373 #define PORT_V(x) ((x) << PORT_S)
1374 #define PORT_F PORT_V(1U)
1377 #define FCOE_V(x) ((x) << FCOE_S)
1378 #define FCOE_F FCOE_V(1U)
1380 #define FILTERMODE_S 15
1381 #define FILTERMODE_V(x) ((x) << FILTERMODE_S)
1382 #define FILTERMODE_F FILTERMODE_V(1U)
1384 #define FCOEMASK_S 14
1385 #define FCOEMASK_V(x) ((x) << FCOEMASK_S)
1386 #define FCOEMASK_F FCOEMASK_V(1U)
1388 #define TP_INGRESS_CONFIG_A 0x141
1391 #define VNIC_V(x) ((x) << VNIC_S)
1392 #define VNIC_F VNIC_V(1U)
1394 #define CSUM_HAS_PSEUDO_HDR_S 10
1395 #define CSUM_HAS_PSEUDO_HDR_V(x) ((x) << CSUM_HAS_PSEUDO_HDR_S)
1396 #define CSUM_HAS_PSEUDO_HDR_F CSUM_HAS_PSEUDO_HDR_V(1U)
1398 #define TP_MIB_MAC_IN_ERR_0_A 0x0
1399 #define TP_MIB_TCP_OUT_RST_A 0xc
1400 #define TP_MIB_TCP_IN_SEG_HI_A 0x10
1401 #define TP_MIB_TCP_IN_SEG_LO_A 0x11
1402 #define TP_MIB_TCP_OUT_SEG_HI_A 0x12
1403 #define TP_MIB_TCP_OUT_SEG_LO_A 0x13
1404 #define TP_MIB_TCP_RXT_SEG_HI_A 0x14
1405 #define TP_MIB_TCP_RXT_SEG_LO_A 0x15
1406 #define TP_MIB_TNL_CNG_DROP_0_A 0x18
1407 #define TP_MIB_TCP_V6IN_ERR_0_A 0x28
1408 #define TP_MIB_TCP_V6OUT_RST_A 0x2c
1409 #define TP_MIB_OFD_ARP_DROP_A 0x36
1410 #define TP_MIB_TNL_DROP_0_A 0x44
1411 #define TP_MIB_OFD_VLN_DROP_0_A 0x58
1413 #define ULP_TX_INT_CAUSE_A 0x8dcc
1415 #define PBL_BOUND_ERR_CH3_S 31
1416 #define PBL_BOUND_ERR_CH3_V(x) ((x) << PBL_BOUND_ERR_CH3_S)
1417 #define PBL_BOUND_ERR_CH3_F PBL_BOUND_ERR_CH3_V(1U)
1419 #define PBL_BOUND_ERR_CH2_S 30
1420 #define PBL_BOUND_ERR_CH2_V(x) ((x) << PBL_BOUND_ERR_CH2_S)
1421 #define PBL_BOUND_ERR_CH2_F PBL_BOUND_ERR_CH2_V(1U)
1423 #define PBL_BOUND_ERR_CH1_S 29
1424 #define PBL_BOUND_ERR_CH1_V(x) ((x) << PBL_BOUND_ERR_CH1_S)
1425 #define PBL_BOUND_ERR_CH1_F PBL_BOUND_ERR_CH1_V(1U)
1427 #define PBL_BOUND_ERR_CH0_S 28
1428 #define PBL_BOUND_ERR_CH0_V(x) ((x) << PBL_BOUND_ERR_CH0_S)
1429 #define PBL_BOUND_ERR_CH0_F PBL_BOUND_ERR_CH0_V(1U)
1431 #define PM_RX_INT_CAUSE_A 0x8fdc
1432 #define PM_RX_STAT_CONFIG_A 0x8fc8
1433 #define PM_RX_STAT_COUNT_A 0x8fcc
1434 #define PM_RX_STAT_LSB_A 0x8fd0
1435 #define PM_RX_DBG_CTRL_A 0x8fd0
1436 #define PM_RX_DBG_DATA_A 0x8fd4
1437 #define PM_RX_DBG_STAT_MSB_A 0x10013
1439 #define PMRX_FRAMING_ERROR_F 0x003ffff0U
1441 #define ZERO_E_CMD_ERROR_S 22
1442 #define ZERO_E_CMD_ERROR_V(x) ((x) << ZERO_E_CMD_ERROR_S)
1443 #define ZERO_E_CMD_ERROR_F ZERO_E_CMD_ERROR_V(1U)
1445 #define OCSPI_PAR_ERROR_S 3
1446 #define OCSPI_PAR_ERROR_V(x) ((x) << OCSPI_PAR_ERROR_S)
1447 #define OCSPI_PAR_ERROR_F OCSPI_PAR_ERROR_V(1U)
1449 #define DB_OPTIONS_PAR_ERROR_S 2
1450 #define DB_OPTIONS_PAR_ERROR_V(x) ((x) << DB_OPTIONS_PAR_ERROR_S)
1451 #define DB_OPTIONS_PAR_ERROR_F DB_OPTIONS_PAR_ERROR_V(1U)
1453 #define IESPI_PAR_ERROR_S 1
1454 #define IESPI_PAR_ERROR_V(x) ((x) << IESPI_PAR_ERROR_S)
1455 #define IESPI_PAR_ERROR_F IESPI_PAR_ERROR_V(1U)
1457 #define PMRX_E_PCMD_PAR_ERROR_S 0
1458 #define PMRX_E_PCMD_PAR_ERROR_V(x) ((x) << PMRX_E_PCMD_PAR_ERROR_S)
1459 #define PMRX_E_PCMD_PAR_ERROR_F PMRX_E_PCMD_PAR_ERROR_V(1U)
1461 #define PM_TX_INT_CAUSE_A 0x8ffc
1462 #define PM_TX_STAT_CONFIG_A 0x8fe8
1463 #define PM_TX_STAT_COUNT_A 0x8fec
1464 #define PM_TX_STAT_LSB_A 0x8ff0
1465 #define PM_TX_DBG_CTRL_A 0x8ff0
1466 #define PM_TX_DBG_DATA_A 0x8ff4
1467 #define PM_TX_DBG_STAT_MSB_A 0x1001a
1469 #define PCMD_LEN_OVFL0_S 31
1470 #define PCMD_LEN_OVFL0_V(x) ((x) << PCMD_LEN_OVFL0_S)
1471 #define PCMD_LEN_OVFL0_F PCMD_LEN_OVFL0_V(1U)
1473 #define PCMD_LEN_OVFL1_S 30
1474 #define PCMD_LEN_OVFL1_V(x) ((x) << PCMD_LEN_OVFL1_S)
1475 #define PCMD_LEN_OVFL1_F PCMD_LEN_OVFL1_V(1U)
1477 #define PCMD_LEN_OVFL2_S 29
1478 #define PCMD_LEN_OVFL2_V(x) ((x) << PCMD_LEN_OVFL2_S)
1479 #define PCMD_LEN_OVFL2_F PCMD_LEN_OVFL2_V(1U)
1481 #define ZERO_C_CMD_ERROR_S 28
1482 #define ZERO_C_CMD_ERROR_V(x) ((x) << ZERO_C_CMD_ERROR_S)
1483 #define ZERO_C_CMD_ERROR_F ZERO_C_CMD_ERROR_V(1U)
1485 #define PMTX_FRAMING_ERROR_F 0x0ffffff0U
1487 #define OESPI_PAR_ERROR_S 3
1488 #define OESPI_PAR_ERROR_V(x) ((x) << OESPI_PAR_ERROR_S)
1489 #define OESPI_PAR_ERROR_F OESPI_PAR_ERROR_V(1U)
1491 #define ICSPI_PAR_ERROR_S 1
1492 #define ICSPI_PAR_ERROR_V(x) ((x) << ICSPI_PAR_ERROR_S)
1493 #define ICSPI_PAR_ERROR_F ICSPI_PAR_ERROR_V(1U)
1495 #define PMTX_C_PCMD_PAR_ERROR_S 0
1496 #define PMTX_C_PCMD_PAR_ERROR_V(x) ((x) << PMTX_C_PCMD_PAR_ERROR_S)
1497 #define PMTX_C_PCMD_PAR_ERROR_F PMTX_C_PCMD_PAR_ERROR_V(1U)
1499 #define MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
1500 #define MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
1501 #define MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
1502 #define MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
1503 #define MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
1504 #define MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
1505 #define MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
1506 #define MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
1507 #define MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
1508 #define MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
1509 #define MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
1510 #define MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
1511 #define MPS_PORT_STAT_TX_PORT_64B_L 0x430
1512 #define MPS_PORT_STAT_TX_PORT_64B_H 0x434
1513 #define MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
1514 #define MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
1515 #define MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
1516 #define MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
1517 #define MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
1518 #define MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
1519 #define MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
1520 #define MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
1521 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
1522 #define MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
1523 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
1524 #define MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
1525 #define MPS_PORT_STAT_TX_PORT_DROP_L 0x468
1526 #define MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
1527 #define MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
1528 #define MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
1529 #define MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
1530 #define MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
1531 #define MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
1532 #define MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
1533 #define MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
1534 #define MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
1535 #define MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
1536 #define MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
1537 #define MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
1538 #define MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
1539 #define MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
1540 #define MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
1541 #define MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
1542 #define MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
1543 #define MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
1544 #define MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
1545 #define MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
1546 #define MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
1547 #define MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
1548 #define MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
1549 #define MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
1550 #define MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
1551 #define MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
1552 #define MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
1553 #define MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
1554 #define MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
1555 #define MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
1556 #define MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
1557 #define MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
1558 #define MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
1559 #define MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
1560 #define MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
1561 #define MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
1562 #define MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
1563 #define MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
1564 #define MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
1565 #define MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
1566 #define MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
1567 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
1568 #define MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
1569 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
1570 #define MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
1571 #define MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
1572 #define MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
1573 #define MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
1574 #define MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
1575 #define MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
1576 #define MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
1577 #define MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
1578 #define MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
1579 #define MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
1580 #define MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
1581 #define MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
1582 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
1583 #define MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
1584 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
1585 #define MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
1586 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
1587 #define MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
1588 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
1589 #define MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
1590 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
1591 #define MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
1592 #define MPS_PORT_STAT_RX_PORT_64B_L 0x590
1593 #define MPS_PORT_STAT_RX_PORT_64B_H 0x594
1594 #define MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
1595 #define MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
1596 #define MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
1597 #define MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
1598 #define MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
1599 #define MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
1600 #define MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
1601 #define MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
1602 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
1603 #define MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
1604 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
1605 #define MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
1606 #define MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
1607 #define MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
1608 #define MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
1609 #define MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
1610 #define MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
1611 #define MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
1612 #define MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
1613 #define MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
1614 #define MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
1615 #define MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
1616 #define MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
1617 #define MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
1618 #define MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
1619 #define MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
1620 #define MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
1621 #define MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
1622 #define MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
1623 #define MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
1624 #define MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
1625 #define MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
1626 #define MAC_PORT_MAGIC_MACID_LO 0x824
1627 #define MAC_PORT_MAGIC_MACID_HI 0x828
1629 #define MAC_PORT_EPIO_DATA0_A 0x8c0
1630 #define MAC_PORT_EPIO_DATA1_A 0x8c4
1631 #define MAC_PORT_EPIO_DATA2_A 0x8c8
1632 #define MAC_PORT_EPIO_DATA3_A 0x8cc
1633 #define MAC_PORT_EPIO_OP_A 0x8d0
1635 #define MAC_PORT_CFG2_A 0x818
1637 #define MPS_CMN_CTL_A 0x9000
1639 #define NUMPORTS_S 0
1640 #define NUMPORTS_M 0x3U
1641 #define NUMPORTS_G(x) (((x) >> NUMPORTS_S) & NUMPORTS_M)
1643 #define MPS_INT_CAUSE_A 0x9008
1644 #define MPS_TX_INT_CAUSE_A 0x9408
1647 #define FRMERR_V(x) ((x) << FRMERR_S)
1648 #define FRMERR_F FRMERR_V(1U)
1650 #define SECNTERR_S 14
1651 #define SECNTERR_V(x) ((x) << SECNTERR_S)
1652 #define SECNTERR_F SECNTERR_V(1U)
1655 #define BUBBLE_V(x) ((x) << BUBBLE_S)
1656 #define BUBBLE_F BUBBLE_V(1U)
1658 #define TXDESCFIFO_S 9
1659 #define TXDESCFIFO_M 0xfU
1660 #define TXDESCFIFO_V(x) ((x) << TXDESCFIFO_S)
1662 #define TXDATAFIFO_S 5
1663 #define TXDATAFIFO_M 0xfU
1664 #define TXDATAFIFO_V(x) ((x) << TXDATAFIFO_S)
1666 #define NCSIFIFO_S 4
1667 #define NCSIFIFO_V(x) ((x) << NCSIFIFO_S)
1668 #define NCSIFIFO_F NCSIFIFO_V(1U)
1671 #define TPFIFO_M 0xfU
1672 #define TPFIFO_V(x) ((x) << TPFIFO_S)
1674 #define MPS_STAT_PERR_INT_CAUSE_SRAM_A 0x9614
1675 #define MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A 0x9620
1676 #define MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A 0x962c
1678 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
1679 #define MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
1680 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
1681 #define MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
1682 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
1683 #define MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
1684 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
1685 #define MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
1686 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
1687 #define MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
1688 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
1689 #define MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
1690 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
1691 #define MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
1692 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
1693 #define MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
1694 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
1695 #define MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
1696 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
1697 #define MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
1698 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
1699 #define MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
1700 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
1701 #define MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
1702 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
1703 #define MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
1704 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
1705 #define MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
1706 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
1707 #define MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
1708 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
1709 #define MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
1711 #define MPS_TRC_CFG_A 0x9800
1713 #define TRCFIFOEMPTY_S 4
1714 #define TRCFIFOEMPTY_V(x) ((x) << TRCFIFOEMPTY_S)
1715 #define TRCFIFOEMPTY_F TRCFIFOEMPTY_V(1U)
1717 #define TRCIGNOREDROPINPUT_S 3
1718 #define TRCIGNOREDROPINPUT_V(x) ((x) << TRCIGNOREDROPINPUT_S)
1719 #define TRCIGNOREDROPINPUT_F TRCIGNOREDROPINPUT_V(1U)
1721 #define TRCKEEPDUPLICATES_S 2
1722 #define TRCKEEPDUPLICATES_V(x) ((x) << TRCKEEPDUPLICATES_S)
1723 #define TRCKEEPDUPLICATES_F TRCKEEPDUPLICATES_V(1U)
1726 #define TRCEN_V(x) ((x) << TRCEN_S)
1727 #define TRCEN_F TRCEN_V(1U)
1729 #define TRCMULTIFILTER_S 0
1730 #define TRCMULTIFILTER_V(x) ((x) << TRCMULTIFILTER_S)
1731 #define TRCMULTIFILTER_F TRCMULTIFILTER_V(1U)
1733 #define MPS_TRC_RSS_CONTROL_A 0x9808
1734 #define MPS_T5_TRC_RSS_CONTROL_A 0xa00c
1736 #define RSSCONTROL_S 16
1737 #define RSSCONTROL_V(x) ((x) << RSSCONTROL_S)
1739 #define QUEUENUMBER_S 0
1740 #define QUEUENUMBER_V(x) ((x) << QUEUENUMBER_S)
1742 #define TP_RSS_CONFIG_A 0x7df0
1744 #define TNL4TUPENIPV6_S 31
1745 #define TNL4TUPENIPV6_V(x) ((x) << TNL4TUPENIPV6_S)
1746 #define TNL4TUPENIPV6_F TNL4TUPENIPV6_V(1U)
1748 #define TNL2TUPENIPV6_S 30
1749 #define TNL2TUPENIPV6_V(x) ((x) << TNL2TUPENIPV6_S)
1750 #define TNL2TUPENIPV6_F TNL2TUPENIPV6_V(1U)
1752 #define TNL4TUPENIPV4_S 29
1753 #define TNL4TUPENIPV4_V(x) ((x) << TNL4TUPENIPV4_S)
1754 #define TNL4TUPENIPV4_F TNL4TUPENIPV4_V(1U)
1756 #define TNL2TUPENIPV4_S 28
1757 #define TNL2TUPENIPV4_V(x) ((x) << TNL2TUPENIPV4_S)
1758 #define TNL2TUPENIPV4_F TNL2TUPENIPV4_V(1U)
1760 #define TNLTCPSEL_S 27
1761 #define TNLTCPSEL_V(x) ((x) << TNLTCPSEL_S)
1762 #define TNLTCPSEL_F TNLTCPSEL_V(1U)
1764 #define TNLIP6SEL_S 26
1765 #define TNLIP6SEL_V(x) ((x) << TNLIP6SEL_S)
1766 #define TNLIP6SEL_F TNLIP6SEL_V(1U)
1768 #define TNLVRTSEL_S 25
1769 #define TNLVRTSEL_V(x) ((x) << TNLVRTSEL_S)
1770 #define TNLVRTSEL_F TNLVRTSEL_V(1U)
1772 #define TNLMAPEN_S 24
1773 #define TNLMAPEN_V(x) ((x) << TNLMAPEN_S)
1774 #define TNLMAPEN_F TNLMAPEN_V(1U)
1776 #define OFDHASHSAVE_S 19
1777 #define OFDHASHSAVE_V(x) ((x) << OFDHASHSAVE_S)
1778 #define OFDHASHSAVE_F OFDHASHSAVE_V(1U)
1780 #define OFDVRTSEL_S 18
1781 #define OFDVRTSEL_V(x) ((x) << OFDVRTSEL_S)
1782 #define OFDVRTSEL_F OFDVRTSEL_V(1U)
1784 #define OFDMAPEN_S 17
1785 #define OFDMAPEN_V(x) ((x) << OFDMAPEN_S)
1786 #define OFDMAPEN_F OFDMAPEN_V(1U)
1788 #define OFDLKPEN_S 16
1789 #define OFDLKPEN_V(x) ((x) << OFDLKPEN_S)
1790 #define OFDLKPEN_F OFDLKPEN_V(1U)
1792 #define SYN4TUPENIPV6_S 15
1793 #define SYN4TUPENIPV6_V(x) ((x) << SYN4TUPENIPV6_S)
1794 #define SYN4TUPENIPV6_F SYN4TUPENIPV6_V(1U)
1796 #define SYN2TUPENIPV6_S 14
1797 #define SYN2TUPENIPV6_V(x) ((x) << SYN2TUPENIPV6_S)
1798 #define SYN2TUPENIPV6_F SYN2TUPENIPV6_V(1U)
1800 #define SYN4TUPENIPV4_S 13
1801 #define SYN4TUPENIPV4_V(x) ((x) << SYN4TUPENIPV4_S)
1802 #define SYN4TUPENIPV4_F SYN4TUPENIPV4_V(1U)
1804 #define SYN2TUPENIPV4_S 12
1805 #define SYN2TUPENIPV4_V(x) ((x) << SYN2TUPENIPV4_S)
1806 #define SYN2TUPENIPV4_F SYN2TUPENIPV4_V(1U)
1808 #define SYNIP6SEL_S 11
1809 #define SYNIP6SEL_V(x) ((x) << SYNIP6SEL_S)
1810 #define SYNIP6SEL_F SYNIP6SEL_V(1U)
1812 #define SYNVRTSEL_S 10
1813 #define SYNVRTSEL_V(x) ((x) << SYNVRTSEL_S)
1814 #define SYNVRTSEL_F SYNVRTSEL_V(1U)
1816 #define SYNMAPEN_S 9
1817 #define SYNMAPEN_V(x) ((x) << SYNMAPEN_S)
1818 #define SYNMAPEN_F SYNMAPEN_V(1U)
1820 #define SYNLKPEN_S 8
1821 #define SYNLKPEN_V(x) ((x) << SYNLKPEN_S)
1822 #define SYNLKPEN_F SYNLKPEN_V(1U)
1824 #define CHANNELENABLE_S 7
1825 #define CHANNELENABLE_V(x) ((x) << CHANNELENABLE_S)
1826 #define CHANNELENABLE_F CHANNELENABLE_V(1U)
1828 #define PORTENABLE_S 6
1829 #define PORTENABLE_V(x) ((x) << PORTENABLE_S)
1830 #define PORTENABLE_F PORTENABLE_V(1U)
1832 #define TNLALLLOOKUP_S 5
1833 #define TNLALLLOOKUP_V(x) ((x) << TNLALLLOOKUP_S)
1834 #define TNLALLLOOKUP_F TNLALLLOOKUP_V(1U)
1836 #define VIRTENABLE_S 4
1837 #define VIRTENABLE_V(x) ((x) << VIRTENABLE_S)
1838 #define VIRTENABLE_F VIRTENABLE_V(1U)
1840 #define CONGESTIONENABLE_S 3
1841 #define CONGESTIONENABLE_V(x) ((x) << CONGESTIONENABLE_S)
1842 #define CONGESTIONENABLE_F CONGESTIONENABLE_V(1U)
1844 #define HASHTOEPLITZ_S 2
1845 #define HASHTOEPLITZ_V(x) ((x) << HASHTOEPLITZ_S)
1846 #define HASHTOEPLITZ_F HASHTOEPLITZ_V(1U)
1848 #define UDPENABLE_S 1
1849 #define UDPENABLE_V(x) ((x) << UDPENABLE_S)
1850 #define UDPENABLE_F UDPENABLE_V(1U)
1853 #define DISABLE_V(x) ((x) << DISABLE_S)
1854 #define DISABLE_F DISABLE_V(1U)
1856 #define TP_RSS_CONFIG_TNL_A 0x7df4
1858 #define MASKSIZE_S 28
1859 #define MASKSIZE_M 0xfU
1860 #define MASKSIZE_V(x) ((x) << MASKSIZE_S)
1861 #define MASKSIZE_G(x) (((x) >> MASKSIZE_S) & MASKSIZE_M)
1863 #define MASKFILTER_S 16
1864 #define MASKFILTER_M 0x7ffU
1865 #define MASKFILTER_V(x) ((x) << MASKFILTER_S)
1866 #define MASKFILTER_G(x) (((x) >> MASKFILTER_S) & MASKFILTER_M)
1868 #define USEWIRECH_S 0
1869 #define USEWIRECH_V(x) ((x) << USEWIRECH_S)
1870 #define USEWIRECH_F USEWIRECH_V(1U)
1873 #define HASHALL_V(x) ((x) << HASHALL_S)
1874 #define HASHALL_F HASHALL_V(1U)
1877 #define HASHETH_V(x) ((x) << HASHETH_S)
1878 #define HASHETH_F HASHETH_V(1U)
1880 #define TP_RSS_CONFIG_OFD_A 0x7df8
1882 #define RRCPLMAPEN_S 20
1883 #define RRCPLMAPEN_V(x) ((x) << RRCPLMAPEN_S)
1884 #define RRCPLMAPEN_F RRCPLMAPEN_V(1U)
1886 #define RRCPLQUEWIDTH_S 16
1887 #define RRCPLQUEWIDTH_M 0xfU
1888 #define RRCPLQUEWIDTH_V(x) ((x) << RRCPLQUEWIDTH_S)
1889 #define RRCPLQUEWIDTH_G(x) (((x) >> RRCPLQUEWIDTH_S) & RRCPLQUEWIDTH_M)
1891 #define TP_RSS_CONFIG_SYN_A 0x7dfc
1892 #define TP_RSS_CONFIG_VRT_A 0x7e00
1895 #define VFRDRG_V(x) ((x) << VFRDRG_S)
1896 #define VFRDRG_F VFRDRG_V(1U)
1899 #define VFRDEN_V(x) ((x) << VFRDEN_S)
1900 #define VFRDEN_F VFRDEN_V(1U)
1902 #define VFPERREN_S 23
1903 #define VFPERREN_V(x) ((x) << VFPERREN_S)
1904 #define VFPERREN_F VFPERREN_V(1U)
1906 #define KEYPERREN_S 22
1907 #define KEYPERREN_V(x) ((x) << KEYPERREN_S)
1908 #define KEYPERREN_F KEYPERREN_V(1U)
1910 #define DISABLEVLAN_S 21
1911 #define DISABLEVLAN_V(x) ((x) << DISABLEVLAN_S)
1912 #define DISABLEVLAN_F DISABLEVLAN_V(1U)
1914 #define ENABLEUP0_S 20
1915 #define ENABLEUP0_V(x) ((x) << ENABLEUP0_S)
1916 #define ENABLEUP0_F ENABLEUP0_V(1U)
1918 #define HASHDELAY_S 16
1919 #define HASHDELAY_M 0xfU
1920 #define HASHDELAY_V(x) ((x) << HASHDELAY_S)
1921 #define HASHDELAY_G(x) (((x) >> HASHDELAY_S) & HASHDELAY_M)
1923 #define VFWRADDR_S 8
1924 #define VFWRADDR_M 0x7fU
1925 #define VFWRADDR_V(x) ((x) << VFWRADDR_S)
1926 #define VFWRADDR_G(x) (((x) >> VFWRADDR_S) & VFWRADDR_M)
1929 #define KEYMODE_M 0x3U
1930 #define KEYMODE_V(x) ((x) << KEYMODE_S)
1931 #define KEYMODE_G(x) (((x) >> KEYMODE_S) & KEYMODE_M)
1934 #define VFWREN_V(x) ((x) << VFWREN_S)
1935 #define VFWREN_F VFWREN_V(1U)
1938 #define KEYWREN_V(x) ((x) << KEYWREN_S)
1939 #define KEYWREN_F KEYWREN_V(1U)
1941 #define KEYWRADDR_S 0
1942 #define KEYWRADDR_M 0xfU
1943 #define KEYWRADDR_V(x) ((x) << KEYWRADDR_S)
1944 #define KEYWRADDR_G(x) (((x) >> KEYWRADDR_S) & KEYWRADDR_M)
1946 #define KEYWRADDRX_S 30
1947 #define KEYWRADDRX_M 0x3U
1948 #define KEYWRADDRX_V(x) ((x) << KEYWRADDRX_S)
1949 #define KEYWRADDRX_G(x) (((x) >> KEYWRADDRX_S) & KEYWRADDRX_M)
1951 #define KEYEXTEND_S 26
1952 #define KEYEXTEND_V(x) ((x) << KEYEXTEND_S)
1953 #define KEYEXTEND_F KEYEXTEND_V(1U)
1955 #define LKPIDXSIZE_S 24
1956 #define LKPIDXSIZE_M 0x3U
1957 #define LKPIDXSIZE_V(x) ((x) << LKPIDXSIZE_S)
1958 #define LKPIDXSIZE_G(x) (((x) >> LKPIDXSIZE_S) & LKPIDXSIZE_M)
1960 #define TP_RSS_VFL_CONFIG_A 0x3a
1961 #define TP_RSS_VFH_CONFIG_A 0x3b
1963 #define ENABLEUDPHASH_S 31
1964 #define ENABLEUDPHASH_V(x) ((x) << ENABLEUDPHASH_S)
1965 #define ENABLEUDPHASH_F ENABLEUDPHASH_V(1U)
1968 #define VFUPEN_V(x) ((x) << VFUPEN_S)
1969 #define VFUPEN_F VFUPEN_V(1U)
1971 #define VFVLNEX_S 28
1972 #define VFVLNEX_V(x) ((x) << VFVLNEX_S)
1973 #define VFVLNEX_F VFVLNEX_V(1U)
1975 #define VFPRTEN_S 27
1976 #define VFPRTEN_V(x) ((x) << VFPRTEN_S)
1977 #define VFPRTEN_F VFPRTEN_V(1U)
1979 #define VFCHNEN_S 26
1980 #define VFCHNEN_V(x) ((x) << VFCHNEN_S)
1981 #define VFCHNEN_F VFCHNEN_V(1U)
1983 #define DEFAULTQUEUE_S 16
1984 #define DEFAULTQUEUE_M 0x3ffU
1985 #define DEFAULTQUEUE_G(x) (((x) >> DEFAULTQUEUE_S) & DEFAULTQUEUE_M)
1987 #define VFIP6TWOTUPEN_S 6
1988 #define VFIP6TWOTUPEN_V(x) ((x) << VFIP6TWOTUPEN_S)
1989 #define VFIP6TWOTUPEN_F VFIP6TWOTUPEN_V(1U)
1991 #define VFIP4FOURTUPEN_S 5
1992 #define VFIP4FOURTUPEN_V(x) ((x) << VFIP4FOURTUPEN_S)
1993 #define VFIP4FOURTUPEN_F VFIP4FOURTUPEN_V(1U)
1995 #define VFIP4TWOTUPEN_S 4
1996 #define VFIP4TWOTUPEN_V(x) ((x) << VFIP4TWOTUPEN_S)
1997 #define VFIP4TWOTUPEN_F VFIP4TWOTUPEN_V(1U)
1999 #define KEYINDEX_S 0
2000 #define KEYINDEX_M 0xfU
2001 #define KEYINDEX_G(x) (((x) >> KEYINDEX_S) & KEYINDEX_M)
2003 #define MAPENABLE_S 31
2004 #define MAPENABLE_V(x) ((x) << MAPENABLE_S)
2005 #define MAPENABLE_F MAPENABLE_V(1U)
2007 #define CHNENABLE_S 30
2008 #define CHNENABLE_V(x) ((x) << CHNENABLE_S)
2009 #define CHNENABLE_F CHNENABLE_V(1U)
2011 #define PRTENABLE_S 29
2012 #define PRTENABLE_V(x) ((x) << PRTENABLE_S)
2013 #define PRTENABLE_F PRTENABLE_V(1U)
2015 #define UDPFOURTUPEN_S 28
2016 #define UDPFOURTUPEN_V(x) ((x) << UDPFOURTUPEN_S)
2017 #define UDPFOURTUPEN_F UDPFOURTUPEN_V(1U)
2019 #define IP6FOURTUPEN_S 27
2020 #define IP6FOURTUPEN_V(x) ((x) << IP6FOURTUPEN_S)
2021 #define IP6FOURTUPEN_F IP6FOURTUPEN_V(1U)
2023 #define IP6TWOTUPEN_S 26
2024 #define IP6TWOTUPEN_V(x) ((x) << IP6TWOTUPEN_S)
2025 #define IP6TWOTUPEN_F IP6TWOTUPEN_V(1U)
2027 #define IP4FOURTUPEN_S 25
2028 #define IP4FOURTUPEN_V(x) ((x) << IP4FOURTUPEN_S)
2029 #define IP4FOURTUPEN_F IP4FOURTUPEN_V(1U)
2031 #define IP4TWOTUPEN_S 24
2032 #define IP4TWOTUPEN_V(x) ((x) << IP4TWOTUPEN_S)
2033 #define IP4TWOTUPEN_F IP4TWOTUPEN_V(1U)
2035 #define IVFWIDTH_S 20
2036 #define IVFWIDTH_M 0xfU
2037 #define IVFWIDTH_V(x) ((x) << IVFWIDTH_S)
2038 #define IVFWIDTH_G(x) (((x) >> IVFWIDTH_S) & IVFWIDTH_M)
2040 #define CH1DEFAULTQUEUE_S 10
2041 #define CH1DEFAULTQUEUE_M 0x3ffU
2042 #define CH1DEFAULTQUEUE_V(x) ((x) << CH1DEFAULTQUEUE_S)
2043 #define CH1DEFAULTQUEUE_G(x) (((x) >> CH1DEFAULTQUEUE_S) & CH1DEFAULTQUEUE_M)
2045 #define CH0DEFAULTQUEUE_S 0
2046 #define CH0DEFAULTQUEUE_M 0x3ffU
2047 #define CH0DEFAULTQUEUE_V(x) ((x) << CH0DEFAULTQUEUE_S)
2048 #define CH0DEFAULTQUEUE_G(x) (((x) >> CH0DEFAULTQUEUE_S) & CH0DEFAULTQUEUE_M)
2050 #define VFLKPIDX_S 8
2051 #define VFLKPIDX_M 0xffU
2052 #define VFLKPIDX_G(x) (((x) >> VFLKPIDX_S) & VFLKPIDX_M)
2054 #define TP_RSS_CONFIG_CNG_A 0x7e04
2055 #define TP_RSS_SECRET_KEY0_A 0x40
2056 #define TP_RSS_PF0_CONFIG_A 0x30
2057 #define TP_RSS_PF_MAP_A 0x38
2058 #define TP_RSS_PF_MSK_A 0x39
2060 #define PF1LKPIDX_S 3
2062 #define PF0LKPIDX_M 0x7U
2064 #define PF1MSKSIZE_S 4
2065 #define PF1MSKSIZE_M 0xfU
2067 #define CHNCOUNT3_S 31
2068 #define CHNCOUNT3_V(x) ((x) << CHNCOUNT3_S)
2069 #define CHNCOUNT3_F CHNCOUNT3_V(1U)
2071 #define CHNCOUNT2_S 30
2072 #define CHNCOUNT2_V(x) ((x) << CHNCOUNT2_S)
2073 #define CHNCOUNT2_F CHNCOUNT2_V(1U)
2075 #define CHNCOUNT1_S 29
2076 #define CHNCOUNT1_V(x) ((x) << CHNCOUNT1_S)
2077 #define CHNCOUNT1_F CHNCOUNT1_V(1U)
2079 #define CHNCOUNT0_S 28
2080 #define CHNCOUNT0_V(x) ((x) << CHNCOUNT0_S)
2081 #define CHNCOUNT0_F CHNCOUNT0_V(1U)
2083 #define CHNUNDFLOW3_S 27
2084 #define CHNUNDFLOW3_V(x) ((x) << CHNUNDFLOW3_S)
2085 #define CHNUNDFLOW3_F CHNUNDFLOW3_V(1U)
2087 #define CHNUNDFLOW2_S 26
2088 #define CHNUNDFLOW2_V(x) ((x) << CHNUNDFLOW2_S)
2089 #define CHNUNDFLOW2_F CHNUNDFLOW2_V(1U)
2091 #define CHNUNDFLOW1_S 25
2092 #define CHNUNDFLOW1_V(x) ((x) << CHNUNDFLOW1_S)
2093 #define CHNUNDFLOW1_F CHNUNDFLOW1_V(1U)
2095 #define CHNUNDFLOW0_S 24
2096 #define CHNUNDFLOW0_V(x) ((x) << CHNUNDFLOW0_S)
2097 #define CHNUNDFLOW0_F CHNUNDFLOW0_V(1U)
2099 #define RSTCHN3_S 19
2100 #define RSTCHN3_V(x) ((x) << RSTCHN3_S)
2101 #define RSTCHN3_F RSTCHN3_V(1U)
2103 #define RSTCHN2_S 18
2104 #define RSTCHN2_V(x) ((x) << RSTCHN2_S)
2105 #define RSTCHN2_F RSTCHN2_V(1U)
2107 #define RSTCHN1_S 17
2108 #define RSTCHN1_V(x) ((x) << RSTCHN1_S)
2109 #define RSTCHN1_F RSTCHN1_V(1U)
2111 #define RSTCHN0_S 16
2112 #define RSTCHN0_V(x) ((x) << RSTCHN0_S)
2113 #define RSTCHN0_F RSTCHN0_V(1U)
2116 #define UPDVLD_V(x) ((x) << UPDVLD_S)
2117 #define UPDVLD_F UPDVLD_V(1U)
2120 #define XOFF_V(x) ((x) << XOFF_S)
2121 #define XOFF_F XOFF_V(1U)
2123 #define UPDCHN3_S 13
2124 #define UPDCHN3_V(x) ((x) << UPDCHN3_S)
2125 #define UPDCHN3_F UPDCHN3_V(1U)
2127 #define UPDCHN2_S 12
2128 #define UPDCHN2_V(x) ((x) << UPDCHN2_S)
2129 #define UPDCHN2_F UPDCHN2_V(1U)
2131 #define UPDCHN1_S 11
2132 #define UPDCHN1_V(x) ((x) << UPDCHN1_S)
2133 #define UPDCHN1_F UPDCHN1_V(1U)
2135 #define UPDCHN0_S 10
2136 #define UPDCHN0_V(x) ((x) << UPDCHN0_S)
2137 #define UPDCHN0_F UPDCHN0_V(1U)
2140 #define QUEUE_M 0x3ffU
2141 #define QUEUE_V(x) ((x) << QUEUE_S)
2142 #define QUEUE_G(x) (((x) >> QUEUE_S) & QUEUE_M)
2144 #define MPS_TRC_INT_CAUSE_A 0x985c
2146 #define MISCPERR_S 8
2147 #define MISCPERR_V(x) ((x) << MISCPERR_S)
2148 #define MISCPERR_F MISCPERR_V(1U)
2151 #define PKTFIFO_M 0xfU
2152 #define PKTFIFO_V(x) ((x) << PKTFIFO_S)
2155 #define FILTMEM_M 0xfU
2156 #define FILTMEM_V(x) ((x) << FILTMEM_S)
2158 #define MPS_CLS_INT_CAUSE_A 0xd028
2160 #define HASHSRAM_S 2
2161 #define HASHSRAM_V(x) ((x) << HASHSRAM_S)
2162 #define HASHSRAM_F HASHSRAM_V(1U)
2164 #define MATCHTCAM_S 1
2165 #define MATCHTCAM_V(x) ((x) << MATCHTCAM_S)
2166 #define MATCHTCAM_F MATCHTCAM_V(1U)
2168 #define MATCHSRAM_S 0
2169 #define MATCHSRAM_V(x) ((x) << MATCHSRAM_S)
2170 #define MATCHSRAM_F MATCHSRAM_V(1U)
2172 #define MPS_RX_PERR_INT_CAUSE_A 0x11074
2174 #define MPS_CLS_TCAM_Y_L_A 0xf000
2175 #define MPS_CLS_TCAM_X_L_A 0xf008
2177 #define MPS_CLS_TCAM_Y_L(idx) (MPS_CLS_TCAM_Y_L_A + (idx) * 16)
2178 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
2180 #define MPS_CLS_TCAM_X_L(idx) (MPS_CLS_TCAM_X_L_A + (idx) * 16)
2181 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
2183 #define MPS_CLS_SRAM_L_A 0xe000
2184 #define MPS_CLS_SRAM_H_A 0xe004
2186 #define MPS_CLS_SRAM_L(idx) (MPS_CLS_SRAM_L_A + (idx) * 8)
2187 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2189 #define MPS_CLS_SRAM_H(idx) (MPS_CLS_SRAM_H_A + (idx) * 8)
2190 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
2192 #define MULTILISTEN0_S 25
2194 #define REPLICATE_S 11
2195 #define REPLICATE_V(x) ((x) << REPLICATE_S)
2196 #define REPLICATE_F REPLICATE_V(1U)
2200 #define PF_G(x) (((x) >> PF_S) & PF_M)
2202 #define VF_VALID_S 7
2203 #define VF_VALID_V(x) ((x) << VF_VALID_S)
2204 #define VF_VALID_F VF_VALID_V(1U)
2208 #define VF_G(x) (((x) >> VF_S) & VF_M)
2210 #define SRAM_PRIO3_S 22
2211 #define SRAM_PRIO3_M 0x7U
2212 #define SRAM_PRIO3_G(x) (((x) >> SRAM_PRIO3_S) & SRAM_PRIO3_M)
2214 #define SRAM_PRIO2_S 19
2215 #define SRAM_PRIO2_M 0x7U
2216 #define SRAM_PRIO2_G(x) (((x) >> SRAM_PRIO2_S) & SRAM_PRIO2_M)
2218 #define SRAM_PRIO1_S 16
2219 #define SRAM_PRIO1_M 0x7U
2220 #define SRAM_PRIO1_G(x) (((x) >> SRAM_PRIO1_S) & SRAM_PRIO1_M)
2222 #define SRAM_PRIO0_S 13
2223 #define SRAM_PRIO0_M 0x7U
2224 #define SRAM_PRIO0_G(x) (((x) >> SRAM_PRIO0_S) & SRAM_PRIO0_M)
2226 #define SRAM_VLD_S 12
2227 #define SRAM_VLD_V(x) ((x) << SRAM_VLD_S)
2228 #define SRAM_VLD_F SRAM_VLD_V(1U)
2231 #define PORTMAP_M 0xfU
2232 #define PORTMAP_G(x) (((x) >> PORTMAP_S) & PORTMAP_M)
2234 #define CPL_INTR_CAUSE_A 0x19054
2236 #define CIM_OP_MAP_PERR_S 5
2237 #define CIM_OP_MAP_PERR_V(x) ((x) << CIM_OP_MAP_PERR_S)
2238 #define CIM_OP_MAP_PERR_F CIM_OP_MAP_PERR_V(1U)
2240 #define CIM_OVFL_ERROR_S 4
2241 #define CIM_OVFL_ERROR_V(x) ((x) << CIM_OVFL_ERROR_S)
2242 #define CIM_OVFL_ERROR_F CIM_OVFL_ERROR_V(1U)
2244 #define TP_FRAMING_ERROR_S 3
2245 #define TP_FRAMING_ERROR_V(x) ((x) << TP_FRAMING_ERROR_S)
2246 #define TP_FRAMING_ERROR_F TP_FRAMING_ERROR_V(1U)
2248 #define SGE_FRAMING_ERROR_S 2
2249 #define SGE_FRAMING_ERROR_V(x) ((x) << SGE_FRAMING_ERROR_S)
2250 #define SGE_FRAMING_ERROR_F SGE_FRAMING_ERROR_V(1U)
2252 #define CIM_FRAMING_ERROR_S 1
2253 #define CIM_FRAMING_ERROR_V(x) ((x) << CIM_FRAMING_ERROR_S)
2254 #define CIM_FRAMING_ERROR_F CIM_FRAMING_ERROR_V(1U)
2256 #define ZERO_SWITCH_ERROR_S 0
2257 #define ZERO_SWITCH_ERROR_V(x) ((x) << ZERO_SWITCH_ERROR_S)
2258 #define ZERO_SWITCH_ERROR_F ZERO_SWITCH_ERROR_V(1U)
2260 #define SMB_INT_CAUSE_A 0x19090
2262 #define MSTTXFIFOPARINT_S 21
2263 #define MSTTXFIFOPARINT_V(x) ((x) << MSTTXFIFOPARINT_S)
2264 #define MSTTXFIFOPARINT_F MSTTXFIFOPARINT_V(1U)
2266 #define MSTRXFIFOPARINT_S 20
2267 #define MSTRXFIFOPARINT_V(x) ((x) << MSTRXFIFOPARINT_S)
2268 #define MSTRXFIFOPARINT_F MSTRXFIFOPARINT_V(1U)
2270 #define SLVFIFOPARINT_S 19
2271 #define SLVFIFOPARINT_V(x) ((x) << SLVFIFOPARINT_S)
2272 #define SLVFIFOPARINT_F SLVFIFOPARINT_V(1U)
2274 #define ULP_RX_INT_CAUSE_A 0x19158
2275 #define ULP_RX_ISCSI_TAGMASK_A 0x19164
2276 #define ULP_RX_ISCSI_PSZ_A 0x19168
2277 #define ULP_RX_LA_CTL_A 0x1923c
2278 #define ULP_RX_LA_RDPTR_A 0x19240
2279 #define ULP_RX_LA_RDDATA_A 0x19244
2280 #define ULP_RX_LA_WRPTR_A 0x19248
2283 #define HPZ3_V(x) ((x) << HPZ3_S)
2286 #define HPZ2_V(x) ((x) << HPZ2_S)
2289 #define HPZ1_V(x) ((x) << HPZ1_S)
2292 #define HPZ0_V(x) ((x) << HPZ0_S)
2294 #define ULP_RX_TDDP_PSZ_A 0x19178
2296 /* registers for module SF */
2297 #define SF_DATA_A 0x193f8
2298 #define SF_OP_A 0x193fc
2300 #define SF_BUSY_S 31
2301 #define SF_BUSY_V(x) ((x) << SF_BUSY_S)
2302 #define SF_BUSY_F SF_BUSY_V(1U)
2305 #define SF_LOCK_V(x) ((x) << SF_LOCK_S)
2306 #define SF_LOCK_F SF_LOCK_V(1U)
2309 #define SF_CONT_V(x) ((x) << SF_CONT_S)
2310 #define SF_CONT_F SF_CONT_V(1U)
2313 #define BYTECNT_V(x) ((x) << BYTECNT_S)
2316 #define OP_V(x) ((x) << OP_S)
2317 #define OP_F OP_V(1U)
2319 #define PL_PF_INT_CAUSE_A 0x3c0
2322 #define PFSW_V(x) ((x) << PFSW_S)
2323 #define PFSW_F PFSW_V(1U)
2326 #define PFCIM_V(x) ((x) << PFCIM_S)
2327 #define PFCIM_F PFCIM_V(1U)
2329 #define PL_PF_INT_ENABLE_A 0x3c4
2330 #define PL_PF_CTL_A 0x3c8
2332 #define PL_WHOAMI_A 0x19400
2334 #define SOURCEPF_S 8
2335 #define SOURCEPF_M 0x7U
2336 #define SOURCEPF_G(x) (((x) >> SOURCEPF_S) & SOURCEPF_M)
2338 #define PL_INT_CAUSE_A 0x1940c
2341 #define ULP_TX_V(x) ((x) << ULP_TX_S)
2342 #define ULP_TX_F ULP_TX_V(1U)
2345 #define SGE_V(x) ((x) << SGE_S)
2346 #define SGE_F SGE_V(1U)
2348 #define CPL_SWITCH_S 24
2349 #define CPL_SWITCH_V(x) ((x) << CPL_SWITCH_S)
2350 #define CPL_SWITCH_F CPL_SWITCH_V(1U)
2353 #define ULP_RX_V(x) ((x) << ULP_RX_S)
2354 #define ULP_RX_F ULP_RX_V(1U)
2357 #define PM_RX_V(x) ((x) << PM_RX_S)
2358 #define PM_RX_F PM_RX_V(1U)
2361 #define PM_TX_V(x) ((x) << PM_TX_S)
2362 #define PM_TX_F PM_TX_V(1U)
2365 #define MA_V(x) ((x) << MA_S)
2366 #define MA_F MA_V(1U)
2369 #define TP_V(x) ((x) << TP_S)
2370 #define TP_F TP_V(1U)
2373 #define LE_V(x) ((x) << LE_S)
2374 #define LE_F LE_V(1U)
2377 #define EDC1_V(x) ((x) << EDC1_S)
2378 #define EDC1_F EDC1_V(1U)
2381 #define EDC0_V(x) ((x) << EDC0_S)
2382 #define EDC0_F EDC0_V(1U)
2385 #define MC_V(x) ((x) << MC_S)
2386 #define MC_F MC_V(1U)
2389 #define PCIE_V(x) ((x) << PCIE_S)
2390 #define PCIE_F PCIE_V(1U)
2392 #define XGMAC_KR1_S 12
2393 #define XGMAC_KR1_V(x) ((x) << XGMAC_KR1_S)
2394 #define XGMAC_KR1_F XGMAC_KR1_V(1U)
2396 #define XGMAC_KR0_S 11
2397 #define XGMAC_KR0_V(x) ((x) << XGMAC_KR0_S)
2398 #define XGMAC_KR0_F XGMAC_KR0_V(1U)
2401 #define XGMAC1_V(x) ((x) << XGMAC1_S)
2402 #define XGMAC1_F XGMAC1_V(1U)
2405 #define XGMAC0_V(x) ((x) << XGMAC0_S)
2406 #define XGMAC0_F XGMAC0_V(1U)
2409 #define SMB_V(x) ((x) << SMB_S)
2410 #define SMB_F SMB_V(1U)
2413 #define SF_V(x) ((x) << SF_S)
2414 #define SF_F SF_V(1U)
2417 #define PL_V(x) ((x) << PL_S)
2418 #define PL_F PL_V(1U)
2421 #define NCSI_V(x) ((x) << NCSI_S)
2422 #define NCSI_F NCSI_V(1U)
2425 #define MPS_V(x) ((x) << MPS_S)
2426 #define MPS_F MPS_V(1U)
2429 #define CIM_V(x) ((x) << CIM_S)
2430 #define CIM_F CIM_V(1U)
2434 #define PL_INT_ENABLE_A 0x19410
2435 #define PL_INT_MAP0_A 0x19414
2436 #define PL_RST_A 0x19428
2439 #define PIORST_V(x) ((x) << PIORST_S)
2440 #define PIORST_F PIORST_V(1U)
2442 #define PIORSTMODE_S 0
2443 #define PIORSTMODE_V(x) ((x) << PIORSTMODE_S)
2444 #define PIORSTMODE_F PIORSTMODE_V(1U)
2446 #define PL_PL_INT_CAUSE_A 0x19430
2448 #define FATALPERR_S 4
2449 #define FATALPERR_V(x) ((x) << FATALPERR_S)
2450 #define FATALPERR_F FATALPERR_V(1U)
2452 #define PERRVFID_S 0
2453 #define PERRVFID_V(x) ((x) << PERRVFID_S)
2454 #define PERRVFID_F PERRVFID_V(1U)
2456 #define PL_REV_A 0x1943c
2460 #define REV_V(x) ((x) << REV_S)
2461 #define REV_G(x) (((x) >> REV_S) & REV_M)
2463 #define LE_DB_INT_CAUSE_A 0x19c3c
2465 #define REQQPARERR_S 16
2466 #define REQQPARERR_V(x) ((x) << REQQPARERR_S)
2467 #define REQQPARERR_F REQQPARERR_V(1U)
2469 #define UNKNOWNCMD_S 15
2470 #define UNKNOWNCMD_V(x) ((x) << UNKNOWNCMD_S)
2471 #define UNKNOWNCMD_F UNKNOWNCMD_V(1U)
2473 #define PARITYERR_S 6
2474 #define PARITYERR_V(x) ((x) << PARITYERR_S)
2475 #define PARITYERR_F PARITYERR_V(1U)
2478 #define LIPMISS_V(x) ((x) << LIPMISS_S)
2479 #define LIPMISS_F LIPMISS_V(1U)
2482 #define LIP0_V(x) ((x) << LIP0_S)
2483 #define LIP0_F LIP0_V(1U)
2485 #define NCSI_INT_CAUSE_A 0x1a0d8
2487 #define CIM_DM_PRTY_ERR_S 8
2488 #define CIM_DM_PRTY_ERR_V(x) ((x) << CIM_DM_PRTY_ERR_S)
2489 #define CIM_DM_PRTY_ERR_F CIM_DM_PRTY_ERR_V(1U)
2491 #define MPS_DM_PRTY_ERR_S 7
2492 #define MPS_DM_PRTY_ERR_V(x) ((x) << MPS_DM_PRTY_ERR_S)
2493 #define MPS_DM_PRTY_ERR_F MPS_DM_PRTY_ERR_V(1U)
2495 #define TXFIFO_PRTY_ERR_S 1
2496 #define TXFIFO_PRTY_ERR_V(x) ((x) << TXFIFO_PRTY_ERR_S)
2497 #define TXFIFO_PRTY_ERR_F TXFIFO_PRTY_ERR_V(1U)
2499 #define RXFIFO_PRTY_ERR_S 0
2500 #define RXFIFO_PRTY_ERR_V(x) ((x) << RXFIFO_PRTY_ERR_S)
2501 #define RXFIFO_PRTY_ERR_F RXFIFO_PRTY_ERR_V(1U)
2503 #define XGMAC_PORT_CFG2_A 0x1018
2506 #define PATEN_V(x) ((x) << PATEN_S)
2507 #define PATEN_F PATEN_V(1U)
2509 #define MAGICEN_S 17
2510 #define MAGICEN_V(x) ((x) << MAGICEN_S)
2511 #define MAGICEN_F MAGICEN_V(1U)
2513 #define XGMAC_PORT_MAGIC_MACID_LO 0x1024
2514 #define XGMAC_PORT_MAGIC_MACID_HI 0x1028
2516 #define XGMAC_PORT_EPIO_DATA0_A 0x10c0
2517 #define XGMAC_PORT_EPIO_DATA1_A 0x10c4
2518 #define XGMAC_PORT_EPIO_DATA2_A 0x10c8
2519 #define XGMAC_PORT_EPIO_DATA3_A 0x10cc
2520 #define XGMAC_PORT_EPIO_OP_A 0x10d0
2523 #define EPIOWR_V(x) ((x) << EPIOWR_S)
2524 #define EPIOWR_F EPIOWR_V(1U)
2527 #define ADDRESS_V(x) ((x) << ADDRESS_S)
2529 #define MAC_PORT_INT_CAUSE_A 0x8dc
2530 #define XGMAC_PORT_INT_CAUSE_A 0x10dc
2532 #define TP_TX_MOD_QUEUE_REQ_MAP_A 0x7e28
2534 #define TP_TX_MOD_QUEUE_WEIGHT0_A 0x7e30
2535 #define TP_TX_MOD_CHANNEL_WEIGHT_A 0x7e34
2537 #define TX_MOD_QUEUE_REQ_MAP_S 0
2538 #define TX_MOD_QUEUE_REQ_MAP_V(x) ((x) << TX_MOD_QUEUE_REQ_MAP_S)
2540 #define TX_MODQ_WEIGHT3_S 24
2541 #define TX_MODQ_WEIGHT3_V(x) ((x) << TX_MODQ_WEIGHT3_S)
2543 #define TX_MODQ_WEIGHT2_S 16
2544 #define TX_MODQ_WEIGHT2_V(x) ((x) << TX_MODQ_WEIGHT2_S)
2546 #define TX_MODQ_WEIGHT1_S 8
2547 #define TX_MODQ_WEIGHT1_V(x) ((x) << TX_MODQ_WEIGHT1_S)
2549 #define TX_MODQ_WEIGHT0_S 0
2550 #define TX_MODQ_WEIGHT0_V(x) ((x) << TX_MODQ_WEIGHT0_S)
2552 #define TP_TX_SCHED_HDR_A 0x23
2553 #define TP_TX_SCHED_FIFO_A 0x24
2554 #define TP_TX_SCHED_PCMD_A 0x25
2556 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
2557 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
2559 #define T5_PORT0_BASE 0x30000
2560 #define T5_PORT_STRIDE 0x4000
2561 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
2562 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
2564 #define MC_0_BASE_ADDR 0x40000
2565 #define MC_1_BASE_ADDR 0x48000
2566 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
2567 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
2569 #define MC_P_BIST_CMD_A 0x41400
2570 #define MC_P_BIST_CMD_ADDR_A 0x41404
2571 #define MC_P_BIST_CMD_LEN_A 0x41408
2572 #define MC_P_BIST_DATA_PATTERN_A 0x4140c
2573 #define MC_P_BIST_STATUS_RDATA_A 0x41488
2575 #define EDC_T50_BASE_ADDR 0x50000
2577 #define EDC_H_BIST_CMD_A 0x50004
2578 #define EDC_H_BIST_CMD_ADDR_A 0x50008
2579 #define EDC_H_BIST_CMD_LEN_A 0x5000c
2580 #define EDC_H_BIST_DATA_PATTERN_A 0x50010
2581 #define EDC_H_BIST_STATUS_RDATA_A 0x50028
2583 #define EDC_T51_BASE_ADDR 0x50800
2585 #define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
2586 #define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
2588 #define PL_VF_REV_A 0x4
2589 #define PL_VF_WHOAMI_A 0x0
2590 #define PL_VF_REVISION_A 0x8
2592 /* registers for module CIM */
2593 #define CIM_HOST_ACC_CTRL_A 0x7b50
2594 #define CIM_HOST_ACC_DATA_A 0x7b54
2595 #define UP_UP_DBG_LA_CFG_A 0x140
2596 #define UP_UP_DBG_LA_DATA_A 0x144
2598 #define HOSTBUSY_S 17
2599 #define HOSTBUSY_V(x) ((x) << HOSTBUSY_S)
2600 #define HOSTBUSY_F HOSTBUSY_V(1U)
2602 #define HOSTWRITE_S 16
2603 #define HOSTWRITE_V(x) ((x) << HOSTWRITE_S)
2604 #define HOSTWRITE_F HOSTWRITE_V(1U)
2606 #define CIM_IBQ_DBG_CFG_A 0x7b60
2608 #define IBQDBGADDR_S 16
2609 #define IBQDBGADDR_M 0xfffU
2610 #define IBQDBGADDR_V(x) ((x) << IBQDBGADDR_S)
2611 #define IBQDBGADDR_G(x) (((x) >> IBQDBGADDR_S) & IBQDBGADDR_M)
2613 #define IBQDBGBUSY_S 1
2614 #define IBQDBGBUSY_V(x) ((x) << IBQDBGBUSY_S)
2615 #define IBQDBGBUSY_F IBQDBGBUSY_V(1U)
2617 #define IBQDBGEN_S 0
2618 #define IBQDBGEN_V(x) ((x) << IBQDBGEN_S)
2619 #define IBQDBGEN_F IBQDBGEN_V(1U)
2621 #define CIM_OBQ_DBG_CFG_A 0x7b64
2623 #define OBQDBGADDR_S 16
2624 #define OBQDBGADDR_M 0xfffU
2625 #define OBQDBGADDR_V(x) ((x) << OBQDBGADDR_S)
2626 #define OBQDBGADDR_G(x) (((x) >> OBQDBGADDR_S) & OBQDBGADDR_M)
2628 #define OBQDBGBUSY_S 1
2629 #define OBQDBGBUSY_V(x) ((x) << OBQDBGBUSY_S)
2630 #define OBQDBGBUSY_F OBQDBGBUSY_V(1U)
2632 #define OBQDBGEN_S 0
2633 #define OBQDBGEN_V(x) ((x) << OBQDBGEN_S)
2634 #define OBQDBGEN_F OBQDBGEN_V(1U)
2636 #define CIM_IBQ_DBG_DATA_A 0x7b68
2637 #define CIM_OBQ_DBG_DATA_A 0x7b6c
2639 #define UPDBGLARDEN_S 1
2640 #define UPDBGLARDEN_V(x) ((x) << UPDBGLARDEN_S)
2641 #define UPDBGLARDEN_F UPDBGLARDEN_V(1U)
2643 #define UPDBGLAEN_S 0
2644 #define UPDBGLAEN_V(x) ((x) << UPDBGLAEN_S)
2645 #define UPDBGLAEN_F UPDBGLAEN_V(1U)
2647 #define UPDBGLARDPTR_S 2
2648 #define UPDBGLARDPTR_M 0xfffU
2649 #define UPDBGLARDPTR_V(x) ((x) << UPDBGLARDPTR_S)
2651 #define UPDBGLAWRPTR_S 16
2652 #define UPDBGLAWRPTR_M 0xfffU
2653 #define UPDBGLAWRPTR_G(x) (((x) >> UPDBGLAWRPTR_S) & UPDBGLAWRPTR_M)
2655 #define UPDBGLACAPTPCONLY_S 30
2656 #define UPDBGLACAPTPCONLY_V(x) ((x) << UPDBGLACAPTPCONLY_S)
2657 #define UPDBGLACAPTPCONLY_F UPDBGLACAPTPCONLY_V(1U)
2659 #define CIM_QUEUE_CONFIG_REF_A 0x7b48
2660 #define CIM_QUEUE_CONFIG_CTRL_A 0x7b4c
2662 #define CIMQSIZE_S 24
2663 #define CIMQSIZE_M 0x3fU
2664 #define CIMQSIZE_G(x) (((x) >> CIMQSIZE_S) & CIMQSIZE_M)
2666 #define CIMQBASE_S 16
2667 #define CIMQBASE_M 0x3fU
2668 #define CIMQBASE_G(x) (((x) >> CIMQBASE_S) & CIMQBASE_M)
2670 #define QUEFULLTHRSH_S 0
2671 #define QUEFULLTHRSH_M 0x1ffU
2672 #define QUEFULLTHRSH_G(x) (((x) >> QUEFULLTHRSH_S) & QUEFULLTHRSH_M)
2674 #define UP_IBQ_0_RDADDR_A 0x10
2675 #define UP_IBQ_0_SHADOW_RDADDR_A 0x280
2676 #define UP_OBQ_0_REALADDR_A 0x104
2677 #define UP_OBQ_0_SHADOW_REALADDR_A 0x394
2679 #define IBQRDADDR_S 0
2680 #define IBQRDADDR_M 0x1fffU
2681 #define IBQRDADDR_G(x) (((x) >> IBQRDADDR_S) & IBQRDADDR_M)
2683 #define IBQWRADDR_S 0
2684 #define IBQWRADDR_M 0x1fffU
2685 #define IBQWRADDR_G(x) (((x) >> IBQWRADDR_S) & IBQWRADDR_M)
2687 #define QUERDADDR_S 0
2688 #define QUERDADDR_M 0x7fffU
2689 #define QUERDADDR_G(x) (((x) >> QUERDADDR_S) & QUERDADDR_M)
2691 #define QUEREMFLITS_S 0
2692 #define QUEREMFLITS_M 0x7ffU
2693 #define QUEREMFLITS_G(x) (((x) >> QUEREMFLITS_S) & QUEREMFLITS_M)
2695 #define QUEEOPCNT_S 16
2696 #define QUEEOPCNT_M 0xfffU
2697 #define QUEEOPCNT_G(x) (((x) >> QUEEOPCNT_S) & QUEEOPCNT_M)
2699 #define QUESOPCNT_S 0
2700 #define QUESOPCNT_M 0xfffU
2701 #define QUESOPCNT_G(x) (((x) >> QUESOPCNT_S) & QUESOPCNT_M)
2703 #define OBQSELECT_S 4
2704 #define OBQSELECT_V(x) ((x) << OBQSELECT_S)
2705 #define OBQSELECT_F OBQSELECT_V(1U)
2707 #define IBQSELECT_S 3
2708 #define IBQSELECT_V(x) ((x) << IBQSELECT_S)
2709 #define IBQSELECT_F IBQSELECT_V(1U)
2711 #define QUENUMSELECT_S 0
2712 #define QUENUMSELECT_V(x) ((x) << QUENUMSELECT_S)
2714 #endif /* __T4_REGS_H */
This page took 0.084794 seconds and 6 git commands to generate.