projects / deliverable / linux.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
cxgb4: Add support for devlog
[deliverable/linux.git] / drivers / net / ethernet / chelsio / cxgb4 / t4fw_api.h
1 /*
2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
3 *
4 * Copyright (c) 2009-2014 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #ifndef _T4FW_INTERFACE_H_
36 #define _T4FW_INTERFACE_H_
37
38 enum fw_retval {
39 FW_SUCCESS = 0, /* completed sucessfully */
40 FW_EPERM = 1, /* operation not permitted */
41 FW_ENOENT = 2, /* no such file or directory */
42 FW_EIO = 5, /* input/output error; hw bad */
43 FW_ENOEXEC = 8, /* exec format error; inv microcode */
44 FW_EAGAIN = 11, /* try again */
45 FW_ENOMEM = 12, /* out of memory */
46 FW_EFAULT = 14, /* bad address; fw bad */
47 FW_EBUSY = 16, /* resource busy */
48 FW_EEXIST = 17, /* file exists */
49 FW_ENODEV = 19, /* no such device */
50 FW_EINVAL = 22, /* invalid argument */
51 FW_ENOSPC = 28, /* no space left on device */
52 FW_ENOSYS = 38, /* functionality not implemented */
53 FW_ENODATA = 61, /* no data available */
54 FW_EPROTO = 71, /* protocol error */
55 FW_EADDRINUSE = 98, /* address already in use */
56 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */
57 FW_ENETDOWN = 100, /* network is down */
58 FW_ENETUNREACH = 101, /* network is unreachable */
59 FW_ENOBUFS = 105, /* no buffer space available */
60 FW_ETIMEDOUT = 110, /* timeout */
61 FW_EINPROGRESS = 115, /* fw internal */
62 FW_SCSI_ABORT_REQUESTED = 128, /* */
63 FW_SCSI_ABORT_TIMEDOUT = 129, /* */
64 FW_SCSI_ABORTED = 130, /* */
65 FW_SCSI_CLOSE_REQUESTED = 131, /* */
66 FW_ERR_LINK_DOWN = 132, /* */
67 FW_RDEV_NOT_READY = 133, /* */
68 FW_ERR_RDEV_LOST = 134, /* */
69 FW_ERR_RDEV_LOGO = 135, /* */
70 FW_FCOE_NO_XCHG = 136, /* */
71 FW_SCSI_RSP_ERR = 137, /* */
72 FW_ERR_RDEV_IMPL_LOGO = 138, /* */
73 FW_SCSI_UNDER_FLOW_ERR = 139, /* */
74 FW_SCSI_OVER_FLOW_ERR = 140, /* */
75 FW_SCSI_DDP_ERR = 141, /* DDP error*/
76 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */
77 };
78
79 #define FW_T4VF_SGE_BASE_ADDR 0x0000
80 #define FW_T4VF_MPS_BASE_ADDR 0x0100
81 #define FW_T4VF_PL_BASE_ADDR 0x0200
82 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240
83 #define FW_T4VF_CIM_BASE_ADDR 0x0300
84
85 enum fw_wr_opcodes {
86 FW_FILTER_WR = 0x02,
87 FW_ULPTX_WR = 0x04,
88 FW_TP_WR = 0x05,
89 FW_ETH_TX_PKT_WR = 0x08,
90 FW_OFLD_CONNECTION_WR = 0x2f,
91 FW_FLOWC_WR = 0x0a,
92 FW_OFLD_TX_DATA_WR = 0x0b,
93 FW_CMD_WR = 0x10,
94 FW_ETH_TX_PKT_VM_WR = 0x11,
95 FW_RI_RES_WR = 0x0c,
96 FW_RI_INIT_WR = 0x0d,
97 FW_RI_RDMA_WRITE_WR = 0x14,
98 FW_RI_SEND_WR = 0x15,
99 FW_RI_RDMA_READ_WR = 0x16,
100 FW_RI_RECV_WR = 0x17,
101 FW_RI_BIND_MW_WR = 0x18,
102 FW_RI_FR_NSMR_WR = 0x19,
103 FW_RI_INV_LSTAG_WR = 0x1a,
104 FW_LASTC2E_WR = 0x40
105 };
106
107 struct fw_wr_hdr {
108 __be32 hi;
109 __be32 lo;
110 };
111
112 /* work request opcode (hi) */
113 #define FW_WR_OP_S 24
114 #define FW_WR_OP_M 0xff
115 #define FW_WR_OP_V(x) ((x) << FW_WR_OP_S)
116 #define FW_WR_OP_G(x) (((x) >> FW_WR_OP_S) & FW_WR_OP_M)
117
118 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER */
119 #define FW_WR_ATOMIC_S 23
120 #define FW_WR_ATOMIC_V(x) ((x) << FW_WR_ATOMIC_S)
121
122 /* flush flag (hi) - firmware flushes flushable work request buffered
123 * in the flow context.
124 */
125 #define FW_WR_FLUSH_S 22
126 #define FW_WR_FLUSH_V(x) ((x) << FW_WR_FLUSH_S)
127
128 /* completion flag (hi) - firmware generates a cpl_fw6_ack */
129 #define FW_WR_COMPL_S 21
130 #define FW_WR_COMPL_V(x) ((x) << FW_WR_COMPL_S)
131 #define FW_WR_COMPL_F FW_WR_COMPL_V(1U)
132
133 /* work request immediate data length (hi) */
134 #define FW_WR_IMMDLEN_S 0
135 #define FW_WR_IMMDLEN_M 0xff
136 #define FW_WR_IMMDLEN_V(x) ((x) << FW_WR_IMMDLEN_S)
137
138 /* egress queue status update to associated ingress queue entry (lo) */
139 #define FW_WR_EQUIQ_S 31
140 #define FW_WR_EQUIQ_V(x) ((x) << FW_WR_EQUIQ_S)
141 #define FW_WR_EQUIQ_F FW_WR_EQUIQ_V(1U)
142
143 /* egress queue status update to egress queue status entry (lo) */
144 #define FW_WR_EQUEQ_S 30
145 #define FW_WR_EQUEQ_V(x) ((x) << FW_WR_EQUEQ_S)
146 #define FW_WR_EQUEQ_F FW_WR_EQUEQ_V(1U)
147
148 /* flow context identifier (lo) */
149 #define FW_WR_FLOWID_S 8
150 #define FW_WR_FLOWID_V(x) ((x) << FW_WR_FLOWID_S)
151
152 /* length in units of 16-bytes (lo) */
153 #define FW_WR_LEN16_S 0
154 #define FW_WR_LEN16_V(x) ((x) << FW_WR_LEN16_S)
155
156 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B
157 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327
158
159 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */
160 enum fw_filter_wr_cookie {
161 FW_FILTER_WR_SUCCESS,
162 FW_FILTER_WR_FLT_ADDED,
163 FW_FILTER_WR_FLT_DELETED,
164 FW_FILTER_WR_SMT_TBL_FULL,
165 FW_FILTER_WR_EINVAL,
166 };
167
168 struct fw_filter_wr {
169 __be32 op_pkd;
170 __be32 len16_pkd;
171 __be64 r3;
172 __be32 tid_to_iq;
173 __be32 del_filter_to_l2tix;
174 __be16 ethtype;
175 __be16 ethtypem;
176 __u8 frag_to_ovlan_vldm;
177 __u8 smac_sel;
178 __be16 rx_chan_rx_rpl_iq;
179 __be32 maci_to_matchtypem;
180 __u8 ptcl;
181 __u8 ptclm;
182 __u8 ttyp;
183 __u8 ttypm;
184 __be16 ivlan;
185 __be16 ivlanm;
186 __be16 ovlan;
187 __be16 ovlanm;
188 __u8 lip[16];
189 __u8 lipm[16];
190 __u8 fip[16];
191 __u8 fipm[16];
192 __be16 lp;
193 __be16 lpm;
194 __be16 fp;
195 __be16 fpm;
196 __be16 r7;
197 __u8 sma[6];
198 };
199
200 #define FW_FILTER_WR_TID_S 12
201 #define FW_FILTER_WR_TID_M 0xfffff
202 #define FW_FILTER_WR_TID_V(x) ((x) << FW_FILTER_WR_TID_S)
203 #define FW_FILTER_WR_TID_G(x) \
204 (((x) >> FW_FILTER_WR_TID_S) & FW_FILTER_WR_TID_M)
205
206 #define FW_FILTER_WR_RQTYPE_S 11
207 #define FW_FILTER_WR_RQTYPE_M 0x1
208 #define FW_FILTER_WR_RQTYPE_V(x) ((x) << FW_FILTER_WR_RQTYPE_S)
209 #define FW_FILTER_WR_RQTYPE_G(x) \
210 (((x) >> FW_FILTER_WR_RQTYPE_S) & FW_FILTER_WR_RQTYPE_M)
211 #define FW_FILTER_WR_RQTYPE_F FW_FILTER_WR_RQTYPE_V(1U)
212
213 #define FW_FILTER_WR_NOREPLY_S 10
214 #define FW_FILTER_WR_NOREPLY_M 0x1
215 #define FW_FILTER_WR_NOREPLY_V(x) ((x) << FW_FILTER_WR_NOREPLY_S)
216 #define FW_FILTER_WR_NOREPLY_G(x) \
217 (((x) >> FW_FILTER_WR_NOREPLY_S) & FW_FILTER_WR_NOREPLY_M)
218 #define FW_FILTER_WR_NOREPLY_F FW_FILTER_WR_NOREPLY_V(1U)
219
220 #define FW_FILTER_WR_IQ_S 0
221 #define FW_FILTER_WR_IQ_M 0x3ff
222 #define FW_FILTER_WR_IQ_V(x) ((x) << FW_FILTER_WR_IQ_S)
223 #define FW_FILTER_WR_IQ_G(x) \
224 (((x) >> FW_FILTER_WR_IQ_S) & FW_FILTER_WR_IQ_M)
225
226 #define FW_FILTER_WR_DEL_FILTER_S 31
227 #define FW_FILTER_WR_DEL_FILTER_M 0x1
228 #define FW_FILTER_WR_DEL_FILTER_V(x) ((x) << FW_FILTER_WR_DEL_FILTER_S)
229 #define FW_FILTER_WR_DEL_FILTER_G(x) \
230 (((x) >> FW_FILTER_WR_DEL_FILTER_S) & FW_FILTER_WR_DEL_FILTER_M)
231 #define FW_FILTER_WR_DEL_FILTER_F FW_FILTER_WR_DEL_FILTER_V(1U)
232
233 #define FW_FILTER_WR_RPTTID_S 25
234 #define FW_FILTER_WR_RPTTID_M 0x1
235 #define FW_FILTER_WR_RPTTID_V(x) ((x) << FW_FILTER_WR_RPTTID_S)
236 #define FW_FILTER_WR_RPTTID_G(x) \
237 (((x) >> FW_FILTER_WR_RPTTID_S) & FW_FILTER_WR_RPTTID_M)
238 #define FW_FILTER_WR_RPTTID_F FW_FILTER_WR_RPTTID_V(1U)
239
240 #define FW_FILTER_WR_DROP_S 24
241 #define FW_FILTER_WR_DROP_M 0x1
242 #define FW_FILTER_WR_DROP_V(x) ((x) << FW_FILTER_WR_DROP_S)
243 #define FW_FILTER_WR_DROP_G(x) \
244 (((x) >> FW_FILTER_WR_DROP_S) & FW_FILTER_WR_DROP_M)
245 #define FW_FILTER_WR_DROP_F FW_FILTER_WR_DROP_V(1U)
246
247 #define FW_FILTER_WR_DIRSTEER_S 23
248 #define FW_FILTER_WR_DIRSTEER_M 0x1
249 #define FW_FILTER_WR_DIRSTEER_V(x) ((x) << FW_FILTER_WR_DIRSTEER_S)
250 #define FW_FILTER_WR_DIRSTEER_G(x) \
251 (((x) >> FW_FILTER_WR_DIRSTEER_S) & FW_FILTER_WR_DIRSTEER_M)
252 #define FW_FILTER_WR_DIRSTEER_F FW_FILTER_WR_DIRSTEER_V(1U)
253
254 #define FW_FILTER_WR_MASKHASH_S 22
255 #define FW_FILTER_WR_MASKHASH_M 0x1
256 #define FW_FILTER_WR_MASKHASH_V(x) ((x) << FW_FILTER_WR_MASKHASH_S)
257 #define FW_FILTER_WR_MASKHASH_G(x) \
258 (((x) >> FW_FILTER_WR_MASKHASH_S) & FW_FILTER_WR_MASKHASH_M)
259 #define FW_FILTER_WR_MASKHASH_F FW_FILTER_WR_MASKHASH_V(1U)
260
261 #define FW_FILTER_WR_DIRSTEERHASH_S 21
262 #define FW_FILTER_WR_DIRSTEERHASH_M 0x1
263 #define FW_FILTER_WR_DIRSTEERHASH_V(x) ((x) << FW_FILTER_WR_DIRSTEERHASH_S)
264 #define FW_FILTER_WR_DIRSTEERHASH_G(x) \
265 (((x) >> FW_FILTER_WR_DIRSTEERHASH_S) & FW_FILTER_WR_DIRSTEERHASH_M)
266 #define FW_FILTER_WR_DIRSTEERHASH_F FW_FILTER_WR_DIRSTEERHASH_V(1U)
267
268 #define FW_FILTER_WR_LPBK_S 20
269 #define FW_FILTER_WR_LPBK_M 0x1
270 #define FW_FILTER_WR_LPBK_V(x) ((x) << FW_FILTER_WR_LPBK_S)
271 #define FW_FILTER_WR_LPBK_G(x) \
272 (((x) >> FW_FILTER_WR_LPBK_S) & FW_FILTER_WR_LPBK_M)
273 #define FW_FILTER_WR_LPBK_F FW_FILTER_WR_LPBK_V(1U)
274
275 #define FW_FILTER_WR_DMAC_S 19
276 #define FW_FILTER_WR_DMAC_M 0x1
277 #define FW_FILTER_WR_DMAC_V(x) ((x) << FW_FILTER_WR_DMAC_S)
278 #define FW_FILTER_WR_DMAC_G(x) \
279 (((x) >> FW_FILTER_WR_DMAC_S) & FW_FILTER_WR_DMAC_M)
280 #define FW_FILTER_WR_DMAC_F FW_FILTER_WR_DMAC_V(1U)
281
282 #define FW_FILTER_WR_SMAC_S 18
283 #define FW_FILTER_WR_SMAC_M 0x1
284 #define FW_FILTER_WR_SMAC_V(x) ((x) << FW_FILTER_WR_SMAC_S)
285 #define FW_FILTER_WR_SMAC_G(x) \
286 (((x) >> FW_FILTER_WR_SMAC_S) & FW_FILTER_WR_SMAC_M)
287 #define FW_FILTER_WR_SMAC_F FW_FILTER_WR_SMAC_V(1U)
288
289 #define FW_FILTER_WR_INSVLAN_S 17
290 #define FW_FILTER_WR_INSVLAN_M 0x1
291 #define FW_FILTER_WR_INSVLAN_V(x) ((x) << FW_FILTER_WR_INSVLAN_S)
292 #define FW_FILTER_WR_INSVLAN_G(x) \
293 (((x) >> FW_FILTER_WR_INSVLAN_S) & FW_FILTER_WR_INSVLAN_M)
294 #define FW_FILTER_WR_INSVLAN_F FW_FILTER_WR_INSVLAN_V(1U)
295
296 #define FW_FILTER_WR_RMVLAN_S 16
297 #define FW_FILTER_WR_RMVLAN_M 0x1
298 #define FW_FILTER_WR_RMVLAN_V(x) ((x) << FW_FILTER_WR_RMVLAN_S)
299 #define FW_FILTER_WR_RMVLAN_G(x) \
300 (((x) >> FW_FILTER_WR_RMVLAN_S) & FW_FILTER_WR_RMVLAN_M)
301 #define FW_FILTER_WR_RMVLAN_F FW_FILTER_WR_RMVLAN_V(1U)
302
303 #define FW_FILTER_WR_HITCNTS_S 15
304 #define FW_FILTER_WR_HITCNTS_M 0x1
305 #define FW_FILTER_WR_HITCNTS_V(x) ((x) << FW_FILTER_WR_HITCNTS_S)
306 #define FW_FILTER_WR_HITCNTS_G(x) \
307 (((x) >> FW_FILTER_WR_HITCNTS_S) & FW_FILTER_WR_HITCNTS_M)
308 #define FW_FILTER_WR_HITCNTS_F FW_FILTER_WR_HITCNTS_V(1U)
309
310 #define FW_FILTER_WR_TXCHAN_S 13
311 #define FW_FILTER_WR_TXCHAN_M 0x3
312 #define FW_FILTER_WR_TXCHAN_V(x) ((x) << FW_FILTER_WR_TXCHAN_S)
313 #define FW_FILTER_WR_TXCHAN_G(x) \
314 (((x) >> FW_FILTER_WR_TXCHAN_S) & FW_FILTER_WR_TXCHAN_M)
315
316 #define FW_FILTER_WR_PRIO_S 12
317 #define FW_FILTER_WR_PRIO_M 0x1
318 #define FW_FILTER_WR_PRIO_V(x) ((x) << FW_FILTER_WR_PRIO_S)
319 #define FW_FILTER_WR_PRIO_G(x) \
320 (((x) >> FW_FILTER_WR_PRIO_S) & FW_FILTER_WR_PRIO_M)
321 #define FW_FILTER_WR_PRIO_F FW_FILTER_WR_PRIO_V(1U)
322
323 #define FW_FILTER_WR_L2TIX_S 0
324 #define FW_FILTER_WR_L2TIX_M 0xfff
325 #define FW_FILTER_WR_L2TIX_V(x) ((x) << FW_FILTER_WR_L2TIX_S)
326 #define FW_FILTER_WR_L2TIX_G(x) \
327 (((x) >> FW_FILTER_WR_L2TIX_S) & FW_FILTER_WR_L2TIX_M)
328
329 #define FW_FILTER_WR_FRAG_S 7
330 #define FW_FILTER_WR_FRAG_M 0x1
331 #define FW_FILTER_WR_FRAG_V(x) ((x) << FW_FILTER_WR_FRAG_S)
332 #define FW_FILTER_WR_FRAG_G(x) \
333 (((x) >> FW_FILTER_WR_FRAG_S) & FW_FILTER_WR_FRAG_M)
334 #define FW_FILTER_WR_FRAG_F FW_FILTER_WR_FRAG_V(1U)
335
336 #define FW_FILTER_WR_FRAGM_S 6
337 #define FW_FILTER_WR_FRAGM_M 0x1
338 #define FW_FILTER_WR_FRAGM_V(x) ((x) << FW_FILTER_WR_FRAGM_S)
339 #define FW_FILTER_WR_FRAGM_G(x) \
340 (((x) >> FW_FILTER_WR_FRAGM_S) & FW_FILTER_WR_FRAGM_M)
341 #define FW_FILTER_WR_FRAGM_F FW_FILTER_WR_FRAGM_V(1U)
342
343 #define FW_FILTER_WR_IVLAN_VLD_S 5
344 #define FW_FILTER_WR_IVLAN_VLD_M 0x1
345 #define FW_FILTER_WR_IVLAN_VLD_V(x) ((x) << FW_FILTER_WR_IVLAN_VLD_S)
346 #define FW_FILTER_WR_IVLAN_VLD_G(x) \
347 (((x) >> FW_FILTER_WR_IVLAN_VLD_S) & FW_FILTER_WR_IVLAN_VLD_M)
348 #define FW_FILTER_WR_IVLAN_VLD_F FW_FILTER_WR_IVLAN_VLD_V(1U)
349
350 #define FW_FILTER_WR_OVLAN_VLD_S 4
351 #define FW_FILTER_WR_OVLAN_VLD_M 0x1
352 #define FW_FILTER_WR_OVLAN_VLD_V(x) ((x) << FW_FILTER_WR_OVLAN_VLD_S)
353 #define FW_FILTER_WR_OVLAN_VLD_G(x) \
354 (((x) >> FW_FILTER_WR_OVLAN_VLD_S) & FW_FILTER_WR_OVLAN_VLD_M)
355 #define FW_FILTER_WR_OVLAN_VLD_F FW_FILTER_WR_OVLAN_VLD_V(1U)
356
357 #define FW_FILTER_WR_IVLAN_VLDM_S 3
358 #define FW_FILTER_WR_IVLAN_VLDM_M 0x1
359 #define FW_FILTER_WR_IVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_IVLAN_VLDM_S)
360 #define FW_FILTER_WR_IVLAN_VLDM_G(x) \
361 (((x) >> FW_FILTER_WR_IVLAN_VLDM_S) & FW_FILTER_WR_IVLAN_VLDM_M)
362 #define FW_FILTER_WR_IVLAN_VLDM_F FW_FILTER_WR_IVLAN_VLDM_V(1U)
363
364 #define FW_FILTER_WR_OVLAN_VLDM_S 2
365 #define FW_FILTER_WR_OVLAN_VLDM_M 0x1
366 #define FW_FILTER_WR_OVLAN_VLDM_V(x) ((x) << FW_FILTER_WR_OVLAN_VLDM_S)
367 #define FW_FILTER_WR_OVLAN_VLDM_G(x) \
368 (((x) >> FW_FILTER_WR_OVLAN_VLDM_S) & FW_FILTER_WR_OVLAN_VLDM_M)
369 #define FW_FILTER_WR_OVLAN_VLDM_F FW_FILTER_WR_OVLAN_VLDM_V(1U)
370
371 #define FW_FILTER_WR_RX_CHAN_S 15
372 #define FW_FILTER_WR_RX_CHAN_M 0x1
373 #define FW_FILTER_WR_RX_CHAN_V(x) ((x) << FW_FILTER_WR_RX_CHAN_S)
374 #define FW_FILTER_WR_RX_CHAN_G(x) \
375 (((x) >> FW_FILTER_WR_RX_CHAN_S) & FW_FILTER_WR_RX_CHAN_M)
376 #define FW_FILTER_WR_RX_CHAN_F FW_FILTER_WR_RX_CHAN_V(1U)
377
378 #define FW_FILTER_WR_RX_RPL_IQ_S 0
379 #define FW_FILTER_WR_RX_RPL_IQ_M 0x3ff
380 #define FW_FILTER_WR_RX_RPL_IQ_V(x) ((x) << FW_FILTER_WR_RX_RPL_IQ_S)
381 #define FW_FILTER_WR_RX_RPL_IQ_G(x) \
382 (((x) >> FW_FILTER_WR_RX_RPL_IQ_S) & FW_FILTER_WR_RX_RPL_IQ_M)
383
384 #define FW_FILTER_WR_MACI_S 23
385 #define FW_FILTER_WR_MACI_M 0x1ff
386 #define FW_FILTER_WR_MACI_V(x) ((x) << FW_FILTER_WR_MACI_S)
387 #define FW_FILTER_WR_MACI_G(x) \
388 (((x) >> FW_FILTER_WR_MACI_S) & FW_FILTER_WR_MACI_M)
389
390 #define FW_FILTER_WR_MACIM_S 14
391 #define FW_FILTER_WR_MACIM_M 0x1ff
392 #define FW_FILTER_WR_MACIM_V(x) ((x) << FW_FILTER_WR_MACIM_S)
393 #define FW_FILTER_WR_MACIM_G(x) \
394 (((x) >> FW_FILTER_WR_MACIM_S) & FW_FILTER_WR_MACIM_M)
395
396 #define FW_FILTER_WR_FCOE_S 13
397 #define FW_FILTER_WR_FCOE_M 0x1
398 #define FW_FILTER_WR_FCOE_V(x) ((x) << FW_FILTER_WR_FCOE_S)
399 #define FW_FILTER_WR_FCOE_G(x) \
400 (((x) >> FW_FILTER_WR_FCOE_S) & FW_FILTER_WR_FCOE_M)
401 #define FW_FILTER_WR_FCOE_F FW_FILTER_WR_FCOE_V(1U)
402
403 #define FW_FILTER_WR_FCOEM_S 12
404 #define FW_FILTER_WR_FCOEM_M 0x1
405 #define FW_FILTER_WR_FCOEM_V(x) ((x) << FW_FILTER_WR_FCOEM_S)
406 #define FW_FILTER_WR_FCOEM_G(x) \
407 (((x) >> FW_FILTER_WR_FCOEM_S) & FW_FILTER_WR_FCOEM_M)
408 #define FW_FILTER_WR_FCOEM_F FW_FILTER_WR_FCOEM_V(1U)
409
410 #define FW_FILTER_WR_PORT_S 9
411 #define FW_FILTER_WR_PORT_M 0x7
412 #define FW_FILTER_WR_PORT_V(x) ((x) << FW_FILTER_WR_PORT_S)
413 #define FW_FILTER_WR_PORT_G(x) \
414 (((x) >> FW_FILTER_WR_PORT_S) & FW_FILTER_WR_PORT_M)
415
416 #define FW_FILTER_WR_PORTM_S 6
417 #define FW_FILTER_WR_PORTM_M 0x7
418 #define FW_FILTER_WR_PORTM_V(x) ((x) << FW_FILTER_WR_PORTM_S)
419 #define FW_FILTER_WR_PORTM_G(x) \
420 (((x) >> FW_FILTER_WR_PORTM_S) & FW_FILTER_WR_PORTM_M)
421
422 #define FW_FILTER_WR_MATCHTYPE_S 3
423 #define FW_FILTER_WR_MATCHTYPE_M 0x7
424 #define FW_FILTER_WR_MATCHTYPE_V(x) ((x) << FW_FILTER_WR_MATCHTYPE_S)
425 #define FW_FILTER_WR_MATCHTYPE_G(x) \
426 (((x) >> FW_FILTER_WR_MATCHTYPE_S) & FW_FILTER_WR_MATCHTYPE_M)
427
428 #define FW_FILTER_WR_MATCHTYPEM_S 0
429 #define FW_FILTER_WR_MATCHTYPEM_M 0x7
430 #define FW_FILTER_WR_MATCHTYPEM_V(x) ((x) << FW_FILTER_WR_MATCHTYPEM_S)
431 #define FW_FILTER_WR_MATCHTYPEM_G(x) \
432 (((x) >> FW_FILTER_WR_MATCHTYPEM_S) & FW_FILTER_WR_MATCHTYPEM_M)
433
434 struct fw_ulptx_wr {
435 __be32 op_to_compl;
436 __be32 flowid_len16;
437 u64 cookie;
438 };
439
440 struct fw_tp_wr {
441 __be32 op_to_immdlen;
442 __be32 flowid_len16;
443 u64 cookie;
444 };
445
446 struct fw_eth_tx_pkt_wr {
447 __be32 op_immdlen;
448 __be32 equiq_to_len16;
449 __be64 r3;
450 };
451
452 struct fw_ofld_connection_wr {
453 __be32 op_compl;
454 __be32 len16_pkd;
455 __u64 cookie;
456 __be64 r2;
457 __be64 r3;
458 struct fw_ofld_connection_le {
459 __be32 version_cpl;
460 __be32 filter;
461 __be32 r1;
462 __be16 lport;
463 __be16 pport;
464 union fw_ofld_connection_leip {
465 struct fw_ofld_connection_le_ipv4 {
466 __be32 pip;
467 __be32 lip;
468 __be64 r0;
469 __be64 r1;
470 __be64 r2;
471 } ipv4;
472 struct fw_ofld_connection_le_ipv6 {
473 __be64 pip_hi;
474 __be64 pip_lo;
475 __be64 lip_hi;
476 __be64 lip_lo;
477 } ipv6;
478 } u;
479 } le;
480 struct fw_ofld_connection_tcb {
481 __be32 t_state_to_astid;
482 __be16 cplrxdataack_cplpassacceptrpl;
483 __be16 rcv_adv;
484 __be32 rcv_nxt;
485 __be32 tx_max;
486 __be64 opt0;
487 __be32 opt2;
488 __be32 r1;
489 __be64 r2;
490 __be64 r3;
491 } tcb;
492 };
493
494 #define FW_OFLD_CONNECTION_WR_VERSION_S 31
495 #define FW_OFLD_CONNECTION_WR_VERSION_M 0x1
496 #define FW_OFLD_CONNECTION_WR_VERSION_V(x) \
497 ((x) << FW_OFLD_CONNECTION_WR_VERSION_S)
498 #define FW_OFLD_CONNECTION_WR_VERSION_G(x) \
499 (((x) >> FW_OFLD_CONNECTION_WR_VERSION_S) & \
500 FW_OFLD_CONNECTION_WR_VERSION_M)
501 #define FW_OFLD_CONNECTION_WR_VERSION_F \
502 FW_OFLD_CONNECTION_WR_VERSION_V(1U)
503
504 #define FW_OFLD_CONNECTION_WR_CPL_S 30
505 #define FW_OFLD_CONNECTION_WR_CPL_M 0x1
506 #define FW_OFLD_CONNECTION_WR_CPL_V(x) ((x) << FW_OFLD_CONNECTION_WR_CPL_S)
507 #define FW_OFLD_CONNECTION_WR_CPL_G(x) \
508 (((x) >> FW_OFLD_CONNECTION_WR_CPL_S) & FW_OFLD_CONNECTION_WR_CPL_M)
509 #define FW_OFLD_CONNECTION_WR_CPL_F FW_OFLD_CONNECTION_WR_CPL_V(1U)
510
511 #define FW_OFLD_CONNECTION_WR_T_STATE_S 28
512 #define FW_OFLD_CONNECTION_WR_T_STATE_M 0xf
513 #define FW_OFLD_CONNECTION_WR_T_STATE_V(x) \
514 ((x) << FW_OFLD_CONNECTION_WR_T_STATE_S)
515 #define FW_OFLD_CONNECTION_WR_T_STATE_G(x) \
516 (((x) >> FW_OFLD_CONNECTION_WR_T_STATE_S) & \
517 FW_OFLD_CONNECTION_WR_T_STATE_M)
518
519 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_S 24
520 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_M 0xf
521 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_V(x) \
522 ((x) << FW_OFLD_CONNECTION_WR_RCV_SCALE_S)
523 #define FW_OFLD_CONNECTION_WR_RCV_SCALE_G(x) \
524 (((x) >> FW_OFLD_CONNECTION_WR_RCV_SCALE_S) & \
525 FW_OFLD_CONNECTION_WR_RCV_SCALE_M)
526
527 #define FW_OFLD_CONNECTION_WR_ASTID_S 0
528 #define FW_OFLD_CONNECTION_WR_ASTID_M 0xffffff
529 #define FW_OFLD_CONNECTION_WR_ASTID_V(x) \
530 ((x) << FW_OFLD_CONNECTION_WR_ASTID_S)
531 #define FW_OFLD_CONNECTION_WR_ASTID_G(x) \
532 (((x) >> FW_OFLD_CONNECTION_WR_ASTID_S) & FW_OFLD_CONNECTION_WR_ASTID_M)
533
534 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S 15
535 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M 0x1
536 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(x) \
537 ((x) << FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S)
538 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_G(x) \
539 (((x) >> FW_OFLD_CONNECTION_WR_CPLRXDATAACK_S) & \
540 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_M)
541 #define FW_OFLD_CONNECTION_WR_CPLRXDATAACK_F \
542 FW_OFLD_CONNECTION_WR_CPLRXDATAACK_V(1U)
543
544 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S 14
545 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M 0x1
546 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(x) \
547 ((x) << FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S)
548 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_G(x) \
549 (((x) >> FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_S) & \
550 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_M)
551 #define FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_F \
552 FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL_V(1U)
553
554 enum fw_flowc_mnem {
555 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */
556 FW_FLOWC_MNEM_CH,
557 FW_FLOWC_MNEM_PORT,
558 FW_FLOWC_MNEM_IQID,
559 FW_FLOWC_MNEM_SNDNXT,
560 FW_FLOWC_MNEM_RCVNXT,
561 FW_FLOWC_MNEM_SNDBUF,
562 FW_FLOWC_MNEM_MSS,
563 FW_FLOWC_MNEM_TXDATAPLEN_MAX,
564 };
565
566 struct fw_flowc_mnemval {
567 u8 mnemonic;
568 u8 r4[3];
569 __be32 val;
570 };
571
572 struct fw_flowc_wr {
573 __be32 op_to_nparams;
574 __be32 flowid_len16;
575 struct fw_flowc_mnemval mnemval[0];
576 };
577
578 #define FW_FLOWC_WR_NPARAMS_S 0
579 #define FW_FLOWC_WR_NPARAMS_V(x) ((x) << FW_FLOWC_WR_NPARAMS_S)
580
581 struct fw_ofld_tx_data_wr {
582 __be32 op_to_immdlen;
583 __be32 flowid_len16;
584 __be32 plen;
585 __be32 tunnel_to_proxy;
586 };
587
588 #define FW_OFLD_TX_DATA_WR_TUNNEL_S 19
589 #define FW_OFLD_TX_DATA_WR_TUNNEL_V(x) ((x) << FW_OFLD_TX_DATA_WR_TUNNEL_S)
590
591 #define FW_OFLD_TX_DATA_WR_SAVE_S 18
592 #define FW_OFLD_TX_DATA_WR_SAVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SAVE_S)
593
594 #define FW_OFLD_TX_DATA_WR_FLUSH_S 17
595 #define FW_OFLD_TX_DATA_WR_FLUSH_V(x) ((x) << FW_OFLD_TX_DATA_WR_FLUSH_S)
596 #define FW_OFLD_TX_DATA_WR_FLUSH_F FW_OFLD_TX_DATA_WR_FLUSH_V(1U)
597
598 #define FW_OFLD_TX_DATA_WR_URGENT_S 16
599 #define FW_OFLD_TX_DATA_WR_URGENT_V(x) ((x) << FW_OFLD_TX_DATA_WR_URGENT_S)
600
601 #define FW_OFLD_TX_DATA_WR_MORE_S 15
602 #define FW_OFLD_TX_DATA_WR_MORE_V(x) ((x) << FW_OFLD_TX_DATA_WR_MORE_S)
603
604 #define FW_OFLD_TX_DATA_WR_SHOVE_S 14
605 #define FW_OFLD_TX_DATA_WR_SHOVE_V(x) ((x) << FW_OFLD_TX_DATA_WR_SHOVE_S)
606 #define FW_OFLD_TX_DATA_WR_SHOVE_F FW_OFLD_TX_DATA_WR_SHOVE_V(1U)
607
608 #define FW_OFLD_TX_DATA_WR_ULPMODE_S 10
609 #define FW_OFLD_TX_DATA_WR_ULPMODE_V(x) ((x) << FW_OFLD_TX_DATA_WR_ULPMODE_S)
610
611 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_S 6
612 #define FW_OFLD_TX_DATA_WR_ULPSUBMODE_V(x) \
613 ((x) << FW_OFLD_TX_DATA_WR_ULPSUBMODE_S)
614
615 struct fw_cmd_wr {
616 __be32 op_dma;
617 __be32 len16_pkd;
618 __be64 cookie_daddr;
619 };
620
621 #define FW_CMD_WR_DMA_S 17
622 #define FW_CMD_WR_DMA_V(x) ((x) << FW_CMD_WR_DMA_S)
623
624 struct fw_eth_tx_pkt_vm_wr {
625 __be32 op_immdlen;
626 __be32 equiq_to_len16;
627 __be32 r3[2];
628 u8 ethmacdst[6];
629 u8 ethmacsrc[6];
630 __be16 ethtype;
631 __be16 vlantci;
632 };
633
634 #define FW_CMD_MAX_TIMEOUT 10000
635
636 /*
637 * If a host driver does a HELLO and discovers that there's already a MASTER
638 * selected, we may have to wait for that MASTER to finish issuing RESET,
639 * configuration and INITIALIZE commands. Also, there's a possibility that
640 * our own HELLO may get lost if it happens right as the MASTER is issuign a
641 * RESET command, so we need to be willing to make a few retries of our HELLO.
642 */
643 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT)
644 #define FW_CMD_HELLO_RETRIES 3
645
646
647 enum fw_cmd_opcodes {
648 FW_LDST_CMD = 0x01,
649 FW_RESET_CMD = 0x03,
650 FW_HELLO_CMD = 0x04,
651 FW_BYE_CMD = 0x05,
652 FW_INITIALIZE_CMD = 0x06,
653 FW_CAPS_CONFIG_CMD = 0x07,
654 FW_PARAMS_CMD = 0x08,
655 FW_PFVF_CMD = 0x09,
656 FW_IQ_CMD = 0x10,
657 FW_EQ_MNGT_CMD = 0x11,
658 FW_EQ_ETH_CMD = 0x12,
659 FW_EQ_CTRL_CMD = 0x13,
660 FW_EQ_OFLD_CMD = 0x21,
661 FW_VI_CMD = 0x14,
662 FW_VI_MAC_CMD = 0x15,
663 FW_VI_RXMODE_CMD = 0x16,
664 FW_VI_ENABLE_CMD = 0x17,
665 FW_ACL_MAC_CMD = 0x18,
666 FW_ACL_VLAN_CMD = 0x19,
667 FW_VI_STATS_CMD = 0x1a,
668 FW_PORT_CMD = 0x1b,
669 FW_PORT_STATS_CMD = 0x1c,
670 FW_PORT_LB_STATS_CMD = 0x1d,
671 FW_PORT_TRACE_CMD = 0x1e,
672 FW_PORT_TRACE_MMAP_CMD = 0x1f,
673 FW_RSS_IND_TBL_CMD = 0x20,
674 FW_RSS_GLB_CONFIG_CMD = 0x22,
675 FW_RSS_VI_CONFIG_CMD = 0x23,
676 FW_DEVLOG_CMD = 0x25,
677 FW_CLIP_CMD = 0x28,
678 FW_LASTC2E_CMD = 0x40,
679 FW_ERROR_CMD = 0x80,
680 FW_DEBUG_CMD = 0x81,
681 };
682
683 enum fw_cmd_cap {
684 FW_CMD_CAP_PF = 0x01,
685 FW_CMD_CAP_DMAQ = 0x02,
686 FW_CMD_CAP_PORT = 0x04,
687 FW_CMD_CAP_PORTPROMISC = 0x08,
688 FW_CMD_CAP_PORTSTATS = 0x10,
689 FW_CMD_CAP_VF = 0x80,
690 };
691
692 /*
693 * Generic command header flit0
694 */
695 struct fw_cmd_hdr {
696 __be32 hi;
697 __be32 lo;
698 };
699
700 #define FW_CMD_OP_S 24
701 #define FW_CMD_OP_M 0xff
702 #define FW_CMD_OP_V(x) ((x) << FW_CMD_OP_S)
703 #define FW_CMD_OP_G(x) (((x) >> FW_CMD_OP_S) & FW_CMD_OP_M)
704
705 #define FW_CMD_REQUEST_S 23
706 #define FW_CMD_REQUEST_V(x) ((x) << FW_CMD_REQUEST_S)
707 #define FW_CMD_REQUEST_F FW_CMD_REQUEST_V(1U)
708
709 #define FW_CMD_READ_S 22
710 #define FW_CMD_READ_V(x) ((x) << FW_CMD_READ_S)
711 #define FW_CMD_READ_F FW_CMD_READ_V(1U)
712
713 #define FW_CMD_WRITE_S 21
714 #define FW_CMD_WRITE_V(x) ((x) << FW_CMD_WRITE_S)
715 #define FW_CMD_WRITE_F FW_CMD_WRITE_V(1U)
716
717 #define FW_CMD_EXEC_S 20
718 #define FW_CMD_EXEC_V(x) ((x) << FW_CMD_EXEC_S)
719 #define FW_CMD_EXEC_F FW_CMD_EXEC_V(1U)
720
721 #define FW_CMD_RAMASK_S 20
722 #define FW_CMD_RAMASK_V(x) ((x) << FW_CMD_RAMASK_S)
723
724 #define FW_CMD_RETVAL_S 8
725 #define FW_CMD_RETVAL_M 0xff
726 #define FW_CMD_RETVAL_V(x) ((x) << FW_CMD_RETVAL_S)
727 #define FW_CMD_RETVAL_G(x) (((x) >> FW_CMD_RETVAL_S) & FW_CMD_RETVAL_M)
728
729 #define FW_CMD_LEN16_S 0
730 #define FW_CMD_LEN16_V(x) ((x) << FW_CMD_LEN16_S)
731
732 #define FW_LEN16(fw_struct) FW_CMD_LEN16_V(sizeof(fw_struct) / 16)
733
734 enum fw_ldst_addrspc {
735 FW_LDST_ADDRSPC_FIRMWARE = 0x0001,
736 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008,
737 FW_LDST_ADDRSPC_SGE_INGC = 0x0009,
738 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a,
739 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b,
740 FW_LDST_ADDRSPC_TP_PIO = 0x0010,
741 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011,
742 FW_LDST_ADDRSPC_TP_MIB = 0x0012,
743 FW_LDST_ADDRSPC_MDIO = 0x0018,
744 FW_LDST_ADDRSPC_MPS = 0x0020,
745 FW_LDST_ADDRSPC_FUNC = 0x0028,
746 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029,
747 };
748
749 enum fw_ldst_mps_fid {
750 FW_LDST_MPS_ATRB,
751 FW_LDST_MPS_RPLC
752 };
753
754 enum fw_ldst_func_access_ctl {
755 FW_LDST_FUNC_ACC_CTL_VIID,
756 FW_LDST_FUNC_ACC_CTL_FID
757 };
758
759 enum fw_ldst_func_mod_index {
760 FW_LDST_FUNC_MPS
761 };
762
763 struct fw_ldst_cmd {
764 __be32 op_to_addrspace;
765 #define FW_LDST_CMD_ADDRSPACE_S 0
766 #define FW_LDST_CMD_ADDRSPACE_V(x) ((x) << FW_LDST_CMD_ADDRSPACE_S)
767 __be32 cycles_to_len16;
768 union fw_ldst {
769 struct fw_ldst_addrval {
770 __be32 addr;
771 __be32 val;
772 } addrval;
773 struct fw_ldst_idctxt {
774 __be32 physid;
775 __be32 msg_pkd;
776 __be32 ctxt_data7;
777 __be32 ctxt_data6;
778 __be32 ctxt_data5;
779 __be32 ctxt_data4;
780 __be32 ctxt_data3;
781 __be32 ctxt_data2;
782 __be32 ctxt_data1;
783 __be32 ctxt_data0;
784 } idctxt;
785 struct fw_ldst_mdio {
786 __be16 paddr_mmd;
787 __be16 raddr;
788 __be16 vctl;
789 __be16 rval;
790 } mdio;
791 struct fw_ldst_mps {
792 __be16 fid_ctl;
793 __be16 rplcpf_pkd;
794 __be32 rplc127_96;
795 __be32 rplc95_64;
796 __be32 rplc63_32;
797 __be32 rplc31_0;
798 __be32 atrb;
799 __be16 vlan[16];
800 } mps;
801 struct fw_ldst_func {
802 u8 access_ctl;
803 u8 mod_index;
804 __be16 ctl_id;
805 __be32 offset;
806 __be64 data0;
807 __be64 data1;
808 } func;
809 struct fw_ldst_pcie {
810 u8 ctrl_to_fn;
811 u8 bnum;
812 u8 r;
813 u8 ext_r;
814 u8 select_naccess;
815 u8 pcie_fn;
816 __be16 nset_pkd;
817 __be32 data[12];
818 } pcie;
819 } u;
820 };
821
822 #define FW_LDST_CMD_MSG_S 31
823 #define FW_LDST_CMD_MSG_V(x) ((x) << FW_LDST_CMD_MSG_S)
824
825 #define FW_LDST_CMD_PADDR_S 8
826 #define FW_LDST_CMD_PADDR_V(x) ((x) << FW_LDST_CMD_PADDR_S)
827
828 #define FW_LDST_CMD_MMD_S 0
829 #define FW_LDST_CMD_MMD_V(x) ((x) << FW_LDST_CMD_MMD_S)
830
831 #define FW_LDST_CMD_FID_S 15
832 #define FW_LDST_CMD_FID_V(x) ((x) << FW_LDST_CMD_FID_S)
833
834 #define FW_LDST_CMD_CTL_S 0
835 #define FW_LDST_CMD_CTL_V(x) ((x) << FW_LDST_CMD_CTL_S)
836
837 #define FW_LDST_CMD_RPLCPF_S 0
838 #define FW_LDST_CMD_RPLCPF_V(x) ((x) << FW_LDST_CMD_RPLCPF_S)
839
840 #define FW_LDST_CMD_LC_S 4
841 #define FW_LDST_CMD_LC_V(x) ((x) << FW_LDST_CMD_LC_S)
842 #define FW_LDST_CMD_LC_F FW_LDST_CMD_LC_V(1U)
843
844 #define FW_LDST_CMD_FN_S 0
845 #define FW_LDST_CMD_FN_V(x) ((x) << FW_LDST_CMD_FN_S)
846
847 #define FW_LDST_CMD_NACCESS_S 0
848 #define FW_LDST_CMD_NACCESS_V(x) ((x) << FW_LDST_CMD_NACCESS_S)
849
850 struct fw_reset_cmd {
851 __be32 op_to_write;
852 __be32 retval_len16;
853 __be32 val;
854 __be32 halt_pkd;
855 };
856
857 #define FW_RESET_CMD_HALT_S 31
858 #define FW_RESET_CMD_HALT_M 0x1
859 #define FW_RESET_CMD_HALT_V(x) ((x) << FW_RESET_CMD_HALT_S)
860 #define FW_RESET_CMD_HALT_G(x) \
861 (((x) >> FW_RESET_CMD_HALT_S) & FW_RESET_CMD_HALT_M)
862 #define FW_RESET_CMD_HALT_F FW_RESET_CMD_HALT_V(1U)
863
864 enum fw_hellow_cmd {
865 fw_hello_cmd_stage_os = 0x0
866 };
867
868 struct fw_hello_cmd {
869 __be32 op_to_write;
870 __be32 retval_len16;
871 __be32 err_to_clearinit;
872 __be32 fwrev;
873 };
874
875 #define FW_HELLO_CMD_ERR_S 31
876 #define FW_HELLO_CMD_ERR_V(x) ((x) << FW_HELLO_CMD_ERR_S)
877 #define FW_HELLO_CMD_ERR_F FW_HELLO_CMD_ERR_V(1U)
878
879 #define FW_HELLO_CMD_INIT_S 30
880 #define FW_HELLO_CMD_INIT_V(x) ((x) << FW_HELLO_CMD_INIT_S)
881 #define FW_HELLO_CMD_INIT_F FW_HELLO_CMD_INIT_V(1U)
882
883 #define FW_HELLO_CMD_MASTERDIS_S 29
884 #define FW_HELLO_CMD_MASTERDIS_V(x) ((x) << FW_HELLO_CMD_MASTERDIS_S)
885
886 #define FW_HELLO_CMD_MASTERFORCE_S 28
887 #define FW_HELLO_CMD_MASTERFORCE_V(x) ((x) << FW_HELLO_CMD_MASTERFORCE_S)
888
889 #define FW_HELLO_CMD_MBMASTER_S 24
890 #define FW_HELLO_CMD_MBMASTER_M 0xfU
891 #define FW_HELLO_CMD_MBMASTER_V(x) ((x) << FW_HELLO_CMD_MBMASTER_S)
892 #define FW_HELLO_CMD_MBMASTER_G(x) \
893 (((x) >> FW_HELLO_CMD_MBMASTER_S) & FW_HELLO_CMD_MBMASTER_M)
894
895 #define FW_HELLO_CMD_MBASYNCNOTINT_S 23
896 #define FW_HELLO_CMD_MBASYNCNOTINT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOTINT_S)
897
898 #define FW_HELLO_CMD_MBASYNCNOT_S 20
899 #define FW_HELLO_CMD_MBASYNCNOT_V(x) ((x) << FW_HELLO_CMD_MBASYNCNOT_S)
900
901 #define FW_HELLO_CMD_STAGE_S 17
902 #define FW_HELLO_CMD_STAGE_V(x) ((x) << FW_HELLO_CMD_STAGE_S)
903
904 #define FW_HELLO_CMD_CLEARINIT_S 16
905 #define FW_HELLO_CMD_CLEARINIT_V(x) ((x) << FW_HELLO_CMD_CLEARINIT_S)
906 #define FW_HELLO_CMD_CLEARINIT_F FW_HELLO_CMD_CLEARINIT_V(1U)
907
908 struct fw_bye_cmd {
909 __be32 op_to_write;
910 __be32 retval_len16;
911 __be64 r3;
912 };
913
914 struct fw_initialize_cmd {
915 __be32 op_to_write;
916 __be32 retval_len16;
917 __be64 r3;
918 };
919
920 enum fw_caps_config_hm {
921 FW_CAPS_CONFIG_HM_PCIE = 0x00000001,
922 FW_CAPS_CONFIG_HM_PL = 0x00000002,
923 FW_CAPS_CONFIG_HM_SGE = 0x00000004,
924 FW_CAPS_CONFIG_HM_CIM = 0x00000008,
925 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010,
926 FW_CAPS_CONFIG_HM_TP = 0x00000020,
927 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040,
928 FW_CAPS_CONFIG_HM_PMRX = 0x00000080,
929 FW_CAPS_CONFIG_HM_PMTX = 0x00000100,
930 FW_CAPS_CONFIG_HM_MC = 0x00000200,
931 FW_CAPS_CONFIG_HM_LE = 0x00000400,
932 FW_CAPS_CONFIG_HM_MPS = 0x00000800,
933 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000,
934 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000,
935 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000,
936 FW_CAPS_CONFIG_HM_MI = 0x00008000,
937 FW_CAPS_CONFIG_HM_I2CM = 0x00010000,
938 FW_CAPS_CONFIG_HM_NCSI = 0x00020000,
939 FW_CAPS_CONFIG_HM_SMB = 0x00040000,
940 FW_CAPS_CONFIG_HM_MA = 0x00080000,
941 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000,
942 FW_CAPS_CONFIG_HM_PMU = 0x00200000,
943 FW_CAPS_CONFIG_HM_UART = 0x00400000,
944 FW_CAPS_CONFIG_HM_SF = 0x00800000,
945 };
946
947 enum fw_caps_config_nbm {
948 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001,
949 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002,
950 };
951
952 enum fw_caps_config_link {
953 FW_CAPS_CONFIG_LINK_PPP = 0x00000001,
954 FW_CAPS_CONFIG_LINK_QFC = 0x00000002,
955 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004,
956 };
957
958 enum fw_caps_config_switch {
959 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001,
960 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002,
961 };
962
963 enum fw_caps_config_nic {
964 FW_CAPS_CONFIG_NIC = 0x00000001,
965 FW_CAPS_CONFIG_NIC_VM = 0x00000002,
966 };
967
968 enum fw_caps_config_ofld {
969 FW_CAPS_CONFIG_OFLD = 0x00000001,
970 };
971
972 enum fw_caps_config_rdma {
973 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001,
974 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002,
975 };
976
977 enum fw_caps_config_iscsi {
978 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001,
979 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002,
980 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004,
981 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008,
982 };
983
984 enum fw_caps_config_fcoe {
985 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001,
986 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002,
987 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004,
988 };
989
990 enum fw_memtype_cf {
991 FW_MEMTYPE_CF_EDC0 = 0x0,
992 FW_MEMTYPE_CF_EDC1 = 0x1,
993 FW_MEMTYPE_CF_EXTMEM = 0x2,
994 FW_MEMTYPE_CF_FLASH = 0x4,
995 FW_MEMTYPE_CF_INTERNAL = 0x5,
996 };
997
998 struct fw_caps_config_cmd {
999 __be32 op_to_write;
1000 __be32 cfvalid_to_len16;
1001 __be32 r2;
1002 __be32 hwmbitmap;
1003 __be16 nbmcaps;
1004 __be16 linkcaps;
1005 __be16 switchcaps;
1006 __be16 r3;
1007 __be16 niccaps;
1008 __be16 ofldcaps;
1009 __be16 rdmacaps;
1010 __be16 r4;
1011 __be16 iscsicaps;
1012 __be16 fcoecaps;
1013 __be32 cfcsum;
1014 __be32 finiver;
1015 __be32 finicsum;
1016 };
1017
1018 #define FW_CAPS_CONFIG_CMD_CFVALID_S 27
1019 #define FW_CAPS_CONFIG_CMD_CFVALID_V(x) ((x) << FW_CAPS_CONFIG_CMD_CFVALID_S)
1020 #define FW_CAPS_CONFIG_CMD_CFVALID_F FW_CAPS_CONFIG_CMD_CFVALID_V(1U)
1021
1022 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S 24
1023 #define FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(x) \
1024 ((x) << FW_CAPS_CONFIG_CMD_MEMTYPE_CF_S)
1025
1026 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S 16
1027 #define FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(x) \
1028 ((x) << FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_S)
1029
1030 /*
1031 * params command mnemonics
1032 */
1033 enum fw_params_mnem {
1034 FW_PARAMS_MNEM_DEV = 1, /* device params */
1035 FW_PARAMS_MNEM_PFVF = 2, /* function params */
1036 FW_PARAMS_MNEM_REG = 3, /* limited register access */
1037 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */
1038 FW_PARAMS_MNEM_LAST
1039 };
1040
1041 /*
1042 * device parameters
1043 */
1044 enum fw_params_param_dev {
1045 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */
1046 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */
1047 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs
1048 * allocated by the device's
1049 * Lookup Engine
1050 */
1051 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03,
1052 FW_PARAMS_PARAM_DEV_INTVER_NIC = 0x04,
1053 FW_PARAMS_PARAM_DEV_INTVER_VNIC = 0x05,
1054 FW_PARAMS_PARAM_DEV_INTVER_OFLD = 0x06,
1055 FW_PARAMS_PARAM_DEV_INTVER_RI = 0x07,
1056 FW_PARAMS_PARAM_DEV_INTVER_ISCSIPDU = 0x08,
1057 FW_PARAMS_PARAM_DEV_INTVER_ISCSI = 0x09,
1058 FW_PARAMS_PARAM_DEV_INTVER_FCOE = 0x0A,
1059 FW_PARAMS_PARAM_DEV_FWREV = 0x0B,
1060 FW_PARAMS_PARAM_DEV_TPREV = 0x0C,
1061 FW_PARAMS_PARAM_DEV_CF = 0x0D,
1062 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD */
1063 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER = 0x14, /* max supported adap IRD */
1064 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
1065 };
1066
1067 /*
1068 * physical and virtual function parameters
1069 */
1070 enum fw_params_param_pfvf {
1071 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00,
1072 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01,
1073 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02,
1074 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03,
1075 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04,
1076 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05,
1077 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06,
1078 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07,
1079 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08,
1080 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09,
1081 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A,
1082 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B,
1083 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C,
1084 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D,
1085 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E,
1086 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F,
1087 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10,
1088 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11,
1089 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12,
1090 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13,
1091 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14,
1092 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15,
1093 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16,
1094 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17,
1095 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18,
1096 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20,
1097 FW_PARAMS_PARAM_PFVF_VIID = 0x24,
1098 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25,
1099 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26,
1100 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27,
1101 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28,
1102 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29,
1103 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A,
1104 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B,
1105 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C,
1106 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D,
1107 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E,
1108 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30,
1109 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31
1110 };
1111
1112 /*
1113 * dma queue parameters
1114 */
1115 enum fw_params_param_dmaq {
1116 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00,
1117 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01,
1118 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10,
1119 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11,
1120 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12,
1121 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13,
1122 };
1123
1124 #define FW_PARAMS_MNEM_S 24
1125 #define FW_PARAMS_MNEM_V(x) ((x) << FW_PARAMS_MNEM_S)
1126
1127 #define FW_PARAMS_PARAM_X_S 16
1128 #define FW_PARAMS_PARAM_X_V(x) ((x) << FW_PARAMS_PARAM_X_S)
1129
1130 #define FW_PARAMS_PARAM_Y_S 8
1131 #define FW_PARAMS_PARAM_Y_M 0xffU
1132 #define FW_PARAMS_PARAM_Y_V(x) ((x) << FW_PARAMS_PARAM_Y_S)
1133 #define FW_PARAMS_PARAM_Y_G(x) (((x) >> FW_PARAMS_PARAM_Y_S) &\
1134 FW_PARAMS_PARAM_Y_M)
1135
1136 #define FW_PARAMS_PARAM_Z_S 0
1137 #define FW_PARAMS_PARAM_Z_M 0xffu
1138 #define FW_PARAMS_PARAM_Z_V(x) ((x) << FW_PARAMS_PARAM_Z_S)
1139 #define FW_PARAMS_PARAM_Z_G(x) (((x) >> FW_PARAMS_PARAM_Z_S) &\
1140 FW_PARAMS_PARAM_Z_M)
1141
1142 #define FW_PARAMS_PARAM_XYZ_S 0
1143 #define FW_PARAMS_PARAM_XYZ_V(x) ((x) << FW_PARAMS_PARAM_XYZ_S)
1144
1145 #define FW_PARAMS_PARAM_YZ_S 0
1146 #define FW_PARAMS_PARAM_YZ_V(x) ((x) << FW_PARAMS_PARAM_YZ_S)
1147
1148 struct fw_params_cmd {
1149 __be32 op_to_vfn;
1150 __be32 retval_len16;
1151 struct fw_params_param {
1152 __be32 mnem;
1153 __be32 val;
1154 } param[7];
1155 };
1156
1157 #define FW_PARAMS_CMD_PFN_S 8
1158 #define FW_PARAMS_CMD_PFN_V(x) ((x) << FW_PARAMS_CMD_PFN_S)
1159
1160 #define FW_PARAMS_CMD_VFN_S 0
1161 #define FW_PARAMS_CMD_VFN_V(x) ((x) << FW_PARAMS_CMD_VFN_S)
1162
1163 struct fw_pfvf_cmd {
1164 __be32 op_to_vfn;
1165 __be32 retval_len16;
1166 __be32 niqflint_niq;
1167 __be32 type_to_neq;
1168 __be32 tc_to_nexactf;
1169 __be32 r_caps_to_nethctrl;
1170 __be16 nricq;
1171 __be16 nriqp;
1172 __be32 r4;
1173 };
1174
1175 #define FW_PFVF_CMD_PFN_S 8
1176 #define FW_PFVF_CMD_PFN_V(x) ((x) << FW_PFVF_CMD_PFN_S)
1177
1178 #define FW_PFVF_CMD_VFN_S 0
1179 #define FW_PFVF_CMD_VFN_V(x) ((x) << FW_PFVF_CMD_VFN_S)
1180
1181 #define FW_PFVF_CMD_NIQFLINT_S 20
1182 #define FW_PFVF_CMD_NIQFLINT_M 0xfff
1183 #define FW_PFVF_CMD_NIQFLINT_V(x) ((x) << FW_PFVF_CMD_NIQFLINT_S)
1184 #define FW_PFVF_CMD_NIQFLINT_G(x) \
1185 (((x) >> FW_PFVF_CMD_NIQFLINT_S) & FW_PFVF_CMD_NIQFLINT_M)
1186
1187 #define FW_PFVF_CMD_NIQ_S 0
1188 #define FW_PFVF_CMD_NIQ_M 0xfffff
1189 #define FW_PFVF_CMD_NIQ_V(x) ((x) << FW_PFVF_CMD_NIQ_S)
1190 #define FW_PFVF_CMD_NIQ_G(x) \
1191 (((x) >> FW_PFVF_CMD_NIQ_S) & FW_PFVF_CMD_NIQ_M)
1192
1193 #define FW_PFVF_CMD_TYPE_S 31
1194 #define FW_PFVF_CMD_TYPE_M 0x1
1195 #define FW_PFVF_CMD_TYPE_V(x) ((x) << FW_PFVF_CMD_TYPE_S)
1196 #define FW_PFVF_CMD_TYPE_G(x) \
1197 (((x) >> FW_PFVF_CMD_TYPE_S) & FW_PFVF_CMD_TYPE_M)
1198 #define FW_PFVF_CMD_TYPE_F FW_PFVF_CMD_TYPE_V(1U)
1199
1200 #define FW_PFVF_CMD_CMASK_S 24
1201 #define FW_PFVF_CMD_CMASK_M 0xf
1202 #define FW_PFVF_CMD_CMASK_V(x) ((x) << FW_PFVF_CMD_CMASK_S)
1203 #define FW_PFVF_CMD_CMASK_G(x) \
1204 (((x) >> FW_PFVF_CMD_CMASK_S) & FW_PFVF_CMD_CMASK_M)
1205
1206 #define FW_PFVF_CMD_PMASK_S 20
1207 #define FW_PFVF_CMD_PMASK_M 0xf
1208 #define FW_PFVF_CMD_PMASK_V(x) ((x) << FW_PFVF_CMD_PMASK_S)
1209 #define FW_PFVF_CMD_PMASK_G(x) \
1210 (((x) >> FW_PFVF_CMD_PMASK_S) & FW_PFVF_CMD_PMASK_M)
1211
1212 #define FW_PFVF_CMD_NEQ_S 0
1213 #define FW_PFVF_CMD_NEQ_M 0xfffff
1214 #define FW_PFVF_CMD_NEQ_V(x) ((x) << FW_PFVF_CMD_NEQ_S)
1215 #define FW_PFVF_CMD_NEQ_G(x) \
1216 (((x) >> FW_PFVF_CMD_NEQ_S) & FW_PFVF_CMD_NEQ_M)
1217
1218 #define FW_PFVF_CMD_TC_S 24
1219 #define FW_PFVF_CMD_TC_M 0xff
1220 #define FW_PFVF_CMD_TC_V(x) ((x) << FW_PFVF_CMD_TC_S)
1221 #define FW_PFVF_CMD_TC_G(x) (((x) >> FW_PFVF_CMD_TC_S) & FW_PFVF_CMD_TC_M)
1222
1223 #define FW_PFVF_CMD_NVI_S 16
1224 #define FW_PFVF_CMD_NVI_M 0xff
1225 #define FW_PFVF_CMD_NVI_V(x) ((x) << FW_PFVF_CMD_NVI_S)
1226 #define FW_PFVF_CMD_NVI_G(x) (((x) >> FW_PFVF_CMD_NVI_S) & FW_PFVF_CMD_NVI_M)
1227
1228 #define FW_PFVF_CMD_NEXACTF_S 0
1229 #define FW_PFVF_CMD_NEXACTF_M 0xffff
1230 #define FW_PFVF_CMD_NEXACTF_V(x) ((x) << FW_PFVF_CMD_NEXACTF_S)
1231 #define FW_PFVF_CMD_NEXACTF_G(x) \
1232 (((x) >> FW_PFVF_CMD_NEXACTF_S) & FW_PFVF_CMD_NEXACTF_M)
1233
1234 #define FW_PFVF_CMD_R_CAPS_S 24
1235 #define FW_PFVF_CMD_R_CAPS_M 0xff
1236 #define FW_PFVF_CMD_R_CAPS_V(x) ((x) << FW_PFVF_CMD_R_CAPS_S)
1237 #define FW_PFVF_CMD_R_CAPS_G(x) \
1238 (((x) >> FW_PFVF_CMD_R_CAPS_S) & FW_PFVF_CMD_R_CAPS_M)
1239
1240 #define FW_PFVF_CMD_WX_CAPS_S 16
1241 #define FW_PFVF_CMD_WX_CAPS_M 0xff
1242 #define FW_PFVF_CMD_WX_CAPS_V(x) ((x) << FW_PFVF_CMD_WX_CAPS_S)
1243 #define FW_PFVF_CMD_WX_CAPS_G(x) \
1244 (((x) >> FW_PFVF_CMD_WX_CAPS_S) & FW_PFVF_CMD_WX_CAPS_M)
1245
1246 #define FW_PFVF_CMD_NETHCTRL_S 0
1247 #define FW_PFVF_CMD_NETHCTRL_M 0xffff
1248 #define FW_PFVF_CMD_NETHCTRL_V(x) ((x) << FW_PFVF_CMD_NETHCTRL_S)
1249 #define FW_PFVF_CMD_NETHCTRL_G(x) \
1250 (((x) >> FW_PFVF_CMD_NETHCTRL_S) & FW_PFVF_CMD_NETHCTRL_M)
1251
1252 enum fw_iq_type {
1253 FW_IQ_TYPE_FL_INT_CAP,
1254 FW_IQ_TYPE_NO_FL_INT_CAP
1255 };
1256
1257 struct fw_iq_cmd {
1258 __be32 op_to_vfn;
1259 __be32 alloc_to_len16;
1260 __be16 physiqid;
1261 __be16 iqid;
1262 __be16 fl0id;
1263 __be16 fl1id;
1264 __be32 type_to_iqandstindex;
1265 __be16 iqdroprss_to_iqesize;
1266 __be16 iqsize;
1267 __be64 iqaddr;
1268 __be32 iqns_to_fl0congen;
1269 __be16 fl0dcaen_to_fl0cidxfthresh;
1270 __be16 fl0size;
1271 __be64 fl0addr;
1272 __be32 fl1cngchmap_to_fl1congen;
1273 __be16 fl1dcaen_to_fl1cidxfthresh;
1274 __be16 fl1size;
1275 __be64 fl1addr;
1276 };
1277
1278 #define FW_IQ_CMD_PFN_S 8
1279 #define FW_IQ_CMD_PFN_V(x) ((x) << FW_IQ_CMD_PFN_S)
1280
1281 #define FW_IQ_CMD_VFN_S 0
1282 #define FW_IQ_CMD_VFN_V(x) ((x) << FW_IQ_CMD_VFN_S)
1283
1284 #define FW_IQ_CMD_ALLOC_S 31
1285 #define FW_IQ_CMD_ALLOC_V(x) ((x) << FW_IQ_CMD_ALLOC_S)
1286 #define FW_IQ_CMD_ALLOC_F FW_IQ_CMD_ALLOC_V(1U)
1287
1288 #define FW_IQ_CMD_FREE_S 30
1289 #define FW_IQ_CMD_FREE_V(x) ((x) << FW_IQ_CMD_FREE_S)
1290 #define FW_IQ_CMD_FREE_F FW_IQ_CMD_FREE_V(1U)
1291
1292 #define FW_IQ_CMD_MODIFY_S 29
1293 #define FW_IQ_CMD_MODIFY_V(x) ((x) << FW_IQ_CMD_MODIFY_S)
1294 #define FW_IQ_CMD_MODIFY_F FW_IQ_CMD_MODIFY_V(1U)
1295
1296 #define FW_IQ_CMD_IQSTART_S 28
1297 #define FW_IQ_CMD_IQSTART_V(x) ((x) << FW_IQ_CMD_IQSTART_S)
1298 #define FW_IQ_CMD_IQSTART_F FW_IQ_CMD_IQSTART_V(1U)
1299
1300 #define FW_IQ_CMD_IQSTOP_S 27
1301 #define FW_IQ_CMD_IQSTOP_V(x) ((x) << FW_IQ_CMD_IQSTOP_S)
1302 #define FW_IQ_CMD_IQSTOP_F FW_IQ_CMD_IQSTOP_V(1U)
1303
1304 #define FW_IQ_CMD_TYPE_S 29
1305 #define FW_IQ_CMD_TYPE_V(x) ((x) << FW_IQ_CMD_TYPE_S)
1306
1307 #define FW_IQ_CMD_IQASYNCH_S 28
1308 #define FW_IQ_CMD_IQASYNCH_V(x) ((x) << FW_IQ_CMD_IQASYNCH_S)
1309
1310 #define FW_IQ_CMD_VIID_S 16
1311 #define FW_IQ_CMD_VIID_V(x) ((x) << FW_IQ_CMD_VIID_S)
1312
1313 #define FW_IQ_CMD_IQANDST_S 15
1314 #define FW_IQ_CMD_IQANDST_V(x) ((x) << FW_IQ_CMD_IQANDST_S)
1315
1316 #define FW_IQ_CMD_IQANUS_S 14
1317 #define FW_IQ_CMD_IQANUS_V(x) ((x) << FW_IQ_CMD_IQANUS_S)
1318
1319 #define FW_IQ_CMD_IQANUD_S 12
1320 #define FW_IQ_CMD_IQANUD_V(x) ((x) << FW_IQ_CMD_IQANUD_S)
1321
1322 #define FW_IQ_CMD_IQANDSTINDEX_S 0
1323 #define FW_IQ_CMD_IQANDSTINDEX_V(x) ((x) << FW_IQ_CMD_IQANDSTINDEX_S)
1324
1325 #define FW_IQ_CMD_IQDROPRSS_S 15
1326 #define FW_IQ_CMD_IQDROPRSS_V(x) ((x) << FW_IQ_CMD_IQDROPRSS_S)
1327 #define FW_IQ_CMD_IQDROPRSS_F FW_IQ_CMD_IQDROPRSS_V(1U)
1328
1329 #define FW_IQ_CMD_IQGTSMODE_S 14
1330 #define FW_IQ_CMD_IQGTSMODE_V(x) ((x) << FW_IQ_CMD_IQGTSMODE_S)
1331 #define FW_IQ_CMD_IQGTSMODE_F FW_IQ_CMD_IQGTSMODE_V(1U)
1332
1333 #define FW_IQ_CMD_IQPCIECH_S 12
1334 #define FW_IQ_CMD_IQPCIECH_V(x) ((x) << FW_IQ_CMD_IQPCIECH_S)
1335
1336 #define FW_IQ_CMD_IQDCAEN_S 11
1337 #define FW_IQ_CMD_IQDCAEN_V(x) ((x) << FW_IQ_CMD_IQDCAEN_S)
1338
1339 #define FW_IQ_CMD_IQDCACPU_S 6
1340 #define FW_IQ_CMD_IQDCACPU_V(x) ((x) << FW_IQ_CMD_IQDCACPU_S)
1341
1342 #define FW_IQ_CMD_IQINTCNTTHRESH_S 4
1343 #define FW_IQ_CMD_IQINTCNTTHRESH_V(x) ((x) << FW_IQ_CMD_IQINTCNTTHRESH_S)
1344
1345 #define FW_IQ_CMD_IQO_S 3
1346 #define FW_IQ_CMD_IQO_V(x) ((x) << FW_IQ_CMD_IQO_S)
1347 #define FW_IQ_CMD_IQO_F FW_IQ_CMD_IQO_V(1U)
1348
1349 #define FW_IQ_CMD_IQCPRIO_S 2
1350 #define FW_IQ_CMD_IQCPRIO_V(x) ((x) << FW_IQ_CMD_IQCPRIO_S)
1351
1352 #define FW_IQ_CMD_IQESIZE_S 0
1353 #define FW_IQ_CMD_IQESIZE_V(x) ((x) << FW_IQ_CMD_IQESIZE_S)
1354
1355 #define FW_IQ_CMD_IQNS_S 31
1356 #define FW_IQ_CMD_IQNS_V(x) ((x) << FW_IQ_CMD_IQNS_S)
1357
1358 #define FW_IQ_CMD_IQRO_S 30
1359 #define FW_IQ_CMD_IQRO_V(x) ((x) << FW_IQ_CMD_IQRO_S)
1360
1361 #define FW_IQ_CMD_IQFLINTIQHSEN_S 28
1362 #define FW_IQ_CMD_IQFLINTIQHSEN_V(x) ((x) << FW_IQ_CMD_IQFLINTIQHSEN_S)
1363
1364 #define FW_IQ_CMD_IQFLINTCONGEN_S 27
1365 #define FW_IQ_CMD_IQFLINTCONGEN_V(x) ((x) << FW_IQ_CMD_IQFLINTCONGEN_S)
1366
1367 #define FW_IQ_CMD_IQFLINTISCSIC_S 26
1368 #define FW_IQ_CMD_IQFLINTISCSIC_V(x) ((x) << FW_IQ_CMD_IQFLINTISCSIC_S)
1369
1370 #define FW_IQ_CMD_FL0CNGCHMAP_S 20
1371 #define FW_IQ_CMD_FL0CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL0CNGCHMAP_S)
1372
1373 #define FW_IQ_CMD_FL0CACHELOCK_S 15
1374 #define FW_IQ_CMD_FL0CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL0CACHELOCK_S)
1375
1376 #define FW_IQ_CMD_FL0DBP_S 14
1377 #define FW_IQ_CMD_FL0DBP_V(x) ((x) << FW_IQ_CMD_FL0DBP_S)
1378
1379 #define FW_IQ_CMD_FL0DATANS_S 13
1380 #define FW_IQ_CMD_FL0DATANS_V(x) ((x) << FW_IQ_CMD_FL0DATANS_S)
1381
1382 #define FW_IQ_CMD_FL0DATARO_S 12
1383 #define FW_IQ_CMD_FL0DATARO_V(x) ((x) << FW_IQ_CMD_FL0DATARO_S)
1384 #define FW_IQ_CMD_FL0DATARO_F FW_IQ_CMD_FL0DATARO_V(1U)
1385
1386 #define FW_IQ_CMD_FL0CONGCIF_S 11
1387 #define FW_IQ_CMD_FL0CONGCIF_V(x) ((x) << FW_IQ_CMD_FL0CONGCIF_S)
1388
1389 #define FW_IQ_CMD_FL0ONCHIP_S 10
1390 #define FW_IQ_CMD_FL0ONCHIP_V(x) ((x) << FW_IQ_CMD_FL0ONCHIP_S)
1391
1392 #define FW_IQ_CMD_FL0STATUSPGNS_S 9
1393 #define FW_IQ_CMD_FL0STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGNS_S)
1394
1395 #define FW_IQ_CMD_FL0STATUSPGRO_S 8
1396 #define FW_IQ_CMD_FL0STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL0STATUSPGRO_S)
1397
1398 #define FW_IQ_CMD_FL0FETCHNS_S 7
1399 #define FW_IQ_CMD_FL0FETCHNS_V(x) ((x) << FW_IQ_CMD_FL0FETCHNS_S)
1400
1401 #define FW_IQ_CMD_FL0FETCHRO_S 6
1402 #define FW_IQ_CMD_FL0FETCHRO_V(x) ((x) << FW_IQ_CMD_FL0FETCHRO_S)
1403 #define FW_IQ_CMD_FL0FETCHRO_F FW_IQ_CMD_FL0FETCHRO_V(1U)
1404
1405 #define FW_IQ_CMD_FL0HOSTFCMODE_S 4
1406 #define FW_IQ_CMD_FL0HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL0HOSTFCMODE_S)
1407
1408 #define FW_IQ_CMD_FL0CPRIO_S 3
1409 #define FW_IQ_CMD_FL0CPRIO_V(x) ((x) << FW_IQ_CMD_FL0CPRIO_S)
1410
1411 #define FW_IQ_CMD_FL0PADEN_S 2
1412 #define FW_IQ_CMD_FL0PADEN_V(x) ((x) << FW_IQ_CMD_FL0PADEN_S)
1413 #define FW_IQ_CMD_FL0PADEN_F FW_IQ_CMD_FL0PADEN_V(1U)
1414
1415 #define FW_IQ_CMD_FL0PACKEN_S 1
1416 #define FW_IQ_CMD_FL0PACKEN_V(x) ((x) << FW_IQ_CMD_FL0PACKEN_S)
1417 #define FW_IQ_CMD_FL0PACKEN_F FW_IQ_CMD_FL0PACKEN_V(1U)
1418
1419 #define FW_IQ_CMD_FL0CONGEN_S 0
1420 #define FW_IQ_CMD_FL0CONGEN_V(x) ((x) << FW_IQ_CMD_FL0CONGEN_S)
1421 #define FW_IQ_CMD_FL0CONGEN_F FW_IQ_CMD_FL0CONGEN_V(1U)
1422
1423 #define FW_IQ_CMD_FL0DCAEN_S 15
1424 #define FW_IQ_CMD_FL0DCAEN_V(x) ((x) << FW_IQ_CMD_FL0DCAEN_S)
1425
1426 #define FW_IQ_CMD_FL0DCACPU_S 10
1427 #define FW_IQ_CMD_FL0DCACPU_V(x) ((x) << FW_IQ_CMD_FL0DCACPU_S)
1428
1429 #define FW_IQ_CMD_FL0FBMIN_S 7
1430 #define FW_IQ_CMD_FL0FBMIN_V(x) ((x) << FW_IQ_CMD_FL0FBMIN_S)
1431
1432 #define FW_IQ_CMD_FL0FBMAX_S 4
1433 #define FW_IQ_CMD_FL0FBMAX_V(x) ((x) << FW_IQ_CMD_FL0FBMAX_S)
1434
1435 #define FW_IQ_CMD_FL0CIDXFTHRESHO_S 3
1436 #define FW_IQ_CMD_FL0CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESHO_S)
1437 #define FW_IQ_CMD_FL0CIDXFTHRESHO_F FW_IQ_CMD_FL0CIDXFTHRESHO_V(1U)
1438
1439 #define FW_IQ_CMD_FL0CIDXFTHRESH_S 0
1440 #define FW_IQ_CMD_FL0CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL0CIDXFTHRESH_S)
1441
1442 #define FW_IQ_CMD_FL1CNGCHMAP_S 20
1443 #define FW_IQ_CMD_FL1CNGCHMAP_V(x) ((x) << FW_IQ_CMD_FL1CNGCHMAP_S)
1444
1445 #define FW_IQ_CMD_FL1CACHELOCK_S 15
1446 #define FW_IQ_CMD_FL1CACHELOCK_V(x) ((x) << FW_IQ_CMD_FL1CACHELOCK_S)
1447
1448 #define FW_IQ_CMD_FL1DBP_S 14
1449 #define FW_IQ_CMD_FL1DBP_V(x) ((x) << FW_IQ_CMD_FL1DBP_S)
1450
1451 #define FW_IQ_CMD_FL1DATANS_S 13
1452 #define FW_IQ_CMD_FL1DATANS_V(x) ((x) << FW_IQ_CMD_FL1DATANS_S)
1453
1454 #define FW_IQ_CMD_FL1DATARO_S 12
1455 #define FW_IQ_CMD_FL1DATARO_V(x) ((x) << FW_IQ_CMD_FL1DATARO_S)
1456
1457 #define FW_IQ_CMD_FL1CONGCIF_S 11
1458 #define FW_IQ_CMD_FL1CONGCIF_V(x) ((x) << FW_IQ_CMD_FL1CONGCIF_S)
1459
1460 #define FW_IQ_CMD_FL1ONCHIP_S 10
1461 #define FW_IQ_CMD_FL1ONCHIP_V(x) ((x) << FW_IQ_CMD_FL1ONCHIP_S)
1462
1463 #define FW_IQ_CMD_FL1STATUSPGNS_S 9
1464 #define FW_IQ_CMD_FL1STATUSPGNS_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGNS_S)
1465
1466 #define FW_IQ_CMD_FL1STATUSPGRO_S 8
1467 #define FW_IQ_CMD_FL1STATUSPGRO_V(x) ((x) << FW_IQ_CMD_FL1STATUSPGRO_S)
1468
1469 #define FW_IQ_CMD_FL1FETCHNS_S 7
1470 #define FW_IQ_CMD_FL1FETCHNS_V(x) ((x) << FW_IQ_CMD_FL1FETCHNS_S)
1471
1472 #define FW_IQ_CMD_FL1FETCHRO_S 6
1473 #define FW_IQ_CMD_FL1FETCHRO_V(x) ((x) << FW_IQ_CMD_FL1FETCHRO_S)
1474
1475 #define FW_IQ_CMD_FL1HOSTFCMODE_S 4
1476 #define FW_IQ_CMD_FL1HOSTFCMODE_V(x) ((x) << FW_IQ_CMD_FL1HOSTFCMODE_S)
1477
1478 #define FW_IQ_CMD_FL1CPRIO_S 3
1479 #define FW_IQ_CMD_FL1CPRIO_V(x) ((x) << FW_IQ_CMD_FL1CPRIO_S)
1480
1481 #define FW_IQ_CMD_FL1PADEN_S 2
1482 #define FW_IQ_CMD_FL1PADEN_V(x) ((x) << FW_IQ_CMD_FL1PADEN_S)
1483 #define FW_IQ_CMD_FL1PADEN_F FW_IQ_CMD_FL1PADEN_V(1U)
1484
1485 #define FW_IQ_CMD_FL1PACKEN_S 1
1486 #define FW_IQ_CMD_FL1PACKEN_V(x) ((x) << FW_IQ_CMD_FL1PACKEN_S)
1487 #define FW_IQ_CMD_FL1PACKEN_F FW_IQ_CMD_FL1PACKEN_V(1U)
1488
1489 #define FW_IQ_CMD_FL1CONGEN_S 0
1490 #define FW_IQ_CMD_FL1CONGEN_V(x) ((x) << FW_IQ_CMD_FL1CONGEN_S)
1491 #define FW_IQ_CMD_FL1CONGEN_F FW_IQ_CMD_FL1CONGEN_V(1U)
1492
1493 #define FW_IQ_CMD_FL1DCAEN_S 15
1494 #define FW_IQ_CMD_FL1DCAEN_V(x) ((x) << FW_IQ_CMD_FL1DCAEN_S)
1495
1496 #define FW_IQ_CMD_FL1DCACPU_S 10
1497 #define FW_IQ_CMD_FL1DCACPU_V(x) ((x) << FW_IQ_CMD_FL1DCACPU_S)
1498
1499 #define FW_IQ_CMD_FL1FBMIN_S 7
1500 #define FW_IQ_CMD_FL1FBMIN_V(x) ((x) << FW_IQ_CMD_FL1FBMIN_S)
1501
1502 #define FW_IQ_CMD_FL1FBMAX_S 4
1503 #define FW_IQ_CMD_FL1FBMAX_V(x) ((x) << FW_IQ_CMD_FL1FBMAX_S)
1504
1505 #define FW_IQ_CMD_FL1CIDXFTHRESHO_S 3
1506 #define FW_IQ_CMD_FL1CIDXFTHRESHO_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESHO_S)
1507 #define FW_IQ_CMD_FL1CIDXFTHRESHO_F FW_IQ_CMD_FL1CIDXFTHRESHO_V(1U)
1508
1509 #define FW_IQ_CMD_FL1CIDXFTHRESH_S 0
1510 #define FW_IQ_CMD_FL1CIDXFTHRESH_V(x) ((x) << FW_IQ_CMD_FL1CIDXFTHRESH_S)
1511
1512 struct fw_eq_eth_cmd {
1513 __be32 op_to_vfn;
1514 __be32 alloc_to_len16;
1515 __be32 eqid_pkd;
1516 __be32 physeqid_pkd;
1517 __be32 fetchszm_to_iqid;
1518 __be32 dcaen_to_eqsize;
1519 __be64 eqaddr;
1520 __be32 viid_pkd;
1521 __be32 r8_lo;
1522 __be64 r9;
1523 };
1524
1525 #define FW_EQ_ETH_CMD_PFN_S 8
1526 #define FW_EQ_ETH_CMD_PFN_V(x) ((x) << FW_EQ_ETH_CMD_PFN_S)
1527
1528 #define FW_EQ_ETH_CMD_VFN_S 0
1529 #define FW_EQ_ETH_CMD_VFN_V(x) ((x) << FW_EQ_ETH_CMD_VFN_S)
1530
1531 #define FW_EQ_ETH_CMD_ALLOC_S 31
1532 #define FW_EQ_ETH_CMD_ALLOC_V(x) ((x) << FW_EQ_ETH_CMD_ALLOC_S)
1533 #define FW_EQ_ETH_CMD_ALLOC_F FW_EQ_ETH_CMD_ALLOC_V(1U)
1534
1535 #define FW_EQ_ETH_CMD_FREE_S 30
1536 #define FW_EQ_ETH_CMD_FREE_V(x) ((x) << FW_EQ_ETH_CMD_FREE_S)
1537 #define FW_EQ_ETH_CMD_FREE_F FW_EQ_ETH_CMD_FREE_V(1U)
1538
1539 #define FW_EQ_ETH_CMD_MODIFY_S 29
1540 #define FW_EQ_ETH_CMD_MODIFY_V(x) ((x) << FW_EQ_ETH_CMD_MODIFY_S)
1541 #define FW_EQ_ETH_CMD_MODIFY_F FW_EQ_ETH_CMD_MODIFY_V(1U)
1542
1543 #define FW_EQ_ETH_CMD_EQSTART_S 28
1544 #define FW_EQ_ETH_CMD_EQSTART_V(x) ((x) << FW_EQ_ETH_CMD_EQSTART_S)
1545 #define FW_EQ_ETH_CMD_EQSTART_F FW_EQ_ETH_CMD_EQSTART_V(1U)
1546
1547 #define FW_EQ_ETH_CMD_EQSTOP_S 27
1548 #define FW_EQ_ETH_CMD_EQSTOP_V(x) ((x) << FW_EQ_ETH_CMD_EQSTOP_S)
1549 #define FW_EQ_ETH_CMD_EQSTOP_F FW_EQ_ETH_CMD_EQSTOP_V(1U)
1550
1551 #define FW_EQ_ETH_CMD_EQID_S 0
1552 #define FW_EQ_ETH_CMD_EQID_M 0xfffff
1553 #define FW_EQ_ETH_CMD_EQID_V(x) ((x) << FW_EQ_ETH_CMD_EQID_S)
1554 #define FW_EQ_ETH_CMD_EQID_G(x) \
1555 (((x) >> FW_EQ_ETH_CMD_EQID_S) & FW_EQ_ETH_CMD_EQID_M)
1556
1557 #define FW_EQ_ETH_CMD_PHYSEQID_S 0
1558 #define FW_EQ_ETH_CMD_PHYSEQID_M 0xfffff
1559 #define FW_EQ_ETH_CMD_PHYSEQID_V(x) ((x) << FW_EQ_ETH_CMD_PHYSEQID_S)
1560 #define FW_EQ_ETH_CMD_PHYSEQID_G(x) \
1561 (((x) >> FW_EQ_ETH_CMD_PHYSEQID_S) & FW_EQ_ETH_CMD_PHYSEQID_M)
1562
1563 #define FW_EQ_ETH_CMD_FETCHSZM_S 26
1564 #define FW_EQ_ETH_CMD_FETCHSZM_V(x) ((x) << FW_EQ_ETH_CMD_FETCHSZM_S)
1565 #define FW_EQ_ETH_CMD_FETCHSZM_F FW_EQ_ETH_CMD_FETCHSZM_V(1U)
1566
1567 #define FW_EQ_ETH_CMD_STATUSPGNS_S 25
1568 #define FW_EQ_ETH_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGNS_S)
1569
1570 #define FW_EQ_ETH_CMD_STATUSPGRO_S 24
1571 #define FW_EQ_ETH_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_ETH_CMD_STATUSPGRO_S)
1572
1573 #define FW_EQ_ETH_CMD_FETCHNS_S 23
1574 #define FW_EQ_ETH_CMD_FETCHNS_V(x) ((x) << FW_EQ_ETH_CMD_FETCHNS_S)
1575
1576 #define FW_EQ_ETH_CMD_FETCHRO_S 22
1577 #define FW_EQ_ETH_CMD_FETCHRO_V(x) ((x) << FW_EQ_ETH_CMD_FETCHRO_S)
1578
1579 #define FW_EQ_ETH_CMD_HOSTFCMODE_S 20
1580 #define FW_EQ_ETH_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_ETH_CMD_HOSTFCMODE_S)
1581
1582 #define FW_EQ_ETH_CMD_CPRIO_S 19
1583 #define FW_EQ_ETH_CMD_CPRIO_V(x) ((x) << FW_EQ_ETH_CMD_CPRIO_S)
1584
1585 #define FW_EQ_ETH_CMD_ONCHIP_S 18
1586 #define FW_EQ_ETH_CMD_ONCHIP_V(x) ((x) << FW_EQ_ETH_CMD_ONCHIP_S)
1587
1588 #define FW_EQ_ETH_CMD_PCIECHN_S 16
1589 #define FW_EQ_ETH_CMD_PCIECHN_V(x) ((x) << FW_EQ_ETH_CMD_PCIECHN_S)
1590
1591 #define FW_EQ_ETH_CMD_IQID_S 0
1592 #define FW_EQ_ETH_CMD_IQID_V(x) ((x) << FW_EQ_ETH_CMD_IQID_S)
1593
1594 #define FW_EQ_ETH_CMD_DCAEN_S 31
1595 #define FW_EQ_ETH_CMD_DCAEN_V(x) ((x) << FW_EQ_ETH_CMD_DCAEN_S)
1596
1597 #define FW_EQ_ETH_CMD_DCACPU_S 26
1598 #define FW_EQ_ETH_CMD_DCACPU_V(x) ((x) << FW_EQ_ETH_CMD_DCACPU_S)
1599
1600 #define FW_EQ_ETH_CMD_FBMIN_S 23
1601 #define FW_EQ_ETH_CMD_FBMIN_V(x) ((x) << FW_EQ_ETH_CMD_FBMIN_S)
1602
1603 #define FW_EQ_ETH_CMD_FBMAX_S 20
1604 #define FW_EQ_ETH_CMD_FBMAX_V(x) ((x) << FW_EQ_ETH_CMD_FBMAX_S)
1605
1606 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_S 19
1607 #define FW_EQ_ETH_CMD_CIDXFTHRESHO_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESHO_S)
1608
1609 #define FW_EQ_ETH_CMD_CIDXFTHRESH_S 16
1610 #define FW_EQ_ETH_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_ETH_CMD_CIDXFTHRESH_S)
1611
1612 #define FW_EQ_ETH_CMD_EQSIZE_S 0
1613 #define FW_EQ_ETH_CMD_EQSIZE_V(x) ((x) << FW_EQ_ETH_CMD_EQSIZE_S)
1614
1615 #define FW_EQ_ETH_CMD_AUTOEQUEQE_S 30
1616 #define FW_EQ_ETH_CMD_AUTOEQUEQE_V(x) ((x) << FW_EQ_ETH_CMD_AUTOEQUEQE_S)
1617 #define FW_EQ_ETH_CMD_AUTOEQUEQE_F FW_EQ_ETH_CMD_AUTOEQUEQE_V(1U)
1618
1619 #define FW_EQ_ETH_CMD_VIID_S 16
1620 #define FW_EQ_ETH_CMD_VIID_V(x) ((x) << FW_EQ_ETH_CMD_VIID_S)
1621
1622 struct fw_eq_ctrl_cmd {
1623 __be32 op_to_vfn;
1624 __be32 alloc_to_len16;
1625 __be32 cmpliqid_eqid;
1626 __be32 physeqid_pkd;
1627 __be32 fetchszm_to_iqid;
1628 __be32 dcaen_to_eqsize;
1629 __be64 eqaddr;
1630 };
1631
1632 #define FW_EQ_CTRL_CMD_PFN_S 8
1633 #define FW_EQ_CTRL_CMD_PFN_V(x) ((x) << FW_EQ_CTRL_CMD_PFN_S)
1634
1635 #define FW_EQ_CTRL_CMD_VFN_S 0
1636 #define FW_EQ_CTRL_CMD_VFN_V(x) ((x) << FW_EQ_CTRL_CMD_VFN_S)
1637
1638 #define FW_EQ_CTRL_CMD_ALLOC_S 31
1639 #define FW_EQ_CTRL_CMD_ALLOC_V(x) ((x) << FW_EQ_CTRL_CMD_ALLOC_S)
1640 #define FW_EQ_CTRL_CMD_ALLOC_F FW_EQ_CTRL_CMD_ALLOC_V(1U)
1641
1642 #define FW_EQ_CTRL_CMD_FREE_S 30
1643 #define FW_EQ_CTRL_CMD_FREE_V(x) ((x) << FW_EQ_CTRL_CMD_FREE_S)
1644 #define FW_EQ_CTRL_CMD_FREE_F FW_EQ_CTRL_CMD_FREE_V(1U)
1645
1646 #define FW_EQ_CTRL_CMD_MODIFY_S 29
1647 #define FW_EQ_CTRL_CMD_MODIFY_V(x) ((x) << FW_EQ_CTRL_CMD_MODIFY_S)
1648 #define FW_EQ_CTRL_CMD_MODIFY_F FW_EQ_CTRL_CMD_MODIFY_V(1U)
1649
1650 #define FW_EQ_CTRL_CMD_EQSTART_S 28
1651 #define FW_EQ_CTRL_CMD_EQSTART_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTART_S)
1652 #define FW_EQ_CTRL_CMD_EQSTART_F FW_EQ_CTRL_CMD_EQSTART_V(1U)
1653
1654 #define FW_EQ_CTRL_CMD_EQSTOP_S 27
1655 #define FW_EQ_CTRL_CMD_EQSTOP_V(x) ((x) << FW_EQ_CTRL_CMD_EQSTOP_S)
1656 #define FW_EQ_CTRL_CMD_EQSTOP_F FW_EQ_CTRL_CMD_EQSTOP_V(1U)
1657
1658 #define FW_EQ_CTRL_CMD_CMPLIQID_S 20
1659 #define FW_EQ_CTRL_CMD_CMPLIQID_V(x) ((x) << FW_EQ_CTRL_CMD_CMPLIQID_S)
1660
1661 #define FW_EQ_CTRL_CMD_EQID_S 0
1662 #define FW_EQ_CTRL_CMD_EQID_M 0xfffff
1663 #define FW_EQ_CTRL_CMD_EQID_V(x) ((x) << FW_EQ_CTRL_CMD_EQID_S)
1664 #define FW_EQ_CTRL_CMD_EQID_G(x) \
1665 (((x) >> FW_EQ_CTRL_CMD_EQID_S) & FW_EQ_CTRL_CMD_EQID_M)
1666
1667 #define FW_EQ_CTRL_CMD_PHYSEQID_S 0
1668 #define FW_EQ_CTRL_CMD_PHYSEQID_M 0xfffff
1669 #define FW_EQ_CTRL_CMD_PHYSEQID_G(x) \
1670 (((x) >> FW_EQ_CTRL_CMD_PHYSEQID_S) & FW_EQ_CTRL_CMD_PHYSEQID_M)
1671
1672 #define FW_EQ_CTRL_CMD_FETCHSZM_S 26
1673 #define FW_EQ_CTRL_CMD_FETCHSZM_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHSZM_S)
1674 #define FW_EQ_CTRL_CMD_FETCHSZM_F FW_EQ_CTRL_CMD_FETCHSZM_V(1U)
1675
1676 #define FW_EQ_CTRL_CMD_STATUSPGNS_S 25
1677 #define FW_EQ_CTRL_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGNS_S)
1678 #define FW_EQ_CTRL_CMD_STATUSPGNS_F FW_EQ_CTRL_CMD_STATUSPGNS_V(1U)
1679
1680 #define FW_EQ_CTRL_CMD_STATUSPGRO_S 24
1681 #define FW_EQ_CTRL_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_CTRL_CMD_STATUSPGRO_S)
1682 #define FW_EQ_CTRL_CMD_STATUSPGRO_F FW_EQ_CTRL_CMD_STATUSPGRO_V(1U)
1683
1684 #define FW_EQ_CTRL_CMD_FETCHNS_S 23
1685 #define FW_EQ_CTRL_CMD_FETCHNS_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHNS_S)
1686 #define FW_EQ_CTRL_CMD_FETCHNS_F FW_EQ_CTRL_CMD_FETCHNS_V(1U)
1687
1688 #define FW_EQ_CTRL_CMD_FETCHRO_S 22
1689 #define FW_EQ_CTRL_CMD_FETCHRO_V(x) ((x) << FW_EQ_CTRL_CMD_FETCHRO_S)
1690 #define FW_EQ_CTRL_CMD_FETCHRO_F FW_EQ_CTRL_CMD_FETCHRO_V(1U)
1691
1692 #define FW_EQ_CTRL_CMD_HOSTFCMODE_S 20
1693 #define FW_EQ_CTRL_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_CTRL_CMD_HOSTFCMODE_S)
1694
1695 #define FW_EQ_CTRL_CMD_CPRIO_S 19
1696 #define FW_EQ_CTRL_CMD_CPRIO_V(x) ((x) << FW_EQ_CTRL_CMD_CPRIO_S)
1697
1698 #define FW_EQ_CTRL_CMD_ONCHIP_S 18
1699 #define FW_EQ_CTRL_CMD_ONCHIP_V(x) ((x) << FW_EQ_CTRL_CMD_ONCHIP_S)
1700
1701 #define FW_EQ_CTRL_CMD_PCIECHN_S 16
1702 #define FW_EQ_CTRL_CMD_PCIECHN_V(x) ((x) << FW_EQ_CTRL_CMD_PCIECHN_S)
1703
1704 #define FW_EQ_CTRL_CMD_IQID_S 0
1705 #define FW_EQ_CTRL_CMD_IQID_V(x) ((x) << FW_EQ_CTRL_CMD_IQID_S)
1706
1707 #define FW_EQ_CTRL_CMD_DCAEN_S 31
1708 #define FW_EQ_CTRL_CMD_DCAEN_V(x) ((x) << FW_EQ_CTRL_CMD_DCAEN_S)
1709
1710 #define FW_EQ_CTRL_CMD_DCACPU_S 26
1711 #define FW_EQ_CTRL_CMD_DCACPU_V(x) ((x) << FW_EQ_CTRL_CMD_DCACPU_S)
1712
1713 #define FW_EQ_CTRL_CMD_FBMIN_S 23
1714 #define FW_EQ_CTRL_CMD_FBMIN_V(x) ((x) << FW_EQ_CTRL_CMD_FBMIN_S)
1715
1716 #define FW_EQ_CTRL_CMD_FBMAX_S 20
1717 #define FW_EQ_CTRL_CMD_FBMAX_V(x) ((x) << FW_EQ_CTRL_CMD_FBMAX_S)
1718
1719 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_S 19
1720 #define FW_EQ_CTRL_CMD_CIDXFTHRESHO_V(x) \
1721 ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESHO_S)
1722
1723 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_S 16
1724 #define FW_EQ_CTRL_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_CTRL_CMD_CIDXFTHRESH_S)
1725
1726 #define FW_EQ_CTRL_CMD_EQSIZE_S 0
1727 #define FW_EQ_CTRL_CMD_EQSIZE_V(x) ((x) << FW_EQ_CTRL_CMD_EQSIZE_S)
1728
1729 struct fw_eq_ofld_cmd {
1730 __be32 op_to_vfn;
1731 __be32 alloc_to_len16;
1732 __be32 eqid_pkd;
1733 __be32 physeqid_pkd;
1734 __be32 fetchszm_to_iqid;
1735 __be32 dcaen_to_eqsize;
1736 __be64 eqaddr;
1737 };
1738
1739 #define FW_EQ_OFLD_CMD_PFN_S 8
1740 #define FW_EQ_OFLD_CMD_PFN_V(x) ((x) << FW_EQ_OFLD_CMD_PFN_S)
1741
1742 #define FW_EQ_OFLD_CMD_VFN_S 0
1743 #define FW_EQ_OFLD_CMD_VFN_V(x) ((x) << FW_EQ_OFLD_CMD_VFN_S)
1744
1745 #define FW_EQ_OFLD_CMD_ALLOC_S 31
1746 #define FW_EQ_OFLD_CMD_ALLOC_V(x) ((x) << FW_EQ_OFLD_CMD_ALLOC_S)
1747 #define FW_EQ_OFLD_CMD_ALLOC_F FW_EQ_OFLD_CMD_ALLOC_V(1U)
1748
1749 #define FW_EQ_OFLD_CMD_FREE_S 30
1750 #define FW_EQ_OFLD_CMD_FREE_V(x) ((x) << FW_EQ_OFLD_CMD_FREE_S)
1751 #define FW_EQ_OFLD_CMD_FREE_F FW_EQ_OFLD_CMD_FREE_V(1U)
1752
1753 #define FW_EQ_OFLD_CMD_MODIFY_S 29
1754 #define FW_EQ_OFLD_CMD_MODIFY_V(x) ((x) << FW_EQ_OFLD_CMD_MODIFY_S)
1755 #define FW_EQ_OFLD_CMD_MODIFY_F FW_EQ_OFLD_CMD_MODIFY_V(1U)
1756
1757 #define FW_EQ_OFLD_CMD_EQSTART_S 28
1758 #define FW_EQ_OFLD_CMD_EQSTART_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTART_S)
1759 #define FW_EQ_OFLD_CMD_EQSTART_F FW_EQ_OFLD_CMD_EQSTART_V(1U)
1760
1761 #define FW_EQ_OFLD_CMD_EQSTOP_S 27
1762 #define FW_EQ_OFLD_CMD_EQSTOP_V(x) ((x) << FW_EQ_OFLD_CMD_EQSTOP_S)
1763 #define FW_EQ_OFLD_CMD_EQSTOP_F FW_EQ_OFLD_CMD_EQSTOP_V(1U)
1764
1765 #define FW_EQ_OFLD_CMD_EQID_S 0
1766 #define FW_EQ_OFLD_CMD_EQID_M 0xfffff
1767 #define FW_EQ_OFLD_CMD_EQID_V(x) ((x) << FW_EQ_OFLD_CMD_EQID_S)
1768 #define FW_EQ_OFLD_CMD_EQID_G(x) \
1769 (((x) >> FW_EQ_OFLD_CMD_EQID_S) & FW_EQ_OFLD_CMD_EQID_M)
1770
1771 #define FW_EQ_OFLD_CMD_PHYSEQID_S 0
1772 #define FW_EQ_OFLD_CMD_PHYSEQID_M 0xfffff
1773 #define FW_EQ_OFLD_CMD_PHYSEQID_G(x) \
1774 (((x) >> FW_EQ_OFLD_CMD_PHYSEQID_S) & FW_EQ_OFLD_CMD_PHYSEQID_M)
1775
1776 #define FW_EQ_OFLD_CMD_FETCHSZM_S 26
1777 #define FW_EQ_OFLD_CMD_FETCHSZM_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHSZM_S)
1778
1779 #define FW_EQ_OFLD_CMD_STATUSPGNS_S 25
1780 #define FW_EQ_OFLD_CMD_STATUSPGNS_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGNS_S)
1781
1782 #define FW_EQ_OFLD_CMD_STATUSPGRO_S 24
1783 #define FW_EQ_OFLD_CMD_STATUSPGRO_V(x) ((x) << FW_EQ_OFLD_CMD_STATUSPGRO_S)
1784
1785 #define FW_EQ_OFLD_CMD_FETCHNS_S 23
1786 #define FW_EQ_OFLD_CMD_FETCHNS_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHNS_S)
1787
1788 #define FW_EQ_OFLD_CMD_FETCHRO_S 22
1789 #define FW_EQ_OFLD_CMD_FETCHRO_V(x) ((x) << FW_EQ_OFLD_CMD_FETCHRO_S)
1790 #define FW_EQ_OFLD_CMD_FETCHRO_F FW_EQ_OFLD_CMD_FETCHRO_V(1U)
1791
1792 #define FW_EQ_OFLD_CMD_HOSTFCMODE_S 20
1793 #define FW_EQ_OFLD_CMD_HOSTFCMODE_V(x) ((x) << FW_EQ_OFLD_CMD_HOSTFCMODE_S)
1794
1795 #define FW_EQ_OFLD_CMD_CPRIO_S 19
1796 #define FW_EQ_OFLD_CMD_CPRIO_V(x) ((x) << FW_EQ_OFLD_CMD_CPRIO_S)
1797
1798 #define FW_EQ_OFLD_CMD_ONCHIP_S 18
1799 #define FW_EQ_OFLD_CMD_ONCHIP_V(x) ((x) << FW_EQ_OFLD_CMD_ONCHIP_S)
1800
1801 #define FW_EQ_OFLD_CMD_PCIECHN_S 16
1802 #define FW_EQ_OFLD_CMD_PCIECHN_V(x) ((x) << FW_EQ_OFLD_CMD_PCIECHN_S)
1803
1804 #define FW_EQ_OFLD_CMD_IQID_S 0
1805 #define FW_EQ_OFLD_CMD_IQID_V(x) ((x) << FW_EQ_OFLD_CMD_IQID_S)
1806
1807 #define FW_EQ_OFLD_CMD_DCAEN_S 31
1808 #define FW_EQ_OFLD_CMD_DCAEN_V(x) ((x) << FW_EQ_OFLD_CMD_DCAEN_S)
1809
1810 #define FW_EQ_OFLD_CMD_DCACPU_S 26
1811 #define FW_EQ_OFLD_CMD_DCACPU_V(x) ((x) << FW_EQ_OFLD_CMD_DCACPU_S)
1812
1813 #define FW_EQ_OFLD_CMD_FBMIN_S 23
1814 #define FW_EQ_OFLD_CMD_FBMIN_V(x) ((x) << FW_EQ_OFLD_CMD_FBMIN_S)
1815
1816 #define FW_EQ_OFLD_CMD_FBMAX_S 20
1817 #define FW_EQ_OFLD_CMD_FBMAX_V(x) ((x) << FW_EQ_OFLD_CMD_FBMAX_S)
1818
1819 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_S 19
1820 #define FW_EQ_OFLD_CMD_CIDXFTHRESHO_V(x) \
1821 ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESHO_S)
1822
1823 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_S 16
1824 #define FW_EQ_OFLD_CMD_CIDXFTHRESH_V(x) ((x) << FW_EQ_OFLD_CMD_CIDXFTHRESH_S)
1825
1826 #define FW_EQ_OFLD_CMD_EQSIZE_S 0
1827 #define FW_EQ_OFLD_CMD_EQSIZE_V(x) ((x) << FW_EQ_OFLD_CMD_EQSIZE_S)
1828
1829 /*
1830 * Macros for VIID parsing:
1831 * VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number
1832 */
1833
1834 #define FW_VIID_PFN_S 8
1835 #define FW_VIID_PFN_M 0x7
1836 #define FW_VIID_PFN_G(x) (((x) >> FW_VIID_PFN_S) & FW_VIID_PFN_M)
1837
1838 #define FW_VIID_VIVLD_S 7
1839 #define FW_VIID_VIVLD_M 0x1
1840 #define FW_VIID_VIVLD_G(x) (((x) >> FW_VIID_VIVLD_S) & FW_VIID_VIVLD_M)
1841
1842 #define FW_VIID_VIN_S 0
1843 #define FW_VIID_VIN_M 0x7F
1844 #define FW_VIID_VIN_G(x) (((x) >> FW_VIID_VIN_S) & FW_VIID_VIN_M)
1845
1846 struct fw_vi_cmd {
1847 __be32 op_to_vfn;
1848 __be32 alloc_to_len16;
1849 __be16 type_viid;
1850 u8 mac[6];
1851 u8 portid_pkd;
1852 u8 nmac;
1853 u8 nmac0[6];
1854 __be16 rsssize_pkd;
1855 u8 nmac1[6];
1856 __be16 idsiiq_pkd;
1857 u8 nmac2[6];
1858 __be16 idseiq_pkd;
1859 u8 nmac3[6];
1860 __be64 r9;
1861 __be64 r10;
1862 };
1863
1864 #define FW_VI_CMD_PFN_S 8
1865 #define FW_VI_CMD_PFN_V(x) ((x) << FW_VI_CMD_PFN_S)
1866
1867 #define FW_VI_CMD_VFN_S 0
1868 #define FW_VI_CMD_VFN_V(x) ((x) << FW_VI_CMD_VFN_S)
1869
1870 #define FW_VI_CMD_ALLOC_S 31
1871 #define FW_VI_CMD_ALLOC_V(x) ((x) << FW_VI_CMD_ALLOC_S)
1872 #define FW_VI_CMD_ALLOC_F FW_VI_CMD_ALLOC_V(1U)
1873
1874 #define FW_VI_CMD_FREE_S 30
1875 #define FW_VI_CMD_FREE_V(x) ((x) << FW_VI_CMD_FREE_S)
1876 #define FW_VI_CMD_FREE_F FW_VI_CMD_FREE_V(1U)
1877
1878 #define FW_VI_CMD_VIID_S 0
1879 #define FW_VI_CMD_VIID_M 0xfff
1880 #define FW_VI_CMD_VIID_V(x) ((x) << FW_VI_CMD_VIID_S)
1881 #define FW_VI_CMD_VIID_G(x) (((x) >> FW_VI_CMD_VIID_S) & FW_VI_CMD_VIID_M)
1882
1883 #define FW_VI_CMD_PORTID_S 4
1884 #define FW_VI_CMD_PORTID_M 0xf
1885 #define FW_VI_CMD_PORTID_V(x) ((x) << FW_VI_CMD_PORTID_S)
1886 #define FW_VI_CMD_PORTID_G(x) \
1887 (((x) >> FW_VI_CMD_PORTID_S) & FW_VI_CMD_PORTID_M)
1888
1889 #define FW_VI_CMD_RSSSIZE_S 0
1890 #define FW_VI_CMD_RSSSIZE_M 0x7ff
1891 #define FW_VI_CMD_RSSSIZE_G(x) \
1892 (((x) >> FW_VI_CMD_RSSSIZE_S) & FW_VI_CMD_RSSSIZE_M)
1893
1894 /* Special VI_MAC command index ids */
1895 #define FW_VI_MAC_ADD_MAC 0x3FF
1896 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE
1897 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD
1898 #define FW_CLS_TCAM_NUM_ENTRIES 336
1899
1900 enum fw_vi_mac_smac {
1901 FW_VI_MAC_MPS_TCAM_ENTRY,
1902 FW_VI_MAC_MPS_TCAM_ONLY,
1903 FW_VI_MAC_SMT_ONLY,
1904 FW_VI_MAC_SMT_AND_MPSTCAM
1905 };
1906
1907 enum fw_vi_mac_result {
1908 FW_VI_MAC_R_SUCCESS,
1909 FW_VI_MAC_R_F_NONEXISTENT_NOMEM,
1910 FW_VI_MAC_R_SMAC_FAIL,
1911 FW_VI_MAC_R_F_ACL_CHECK
1912 };
1913
1914 struct fw_vi_mac_cmd {
1915 __be32 op_to_viid;
1916 __be32 freemacs_to_len16;
1917 union fw_vi_mac {
1918 struct fw_vi_mac_exact {
1919 __be16 valid_to_idx;
1920 u8 macaddr[6];
1921 } exact[7];
1922 struct fw_vi_mac_hash {
1923 __be64 hashvec;
1924 } hash;
1925 } u;
1926 };
1927
1928 #define FW_VI_MAC_CMD_VIID_S 0
1929 #define FW_VI_MAC_CMD_VIID_V(x) ((x) << FW_VI_MAC_CMD_VIID_S)
1930
1931 #define FW_VI_MAC_CMD_FREEMACS_S 31
1932 #define FW_VI_MAC_CMD_FREEMACS_V(x) ((x) << FW_VI_MAC_CMD_FREEMACS_S)
1933
1934 #define FW_VI_MAC_CMD_HASHVECEN_S 23
1935 #define FW_VI_MAC_CMD_HASHVECEN_V(x) ((x) << FW_VI_MAC_CMD_HASHVECEN_S)
1936 #define FW_VI_MAC_CMD_HASHVECEN_F FW_VI_MAC_CMD_HASHVECEN_V(1U)
1937
1938 #define FW_VI_MAC_CMD_HASHUNIEN_S 22
1939 #define FW_VI_MAC_CMD_HASHUNIEN_V(x) ((x) << FW_VI_MAC_CMD_HASHUNIEN_S)
1940
1941 #define FW_VI_MAC_CMD_VALID_S 15
1942 #define FW_VI_MAC_CMD_VALID_V(x) ((x) << FW_VI_MAC_CMD_VALID_S)
1943 #define FW_VI_MAC_CMD_VALID_F FW_VI_MAC_CMD_VALID_V(1U)
1944
1945 #define FW_VI_MAC_CMD_PRIO_S 12
1946 #define FW_VI_MAC_CMD_PRIO_V(x) ((x) << FW_VI_MAC_CMD_PRIO_S)
1947
1948 #define FW_VI_MAC_CMD_SMAC_RESULT_S 10
1949 #define FW_VI_MAC_CMD_SMAC_RESULT_M 0x3
1950 #define FW_VI_MAC_CMD_SMAC_RESULT_V(x) ((x) << FW_VI_MAC_CMD_SMAC_RESULT_S)
1951 #define FW_VI_MAC_CMD_SMAC_RESULT_G(x) \
1952 (((x) >> FW_VI_MAC_CMD_SMAC_RESULT_S) & FW_VI_MAC_CMD_SMAC_RESULT_M)
1953
1954 #define FW_VI_MAC_CMD_IDX_S 0
1955 #define FW_VI_MAC_CMD_IDX_M 0x3ff
1956 #define FW_VI_MAC_CMD_IDX_V(x) ((x) << FW_VI_MAC_CMD_IDX_S)
1957 #define FW_VI_MAC_CMD_IDX_G(x) \
1958 (((x) >> FW_VI_MAC_CMD_IDX_S) & FW_VI_MAC_CMD_IDX_M)
1959
1960 #define FW_RXMODE_MTU_NO_CHG 65535
1961
1962 struct fw_vi_rxmode_cmd {
1963 __be32 op_to_viid;
1964 __be32 retval_len16;
1965 __be32 mtu_to_vlanexen;
1966 __be32 r4_lo;
1967 };
1968
1969 #define FW_VI_RXMODE_CMD_VIID_S 0
1970 #define FW_VI_RXMODE_CMD_VIID_V(x) ((x) << FW_VI_RXMODE_CMD_VIID_S)
1971
1972 #define FW_VI_RXMODE_CMD_MTU_S 16
1973 #define FW_VI_RXMODE_CMD_MTU_M 0xffff
1974 #define FW_VI_RXMODE_CMD_MTU_V(x) ((x) << FW_VI_RXMODE_CMD_MTU_S)
1975
1976 #define FW_VI_RXMODE_CMD_PROMISCEN_S 14
1977 #define FW_VI_RXMODE_CMD_PROMISCEN_M 0x3
1978 #define FW_VI_RXMODE_CMD_PROMISCEN_V(x) ((x) << FW_VI_RXMODE_CMD_PROMISCEN_S)
1979
1980 #define FW_VI_RXMODE_CMD_ALLMULTIEN_S 12
1981 #define FW_VI_RXMODE_CMD_ALLMULTIEN_M 0x3
1982 #define FW_VI_RXMODE_CMD_ALLMULTIEN_V(x) \
1983 ((x) << FW_VI_RXMODE_CMD_ALLMULTIEN_S)
1984
1985 #define FW_VI_RXMODE_CMD_BROADCASTEN_S 10
1986 #define FW_VI_RXMODE_CMD_BROADCASTEN_M 0x3
1987 #define FW_VI_RXMODE_CMD_BROADCASTEN_V(x) \
1988 ((x) << FW_VI_RXMODE_CMD_BROADCASTEN_S)
1989
1990 #define FW_VI_RXMODE_CMD_VLANEXEN_S 8
1991 #define FW_VI_RXMODE_CMD_VLANEXEN_M 0x3
1992 #define FW_VI_RXMODE_CMD_VLANEXEN_V(x) ((x) << FW_VI_RXMODE_CMD_VLANEXEN_S)
1993
1994 struct fw_vi_enable_cmd {
1995 __be32 op_to_viid;
1996 __be32 ien_to_len16;
1997 __be16 blinkdur;
1998 __be16 r3;
1999 __be32 r4;
2000 };
2001
2002 #define FW_VI_ENABLE_CMD_VIID_S 0
2003 #define FW_VI_ENABLE_CMD_VIID_V(x) ((x) << FW_VI_ENABLE_CMD_VIID_S)
2004
2005 #define FW_VI_ENABLE_CMD_IEN_S 31
2006 #define FW_VI_ENABLE_CMD_IEN_V(x) ((x) << FW_VI_ENABLE_CMD_IEN_S)
2007
2008 #define FW_VI_ENABLE_CMD_EEN_S 30
2009 #define FW_VI_ENABLE_CMD_EEN_V(x) ((x) << FW_VI_ENABLE_CMD_EEN_S)
2010
2011 #define FW_VI_ENABLE_CMD_LED_S 29
2012 #define FW_VI_ENABLE_CMD_LED_V(x) ((x) << FW_VI_ENABLE_CMD_LED_S)
2013 #define FW_VI_ENABLE_CMD_LED_F FW_VI_ENABLE_CMD_LED_V(1U)
2014
2015 #define FW_VI_ENABLE_CMD_DCB_INFO_S 28
2016 #define FW_VI_ENABLE_CMD_DCB_INFO_V(x) ((x) << FW_VI_ENABLE_CMD_DCB_INFO_S)
2017
2018 /* VI VF stats offset definitions */
2019 #define VI_VF_NUM_STATS 16
2020 enum fw_vi_stats_vf_index {
2021 FW_VI_VF_STAT_TX_BCAST_BYTES_IX,
2022 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX,
2023 FW_VI_VF_STAT_TX_MCAST_BYTES_IX,
2024 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX,
2025 FW_VI_VF_STAT_TX_UCAST_BYTES_IX,
2026 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX,
2027 FW_VI_VF_STAT_TX_DROP_FRAMES_IX,
2028 FW_VI_VF_STAT_TX_OFLD_BYTES_IX,
2029 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX,
2030 FW_VI_VF_STAT_RX_BCAST_BYTES_IX,
2031 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX,
2032 FW_VI_VF_STAT_RX_MCAST_BYTES_IX,
2033 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX,
2034 FW_VI_VF_STAT_RX_UCAST_BYTES_IX,
2035 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX,
2036 FW_VI_VF_STAT_RX_ERR_FRAMES_IX
2037 };
2038
2039 /* VI PF stats offset definitions */
2040 #define VI_PF_NUM_STATS 17
2041 enum fw_vi_stats_pf_index {
2042 FW_VI_PF_STAT_TX_BCAST_BYTES_IX,
2043 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX,
2044 FW_VI_PF_STAT_TX_MCAST_BYTES_IX,
2045 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX,
2046 FW_VI_PF_STAT_TX_UCAST_BYTES_IX,
2047 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX,
2048 FW_VI_PF_STAT_TX_OFLD_BYTES_IX,
2049 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX,
2050 FW_VI_PF_STAT_RX_BYTES_IX,
2051 FW_VI_PF_STAT_RX_FRAMES_IX,
2052 FW_VI_PF_STAT_RX_BCAST_BYTES_IX,
2053 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX,
2054 FW_VI_PF_STAT_RX_MCAST_BYTES_IX,
2055 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX,
2056 FW_VI_PF_STAT_RX_UCAST_BYTES_IX,
2057 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX,
2058 FW_VI_PF_STAT_RX_ERR_FRAMES_IX
2059 };
2060
2061 struct fw_vi_stats_cmd {
2062 __be32 op_to_viid;
2063 __be32 retval_len16;
2064 union fw_vi_stats {
2065 struct fw_vi_stats_ctl {
2066 __be16 nstats_ix;
2067 __be16 r6;
2068 __be32 r7;
2069 __be64 stat0;
2070 __be64 stat1;
2071 __be64 stat2;
2072 __be64 stat3;
2073 __be64 stat4;
2074 __be64 stat5;
2075 } ctl;
2076 struct fw_vi_stats_pf {
2077 __be64 tx_bcast_bytes;
2078 __be64 tx_bcast_frames;
2079 __be64 tx_mcast_bytes;
2080 __be64 tx_mcast_frames;
2081 __be64 tx_ucast_bytes;
2082 __be64 tx_ucast_frames;
2083 __be64 tx_offload_bytes;
2084 __be64 tx_offload_frames;
2085 __be64 rx_pf_bytes;
2086 __be64 rx_pf_frames;
2087 __be64 rx_bcast_bytes;
2088 __be64 rx_bcast_frames;
2089 __be64 rx_mcast_bytes;
2090 __be64 rx_mcast_frames;
2091 __be64 rx_ucast_bytes;
2092 __be64 rx_ucast_frames;
2093 __be64 rx_err_frames;
2094 } pf;
2095 struct fw_vi_stats_vf {
2096 __be64 tx_bcast_bytes;
2097 __be64 tx_bcast_frames;
2098 __be64 tx_mcast_bytes;
2099 __be64 tx_mcast_frames;
2100 __be64 tx_ucast_bytes;
2101 __be64 tx_ucast_frames;
2102 __be64 tx_drop_frames;
2103 __be64 tx_offload_bytes;
2104 __be64 tx_offload_frames;
2105 __be64 rx_bcast_bytes;
2106 __be64 rx_bcast_frames;
2107 __be64 rx_mcast_bytes;
2108 __be64 rx_mcast_frames;
2109 __be64 rx_ucast_bytes;
2110 __be64 rx_ucast_frames;
2111 __be64 rx_err_frames;
2112 } vf;
2113 } u;
2114 };
2115
2116 #define FW_VI_STATS_CMD_VIID_S 0
2117 #define FW_VI_STATS_CMD_VIID_V(x) ((x) << FW_VI_STATS_CMD_VIID_S)
2118
2119 #define FW_VI_STATS_CMD_NSTATS_S 12
2120 #define FW_VI_STATS_CMD_NSTATS_V(x) ((x) << FW_VI_STATS_CMD_NSTATS_S)
2121
2122 #define FW_VI_STATS_CMD_IX_S 0
2123 #define FW_VI_STATS_CMD_IX_V(x) ((x) << FW_VI_STATS_CMD_IX_S)
2124
2125 struct fw_acl_mac_cmd {
2126 __be32 op_to_vfn;
2127 __be32 en_to_len16;
2128 u8 nmac;
2129 u8 r3[7];
2130 __be16 r4;
2131 u8 macaddr0[6];
2132 __be16 r5;
2133 u8 macaddr1[6];
2134 __be16 r6;
2135 u8 macaddr2[6];
2136 __be16 r7;
2137 u8 macaddr3[6];
2138 };
2139
2140 #define FW_ACL_MAC_CMD_PFN_S 8
2141 #define FW_ACL_MAC_CMD_PFN_V(x) ((x) << FW_ACL_MAC_CMD_PFN_S)
2142
2143 #define FW_ACL_MAC_CMD_VFN_S 0
2144 #define FW_ACL_MAC_CMD_VFN_V(x) ((x) << FW_ACL_MAC_CMD_VFN_S)
2145
2146 #define FW_ACL_MAC_CMD_EN_S 31
2147 #define FW_ACL_MAC_CMD_EN_V(x) ((x) << FW_ACL_MAC_CMD_EN_S)
2148
2149 struct fw_acl_vlan_cmd {
2150 __be32 op_to_vfn;
2151 __be32 en_to_len16;
2152 u8 nvlan;
2153 u8 dropnovlan_fm;
2154 u8 r3_lo[6];
2155 __be16 vlanid[16];
2156 };
2157
2158 #define FW_ACL_VLAN_CMD_PFN_S 8
2159 #define FW_ACL_VLAN_CMD_PFN_V(x) ((x) << FW_ACL_VLAN_CMD_PFN_S)
2160
2161 #define FW_ACL_VLAN_CMD_VFN_S 0
2162 #define FW_ACL_VLAN_CMD_VFN_V(x) ((x) << FW_ACL_VLAN_CMD_VFN_S)
2163
2164 #define FW_ACL_VLAN_CMD_EN_S 31
2165 #define FW_ACL_VLAN_CMD_EN_V(x) ((x) << FW_ACL_VLAN_CMD_EN_S)
2166
2167 #define FW_ACL_VLAN_CMD_DROPNOVLAN_S 7
2168 #define FW_ACL_VLAN_CMD_DROPNOVLAN_V(x) ((x) << FW_ACL_VLAN_CMD_DROPNOVLAN_S)
2169
2170 #define FW_ACL_VLAN_CMD_FM_S 6
2171 #define FW_ACL_VLAN_CMD_FM_V(x) ((x) << FW_ACL_VLAN_CMD_FM_S)
2172
2173 enum fw_port_cap {
2174 FW_PORT_CAP_SPEED_100M = 0x0001,
2175 FW_PORT_CAP_SPEED_1G = 0x0002,
2176 FW_PORT_CAP_SPEED_2_5G = 0x0004,
2177 FW_PORT_CAP_SPEED_10G = 0x0008,
2178 FW_PORT_CAP_SPEED_40G = 0x0010,
2179 FW_PORT_CAP_SPEED_100G = 0x0020,
2180 FW_PORT_CAP_FC_RX = 0x0040,
2181 FW_PORT_CAP_FC_TX = 0x0080,
2182 FW_PORT_CAP_ANEG = 0x0100,
2183 FW_PORT_CAP_MDI_0 = 0x0200,
2184 FW_PORT_CAP_MDI_1 = 0x0400,
2185 FW_PORT_CAP_BEAN = 0x0800,
2186 FW_PORT_CAP_PMA_LPBK = 0x1000,
2187 FW_PORT_CAP_PCS_LPBK = 0x2000,
2188 FW_PORT_CAP_PHYXS_LPBK = 0x4000,
2189 FW_PORT_CAP_FAR_END_LPBK = 0x8000,
2190 };
2191
2192 enum fw_port_mdi {
2193 FW_PORT_CAP_MDI_UNCHANGED,
2194 FW_PORT_CAP_MDI_AUTO,
2195 FW_PORT_CAP_MDI_F_STRAIGHT,
2196 FW_PORT_CAP_MDI_F_CROSSOVER
2197 };
2198
2199 #define FW_PORT_CAP_MDI_S 9
2200 #define FW_PORT_CAP_MDI_V(x) ((x) << FW_PORT_CAP_MDI_S)
2201
2202 enum fw_port_action {
2203 FW_PORT_ACTION_L1_CFG = 0x0001,
2204 FW_PORT_ACTION_L2_CFG = 0x0002,
2205 FW_PORT_ACTION_GET_PORT_INFO = 0x0003,
2206 FW_PORT_ACTION_L2_PPP_CFG = 0x0004,
2207 FW_PORT_ACTION_L2_DCB_CFG = 0x0005,
2208 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006,
2209 FW_PORT_ACTION_DCB_READ_RECV = 0x0007,
2210 FW_PORT_ACTION_DCB_READ_DET = 0x0008,
2211 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010,
2212 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
2213 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
2214 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
2215 FW_PORT_ACTION_L1_LPBK = 0x0021,
2216 FW_PORT_ACTION_L1_PMA_LPBK = 0x0022,
2217 FW_PORT_ACTION_L1_PCS_LPBK = 0x0023,
2218 FW_PORT_ACTION_L1_PHYXS_CSIDE_LPBK = 0x0024,
2219 FW_PORT_ACTION_L1_PHYXS_ESIDE_LPBK = 0x0025,
2220 FW_PORT_ACTION_PHY_RESET = 0x0040,
2221 FW_PORT_ACTION_PMA_RESET = 0x0041,
2222 FW_PORT_ACTION_PCS_RESET = 0x0042,
2223 FW_PORT_ACTION_PHYXS_RESET = 0x0043,
2224 FW_PORT_ACTION_DTEXS_REEST = 0x0044,
2225 FW_PORT_ACTION_AN_RESET = 0x0045
2226 };
2227
2228 enum fw_port_l2cfg_ctlbf {
2229 FW_PORT_L2_CTLBF_OVLAN0 = 0x01,
2230 FW_PORT_L2_CTLBF_OVLAN1 = 0x02,
2231 FW_PORT_L2_CTLBF_OVLAN2 = 0x04,
2232 FW_PORT_L2_CTLBF_OVLAN3 = 0x08,
2233 FW_PORT_L2_CTLBF_IVLAN = 0x10,
2234 FW_PORT_L2_CTLBF_TXIPG = 0x20
2235 };
2236
2237 enum fw_port_dcb_versions {
2238 FW_PORT_DCB_VER_UNKNOWN,
2239 FW_PORT_DCB_VER_CEE1D0,
2240 FW_PORT_DCB_VER_CEE1D01,
2241 FW_PORT_DCB_VER_IEEE,
2242 FW_PORT_DCB_VER_AUTO = 7
2243 };
2244
2245 enum fw_port_dcb_cfg {
2246 FW_PORT_DCB_CFG_PG = 0x01,
2247 FW_PORT_DCB_CFG_PFC = 0x02,
2248 FW_PORT_DCB_CFG_APPL = 0x04
2249 };
2250
2251 enum fw_port_dcb_cfg_rc {
2252 FW_PORT_DCB_CFG_SUCCESS = 0x0,
2253 FW_PORT_DCB_CFG_ERROR = 0x1
2254 };
2255
2256 enum fw_port_dcb_type {
2257 FW_PORT_DCB_TYPE_PGID = 0x00,
2258 FW_PORT_DCB_TYPE_PGRATE = 0x01,
2259 FW_PORT_DCB_TYPE_PRIORATE = 0x02,
2260 FW_PORT_DCB_TYPE_PFC = 0x03,
2261 FW_PORT_DCB_TYPE_APP_ID = 0x04,
2262 FW_PORT_DCB_TYPE_CONTROL = 0x05,
2263 };
2264
2265 enum fw_port_dcb_feature_state {
2266 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
2267 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
2268 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
2269 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
2270 };
2271
2272 struct fw_port_cmd {
2273 __be32 op_to_portid;
2274 __be32 action_to_len16;
2275 union fw_port {
2276 struct fw_port_l1cfg {
2277 __be32 rcap;
2278 __be32 r;
2279 } l1cfg;
2280 struct fw_port_l2cfg {
2281 __u8 ctlbf;
2282 __u8 ovlan3_to_ivlan0;
2283 __be16 ivlantype;
2284 __be16 txipg_force_pinfo;
2285 __be16 mtu;
2286 __be16 ovlan0mask;
2287 __be16 ovlan0type;
2288 __be16 ovlan1mask;
2289 __be16 ovlan1type;
2290 __be16 ovlan2mask;
2291 __be16 ovlan2type;
2292 __be16 ovlan3mask;
2293 __be16 ovlan3type;
2294 } l2cfg;
2295 struct fw_port_info {
2296 __be32 lstatus_to_modtype;
2297 __be16 pcap;
2298 __be16 acap;
2299 __be16 mtu;
2300 __u8 cbllen;
2301 __u8 auxlinfo;
2302 __u8 dcbxdis_pkd;
2303 __u8 r8_lo[3];
2304 __be64 r9;
2305 } info;
2306 struct fw_port_diags {
2307 __u8 diagop;
2308 __u8 r[3];
2309 __be32 diagval;
2310 } diags;
2311 union fw_port_dcb {
2312 struct fw_port_dcb_pgid {
2313 __u8 type;
2314 __u8 apply_pkd;
2315 __u8 r10_lo[2];
2316 __be32 pgid;
2317 __be64 r11;
2318 } pgid;
2319 struct fw_port_dcb_pgrate {
2320 __u8 type;
2321 __u8 apply_pkd;
2322 __u8 r10_lo[5];
2323 __u8 num_tcs_supported;
2324 __u8 pgrate[8];
2325 __u8 tsa[8];
2326 } pgrate;
2327 struct fw_port_dcb_priorate {
2328 __u8 type;
2329 __u8 apply_pkd;
2330 __u8 r10_lo[6];
2331 __u8 strict_priorate[8];
2332 } priorate;
2333 struct fw_port_dcb_pfc {
2334 __u8 type;
2335 __u8 pfcen;
2336 __u8 r10[5];
2337 __u8 max_pfc_tcs;
2338 __be64 r11;
2339 } pfc;
2340 struct fw_port_app_priority {
2341 __u8 type;
2342 __u8 r10[2];
2343 __u8 idx;
2344 __u8 user_prio_map;
2345 __u8 sel_field;
2346 __be16 protocolid;
2347 __be64 r12;
2348 } app_priority;
2349 struct fw_port_dcb_control {
2350 __u8 type;
2351 __u8 all_syncd_pkd;
2352 __be16 dcb_version_to_app_state;
2353 __be32 r11;
2354 __be64 r12;
2355 } control;
2356 } dcb;
2357 } u;
2358 };
2359
2360 #define FW_PORT_CMD_READ_S 22
2361 #define FW_PORT_CMD_READ_V(x) ((x) << FW_PORT_CMD_READ_S)
2362 #define FW_PORT_CMD_READ_F FW_PORT_CMD_READ_V(1U)
2363
2364 #define FW_PORT_CMD_PORTID_S 0
2365 #define FW_PORT_CMD_PORTID_M 0xf
2366 #define FW_PORT_CMD_PORTID_V(x) ((x) << FW_PORT_CMD_PORTID_S)
2367 #define FW_PORT_CMD_PORTID_G(x) \
2368 (((x) >> FW_PORT_CMD_PORTID_S) & FW_PORT_CMD_PORTID_M)
2369
2370 #define FW_PORT_CMD_ACTION_S 16
2371 #define FW_PORT_CMD_ACTION_M 0xffff
2372 #define FW_PORT_CMD_ACTION_V(x) ((x) << FW_PORT_CMD_ACTION_S)
2373 #define FW_PORT_CMD_ACTION_G(x) \
2374 (((x) >> FW_PORT_CMD_ACTION_S) & FW_PORT_CMD_ACTION_M)
2375
2376 #define FW_PORT_CMD_OVLAN3_S 7
2377 #define FW_PORT_CMD_OVLAN3_V(x) ((x) << FW_PORT_CMD_OVLAN3_S)
2378
2379 #define FW_PORT_CMD_OVLAN2_S 6
2380 #define FW_PORT_CMD_OVLAN2_V(x) ((x) << FW_PORT_CMD_OVLAN2_S)
2381
2382 #define FW_PORT_CMD_OVLAN1_S 5
2383 #define FW_PORT_CMD_OVLAN1_V(x) ((x) << FW_PORT_CMD_OVLAN1_S)
2384
2385 #define FW_PORT_CMD_OVLAN0_S 4
2386 #define FW_PORT_CMD_OVLAN0_V(x) ((x) << FW_PORT_CMD_OVLAN0_S)
2387
2388 #define FW_PORT_CMD_IVLAN0_S 3
2389 #define FW_PORT_CMD_IVLAN0_V(x) ((x) << FW_PORT_CMD_IVLAN0_S)
2390
2391 #define FW_PORT_CMD_TXIPG_S 3
2392 #define FW_PORT_CMD_TXIPG_V(x) ((x) << FW_PORT_CMD_TXIPG_S)
2393
2394 #define FW_PORT_CMD_LSTATUS_S 31
2395 #define FW_PORT_CMD_LSTATUS_M 0x1
2396 #define FW_PORT_CMD_LSTATUS_V(x) ((x) << FW_PORT_CMD_LSTATUS_S)
2397 #define FW_PORT_CMD_LSTATUS_G(x) \
2398 (((x) >> FW_PORT_CMD_LSTATUS_S) & FW_PORT_CMD_LSTATUS_M)
2399 #define FW_PORT_CMD_LSTATUS_F FW_PORT_CMD_LSTATUS_V(1U)
2400
2401 #define FW_PORT_CMD_LSPEED_S 24
2402 #define FW_PORT_CMD_LSPEED_M 0x3f
2403 #define FW_PORT_CMD_LSPEED_V(x) ((x) << FW_PORT_CMD_LSPEED_S)
2404 #define FW_PORT_CMD_LSPEED_G(x) \
2405 (((x) >> FW_PORT_CMD_LSPEED_S) & FW_PORT_CMD_LSPEED_M)
2406
2407 #define FW_PORT_CMD_TXPAUSE_S 23
2408 #define FW_PORT_CMD_TXPAUSE_V(x) ((x) << FW_PORT_CMD_TXPAUSE_S)
2409 #define FW_PORT_CMD_TXPAUSE_F FW_PORT_CMD_TXPAUSE_V(1U)
2410
2411 #define FW_PORT_CMD_RXPAUSE_S 22
2412 #define FW_PORT_CMD_RXPAUSE_V(x) ((x) << FW_PORT_CMD_RXPAUSE_S)
2413 #define FW_PORT_CMD_RXPAUSE_F FW_PORT_CMD_RXPAUSE_V(1U)
2414
2415 #define FW_PORT_CMD_MDIOCAP_S 21
2416 #define FW_PORT_CMD_MDIOCAP_V(x) ((x) << FW_PORT_CMD_MDIOCAP_S)
2417 #define FW_PORT_CMD_MDIOCAP_F FW_PORT_CMD_MDIOCAP_V(1U)
2418
2419 #define FW_PORT_CMD_MDIOADDR_S 16
2420 #define FW_PORT_CMD_MDIOADDR_M 0x1f
2421 #define FW_PORT_CMD_MDIOADDR_G(x) \
2422 (((x) >> FW_PORT_CMD_MDIOADDR_S) & FW_PORT_CMD_MDIOADDR_M)
2423
2424 #define FW_PORT_CMD_LPTXPAUSE_S 15
2425 #define FW_PORT_CMD_LPTXPAUSE_V(x) ((x) << FW_PORT_CMD_LPTXPAUSE_S)
2426 #define FW_PORT_CMD_LPTXPAUSE_F FW_PORT_CMD_LPTXPAUSE_V(1U)
2427
2428 #define FW_PORT_CMD_LPRXPAUSE_S 14
2429 #define FW_PORT_CMD_LPRXPAUSE_V(x) ((x) << FW_PORT_CMD_LPRXPAUSE_S)
2430 #define FW_PORT_CMD_LPRXPAUSE_F FW_PORT_CMD_LPRXPAUSE_V(1U)
2431
2432 #define FW_PORT_CMD_PTYPE_S 8
2433 #define FW_PORT_CMD_PTYPE_M 0x1f
2434 #define FW_PORT_CMD_PTYPE_G(x) \
2435 (((x) >> FW_PORT_CMD_PTYPE_S) & FW_PORT_CMD_PTYPE_M)
2436
2437 #define FW_PORT_CMD_MODTYPE_S 0
2438 #define FW_PORT_CMD_MODTYPE_M 0x1f
2439 #define FW_PORT_CMD_MODTYPE_V(x) ((x) << FW_PORT_CMD_MODTYPE_S)
2440 #define FW_PORT_CMD_MODTYPE_G(x) \
2441 (((x) >> FW_PORT_CMD_MODTYPE_S) & FW_PORT_CMD_MODTYPE_M)
2442
2443 #define FW_PORT_CMD_DCBXDIS_S 7
2444 #define FW_PORT_CMD_DCBXDIS_V(x) ((x) << FW_PORT_CMD_DCBXDIS_S)
2445 #define FW_PORT_CMD_DCBXDIS_F FW_PORT_CMD_DCBXDIS_V(1U)
2446
2447 #define FW_PORT_CMD_APPLY_S 7
2448 #define FW_PORT_CMD_APPLY_V(x) ((x) << FW_PORT_CMD_APPLY_S)
2449 #define FW_PORT_CMD_APPLY_F FW_PORT_CMD_APPLY_V(1U)
2450
2451 #define FW_PORT_CMD_ALL_SYNCD_S 7
2452 #define FW_PORT_CMD_ALL_SYNCD_V(x) ((x) << FW_PORT_CMD_ALL_SYNCD_S)
2453 #define FW_PORT_CMD_ALL_SYNCD_F FW_PORT_CMD_ALL_SYNCD_V(1U)
2454
2455 #define FW_PORT_CMD_DCB_VERSION_S 12
2456 #define FW_PORT_CMD_DCB_VERSION_M 0x7
2457 #define FW_PORT_CMD_DCB_VERSION_G(x) \
2458 (((x) >> FW_PORT_CMD_DCB_VERSION_S) & FW_PORT_CMD_DCB_VERSION_M)
2459
2460 enum fw_port_type {
2461 FW_PORT_TYPE_FIBER_XFI,
2462 FW_PORT_TYPE_FIBER_XAUI,
2463 FW_PORT_TYPE_BT_SGMII,
2464 FW_PORT_TYPE_BT_XFI,
2465 FW_PORT_TYPE_BT_XAUI,
2466 FW_PORT_TYPE_KX4,
2467 FW_PORT_TYPE_CX4,
2468 FW_PORT_TYPE_KX,
2469 FW_PORT_TYPE_KR,
2470 FW_PORT_TYPE_SFP,
2471 FW_PORT_TYPE_BP_AP,
2472 FW_PORT_TYPE_BP4_AP,
2473 FW_PORT_TYPE_QSFP_10G,
2474 FW_PORT_TYPE_QSA,
2475 FW_PORT_TYPE_QSFP,
2476 FW_PORT_TYPE_BP40_BA,
2477
2478 FW_PORT_TYPE_NONE = FW_PORT_CMD_PTYPE_M
2479 };
2480
2481 enum fw_port_module_type {
2482 FW_PORT_MOD_TYPE_NA,
2483 FW_PORT_MOD_TYPE_LR,
2484 FW_PORT_MOD_TYPE_SR,
2485 FW_PORT_MOD_TYPE_ER,
2486 FW_PORT_MOD_TYPE_TWINAX_PASSIVE,
2487 FW_PORT_MOD_TYPE_TWINAX_ACTIVE,
2488 FW_PORT_MOD_TYPE_LRM,
2489 FW_PORT_MOD_TYPE_ERROR = FW_PORT_CMD_MODTYPE_M - 3,
2490 FW_PORT_MOD_TYPE_UNKNOWN = FW_PORT_CMD_MODTYPE_M - 2,
2491 FW_PORT_MOD_TYPE_NOTSUPPORTED = FW_PORT_CMD_MODTYPE_M - 1,
2492
2493 FW_PORT_MOD_TYPE_NONE = FW_PORT_CMD_MODTYPE_M
2494 };
2495
2496 enum fw_port_mod_sub_type {
2497 FW_PORT_MOD_SUB_TYPE_NA,
2498 FW_PORT_MOD_SUB_TYPE_MV88E114X = 0x1,
2499 FW_PORT_MOD_SUB_TYPE_TN8022 = 0x2,
2500 FW_PORT_MOD_SUB_TYPE_AQ1202 = 0x3,
2501 FW_PORT_MOD_SUB_TYPE_88x3120 = 0x4,
2502 FW_PORT_MOD_SUB_TYPE_BCM84834 = 0x5,
2503 FW_PORT_MOD_SUB_TYPE_BT_VSC8634 = 0x8,
2504
2505 /* The following will never been in the VPD. They are TWINAX cable
2506 * lengths decoded from SFP+ module i2c PROMs. These should
2507 * almost certainly go somewhere else ...
2508 */
2509 FW_PORT_MOD_SUB_TYPE_TWINAX_1 = 0x9,
2510 FW_PORT_MOD_SUB_TYPE_TWINAX_3 = 0xA,
2511 FW_PORT_MOD_SUB_TYPE_TWINAX_5 = 0xB,
2512 FW_PORT_MOD_SUB_TYPE_TWINAX_7 = 0xC,
2513 };
2514
2515 /* port stats */
2516 #define FW_NUM_PORT_STATS 50
2517 #define FW_NUM_PORT_TX_STATS 23
2518 #define FW_NUM_PORT_RX_STATS 27
2519
2520 enum fw_port_stats_tx_index {
2521 FW_STAT_TX_PORT_BYTES_IX,
2522 FW_STAT_TX_PORT_FRAMES_IX,
2523 FW_STAT_TX_PORT_BCAST_IX,
2524 FW_STAT_TX_PORT_MCAST_IX,
2525 FW_STAT_TX_PORT_UCAST_IX,
2526 FW_STAT_TX_PORT_ERROR_IX,
2527 FW_STAT_TX_PORT_64B_IX,
2528 FW_STAT_TX_PORT_65B_127B_IX,
2529 FW_STAT_TX_PORT_128B_255B_IX,
2530 FW_STAT_TX_PORT_256B_511B_IX,
2531 FW_STAT_TX_PORT_512B_1023B_IX,
2532 FW_STAT_TX_PORT_1024B_1518B_IX,
2533 FW_STAT_TX_PORT_1519B_MAX_IX,
2534 FW_STAT_TX_PORT_DROP_IX,
2535 FW_STAT_TX_PORT_PAUSE_IX,
2536 FW_STAT_TX_PORT_PPP0_IX,
2537 FW_STAT_TX_PORT_PPP1_IX,
2538 FW_STAT_TX_PORT_PPP2_IX,
2539 FW_STAT_TX_PORT_PPP3_IX,
2540 FW_STAT_TX_PORT_PPP4_IX,
2541 FW_STAT_TX_PORT_PPP5_IX,
2542 FW_STAT_TX_PORT_PPP6_IX,
2543 FW_STAT_TX_PORT_PPP7_IX
2544 };
2545
2546 enum fw_port_stat_rx_index {
2547 FW_STAT_RX_PORT_BYTES_IX,
2548 FW_STAT_RX_PORT_FRAMES_IX,
2549 FW_STAT_RX_PORT_BCAST_IX,
2550 FW_STAT_RX_PORT_MCAST_IX,
2551 FW_STAT_RX_PORT_UCAST_IX,
2552 FW_STAT_RX_PORT_MTU_ERROR_IX,
2553 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX,
2554 FW_STAT_RX_PORT_CRC_ERROR_IX,
2555 FW_STAT_RX_PORT_LEN_ERROR_IX,
2556 FW_STAT_RX_PORT_SYM_ERROR_IX,
2557 FW_STAT_RX_PORT_64B_IX,
2558 FW_STAT_RX_PORT_65B_127B_IX,
2559 FW_STAT_RX_PORT_128B_255B_IX,
2560 FW_STAT_RX_PORT_256B_511B_IX,
2561 FW_STAT_RX_PORT_512B_1023B_IX,
2562 FW_STAT_RX_PORT_1024B_1518B_IX,
2563 FW_STAT_RX_PORT_1519B_MAX_IX,
2564 FW_STAT_RX_PORT_PAUSE_IX,
2565 FW_STAT_RX_PORT_PPP0_IX,
2566 FW_STAT_RX_PORT_PPP1_IX,
2567 FW_STAT_RX_PORT_PPP2_IX,
2568 FW_STAT_RX_PORT_PPP3_IX,
2569 FW_STAT_RX_PORT_PPP4_IX,
2570 FW_STAT_RX_PORT_PPP5_IX,
2571 FW_STAT_RX_PORT_PPP6_IX,
2572 FW_STAT_RX_PORT_PPP7_IX,
2573 FW_STAT_RX_PORT_LESS_64B_IX
2574 };
2575
2576 struct fw_port_stats_cmd {
2577 __be32 op_to_portid;
2578 __be32 retval_len16;
2579 union fw_port_stats {
2580 struct fw_port_stats_ctl {
2581 u8 nstats_bg_bm;
2582 u8 tx_ix;
2583 __be16 r6;
2584 __be32 r7;
2585 __be64 stat0;
2586 __be64 stat1;
2587 __be64 stat2;
2588 __be64 stat3;
2589 __be64 stat4;
2590 __be64 stat5;
2591 } ctl;
2592 struct fw_port_stats_all {
2593 __be64 tx_bytes;
2594 __be64 tx_frames;
2595 __be64 tx_bcast;
2596 __be64 tx_mcast;
2597 __be64 tx_ucast;
2598 __be64 tx_error;
2599 __be64 tx_64b;
2600 __be64 tx_65b_127b;
2601 __be64 tx_128b_255b;
2602 __be64 tx_256b_511b;
2603 __be64 tx_512b_1023b;
2604 __be64 tx_1024b_1518b;
2605 __be64 tx_1519b_max;
2606 __be64 tx_drop;
2607 __be64 tx_pause;
2608 __be64 tx_ppp0;
2609 __be64 tx_ppp1;
2610 __be64 tx_ppp2;
2611 __be64 tx_ppp3;
2612 __be64 tx_ppp4;
2613 __be64 tx_ppp5;
2614 __be64 tx_ppp6;
2615 __be64 tx_ppp7;
2616 __be64 rx_bytes;
2617 __be64 rx_frames;
2618 __be64 rx_bcast;
2619 __be64 rx_mcast;
2620 __be64 rx_ucast;
2621 __be64 rx_mtu_error;
2622 __be64 rx_mtu_crc_error;
2623 __be64 rx_crc_error;
2624 __be64 rx_len_error;
2625 __be64 rx_sym_error;
2626 __be64 rx_64b;
2627 __be64 rx_65b_127b;
2628 __be64 rx_128b_255b;
2629 __be64 rx_256b_511b;
2630 __be64 rx_512b_1023b;
2631 __be64 rx_1024b_1518b;
2632 __be64 rx_1519b_max;
2633 __be64 rx_pause;
2634 __be64 rx_ppp0;
2635 __be64 rx_ppp1;
2636 __be64 rx_ppp2;
2637 __be64 rx_ppp3;
2638 __be64 rx_ppp4;
2639 __be64 rx_ppp5;
2640 __be64 rx_ppp6;
2641 __be64 rx_ppp7;
2642 __be64 rx_less_64b;
2643 __be64 rx_bg_drop;
2644 __be64 rx_bg_trunc;
2645 } all;
2646 } u;
2647 };
2648
2649 /* port loopback stats */
2650 #define FW_NUM_LB_STATS 16
2651 enum fw_port_lb_stats_index {
2652 FW_STAT_LB_PORT_BYTES_IX,
2653 FW_STAT_LB_PORT_FRAMES_IX,
2654 FW_STAT_LB_PORT_BCAST_IX,
2655 FW_STAT_LB_PORT_MCAST_IX,
2656 FW_STAT_LB_PORT_UCAST_IX,
2657 FW_STAT_LB_PORT_ERROR_IX,
2658 FW_STAT_LB_PORT_64B_IX,
2659 FW_STAT_LB_PORT_65B_127B_IX,
2660 FW_STAT_LB_PORT_128B_255B_IX,
2661 FW_STAT_LB_PORT_256B_511B_IX,
2662 FW_STAT_LB_PORT_512B_1023B_IX,
2663 FW_STAT_LB_PORT_1024B_1518B_IX,
2664 FW_STAT_LB_PORT_1519B_MAX_IX,
2665 FW_STAT_LB_PORT_DROP_FRAMES_IX
2666 };
2667
2668 struct fw_port_lb_stats_cmd {
2669 __be32 op_to_lbport;
2670 __be32 retval_len16;
2671 union fw_port_lb_stats {
2672 struct fw_port_lb_stats_ctl {
2673 u8 nstats_bg_bm;
2674 u8 ix_pkd;
2675 __be16 r6;
2676 __be32 r7;
2677 __be64 stat0;
2678 __be64 stat1;
2679 __be64 stat2;
2680 __be64 stat3;
2681 __be64 stat4;
2682 __be64 stat5;
2683 } ctl;
2684 struct fw_port_lb_stats_all {
2685 __be64 tx_bytes;
2686 __be64 tx_frames;
2687 __be64 tx_bcast;
2688 __be64 tx_mcast;
2689 __be64 tx_ucast;
2690 __be64 tx_error;
2691 __be64 tx_64b;
2692 __be64 tx_65b_127b;
2693 __be64 tx_128b_255b;
2694 __be64 tx_256b_511b;
2695 __be64 tx_512b_1023b;
2696 __be64 tx_1024b_1518b;
2697 __be64 tx_1519b_max;
2698 __be64 rx_lb_drop;
2699 __be64 rx_lb_trunc;
2700 } all;
2701 } u;
2702 };
2703
2704 struct fw_rss_ind_tbl_cmd {
2705 __be32 op_to_viid;
2706 __be32 retval_len16;
2707 __be16 niqid;
2708 __be16 startidx;
2709 __be32 r3;
2710 __be32 iq0_to_iq2;
2711 __be32 iq3_to_iq5;
2712 __be32 iq6_to_iq8;
2713 __be32 iq9_to_iq11;
2714 __be32 iq12_to_iq14;
2715 __be32 iq15_to_iq17;
2716 __be32 iq18_to_iq20;
2717 __be32 iq21_to_iq23;
2718 __be32 iq24_to_iq26;
2719 __be32 iq27_to_iq29;
2720 __be32 iq30_iq31;
2721 __be32 r15_lo;
2722 };
2723
2724 #define FW_RSS_IND_TBL_CMD_VIID_S 0
2725 #define FW_RSS_IND_TBL_CMD_VIID_V(x) ((x) << FW_RSS_IND_TBL_CMD_VIID_S)
2726
2727 #define FW_RSS_IND_TBL_CMD_IQ0_S 20
2728 #define FW_RSS_IND_TBL_CMD_IQ0_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ0_S)
2729
2730 #define FW_RSS_IND_TBL_CMD_IQ1_S 10
2731 #define FW_RSS_IND_TBL_CMD_IQ1_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ1_S)
2732
2733 #define FW_RSS_IND_TBL_CMD_IQ2_S 0
2734 #define FW_RSS_IND_TBL_CMD_IQ2_V(x) ((x) << FW_RSS_IND_TBL_CMD_IQ2_S)
2735
2736 struct fw_rss_glb_config_cmd {
2737 __be32 op_to_write;
2738 __be32 retval_len16;
2739 union fw_rss_glb_config {
2740 struct fw_rss_glb_config_manual {
2741 __be32 mode_pkd;
2742 __be32 r3;
2743 __be64 r4;
2744 __be64 r5;
2745 } manual;
2746 struct fw_rss_glb_config_basicvirtual {
2747 __be32 mode_pkd;
2748 __be32 synmapen_to_hashtoeplitz;
2749 __be64 r8;
2750 __be64 r9;
2751 } basicvirtual;
2752 } u;
2753 };
2754
2755 #define FW_RSS_GLB_CONFIG_CMD_MODE_S 28
2756 #define FW_RSS_GLB_CONFIG_CMD_MODE_M 0xf
2757 #define FW_RSS_GLB_CONFIG_CMD_MODE_V(x) ((x) << FW_RSS_GLB_CONFIG_CMD_MODE_S)
2758 #define FW_RSS_GLB_CONFIG_CMD_MODE_G(x) \
2759 (((x) >> FW_RSS_GLB_CONFIG_CMD_MODE_S) & FW_RSS_GLB_CONFIG_CMD_MODE_M)
2760
2761 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0
2762 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1
2763
2764 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S 8
2765 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(x) \
2766 ((x) << FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_S)
2767 #define FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_F \
2768 FW_RSS_GLB_CONFIG_CMD_SYNMAPEN_V(1U)
2769
2770 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S 7
2771 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(x) \
2772 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_S)
2773 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_F \
2774 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6_V(1U)
2775
2776 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S 6
2777 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(x) \
2778 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_S)
2779 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_F \
2780 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6_V(1U)
2781
2782 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S 5
2783 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(x) \
2784 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_S)
2785 #define FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_F \
2786 FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4_V(1U)
2787
2788 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S 4
2789 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(x) \
2790 ((x) << FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_S)
2791 #define FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_F \
2792 FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4_V(1U)
2793
2794 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S 3
2795 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(x) \
2796 ((x) << FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_S)
2797 #define FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_F \
2798 FW_RSS_GLB_CONFIG_CMD_OFDMAPEN_V(1U)
2799
2800 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S 2
2801 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(x) \
2802 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_S)
2803 #define FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_F \
2804 FW_RSS_GLB_CONFIG_CMD_TNLMAPEN_V(1U)
2805
2806 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S 1
2807 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(x) \
2808 ((x) << FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_S)
2809 #define FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_F \
2810 FW_RSS_GLB_CONFIG_CMD_TNLALLLKP_V(1U)
2811
2812 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S 0
2813 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(x) \
2814 ((x) << FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_S)
2815 #define FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_F \
2816 FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ_V(1U)
2817
2818 struct fw_rss_vi_config_cmd {
2819 __be32 op_to_viid;
2820 #define FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << 0)
2821 __be32 retval_len16;
2822 union fw_rss_vi_config {
2823 struct fw_rss_vi_config_manual {
2824 __be64 r3;
2825 __be64 r4;
2826 __be64 r5;
2827 } manual;
2828 struct fw_rss_vi_config_basicvirtual {
2829 __be32 r6;
2830 __be32 defaultq_to_udpen;
2831 __be64 r9;
2832 __be64 r10;
2833 } basicvirtual;
2834 } u;
2835 };
2836
2837 #define FW_RSS_VI_CONFIG_CMD_VIID_S 0
2838 #define FW_RSS_VI_CONFIG_CMD_VIID_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_VIID_S)
2839
2840 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S 16
2841 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M 0x3ff
2842 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_V(x) \
2843 ((x) << FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S)
2844 #define FW_RSS_VI_CONFIG_CMD_DEFAULTQ_G(x) \
2845 (((x) >> FW_RSS_VI_CONFIG_CMD_DEFAULTQ_S) & \
2846 FW_RSS_VI_CONFIG_CMD_DEFAULTQ_M)
2847
2848 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S 4
2849 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(x) \
2850 ((x) << FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_S)
2851 #define FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_F \
2852 FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN_V(1U)
2853
2854 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S 3
2855 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(x) \
2856 ((x) << FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_S)
2857 #define FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_F \
2858 FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN_V(1U)
2859
2860 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S 2
2861 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(x) \
2862 ((x) << FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_S)
2863 #define FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_F \
2864 FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN_V(1U)
2865
2866 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S 1
2867 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(x) \
2868 ((x) << FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_S)
2869 #define FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_F \
2870 FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN_V(1U)
2871
2872 #define FW_RSS_VI_CONFIG_CMD_UDPEN_S 0
2873 #define FW_RSS_VI_CONFIG_CMD_UDPEN_V(x) ((x) << FW_RSS_VI_CONFIG_CMD_UDPEN_S)
2874 #define FW_RSS_VI_CONFIG_CMD_UDPEN_F FW_RSS_VI_CONFIG_CMD_UDPEN_V(1U)
2875
2876 struct fw_clip_cmd {
2877 __be32 op_to_write;
2878 __be32 alloc_to_len16;
2879 __be64 ip_hi;
2880 __be64 ip_lo;
2881 __be32 r4[2];
2882 };
2883
2884 #define FW_CLIP_CMD_ALLOC_S 31
2885 #define FW_CLIP_CMD_ALLOC_V(x) ((x) << FW_CLIP_CMD_ALLOC_S)
2886 #define FW_CLIP_CMD_ALLOC_F FW_CLIP_CMD_ALLOC_V(1U)
2887
2888 #define FW_CLIP_CMD_FREE_S 30
2889 #define FW_CLIP_CMD_FREE_V(x) ((x) << FW_CLIP_CMD_FREE_S)
2890 #define FW_CLIP_CMD_FREE_F FW_CLIP_CMD_FREE_V(1U)
2891
2892 enum fw_error_type {
2893 FW_ERROR_TYPE_EXCEPTION = 0x0,
2894 FW_ERROR_TYPE_HWMODULE = 0x1,
2895 FW_ERROR_TYPE_WR = 0x2,
2896 FW_ERROR_TYPE_ACL = 0x3,
2897 };
2898
2899 struct fw_error_cmd {
2900 __be32 op_to_type;
2901 __be32 len16_pkd;
2902 union fw_error {
2903 struct fw_error_exception {
2904 __be32 info[6];
2905 } exception;
2906 struct fw_error_hwmodule {
2907 __be32 regaddr;
2908 __be32 regval;
2909 } hwmodule;
2910 struct fw_error_wr {
2911 __be16 cidx;
2912 __be16 pfn_vfn;
2913 __be32 eqid;
2914 u8 wrhdr[16];
2915 } wr;
2916 struct fw_error_acl {
2917 __be16 cidx;
2918 __be16 pfn_vfn;
2919 __be32 eqid;
2920 __be16 mv_pkd;
2921 u8 val[6];
2922 __be64 r4;
2923 } acl;
2924 } u;
2925 };
2926
2927 struct fw_debug_cmd {
2928 __be32 op_type;
2929 __be32 len16_pkd;
2930 union fw_debug {
2931 struct fw_debug_assert {
2932 __be32 fcid;
2933 __be32 line;
2934 __be32 x;
2935 __be32 y;
2936 u8 filename_0_7[8];
2937 u8 filename_8_15[8];
2938 __be64 r3;
2939 } assert;
2940 struct fw_debug_prt {
2941 __be16 dprtstridx;
2942 __be16 r3[3];
2943 __be32 dprtstrparam0;
2944 __be32 dprtstrparam1;
2945 __be32 dprtstrparam2;
2946 __be32 dprtstrparam3;
2947 } prt;
2948 } u;
2949 };
2950
2951 #define FW_DEBUG_CMD_TYPE_S 0
2952 #define FW_DEBUG_CMD_TYPE_M 0xff
2953 #define FW_DEBUG_CMD_TYPE_G(x) \
2954 (((x) >> FW_DEBUG_CMD_TYPE_S) & FW_DEBUG_CMD_TYPE_M)
2955
2956 #define PCIE_FW_ERR_S 31
2957 #define PCIE_FW_ERR_V(x) ((x) << PCIE_FW_ERR_S)
2958 #define PCIE_FW_ERR_F PCIE_FW_ERR_V(1U)
2959
2960 #define PCIE_FW_INIT_S 30
2961 #define PCIE_FW_INIT_V(x) ((x) << PCIE_FW_INIT_S)
2962 #define PCIE_FW_INIT_F PCIE_FW_INIT_V(1U)
2963
2964 #define PCIE_FW_HALT_S 29
2965 #define PCIE_FW_HALT_V(x) ((x) << PCIE_FW_HALT_S)
2966 #define PCIE_FW_HALT_F PCIE_FW_HALT_V(1U)
2967
2968 #define PCIE_FW_EVAL_S 24
2969 #define PCIE_FW_EVAL_M 0x7
2970 #define PCIE_FW_EVAL_G(x) (((x) >> PCIE_FW_EVAL_S) & PCIE_FW_EVAL_M)
2971
2972 #define PCIE_FW_MASTER_VLD_S 15
2973 #define PCIE_FW_MASTER_VLD_V(x) ((x) << PCIE_FW_MASTER_VLD_S)
2974 #define PCIE_FW_MASTER_VLD_F PCIE_FW_MASTER_VLD_V(1U)
2975
2976 #define PCIE_FW_MASTER_S 12
2977 #define PCIE_FW_MASTER_M 0x7
2978 #define PCIE_FW_MASTER_V(x) ((x) << PCIE_FW_MASTER_S)
2979 #define PCIE_FW_MASTER_G(x) (((x) >> PCIE_FW_MASTER_S) & PCIE_FW_MASTER_M)
2980
2981 struct fw_hdr {
2982 u8 ver;
2983 u8 chip; /* terminator chip type */
2984 __be16 len512; /* bin length in units of 512-bytes */
2985 __be32 fw_ver; /* firmware version */
2986 __be32 tp_microcode_ver;
2987 u8 intfver_nic;
2988 u8 intfver_vnic;
2989 u8 intfver_ofld;
2990 u8 intfver_ri;
2991 u8 intfver_iscsipdu;
2992 u8 intfver_iscsi;
2993 u8 intfver_fcoepdu;
2994 u8 intfver_fcoe;
2995 __u32 reserved2;
2996 __u32 reserved3;
2997 __u32 reserved4;
2998 __be32 flags;
2999 __be32 reserved6[23];
3000 };
3001
3002 enum fw_hdr_chip {
3003 FW_HDR_CHIP_T4,
3004 FW_HDR_CHIP_T5
3005 };
3006
3007 #define FW_HDR_FW_VER_MAJOR_S 24
3008 #define FW_HDR_FW_VER_MAJOR_M 0xff
3009 #define FW_HDR_FW_VER_MAJOR_G(x) \
3010 (((x) >> FW_HDR_FW_VER_MAJOR_S) & FW_HDR_FW_VER_MAJOR_M)
3011
3012 #define FW_HDR_FW_VER_MINOR_S 16
3013 #define FW_HDR_FW_VER_MINOR_M 0xff
3014 #define FW_HDR_FW_VER_MINOR_G(x) \
3015 (((x) >> FW_HDR_FW_VER_MINOR_S) & FW_HDR_FW_VER_MINOR_M)
3016
3017 #define FW_HDR_FW_VER_MICRO_S 8
3018 #define FW_HDR_FW_VER_MICRO_M 0xff
3019 #define FW_HDR_FW_VER_MICRO_G(x) \
3020 (((x) >> FW_HDR_FW_VER_MICRO_S) & FW_HDR_FW_VER_MICRO_M)
3021
3022 #define FW_HDR_FW_VER_BUILD_S 0
3023 #define FW_HDR_FW_VER_BUILD_M 0xff
3024 #define FW_HDR_FW_VER_BUILD_G(x) \
3025 (((x) >> FW_HDR_FW_VER_BUILD_S) & FW_HDR_FW_VER_BUILD_M)
3026
3027 enum fw_hdr_intfver {
3028 FW_HDR_INTFVER_NIC = 0x00,
3029 FW_HDR_INTFVER_VNIC = 0x00,
3030 FW_HDR_INTFVER_OFLD = 0x00,
3031 FW_HDR_INTFVER_RI = 0x00,
3032 FW_HDR_INTFVER_ISCSIPDU = 0x00,
3033 FW_HDR_INTFVER_ISCSI = 0x00,
3034 FW_HDR_INTFVER_FCOEPDU = 0x00,
3035 FW_HDR_INTFVER_FCOE = 0x00,
3036 };
3037
3038 enum fw_hdr_flags {
3039 FW_HDR_FLAGS_RESET_HALT = 0x00000001,
3040 };
3041
3042 /* length of the formatting string */
3043 #define FW_DEVLOG_FMT_LEN 192
3044
3045 /* maximum number of the formatting string parameters */
3046 #define FW_DEVLOG_FMT_PARAMS_NUM 8
3047
3048 /* priority levels */
3049 enum fw_devlog_level {
3050 FW_DEVLOG_LEVEL_EMERG = 0x0,
3051 FW_DEVLOG_LEVEL_CRIT = 0x1,
3052 FW_DEVLOG_LEVEL_ERR = 0x2,
3053 FW_DEVLOG_LEVEL_NOTICE = 0x3,
3054 FW_DEVLOG_LEVEL_INFO = 0x4,
3055 FW_DEVLOG_LEVEL_DEBUG = 0x5,
3056 FW_DEVLOG_LEVEL_MAX = 0x5,
3057 };
3058
3059 /* facilities that may send a log message */
3060 enum fw_devlog_facility {
3061 FW_DEVLOG_FACILITY_CORE = 0x00,
3062 FW_DEVLOG_FACILITY_CF = 0x01,
3063 FW_DEVLOG_FACILITY_SCHED = 0x02,
3064 FW_DEVLOG_FACILITY_TIMER = 0x04,
3065 FW_DEVLOG_FACILITY_RES = 0x06,
3066 FW_DEVLOG_FACILITY_HW = 0x08,
3067 FW_DEVLOG_FACILITY_FLR = 0x10,
3068 FW_DEVLOG_FACILITY_DMAQ = 0x12,
3069 FW_DEVLOG_FACILITY_PHY = 0x14,
3070 FW_DEVLOG_FACILITY_MAC = 0x16,
3071 FW_DEVLOG_FACILITY_PORT = 0x18,
3072 FW_DEVLOG_FACILITY_VI = 0x1A,
3073 FW_DEVLOG_FACILITY_FILTER = 0x1C,
3074 FW_DEVLOG_FACILITY_ACL = 0x1E,
3075 FW_DEVLOG_FACILITY_TM = 0x20,
3076 FW_DEVLOG_FACILITY_QFC = 0x22,
3077 FW_DEVLOG_FACILITY_DCB = 0x24,
3078 FW_DEVLOG_FACILITY_ETH = 0x26,
3079 FW_DEVLOG_FACILITY_OFLD = 0x28,
3080 FW_DEVLOG_FACILITY_RI = 0x2A,
3081 FW_DEVLOG_FACILITY_ISCSI = 0x2C,
3082 FW_DEVLOG_FACILITY_FCOE = 0x2E,
3083 FW_DEVLOG_FACILITY_FOISCSI = 0x30,
3084 FW_DEVLOG_FACILITY_FOFCOE = 0x32,
3085 FW_DEVLOG_FACILITY_MAX = 0x32,
3086 };
3087
3088 /* log message format */
3089 struct fw_devlog_e {
3090 __be64 timestamp;
3091 __be32 seqno;
3092 __be16 reserved1;
3093 __u8 level;
3094 __u8 facility;
3095 __u8 fmt[FW_DEVLOG_FMT_LEN];
3096 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM];
3097 __be32 reserved3[4];
3098 };
3099
3100 struct fw_devlog_cmd {
3101 __be32 op_to_write;
3102 __be32 retval_len16;
3103 __u8 level;
3104 __u8 r2[7];
3105 __be32 memtype_devlog_memaddr16_devlog;
3106 __be32 memsize_devlog;
3107 __be32 r3[2];
3108 };
3109
3110 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S 28
3111 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M 0xf
3112 #define FW_DEVLOG_CMD_MEMTYPE_DEVLOG_G(x) \
3113 (((x) >> FW_DEVLOG_CMD_MEMTYPE_DEVLOG_S) & \
3114 FW_DEVLOG_CMD_MEMTYPE_DEVLOG_M)
3115
3116 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S 0
3117 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M 0xfffffff
3118 #define FW_DEVLOG_CMD_MEMADDR16_DEVLOG_G(x) \
3119 (((x) >> FW_DEVLOG_CMD_MEMADDR16_DEVLOG_S) & \
3120 FW_DEVLOG_CMD_MEMADDR16_DEVLOG_M)
3121
3122 #endif /* _T4FW_INTERFACE_H_ */
Linux kernel - Deliverables
This page took 0.092718 seconds and 6 git commands to generate.