drivers/net/ethernet/emulex/benet/be.h

   1 /*
   2  * Copyright (C) 2005 - 2011 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Contact Information:
  11  * linux-drivers@emulex.com
  12  *
  13  * Emulex
  14  * 3333 Susan Street
  15  * Costa Mesa, CA 92626
  16  */
  17
  18 #ifndef BE_H
  19 #define BE_H
  20
  21 #include <linux/pci.h>
  22 #include <linux/etherdevice.h>
  23 #include <linux/delay.h>
  24 #include <net/tcp.h>
  25 #include <net/ip.h>
  26 #include <net/ipv6.h>
  27 #include <linux/if_vlan.h>
  28 #include <linux/workqueue.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/firmware.h>
  31 #include <linux/slab.h>
  32 #include <linux/u64_stats_sync.h>
  33
  34 #include "be_hw.h"
  35
  36 #define DRV_VER                 "4.2.220u"
  37 #define DRV_NAME                "be2net"
  38 #define BE_NAME                 "ServerEngines BladeEngine2 10Gbps NIC"
  39 #define BE3_NAME                "ServerEngines BladeEngine3 10Gbps NIC"
  40 #define OC_NAME                 "Emulex OneConnect 10Gbps NIC"
  41 #define OC_NAME_BE              OC_NAME "(be3)"
  42 #define OC_NAME_LANCER          OC_NAME "(Lancer)"
  43 #define OC_NAME_SH              OC_NAME "(Skyhawk)"
  44 #define DRV_DESC                "ServerEngines BladeEngine 10Gbps NIC Driver"
  45
  46 #define BE_VENDOR_ID            0x19a2
  47 #define EMULEX_VENDOR_ID        0x10df
  48 #define BE_DEVICE_ID1           0x211
  49 #define BE_DEVICE_ID2           0x221
  50 #define OC_DEVICE_ID1           0x700   /* Device Id for BE2 cards */
  51 #define OC_DEVICE_ID2           0x710   /* Device Id for BE3 cards */
  52 #define OC_DEVICE_ID3           0xe220  /* Device id for Lancer cards */
  53 #define OC_DEVICE_ID4           0xe228   /* Device id for VF in Lancer */
  54 #define OC_DEVICE_ID5           0x720   /* Device Id for Skyhawk cards */
  55 #define OC_SUBSYS_DEVICE_ID1    0xE602
  56 #define OC_SUBSYS_DEVICE_ID2    0xE642
  57 #define OC_SUBSYS_DEVICE_ID3    0xE612
  58 #define OC_SUBSYS_DEVICE_ID4    0xE652
  59
  60 static inline char *nic_name(struct pci_dev *pdev)
  61 {
  62         switch (pdev->device) {
  63         case OC_DEVICE_ID1:
  64                 return OC_NAME;
  65         case OC_DEVICE_ID2:
  66                 return OC_NAME_BE;
  67         case OC_DEVICE_ID3:
  68         case OC_DEVICE_ID4:
  69                 return OC_NAME_LANCER;
  70         case BE_DEVICE_ID2:
  71                 return BE3_NAME;
  72         case OC_DEVICE_ID5:
  73                 return OC_NAME_SH;
  74         default:
  75                 return BE_NAME;
  76         }
  77 }
  78
  79 /* Number of bytes of an RX frame that are copied to skb->data */
  80 #define BE_HDR_LEN              ((u16) 64)
  81 /* allocate extra space to allow tunneling decapsulation without head reallocation */
  82 #define BE_RX_SKB_ALLOC_SIZE (BE_HDR_LEN + 64)
  83
  84 #define BE_MAX_JUMBO_FRAME_SIZE 9018
  85 #define BE_MIN_MTU              256
  86
  87 #define BE_NUM_VLANS_SUPPORTED  64
  88 #define BE_MAX_EQD              96u
  89 #define BE_MAX_TX_FRAG_COUNT    30
  90
  91 #define EVNT_Q_LEN              1024
  92 #define TX_Q_LEN                2048
  93 #define TX_CQ_LEN               1024
  94 #define RX_Q_LEN                1024    /* Does not support any other value */
  95 #define RX_CQ_LEN               1024
  96 #define MCC_Q_LEN               128     /* total size not to exceed 8 pages */
  97 #define MCC_CQ_LEN              256
  98
  99 #define BE3_MAX_RSS_QS          8
 100 #define BE2_MAX_RSS_QS          4
 101 #define MAX_RSS_QS              BE3_MAX_RSS_QS
 102 #define MAX_RX_QS               (MAX_RSS_QS + 1) /* RSS qs + 1 def Rx */
 103
 104 #define MAX_TX_QS               8
 105 #define MAX_MSIX_VECTORS        MAX_RSS_QS
 106 #define BE_TX_BUDGET            256
 107 #define BE_NAPI_WEIGHT          64
 108 #define MAX_RX_POST             BE_NAPI_WEIGHT /* Frags posted at a time */
 109 #define RX_FRAGS_REFILL_WM      (RX_Q_LEN - MAX_RX_POST)
 110
 111 #define FW_VER_LEN              32
 112
 113 struct be_dma_mem {
 114         void *va;
 115         dma_addr_t dma;
 116         u32 size;
 117 };
 118
 119 struct be_queue_info {
 120         struct be_dma_mem dma_mem;
 121         u16 len;
 122         u16 entry_size; /* Size of an element in the queue */
 123         u16 id;
 124         u16 tail, head;
 125         bool created;
 126         atomic_t used;  /* Number of valid elements in the queue */
 127 };
 128
 129 static inline u32 MODULO(u16 val, u16 limit)
 130 {
 131         BUG_ON(limit & (limit - 1));
 132         return val & (limit - 1);
 133 }
 134
 135 static inline void index_adv(u16 *index, u16 val, u16 limit)
 136 {
 137         *index = MODULO((*index + val), limit);
 138 }
 139
 140 static inline void index_inc(u16 *index, u16 limit)
 141 {
 142         *index = MODULO((*index + 1), limit);
 143 }
 144
 145 static inline void *queue_head_node(struct be_queue_info *q)
 146 {
 147         return q->dma_mem.va + q->head * q->entry_size;
 148 }
 149
 150 static inline void *queue_tail_node(struct be_queue_info *q)
 151 {
 152         return q->dma_mem.va + q->tail * q->entry_size;
 153 }
 154
 155 static inline void *queue_index_node(struct be_queue_info *q, u16 index)
 156 {
 157         return q->dma_mem.va + index * q->entry_size;
 158 }
 159
 160 static inline void queue_head_inc(struct be_queue_info *q)
 161 {
 162         index_inc(&q->head, q->len);
 163 }
 164
 165 static inline void index_dec(u16 *index, u16 limit)
 166 {
 167         *index = MODULO((*index - 1), limit);
 168 }
 169
 170 static inline void queue_tail_inc(struct be_queue_info *q)
 171 {
 172         index_inc(&q->tail, q->len);
 173 }
 174
 175 struct be_eq_obj {
 176         struct be_queue_info q;
 177         char desc[32];
 178
 179         /* Adaptive interrupt coalescing (AIC) info */
 180         bool enable_aic;
 181         u32 min_eqd;            /* in usecs */
 182         u32 max_eqd;            /* in usecs */
 183         u32 eqd;                /* configured val when aic is off */
 184         u32 cur_eqd;            /* in usecs */
 185
 186         u8 idx;                 /* array index */
 187         u16 tx_budget;
 188         struct napi_struct napi;
 189         struct be_adapter *adapter;
 190 } ____cacheline_aligned_in_smp;
 191
 192 struct be_mcc_obj {
 193         struct be_queue_info q;
 194         struct be_queue_info cq;
 195         bool rearm_cq;
 196 };
 197
 198 struct be_tx_stats {
 199         u64 tx_bytes;
 200         u64 tx_pkts;
 201         u64 tx_reqs;
 202         u64 tx_wrbs;
 203         u64 tx_compl;
 204         ulong tx_jiffies;
 205         u32 tx_stops;
 206         struct u64_stats_sync sync;
 207         struct u64_stats_sync sync_compl;
 208 };
 209
 210 struct be_tx_obj {
 211         struct be_queue_info q;
 212         struct be_queue_info cq;
 213         /* Remember the skbs that were transmitted */
 214         struct sk_buff *sent_skb_list[TX_Q_LEN];
 215         struct be_tx_stats stats;
 216 } ____cacheline_aligned_in_smp;
 217
 218 /* Struct to remember the pages posted for rx frags */
 219 struct be_rx_page_info {
 220         struct page *page;
 221         DEFINE_DMA_UNMAP_ADDR(bus);
 222         u16 page_offset;
 223         bool last_page_user;
 224 };
 225
 226 struct be_rx_stats {
 227         u64 rx_bytes;
 228         u64 rx_pkts;
 229         u64 rx_pkts_prev;
 230         ulong rx_jiffies;
 231         u32 rx_drops_no_skbs;   /* skb allocation errors */
 232         u32 rx_drops_no_frags;  /* HW has no fetched frags */
 233         u32 rx_post_fail;       /* page post alloc failures */
 234         u32 rx_compl;
 235         u32 rx_mcast_pkts;
 236         u32 rx_compl_err;       /* completions with err set */
 237         u32 rx_pps;             /* pkts per second */
 238         struct u64_stats_sync sync;
 239 };
 240
 241 struct be_rx_compl_info {
 242         u32 rss_hash;
 243         u16 vlan_tag;
 244         u16 pkt_size;
 245         u16 rxq_idx;
 246         u16 port;
 247         u8 vlanf;
 248         u8 num_rcvd;
 249         u8 err;
 250         u8 ipf;
 251         u8 tcpf;
 252         u8 udpf;
 253         u8 ip_csum;
 254         u8 l4_csum;
 255         u8 ipv6;
 256         u8 vtm;
 257         u8 pkt_type;
 258 };
 259
 260 struct be_rx_obj {
 261         struct be_adapter *adapter;
 262         struct be_queue_info q;
 263         struct be_queue_info cq;
 264         struct be_rx_compl_info rxcp;
 265         struct be_rx_page_info page_info_tbl[RX_Q_LEN];
 266         struct be_rx_stats stats;
 267         u8 rss_id;
 268         bool rx_post_starved;   /* Zero rx frags have been posted to BE */
 269 } ____cacheline_aligned_in_smp;
 270
 271 struct be_drv_stats {
 272         u32 be_on_die_temperature;
 273         u32 eth_red_drops;
 274         u32 rx_drops_no_pbuf;
 275         u32 rx_drops_no_txpb;
 276         u32 rx_drops_no_erx_descr;
 277         u32 rx_drops_no_tpre_descr;
 278         u32 rx_drops_too_many_frags;
 279         u32 forwarded_packets;
 280         u32 rx_drops_mtu;
 281         u32 rx_crc_errors;
 282         u32 rx_alignment_symbol_errors;
 283         u32 rx_pause_frames;
 284         u32 rx_priority_pause_frames;
 285         u32 rx_control_frames;
 286         u32 rx_in_range_errors;
 287         u32 rx_out_range_errors;
 288         u32 rx_frame_too_long;
 289         u32 rx_address_mismatch_drops;
 290         u32 rx_dropped_too_small;
 291         u32 rx_dropped_too_short;
 292         u32 rx_dropped_header_too_small;
 293         u32 rx_dropped_tcp_length;
 294         u32 rx_dropped_runt;
 295         u32 rx_ip_checksum_errs;
 296         u32 rx_tcp_checksum_errs;
 297         u32 rx_udp_checksum_errs;
 298         u32 tx_pauseframes;
 299         u32 tx_priority_pauseframes;
 300         u32 tx_controlframes;
 301         u32 rxpp_fifo_overflow_drop;
 302         u32 rx_input_fifo_overflow_drop;
 303         u32 pmem_fifo_overflow_drop;
 304         u32 jabber_events;
 305 };
 306
 307 struct be_vf_cfg {
 308         unsigned char mac_addr[ETH_ALEN];
 309         int if_handle;
 310         int pmac_id;
 311         u16 def_vid;
 312         u16 vlan_tag;
 313         u32 tx_rate;
 314 };
 315
 316 enum vf_state {
 317         ENABLED = 0,
 318         ASSIGNED = 1
 319 };
 320
 321 #define BE_FLAGS_LINK_STATUS_INIT               1
 322 #define BE_FLAGS_WORKER_SCHEDULED               (1 << 3)
 323 #define BE_UC_PMAC_COUNT                30
 324 #define BE_VF_UC_PMAC_COUNT             2
 325
 326 struct phy_info {
 327         u8 transceiver;
 328         u8 autoneg;
 329         u8 fc_autoneg;
 330         u8 port_type;
 331         u16 phy_type;
 332         u16 interface_type;
 333         u32 misc_params;
 334         u16 auto_speeds_supported;
 335         u16 fixed_speeds_supported;
 336         int link_speed;
 337         int forced_port_speed;
 338         u32 dac_cable_len;
 339         u32 advertising;
 340         u32 supported;
 341 };
 342
 343 struct be_adapter {
 344         struct pci_dev *pdev;
 345         struct net_device *netdev;
 346
 347         u8 __iomem *csr;
 348         u8 __iomem *db;         /* Door Bell */
 349
 350         struct mutex mbox_lock; /* For serializing mbox cmds to BE card */
 351         struct be_dma_mem mbox_mem;
 352         /* Mbox mem is adjusted to align to 16 bytes. The allocated addr
 353          * is stored for freeing purpose */
 354         struct be_dma_mem mbox_mem_alloced;
 355
 356         struct be_mcc_obj mcc_obj;
 357         spinlock_t mcc_lock;    /* For serializing mcc cmds to BE card */
 358         spinlock_t mcc_cq_lock;
 359
 360         u32 num_msix_vec;
 361         u32 num_evt_qs;
 362         struct be_eq_obj eq_obj[MAX_MSIX_VECTORS];
 363         struct msix_entry msix_entries[MAX_MSIX_VECTORS];
 364         bool isr_registered;
 365
 366         /* TX Rings */
 367         u32 num_tx_qs;
 368         struct be_tx_obj tx_obj[MAX_TX_QS];
 369
 370         /* Rx rings */
 371         u32 num_rx_qs;
 372         struct be_rx_obj rx_obj[MAX_RX_QS];
 373         u32 big_page_size;      /* Compounded page size shared by rx wrbs */
 374
 375         u8 eq_next_idx;
 376         struct be_drv_stats drv_stats;
 377
 378         u16 vlans_added;
 379         u16 max_vlans;  /* Number of vlans supported */
 380         u8 vlan_tag[VLAN_N_VID];
 381         u8 vlan_prio_bmap;      /* Available Priority BitMap */
 382         u16 recommended_prio;   /* Recommended Priority */
 383         struct be_dma_mem rx_filter; /* Cmd DMA mem for rx-filter */
 384
 385         struct be_dma_mem stats_cmd;
 386         /* Work queue used to perform periodic tasks like getting statistics */
 387         struct delayed_work work;
 388         u16 work_counter;
 389
 390         u32 flags;
 391         /* Ethtool knobs and info */
 392         char fw_ver[FW_VER_LEN];
 393         int if_handle;          /* Used to configure filtering */
 394         u32 *pmac_id;           /* MAC addr handle used by BE card */
 395         u32 beacon_state;       /* for set_phys_id */
 396
 397         bool eeh_err;
 398         bool ue_detected;
 399         bool fw_timeout;
 400         u32 port_num;
 401         bool promiscuous;
 402         u32 function_mode;
 403         u32 function_caps;
 404         u32 rx_fc;              /* Rx flow control */
 405         u32 tx_fc;              /* Tx flow control */
 406         bool stats_cmd_sent;
 407         u8 generation;          /* BladeEngine ASIC generation */
 408         u32 flash_status;
 409         struct completion flash_compl;
 410
 411         u32 num_vfs;            /* Number of VFs provisioned by PF driver */
 412         u32 dev_num_vfs;        /* Number of VFs supported by HW */
 413         u8 virtfn;
 414         struct be_vf_cfg *vf_cfg;
 415         bool be3_native;
 416         u32 sli_family;
 417         u8 hba_port_num;
 418         u16 pvid;
 419         struct phy_info phy;
 420         u8 wol_cap;
 421         bool wol;
 422         u32 max_pmac_cnt;       /* Max secondary UC MACs programmable */
 423         u32 uc_macs;            /* Count of secondary UC MAC programmed */
 424 };
 425
 426 #define be_physfn(adapter)              (!adapter->virtfn)
 427 #define sriov_enabled(adapter)          (adapter->num_vfs > 0)
 428 #define sriov_want(adapter)             (adapter->dev_num_vfs && num_vfs && \
 429                                          be_physfn(adapter))
 430 #define for_all_vfs(adapter, vf_cfg, i)                                 \
 431         for (i = 0, vf_cfg = &adapter->vf_cfg[i]; i < adapter->num_vfs; \
 432                 i++, vf_cfg++)
 433
 434 /* BladeEngine Generation numbers */
 435 #define BE_GEN2 2
 436 #define BE_GEN3 3
 437
 438 #define ON                              1
 439 #define OFF                             0
 440 #define lancer_chip(adapter)    ((adapter->pdev->device == OC_DEVICE_ID3) || \
 441                                  (adapter->pdev->device == OC_DEVICE_ID4))
 442
 443 extern const struct ethtool_ops be_ethtool_ops;
 444
 445 #define msix_enabled(adapter)           (adapter->num_msix_vec > 0)
 446 #define num_irqs(adapter)               (msix_enabled(adapter) ?        \
 447                                                 adapter->num_msix_vec : 1)
 448 #define tx_stats(txo)                   (&(txo)->stats)
 449 #define rx_stats(rxo)                   (&(rxo)->stats)
 450
 451 /* The default RXQ is the last RXQ */
 452 #define default_rxo(adpt)               (&adpt->rx_obj[adpt->num_rx_qs - 1])
 453
 454 #define for_all_rx_queues(adapter, rxo, i)                              \
 455         for (i = 0, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;  \
 456                 i++, rxo++)
 457
 458 /* Skip the default non-rss queue (last one)*/
 459 #define for_all_rss_queues(adapter, rxo, i)                             \
 460         for (i = 0, rxo = &adapter->rx_obj[i]; i < (adapter->num_rx_qs - 1);\
 461                 i++, rxo++)
 462
 463 #define for_all_tx_queues(adapter, txo, i)                              \
 464         for (i = 0, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;  \
 465                 i++, txo++)
 466
 467 #define for_all_evt_queues(adapter, eqo, i)                             \
 468         for (i = 0, eqo = &adapter->eq_obj[i]; i < adapter->num_evt_qs; \
 469                 i++, eqo++)
 470
 471 #define is_mcc_eqo(eqo)                 (eqo->idx == 0)
 472 #define mcc_eqo(adapter)                (&adapter->eq_obj[0])
 473
 474 #define PAGE_SHIFT_4K           12
 475 #define PAGE_SIZE_4K            (1 << PAGE_SHIFT_4K)
 476
 477 /* Returns number of pages spanned by the data starting at the given addr */
 478 #define PAGES_4K_SPANNED(_address, size)                                \
 479                 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) +     \
 480                         (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
 481
 482 /* Returns bit offset within a DWORD of a bitfield */
 483 #define AMAP_BIT_OFFSET(_struct, field)                                 \
 484                 (((size_t)&(((_struct *)0)->field))%32)
 485
 486 /* Returns the bit mask of the field that is NOT shifted into location. */
 487 static inline u32 amap_mask(u32 bitsize)
 488 {
 489         return (bitsize == 32 ? 0xFFFFFFFF : (1 << bitsize) - 1);
 490 }
 491
 492 static inline void
 493 amap_set(void *ptr, u32 dw_offset, u32 mask, u32 offset, u32 value)
 494 {
 495         u32 *dw = (u32 *) ptr + dw_offset;
 496         *dw &= ~(mask << offset);
 497         *dw |= (mask & value) << offset;
 498 }
 499
 500 #define AMAP_SET_BITS(_struct, field, ptr, val)                         \
 501                 amap_set(ptr,                                           \
 502                         offsetof(_struct, field)/32,                    \
 503                         amap_mask(sizeof(((_struct *)0)->field)),       \
 504                         AMAP_BIT_OFFSET(_struct, field),                \
 505                         val)
 506
 507 static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
 508 {
 509         u32 *dw = (u32 *) ptr;
 510         return mask & (*(dw + dw_offset) >> offset);
 511 }
 512
 513 #define AMAP_GET_BITS(_struct, field, ptr)                              \
 514                 amap_get(ptr,                                           \
 515                         offsetof(_struct, field)/32,                    \
 516                         amap_mask(sizeof(((_struct *)0)->field)),       \
 517                         AMAP_BIT_OFFSET(_struct, field))
 518
 519 #define be_dws_cpu_to_le(wrb, len)      swap_dws(wrb, len)
 520 #define be_dws_le_to_cpu(wrb, len)      swap_dws(wrb, len)
 521 static inline void swap_dws(void *wrb, int len)
 522 {
 523 #ifdef __BIG_ENDIAN
 524         u32 *dw = wrb;
 525         BUG_ON(len % 4);
 526         do {
 527                 *dw = cpu_to_le32(*dw);
 528                 dw++;
 529                 len -= 4;
 530         } while (len);
 531 #endif                          /* __BIG_ENDIAN */
 532 }
 533
 534 static inline u8 is_tcp_pkt(struct sk_buff *skb)
 535 {
 536         u8 val = 0;
 537
 538         if (ip_hdr(skb)->version == 4)
 539                 val = (ip_hdr(skb)->protocol == IPPROTO_TCP);
 540         else if (ip_hdr(skb)->version == 6)
 541                 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_TCP);
 542
 543         return val;
 544 }
 545
 546 static inline u8 is_udp_pkt(struct sk_buff *skb)
 547 {
 548         u8 val = 0;
 549
 550         if (ip_hdr(skb)->version == 4)
 551                 val = (ip_hdr(skb)->protocol == IPPROTO_UDP);
 552         else if (ip_hdr(skb)->version == 6)
 553                 val = (ipv6_hdr(skb)->nexthdr == NEXTHDR_UDP);
 554
 555         return val;
 556 }
 557
 558 static inline void be_vf_eth_addr_generate(struct be_adapter *adapter, u8 *mac)
 559 {
 560         u32 addr;
 561
 562         addr = jhash(adapter->netdev->dev_addr, ETH_ALEN, 0);
 563
 564         mac[5] = (u8)(addr & 0xFF);
 565         mac[4] = (u8)((addr >> 8) & 0xFF);
 566         mac[3] = (u8)((addr >> 16) & 0xFF);
 567         /* Use the OUI from the current MAC address */
 568         memcpy(mac, adapter->netdev->dev_addr, 3);
 569 }
 570
 571 static inline bool be_multi_rxq(const struct be_adapter *adapter)
 572 {
 573         return adapter->num_rx_qs > 1;
 574 }
 575
 576 static inline bool be_error(struct be_adapter *adapter)
 577 {
 578         return adapter->eeh_err || adapter->ue_detected || adapter->fw_timeout;
 579 }
 580
 581 static inline bool be_is_wol_excluded(struct be_adapter *adapter)
 582 {
 583         struct pci_dev *pdev = adapter->pdev;
 584
 585         if (!be_physfn(adapter))
 586                 return true;
 587
 588         switch (pdev->subsystem_device) {
 589         case OC_SUBSYS_DEVICE_ID1:
 590         case OC_SUBSYS_DEVICE_ID2:
 591         case OC_SUBSYS_DEVICE_ID3:
 592         case OC_SUBSYS_DEVICE_ID4:
 593                 return true;
 594         default:
 595                 return false;
 596         }
 597 }
 598
 599 extern void be_cq_notify(struct be_adapter *adapter, u16 qid, bool arm,
 600                 u16 num_popped);
 601 extern void be_link_status_update(struct be_adapter *adapter, u8 link_status);
 602 extern void be_parse_stats(struct be_adapter *adapter);
 603 extern int be_load_fw(struct be_adapter *adapter, u8 *func);
 604 extern bool be_is_wol_supported(struct be_adapter *adapter);
 605 extern bool be_pause_supported(struct be_adapter *adapter);
 606 #endif                          /* BE_H */